1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "12"
34 /* Information for net */
35 #define NET_VERSION "11"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RCR1 0xc012
47 #define PLA_RMS 0xc016
48 #define PLA_RXFIFO_CTRL0 0xc0a0
49 #define PLA_RXFIFO_FULL 0xc0a2
50 #define PLA_RXFIFO_CTRL1 0xc0a4
51 #define PLA_RX_FIFO_FULL 0xc0a6
52 #define PLA_RXFIFO_CTRL2 0xc0a8
53 #define PLA_RX_FIFO_EMPTY 0xc0aa
54 #define PLA_DMY_REG0 0xc0b0
55 #define PLA_FMC 0xc0b4
56 #define PLA_CFG_WOL 0xc0b6
57 #define PLA_TEREDO_CFG 0xc0bc
58 #define PLA_TEREDO_WAKE_BASE 0xc0c4
59 #define PLA_MAR 0xcd00
60 #define PLA_BACKUP 0xd000
61 #define PLA_BDC_CR 0xd1a0
62 #define PLA_TEREDO_TIMER 0xd2cc
63 #define PLA_REALWOW_TIMER 0xd2e8
64 #define PLA_UPHY_TIMER 0xd388
65 #define PLA_SUSPEND_FLAG 0xd38a
66 #define PLA_INDICATE_FALG 0xd38c
67 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
68 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
69 #define PLA_EXTRA_STATUS 0xd398
70 #define PLA_GPHY_CTRL 0xd3ae
71 #define PLA_POL_GPIO_CTRL 0xdc6a
72 #define PLA_EFUSE_DATA 0xdd00
73 #define PLA_EFUSE_CMD 0xdd02
74 #define PLA_LEDSEL 0xdd90
75 #define PLA_LED_FEATURE 0xdd92
76 #define PLA_PHYAR 0xde00
77 #define PLA_BOOT_CTRL 0xe004
78 #define PLA_LWAKE_CTRL_REG 0xe007
79 #define PLA_GPHY_INTR_IMR 0xe022
80 #define PLA_EEE_CR 0xe040
81 #define PLA_EEE_TXTWSYS 0xe04c
82 #define PLA_EEE_TXTWSYS_2P5G 0xe058
83 #define PLA_EEEP_CR 0xe080
84 #define PLA_MAC_PWR_CTRL 0xe0c0
85 #define PLA_MAC_PWR_CTRL2 0xe0ca
86 #define PLA_MAC_PWR_CTRL3 0xe0cc
87 #define PLA_MAC_PWR_CTRL4 0xe0ce
88 #define PLA_WDT6_CTRL 0xe428
89 #define PLA_TCR0 0xe610
90 #define PLA_TCR1 0xe612
91 #define PLA_MTPS 0xe615
92 #define PLA_TXFIFO_CTRL 0xe618
93 #define PLA_TXFIFO_FULL 0xe61a
94 #define PLA_RSTTALLY 0xe800
96 #define PLA_CRWECR 0xe81c
97 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
98 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
99 #define PLA_CONFIG5 0xe822
100 #define PLA_PHY_PWR 0xe84c
101 #define PLA_OOB_CTRL 0xe84f
102 #define PLA_CPCR 0xe854
103 #define PLA_MISC_0 0xe858
104 #define PLA_MISC_1 0xe85a
105 #define PLA_OCP_GPHY_BASE 0xe86c
106 #define PLA_TALLYCNT 0xe890
107 #define PLA_SFF_STS_7 0xe8de
108 #define PLA_PHYSTATUS 0xe908
109 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
110 #define PLA_USB_CFG 0xe952
111 #define PLA_BP_BA 0xfc26
112 #define PLA_BP_0 0xfc28
113 #define PLA_BP_1 0xfc2a
114 #define PLA_BP_2 0xfc2c
115 #define PLA_BP_3 0xfc2e
116 #define PLA_BP_4 0xfc30
117 #define PLA_BP_5 0xfc32
118 #define PLA_BP_6 0xfc34
119 #define PLA_BP_7 0xfc36
120 #define PLA_BP_EN 0xfc38
122 #define USB_USB2PHY 0xb41e
123 #define USB_SSPHYLINK1 0xb426
124 #define USB_SSPHYLINK2 0xb428
125 #define USB_L1_CTRL 0xb45e
126 #define USB_U2P3_CTRL 0xb460
127 #define USB_CSR_DUMMY1 0xb464
128 #define USB_CSR_DUMMY2 0xb466
129 #define USB_DEV_STAT 0xb808
130 #define USB_CONNECT_TIMER 0xcbf8
131 #define USB_MSC_TIMER 0xcbfc
132 #define USB_BURST_SIZE 0xcfc0
133 #define USB_FW_FIX_EN0 0xcfca
134 #define USB_FW_FIX_EN1 0xcfcc
135 #define USB_LPM_CONFIG 0xcfd8
136 #define USB_ECM_OPTION 0xcfee
137 #define USB_CSTMR 0xcfef /* RTL8153A */
138 #define USB_MISC_2 0xcfff
139 #define USB_ECM_OP 0xd26b
140 #define USB_GPHY_CTRL 0xd284
141 #define USB_SPEED_OPTION 0xd32a
142 #define USB_FW_CTRL 0xd334 /* RTL8153B */
143 #define USB_FC_TIMER 0xd340
144 #define USB_USB_CTRL 0xd406
145 #define USB_PHY_CTRL 0xd408
146 #define USB_TX_AGG 0xd40a
147 #define USB_RX_BUF_TH 0xd40c
148 #define USB_USB_TIMER 0xd428
149 #define USB_RX_EARLY_TIMEOUT 0xd42c
150 #define USB_RX_EARLY_SIZE 0xd42e
151 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
152 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
153 #define USB_TX_DMA 0xd434
154 #define USB_UPT_RXDMA_OWN 0xd437
155 #define USB_UPHY3_MDCMDIO 0xd480
156 #define USB_TOLERANCE 0xd490
157 #define USB_LPM_CTRL 0xd41a
158 #define USB_BMU_RESET 0xd4b0
159 #define USB_BMU_CONFIG 0xd4b4
160 #define USB_U1U2_TIMER 0xd4da
161 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
162 #define USB_RX_AGGR_NUM 0xd4ee
163 #define USB_UPS_CTRL 0xd800
164 #define USB_POWER_CUT 0xd80a
165 #define USB_MISC_0 0xd81a
166 #define USB_MISC_1 0xd81f
167 #define USB_AFE_CTRL2 0xd824
168 #define USB_UPHY_XTAL 0xd826
169 #define USB_UPS_CFG 0xd842
170 #define USB_UPS_FLAGS 0xd848
171 #define USB_WDT1_CTRL 0xe404
172 #define USB_WDT11_CTRL 0xe43c
173 #define USB_BP_BA PLA_BP_BA
174 #define USB_BP_0 PLA_BP_0
175 #define USB_BP_1 PLA_BP_1
176 #define USB_BP_2 PLA_BP_2
177 #define USB_BP_3 PLA_BP_3
178 #define USB_BP_4 PLA_BP_4
179 #define USB_BP_5 PLA_BP_5
180 #define USB_BP_6 PLA_BP_6
181 #define USB_BP_7 PLA_BP_7
182 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
183 #define USB_BP_8 0xfc38 /* RTL8153B */
184 #define USB_BP_9 0xfc3a
185 #define USB_BP_10 0xfc3c
186 #define USB_BP_11 0xfc3e
187 #define USB_BP_12 0xfc40
188 #define USB_BP_13 0xfc42
189 #define USB_BP_14 0xfc44
190 #define USB_BP_15 0xfc46
191 #define USB_BP2_EN 0xfc48
194 #define OCP_ALDPS_CONFIG 0x2010
195 #define OCP_EEE_CONFIG1 0x2080
196 #define OCP_EEE_CONFIG2 0x2092
197 #define OCP_EEE_CONFIG3 0x2094
198 #define OCP_BASE_MII 0xa400
199 #define OCP_EEE_AR 0xa41a
200 #define OCP_EEE_DATA 0xa41c
201 #define OCP_PHY_STATUS 0xa420
202 #define OCP_NCTL_CFG 0xa42c
203 #define OCP_POWER_CFG 0xa430
204 #define OCP_EEE_CFG 0xa432
205 #define OCP_SRAM_ADDR 0xa436
206 #define OCP_SRAM_DATA 0xa438
207 #define OCP_DOWN_SPEED 0xa442
208 #define OCP_EEE_ABLE 0xa5c4
209 #define OCP_EEE_ADV 0xa5d0
210 #define OCP_EEE_LPABLE 0xa5d2
211 #define OCP_10GBT_CTRL 0xa5d4
212 #define OCP_10GBT_STAT 0xa5d6
213 #define OCP_EEE_ADV2 0xa6d4
214 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
215 #define OCP_PHY_PATCH_STAT 0xb800
216 #define OCP_PHY_PATCH_CMD 0xb820
217 #define OCP_PHY_LOCK 0xb82e
218 #define OCP_ADC_IOFFSET 0xbcfc
219 #define OCP_ADC_CFG 0xbc06
220 #define OCP_SYSCLK_CFG 0xc416
223 #define SRAM_GREEN_CFG 0x8011
224 #define SRAM_LPF_CFG 0x8012
225 #define SRAM_GPHY_FW_VER 0x801e
226 #define SRAM_10M_AMP1 0x8080
227 #define SRAM_10M_AMP2 0x8082
228 #define SRAM_IMPEDANCE 0x8084
229 #define SRAM_PHY_LOCK 0xb82e
232 #define RCR_AAP 0x00000001
233 #define RCR_APM 0x00000002
234 #define RCR_AM 0x00000004
235 #define RCR_AB 0x00000008
236 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
237 #define SLOT_EN BIT(11)
240 #define OUTER_VLAN BIT(7)
241 #define INNER_VLAN BIT(6)
243 /* PLA_RXFIFO_CTRL0 */
244 #define RXFIFO_THR1_NORMAL 0x00080002
245 #define RXFIFO_THR1_OOB 0x01800003
247 /* PLA_RXFIFO_FULL */
248 #define RXFIFO_FULL_MASK 0xfff
250 /* PLA_RXFIFO_CTRL1 */
251 #define RXFIFO_THR2_FULL 0x00000060
252 #define RXFIFO_THR2_HIGH 0x00000038
253 #define RXFIFO_THR2_OOB 0x0000004a
254 #define RXFIFO_THR2_NORMAL 0x00a0
256 /* PLA_RXFIFO_CTRL2 */
257 #define RXFIFO_THR3_FULL 0x00000078
258 #define RXFIFO_THR3_HIGH 0x00000048
259 #define RXFIFO_THR3_OOB 0x0000005a
260 #define RXFIFO_THR3_NORMAL 0x0110
262 /* PLA_TXFIFO_CTRL */
263 #define TXFIFO_THR_NORMAL 0x00400008
264 #define TXFIFO_THR_NORMAL2 0x01000008
267 #define ECM_ALDPS 0x0002
270 #define FMC_FCR_MCU_EN 0x0001
273 #define EEEP_CR_EEEP_TX 0x0002
276 #define WDT6_SET_MODE 0x0010
279 #define TCR0_TX_EMPTY 0x0800
280 #define TCR0_AUTO_FIFO 0x0080
283 #define VERSION_MASK 0x7cf0
284 #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
285 #define IFG_144NS BIT(9)
286 #define IFG_96NS (BIT(9) | BIT(8))
289 #define MTPS_JUMBO (12 * 1024 / 64)
290 #define MTPS_DEFAULT (6 * 1024 / 64)
293 #define TALLY_RESET 0x0001
301 #define CRWECR_NORAML 0x00
302 #define CRWECR_CONFIG 0xc0
305 #define NOW_IS_OOB 0x80
306 #define TXFIFO_EMPTY 0x20
307 #define RXFIFO_EMPTY 0x10
308 #define LINK_LIST_READY 0x02
309 #define DIS_MCU_CLROOB 0x01
310 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
313 #define RXDY_GATED_EN 0x0008
316 #define RE_INIT_LL 0x8000
317 #define MCU_BORW_EN 0x4000
320 #define FLOW_CTRL_EN BIT(0)
321 #define CPCR_RX_VLAN 0x0040
324 #define MAGIC_EN 0x0001
327 #define TEREDO_SEL 0x8000
328 #define TEREDO_WAKE_MASK 0x7f00
329 #define TEREDO_RS_EVENT_MASK 0x00fe
330 #define OOB_TEREDO_EN 0x0001
333 #define ALDPS_PROXY_MODE 0x0001
336 #define EFUSE_READ_CMD BIT(15)
337 #define EFUSE_DATA_BIT16 BIT(7)
340 #define LINK_ON_WAKE_EN 0x0010
341 #define LINK_OFF_WAKE_EN 0x0008
344 #define LANWAKE_CLR_EN BIT(0)
347 #define EN_XG_LIP BIT(1)
348 #define EN_G_LIP BIT(2)
351 #define BWF_EN 0x0040
352 #define MWF_EN 0x0020
353 #define UWF_EN 0x0010
354 #define LAN_WAKE_EN 0x0002
356 /* PLA_LED_FEATURE */
357 #define LED_MODE_MASK 0x0700
360 #define TX_10M_IDLE_EN 0x0080
361 #define PFM_PWM_SWITCH 0x0040
362 #define TEST_IO_OFF BIT(4)
364 /* PLA_MAC_PWR_CTRL */
365 #define D3_CLK_GATED_EN 0x00004000
366 #define MCU_CLK_RATIO 0x07010f07
367 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
368 #define ALDPS_SPDWN_RATIO 0x0f87
370 /* PLA_MAC_PWR_CTRL2 */
371 #define EEE_SPDWN_RATIO 0x8007
372 #define MAC_CLK_SPDWN_EN BIT(15)
373 #define EEE_SPDWN_RATIO_MASK 0xff
375 /* PLA_MAC_PWR_CTRL3 */
376 #define PLA_MCU_SPDWN_EN BIT(14)
377 #define PKT_AVAIL_SPDWN_EN 0x0100
378 #define SUSPEND_SPDWN_EN 0x0004
379 #define U1U2_SPDWN_EN 0x0002
380 #define L1_SPDWN_EN 0x0001
382 /* PLA_MAC_PWR_CTRL4 */
383 #define PWRSAVE_SPDWN_EN 0x1000
384 #define RXDV_SPDWN_EN 0x0800
385 #define TX10MIDLE_EN 0x0100
386 #define IDLE_SPDWN_EN BIT(6)
387 #define TP100_SPDWN_EN 0x0020
388 #define TP500_SPDWN_EN 0x0010
389 #define TP1000_SPDWN_EN 0x0008
390 #define EEE_SPDWN_EN 0x0001
392 /* PLA_GPHY_INTR_IMR */
393 #define GPHY_STS_MSK 0x0001
394 #define SPEED_DOWN_MSK 0x0002
395 #define SPDWN_RXDV_MSK 0x0004
396 #define SPDWN_LINKCHG_MSK 0x0008
399 #define PHYAR_FLAG 0x80000000
402 #define EEE_RX_EN 0x0001
403 #define EEE_TX_EN 0x0002
406 #define AUTOLOAD_DONE 0x0002
408 /* PLA_LWAKE_CTRL_REG */
409 #define LANWAKE_PIN BIT(7)
411 /* PLA_SUSPEND_FLAG */
412 #define LINK_CHG_EVENT BIT(0)
414 /* PLA_INDICATE_FALG */
415 #define UPCOMING_RUNTIME_D3 BIT(0)
417 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
418 #define DEBUG_OE BIT(0)
419 #define DEBUG_LTSSM 0x0082
421 /* PLA_EXTRA_STATUS */
422 #define CUR_LINK_OK BIT(15)
423 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
424 #define LINK_CHANGE_FLAG BIT(8)
425 #define POLL_LINK_CHG BIT(0)
428 #define GPHY_FLASH BIT(1)
430 /* PLA_POL_GPIO_CTRL */
431 #define DACK_DET_EN BIT(15)
432 #define POL_GPHY_PATCH BIT(4)
435 #define USB2PHY_SUSPEND 0x0001
436 #define USB2PHY_L1 0x0002
439 #define DELAY_PHY_PWR_CHG BIT(1)
442 #define pwd_dn_scale_mask 0x3ffe
443 #define pwd_dn_scale(x) ((x) << 1)
446 #define DYNAMIC_BURST 0x0001
449 #define EP4_FULL_FC 0x0001
452 #define STAT_SPEED_MASK 0x0006
453 #define STAT_SPEED_HIGH 0x0000
454 #define STAT_SPEED_FULL 0x0002
457 #define FW_FIX_SUSPEND BIT(14)
460 #define FW_IP_RESET_EN BIT(9)
463 #define LPM_U1U2_EN BIT(0)
466 #define TX_AGG_MAX_THRESHOLD 0x03
469 #define RX_THR_SUPPER 0x0c350180
470 #define RX_THR_HIGH 0x7a120180
471 #define RX_THR_SLOW 0xffff0180
472 #define RX_THR_B 0x00010001
475 #define TEST_MODE_DISABLE 0x00000001
476 #define TX_SIZE_ADJUST1 0x00000100
479 #define BMU_RESET_EP_IN 0x01
480 #define BMU_RESET_EP_OUT 0x02
483 #define ACT_ODMA BIT(1)
485 /* USB_UPT_RXDMA_OWN */
486 #define OWN_UPDATE BIT(0)
487 #define OWN_CLEAR BIT(1)
490 #define FC_PATCH_TASK BIT(1)
492 /* USB_RX_AGGR_NUM */
493 #define RX_AGGR_NUM_MASK 0x1ff
496 #define POWER_CUT 0x0100
498 /* USB_PM_CTRL_STATUS */
499 #define RESUME_INDICATE 0x0001
502 #define BYPASS_MAC_RESET BIT(5)
505 #define FORCE_SUPER BIT(0)
508 #define UPS_FORCE_PWR_DOWN BIT(0)
511 #define EN_ALL_SPEED BIT(0)
514 #define GPHY_PATCH_DONE BIT(2)
515 #define BYPASS_FLASH BIT(5)
516 #define BACKUP_RESTRORE BIT(6)
518 /* USB_SPEED_OPTION */
519 #define RG_PWRDN_EN BIT(8)
520 #define ALL_SPEED_OFF BIT(9)
523 #define FLOW_CTRL_PATCH_OPT BIT(1)
524 #define AUTO_SPEEDUP BIT(3)
525 #define FLOW_CTRL_PATCH_2 BIT(8)
528 #define CTRL_TIMER_EN BIT(15)
531 #define CDC_ECM_EN BIT(3)
532 #define RX_AGG_DISABLE 0x0010
533 #define RX_ZERO_EN 0x0080
536 #define U2P3_ENABLE 0x0001
537 #define RX_DETECT8 BIT(3)
540 #define PWR_EN 0x0001
541 #define PHASE2_EN 0x0008
542 #define UPS_EN BIT(4)
543 #define USP_PREWAKE BIT(5)
546 #define PCUT_STATUS 0x0001
548 /* USB_RX_EARLY_TIMEOUT */
549 #define COALESCE_SUPER 85000U
550 #define COALESCE_HIGH 250000U
551 #define COALESCE_SLOW 524280U
554 #define WTD1_EN BIT(0)
557 #define TIMER11_EN 0x0001
560 /* bit 4 ~ 5: fifo empty boundary */
561 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
562 /* bit 2 ~ 3: LMP timer */
563 #define LPM_TIMER_MASK 0x0c
564 #define LPM_TIMER_500MS 0x04 /* 500 ms */
565 #define LPM_TIMER_500US 0x0c /* 500 us */
566 #define ROK_EXIT_LPM 0x02
569 #define SEN_VAL_MASK 0xf800
570 #define SEN_VAL_NORMAL 0xa000
571 #define SEL_RXIDLE 0x0100
574 #define OOBS_POLLING BIT(8)
577 #define SAW_CNT_1MS_MASK 0x0fff
578 #define MID_REVERSE BIT(5) /* RTL8156A */
581 #define UPS_FLAGS_R_TUNE BIT(0)
582 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
583 #define UPS_FLAGS_250M_CKDIV BIT(2)
584 #define UPS_FLAGS_EN_ALDPS BIT(3)
585 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
586 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
587 #define ups_flags_speed(x) ((x) << 16)
588 #define UPS_FLAGS_EN_EEE BIT(20)
589 #define UPS_FLAGS_EN_500M_EEE BIT(21)
590 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
591 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
592 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
593 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
594 #define UPS_FLAGS_EN_GREEN BIT(26)
595 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
611 /* OCP_ALDPS_CONFIG */
612 #define ENPWRSAVE 0x8000
613 #define ENPDNPS 0x0200
614 #define LINKENA 0x0100
615 #define DIS_SDSAVE 0x0010
618 #define PHY_STAT_MASK 0x0007
619 #define PHY_STAT_EXT_INIT 2
620 #define PHY_STAT_LAN_ON 3
621 #define PHY_STAT_PWRDN 5
624 #define PGA_RETURN_EN BIT(1)
627 #define EEE_CLKDIV_EN 0x8000
628 #define EN_ALDPS 0x0004
629 #define EN_10M_PLLOFF 0x0001
631 /* OCP_EEE_CONFIG1 */
632 #define RG_TXLPI_MSK_HFDUP 0x8000
633 #define RG_MATCLR_EN 0x4000
634 #define EEE_10_CAP 0x2000
635 #define EEE_NWAY_EN 0x1000
636 #define TX_QUIET_EN 0x0200
637 #define RX_QUIET_EN 0x0100
638 #define sd_rise_time_mask 0x0070
639 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
640 #define RG_RXLPI_MSK_HFDUP 0x0008
641 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
643 /* OCP_EEE_CONFIG2 */
644 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
645 #define RG_DACQUIET_EN 0x0400
646 #define RG_LDVQUIET_EN 0x0200
647 #define RG_CKRSEL 0x0020
648 #define RG_EEEPRG_EN 0x0010
650 /* OCP_EEE_CONFIG3 */
651 #define fast_snr_mask 0xff80
652 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
653 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
654 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
657 /* bit[15:14] function */
658 #define FUN_ADDR 0x0000
659 #define FUN_DATA 0x4000
660 /* bit[4:0] device addr */
663 #define CTAP_SHORT_EN 0x0040
664 #define EEE10_EN 0x0010
667 #define EN_EEE_CMODE BIT(14)
668 #define EN_EEE_1000 BIT(13)
669 #define EN_EEE_100 BIT(12)
670 #define EN_10M_CLKDIV BIT(11)
671 #define EN_10M_BGOFF 0x0080
674 #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
677 #define TXDIS_STATE 0x01
678 #define ABD_STATE 0x02
680 /* OCP_PHY_PATCH_STAT */
681 #define PATCH_READY BIT(6)
683 /* OCP_PHY_PATCH_CMD */
684 #define PATCH_REQUEST BIT(4)
687 #define PATCH_LOCK BIT(0)
690 #define CKADSEL_L 0x0100
691 #define ADC_EN 0x0080
692 #define EN_EMI_L 0x0040
695 #define sysclk_div_expo(x) (min(x, 5) << 8)
696 #define clk_div_expo(x) (min(x, 5) << 4)
699 #define GREEN_ETH_EN BIT(15)
700 #define R_TUNE_EN BIT(11)
703 #define LPF_AUTO_TUNE 0x8000
706 #define GDAC_IB_UPALL 0x0008
709 #define AMP_DN 0x0200
712 #define RX_DRIVING_MASK 0x6000
715 #define PHY_PATCH_LOCK 0x0001
718 #define AD_MASK 0xfee0
719 #define BND_MASK 0x0004
720 #define BD_MASK 0x0001
722 #define PASS_THRU_MASK 0x1
724 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
726 enum rtl_register_content
{
739 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
740 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
742 #define RTL8152_MAX_TX 4
743 #define RTL8152_MAX_RX 10
748 #define RTL8152_RX_MAX_PENDING 4096
749 #define RTL8152_RXFG_HEADSZ 256
751 #define INTR_LINK 0x0004
753 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
754 #define RTL8153_RMS RTL8153_MAX_PACKET
755 #define RTL8152_TX_TIMEOUT (5 * HZ)
756 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
757 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
758 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
773 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
774 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
776 struct tally_counter
{
783 __le32 tx_one_collision
;
784 __le32 tx_multi_collision
;
794 #define RX_LEN_MASK 0x7fff
797 #define RD_UDP_CS BIT(23)
798 #define RD_TCP_CS BIT(22)
799 #define RD_IPV6_CS BIT(20)
800 #define RD_IPV4_CS BIT(19)
803 #define IPF BIT(23) /* IP checksum fail */
804 #define UDPF BIT(22) /* UDP checksum fail */
805 #define TCPF BIT(21) /* TCP checksum fail */
806 #define RX_VLAN_TAG BIT(16)
815 #define TX_FS BIT(31) /* First segment of a packet */
816 #define TX_LS BIT(30) /* Final segment of a packet */
817 #define GTSENDV4 BIT(28)
818 #define GTSENDV6 BIT(27)
819 #define GTTCPHO_SHIFT 18
820 #define GTTCPHO_MAX 0x7fU
821 #define TX_LEN_MAX 0x3ffffU
824 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
825 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
826 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
827 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
829 #define MSS_MAX 0x7ffU
830 #define TCPHO_SHIFT 17
831 #define TCPHO_MAX 0x7ffU
832 #define TX_VLAN_TAG BIT(16)
838 struct list_head list
, info_list
;
840 struct r8152
*context
;
846 struct list_head list
;
848 struct r8152
*context
;
857 struct usb_device
*udev
;
858 struct napi_struct napi
;
859 struct usb_interface
*intf
;
860 struct net_device
*netdev
;
861 struct urb
*intr_urb
;
862 struct tx_agg tx_info
[RTL8152_MAX_TX
];
863 struct list_head rx_info
, rx_used
;
864 struct list_head rx_done
, tx_free
;
865 struct sk_buff_head tx_queue
, rx_queue
;
866 spinlock_t rx_lock
, tx_lock
;
867 struct delayed_work schedule
, hw_phy_work
;
868 struct mii_if_info mii
;
869 struct mutex control
; /* use for hw setting */
870 #ifdef CONFIG_PM_SLEEP
871 struct notifier_block pm_notifier
;
873 struct tasklet_struct tx_tl
;
876 void (*init
)(struct r8152
*tp
);
877 int (*enable
)(struct r8152
*tp
);
878 void (*disable
)(struct r8152
*tp
);
879 void (*up
)(struct r8152
*tp
);
880 void (*down
)(struct r8152
*tp
);
881 void (*unload
)(struct r8152
*tp
);
882 int (*eee_get
)(struct r8152
*tp
, struct ethtool_eee
*eee
);
883 int (*eee_set
)(struct r8152
*tp
, struct ethtool_eee
*eee
);
884 bool (*in_nway
)(struct r8152
*tp
);
885 void (*hw_phy_cfg
)(struct r8152
*tp
);
886 void (*autosuspend_en
)(struct r8152
*tp
, bool enable
);
887 void (*change_mtu
)(struct r8152
*tp
);
900 u32 eee_plloff_100
:1;
901 u32 eee_plloff_giga
:1;
905 u32 ctap_short_off
:1;
908 #define RTL_VER_SIZE 32
912 const struct firmware
*fw
;
914 char version
[RTL_VER_SIZE
];
915 int (*pre_fw
)(struct r8152
*tp
);
916 int (*post_fw
)(struct r8152
*tp
);
933 u32 fc_pause_on
, fc_pause_off
;
935 unsigned int pipe_in
, pipe_out
, pipe_intr
, pipe_ctrl_in
, pipe_ctrl_out
;
937 u32 support_2500full
:1;
938 u32 lenovo_macpassthru
:1;
939 u32 dell_tb_rx_agg_bug
:1;
950 * struct fw_block - block type and total length
951 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
952 * RTL_FW_USB and so on.
953 * @length: total length of the current block.
961 * struct fw_header - header of the firmware file
962 * @checksum: checksum of sha256 which is calculated from the whole file
963 * except the checksum field of the file. That is, calculate sha256
964 * from the version field to the end of the file.
965 * @version: version of this firmware.
966 * @blocks: the first firmware block of the file
970 char version
[RTL_VER_SIZE
];
971 struct fw_block blocks
[];
974 enum rtl8152_fw_flags
{
988 enum rtl8152_fw_fixup_cmd
{
1000 struct fw_phy_speed_up
{
1001 struct fw_block blk_hdr
;
1010 struct fw_block blk_hdr
;
1011 struct fw_phy_set ver
;
1015 struct fw_phy_fixup
{
1016 struct fw_block blk_hdr
;
1017 struct fw_phy_set setting
;
1022 struct fw_phy_union
{
1023 struct fw_block blk_hdr
;
1026 struct fw_phy_set pre_set
[2];
1027 struct fw_phy_set bp
[8];
1028 struct fw_phy_set bp_en
;
1035 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1036 * The layout of the firmware block is:
1037 * <struct fw_mac> + <info> + <firmware data>.
1038 * @blk_hdr: firmware descriptor (type, length)
1039 * @fw_offset: offset of the firmware binary data. The start address of
1040 * the data would be the address of struct fw_mac + @fw_offset.
1041 * @fw_reg: the register to load the firmware. Depends on chip.
1042 * @bp_ba_addr: the register to write break point base address. Depends on
1044 * @bp_ba_value: break point base address. Depends on chip.
1045 * @bp_en_addr: the register to write break point enabled mask. Depends
1047 * @bp_en_value: break point enabled mask. Depends on the firmware.
1048 * @bp_start: the start register of break points. Depends on chip.
1049 * @bp_num: the break point number which needs to be set for this firmware.
1050 * Depends on the firmware.
1051 * @bp: break points. Depends on firmware.
1052 * @reserved: reserved space (unused)
1053 * @fw_ver_reg: the register to store the fw version.
1054 * @fw_ver_data: the firmware version of the current type.
1055 * @info: additional information for debugging, and is followed by the
1056 * binary data of firmware.
1059 struct fw_block blk_hdr
;
1068 __le16 bp
[16]; /* any value determined by firmware */
1076 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1077 * This is used to set patch key when loading the firmware of PHY.
1078 * @blk_hdr: firmware descriptor (type, length)
1079 * @key_reg: the register to write the patch key.
1080 * @key_data: patch key.
1081 * @reserved: reserved space (unused)
1083 struct fw_phy_patch_key
{
1084 struct fw_block blk_hdr
;
1091 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1092 * The layout of the firmware block is:
1093 * <struct fw_phy_nc> + <info> + <firmware data>.
1094 * @blk_hdr: firmware descriptor (type, length)
1095 * @fw_offset: offset of the firmware binary data. The start address of
1096 * the data would be the address of struct fw_phy_nc + @fw_offset.
1097 * @fw_reg: the register to load the firmware. Depends on chip.
1098 * @ba_reg: the register to write the base address. Depends on chip.
1099 * @ba_data: base address. Depends on chip.
1100 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1101 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1102 * @mode_reg: the regitster of switching the mode.
1103 * @mode_pre: the mode needing to be set before loading the firmware.
1104 * @mode_post: the mode to be set when finishing to load the firmware.
1105 * @reserved: reserved space (unused)
1106 * @bp_start: the start register of break points. Depends on chip.
1107 * @bp_num: the break point number which needs to be set for this firmware.
1108 * Depends on the firmware.
1109 * @bp: break points. Depends on firmware.
1110 * @info: additional information for debugging, and is followed by the
1111 * binary data of firmware.
1114 struct fw_block blk_hdr
;
1119 __le16 patch_en_addr
;
1120 __le16 patch_en_value
;
1139 RTL_FW_PHY_UNION_NC
,
1140 RTL_FW_PHY_UNION_NC1
,
1141 RTL_FW_PHY_UNION_NC2
,
1142 RTL_FW_PHY_UNION_UC2
,
1143 RTL_FW_PHY_UNION_UC
,
1144 RTL_FW_PHY_UNION_MISC
,
1145 RTL_FW_PHY_SPEED_UP
,
1150 RTL_VER_UNKNOWN
= 0,
1173 TX_CSUM_SUCCESS
= 0,
1178 #define RTL_ADVERTISED_10_HALF BIT(0)
1179 #define RTL_ADVERTISED_10_FULL BIT(1)
1180 #define RTL_ADVERTISED_100_HALF BIT(2)
1181 #define RTL_ADVERTISED_100_FULL BIT(3)
1182 #define RTL_ADVERTISED_1000_HALF BIT(4)
1183 #define RTL_ADVERTISED_1000_FULL BIT(5)
1184 #define RTL_ADVERTISED_2500_FULL BIT(6)
1186 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1187 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1189 static const int multicast_filter_limit
= 32;
1190 static unsigned int agg_buf_sz
= 16384;
1192 #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1195 int get_registers(struct r8152
*tp
, u16 value
, u16 index
, u16 size
, void *data
)
1200 tmp
= kmalloc(size
, GFP_KERNEL
);
1204 ret
= usb_control_msg(tp
->udev
, tp
->pipe_ctrl_in
,
1205 RTL8152_REQ_GET_REGS
, RTL8152_REQT_READ
,
1206 value
, index
, tmp
, size
, 500);
1208 memset(data
, 0xff, size
);
1210 memcpy(data
, tmp
, size
);
1218 int set_registers(struct r8152
*tp
, u16 value
, u16 index
, u16 size
, void *data
)
1223 tmp
= kmemdup(data
, size
, GFP_KERNEL
);
1227 ret
= usb_control_msg(tp
->udev
, tp
->pipe_ctrl_out
,
1228 RTL8152_REQ_SET_REGS
, RTL8152_REQT_WRITE
,
1229 value
, index
, tmp
, size
, 500);
1236 static void rtl_set_unplug(struct r8152
*tp
)
1238 if (tp
->udev
->state
== USB_STATE_NOTATTACHED
) {
1239 set_bit(RTL8152_UNPLUG
, &tp
->flags
);
1240 smp_mb__after_atomic();
1244 static int generic_ocp_read(struct r8152
*tp
, u16 index
, u16 size
,
1245 void *data
, u16 type
)
1250 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1253 /* both size and indix must be 4 bytes align */
1254 if ((size
& 3) || !size
|| (index
& 3) || !data
)
1257 if ((u32
)index
+ (u32
)size
> 0xffff)
1262 ret
= get_registers(tp
, index
, type
, limit
, data
);
1270 ret
= get_registers(tp
, index
, type
, size
, data
);
1287 static int generic_ocp_write(struct r8152
*tp
, u16 index
, u16 byteen
,
1288 u16 size
, void *data
, u16 type
)
1291 u16 byteen_start
, byteen_end
, byen
;
1294 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1297 /* both size and indix must be 4 bytes align */
1298 if ((size
& 3) || !size
|| (index
& 3) || !data
)
1301 if ((u32
)index
+ (u32
)size
> 0xffff)
1304 byteen_start
= byteen
& BYTE_EN_START_MASK
;
1305 byteen_end
= byteen
& BYTE_EN_END_MASK
;
1307 byen
= byteen_start
| (byteen_start
<< 4);
1308 ret
= set_registers(tp
, index
, type
| byen
, 4, data
);
1321 ret
= set_registers(tp
, index
,
1322 type
| BYTE_EN_DWORD
,
1331 ret
= set_registers(tp
, index
,
1332 type
| BYTE_EN_DWORD
,
1344 byen
= byteen_end
| (byteen_end
>> 4);
1345 ret
= set_registers(tp
, index
, type
| byen
, 4, data
);
1358 int pla_ocp_read(struct r8152
*tp
, u16 index
, u16 size
, void *data
)
1360 return generic_ocp_read(tp
, index
, size
, data
, MCU_TYPE_PLA
);
1364 int pla_ocp_write(struct r8152
*tp
, u16 index
, u16 byteen
, u16 size
, void *data
)
1366 return generic_ocp_write(tp
, index
, byteen
, size
, data
, MCU_TYPE_PLA
);
1370 int usb_ocp_write(struct r8152
*tp
, u16 index
, u16 byteen
, u16 size
, void *data
)
1372 return generic_ocp_write(tp
, index
, byteen
, size
, data
, MCU_TYPE_USB
);
1375 static u32
ocp_read_dword(struct r8152
*tp
, u16 type
, u16 index
)
1379 generic_ocp_read(tp
, index
, sizeof(data
), &data
, type
);
1381 return __le32_to_cpu(data
);
1384 static void ocp_write_dword(struct r8152
*tp
, u16 type
, u16 index
, u32 data
)
1386 __le32 tmp
= __cpu_to_le32(data
);
1388 generic_ocp_write(tp
, index
, BYTE_EN_DWORD
, sizeof(tmp
), &tmp
, type
);
1391 static u16
ocp_read_word(struct r8152
*tp
, u16 type
, u16 index
)
1395 u16 byen
= BYTE_EN_WORD
;
1396 u8 shift
= index
& 2;
1401 generic_ocp_read(tp
, index
, sizeof(tmp
), &tmp
, type
| byen
);
1403 data
= __le32_to_cpu(tmp
);
1404 data
>>= (shift
* 8);
1410 static void ocp_write_word(struct r8152
*tp
, u16 type
, u16 index
, u32 data
)
1414 u16 byen
= BYTE_EN_WORD
;
1415 u8 shift
= index
& 2;
1421 mask
<<= (shift
* 8);
1422 data
<<= (shift
* 8);
1426 tmp
= __cpu_to_le32(data
);
1428 generic_ocp_write(tp
, index
, byen
, sizeof(tmp
), &tmp
, type
);
1431 static u8
ocp_read_byte(struct r8152
*tp
, u16 type
, u16 index
)
1435 u8 shift
= index
& 3;
1439 generic_ocp_read(tp
, index
, sizeof(tmp
), &tmp
, type
);
1441 data
= __le32_to_cpu(tmp
);
1442 data
>>= (shift
* 8);
1448 static void ocp_write_byte(struct r8152
*tp
, u16 type
, u16 index
, u32 data
)
1452 u16 byen
= BYTE_EN_BYTE
;
1453 u8 shift
= index
& 3;
1459 mask
<<= (shift
* 8);
1460 data
<<= (shift
* 8);
1464 tmp
= __cpu_to_le32(data
);
1466 generic_ocp_write(tp
, index
, byen
, sizeof(tmp
), &tmp
, type
);
1469 static u16
ocp_reg_read(struct r8152
*tp
, u16 addr
)
1471 u16 ocp_base
, ocp_index
;
1473 ocp_base
= addr
& 0xf000;
1474 if (ocp_base
!= tp
->ocp_base
) {
1475 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_OCP_GPHY_BASE
, ocp_base
);
1476 tp
->ocp_base
= ocp_base
;
1479 ocp_index
= (addr
& 0x0fff) | 0xb000;
1480 return ocp_read_word(tp
, MCU_TYPE_PLA
, ocp_index
);
1483 static void ocp_reg_write(struct r8152
*tp
, u16 addr
, u16 data
)
1485 u16 ocp_base
, ocp_index
;
1487 ocp_base
= addr
& 0xf000;
1488 if (ocp_base
!= tp
->ocp_base
) {
1489 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_OCP_GPHY_BASE
, ocp_base
);
1490 tp
->ocp_base
= ocp_base
;
1493 ocp_index
= (addr
& 0x0fff) | 0xb000;
1494 ocp_write_word(tp
, MCU_TYPE_PLA
, ocp_index
, data
);
1497 static inline void r8152_mdio_write(struct r8152
*tp
, u32 reg_addr
, u32 value
)
1499 ocp_reg_write(tp
, OCP_BASE_MII
+ reg_addr
* 2, value
);
1502 static inline int r8152_mdio_read(struct r8152
*tp
, u32 reg_addr
)
1504 return ocp_reg_read(tp
, OCP_BASE_MII
+ reg_addr
* 2);
1507 static void sram_write(struct r8152
*tp
, u16 addr
, u16 data
)
1509 ocp_reg_write(tp
, OCP_SRAM_ADDR
, addr
);
1510 ocp_reg_write(tp
, OCP_SRAM_DATA
, data
);
1513 static u16
sram_read(struct r8152
*tp
, u16 addr
)
1515 ocp_reg_write(tp
, OCP_SRAM_ADDR
, addr
);
1516 return ocp_reg_read(tp
, OCP_SRAM_DATA
);
1519 static int read_mii_word(struct net_device
*netdev
, int phy_id
, int reg
)
1521 struct r8152
*tp
= netdev_priv(netdev
);
1524 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1527 if (phy_id
!= R8152_PHY_ID
)
1530 ret
= r8152_mdio_read(tp
, reg
);
1536 void write_mii_word(struct net_device
*netdev
, int phy_id
, int reg
, int val
)
1538 struct r8152
*tp
= netdev_priv(netdev
);
1540 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1543 if (phy_id
!= R8152_PHY_ID
)
1546 r8152_mdio_write(tp
, reg
, val
);
1550 r8152_submit_rx(struct r8152
*tp
, struct rx_agg
*agg
, gfp_t mem_flags
);
1553 rtl8152_set_speed(struct r8152
*tp
, u8 autoneg
, u32 speed
, u8 duplex
,
1556 static int __rtl8152_set_mac_address(struct net_device
*netdev
, void *p
,
1559 struct r8152
*tp
= netdev_priv(netdev
);
1560 struct sockaddr
*addr
= p
;
1561 int ret
= -EADDRNOTAVAIL
;
1563 if (!is_valid_ether_addr(addr
->sa_data
))
1567 ret
= usb_autopm_get_interface(tp
->intf
);
1572 mutex_lock(&tp
->control
);
1574 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1576 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
1577 pla_ocp_write(tp
, PLA_IDR
, BYTE_EN_SIX_BYTES
, 8, addr
->sa_data
);
1578 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
1580 mutex_unlock(&tp
->control
);
1583 usb_autopm_put_interface(tp
->intf
);
1588 static int rtl8152_set_mac_address(struct net_device
*netdev
, void *p
)
1590 return __rtl8152_set_mac_address(netdev
, p
, false);
1593 /* Devices containing proper chips can support a persistent
1594 * host system provided MAC address.
1595 * Examples of this are Dell TB15 and Dell WD15 docks
1597 static int vendor_mac_passthru_addr_read(struct r8152
*tp
, struct sockaddr
*sa
)
1600 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
1601 union acpi_object
*obj
;
1604 unsigned char buf
[6];
1606 acpi_object_type mac_obj_type
;
1609 if (tp
->lenovo_macpassthru
) {
1610 mac_obj_name
= "\\MACA";
1611 mac_obj_type
= ACPI_TYPE_STRING
;
1614 /* test for -AD variant of RTL8153 */
1615 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
1616 if ((ocp_data
& AD_MASK
) == 0x1000) {
1617 /* test for MAC address pass-through bit */
1618 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, EFUSE
);
1619 if ((ocp_data
& PASS_THRU_MASK
) != 1) {
1620 netif_dbg(tp
, probe
, tp
->netdev
,
1621 "No efuse for RTL8153-AD MAC pass through\n");
1625 /* test for RTL8153-BND and RTL8153-BD */
1626 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_1
);
1627 if ((ocp_data
& BND_MASK
) == 0 && (ocp_data
& BD_MASK
) == 0) {
1628 netif_dbg(tp
, probe
, tp
->netdev
,
1629 "Invalid variant for MAC pass through\n");
1634 mac_obj_name
= "\\_SB.AMAC";
1635 mac_obj_type
= ACPI_TYPE_BUFFER
;
1639 /* returns _AUXMAC_#AABBCCDDEEFF# */
1640 status
= acpi_evaluate_object(NULL
, mac_obj_name
, NULL
, &buffer
);
1641 obj
= (union acpi_object
*)buffer
.pointer
;
1642 if (!ACPI_SUCCESS(status
))
1644 if (obj
->type
!= mac_obj_type
|| obj
->string
.length
!= mac_strlen
) {
1645 netif_warn(tp
, probe
, tp
->netdev
,
1646 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1647 obj
->type
, obj
->string
.length
);
1651 if (strncmp(obj
->string
.pointer
, "_AUXMAC_#", 9) != 0 ||
1652 strncmp(obj
->string
.pointer
+ 0x15, "#", 1) != 0) {
1653 netif_warn(tp
, probe
, tp
->netdev
,
1654 "Invalid header when reading pass-thru MAC addr\n");
1657 ret
= hex2bin(buf
, obj
->string
.pointer
+ 9, 6);
1658 if (!(ret
== 0 && is_valid_ether_addr(buf
))) {
1659 netif_warn(tp
, probe
, tp
->netdev
,
1660 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1665 memcpy(sa
->sa_data
, buf
, 6);
1666 netif_info(tp
, probe
, tp
->netdev
,
1667 "Using pass-thru MAC addr %pM\n", sa
->sa_data
);
1674 static int determine_ethernet_addr(struct r8152
*tp
, struct sockaddr
*sa
)
1676 struct net_device
*dev
= tp
->netdev
;
1679 sa
->sa_family
= dev
->type
;
1681 ret
= eth_platform_get_mac_address(&tp
->udev
->dev
, sa
->sa_data
);
1683 if (tp
->version
== RTL_VER_01
) {
1684 ret
= pla_ocp_read(tp
, PLA_IDR
, 8, sa
->sa_data
);
1686 /* if device doesn't support MAC pass through this will
1687 * be expected to be non-zero
1689 ret
= vendor_mac_passthru_addr_read(tp
, sa
);
1691 ret
= pla_ocp_read(tp
, PLA_BACKUP
, 8,
1697 netif_err(tp
, probe
, dev
, "Get ether addr fail\n");
1698 } else if (!is_valid_ether_addr(sa
->sa_data
)) {
1699 netif_err(tp
, probe
, dev
, "Invalid ether addr %pM\n",
1701 eth_hw_addr_random(dev
);
1702 ether_addr_copy(sa
->sa_data
, dev
->dev_addr
);
1703 netif_info(tp
, probe
, dev
, "Random ether addr %pM\n",
1711 static int set_ethernet_addr(struct r8152
*tp
, bool in_resume
)
1713 struct net_device
*dev
= tp
->netdev
;
1717 ret
= determine_ethernet_addr(tp
, &sa
);
1721 if (tp
->version
== RTL_VER_01
)
1722 ether_addr_copy(dev
->dev_addr
, sa
.sa_data
);
1724 ret
= __rtl8152_set_mac_address(dev
, &sa
, in_resume
);
1729 static void read_bulk_callback(struct urb
*urb
)
1731 struct net_device
*netdev
;
1732 int status
= urb
->status
;
1735 unsigned long flags
;
1745 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1748 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
1751 netdev
= tp
->netdev
;
1753 /* When link down, the driver would cancel all bulks. */
1754 /* This avoid the re-submitting bulk */
1755 if (!netif_carrier_ok(netdev
))
1758 usb_mark_last_busy(tp
->udev
);
1762 if (urb
->actual_length
< ETH_ZLEN
)
1765 spin_lock_irqsave(&tp
->rx_lock
, flags
);
1766 list_add_tail(&agg
->list
, &tp
->rx_done
);
1767 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
1768 napi_schedule(&tp
->napi
);
1772 netif_device_detach(tp
->netdev
);
1775 urb
->actual_length
= 0;
1776 spin_lock_irqsave(&tp
->rx_lock
, flags
);
1777 list_add_tail(&agg
->list
, &tp
->rx_done
);
1778 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
1779 set_bit(RX_EPROTO
, &tp
->flags
);
1780 schedule_delayed_work(&tp
->schedule
, 1);
1783 return; /* the urb is in unlink state */
1785 if (net_ratelimit())
1786 netdev_warn(netdev
, "maybe reset is needed?\n");
1789 if (net_ratelimit())
1790 netdev_warn(netdev
, "Rx status %d\n", status
);
1794 r8152_submit_rx(tp
, agg
, GFP_ATOMIC
);
1797 static void write_bulk_callback(struct urb
*urb
)
1799 struct net_device_stats
*stats
;
1800 struct net_device
*netdev
;
1803 unsigned long flags
;
1804 int status
= urb
->status
;
1814 netdev
= tp
->netdev
;
1815 stats
= &netdev
->stats
;
1817 if (net_ratelimit())
1818 netdev_warn(netdev
, "Tx status %d\n", status
);
1819 stats
->tx_errors
+= agg
->skb_num
;
1821 stats
->tx_packets
+= agg
->skb_num
;
1822 stats
->tx_bytes
+= agg
->skb_len
;
1825 spin_lock_irqsave(&tp
->tx_lock
, flags
);
1826 list_add_tail(&agg
->list
, &tp
->tx_free
);
1827 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
1829 usb_autopm_put_interface_async(tp
->intf
);
1831 if (!netif_carrier_ok(netdev
))
1834 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
1837 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1840 if (!skb_queue_empty(&tp
->tx_queue
))
1841 tasklet_schedule(&tp
->tx_tl
);
1844 static void intr_callback(struct urb
*urb
)
1848 int status
= urb
->status
;
1855 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
1858 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1862 case 0: /* success */
1864 case -ECONNRESET
: /* unlink */
1866 netif_device_detach(tp
->netdev
);
1870 netif_info(tp
, intr
, tp
->netdev
,
1871 "Stop submitting intr, status %d\n", status
);
1874 netif_info(tp
, intr
, tp
->netdev
, "intr status -EOVERFLOW\n");
1876 /* -EPIPE: should clear the halt */
1878 netif_info(tp
, intr
, tp
->netdev
, "intr status %d\n", status
);
1882 d
= urb
->transfer_buffer
;
1883 if (INTR_LINK
& __le16_to_cpu(d
[0])) {
1884 if (!netif_carrier_ok(tp
->netdev
)) {
1885 set_bit(RTL8152_LINK_CHG
, &tp
->flags
);
1886 schedule_delayed_work(&tp
->schedule
, 0);
1889 if (netif_carrier_ok(tp
->netdev
)) {
1890 netif_stop_queue(tp
->netdev
);
1891 set_bit(RTL8152_LINK_CHG
, &tp
->flags
);
1892 schedule_delayed_work(&tp
->schedule
, 0);
1897 res
= usb_submit_urb(urb
, GFP_ATOMIC
);
1898 if (res
== -ENODEV
) {
1900 netif_device_detach(tp
->netdev
);
1902 netif_err(tp
, intr
, tp
->netdev
,
1903 "can't resubmit intr, status %d\n", res
);
1907 static inline void *rx_agg_align(void *data
)
1909 return (void *)ALIGN((uintptr_t)data
, RX_ALIGN
);
1912 static inline void *tx_agg_align(void *data
)
1914 return (void *)ALIGN((uintptr_t)data
, TX_ALIGN
);
1917 static void free_rx_agg(struct r8152
*tp
, struct rx_agg
*agg
)
1919 list_del(&agg
->info_list
);
1921 usb_free_urb(agg
->urb
);
1922 put_page(agg
->page
);
1925 atomic_dec(&tp
->rx_count
);
1928 static struct rx_agg
*alloc_rx_agg(struct r8152
*tp
, gfp_t mflags
)
1930 struct net_device
*netdev
= tp
->netdev
;
1931 int node
= netdev
->dev
.parent
? dev_to_node(netdev
->dev
.parent
) : -1;
1932 unsigned int order
= get_order(tp
->rx_buf_sz
);
1933 struct rx_agg
*rx_agg
;
1934 unsigned long flags
;
1936 rx_agg
= kmalloc_node(sizeof(*rx_agg
), mflags
, node
);
1940 rx_agg
->page
= alloc_pages(mflags
| __GFP_COMP
, order
);
1944 rx_agg
->buffer
= page_address(rx_agg
->page
);
1946 rx_agg
->urb
= usb_alloc_urb(0, mflags
);
1950 rx_agg
->context
= tp
;
1952 INIT_LIST_HEAD(&rx_agg
->list
);
1953 INIT_LIST_HEAD(&rx_agg
->info_list
);
1954 spin_lock_irqsave(&tp
->rx_lock
, flags
);
1955 list_add_tail(&rx_agg
->info_list
, &tp
->rx_info
);
1956 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
1958 atomic_inc(&tp
->rx_count
);
1963 __free_pages(rx_agg
->page
, order
);
1969 static void free_all_mem(struct r8152
*tp
)
1971 struct rx_agg
*agg
, *agg_next
;
1972 unsigned long flags
;
1975 spin_lock_irqsave(&tp
->rx_lock
, flags
);
1977 list_for_each_entry_safe(agg
, agg_next
, &tp
->rx_info
, info_list
)
1978 free_rx_agg(tp
, agg
);
1980 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
1982 WARN_ON(atomic_read(&tp
->rx_count
));
1984 for (i
= 0; i
< RTL8152_MAX_TX
; i
++) {
1985 usb_free_urb(tp
->tx_info
[i
].urb
);
1986 tp
->tx_info
[i
].urb
= NULL
;
1988 kfree(tp
->tx_info
[i
].buffer
);
1989 tp
->tx_info
[i
].buffer
= NULL
;
1990 tp
->tx_info
[i
].head
= NULL
;
1993 usb_free_urb(tp
->intr_urb
);
1994 tp
->intr_urb
= NULL
;
1996 kfree(tp
->intr_buff
);
1997 tp
->intr_buff
= NULL
;
2000 static int alloc_all_mem(struct r8152
*tp
)
2002 struct net_device
*netdev
= tp
->netdev
;
2003 struct usb_interface
*intf
= tp
->intf
;
2004 struct usb_host_interface
*alt
= intf
->cur_altsetting
;
2005 struct usb_host_endpoint
*ep_intr
= alt
->endpoint
+ 2;
2008 node
= netdev
->dev
.parent
? dev_to_node(netdev
->dev
.parent
) : -1;
2010 spin_lock_init(&tp
->rx_lock
);
2011 spin_lock_init(&tp
->tx_lock
);
2012 INIT_LIST_HEAD(&tp
->rx_info
);
2013 INIT_LIST_HEAD(&tp
->tx_free
);
2014 INIT_LIST_HEAD(&tp
->rx_done
);
2015 skb_queue_head_init(&tp
->tx_queue
);
2016 skb_queue_head_init(&tp
->rx_queue
);
2017 atomic_set(&tp
->rx_count
, 0);
2019 for (i
= 0; i
< RTL8152_MAX_RX
; i
++) {
2020 if (!alloc_rx_agg(tp
, GFP_KERNEL
))
2024 for (i
= 0; i
< RTL8152_MAX_TX
; i
++) {
2028 buf
= kmalloc_node(agg_buf_sz
, GFP_KERNEL
, node
);
2032 if (buf
!= tx_agg_align(buf
)) {
2034 buf
= kmalloc_node(agg_buf_sz
+ TX_ALIGN
, GFP_KERNEL
,
2040 urb
= usb_alloc_urb(0, GFP_KERNEL
);
2046 INIT_LIST_HEAD(&tp
->tx_info
[i
].list
);
2047 tp
->tx_info
[i
].context
= tp
;
2048 tp
->tx_info
[i
].urb
= urb
;
2049 tp
->tx_info
[i
].buffer
= buf
;
2050 tp
->tx_info
[i
].head
= tx_agg_align(buf
);
2052 list_add_tail(&tp
->tx_info
[i
].list
, &tp
->tx_free
);
2055 tp
->intr_urb
= usb_alloc_urb(0, GFP_KERNEL
);
2059 tp
->intr_buff
= kmalloc(INTBUFSIZE
, GFP_KERNEL
);
2063 tp
->intr_interval
= (int)ep_intr
->desc
.bInterval
;
2064 usb_fill_int_urb(tp
->intr_urb
, tp
->udev
, tp
->pipe_intr
,
2065 tp
->intr_buff
, INTBUFSIZE
, intr_callback
,
2066 tp
, tp
->intr_interval
);
2075 static struct tx_agg
*r8152_get_tx_agg(struct r8152
*tp
)
2077 struct tx_agg
*agg
= NULL
;
2078 unsigned long flags
;
2080 if (list_empty(&tp
->tx_free
))
2083 spin_lock_irqsave(&tp
->tx_lock
, flags
);
2084 if (!list_empty(&tp
->tx_free
)) {
2085 struct list_head
*cursor
;
2087 cursor
= tp
->tx_free
.next
;
2088 list_del_init(cursor
);
2089 agg
= list_entry(cursor
, struct tx_agg
, list
);
2091 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
2096 /* r8152_csum_workaround()
2097 * The hw limits the value of the transport offset. When the offset is out of
2098 * range, calculate the checksum by sw.
2100 static void r8152_csum_workaround(struct r8152
*tp
, struct sk_buff
*skb
,
2101 struct sk_buff_head
*list
)
2103 if (skb_shinfo(skb
)->gso_size
) {
2104 netdev_features_t features
= tp
->netdev
->features
;
2105 struct sk_buff
*segs
, *seg
, *next
;
2106 struct sk_buff_head seg_list
;
2108 features
&= ~(NETIF_F_SG
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
);
2109 segs
= skb_gso_segment(skb
, features
);
2110 if (IS_ERR(segs
) || !segs
)
2113 __skb_queue_head_init(&seg_list
);
2115 skb_list_walk_safe(segs
, seg
, next
) {
2116 skb_mark_not_on_list(seg
);
2117 __skb_queue_tail(&seg_list
, seg
);
2120 skb_queue_splice(&seg_list
, list
);
2122 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2123 if (skb_checksum_help(skb
) < 0)
2126 __skb_queue_head(list
, skb
);
2128 struct net_device_stats
*stats
;
2131 stats
= &tp
->netdev
->stats
;
2132 stats
->tx_dropped
++;
2137 static inline void rtl_tx_vlan_tag(struct tx_desc
*desc
, struct sk_buff
*skb
)
2139 if (skb_vlan_tag_present(skb
)) {
2142 opts2
= TX_VLAN_TAG
| swab16(skb_vlan_tag_get(skb
));
2143 desc
->opts2
|= cpu_to_le32(opts2
);
2147 static inline void rtl_rx_vlan_tag(struct rx_desc
*desc
, struct sk_buff
*skb
)
2149 u32 opts2
= le32_to_cpu(desc
->opts2
);
2151 if (opts2
& RX_VLAN_TAG
)
2152 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
2153 swab16(opts2
& 0xffff));
2156 static int r8152_tx_csum(struct r8152
*tp
, struct tx_desc
*desc
,
2157 struct sk_buff
*skb
, u32 len
, u32 transport_offset
)
2159 u32 mss
= skb_shinfo(skb
)->gso_size
;
2160 u32 opts1
, opts2
= 0;
2161 int ret
= TX_CSUM_SUCCESS
;
2163 WARN_ON_ONCE(len
> TX_LEN_MAX
);
2165 opts1
= len
| TX_FS
| TX_LS
;
2168 if (transport_offset
> GTTCPHO_MAX
) {
2169 netif_warn(tp
, tx_err
, tp
->netdev
,
2170 "Invalid transport offset 0x%x for TSO\n",
2176 switch (vlan_get_protocol(skb
)) {
2177 case htons(ETH_P_IP
):
2181 case htons(ETH_P_IPV6
):
2182 if (skb_cow_head(skb
, 0)) {
2186 tcp_v6_gso_csum_prep(skb
);
2195 opts1
|= transport_offset
<< GTTCPHO_SHIFT
;
2196 opts2
|= min(mss
, MSS_MAX
) << MSS_SHIFT
;
2197 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2200 if (transport_offset
> TCPHO_MAX
) {
2201 netif_warn(tp
, tx_err
, tp
->netdev
,
2202 "Invalid transport offset 0x%x\n",
2208 switch (vlan_get_protocol(skb
)) {
2209 case htons(ETH_P_IP
):
2211 ip_protocol
= ip_hdr(skb
)->protocol
;
2214 case htons(ETH_P_IPV6
):
2216 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
2220 ip_protocol
= IPPROTO_RAW
;
2224 if (ip_protocol
== IPPROTO_TCP
)
2226 else if (ip_protocol
== IPPROTO_UDP
)
2231 opts2
|= transport_offset
<< TCPHO_SHIFT
;
2234 desc
->opts2
= cpu_to_le32(opts2
);
2235 desc
->opts1
= cpu_to_le32(opts1
);
2241 static int r8152_tx_agg_fill(struct r8152
*tp
, struct tx_agg
*agg
)
2243 struct sk_buff_head skb_head
, *tx_queue
= &tp
->tx_queue
;
2247 __skb_queue_head_init(&skb_head
);
2248 spin_lock(&tx_queue
->lock
);
2249 skb_queue_splice_init(tx_queue
, &skb_head
);
2250 spin_unlock(&tx_queue
->lock
);
2252 tx_data
= agg
->head
;
2255 remain
= agg_buf_sz
;
2257 while (remain
>= ETH_ZLEN
+ sizeof(struct tx_desc
)) {
2258 struct tx_desc
*tx_desc
;
2259 struct sk_buff
*skb
;
2263 skb
= __skb_dequeue(&skb_head
);
2267 len
= skb
->len
+ sizeof(*tx_desc
);
2270 __skb_queue_head(&skb_head
, skb
);
2274 tx_data
= tx_agg_align(tx_data
);
2275 tx_desc
= (struct tx_desc
*)tx_data
;
2277 offset
= (u32
)skb_transport_offset(skb
);
2279 if (r8152_tx_csum(tp
, tx_desc
, skb
, skb
->len
, offset
)) {
2280 r8152_csum_workaround(tp
, skb
, &skb_head
);
2284 rtl_tx_vlan_tag(tx_desc
, skb
);
2286 tx_data
+= sizeof(*tx_desc
);
2289 if (skb_copy_bits(skb
, 0, tx_data
, len
) < 0) {
2290 struct net_device_stats
*stats
= &tp
->netdev
->stats
;
2292 stats
->tx_dropped
++;
2293 dev_kfree_skb_any(skb
);
2294 tx_data
-= sizeof(*tx_desc
);
2299 agg
->skb_len
+= len
;
2300 agg
->skb_num
+= skb_shinfo(skb
)->gso_segs
?: 1;
2302 dev_kfree_skb_any(skb
);
2304 remain
= agg_buf_sz
- (int)(tx_agg_align(tx_data
) - agg
->head
);
2306 if (tp
->dell_tb_rx_agg_bug
)
2310 if (!skb_queue_empty(&skb_head
)) {
2311 spin_lock(&tx_queue
->lock
);
2312 skb_queue_splice(&skb_head
, tx_queue
);
2313 spin_unlock(&tx_queue
->lock
);
2316 netif_tx_lock(tp
->netdev
);
2318 if (netif_queue_stopped(tp
->netdev
) &&
2319 skb_queue_len(&tp
->tx_queue
) < tp
->tx_qlen
)
2320 netif_wake_queue(tp
->netdev
);
2322 netif_tx_unlock(tp
->netdev
);
2324 ret
= usb_autopm_get_interface_async(tp
->intf
);
2328 usb_fill_bulk_urb(agg
->urb
, tp
->udev
, tp
->pipe_out
,
2329 agg
->head
, (int)(tx_data
- (u8
*)agg
->head
),
2330 (usb_complete_t
)write_bulk_callback
, agg
);
2332 ret
= usb_submit_urb(agg
->urb
, GFP_ATOMIC
);
2334 usb_autopm_put_interface_async(tp
->intf
);
2340 static u8
r8152_rx_csum(struct r8152
*tp
, struct rx_desc
*rx_desc
)
2342 u8 checksum
= CHECKSUM_NONE
;
2345 if (!(tp
->netdev
->features
& NETIF_F_RXCSUM
))
2348 opts2
= le32_to_cpu(rx_desc
->opts2
);
2349 opts3
= le32_to_cpu(rx_desc
->opts3
);
2351 if (opts2
& RD_IPV4_CS
) {
2353 checksum
= CHECKSUM_NONE
;
2354 else if ((opts2
& RD_UDP_CS
) && !(opts3
& UDPF
))
2355 checksum
= CHECKSUM_UNNECESSARY
;
2356 else if ((opts2
& RD_TCP_CS
) && !(opts3
& TCPF
))
2357 checksum
= CHECKSUM_UNNECESSARY
;
2358 } else if (opts2
& RD_IPV6_CS
) {
2359 if ((opts2
& RD_UDP_CS
) && !(opts3
& UDPF
))
2360 checksum
= CHECKSUM_UNNECESSARY
;
2361 else if ((opts2
& RD_TCP_CS
) && !(opts3
& TCPF
))
2362 checksum
= CHECKSUM_UNNECESSARY
;
2369 static inline bool rx_count_exceed(struct r8152
*tp
)
2371 return atomic_read(&tp
->rx_count
) > RTL8152_MAX_RX
;
2374 static inline int agg_offset(struct rx_agg
*agg
, void *addr
)
2376 return (int)(addr
- agg
->buffer
);
2379 static struct rx_agg
*rtl_get_free_rx(struct r8152
*tp
, gfp_t mflags
)
2381 struct rx_agg
*agg
, *agg_next
, *agg_free
= NULL
;
2382 unsigned long flags
;
2384 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2386 list_for_each_entry_safe(agg
, agg_next
, &tp
->rx_used
, list
) {
2387 if (page_count(agg
->page
) == 1) {
2389 list_del_init(&agg
->list
);
2393 if (rx_count_exceed(tp
)) {
2394 list_del_init(&agg
->list
);
2395 free_rx_agg(tp
, agg
);
2401 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2403 if (!agg_free
&& atomic_read(&tp
->rx_count
) < tp
->rx_pending
)
2404 agg_free
= alloc_rx_agg(tp
, mflags
);
2409 static int rx_bottom(struct r8152
*tp
, int budget
)
2411 unsigned long flags
;
2412 struct list_head
*cursor
, *next
, rx_queue
;
2413 int ret
= 0, work_done
= 0;
2414 struct napi_struct
*napi
= &tp
->napi
;
2416 if (!skb_queue_empty(&tp
->rx_queue
)) {
2417 while (work_done
< budget
) {
2418 struct sk_buff
*skb
= __skb_dequeue(&tp
->rx_queue
);
2419 struct net_device
*netdev
= tp
->netdev
;
2420 struct net_device_stats
*stats
= &netdev
->stats
;
2421 unsigned int pkt_len
;
2427 napi_gro_receive(napi
, skb
);
2429 stats
->rx_packets
++;
2430 stats
->rx_bytes
+= pkt_len
;
2434 if (list_empty(&tp
->rx_done
))
2437 clear_bit(RX_EPROTO
, &tp
->flags
);
2438 INIT_LIST_HEAD(&rx_queue
);
2439 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2440 list_splice_init(&tp
->rx_done
, &rx_queue
);
2441 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2443 list_for_each_safe(cursor
, next
, &rx_queue
) {
2444 struct rx_desc
*rx_desc
;
2445 struct rx_agg
*agg
, *agg_free
;
2450 list_del_init(cursor
);
2452 agg
= list_entry(cursor
, struct rx_agg
, list
);
2454 if (urb
->status
!= 0 || urb
->actual_length
< ETH_ZLEN
)
2457 agg_free
= rtl_get_free_rx(tp
, GFP_ATOMIC
);
2459 rx_desc
= agg
->buffer
;
2460 rx_data
= agg
->buffer
;
2461 len_used
+= sizeof(struct rx_desc
);
2463 while (urb
->actual_length
> len_used
) {
2464 struct net_device
*netdev
= tp
->netdev
;
2465 struct net_device_stats
*stats
= &netdev
->stats
;
2466 unsigned int pkt_len
, rx_frag_head_sz
;
2467 struct sk_buff
*skb
;
2469 /* limit the skb numbers for rx_queue */
2470 if (unlikely(skb_queue_len(&tp
->rx_queue
) >= 1000))
2473 pkt_len
= le32_to_cpu(rx_desc
->opts1
) & RX_LEN_MASK
;
2474 if (pkt_len
< ETH_ZLEN
)
2477 len_used
+= pkt_len
;
2478 if (urb
->actual_length
< len_used
)
2481 pkt_len
-= ETH_FCS_LEN
;
2482 rx_data
+= sizeof(struct rx_desc
);
2484 if (!agg_free
|| tp
->rx_copybreak
> pkt_len
)
2485 rx_frag_head_sz
= pkt_len
;
2487 rx_frag_head_sz
= tp
->rx_copybreak
;
2489 skb
= napi_alloc_skb(napi
, rx_frag_head_sz
);
2491 stats
->rx_dropped
++;
2495 skb
->ip_summed
= r8152_rx_csum(tp
, rx_desc
);
2496 memcpy(skb
->data
, rx_data
, rx_frag_head_sz
);
2497 skb_put(skb
, rx_frag_head_sz
);
2498 pkt_len
-= rx_frag_head_sz
;
2499 rx_data
+= rx_frag_head_sz
;
2501 skb_add_rx_frag(skb
, 0, agg
->page
,
2502 agg_offset(agg
, rx_data
),
2504 SKB_DATA_ALIGN(pkt_len
));
2505 get_page(agg
->page
);
2508 skb
->protocol
= eth_type_trans(skb
, netdev
);
2509 rtl_rx_vlan_tag(rx_desc
, skb
);
2510 if (work_done
< budget
) {
2512 stats
->rx_packets
++;
2513 stats
->rx_bytes
+= skb
->len
;
2514 napi_gro_receive(napi
, skb
);
2516 __skb_queue_tail(&tp
->rx_queue
, skb
);
2520 rx_data
= rx_agg_align(rx_data
+ pkt_len
+ ETH_FCS_LEN
);
2521 rx_desc
= (struct rx_desc
*)rx_data
;
2522 len_used
= agg_offset(agg
, rx_data
);
2523 len_used
+= sizeof(struct rx_desc
);
2526 WARN_ON(!agg_free
&& page_count(agg
->page
) > 1);
2529 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2530 if (page_count(agg
->page
) == 1) {
2531 list_add(&agg_free
->list
, &tp
->rx_used
);
2533 list_add_tail(&agg
->list
, &tp
->rx_used
);
2537 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2542 ret
= r8152_submit_rx(tp
, agg
, GFP_ATOMIC
);
2544 urb
->actual_length
= 0;
2545 list_add_tail(&agg
->list
, next
);
2549 if (!list_empty(&rx_queue
)) {
2550 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2551 list_splice_tail(&rx_queue
, &tp
->rx_done
);
2552 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2559 static void tx_bottom(struct r8152
*tp
)
2564 struct net_device
*netdev
= tp
->netdev
;
2567 if (skb_queue_empty(&tp
->tx_queue
))
2570 agg
= r8152_get_tx_agg(tp
);
2574 res
= r8152_tx_agg_fill(tp
, agg
);
2578 if (res
== -ENODEV
) {
2580 netif_device_detach(netdev
);
2582 struct net_device_stats
*stats
= &netdev
->stats
;
2583 unsigned long flags
;
2585 netif_warn(tp
, tx_err
, netdev
,
2586 "failed tx_urb %d\n", res
);
2587 stats
->tx_dropped
+= agg
->skb_num
;
2589 spin_lock_irqsave(&tp
->tx_lock
, flags
);
2590 list_add_tail(&agg
->list
, &tp
->tx_free
);
2591 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
2596 static void bottom_half(struct tasklet_struct
*t
)
2598 struct r8152
*tp
= from_tasklet(tp
, t
, tx_tl
);
2600 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
2603 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
2606 /* When link down, the driver would cancel all bulks. */
2607 /* This avoid the re-submitting bulk */
2608 if (!netif_carrier_ok(tp
->netdev
))
2611 clear_bit(SCHEDULE_TASKLET
, &tp
->flags
);
2616 static int r8152_poll(struct napi_struct
*napi
, int budget
)
2618 struct r8152
*tp
= container_of(napi
, struct r8152
, napi
);
2621 work_done
= rx_bottom(tp
, budget
);
2623 if (work_done
< budget
) {
2624 if (!napi_complete_done(napi
, work_done
))
2626 if (!list_empty(&tp
->rx_done
))
2627 napi_schedule(napi
);
2635 int r8152_submit_rx(struct r8152
*tp
, struct rx_agg
*agg
, gfp_t mem_flags
)
2639 /* The rx would be stopped, so skip submitting */
2640 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
) ||
2641 !test_bit(WORK_ENABLE
, &tp
->flags
) || !netif_carrier_ok(tp
->netdev
))
2644 usb_fill_bulk_urb(agg
->urb
, tp
->udev
, tp
->pipe_in
,
2645 agg
->buffer
, tp
->rx_buf_sz
,
2646 (usb_complete_t
)read_bulk_callback
, agg
);
2648 ret
= usb_submit_urb(agg
->urb
, mem_flags
);
2649 if (ret
== -ENODEV
) {
2651 netif_device_detach(tp
->netdev
);
2653 struct urb
*urb
= agg
->urb
;
2654 unsigned long flags
;
2656 urb
->actual_length
= 0;
2657 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2658 list_add_tail(&agg
->list
, &tp
->rx_done
);
2659 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2661 netif_err(tp
, rx_err
, tp
->netdev
,
2662 "Couldn't submit rx[%p], ret = %d\n", agg
, ret
);
2664 napi_schedule(&tp
->napi
);
2670 static void rtl_drop_queued_tx(struct r8152
*tp
)
2672 struct net_device_stats
*stats
= &tp
->netdev
->stats
;
2673 struct sk_buff_head skb_head
, *tx_queue
= &tp
->tx_queue
;
2674 struct sk_buff
*skb
;
2676 if (skb_queue_empty(tx_queue
))
2679 __skb_queue_head_init(&skb_head
);
2680 spin_lock_bh(&tx_queue
->lock
);
2681 skb_queue_splice_init(tx_queue
, &skb_head
);
2682 spin_unlock_bh(&tx_queue
->lock
);
2684 while ((skb
= __skb_dequeue(&skb_head
))) {
2686 stats
->tx_dropped
++;
2690 static void rtl8152_tx_timeout(struct net_device
*netdev
, unsigned int txqueue
)
2692 struct r8152
*tp
= netdev_priv(netdev
);
2694 netif_warn(tp
, tx_err
, netdev
, "Tx timeout\n");
2696 usb_queue_reset_device(tp
->intf
);
2699 static void rtl8152_set_rx_mode(struct net_device
*netdev
)
2701 struct r8152
*tp
= netdev_priv(netdev
);
2703 if (netif_carrier_ok(netdev
)) {
2704 set_bit(RTL8152_SET_RX_MODE
, &tp
->flags
);
2705 schedule_delayed_work(&tp
->schedule
, 0);
2709 static void _rtl8152_set_rx_mode(struct net_device
*netdev
)
2711 struct r8152
*tp
= netdev_priv(netdev
);
2712 u32 mc_filter
[2]; /* Multicast hash filter */
2716 netif_stop_queue(netdev
);
2717 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
2718 ocp_data
&= ~RCR_ACPT_ALL
;
2719 ocp_data
|= RCR_AB
| RCR_APM
;
2721 if (netdev
->flags
& IFF_PROMISC
) {
2722 /* Unconditionally log net taps. */
2723 netif_notice(tp
, link
, netdev
, "Promiscuous mode enabled\n");
2724 ocp_data
|= RCR_AM
| RCR_AAP
;
2725 mc_filter
[1] = 0xffffffff;
2726 mc_filter
[0] = 0xffffffff;
2727 } else if ((netdev_mc_count(netdev
) > multicast_filter_limit
) ||
2728 (netdev
->flags
& IFF_ALLMULTI
)) {
2729 /* Too many to filter perfectly -- accept all multicasts. */
2731 mc_filter
[1] = 0xffffffff;
2732 mc_filter
[0] = 0xffffffff;
2734 struct netdev_hw_addr
*ha
;
2738 netdev_for_each_mc_addr(ha
, netdev
) {
2739 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
2741 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
2746 tmp
[0] = __cpu_to_le32(swab32(mc_filter
[1]));
2747 tmp
[1] = __cpu_to_le32(swab32(mc_filter
[0]));
2749 pla_ocp_write(tp
, PLA_MAR
, BYTE_EN_DWORD
, sizeof(tmp
), tmp
);
2750 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
2751 netif_wake_queue(netdev
);
2754 static netdev_features_t
2755 rtl8152_features_check(struct sk_buff
*skb
, struct net_device
*dev
,
2756 netdev_features_t features
)
2758 u32 mss
= skb_shinfo(skb
)->gso_size
;
2759 int max_offset
= mss
? GTTCPHO_MAX
: TCPHO_MAX
;
2760 int offset
= skb_transport_offset(skb
);
2762 if ((mss
|| skb
->ip_summed
== CHECKSUM_PARTIAL
) && offset
> max_offset
)
2763 features
&= ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
2764 else if ((skb
->len
+ sizeof(struct tx_desc
)) > agg_buf_sz
)
2765 features
&= ~NETIF_F_GSO_MASK
;
2770 static netdev_tx_t
rtl8152_start_xmit(struct sk_buff
*skb
,
2771 struct net_device
*netdev
)
2773 struct r8152
*tp
= netdev_priv(netdev
);
2775 skb_tx_timestamp(skb
);
2777 skb_queue_tail(&tp
->tx_queue
, skb
);
2779 if (!list_empty(&tp
->tx_free
)) {
2780 if (test_bit(SELECTIVE_SUSPEND
, &tp
->flags
)) {
2781 set_bit(SCHEDULE_TASKLET
, &tp
->flags
);
2782 schedule_delayed_work(&tp
->schedule
, 0);
2784 usb_mark_last_busy(tp
->udev
);
2785 tasklet_schedule(&tp
->tx_tl
);
2787 } else if (skb_queue_len(&tp
->tx_queue
) > tp
->tx_qlen
) {
2788 netif_stop_queue(netdev
);
2791 return NETDEV_TX_OK
;
2794 static void r8152b_reset_packet_filter(struct r8152
*tp
)
2798 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_FMC
);
2799 ocp_data
&= ~FMC_FCR_MCU_EN
;
2800 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_FMC
, ocp_data
);
2801 ocp_data
|= FMC_FCR_MCU_EN
;
2802 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_FMC
, ocp_data
);
2805 static void rtl8152_nic_reset(struct r8152
*tp
)
2810 switch (tp
->version
) {
2814 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CR
);
2816 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CR
, ocp_data
);
2818 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_BMU_RESET
);
2819 ocp_data
&= ~BMU_RESET_EP_IN
;
2820 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BMU_RESET
, ocp_data
);
2822 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
2823 ocp_data
|= CDC_ECM_EN
;
2824 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
2826 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CR
);
2828 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CR
, ocp_data
);
2830 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_BMU_RESET
);
2831 ocp_data
|= BMU_RESET_EP_IN
;
2832 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BMU_RESET
, ocp_data
);
2834 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
2835 ocp_data
&= ~CDC_ECM_EN
;
2836 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
2840 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CR
, CR_RST
);
2842 for (i
= 0; i
< 1000; i
++) {
2843 if (!(ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CR
) & CR_RST
))
2845 usleep_range(100, 400);
2851 static void set_tx_qlen(struct r8152
*tp
)
2853 tp
->tx_qlen
= agg_buf_sz
/ (mtu_to_size(tp
->netdev
->mtu
) + sizeof(struct tx_desc
));
2856 static inline u16
rtl8152_get_speed(struct r8152
*tp
)
2858 return ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHYSTATUS
);
2861 static void rtl_eee_plus_en(struct r8152
*tp
, bool enable
)
2865 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEEP_CR
);
2867 ocp_data
|= EEEP_CR_EEEP_TX
;
2869 ocp_data
&= ~EEEP_CR_EEEP_TX
;
2870 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEEP_CR
, ocp_data
);
2873 static void rtl_set_eee_plus(struct r8152
*tp
)
2875 if (rtl8152_get_speed(tp
) & _10bps
)
2876 rtl_eee_plus_en(tp
, true);
2878 rtl_eee_plus_en(tp
, false);
2881 static void rxdy_gated_en(struct r8152
*tp
, bool enable
)
2885 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MISC_1
);
2887 ocp_data
|= RXDY_GATED_EN
;
2889 ocp_data
&= ~RXDY_GATED_EN
;
2890 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MISC_1
, ocp_data
);
2893 static int rtl_start_rx(struct r8152
*tp
)
2895 struct rx_agg
*agg
, *agg_next
;
2896 struct list_head tmp_list
;
2897 unsigned long flags
;
2900 INIT_LIST_HEAD(&tmp_list
);
2902 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2904 INIT_LIST_HEAD(&tp
->rx_done
);
2905 INIT_LIST_HEAD(&tp
->rx_used
);
2907 list_splice_init(&tp
->rx_info
, &tmp_list
);
2909 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2911 list_for_each_entry_safe(agg
, agg_next
, &tmp_list
, info_list
) {
2912 INIT_LIST_HEAD(&agg
->list
);
2914 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2915 if (++i
> RTL8152_MAX_RX
) {
2916 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2917 list_add_tail(&agg
->list
, &tp
->rx_used
);
2918 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2919 } else if (unlikely(ret
< 0)) {
2920 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2921 list_add_tail(&agg
->list
, &tp
->rx_done
);
2922 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2924 ret
= r8152_submit_rx(tp
, agg
, GFP_KERNEL
);
2928 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2929 WARN_ON(!list_empty(&tp
->rx_info
));
2930 list_splice(&tmp_list
, &tp
->rx_info
);
2931 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2936 static int rtl_stop_rx(struct r8152
*tp
)
2938 struct rx_agg
*agg
, *agg_next
;
2939 struct list_head tmp_list
;
2940 unsigned long flags
;
2942 INIT_LIST_HEAD(&tmp_list
);
2944 /* The usb_kill_urb() couldn't be used in atomic.
2945 * Therefore, move the list of rx_info to a tmp one.
2946 * Then, list_for_each_entry_safe could be used without
2950 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2951 list_splice_init(&tp
->rx_info
, &tmp_list
);
2952 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2954 list_for_each_entry_safe(agg
, agg_next
, &tmp_list
, info_list
) {
2955 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2956 * equal to 1, so the other ones could be freed safely.
2958 if (page_count(agg
->page
) > 1)
2959 free_rx_agg(tp
, agg
);
2961 usb_kill_urb(agg
->urb
);
2964 /* Move back the list of temp to the rx_info */
2965 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2966 WARN_ON(!list_empty(&tp
->rx_info
));
2967 list_splice(&tmp_list
, &tp
->rx_info
);
2968 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2970 while (!skb_queue_empty(&tp
->rx_queue
))
2971 dev_kfree_skb(__skb_dequeue(&tp
->rx_queue
));
2976 static void rtl_set_ifg(struct r8152
*tp
, u16 speed
)
2980 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TCR1
);
2981 ocp_data
&= ~IFG_MASK
;
2982 if ((speed
& (_10bps
| _100bps
)) && !(speed
& FULL_DUP
)) {
2983 ocp_data
|= IFG_144NS
;
2984 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TCR1
, ocp_data
);
2986 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
);
2987 ocp_data
&= ~TX10MIDLE_EN
;
2988 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
, ocp_data
);
2990 ocp_data
|= IFG_96NS
;
2991 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TCR1
, ocp_data
);
2993 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
);
2994 ocp_data
|= TX10MIDLE_EN
;
2995 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
, ocp_data
);
2999 static inline void r8153b_rx_agg_chg_indicate(struct r8152
*tp
)
3001 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_UPT_RXDMA_OWN
,
3002 OWN_UPDATE
| OWN_CLEAR
);
3005 static int rtl_enable(struct r8152
*tp
)
3009 r8152b_reset_packet_filter(tp
);
3011 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CR
);
3012 ocp_data
|= CR_RE
| CR_TE
;
3013 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CR
, ocp_data
);
3015 switch (tp
->version
) {
3019 r8153b_rx_agg_chg_indicate(tp
);
3025 rxdy_gated_en(tp
, false);
3030 static int rtl8152_enable(struct r8152
*tp
)
3032 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
3036 rtl_set_eee_plus(tp
);
3038 return rtl_enable(tp
);
3041 static void r8153_set_rx_early_timeout(struct r8152
*tp
)
3043 u32 ocp_data
= tp
->coalesce
/ 8;
3045 switch (tp
->version
) {
3050 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_TIMEOUT
,
3057 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3058 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3060 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_TIMEOUT
,
3062 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EXTRA_AGGR_TMR
,
3071 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_TIMEOUT
,
3073 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EXTRA_AGGR_TMR
,
3075 r8153b_rx_agg_chg_indicate(tp
);
3083 static void r8153_set_rx_early_size(struct r8152
*tp
)
3085 u32 ocp_data
= tp
->rx_buf_sz
- rx_reserved_size(tp
->netdev
->mtu
);
3087 switch (tp
->version
) {
3092 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_SIZE
,
3098 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_SIZE
,
3107 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_SIZE
,
3109 r8153b_rx_agg_chg_indicate(tp
);
3117 static int rtl8153_enable(struct r8152
*tp
)
3121 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
3125 rtl_set_eee_plus(tp
);
3126 r8153_set_rx_early_timeout(tp
);
3127 r8153_set_rx_early_size(tp
);
3129 rtl_set_ifg(tp
, rtl8152_get_speed(tp
));
3131 switch (tp
->version
) {
3134 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
);
3135 ocp_data
&= ~FC_PATCH_TASK
;
3136 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
, ocp_data
);
3137 usleep_range(1000, 2000);
3138 ocp_data
|= FC_PATCH_TASK
;
3139 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
, ocp_data
);
3145 return rtl_enable(tp
);
3148 static void rtl_disable(struct r8152
*tp
)
3153 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
3154 rtl_drop_queued_tx(tp
);
3158 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
3159 ocp_data
&= ~RCR_ACPT_ALL
;
3160 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
3162 rtl_drop_queued_tx(tp
);
3164 for (i
= 0; i
< RTL8152_MAX_TX
; i
++)
3165 usb_kill_urb(tp
->tx_info
[i
].urb
);
3167 rxdy_gated_en(tp
, true);
3169 for (i
= 0; i
< 1000; i
++) {
3170 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3171 if ((ocp_data
& FIFO_EMPTY
) == FIFO_EMPTY
)
3173 usleep_range(1000, 2000);
3176 for (i
= 0; i
< 1000; i
++) {
3177 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
) & TCR0_TX_EMPTY
)
3179 usleep_range(1000, 2000);
3184 rtl8152_nic_reset(tp
);
3187 static void r8152_power_cut_en(struct r8152
*tp
, bool enable
)
3191 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_UPS_CTRL
);
3193 ocp_data
|= POWER_CUT
;
3195 ocp_data
&= ~POWER_CUT
;
3196 ocp_write_word(tp
, MCU_TYPE_USB
, USB_UPS_CTRL
, ocp_data
);
3198 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_PM_CTRL_STATUS
);
3199 ocp_data
&= ~RESUME_INDICATE
;
3200 ocp_write_word(tp
, MCU_TYPE_USB
, USB_PM_CTRL_STATUS
, ocp_data
);
3203 static void rtl_rx_vlan_en(struct r8152
*tp
, bool enable
)
3207 switch (tp
->version
) {
3218 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CPCR
);
3220 ocp_data
|= CPCR_RX_VLAN
;
3222 ocp_data
&= ~CPCR_RX_VLAN
;
3223 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CPCR
, ocp_data
);
3233 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_RCR1
);
3235 ocp_data
|= OUTER_VLAN
| INNER_VLAN
;
3237 ocp_data
&= ~(OUTER_VLAN
| INNER_VLAN
);
3238 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RCR1
, ocp_data
);
3243 static int rtl8152_set_features(struct net_device
*dev
,
3244 netdev_features_t features
)
3246 netdev_features_t changed
= features
^ dev
->features
;
3247 struct r8152
*tp
= netdev_priv(dev
);
3250 ret
= usb_autopm_get_interface(tp
->intf
);
3254 mutex_lock(&tp
->control
);
3256 if (changed
& NETIF_F_HW_VLAN_CTAG_RX
) {
3257 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
3258 rtl_rx_vlan_en(tp
, true);
3260 rtl_rx_vlan_en(tp
, false);
3263 mutex_unlock(&tp
->control
);
3265 usb_autopm_put_interface(tp
->intf
);
3271 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3273 static u32
__rtl_get_wol(struct r8152
*tp
)
3278 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
3279 if (ocp_data
& LINK_ON_WAKE_EN
)
3280 wolopts
|= WAKE_PHY
;
3282 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG5
);
3283 if (ocp_data
& UWF_EN
)
3284 wolopts
|= WAKE_UCAST
;
3285 if (ocp_data
& BWF_EN
)
3286 wolopts
|= WAKE_BCAST
;
3287 if (ocp_data
& MWF_EN
)
3288 wolopts
|= WAKE_MCAST
;
3290 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CFG_WOL
);
3291 if (ocp_data
& MAGIC_EN
)
3292 wolopts
|= WAKE_MAGIC
;
3297 static void __rtl_set_wol(struct r8152
*tp
, u32 wolopts
)
3301 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
3303 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
3304 ocp_data
&= ~LINK_ON_WAKE_EN
;
3305 if (wolopts
& WAKE_PHY
)
3306 ocp_data
|= LINK_ON_WAKE_EN
;
3307 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
, ocp_data
);
3309 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG5
);
3310 ocp_data
&= ~(UWF_EN
| BWF_EN
| MWF_EN
);
3311 if (wolopts
& WAKE_UCAST
)
3313 if (wolopts
& WAKE_BCAST
)
3315 if (wolopts
& WAKE_MCAST
)
3317 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG5
, ocp_data
);
3319 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
3321 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CFG_WOL
);
3322 ocp_data
&= ~MAGIC_EN
;
3323 if (wolopts
& WAKE_MAGIC
)
3324 ocp_data
|= MAGIC_EN
;
3325 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CFG_WOL
, ocp_data
);
3327 if (wolopts
& WAKE_ANY
)
3328 device_set_wakeup_enable(&tp
->udev
->dev
, true);
3330 device_set_wakeup_enable(&tp
->udev
->dev
, false);
3333 static void r8153_mac_clk_speed_down(struct r8152
*tp
, bool enable
)
3335 u32 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
);
3337 /* MAC clock speed down */
3339 ocp_data
|= MAC_CLK_SPDWN_EN
;
3341 ocp_data
&= ~MAC_CLK_SPDWN_EN
;
3343 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
, ocp_data
);
3346 static void r8156_mac_clk_spd(struct r8152
*tp
, bool enable
)
3350 /* MAC clock speed down */
3352 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3353 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL
,
3356 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
);
3357 ocp_data
&= ~EEE_SPDWN_RATIO_MASK
;
3358 ocp_data
|= MAC_CLK_SPDWN_EN
| 0x03; /* eee_spdwn_ratio */
3359 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
, ocp_data
);
3361 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
);
3362 ocp_data
&= ~MAC_CLK_SPDWN_EN
;
3363 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
, ocp_data
);
3367 static void r8153_u1u2en(struct r8152
*tp
, bool enable
)
3372 memset(u1u2
, 0xff, sizeof(u1u2
));
3374 memset(u1u2
, 0x00, sizeof(u1u2
));
3376 usb_ocp_write(tp
, USB_TOLERANCE
, BYTE_EN_SIX_BYTES
, sizeof(u1u2
), u1u2
);
3379 static void r8153b_u1u2en(struct r8152
*tp
, bool enable
)
3383 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_LPM_CONFIG
);
3385 ocp_data
|= LPM_U1U2_EN
;
3387 ocp_data
&= ~LPM_U1U2_EN
;
3389 ocp_write_word(tp
, MCU_TYPE_USB
, USB_LPM_CONFIG
, ocp_data
);
3392 static void r8153_u2p3en(struct r8152
*tp
, bool enable
)
3396 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_U2P3_CTRL
);
3398 ocp_data
|= U2P3_ENABLE
;
3400 ocp_data
&= ~U2P3_ENABLE
;
3401 ocp_write_word(tp
, MCU_TYPE_USB
, USB_U2P3_CTRL
, ocp_data
);
3404 static void r8153b_ups_flags(struct r8152
*tp
)
3408 if (tp
->ups_info
.green
)
3409 ups_flags
|= UPS_FLAGS_EN_GREEN
;
3411 if (tp
->ups_info
.aldps
)
3412 ups_flags
|= UPS_FLAGS_EN_ALDPS
;
3414 if (tp
->ups_info
.eee
)
3415 ups_flags
|= UPS_FLAGS_EN_EEE
;
3417 if (tp
->ups_info
.flow_control
)
3418 ups_flags
|= UPS_FLAGS_EN_FLOW_CTR
;
3420 if (tp
->ups_info
.eee_ckdiv
)
3421 ups_flags
|= UPS_FLAGS_EN_EEE_CKDIV
;
3423 if (tp
->ups_info
.eee_cmod_lv
)
3424 ups_flags
|= UPS_FLAGS_EEE_CMOD_LV_EN
;
3426 if (tp
->ups_info
.r_tune
)
3427 ups_flags
|= UPS_FLAGS_R_TUNE
;
3429 if (tp
->ups_info
._10m_ckdiv
)
3430 ups_flags
|= UPS_FLAGS_EN_10M_CKDIV
;
3432 if (tp
->ups_info
.eee_plloff_100
)
3433 ups_flags
|= UPS_FLAGS_EEE_PLLOFF_100
;
3435 if (tp
->ups_info
.eee_plloff_giga
)
3436 ups_flags
|= UPS_FLAGS_EEE_PLLOFF_GIGA
;
3438 if (tp
->ups_info
._250m_ckdiv
)
3439 ups_flags
|= UPS_FLAGS_250M_CKDIV
;
3441 if (tp
->ups_info
.ctap_short_off
)
3442 ups_flags
|= UPS_FLAGS_CTAP_SHORT_DIS
;
3444 switch (tp
->ups_info
.speed_duplex
) {
3446 ups_flags
|= ups_flags_speed(1);
3449 ups_flags
|= ups_flags_speed(2);
3451 case NWAY_100M_HALF
:
3452 ups_flags
|= ups_flags_speed(3);
3454 case NWAY_100M_FULL
:
3455 ups_flags
|= ups_flags_speed(4);
3457 case NWAY_1000M_FULL
:
3458 ups_flags
|= ups_flags_speed(5);
3460 case FORCE_10M_HALF
:
3461 ups_flags
|= ups_flags_speed(6);
3463 case FORCE_10M_FULL
:
3464 ups_flags
|= ups_flags_speed(7);
3466 case FORCE_100M_HALF
:
3467 ups_flags
|= ups_flags_speed(8);
3469 case FORCE_100M_FULL
:
3470 ups_flags
|= ups_flags_speed(9);
3476 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_UPS_FLAGS
, ups_flags
);
3479 static void r8156_ups_flags(struct r8152
*tp
)
3483 if (tp
->ups_info
.green
)
3484 ups_flags
|= UPS_FLAGS_EN_GREEN
;
3486 if (tp
->ups_info
.aldps
)
3487 ups_flags
|= UPS_FLAGS_EN_ALDPS
;
3489 if (tp
->ups_info
.eee
)
3490 ups_flags
|= UPS_FLAGS_EN_EEE
;
3492 if (tp
->ups_info
.flow_control
)
3493 ups_flags
|= UPS_FLAGS_EN_FLOW_CTR
;
3495 if (tp
->ups_info
.eee_ckdiv
)
3496 ups_flags
|= UPS_FLAGS_EN_EEE_CKDIV
;
3498 if (tp
->ups_info
._10m_ckdiv
)
3499 ups_flags
|= UPS_FLAGS_EN_10M_CKDIV
;
3501 if (tp
->ups_info
.eee_plloff_100
)
3502 ups_flags
|= UPS_FLAGS_EEE_PLLOFF_100
;
3504 if (tp
->ups_info
.eee_plloff_giga
)
3505 ups_flags
|= UPS_FLAGS_EEE_PLLOFF_GIGA
;
3507 if (tp
->ups_info
._250m_ckdiv
)
3508 ups_flags
|= UPS_FLAGS_250M_CKDIV
;
3510 switch (tp
->ups_info
.speed_duplex
) {
3511 case FORCE_10M_HALF
:
3512 ups_flags
|= ups_flags_speed(0);
3514 case FORCE_10M_FULL
:
3515 ups_flags
|= ups_flags_speed(1);
3517 case FORCE_100M_HALF
:
3518 ups_flags
|= ups_flags_speed(2);
3520 case FORCE_100M_FULL
:
3521 ups_flags
|= ups_flags_speed(3);
3524 ups_flags
|= ups_flags_speed(4);
3527 ups_flags
|= ups_flags_speed(5);
3529 case NWAY_100M_HALF
:
3530 ups_flags
|= ups_flags_speed(6);
3532 case NWAY_100M_FULL
:
3533 ups_flags
|= ups_flags_speed(7);
3535 case NWAY_1000M_FULL
:
3536 ups_flags
|= ups_flags_speed(8);
3538 case NWAY_2500M_FULL
:
3539 ups_flags
|= ups_flags_speed(9);
3545 switch (tp
->ups_info
.lite_mode
) {
3547 ups_flags
|= 0 << 5;
3550 ups_flags
|= 2 << 5;
3554 ups_flags
|= 1 << 5;
3558 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_UPS_FLAGS
, ups_flags
);
3561 static void rtl_green_en(struct r8152
*tp
, bool enable
)
3565 data
= sram_read(tp
, SRAM_GREEN_CFG
);
3567 data
|= GREEN_ETH_EN
;
3569 data
&= ~GREEN_ETH_EN
;
3570 sram_write(tp
, SRAM_GREEN_CFG
, data
);
3572 tp
->ups_info
.green
= enable
;
3575 static void r8153b_green_en(struct r8152
*tp
, bool enable
)
3578 sram_write(tp
, 0x8045, 0); /* 10M abiq&ldvbias */
3579 sram_write(tp
, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3580 sram_write(tp
, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3582 sram_write(tp
, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3583 sram_write(tp
, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3584 sram_write(tp
, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3587 rtl_green_en(tp
, true);
3590 static u16
r8153_phy_status(struct r8152
*tp
, u16 desired
)
3595 for (i
= 0; i
< 500; i
++) {
3596 data
= ocp_reg_read(tp
, OCP_PHY_STATUS
);
3597 data
&= PHY_STAT_MASK
;
3599 if (data
== desired
)
3601 } else if (data
== PHY_STAT_LAN_ON
|| data
== PHY_STAT_PWRDN
||
3602 data
== PHY_STAT_EXT_INIT
) {
3607 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
3614 static void r8153b_ups_en(struct r8152
*tp
, bool enable
)
3616 u32 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
);
3619 r8153b_ups_flags(tp
);
3621 ocp_data
|= UPS_EN
| USP_PREWAKE
| PHASE2_EN
;
3622 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
3624 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
);
3625 ocp_data
|= UPS_FORCE_PWR_DOWN
;
3626 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
, ocp_data
);
3628 ocp_data
&= ~(UPS_EN
| USP_PREWAKE
);
3629 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
3631 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
);
3632 ocp_data
&= ~UPS_FORCE_PWR_DOWN
;
3633 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
, ocp_data
);
3635 if (ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
) & PCUT_STATUS
) {
3638 for (i
= 0; i
< 500; i
++) {
3639 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
3645 tp
->rtl_ops
.hw_phy_cfg(tp
);
3647 rtl8152_set_speed(tp
, tp
->autoneg
, tp
->speed
,
3648 tp
->duplex
, tp
->advertising
);
3653 static void r8153c_ups_en(struct r8152
*tp
, bool enable
)
3655 u32 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
);
3658 r8153b_ups_flags(tp
);
3660 ocp_data
|= UPS_EN
| USP_PREWAKE
| PHASE2_EN
;
3661 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
3663 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
);
3664 ocp_data
|= UPS_FORCE_PWR_DOWN
;
3665 ocp_data
&= ~BIT(7);
3666 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
, ocp_data
);
3668 ocp_data
&= ~(UPS_EN
| USP_PREWAKE
);
3669 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
3671 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
);
3672 ocp_data
&= ~UPS_FORCE_PWR_DOWN
;
3673 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
, ocp_data
);
3675 if (ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
) & PCUT_STATUS
) {
3678 for (i
= 0; i
< 500; i
++) {
3679 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
3685 tp
->rtl_ops
.hw_phy_cfg(tp
);
3687 rtl8152_set_speed(tp
, tp
->autoneg
, tp
->speed
,
3688 tp
->duplex
, tp
->advertising
);
3691 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
3693 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
3695 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
, ocp_data
);
3697 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
3701 static void r8156_ups_en(struct r8152
*tp
, bool enable
)
3703 u32 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
);
3706 r8156_ups_flags(tp
);
3708 ocp_data
|= UPS_EN
| USP_PREWAKE
| PHASE2_EN
;
3709 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
3711 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
);
3712 ocp_data
|= UPS_FORCE_PWR_DOWN
;
3713 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
, ocp_data
);
3715 switch (tp
->version
) {
3718 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_UPHY_XTAL
);
3719 ocp_data
&= ~OOBS_POLLING
;
3720 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_UPHY_XTAL
, ocp_data
);
3726 ocp_data
&= ~(UPS_EN
| USP_PREWAKE
);
3727 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
3729 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
);
3730 ocp_data
&= ~UPS_FORCE_PWR_DOWN
;
3731 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
, ocp_data
);
3733 if (ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
) & PCUT_STATUS
) {
3734 tp
->rtl_ops
.hw_phy_cfg(tp
);
3736 rtl8152_set_speed(tp
, tp
->autoneg
, tp
->speed
,
3737 tp
->duplex
, tp
->advertising
);
3742 static void r8153_power_cut_en(struct r8152
*tp
, bool enable
)
3746 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_POWER_CUT
);
3748 ocp_data
|= PWR_EN
| PHASE2_EN
;
3750 ocp_data
&= ~(PWR_EN
| PHASE2_EN
);
3751 ocp_write_word(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
3753 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
3754 ocp_data
&= ~PCUT_STATUS
;
3755 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MISC_0
, ocp_data
);
3758 static void r8153b_power_cut_en(struct r8152
*tp
, bool enable
)
3762 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_POWER_CUT
);
3764 ocp_data
|= PWR_EN
| PHASE2_EN
;
3766 ocp_data
&= ~PWR_EN
;
3767 ocp_write_word(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
3769 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
3770 ocp_data
&= ~PCUT_STATUS
;
3771 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MISC_0
, ocp_data
);
3774 static void r8153_queue_wake(struct r8152
*tp
, bool enable
)
3778 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_INDICATE_FALG
);
3780 ocp_data
|= UPCOMING_RUNTIME_D3
;
3782 ocp_data
&= ~UPCOMING_RUNTIME_D3
;
3783 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_INDICATE_FALG
, ocp_data
);
3785 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_SUSPEND_FLAG
);
3786 ocp_data
&= ~LINK_CHG_EVENT
;
3787 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_SUSPEND_FLAG
, ocp_data
);
3789 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
);
3790 ocp_data
&= ~LINK_CHANGE_FLAG
;
3791 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
, ocp_data
);
3794 static bool rtl_can_wakeup(struct r8152
*tp
)
3796 struct usb_device
*udev
= tp
->udev
;
3798 return (udev
->actconfig
->desc
.bmAttributes
& USB_CONFIG_ATT_WAKEUP
);
3801 static void rtl_runtime_suspend_enable(struct r8152
*tp
, bool enable
)
3806 __rtl_set_wol(tp
, WAKE_ANY
);
3808 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
3810 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
3811 ocp_data
|= LINK_OFF_WAKE_EN
;
3812 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
, ocp_data
);
3814 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
3818 __rtl_set_wol(tp
, tp
->saved_wolopts
);
3820 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
3822 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
3823 ocp_data
&= ~LINK_OFF_WAKE_EN
;
3824 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
, ocp_data
);
3826 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
3830 static void rtl8153_runtime_enable(struct r8152
*tp
, bool enable
)
3833 r8153_u1u2en(tp
, false);
3834 r8153_u2p3en(tp
, false);
3835 rtl_runtime_suspend_enable(tp
, true);
3837 rtl_runtime_suspend_enable(tp
, false);
3839 switch (tp
->version
) {
3846 r8153_u2p3en(tp
, true);
3850 r8153_u1u2en(tp
, true);
3854 static void rtl8153b_runtime_enable(struct r8152
*tp
, bool enable
)
3857 r8153_queue_wake(tp
, true);
3858 r8153b_u1u2en(tp
, false);
3859 r8153_u2p3en(tp
, false);
3860 rtl_runtime_suspend_enable(tp
, true);
3861 r8153b_ups_en(tp
, true);
3863 r8153b_ups_en(tp
, false);
3864 r8153_queue_wake(tp
, false);
3865 rtl_runtime_suspend_enable(tp
, false);
3866 if (tp
->udev
->speed
>= USB_SPEED_SUPER
)
3867 r8153b_u1u2en(tp
, true);
3871 static void rtl8153c_runtime_enable(struct r8152
*tp
, bool enable
)
3874 r8153_queue_wake(tp
, true);
3875 r8153b_u1u2en(tp
, false);
3876 r8153_u2p3en(tp
, false);
3877 rtl_runtime_suspend_enable(tp
, true);
3878 r8153c_ups_en(tp
, true);
3880 r8153c_ups_en(tp
, false);
3881 r8153_queue_wake(tp
, false);
3882 rtl_runtime_suspend_enable(tp
, false);
3883 r8153b_u1u2en(tp
, true);
3887 static void rtl8156_runtime_enable(struct r8152
*tp
, bool enable
)
3890 r8153_queue_wake(tp
, true);
3891 r8153b_u1u2en(tp
, false);
3892 r8153_u2p3en(tp
, false);
3893 rtl_runtime_suspend_enable(tp
, true);
3895 r8153_queue_wake(tp
, false);
3896 rtl_runtime_suspend_enable(tp
, false);
3897 r8153_u2p3en(tp
, true);
3898 if (tp
->udev
->speed
>= USB_SPEED_SUPER
)
3899 r8153b_u1u2en(tp
, true);
3903 static void r8153_teredo_off(struct r8152
*tp
)
3907 switch (tp
->version
) {
3915 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
);
3916 ocp_data
&= ~(TEREDO_SEL
| TEREDO_RS_EVENT_MASK
|
3918 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
, ocp_data
);
3931 /* The bit 0 ~ 7 are relative with teredo settings. They are
3932 * W1C (write 1 to clear), so set all 1 to disable it.
3934 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
, 0xff);
3938 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_WDT6_CTRL
, WDT6_SET_MODE
);
3939 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_REALWOW_TIMER
, 0);
3940 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_TEREDO_TIMER
, 0);
3943 static void rtl_reset_bmu(struct r8152
*tp
)
3947 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_BMU_RESET
);
3948 ocp_data
&= ~(BMU_RESET_EP_IN
| BMU_RESET_EP_OUT
);
3949 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_BMU_RESET
, ocp_data
);
3950 ocp_data
|= BMU_RESET_EP_IN
| BMU_RESET_EP_OUT
;
3951 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_BMU_RESET
, ocp_data
);
3954 /* Clear the bp to stop the firmware before loading a new one */
3955 static void rtl_clear_bp(struct r8152
*tp
, u16 type
)
3957 switch (tp
->version
) {
3966 ocp_write_byte(tp
, type
, PLA_BP_EN
, 0);
3969 ocp_write_word(tp
, type
, USB_BP2_EN
, 0);
3971 ocp_write_word(tp
, type
, USB_BP_8
, 0);
3972 ocp_write_word(tp
, type
, USB_BP_9
, 0);
3973 ocp_write_word(tp
, type
, USB_BP_10
, 0);
3974 ocp_write_word(tp
, type
, USB_BP_11
, 0);
3975 ocp_write_word(tp
, type
, USB_BP_12
, 0);
3976 ocp_write_word(tp
, type
, USB_BP_13
, 0);
3977 ocp_write_word(tp
, type
, USB_BP_14
, 0);
3978 ocp_write_word(tp
, type
, USB_BP_15
, 0);
3988 if (type
== MCU_TYPE_USB
) {
3989 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP2_EN
, 0);
3991 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_8
, 0);
3992 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_9
, 0);
3993 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_10
, 0);
3994 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_11
, 0);
3995 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_12
, 0);
3996 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_13
, 0);
3997 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_14
, 0);
3998 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_15
, 0);
4000 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_BP_EN
, 0);
4005 ocp_write_word(tp
, type
, PLA_BP_0
, 0);
4006 ocp_write_word(tp
, type
, PLA_BP_1
, 0);
4007 ocp_write_word(tp
, type
, PLA_BP_2
, 0);
4008 ocp_write_word(tp
, type
, PLA_BP_3
, 0);
4009 ocp_write_word(tp
, type
, PLA_BP_4
, 0);
4010 ocp_write_word(tp
, type
, PLA_BP_5
, 0);
4011 ocp_write_word(tp
, type
, PLA_BP_6
, 0);
4012 ocp_write_word(tp
, type
, PLA_BP_7
, 0);
4014 /* wait 3 ms to make sure the firmware is stopped */
4015 usleep_range(3000, 6000);
4016 ocp_write_word(tp
, type
, PLA_BP_BA
, 0);
4019 static int rtl_phy_patch_request(struct r8152
*tp
, bool request
, bool wait
)
4024 data
= ocp_reg_read(tp
, OCP_PHY_PATCH_CMD
);
4026 data
|= PATCH_REQUEST
;
4029 data
&= ~PATCH_REQUEST
;
4030 check
= PATCH_READY
;
4032 ocp_reg_write(tp
, OCP_PHY_PATCH_CMD
, data
);
4034 for (i
= 0; wait
&& i
< 5000; i
++) {
4037 usleep_range(1000, 2000);
4038 ocp_data
= ocp_reg_read(tp
, OCP_PHY_PATCH_STAT
);
4039 if ((ocp_data
& PATCH_READY
) ^ check
)
4043 if (request
&& wait
&&
4044 !(ocp_reg_read(tp
, OCP_PHY_PATCH_STAT
) & PATCH_READY
)) {
4045 dev_err(&tp
->intf
->dev
, "PHY patch request fail\n");
4046 rtl_phy_patch_request(tp
, false, false);
4053 static void rtl_patch_key_set(struct r8152
*tp
, u16 key_addr
, u16 patch_key
)
4055 if (patch_key
&& key_addr
) {
4056 sram_write(tp
, key_addr
, patch_key
);
4057 sram_write(tp
, SRAM_PHY_LOCK
, PHY_PATCH_LOCK
);
4058 } else if (key_addr
) {
4061 sram_write(tp
, 0x0000, 0x0000);
4063 data
= ocp_reg_read(tp
, OCP_PHY_LOCK
);
4064 data
&= ~PATCH_LOCK
;
4065 ocp_reg_write(tp
, OCP_PHY_LOCK
, data
);
4067 sram_write(tp
, key_addr
, 0x0000);
4074 rtl_pre_ram_code(struct r8152
*tp
, u16 key_addr
, u16 patch_key
, bool wait
)
4076 if (rtl_phy_patch_request(tp
, true, wait
))
4079 rtl_patch_key_set(tp
, key_addr
, patch_key
);
4084 static int rtl_post_ram_code(struct r8152
*tp
, u16 key_addr
, bool wait
)
4086 rtl_patch_key_set(tp
, key_addr
, 0);
4088 rtl_phy_patch_request(tp
, false, wait
);
4090 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_OCP_GPHY_BASE
, tp
->ocp_base
);
4095 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152
*tp
, struct fw_phy_speed_up
*phy
)
4101 switch (tp
->version
) {
4122 fw_offset
= __le16_to_cpu(phy
->fw_offset
);
4123 length
= __le32_to_cpu(phy
->blk_hdr
.length
);
4124 if (fw_offset
< sizeof(*phy
) || length
<= fw_offset
) {
4125 dev_err(&tp
->intf
->dev
, "invalid fw_offset\n");
4129 length
-= fw_offset
;
4131 dev_err(&tp
->intf
->dev
, "invalid block length\n");
4135 if (__le16_to_cpu(phy
->fw_reg
) != 0x9A00) {
4136 dev_err(&tp
->intf
->dev
, "invalid register to load firmware\n");
4145 static bool rtl8152_is_fw_phy_ver_ok(struct r8152
*tp
, struct fw_phy_ver
*ver
)
4149 switch (tp
->version
) {
4160 if (__le32_to_cpu(ver
->blk_hdr
.length
) != sizeof(*ver
)) {
4161 dev_err(&tp
->intf
->dev
, "invalid block length\n");
4165 if (__le16_to_cpu(ver
->ver
.addr
) != SRAM_GPHY_FW_VER
) {
4166 dev_err(&tp
->intf
->dev
, "invalid phy ver addr\n");
4175 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152
*tp
, struct fw_phy_fixup
*fix
)
4179 switch (tp
->version
) {
4190 if (__le32_to_cpu(fix
->blk_hdr
.length
) != sizeof(*fix
)) {
4191 dev_err(&tp
->intf
->dev
, "invalid block length\n");
4195 if (__le16_to_cpu(fix
->setting
.addr
) != OCP_PHY_PATCH_CMD
||
4196 __le16_to_cpu(fix
->setting
.data
) != BIT(7)) {
4197 dev_err(&tp
->intf
->dev
, "invalid phy fixup\n");
4206 static bool rtl8152_is_fw_phy_union_ok(struct r8152
*tp
, struct fw_phy_union
*phy
)
4212 switch (tp
->version
) {
4223 fw_offset
= __le16_to_cpu(phy
->fw_offset
);
4224 length
= __le32_to_cpu(phy
->blk_hdr
.length
);
4225 if (fw_offset
< sizeof(*phy
) || length
<= fw_offset
) {
4226 dev_err(&tp
->intf
->dev
, "invalid fw_offset\n");
4230 length
-= fw_offset
;
4232 dev_err(&tp
->intf
->dev
, "invalid block length\n");
4236 if (phy
->pre_num
> 2) {
4237 dev_err(&tp
->intf
->dev
, "invalid pre_num %d\n", phy
->pre_num
);
4241 if (phy
->bp_num
> 8) {
4242 dev_err(&tp
->intf
->dev
, "invalid bp_num %d\n", phy
->bp_num
);
4251 static bool rtl8152_is_fw_phy_nc_ok(struct r8152
*tp
, struct fw_phy_nc
*phy
)
4254 u16 fw_offset
, fw_reg
, ba_reg
, patch_en_addr
, mode_reg
, bp_start
;
4257 switch (tp
->version
) {
4263 patch_en_addr
= 0xa01a;
4271 fw_offset
= __le16_to_cpu(phy
->fw_offset
);
4272 if (fw_offset
< sizeof(*phy
)) {
4273 dev_err(&tp
->intf
->dev
, "fw_offset too small\n");
4277 length
= __le32_to_cpu(phy
->blk_hdr
.length
);
4278 if (length
< fw_offset
) {
4279 dev_err(&tp
->intf
->dev
, "invalid fw_offset\n");
4283 length
-= __le16_to_cpu(phy
->fw_offset
);
4284 if (!length
|| (length
& 1)) {
4285 dev_err(&tp
->intf
->dev
, "invalid block length\n");
4289 if (__le16_to_cpu(phy
->fw_reg
) != fw_reg
) {
4290 dev_err(&tp
->intf
->dev
, "invalid register to load firmware\n");
4294 if (__le16_to_cpu(phy
->ba_reg
) != ba_reg
) {
4295 dev_err(&tp
->intf
->dev
, "invalid base address register\n");
4299 if (__le16_to_cpu(phy
->patch_en_addr
) != patch_en_addr
) {
4300 dev_err(&tp
->intf
->dev
,
4301 "invalid patch mode enabled register\n");
4305 if (__le16_to_cpu(phy
->mode_reg
) != mode_reg
) {
4306 dev_err(&tp
->intf
->dev
,
4307 "invalid register to switch the mode\n");
4311 if (__le16_to_cpu(phy
->bp_start
) != bp_start
) {
4312 dev_err(&tp
->intf
->dev
,
4313 "invalid start register of break point\n");
4317 if (__le16_to_cpu(phy
->bp_num
) > 4) {
4318 dev_err(&tp
->intf
->dev
, "invalid break point number\n");
4327 static bool rtl8152_is_fw_mac_ok(struct r8152
*tp
, struct fw_mac
*mac
)
4329 u16 fw_reg
, bp_ba_addr
, bp_en_addr
, bp_start
, fw_offset
;
4334 type
= __le32_to_cpu(mac
->blk_hdr
.type
);
4335 if (type
== RTL_FW_PLA
) {
4336 switch (tp
->version
) {
4341 bp_ba_addr
= PLA_BP_BA
;
4343 bp_start
= PLA_BP_0
;
4357 bp_ba_addr
= PLA_BP_BA
;
4358 bp_en_addr
= PLA_BP_EN
;
4359 bp_start
= PLA_BP_0
;
4364 bp_ba_addr
= PLA_BP_BA
;
4365 bp_en_addr
= USB_BP2_EN
;
4366 bp_start
= PLA_BP_0
;
4372 } else if (type
== RTL_FW_USB
) {
4373 switch (tp
->version
) {
4379 bp_ba_addr
= USB_BP_BA
;
4380 bp_en_addr
= USB_BP_EN
;
4381 bp_start
= USB_BP_0
;
4392 bp_ba_addr
= USB_BP_BA
;
4393 bp_en_addr
= USB_BP2_EN
;
4394 bp_start
= USB_BP_0
;
4407 fw_offset
= __le16_to_cpu(mac
->fw_offset
);
4408 if (fw_offset
< sizeof(*mac
)) {
4409 dev_err(&tp
->intf
->dev
, "fw_offset too small\n");
4413 length
= __le32_to_cpu(mac
->blk_hdr
.length
);
4414 if (length
< fw_offset
) {
4415 dev_err(&tp
->intf
->dev
, "invalid fw_offset\n");
4419 length
-= fw_offset
;
4420 if (length
< 4 || (length
& 3)) {
4421 dev_err(&tp
->intf
->dev
, "invalid block length\n");
4425 if (__le16_to_cpu(mac
->fw_reg
) != fw_reg
) {
4426 dev_err(&tp
->intf
->dev
, "invalid register to load firmware\n");
4430 if (__le16_to_cpu(mac
->bp_ba_addr
) != bp_ba_addr
) {
4431 dev_err(&tp
->intf
->dev
, "invalid base address register\n");
4435 if (__le16_to_cpu(mac
->bp_en_addr
) != bp_en_addr
) {
4436 dev_err(&tp
->intf
->dev
, "invalid enabled mask register\n");
4440 if (__le16_to_cpu(mac
->bp_start
) != bp_start
) {
4441 dev_err(&tp
->intf
->dev
,
4442 "invalid start register of break point\n");
4446 if (__le16_to_cpu(mac
->bp_num
) > max_bp
) {
4447 dev_err(&tp
->intf
->dev
, "invalid break point number\n");
4451 for (i
= __le16_to_cpu(mac
->bp_num
); i
< max_bp
; i
++) {
4453 dev_err(&tp
->intf
->dev
, "unused bp%u is not zero\n", i
);
4463 /* Verify the checksum for the firmware file. It is calculated from the version
4464 * field to the end of the file. Compare the result with the checksum field to
4465 * make sure the file is correct.
4467 static long rtl8152_fw_verify_checksum(struct r8152
*tp
,
4468 struct fw_header
*fw_hdr
, size_t size
)
4470 unsigned char checksum
[sizeof(fw_hdr
->checksum
)];
4471 struct crypto_shash
*alg
;
4472 struct shash_desc
*sdesc
;
4476 alg
= crypto_alloc_shash("sha256", 0, 0);
4482 if (crypto_shash_digestsize(alg
) != sizeof(fw_hdr
->checksum
)) {
4484 dev_err(&tp
->intf
->dev
, "digestsize incorrect (%u)\n",
4485 crypto_shash_digestsize(alg
));
4489 len
= sizeof(*sdesc
) + crypto_shash_descsize(alg
);
4490 sdesc
= kmalloc(len
, GFP_KERNEL
);
4497 len
= size
- sizeof(fw_hdr
->checksum
);
4498 rc
= crypto_shash_digest(sdesc
, fw_hdr
->version
, len
, checksum
);
4503 if (memcmp(fw_hdr
->checksum
, checksum
, sizeof(fw_hdr
->checksum
))) {
4504 dev_err(&tp
->intf
->dev
, "checksum fail\n");
4509 crypto_free_shash(alg
);
4514 static long rtl8152_check_firmware(struct r8152
*tp
, struct rtl_fw
*rtl_fw
)
4516 const struct firmware
*fw
= rtl_fw
->fw
;
4517 struct fw_header
*fw_hdr
= (struct fw_header
*)fw
->data
;
4518 unsigned long fw_flags
= 0;
4522 if (fw
->size
< sizeof(*fw_hdr
)) {
4523 dev_err(&tp
->intf
->dev
, "file too small\n");
4527 ret
= rtl8152_fw_verify_checksum(tp
, fw_hdr
, fw
->size
);
4533 for (i
= sizeof(*fw_hdr
); i
< fw
->size
;) {
4534 struct fw_block
*block
= (struct fw_block
*)&fw
->data
[i
];
4537 if ((i
+ sizeof(*block
)) > fw
->size
)
4540 type
= __le32_to_cpu(block
->type
);
4543 if (__le32_to_cpu(block
->length
) != sizeof(*block
))
4547 if (test_bit(FW_FLAGS_PLA
, &fw_flags
)) {
4548 dev_err(&tp
->intf
->dev
,
4549 "multiple PLA firmware encountered");
4553 if (!rtl8152_is_fw_mac_ok(tp
, (struct fw_mac
*)block
)) {
4554 dev_err(&tp
->intf
->dev
,
4555 "check PLA firmware failed\n");
4558 __set_bit(FW_FLAGS_PLA
, &fw_flags
);
4561 if (test_bit(FW_FLAGS_USB
, &fw_flags
)) {
4562 dev_err(&tp
->intf
->dev
,
4563 "multiple USB firmware encountered");
4567 if (!rtl8152_is_fw_mac_ok(tp
, (struct fw_mac
*)block
)) {
4568 dev_err(&tp
->intf
->dev
,
4569 "check USB firmware failed\n");
4572 __set_bit(FW_FLAGS_USB
, &fw_flags
);
4574 case RTL_FW_PHY_START
:
4575 if (test_bit(FW_FLAGS_START
, &fw_flags
) ||
4576 test_bit(FW_FLAGS_NC
, &fw_flags
) ||
4577 test_bit(FW_FLAGS_NC1
, &fw_flags
) ||
4578 test_bit(FW_FLAGS_NC2
, &fw_flags
) ||
4579 test_bit(FW_FLAGS_UC2
, &fw_flags
) ||
4580 test_bit(FW_FLAGS_UC
, &fw_flags
) ||
4581 test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4582 dev_err(&tp
->intf
->dev
,
4583 "check PHY_START fail\n");
4587 if (__le32_to_cpu(block
->length
) != sizeof(struct fw_phy_patch_key
)) {
4588 dev_err(&tp
->intf
->dev
,
4589 "Invalid length for PHY_START\n");
4592 __set_bit(FW_FLAGS_START
, &fw_flags
);
4594 case RTL_FW_PHY_STOP
:
4595 if (test_bit(FW_FLAGS_STOP
, &fw_flags
) ||
4596 !test_bit(FW_FLAGS_START
, &fw_flags
)) {
4597 dev_err(&tp
->intf
->dev
,
4598 "Check PHY_STOP fail\n");
4602 if (__le32_to_cpu(block
->length
) != sizeof(*block
)) {
4603 dev_err(&tp
->intf
->dev
,
4604 "Invalid length for PHY_STOP\n");
4607 __set_bit(FW_FLAGS_STOP
, &fw_flags
);
4610 if (!test_bit(FW_FLAGS_START
, &fw_flags
) ||
4611 test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4612 dev_err(&tp
->intf
->dev
,
4613 "check PHY_NC fail\n");
4617 if (test_bit(FW_FLAGS_NC
, &fw_flags
)) {
4618 dev_err(&tp
->intf
->dev
,
4619 "multiple PHY NC encountered\n");
4623 if (!rtl8152_is_fw_phy_nc_ok(tp
, (struct fw_phy_nc
*)block
)) {
4624 dev_err(&tp
->intf
->dev
,
4625 "check PHY NC firmware failed\n");
4628 __set_bit(FW_FLAGS_NC
, &fw_flags
);
4630 case RTL_FW_PHY_UNION_NC
:
4631 if (!test_bit(FW_FLAGS_START
, &fw_flags
) ||
4632 test_bit(FW_FLAGS_NC1
, &fw_flags
) ||
4633 test_bit(FW_FLAGS_NC2
, &fw_flags
) ||
4634 test_bit(FW_FLAGS_UC2
, &fw_flags
) ||
4635 test_bit(FW_FLAGS_UC
, &fw_flags
) ||
4636 test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4637 dev_err(&tp
->intf
->dev
, "PHY_UNION_NC out of order\n");
4641 if (test_bit(FW_FLAGS_NC
, &fw_flags
)) {
4642 dev_err(&tp
->intf
->dev
, "multiple PHY_UNION_NC encountered\n");
4646 if (!rtl8152_is_fw_phy_union_ok(tp
, (struct fw_phy_union
*)block
)) {
4647 dev_err(&tp
->intf
->dev
, "check PHY_UNION_NC failed\n");
4650 __set_bit(FW_FLAGS_NC
, &fw_flags
);
4652 case RTL_FW_PHY_UNION_NC1
:
4653 if (!test_bit(FW_FLAGS_START
, &fw_flags
) ||
4654 test_bit(FW_FLAGS_NC2
, &fw_flags
) ||
4655 test_bit(FW_FLAGS_UC2
, &fw_flags
) ||
4656 test_bit(FW_FLAGS_UC
, &fw_flags
) ||
4657 test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4658 dev_err(&tp
->intf
->dev
, "PHY_UNION_NC1 out of order\n");
4662 if (test_bit(FW_FLAGS_NC1
, &fw_flags
)) {
4663 dev_err(&tp
->intf
->dev
, "multiple PHY NC1 encountered\n");
4667 if (!rtl8152_is_fw_phy_union_ok(tp
, (struct fw_phy_union
*)block
)) {
4668 dev_err(&tp
->intf
->dev
, "check PHY_UNION_NC1 failed\n");
4671 __set_bit(FW_FLAGS_NC1
, &fw_flags
);
4673 case RTL_FW_PHY_UNION_NC2
:
4674 if (!test_bit(FW_FLAGS_START
, &fw_flags
) ||
4675 test_bit(FW_FLAGS_UC2
, &fw_flags
) ||
4676 test_bit(FW_FLAGS_UC
, &fw_flags
) ||
4677 test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4678 dev_err(&tp
->intf
->dev
, "PHY_UNION_NC2 out of order\n");
4682 if (test_bit(FW_FLAGS_NC2
, &fw_flags
)) {
4683 dev_err(&tp
->intf
->dev
, "multiple PHY NC2 encountered\n");
4687 if (!rtl8152_is_fw_phy_union_ok(tp
, (struct fw_phy_union
*)block
)) {
4688 dev_err(&tp
->intf
->dev
, "check PHY_UNION_NC2 failed\n");
4691 __set_bit(FW_FLAGS_NC2
, &fw_flags
);
4693 case RTL_FW_PHY_UNION_UC2
:
4694 if (!test_bit(FW_FLAGS_START
, &fw_flags
) ||
4695 test_bit(FW_FLAGS_UC
, &fw_flags
) ||
4696 test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4697 dev_err(&tp
->intf
->dev
, "PHY_UNION_UC2 out of order\n");
4701 if (test_bit(FW_FLAGS_UC2
, &fw_flags
)) {
4702 dev_err(&tp
->intf
->dev
, "multiple PHY UC2 encountered\n");
4706 if (!rtl8152_is_fw_phy_union_ok(tp
, (struct fw_phy_union
*)block
)) {
4707 dev_err(&tp
->intf
->dev
, "check PHY_UNION_UC2 failed\n");
4710 __set_bit(FW_FLAGS_UC2
, &fw_flags
);
4712 case RTL_FW_PHY_UNION_UC
:
4713 if (!test_bit(FW_FLAGS_START
, &fw_flags
) ||
4714 test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4715 dev_err(&tp
->intf
->dev
, "PHY_UNION_UC out of order\n");
4719 if (test_bit(FW_FLAGS_UC
, &fw_flags
)) {
4720 dev_err(&tp
->intf
->dev
, "multiple PHY UC encountered\n");
4724 if (!rtl8152_is_fw_phy_union_ok(tp
, (struct fw_phy_union
*)block
)) {
4725 dev_err(&tp
->intf
->dev
, "check PHY_UNION_UC failed\n");
4728 __set_bit(FW_FLAGS_UC
, &fw_flags
);
4730 case RTL_FW_PHY_UNION_MISC
:
4731 if (!rtl8152_is_fw_phy_union_ok(tp
, (struct fw_phy_union
*)block
)) {
4732 dev_err(&tp
->intf
->dev
, "check RTL_FW_PHY_UNION_MISC failed\n");
4736 case RTL_FW_PHY_FIXUP
:
4737 if (!rtl8152_is_fw_phy_fixup_ok(tp
, (struct fw_phy_fixup
*)block
)) {
4738 dev_err(&tp
->intf
->dev
, "check PHY fixup failed\n");
4742 case RTL_FW_PHY_SPEED_UP
:
4743 if (test_bit(FW_FLAGS_SPEED_UP
, &fw_flags
)) {
4744 dev_err(&tp
->intf
->dev
, "multiple PHY firmware encountered");
4748 if (!rtl8152_is_fw_phy_speed_up_ok(tp
, (struct fw_phy_speed_up
*)block
)) {
4749 dev_err(&tp
->intf
->dev
, "check PHY speed up failed\n");
4752 __set_bit(FW_FLAGS_SPEED_UP
, &fw_flags
);
4754 case RTL_FW_PHY_VER
:
4755 if (test_bit(FW_FLAGS_START
, &fw_flags
) ||
4756 test_bit(FW_FLAGS_NC
, &fw_flags
) ||
4757 test_bit(FW_FLAGS_NC1
, &fw_flags
) ||
4758 test_bit(FW_FLAGS_NC2
, &fw_flags
) ||
4759 test_bit(FW_FLAGS_UC2
, &fw_flags
) ||
4760 test_bit(FW_FLAGS_UC
, &fw_flags
) ||
4761 test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4762 dev_err(&tp
->intf
->dev
, "Invalid order to set PHY version\n");
4766 if (test_bit(FW_FLAGS_VER
, &fw_flags
)) {
4767 dev_err(&tp
->intf
->dev
, "multiple PHY version encountered");
4771 if (!rtl8152_is_fw_phy_ver_ok(tp
, (struct fw_phy_ver
*)block
)) {
4772 dev_err(&tp
->intf
->dev
, "check PHY version failed\n");
4775 __set_bit(FW_FLAGS_VER
, &fw_flags
);
4778 dev_warn(&tp
->intf
->dev
, "Unknown type %u is found\n",
4784 i
+= ALIGN(__le32_to_cpu(block
->length
), 8);
4788 if (test_bit(FW_FLAGS_START
, &fw_flags
) && !test_bit(FW_FLAGS_STOP
, &fw_flags
)) {
4789 dev_err(&tp
->intf
->dev
, "without PHY_STOP\n");
4798 static void rtl_ram_code_speed_up(struct r8152
*tp
, struct fw_phy_speed_up
*phy
, bool wait
)
4803 if (sram_read(tp
, SRAM_GPHY_FW_VER
) >= __le16_to_cpu(phy
->version
)) {
4804 dev_dbg(&tp
->intf
->dev
, "PHY firmware has been the newest\n");
4808 len
= __le32_to_cpu(phy
->blk_hdr
.length
);
4809 len
-= __le16_to_cpu(phy
->fw_offset
);
4810 data
= (u8
*)phy
+ __le16_to_cpu(phy
->fw_offset
);
4812 if (rtl_phy_patch_request(tp
, true, wait
))
4824 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_GPHY_CTRL
);
4825 ocp_data
|= GPHY_PATCH_DONE
| BACKUP_RESTRORE
;
4826 ocp_write_word(tp
, MCU_TYPE_USB
, USB_GPHY_CTRL
, ocp_data
);
4828 generic_ocp_write(tp
, __le16_to_cpu(phy
->fw_reg
), 0xff, size
, data
, MCU_TYPE_USB
);
4833 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_POL_GPIO_CTRL
);
4834 ocp_data
|= POL_GPHY_PATCH
;
4835 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_POL_GPIO_CTRL
, ocp_data
);
4837 for (i
= 0; i
< 1000; i
++) {
4838 if (!(ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_POL_GPIO_CTRL
) & POL_GPHY_PATCH
))
4843 dev_err(&tp
->intf
->dev
, "ram code speedup mode timeout\n");
4848 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_OCP_GPHY_BASE
, tp
->ocp_base
);
4849 rtl_phy_patch_request(tp
, false, wait
);
4851 if (sram_read(tp
, SRAM_GPHY_FW_VER
) == __le16_to_cpu(phy
->version
))
4852 dev_dbg(&tp
->intf
->dev
, "successfully applied %s\n", phy
->info
);
4854 dev_err(&tp
->intf
->dev
, "ram code speedup mode fail\n");
4857 static int rtl8152_fw_phy_ver(struct r8152
*tp
, struct fw_phy_ver
*phy_ver
)
4861 ver_addr
= __le16_to_cpu(phy_ver
->ver
.addr
);
4862 ver
= __le16_to_cpu(phy_ver
->ver
.data
);
4864 if (sram_read(tp
, ver_addr
) >= ver
) {
4865 dev_dbg(&tp
->intf
->dev
, "PHY firmware has been the newest\n");
4869 sram_write(tp
, ver_addr
, ver
);
4871 dev_dbg(&tp
->intf
->dev
, "PHY firmware version %x\n", ver
);
4876 static void rtl8152_fw_phy_fixup(struct r8152
*tp
, struct fw_phy_fixup
*fix
)
4880 addr
= __le16_to_cpu(fix
->setting
.addr
);
4881 data
= ocp_reg_read(tp
, addr
);
4883 switch (__le16_to_cpu(fix
->bit_cmd
)) {
4885 data
&= __le16_to_cpu(fix
->setting
.data
);
4888 data
|= __le16_to_cpu(fix
->setting
.data
);
4891 data
&= ~__le16_to_cpu(fix
->setting
.data
);
4894 data
^= __le16_to_cpu(fix
->setting
.data
);
4900 ocp_reg_write(tp
, addr
, data
);
4902 dev_dbg(&tp
->intf
->dev
, "applied ocp %x %x\n", addr
, data
);
4905 static void rtl8152_fw_phy_union_apply(struct r8152
*tp
, struct fw_phy_union
*phy
)
4912 for (i
= 0; i
< num
; i
++)
4913 sram_write(tp
, __le16_to_cpu(phy
->pre_set
[i
].addr
),
4914 __le16_to_cpu(phy
->pre_set
[i
].data
));
4916 length
= __le32_to_cpu(phy
->blk_hdr
.length
);
4917 length
-= __le16_to_cpu(phy
->fw_offset
);
4919 data
= (__le16
*)((u8
*)phy
+ __le16_to_cpu(phy
->fw_offset
));
4921 ocp_reg_write(tp
, OCP_SRAM_ADDR
, __le16_to_cpu(phy
->fw_reg
));
4922 for (i
= 0; i
< num
; i
++)
4923 ocp_reg_write(tp
, OCP_SRAM_DATA
, __le16_to_cpu(data
[i
]));
4926 for (i
= 0; i
< num
; i
++)
4927 sram_write(tp
, __le16_to_cpu(phy
->bp
[i
].addr
), __le16_to_cpu(phy
->bp
[i
].data
));
4929 if (phy
->bp_num
&& phy
->bp_en
.addr
)
4930 sram_write(tp
, __le16_to_cpu(phy
->bp_en
.addr
), __le16_to_cpu(phy
->bp_en
.data
));
4932 dev_dbg(&tp
->intf
->dev
, "successfully applied %s\n", phy
->info
);
4935 static void rtl8152_fw_phy_nc_apply(struct r8152
*tp
, struct fw_phy_nc
*phy
)
4937 u16 mode_reg
, bp_index
;
4941 mode_reg
= __le16_to_cpu(phy
->mode_reg
);
4942 sram_write(tp
, mode_reg
, __le16_to_cpu(phy
->mode_pre
));
4943 sram_write(tp
, __le16_to_cpu(phy
->ba_reg
),
4944 __le16_to_cpu(phy
->ba_data
));
4946 length
= __le32_to_cpu(phy
->blk_hdr
.length
);
4947 length
-= __le16_to_cpu(phy
->fw_offset
);
4949 data
= (__le16
*)((u8
*)phy
+ __le16_to_cpu(phy
->fw_offset
));
4951 ocp_reg_write(tp
, OCP_SRAM_ADDR
, __le16_to_cpu(phy
->fw_reg
));
4952 for (i
= 0; i
< num
; i
++)
4953 ocp_reg_write(tp
, OCP_SRAM_DATA
, __le16_to_cpu(data
[i
]));
4955 sram_write(tp
, __le16_to_cpu(phy
->patch_en_addr
),
4956 __le16_to_cpu(phy
->patch_en_value
));
4958 bp_index
= __le16_to_cpu(phy
->bp_start
);
4959 num
= __le16_to_cpu(phy
->bp_num
);
4960 for (i
= 0; i
< num
; i
++) {
4961 sram_write(tp
, bp_index
, __le16_to_cpu(phy
->bp
[i
]));
4965 sram_write(tp
, mode_reg
, __le16_to_cpu(phy
->mode_post
));
4967 dev_dbg(&tp
->intf
->dev
, "successfully applied %s\n", phy
->info
);
4970 static void rtl8152_fw_mac_apply(struct r8152
*tp
, struct fw_mac
*mac
)
4972 u16 bp_en_addr
, bp_index
, type
, bp_num
, fw_ver_reg
;
4977 switch (__le32_to_cpu(mac
->blk_hdr
.type
)) {
4979 type
= MCU_TYPE_PLA
;
4982 type
= MCU_TYPE_USB
;
4988 fw_ver_reg
= __le16_to_cpu(mac
->fw_ver_reg
);
4989 if (fw_ver_reg
&& ocp_read_byte(tp
, MCU_TYPE_USB
, fw_ver_reg
) >= mac
->fw_ver_data
) {
4990 dev_dbg(&tp
->intf
->dev
, "%s firmware has been the newest\n", type
? "PLA" : "USB");
4994 rtl_clear_bp(tp
, type
);
4996 /* Enable backup/restore of MACDBG. This is required after clearing PLA
4997 * break points and before applying the PLA firmware.
4999 if (tp
->version
== RTL_VER_04
&& type
== MCU_TYPE_PLA
&&
5000 !(ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MACDBG_POST
) & DEBUG_OE
)) {
5001 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MACDBG_PRE
, DEBUG_LTSSM
);
5002 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MACDBG_POST
, DEBUG_LTSSM
);
5005 length
= __le32_to_cpu(mac
->blk_hdr
.length
);
5006 length
-= __le16_to_cpu(mac
->fw_offset
);
5009 data
+= __le16_to_cpu(mac
->fw_offset
);
5011 generic_ocp_write(tp
, __le16_to_cpu(mac
->fw_reg
), 0xff, length
, data
,
5014 ocp_write_word(tp
, type
, __le16_to_cpu(mac
->bp_ba_addr
),
5015 __le16_to_cpu(mac
->bp_ba_value
));
5017 bp_index
= __le16_to_cpu(mac
->bp_start
);
5018 bp_num
= __le16_to_cpu(mac
->bp_num
);
5019 for (i
= 0; i
< bp_num
; i
++) {
5020 ocp_write_word(tp
, type
, bp_index
, __le16_to_cpu(mac
->bp
[i
]));
5024 bp_en_addr
= __le16_to_cpu(mac
->bp_en_addr
);
5026 ocp_write_word(tp
, type
, bp_en_addr
,
5027 __le16_to_cpu(mac
->bp_en_value
));
5030 ocp_write_byte(tp
, MCU_TYPE_USB
, fw_ver_reg
,
5033 dev_dbg(&tp
->intf
->dev
, "successfully applied %s\n", mac
->info
);
5036 static void rtl8152_apply_firmware(struct r8152
*tp
, bool power_cut
)
5038 struct rtl_fw
*rtl_fw
= &tp
->rtl_fw
;
5039 const struct firmware
*fw
;
5040 struct fw_header
*fw_hdr
;
5041 struct fw_phy_patch_key
*key
;
5043 int i
, patch_phy
= 1;
5045 if (IS_ERR_OR_NULL(rtl_fw
->fw
))
5049 fw_hdr
= (struct fw_header
*)fw
->data
;
5054 for (i
= offsetof(struct fw_header
, blocks
); i
< fw
->size
;) {
5055 struct fw_block
*block
= (struct fw_block
*)&fw
->data
[i
];
5057 switch (__le32_to_cpu(block
->type
)) {
5062 rtl8152_fw_mac_apply(tp
, (struct fw_mac
*)block
);
5064 case RTL_FW_PHY_START
:
5067 key
= (struct fw_phy_patch_key
*)block
;
5068 key_addr
= __le16_to_cpu(key
->key_reg
);
5069 rtl_pre_ram_code(tp
, key_addr
, __le16_to_cpu(key
->key_data
), !power_cut
);
5071 case RTL_FW_PHY_STOP
:
5075 rtl_post_ram_code(tp
, key_addr
, !power_cut
);
5078 rtl8152_fw_phy_nc_apply(tp
, (struct fw_phy_nc
*)block
);
5080 case RTL_FW_PHY_VER
:
5081 patch_phy
= rtl8152_fw_phy_ver(tp
, (struct fw_phy_ver
*)block
);
5083 case RTL_FW_PHY_UNION_NC
:
5084 case RTL_FW_PHY_UNION_NC1
:
5085 case RTL_FW_PHY_UNION_NC2
:
5086 case RTL_FW_PHY_UNION_UC2
:
5087 case RTL_FW_PHY_UNION_UC
:
5088 case RTL_FW_PHY_UNION_MISC
:
5090 rtl8152_fw_phy_union_apply(tp
, (struct fw_phy_union
*)block
);
5092 case RTL_FW_PHY_FIXUP
:
5094 rtl8152_fw_phy_fixup(tp
, (struct fw_phy_fixup
*)block
);
5096 case RTL_FW_PHY_SPEED_UP
:
5097 rtl_ram_code_speed_up(tp
, (struct fw_phy_speed_up
*)block
, !power_cut
);
5103 i
+= ALIGN(__le32_to_cpu(block
->length
), 8);
5107 if (rtl_fw
->post_fw
)
5108 rtl_fw
->post_fw(tp
);
5110 strscpy(rtl_fw
->version
, fw_hdr
->version
, RTL_VER_SIZE
);
5111 dev_info(&tp
->intf
->dev
, "load %s successfully\n", rtl_fw
->version
);
5114 static void rtl8152_release_firmware(struct r8152
*tp
)
5116 struct rtl_fw
*rtl_fw
= &tp
->rtl_fw
;
5118 if (!IS_ERR_OR_NULL(rtl_fw
->fw
)) {
5119 release_firmware(rtl_fw
->fw
);
5124 static int rtl8152_request_firmware(struct r8152
*tp
)
5126 struct rtl_fw
*rtl_fw
= &tp
->rtl_fw
;
5129 if (rtl_fw
->fw
|| !rtl_fw
->fw_name
) {
5130 dev_info(&tp
->intf
->dev
, "skip request firmware\n");
5135 rc
= request_firmware(&rtl_fw
->fw
, rtl_fw
->fw_name
, &tp
->intf
->dev
);
5139 rc
= rtl8152_check_firmware(tp
, rtl_fw
);
5141 release_firmware(rtl_fw
->fw
);
5145 rtl_fw
->fw
= ERR_PTR(rc
);
5147 dev_warn(&tp
->intf
->dev
,
5148 "unable to load firmware patch %s (%ld)\n",
5149 rtl_fw
->fw_name
, rc
);
5155 static void r8152_aldps_en(struct r8152
*tp
, bool enable
)
5158 ocp_reg_write(tp
, OCP_ALDPS_CONFIG
, ENPWRSAVE
| ENPDNPS
|
5159 LINKENA
| DIS_SDSAVE
);
5161 ocp_reg_write(tp
, OCP_ALDPS_CONFIG
, ENPDNPS
| LINKENA
|
5167 static inline void r8152_mmd_indirect(struct r8152
*tp
, u16 dev
, u16 reg
)
5169 ocp_reg_write(tp
, OCP_EEE_AR
, FUN_ADDR
| dev
);
5170 ocp_reg_write(tp
, OCP_EEE_DATA
, reg
);
5171 ocp_reg_write(tp
, OCP_EEE_AR
, FUN_DATA
| dev
);
5174 static u16
r8152_mmd_read(struct r8152
*tp
, u16 dev
, u16 reg
)
5178 r8152_mmd_indirect(tp
, dev
, reg
);
5179 data
= ocp_reg_read(tp
, OCP_EEE_DATA
);
5180 ocp_reg_write(tp
, OCP_EEE_AR
, 0x0000);
5185 static void r8152_mmd_write(struct r8152
*tp
, u16 dev
, u16 reg
, u16 data
)
5187 r8152_mmd_indirect(tp
, dev
, reg
);
5188 ocp_reg_write(tp
, OCP_EEE_DATA
, data
);
5189 ocp_reg_write(tp
, OCP_EEE_AR
, 0x0000);
5192 static void r8152_eee_en(struct r8152
*tp
, bool enable
)
5194 u16 config1
, config2
, config3
;
5197 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
);
5198 config1
= ocp_reg_read(tp
, OCP_EEE_CONFIG1
) & ~sd_rise_time_mask
;
5199 config2
= ocp_reg_read(tp
, OCP_EEE_CONFIG2
);
5200 config3
= ocp_reg_read(tp
, OCP_EEE_CONFIG3
) & ~fast_snr_mask
;
5203 ocp_data
|= EEE_RX_EN
| EEE_TX_EN
;
5204 config1
|= EEE_10_CAP
| EEE_NWAY_EN
| TX_QUIET_EN
| RX_QUIET_EN
;
5205 config1
|= sd_rise_time(1);
5206 config2
|= RG_DACQUIET_EN
| RG_LDVQUIET_EN
;
5207 config3
|= fast_snr(42);
5209 ocp_data
&= ~(EEE_RX_EN
| EEE_TX_EN
);
5210 config1
&= ~(EEE_10_CAP
| EEE_NWAY_EN
| TX_QUIET_EN
|
5212 config1
|= sd_rise_time(7);
5213 config2
&= ~(RG_DACQUIET_EN
| RG_LDVQUIET_EN
);
5214 config3
|= fast_snr(511);
5217 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
, ocp_data
);
5218 ocp_reg_write(tp
, OCP_EEE_CONFIG1
, config1
);
5219 ocp_reg_write(tp
, OCP_EEE_CONFIG2
, config2
);
5220 ocp_reg_write(tp
, OCP_EEE_CONFIG3
, config3
);
5223 static void r8153_eee_en(struct r8152
*tp
, bool enable
)
5228 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
);
5229 config
= ocp_reg_read(tp
, OCP_EEE_CFG
);
5232 ocp_data
|= EEE_RX_EN
| EEE_TX_EN
;
5235 ocp_data
&= ~(EEE_RX_EN
| EEE_TX_EN
);
5236 config
&= ~EEE10_EN
;
5239 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
, ocp_data
);
5240 ocp_reg_write(tp
, OCP_EEE_CFG
, config
);
5242 tp
->ups_info
.eee
= enable
;
5245 static void r8156_eee_en(struct r8152
*tp
, bool enable
)
5249 r8153_eee_en(tp
, enable
);
5251 config
= ocp_reg_read(tp
, OCP_EEE_ADV2
);
5254 config
|= MDIO_EEE_2_5GT
;
5256 config
&= ~MDIO_EEE_2_5GT
;
5258 ocp_reg_write(tp
, OCP_EEE_ADV2
, config
);
5261 static void rtl_eee_enable(struct r8152
*tp
, bool enable
)
5263 switch (tp
->version
) {
5268 r8152_eee_en(tp
, true);
5269 r8152_mmd_write(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
,
5272 r8152_eee_en(tp
, false);
5273 r8152_mmd_write(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, 0);
5284 r8153_eee_en(tp
, true);
5285 ocp_reg_write(tp
, OCP_EEE_ADV
, tp
->eee_adv
);
5287 r8153_eee_en(tp
, false);
5288 ocp_reg_write(tp
, OCP_EEE_ADV
, 0);
5297 r8156_eee_en(tp
, true);
5298 ocp_reg_write(tp
, OCP_EEE_ADV
, tp
->eee_adv
);
5300 r8156_eee_en(tp
, false);
5301 ocp_reg_write(tp
, OCP_EEE_ADV
, 0);
5309 static void r8152b_enable_fc(struct r8152
*tp
)
5313 anar
= r8152_mdio_read(tp
, MII_ADVERTISE
);
5314 anar
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
5315 r8152_mdio_write(tp
, MII_ADVERTISE
, anar
);
5317 tp
->ups_info
.flow_control
= true;
5320 static void rtl8152_disable(struct r8152
*tp
)
5322 r8152_aldps_en(tp
, false);
5324 r8152_aldps_en(tp
, true);
5327 static void r8152b_hw_phy_cfg(struct r8152
*tp
)
5329 rtl8152_apply_firmware(tp
, false);
5330 rtl_eee_enable(tp
, tp
->eee_en
);
5331 r8152_aldps_en(tp
, true);
5332 r8152b_enable_fc(tp
);
5334 set_bit(PHY_RESET
, &tp
->flags
);
5337 static void wait_oob_link_list_ready(struct r8152
*tp
)
5342 for (i
= 0; i
< 1000; i
++) {
5343 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
5344 if (ocp_data
& LINK_LIST_READY
)
5346 usleep_range(1000, 2000);
5350 static void r8156b_wait_loading_flash(struct r8152
*tp
)
5352 if ((ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_GPHY_CTRL
) & GPHY_FLASH
) &&
5353 !(ocp_read_word(tp
, MCU_TYPE_USB
, USB_GPHY_CTRL
) & BYPASS_FLASH
)) {
5356 for (i
= 0; i
< 100; i
++) {
5357 if (ocp_read_word(tp
, MCU_TYPE_USB
, USB_GPHY_CTRL
) & GPHY_PATCH_DONE
)
5359 usleep_range(1000, 2000);
5364 static void r8152b_exit_oob(struct r8152
*tp
)
5368 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
5369 ocp_data
&= ~RCR_ACPT_ALL
;
5370 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
5372 rxdy_gated_en(tp
, true);
5373 r8153_teredo_off(tp
);
5374 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
5375 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CR
, 0x00);
5377 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
5378 ocp_data
&= ~NOW_IS_OOB
;
5379 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
5381 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
5382 ocp_data
&= ~MCU_BORW_EN
;
5383 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
5385 wait_oob_link_list_ready(tp
);
5387 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
5388 ocp_data
|= RE_INIT_LL
;
5389 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
5391 wait_oob_link_list_ready(tp
);
5393 rtl8152_nic_reset(tp
);
5395 /* rx share fifo credit full threshold */
5396 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL0
, RXFIFO_THR1_NORMAL
);
5398 if (tp
->udev
->speed
== USB_SPEED_FULL
||
5399 tp
->udev
->speed
== USB_SPEED_LOW
) {
5400 /* rx share fifo credit near full threshold */
5401 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
,
5403 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
,
5406 /* rx share fifo credit near full threshold */
5407 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
,
5409 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
,
5413 /* TX share fifo free credit full threshold */
5414 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_CTRL
, TXFIFO_THR_NORMAL2
);
5416 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_TX_AGG
, TX_AGG_MAX_THRESHOLD
);
5417 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_RX_BUF_TH
, RX_THR_HIGH
);
5418 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_TX_DMA
,
5419 TEST_MODE_DISABLE
| TX_SIZE_ADJUST1
);
5421 rtl_rx_vlan_en(tp
, tp
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
);
5423 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, RTL8152_RMS
);
5425 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
);
5426 ocp_data
|= TCR0_AUTO_FIFO
;
5427 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
, ocp_data
);
5430 static void r8152b_enter_oob(struct r8152
*tp
)
5434 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
5435 ocp_data
&= ~NOW_IS_OOB
;
5436 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
5438 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL0
, RXFIFO_THR1_OOB
);
5439 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
, RXFIFO_THR2_OOB
);
5440 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
, RXFIFO_THR3_OOB
);
5444 wait_oob_link_list_ready(tp
);
5446 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
5447 ocp_data
|= RE_INIT_LL
;
5448 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
5450 wait_oob_link_list_ready(tp
);
5452 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, RTL8152_RMS
);
5454 rtl_rx_vlan_en(tp
, true);
5456 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BDC_CR
);
5457 ocp_data
|= ALDPS_PROXY_MODE
;
5458 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_BDC_CR
, ocp_data
);
5460 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
5461 ocp_data
|= NOW_IS_OOB
| DIS_MCU_CLROOB
;
5462 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
5464 rxdy_gated_en(tp
, false);
5466 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
5467 ocp_data
|= RCR_APM
| RCR_AM
| RCR_AB
;
5468 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
5471 static int r8153_pre_firmware_1(struct r8152
*tp
)
5475 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5476 for (i
= 0; i
< 104; i
++) {
5477 u32 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_WDT1_CTRL
);
5479 if (!(ocp_data
& WTD1_EN
))
5481 usleep_range(1000, 2000);
5487 static int r8153_post_firmware_1(struct r8152
*tp
)
5489 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5490 if (ocp_read_byte(tp
, MCU_TYPE_USB
, USB_CSTMR
) & FORCE_SUPER
)
5491 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BP_4
, BP4_SUPER_ONLY
);
5493 /* reset UPHY timer to 36 ms */
5494 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_UPHY_TIMER
, 36000 / 16);
5499 static int r8153_pre_firmware_2(struct r8152
*tp
)
5503 r8153_pre_firmware_1(tp
);
5505 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN0
);
5506 ocp_data
&= ~FW_FIX_SUSPEND
;
5507 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN0
, ocp_data
);
5512 static int r8153_post_firmware_2(struct r8152
*tp
)
5516 /* enable bp0 if support USB_SPEED_SUPER only */
5517 if (ocp_read_byte(tp
, MCU_TYPE_USB
, USB_CSTMR
) & FORCE_SUPER
) {
5518 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BP_EN
);
5520 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_BP_EN
, ocp_data
);
5523 /* reset UPHY timer to 36 ms */
5524 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_UPHY_TIMER
, 36000 / 16);
5526 /* enable U3P3 check, set the counter to 4 */
5527 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
, U3P3_CHECK_EN
| 4);
5529 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN0
);
5530 ocp_data
|= FW_FIX_SUSPEND
;
5531 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN0
, ocp_data
);
5533 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_USB2PHY
);
5534 ocp_data
|= USB2PHY_L1
| USB2PHY_SUSPEND
;
5535 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_USB2PHY
, ocp_data
);
5540 static int r8153_post_firmware_3(struct r8152
*tp
)
5544 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_USB2PHY
);
5545 ocp_data
|= USB2PHY_L1
| USB2PHY_SUSPEND
;
5546 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_USB2PHY
, ocp_data
);
5548 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN1
);
5549 ocp_data
|= FW_IP_RESET_EN
;
5550 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN1
, ocp_data
);
5555 static int r8153b_pre_firmware_1(struct r8152
*tp
)
5557 /* enable fc timer and set timer to 1 second. */
5558 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FC_TIMER
,
5559 CTRL_TIMER_EN
| (1000 / 8));
5564 static int r8153b_post_firmware_1(struct r8152
*tp
)
5568 /* enable bp0 for RTL8153-BND */
5569 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_1
);
5570 if (ocp_data
& BND_MASK
) {
5571 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BP_EN
);
5573 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_BP_EN
, ocp_data
);
5576 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_CTRL
);
5577 ocp_data
|= FLOW_CTRL_PATCH_OPT
;
5578 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_CTRL
, ocp_data
);
5580 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
);
5581 ocp_data
|= FC_PATCH_TASK
;
5582 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
, ocp_data
);
5584 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN1
);
5585 ocp_data
|= FW_IP_RESET_EN
;
5586 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN1
, ocp_data
);
5591 static int r8153c_post_firmware_1(struct r8152
*tp
)
5595 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_CTRL
);
5596 ocp_data
|= FLOW_CTRL_PATCH_2
;
5597 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_CTRL
, ocp_data
);
5599 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
);
5600 ocp_data
|= FC_PATCH_TASK
;
5601 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
, ocp_data
);
5606 static int r8156a_post_firmware_1(struct r8152
*tp
)
5610 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN1
);
5611 ocp_data
|= FW_IP_RESET_EN
;
5612 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_FIX_EN1
, ocp_data
);
5614 /* Modify U3PHY parameter for compatibility issue */
5615 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_UPHY3_MDCMDIO
, 0x4026840e);
5616 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_UPHY3_MDCMDIO
, 0x4001acc9);
5621 static void r8153_aldps_en(struct r8152
*tp
, bool enable
)
5625 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
5628 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
5633 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
5634 for (i
= 0; i
< 20; i
++) {
5635 usleep_range(1000, 2000);
5636 if (ocp_read_word(tp
, MCU_TYPE_PLA
, 0xe000) & 0x0100)
5641 tp
->ups_info
.aldps
= enable
;
5644 static void r8153_hw_phy_cfg(struct r8152
*tp
)
5649 /* disable ALDPS before updating the PHY parameters */
5650 r8153_aldps_en(tp
, false);
5652 /* disable EEE before updating the PHY parameters */
5653 rtl_eee_enable(tp
, false);
5655 rtl8152_apply_firmware(tp
, false);
5657 if (tp
->version
== RTL_VER_03
) {
5658 data
= ocp_reg_read(tp
, OCP_EEE_CFG
);
5659 data
&= ~CTAP_SHORT_EN
;
5660 ocp_reg_write(tp
, OCP_EEE_CFG
, data
);
5663 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
5664 data
|= EEE_CLKDIV_EN
;
5665 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
5667 data
= ocp_reg_read(tp
, OCP_DOWN_SPEED
);
5668 data
|= EN_10M_BGOFF
;
5669 ocp_reg_write(tp
, OCP_DOWN_SPEED
, data
);
5670 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
5671 data
|= EN_10M_PLLOFF
;
5672 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
5673 sram_write(tp
, SRAM_IMPEDANCE
, 0x0b13);
5675 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
5676 ocp_data
|= PFM_PWM_SWITCH
;
5677 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
5679 /* Enable LPF corner auto tune */
5680 sram_write(tp
, SRAM_LPF_CFG
, 0xf70f);
5682 /* Adjust 10M Amplitude */
5683 sram_write(tp
, SRAM_10M_AMP1
, 0x00af);
5684 sram_write(tp
, SRAM_10M_AMP2
, 0x0208);
5687 rtl_eee_enable(tp
, true);
5689 r8153_aldps_en(tp
, true);
5690 r8152b_enable_fc(tp
);
5692 switch (tp
->version
) {
5699 r8153_u2p3en(tp
, true);
5703 set_bit(PHY_RESET
, &tp
->flags
);
5706 static u32
r8152_efuse_read(struct r8152
*tp
, u8 addr
)
5710 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EFUSE_CMD
, EFUSE_READ_CMD
| addr
);
5711 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EFUSE_CMD
);
5712 ocp_data
= (ocp_data
& EFUSE_DATA_BIT16
) << 9; /* data of bit16 */
5713 ocp_data
|= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EFUSE_DATA
);
5718 static void r8153b_hw_phy_cfg(struct r8152
*tp
)
5723 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
5724 if (ocp_data
& PCUT_STATUS
) {
5725 ocp_data
&= ~PCUT_STATUS
;
5726 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MISC_0
, ocp_data
);
5729 /* disable ALDPS before updating the PHY parameters */
5730 r8153_aldps_en(tp
, false);
5732 /* disable EEE before updating the PHY parameters */
5733 rtl_eee_enable(tp
, false);
5735 /* U1/U2/L1 idle timer. 500 us */
5736 ocp_write_word(tp
, MCU_TYPE_USB
, USB_U1U2_TIMER
, 500);
5738 data
= r8153_phy_status(tp
, 0);
5741 case PHY_STAT_PWRDN
:
5742 case PHY_STAT_EXT_INIT
:
5743 rtl8152_apply_firmware(tp
, true);
5745 data
= r8152_mdio_read(tp
, MII_BMCR
);
5746 data
&= ~BMCR_PDOWN
;
5747 r8152_mdio_write(tp
, MII_BMCR
, data
);
5749 case PHY_STAT_LAN_ON
:
5751 rtl8152_apply_firmware(tp
, false);
5755 r8153b_green_en(tp
, test_bit(GREEN_ETHERNET
, &tp
->flags
));
5757 data
= sram_read(tp
, SRAM_GREEN_CFG
);
5759 sram_write(tp
, SRAM_GREEN_CFG
, data
);
5760 data
= ocp_reg_read(tp
, OCP_NCTL_CFG
);
5761 data
|= PGA_RETURN_EN
;
5762 ocp_reg_write(tp
, OCP_NCTL_CFG
, data
);
5764 /* ADC Bias Calibration:
5765 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5766 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5769 ocp_data
= r8152_efuse_read(tp
, 0x7d);
5770 data
= (u16
)(((ocp_data
& 0x1fff0) >> 1) | (ocp_data
& 0x7));
5772 ocp_reg_write(tp
, OCP_ADC_IOFFSET
, data
);
5774 /* ups mode tx-link-pulse timing adjustment:
5775 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5776 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5778 ocp_data
= ocp_reg_read(tp
, 0xc426);
5781 u32 swr_cnt_1ms_ini
;
5783 swr_cnt_1ms_ini
= (16000000 / ocp_data
) & SAW_CNT_1MS_MASK
;
5784 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_UPS_CFG
);
5785 ocp_data
= (ocp_data
& ~SAW_CNT_1MS_MASK
) | swr_cnt_1ms_ini
;
5786 ocp_write_word(tp
, MCU_TYPE_USB
, USB_UPS_CFG
, ocp_data
);
5789 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
5790 ocp_data
|= PFM_PWM_SWITCH
;
5791 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
5794 if (!rtl_phy_patch_request(tp
, true, true)) {
5795 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
5796 data
|= EEE_CLKDIV_EN
;
5797 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
5798 tp
->ups_info
.eee_ckdiv
= true;
5800 data
= ocp_reg_read(tp
, OCP_DOWN_SPEED
);
5801 data
|= EN_EEE_CMODE
| EN_EEE_1000
| EN_10M_CLKDIV
;
5802 ocp_reg_write(tp
, OCP_DOWN_SPEED
, data
);
5803 tp
->ups_info
.eee_cmod_lv
= true;
5804 tp
->ups_info
._10m_ckdiv
= true;
5805 tp
->ups_info
.eee_plloff_giga
= true;
5807 ocp_reg_write(tp
, OCP_SYSCLK_CFG
, 0);
5808 ocp_reg_write(tp
, OCP_SYSCLK_CFG
, clk_div_expo(5));
5809 tp
->ups_info
._250m_ckdiv
= true;
5811 rtl_phy_patch_request(tp
, false, true);
5815 rtl_eee_enable(tp
, true);
5817 r8153_aldps_en(tp
, true);
5818 r8152b_enable_fc(tp
);
5820 set_bit(PHY_RESET
, &tp
->flags
);
5823 static void r8153c_hw_phy_cfg(struct r8152
*tp
)
5825 r8153b_hw_phy_cfg(tp
);
5827 tp
->ups_info
.r_tune
= true;
5830 static void rtl8153_change_mtu(struct r8152
*tp
)
5832 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, mtu_to_size(tp
->netdev
->mtu
));
5833 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_MTPS
, MTPS_JUMBO
);
5836 static void r8153_first_init(struct r8152
*tp
)
5840 rxdy_gated_en(tp
, true);
5841 r8153_teredo_off(tp
);
5843 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
5844 ocp_data
&= ~RCR_ACPT_ALL
;
5845 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
5847 rtl8152_nic_reset(tp
);
5850 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
5851 ocp_data
&= ~NOW_IS_OOB
;
5852 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
5854 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
5855 ocp_data
&= ~MCU_BORW_EN
;
5856 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
5858 wait_oob_link_list_ready(tp
);
5860 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
5861 ocp_data
|= RE_INIT_LL
;
5862 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
5864 wait_oob_link_list_ready(tp
);
5866 rtl_rx_vlan_en(tp
, tp
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
);
5868 rtl8153_change_mtu(tp
);
5870 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
);
5871 ocp_data
|= TCR0_AUTO_FIFO
;
5872 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
, ocp_data
);
5874 rtl8152_nic_reset(tp
);
5876 /* rx share fifo credit full threshold */
5877 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL0
, RXFIFO_THR1_NORMAL
);
5878 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
, RXFIFO_THR2_NORMAL
);
5879 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
, RXFIFO_THR3_NORMAL
);
5880 /* TX share fifo free credit full threshold */
5881 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_CTRL
, TXFIFO_THR_NORMAL2
);
5884 static void r8153_enter_oob(struct r8152
*tp
)
5888 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
5889 ocp_data
&= ~NOW_IS_OOB
;
5890 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
5895 wait_oob_link_list_ready(tp
);
5897 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
5898 ocp_data
|= RE_INIT_LL
;
5899 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
5901 wait_oob_link_list_ready(tp
);
5903 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, mtu_to_size(tp
->netdev
->mtu
));
5905 switch (tp
->version
) {
5910 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
);
5911 ocp_data
&= ~TEREDO_WAKE_MASK
;
5912 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
, ocp_data
);
5918 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
5919 * type. Set it to zero. bits[7:0] are the W1C bits about
5920 * the events. Set them to all 1 to clear them.
5922 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_WAKE_BASE
, 0x00ff);
5929 rtl_rx_vlan_en(tp
, true);
5931 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BDC_CR
);
5932 ocp_data
|= ALDPS_PROXY_MODE
;
5933 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_BDC_CR
, ocp_data
);
5935 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
5936 ocp_data
|= NOW_IS_OOB
| DIS_MCU_CLROOB
;
5937 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
5939 rxdy_gated_en(tp
, false);
5941 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
5942 ocp_data
|= RCR_APM
| RCR_AM
| RCR_AB
;
5943 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
5946 static void rtl8153_disable(struct r8152
*tp
)
5948 r8153_aldps_en(tp
, false);
5951 r8153_aldps_en(tp
, true);
5954 static int rtl8156_enable(struct r8152
*tp
)
5959 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
5963 rtl_set_eee_plus(tp
);
5964 r8153_set_rx_early_timeout(tp
);
5965 r8153_set_rx_early_size(tp
);
5967 speed
= rtl8152_get_speed(tp
);
5968 rtl_set_ifg(tp
, speed
);
5970 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
);
5971 if (speed
& _2500bps
)
5972 ocp_data
&= ~IDLE_SPDWN_EN
;
5974 ocp_data
|= IDLE_SPDWN_EN
;
5975 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
, ocp_data
);
5977 if (speed
& _1000bps
)
5978 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEE_TXTWSYS
, 0x11);
5979 else if (speed
& _500bps
)
5980 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEE_TXTWSYS
, 0x3d);
5982 if (tp
->udev
->speed
== USB_SPEED_HIGH
) {
5983 /* USB 0xb45e[3:0] l1_nyet_hird */
5984 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_L1_CTRL
);
5986 if (is_flow_control(speed
))
5990 ocp_write_word(tp
, MCU_TYPE_USB
, USB_L1_CTRL
, ocp_data
);
5993 return rtl_enable(tp
);
5996 static int rtl8156b_enable(struct r8152
*tp
)
6001 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6005 rtl_set_eee_plus(tp
);
6007 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_RX_AGGR_NUM
);
6008 ocp_data
&= ~RX_AGGR_NUM_MASK
;
6009 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_AGGR_NUM
, ocp_data
);
6011 r8153_set_rx_early_timeout(tp
);
6012 r8153_set_rx_early_size(tp
);
6014 speed
= rtl8152_get_speed(tp
);
6015 rtl_set_ifg(tp
, speed
);
6017 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
);
6018 if (speed
& _2500bps
)
6019 ocp_data
&= ~IDLE_SPDWN_EN
;
6021 ocp_data
|= IDLE_SPDWN_EN
;
6022 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
, ocp_data
);
6024 if (tp
->udev
->speed
== USB_SPEED_HIGH
) {
6025 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_L1_CTRL
);
6027 if (is_flow_control(speed
))
6031 ocp_write_word(tp
, MCU_TYPE_USB
, USB_L1_CTRL
, ocp_data
);
6034 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
);
6035 ocp_data
&= ~FC_PATCH_TASK
;
6036 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
, ocp_data
);
6037 usleep_range(1000, 2000);
6038 ocp_data
|= FC_PATCH_TASK
;
6039 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
, ocp_data
);
6041 return rtl_enable(tp
);
6044 static int rtl8152_set_speed(struct r8152
*tp
, u8 autoneg
, u32 speed
, u8 duplex
,
6050 if (autoneg
== AUTONEG_DISABLE
) {
6051 if (duplex
!= DUPLEX_HALF
&& duplex
!= DUPLEX_FULL
)
6056 bmcr
= BMCR_SPEED10
;
6057 if (duplex
== DUPLEX_FULL
) {
6058 bmcr
|= BMCR_FULLDPLX
;
6059 tp
->ups_info
.speed_duplex
= FORCE_10M_FULL
;
6061 tp
->ups_info
.speed_duplex
= FORCE_10M_HALF
;
6065 bmcr
= BMCR_SPEED100
;
6066 if (duplex
== DUPLEX_FULL
) {
6067 bmcr
|= BMCR_FULLDPLX
;
6068 tp
->ups_info
.speed_duplex
= FORCE_100M_FULL
;
6070 tp
->ups_info
.speed_duplex
= FORCE_100M_HALF
;
6074 if (tp
->mii
.supports_gmii
) {
6075 bmcr
= BMCR_SPEED1000
| BMCR_FULLDPLX
;
6076 tp
->ups_info
.speed_duplex
= NWAY_1000M_FULL
;
6085 if (duplex
== DUPLEX_FULL
)
6086 tp
->mii
.full_duplex
= 1;
6088 tp
->mii
.full_duplex
= 0;
6090 tp
->mii
.force_media
= 1;
6095 support
= RTL_ADVERTISED_10_HALF
| RTL_ADVERTISED_10_FULL
|
6096 RTL_ADVERTISED_100_HALF
| RTL_ADVERTISED_100_FULL
;
6098 if (tp
->mii
.supports_gmii
) {
6099 support
|= RTL_ADVERTISED_1000_FULL
;
6101 if (tp
->support_2500full
)
6102 support
|= RTL_ADVERTISED_2500_FULL
;
6105 if (!(advertising
& support
))
6108 orig
= r8152_mdio_read(tp
, MII_ADVERTISE
);
6109 new1
= orig
& ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
6110 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
6111 if (advertising
& RTL_ADVERTISED_10_HALF
) {
6112 new1
|= ADVERTISE_10HALF
;
6113 tp
->ups_info
.speed_duplex
= NWAY_10M_HALF
;
6115 if (advertising
& RTL_ADVERTISED_10_FULL
) {
6116 new1
|= ADVERTISE_10FULL
;
6117 tp
->ups_info
.speed_duplex
= NWAY_10M_FULL
;
6120 if (advertising
& RTL_ADVERTISED_100_HALF
) {
6121 new1
|= ADVERTISE_100HALF
;
6122 tp
->ups_info
.speed_duplex
= NWAY_100M_HALF
;
6124 if (advertising
& RTL_ADVERTISED_100_FULL
) {
6125 new1
|= ADVERTISE_100FULL
;
6126 tp
->ups_info
.speed_duplex
= NWAY_100M_FULL
;
6130 r8152_mdio_write(tp
, MII_ADVERTISE
, new1
);
6131 tp
->mii
.advertising
= new1
;
6134 if (tp
->mii
.supports_gmii
) {
6135 orig
= r8152_mdio_read(tp
, MII_CTRL1000
);
6136 new1
= orig
& ~(ADVERTISE_1000FULL
|
6137 ADVERTISE_1000HALF
);
6139 if (advertising
& RTL_ADVERTISED_1000_FULL
) {
6140 new1
|= ADVERTISE_1000FULL
;
6141 tp
->ups_info
.speed_duplex
= NWAY_1000M_FULL
;
6145 r8152_mdio_write(tp
, MII_CTRL1000
, new1
);
6148 if (tp
->support_2500full
) {
6149 orig
= ocp_reg_read(tp
, OCP_10GBT_CTRL
);
6150 new1
= orig
& ~MDIO_AN_10GBT_CTRL_ADV2_5G
;
6152 if (advertising
& RTL_ADVERTISED_2500_FULL
) {
6153 new1
|= MDIO_AN_10GBT_CTRL_ADV2_5G
;
6154 tp
->ups_info
.speed_duplex
= NWAY_2500M_FULL
;
6158 ocp_reg_write(tp
, OCP_10GBT_CTRL
, new1
);
6161 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
6163 tp
->mii
.force_media
= 0;
6166 if (test_and_clear_bit(PHY_RESET
, &tp
->flags
))
6169 r8152_mdio_write(tp
, MII_BMCR
, bmcr
);
6171 if (bmcr
& BMCR_RESET
) {
6174 for (i
= 0; i
< 50; i
++) {
6176 if ((r8152_mdio_read(tp
, MII_BMCR
) & BMCR_RESET
) == 0)
6185 static void rtl8152_up(struct r8152
*tp
)
6187 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6190 r8152_aldps_en(tp
, false);
6191 r8152b_exit_oob(tp
);
6192 r8152_aldps_en(tp
, true);
6195 static void rtl8152_down(struct r8152
*tp
)
6197 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
6198 rtl_drop_queued_tx(tp
);
6202 r8152_power_cut_en(tp
, false);
6203 r8152_aldps_en(tp
, false);
6204 r8152b_enter_oob(tp
);
6205 r8152_aldps_en(tp
, true);
6208 static void rtl8153_up(struct r8152
*tp
)
6212 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6215 r8153_u1u2en(tp
, false);
6216 r8153_u2p3en(tp
, false);
6217 r8153_aldps_en(tp
, false);
6218 r8153_first_init(tp
);
6220 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CONFIG6
);
6221 ocp_data
|= LANWAKE_CLR_EN
;
6222 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CONFIG6
, ocp_data
);
6224 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_LWAKE_CTRL_REG
);
6225 ocp_data
&= ~LANWAKE_PIN
;
6226 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_LWAKE_CTRL_REG
, ocp_data
);
6228 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_SSPHYLINK1
);
6229 ocp_data
&= ~DELAY_PHY_PWR_CHG
;
6230 ocp_write_word(tp
, MCU_TYPE_USB
, USB_SSPHYLINK1
, ocp_data
);
6232 r8153_aldps_en(tp
, true);
6234 switch (tp
->version
) {
6241 r8153_u2p3en(tp
, true);
6245 r8153_u1u2en(tp
, true);
6248 static void rtl8153_down(struct r8152
*tp
)
6252 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
6253 rtl_drop_queued_tx(tp
);
6257 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CONFIG6
);
6258 ocp_data
&= ~LANWAKE_CLR_EN
;
6259 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CONFIG6
, ocp_data
);
6261 r8153_u1u2en(tp
, false);
6262 r8153_u2p3en(tp
, false);
6263 r8153_power_cut_en(tp
, false);
6264 r8153_aldps_en(tp
, false);
6265 r8153_enter_oob(tp
);
6266 r8153_aldps_en(tp
, true);
6269 static void rtl8153b_up(struct r8152
*tp
)
6273 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6276 r8153b_u1u2en(tp
, false);
6277 r8153_u2p3en(tp
, false);
6278 r8153_aldps_en(tp
, false);
6280 r8153_first_init(tp
);
6281 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_RX_BUF_TH
, RX_THR_B
);
6283 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
);
6284 ocp_data
&= ~PLA_MCU_SPDWN_EN
;
6285 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, ocp_data
);
6287 r8153_aldps_en(tp
, true);
6289 if (tp
->udev
->speed
>= USB_SPEED_SUPER
)
6290 r8153b_u1u2en(tp
, true);
6293 static void rtl8153b_down(struct r8152
*tp
)
6297 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
6298 rtl_drop_queued_tx(tp
);
6302 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
);
6303 ocp_data
|= PLA_MCU_SPDWN_EN
;
6304 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, ocp_data
);
6306 r8153b_u1u2en(tp
, false);
6307 r8153_u2p3en(tp
, false);
6308 r8153b_power_cut_en(tp
, false);
6309 r8153_aldps_en(tp
, false);
6310 r8153_enter_oob(tp
);
6311 r8153_aldps_en(tp
, true);
6314 static void rtl8153c_change_mtu(struct r8152
*tp
)
6316 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, mtu_to_size(tp
->netdev
->mtu
));
6317 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_MTPS
, 10 * 1024 / 64);
6319 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_CTRL
, 512 / 64);
6321 /* Adjust the tx fifo free credit full threshold, otherwise
6322 * the fifo would be too small to send a jumbo frame packet.
6324 if (tp
->netdev
->mtu
< 8000)
6325 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_FULL
, 2048 / 8);
6327 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_FULL
, 900 / 8);
6330 static void rtl8153c_up(struct r8152
*tp
)
6334 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6337 r8153b_u1u2en(tp
, false);
6338 r8153_u2p3en(tp
, false);
6339 r8153_aldps_en(tp
, false);
6341 rxdy_gated_en(tp
, true);
6342 r8153_teredo_off(tp
);
6344 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
6345 ocp_data
&= ~RCR_ACPT_ALL
;
6346 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
6348 rtl8152_nic_reset(tp
);
6351 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
6352 ocp_data
&= ~NOW_IS_OOB
;
6353 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
6355 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
6356 ocp_data
&= ~MCU_BORW_EN
;
6357 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
6359 wait_oob_link_list_ready(tp
);
6361 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
6362 ocp_data
|= RE_INIT_LL
;
6363 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
6365 wait_oob_link_list_ready(tp
);
6367 rtl_rx_vlan_en(tp
, tp
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
);
6369 rtl8153c_change_mtu(tp
);
6371 rtl8152_nic_reset(tp
);
6373 /* rx share fifo credit full threshold */
6374 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL0
, 0x02);
6375 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_FULL
, 0x08);
6376 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
, RXFIFO_THR2_NORMAL
);
6377 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
, RXFIFO_THR3_NORMAL
);
6379 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_RX_BUF_TH
, RX_THR_B
);
6381 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
6383 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
6385 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
, ocp_data
);
6387 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
6389 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
);
6390 ocp_data
&= ~PLA_MCU_SPDWN_EN
;
6391 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, ocp_data
);
6393 r8153_aldps_en(tp
, true);
6394 r8153b_u1u2en(tp
, true);
6397 static inline u32
fc_pause_on_auto(struct r8152
*tp
)
6399 return (ALIGN(mtu_to_size(tp
->netdev
->mtu
), 1024) + 6 * 1024);
6402 static inline u32
fc_pause_off_auto(struct r8152
*tp
)
6404 return (ALIGN(mtu_to_size(tp
->netdev
->mtu
), 1024) + 14 * 1024);
6407 static void r8156_fc_parameter(struct r8152
*tp
)
6409 u32 pause_on
= tp
->fc_pause_on
? tp
->fc_pause_on
: fc_pause_on_auto(tp
);
6410 u32 pause_off
= tp
->fc_pause_off
? tp
->fc_pause_off
: fc_pause_off_auto(tp
);
6412 switch (tp
->version
) {
6415 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RX_FIFO_FULL
, pause_on
/ 8);
6416 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RX_FIFO_EMPTY
, pause_off
/ 8);
6421 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RX_FIFO_FULL
, pause_on
/ 16);
6422 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RX_FIFO_EMPTY
, pause_off
/ 16);
6429 static void rtl8156_change_mtu(struct r8152
*tp
)
6431 u32 rx_max_size
= mtu_to_size(tp
->netdev
->mtu
);
6433 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, rx_max_size
);
6434 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_MTPS
, MTPS_JUMBO
);
6435 r8156_fc_parameter(tp
);
6437 /* TX share fifo free credit full threshold */
6438 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_CTRL
, 512 / 64);
6439 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_FULL
,
6440 ALIGN(rx_max_size
+ sizeof(struct tx_desc
), 1024) / 16);
6443 static void rtl8156_up(struct r8152
*tp
)
6447 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6450 r8153b_u1u2en(tp
, false);
6451 r8153_u2p3en(tp
, false);
6452 r8153_aldps_en(tp
, false);
6454 rxdy_gated_en(tp
, true);
6455 r8153_teredo_off(tp
);
6457 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
6458 ocp_data
&= ~RCR_ACPT_ALL
;
6459 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
6461 rtl8152_nic_reset(tp
);
6464 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
6465 ocp_data
&= ~NOW_IS_OOB
;
6466 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
6468 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
6469 ocp_data
&= ~MCU_BORW_EN
;
6470 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
6472 rtl_rx_vlan_en(tp
, tp
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
);
6474 rtl8156_change_mtu(tp
);
6476 switch (tp
->version
) {
6480 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_BMU_CONFIG
);
6481 ocp_data
|= ACT_ODMA
;
6482 ocp_write_word(tp
, MCU_TYPE_USB
, USB_BMU_CONFIG
, ocp_data
);
6488 /* share FIFO settings */
6489 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_FULL
);
6490 ocp_data
&= ~RXFIFO_FULL_MASK
;
6492 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_FULL
, ocp_data
);
6494 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
);
6495 ocp_data
&= ~PLA_MCU_SPDWN_EN
;
6496 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, ocp_data
);
6498 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_SPEED_OPTION
);
6499 ocp_data
&= ~(RG_PWRDN_EN
| ALL_SPEED_OFF
);
6500 ocp_write_word(tp
, MCU_TYPE_USB
, USB_SPEED_OPTION
, ocp_data
);
6502 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_RX_BUF_TH
, 0x00600400);
6504 if (tp
->saved_wolopts
!= __rtl_get_wol(tp
)) {
6505 netif_warn(tp
, ifup
, tp
->netdev
, "wol setting is changed\n");
6506 __rtl_set_wol(tp
, tp
->saved_wolopts
);
6509 r8153_aldps_en(tp
, true);
6510 r8153_u2p3en(tp
, true);
6512 if (tp
->udev
->speed
>= USB_SPEED_SUPER
)
6513 r8153b_u1u2en(tp
, true);
6516 static void rtl8156_down(struct r8152
*tp
)
6520 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
6521 rtl_drop_queued_tx(tp
);
6525 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
);
6526 ocp_data
|= PLA_MCU_SPDWN_EN
;
6527 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, ocp_data
);
6529 r8153b_u1u2en(tp
, false);
6530 r8153_u2p3en(tp
, false);
6531 r8153b_power_cut_en(tp
, false);
6532 r8153_aldps_en(tp
, false);
6534 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
6535 ocp_data
&= ~NOW_IS_OOB
;
6536 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
6541 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6542 * type. Set it to zero. bits[7:0] are the W1C bits about
6543 * the events. Set them to all 1 to clear them.
6545 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_WAKE_BASE
, 0x00ff);
6547 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
6548 ocp_data
|= NOW_IS_OOB
;
6549 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
6551 rtl_rx_vlan_en(tp
, true);
6552 rxdy_gated_en(tp
, false);
6554 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
6555 ocp_data
|= RCR_APM
| RCR_AM
| RCR_AB
;
6556 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
6558 r8153_aldps_en(tp
, true);
6561 static bool rtl8152_in_nway(struct r8152
*tp
)
6565 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_OCP_GPHY_BASE
, 0x2000);
6566 tp
->ocp_base
= 0x2000;
6567 ocp_write_byte(tp
, MCU_TYPE_PLA
, 0xb014, 0x4c); /* phy state */
6568 nway_state
= ocp_read_word(tp
, MCU_TYPE_PLA
, 0xb01a);
6570 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6571 if (nway_state
& 0xc000)
6577 static bool rtl8153_in_nway(struct r8152
*tp
)
6579 u16 phy_state
= ocp_reg_read(tp
, OCP_PHY_STATE
) & 0xff;
6581 if (phy_state
== TXDIS_STATE
|| phy_state
== ABD_STATE
)
6587 static void set_carrier(struct r8152
*tp
)
6589 struct net_device
*netdev
= tp
->netdev
;
6590 struct napi_struct
*napi
= &tp
->napi
;
6593 speed
= rtl8152_get_speed(tp
);
6595 if (speed
& LINK_STATUS
) {
6596 if (!netif_carrier_ok(netdev
)) {
6597 tp
->rtl_ops
.enable(tp
);
6598 netif_stop_queue(netdev
);
6600 netif_carrier_on(netdev
);
6602 clear_bit(RTL8152_SET_RX_MODE
, &tp
->flags
);
6603 _rtl8152_set_rx_mode(netdev
);
6605 netif_wake_queue(netdev
);
6606 netif_info(tp
, link
, netdev
, "carrier on\n");
6607 } else if (netif_queue_stopped(netdev
) &&
6608 skb_queue_len(&tp
->tx_queue
) < tp
->tx_qlen
) {
6609 netif_wake_queue(netdev
);
6612 if (netif_carrier_ok(netdev
)) {
6613 netif_carrier_off(netdev
);
6614 tasklet_disable(&tp
->tx_tl
);
6616 tp
->rtl_ops
.disable(tp
);
6618 tasklet_enable(&tp
->tx_tl
);
6619 netif_info(tp
, link
, netdev
, "carrier off\n");
6624 static void rtl_work_func_t(struct work_struct
*work
)
6626 struct r8152
*tp
= container_of(work
, struct r8152
, schedule
.work
);
6628 /* If the device is unplugged or !netif_running(), the workqueue
6629 * doesn't need to wake the device, and could return directly.
6631 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
) || !netif_running(tp
->netdev
))
6634 if (usb_autopm_get_interface(tp
->intf
) < 0)
6637 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
6640 if (!mutex_trylock(&tp
->control
)) {
6641 schedule_delayed_work(&tp
->schedule
, 0);
6645 if (test_and_clear_bit(RTL8152_LINK_CHG
, &tp
->flags
))
6648 if (test_and_clear_bit(RTL8152_SET_RX_MODE
, &tp
->flags
))
6649 _rtl8152_set_rx_mode(tp
->netdev
);
6651 /* don't schedule tasket before linking */
6652 if (test_and_clear_bit(SCHEDULE_TASKLET
, &tp
->flags
) &&
6653 netif_carrier_ok(tp
->netdev
))
6654 tasklet_schedule(&tp
->tx_tl
);
6656 if (test_and_clear_bit(RX_EPROTO
, &tp
->flags
) &&
6657 !list_empty(&tp
->rx_done
))
6658 napi_schedule(&tp
->napi
);
6660 mutex_unlock(&tp
->control
);
6663 usb_autopm_put_interface(tp
->intf
);
6666 static void rtl_hw_phy_work_func_t(struct work_struct
*work
)
6668 struct r8152
*tp
= container_of(work
, struct r8152
, hw_phy_work
.work
);
6670 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6673 if (usb_autopm_get_interface(tp
->intf
) < 0)
6676 mutex_lock(&tp
->control
);
6678 if (rtl8152_request_firmware(tp
) == -ENODEV
&& tp
->rtl_fw
.retry
) {
6679 tp
->rtl_fw
.retry
= false;
6680 tp
->rtl_fw
.fw
= NULL
;
6682 /* Delay execution in case request_firmware() is not ready yet.
6684 queue_delayed_work(system_long_wq
, &tp
->hw_phy_work
, HZ
* 10);
6688 tp
->rtl_ops
.hw_phy_cfg(tp
);
6690 rtl8152_set_speed(tp
, tp
->autoneg
, tp
->speed
, tp
->duplex
,
6694 mutex_unlock(&tp
->control
);
6696 usb_autopm_put_interface(tp
->intf
);
6699 #ifdef CONFIG_PM_SLEEP
6700 static int rtl_notifier(struct notifier_block
*nb
, unsigned long action
,
6703 struct r8152
*tp
= container_of(nb
, struct r8152
, pm_notifier
);
6706 case PM_HIBERNATION_PREPARE
:
6707 case PM_SUSPEND_PREPARE
:
6708 usb_autopm_get_interface(tp
->intf
);
6711 case PM_POST_HIBERNATION
:
6712 case PM_POST_SUSPEND
:
6713 usb_autopm_put_interface(tp
->intf
);
6716 case PM_POST_RESTORE
:
6717 case PM_RESTORE_PREPARE
:
6726 static int rtl8152_open(struct net_device
*netdev
)
6728 struct r8152
*tp
= netdev_priv(netdev
);
6731 if (work_busy(&tp
->hw_phy_work
.work
) & WORK_BUSY_PENDING
) {
6732 cancel_delayed_work_sync(&tp
->hw_phy_work
);
6733 rtl_hw_phy_work_func_t(&tp
->hw_phy_work
.work
);
6736 res
= alloc_all_mem(tp
);
6740 res
= usb_autopm_get_interface(tp
->intf
);
6744 mutex_lock(&tp
->control
);
6748 netif_carrier_off(netdev
);
6749 netif_start_queue(netdev
);
6750 set_bit(WORK_ENABLE
, &tp
->flags
);
6752 res
= usb_submit_urb(tp
->intr_urb
, GFP_KERNEL
);
6755 netif_device_detach(tp
->netdev
);
6756 netif_warn(tp
, ifup
, netdev
, "intr_urb submit failed: %d\n",
6760 napi_enable(&tp
->napi
);
6761 tasklet_enable(&tp
->tx_tl
);
6763 mutex_unlock(&tp
->control
);
6765 usb_autopm_put_interface(tp
->intf
);
6766 #ifdef CONFIG_PM_SLEEP
6767 tp
->pm_notifier
.notifier_call
= rtl_notifier
;
6768 register_pm_notifier(&tp
->pm_notifier
);
6773 mutex_unlock(&tp
->control
);
6774 usb_autopm_put_interface(tp
->intf
);
6781 static int rtl8152_close(struct net_device
*netdev
)
6783 struct r8152
*tp
= netdev_priv(netdev
);
6786 #ifdef CONFIG_PM_SLEEP
6787 unregister_pm_notifier(&tp
->pm_notifier
);
6789 tasklet_disable(&tp
->tx_tl
);
6790 clear_bit(WORK_ENABLE
, &tp
->flags
);
6791 usb_kill_urb(tp
->intr_urb
);
6792 cancel_delayed_work_sync(&tp
->schedule
);
6793 napi_disable(&tp
->napi
);
6794 netif_stop_queue(netdev
);
6796 res
= usb_autopm_get_interface(tp
->intf
);
6797 if (res
< 0 || test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
6798 rtl_drop_queued_tx(tp
);
6801 mutex_lock(&tp
->control
);
6803 tp
->rtl_ops
.down(tp
);
6805 mutex_unlock(&tp
->control
);
6809 usb_autopm_put_interface(tp
->intf
);
6816 static void rtl_tally_reset(struct r8152
*tp
)
6820 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_RSTTALLY
);
6821 ocp_data
|= TALLY_RESET
;
6822 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RSTTALLY
, ocp_data
);
6825 static void r8152b_init(struct r8152
*tp
)
6830 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6833 data
= r8152_mdio_read(tp
, MII_BMCR
);
6834 if (data
& BMCR_PDOWN
) {
6835 data
&= ~BMCR_PDOWN
;
6836 r8152_mdio_write(tp
, MII_BMCR
, data
);
6839 r8152_aldps_en(tp
, false);
6841 if (tp
->version
== RTL_VER_01
) {
6842 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_LED_FEATURE
);
6843 ocp_data
&= ~LED_MODE_MASK
;
6844 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_LED_FEATURE
, ocp_data
);
6847 r8152_power_cut_en(tp
, false);
6849 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
6850 ocp_data
|= TX_10M_IDLE_EN
| PFM_PWM_SWITCH
;
6851 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
6852 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL
);
6853 ocp_data
&= ~MCU_CLK_RATIO_MASK
;
6854 ocp_data
|= MCU_CLK_RATIO
| D3_CLK_GATED_EN
;
6855 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL
, ocp_data
);
6856 ocp_data
= GPHY_STS_MSK
| SPEED_DOWN_MSK
|
6857 SPDWN_RXDV_MSK
| SPDWN_LINKCHG_MSK
;
6858 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_GPHY_INTR_IMR
, ocp_data
);
6860 rtl_tally_reset(tp
);
6862 /* enable rx aggregation */
6863 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
6864 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
6865 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
6868 static void r8153_init(struct r8152
*tp
)
6874 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6877 r8153_u1u2en(tp
, false);
6879 for (i
= 0; i
< 500; i
++) {
6880 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
6885 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
6889 data
= r8153_phy_status(tp
, 0);
6891 if (tp
->version
== RTL_VER_03
|| tp
->version
== RTL_VER_04
||
6892 tp
->version
== RTL_VER_05
)
6893 ocp_reg_write(tp
, OCP_ADC_CFG
, CKADSEL_L
| ADC_EN
| EN_EMI_L
);
6895 data
= r8152_mdio_read(tp
, MII_BMCR
);
6896 if (data
& BMCR_PDOWN
) {
6897 data
&= ~BMCR_PDOWN
;
6898 r8152_mdio_write(tp
, MII_BMCR
, data
);
6901 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
6903 r8153_u2p3en(tp
, false);
6905 if (tp
->version
== RTL_VER_04
) {
6906 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_SSPHYLINK2
);
6907 ocp_data
&= ~pwd_dn_scale_mask
;
6908 ocp_data
|= pwd_dn_scale(96);
6909 ocp_write_word(tp
, MCU_TYPE_USB
, USB_SSPHYLINK2
, ocp_data
);
6911 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_USB2PHY
);
6912 ocp_data
|= USB2PHY_L1
| USB2PHY_SUSPEND
;
6913 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_USB2PHY
, ocp_data
);
6914 } else if (tp
->version
== RTL_VER_05
) {
6915 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_DMY_REG0
);
6916 ocp_data
&= ~ECM_ALDPS
;
6917 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_DMY_REG0
, ocp_data
);
6919 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY1
);
6920 if (ocp_read_word(tp
, MCU_TYPE_USB
, USB_BURST_SIZE
) == 0)
6921 ocp_data
&= ~DYNAMIC_BURST
;
6923 ocp_data
|= DYNAMIC_BURST
;
6924 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY1
, ocp_data
);
6925 } else if (tp
->version
== RTL_VER_06
) {
6926 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY1
);
6927 if (ocp_read_word(tp
, MCU_TYPE_USB
, USB_BURST_SIZE
) == 0)
6928 ocp_data
&= ~DYNAMIC_BURST
;
6930 ocp_data
|= DYNAMIC_BURST
;
6931 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY1
, ocp_data
);
6933 r8153_queue_wake(tp
, false);
6935 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
);
6936 if (rtl8152_get_speed(tp
) & LINK_STATUS
)
6937 ocp_data
|= CUR_LINK_OK
;
6939 ocp_data
&= ~CUR_LINK_OK
;
6940 ocp_data
|= POLL_LINK_CHG
;
6941 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
, ocp_data
);
6944 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY2
);
6945 ocp_data
|= EP4_FULL_FC
;
6946 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY2
, ocp_data
);
6948 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_WDT11_CTRL
);
6949 ocp_data
&= ~TIMER11_EN
;
6950 ocp_write_word(tp
, MCU_TYPE_USB
, USB_WDT11_CTRL
, ocp_data
);
6952 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_LED_FEATURE
);
6953 ocp_data
&= ~LED_MODE_MASK
;
6954 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_LED_FEATURE
, ocp_data
);
6956 ocp_data
= FIFO_EMPTY_1FB
| ROK_EXIT_LPM
;
6957 if (tp
->version
== RTL_VER_04
&& tp
->udev
->speed
< USB_SPEED_SUPER
)
6958 ocp_data
|= LPM_TIMER_500MS
;
6960 ocp_data
|= LPM_TIMER_500US
;
6961 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_LPM_CTRL
, ocp_data
);
6963 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_AFE_CTRL2
);
6964 ocp_data
&= ~SEN_VAL_MASK
;
6965 ocp_data
|= SEN_VAL_NORMAL
| SEL_RXIDLE
;
6966 ocp_write_word(tp
, MCU_TYPE_USB
, USB_AFE_CTRL2
, ocp_data
);
6968 ocp_write_word(tp
, MCU_TYPE_USB
, USB_CONNECT_TIMER
, 0x0001);
6970 r8153_power_cut_en(tp
, false);
6971 rtl_runtime_suspend_enable(tp
, false);
6972 r8153_mac_clk_speed_down(tp
, false);
6973 r8153_u1u2en(tp
, true);
6974 usb_enable_lpm(tp
->udev
);
6976 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CONFIG6
);
6977 ocp_data
|= LANWAKE_CLR_EN
;
6978 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CONFIG6
, ocp_data
);
6980 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_LWAKE_CTRL_REG
);
6981 ocp_data
&= ~LANWAKE_PIN
;
6982 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_LWAKE_CTRL_REG
, ocp_data
);
6984 /* rx aggregation */
6985 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
6986 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
6987 if (tp
->dell_tb_rx_agg_bug
)
6988 ocp_data
|= RX_AGG_DISABLE
;
6990 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
6992 rtl_tally_reset(tp
);
6994 switch (tp
->udev
->speed
) {
6995 case USB_SPEED_SUPER
:
6996 case USB_SPEED_SUPER_PLUS
:
6997 tp
->coalesce
= COALESCE_SUPER
;
6999 case USB_SPEED_HIGH
:
7000 tp
->coalesce
= COALESCE_HIGH
;
7003 tp
->coalesce
= COALESCE_SLOW
;
7008 static void r8153b_init(struct r8152
*tp
)
7014 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
7017 r8153b_u1u2en(tp
, false);
7019 for (i
= 0; i
< 500; i
++) {
7020 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
7025 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
7029 data
= r8153_phy_status(tp
, 0);
7031 data
= r8152_mdio_read(tp
, MII_BMCR
);
7032 if (data
& BMCR_PDOWN
) {
7033 data
&= ~BMCR_PDOWN
;
7034 r8152_mdio_write(tp
, MII_BMCR
, data
);
7037 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
7039 r8153_u2p3en(tp
, false);
7041 /* MSC timer = 0xfff * 8ms = 32760 ms */
7042 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MSC_TIMER
, 0x0fff);
7044 r8153b_power_cut_en(tp
, false);
7045 r8153b_ups_en(tp
, false);
7046 r8153_queue_wake(tp
, false);
7047 rtl_runtime_suspend_enable(tp
, false);
7049 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
);
7050 if (rtl8152_get_speed(tp
) & LINK_STATUS
)
7051 ocp_data
|= CUR_LINK_OK
;
7053 ocp_data
&= ~CUR_LINK_OK
;
7054 ocp_data
|= POLL_LINK_CHG
;
7055 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
, ocp_data
);
7057 if (tp
->udev
->speed
>= USB_SPEED_SUPER
)
7058 r8153b_u1u2en(tp
, true);
7060 usb_enable_lpm(tp
->udev
);
7062 /* MAC clock speed down */
7063 r8153_mac_clk_speed_down(tp
, true);
7065 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
);
7066 ocp_data
&= ~PLA_MCU_SPDWN_EN
;
7067 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, ocp_data
);
7069 if (tp
->version
== RTL_VER_09
) {
7070 /* Disable Test IO for 32QFN */
7071 if (ocp_read_byte(tp
, MCU_TYPE_PLA
, 0xdc00) & BIT(5)) {
7072 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
7073 ocp_data
|= TEST_IO_OFF
;
7074 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
7078 set_bit(GREEN_ETHERNET
, &tp
->flags
);
7080 /* rx aggregation */
7081 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
7082 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
7083 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
7085 rtl_tally_reset(tp
);
7087 tp
->coalesce
= 15000; /* 15 us */
7090 static void r8153c_init(struct r8152
*tp
)
7096 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
7099 r8153b_u1u2en(tp
, false);
7101 /* Disable spi_en */
7102 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
7103 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG5
);
7104 ocp_data
&= ~BIT(3);
7105 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG5
, ocp_data
);
7106 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, 0xcbf0);
7108 ocp_write_word(tp
, MCU_TYPE_USB
, 0xcbf0, ocp_data
);
7110 for (i
= 0; i
< 500; i
++) {
7111 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
7116 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
7120 data
= r8153_phy_status(tp
, 0);
7122 data
= r8152_mdio_read(tp
, MII_BMCR
);
7123 if (data
& BMCR_PDOWN
) {
7124 data
&= ~BMCR_PDOWN
;
7125 r8152_mdio_write(tp
, MII_BMCR
, data
);
7128 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
7130 r8153_u2p3en(tp
, false);
7132 /* MSC timer = 0xfff * 8ms = 32760 ms */
7133 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MSC_TIMER
, 0x0fff);
7135 r8153b_power_cut_en(tp
, false);
7136 r8153c_ups_en(tp
, false);
7137 r8153_queue_wake(tp
, false);
7138 rtl_runtime_suspend_enable(tp
, false);
7140 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
);
7141 if (rtl8152_get_speed(tp
) & LINK_STATUS
)
7142 ocp_data
|= CUR_LINK_OK
;
7144 ocp_data
&= ~CUR_LINK_OK
;
7146 ocp_data
|= POLL_LINK_CHG
;
7147 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
, ocp_data
);
7149 r8153b_u1u2en(tp
, true);
7151 usb_enable_lpm(tp
->udev
);
7153 /* MAC clock speed down */
7154 r8153_mac_clk_speed_down(tp
, true);
7156 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
);
7157 ocp_data
&= ~BIT(7);
7158 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_MISC_2
, ocp_data
);
7160 set_bit(GREEN_ETHERNET
, &tp
->flags
);
7162 /* rx aggregation */
7163 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
7164 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
7165 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
7167 rtl_tally_reset(tp
);
7169 tp
->coalesce
= 15000; /* 15 us */
7172 static void r8156_hw_phy_cfg(struct r8152
*tp
)
7177 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
7178 if (ocp_data
& PCUT_STATUS
) {
7179 ocp_data
&= ~PCUT_STATUS
;
7180 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MISC_0
, ocp_data
);
7183 data
= r8153_phy_status(tp
, 0);
7185 case PHY_STAT_EXT_INIT
:
7186 rtl8152_apply_firmware(tp
, true);
7188 data
= ocp_reg_read(tp
, 0xa468);
7189 data
&= ~(BIT(3) | BIT(1));
7190 ocp_reg_write(tp
, 0xa468, data
);
7192 case PHY_STAT_LAN_ON
:
7193 case PHY_STAT_PWRDN
:
7195 rtl8152_apply_firmware(tp
, false);
7199 /* disable ALDPS before updating the PHY parameters */
7200 r8153_aldps_en(tp
, false);
7202 /* disable EEE before updating the PHY parameters */
7203 rtl_eee_enable(tp
, false);
7205 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
7206 WARN_ON_ONCE(data
!= PHY_STAT_LAN_ON
);
7208 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
7209 ocp_data
|= PFM_PWM_SWITCH
;
7210 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
7212 switch (tp
->version
) {
7214 data
= ocp_reg_read(tp
, 0xad40);
7216 data
|= BIT(7) | BIT(2);
7217 ocp_reg_write(tp
, 0xad40, data
);
7219 data
= ocp_reg_read(tp
, 0xad4e);
7221 ocp_reg_write(tp
, 0xad4e, data
);
7222 data
= ocp_reg_read(tp
, 0xad16);
7225 ocp_reg_write(tp
, 0xad16, data
);
7226 data
= ocp_reg_read(tp
, 0xad32);
7229 ocp_reg_write(tp
, 0xad32, data
);
7230 data
= ocp_reg_read(tp
, 0xac08);
7231 data
&= ~(BIT(12) | BIT(8));
7232 ocp_reg_write(tp
, 0xac08, data
);
7233 data
= ocp_reg_read(tp
, 0xac8a);
7234 data
|= BIT(12) | BIT(13) | BIT(14);
7236 ocp_reg_write(tp
, 0xac8a, data
);
7237 data
= ocp_reg_read(tp
, 0xad18);
7239 ocp_reg_write(tp
, 0xad18, data
);
7240 data
= ocp_reg_read(tp
, 0xad1a);
7242 ocp_reg_write(tp
, 0xad1a, data
);
7243 data
= ocp_reg_read(tp
, 0xad1c);
7245 ocp_reg_write(tp
, 0xad1c, data
);
7247 data
= sram_read(tp
, 0x80ea);
7250 sram_write(tp
, 0x80ea, data
);
7251 data
= sram_read(tp
, 0x80eb);
7254 sram_write(tp
, 0x80eb, data
);
7255 data
= sram_read(tp
, 0x80f8);
7258 sram_write(tp
, 0x80f8, data
);
7259 data
= sram_read(tp
, 0x80f1);
7262 sram_write(tp
, 0x80f1, data
);
7264 data
= sram_read(tp
, 0x80fe);
7267 sram_write(tp
, 0x80fe, data
);
7268 data
= sram_read(tp
, 0x8102);
7271 sram_write(tp
, 0x8102, data
);
7272 data
= sram_read(tp
, 0x8015);
7275 sram_write(tp
, 0x8015, data
);
7276 data
= sram_read(tp
, 0x8100);
7279 sram_write(tp
, 0x8100, data
);
7280 data
= sram_read(tp
, 0x8014);
7283 sram_write(tp
, 0x8014, data
);
7284 data
= sram_read(tp
, 0x8016);
7287 sram_write(tp
, 0x8016, data
);
7288 data
= sram_read(tp
, 0x80dc);
7291 sram_write(tp
, 0x80dc, data
);
7292 data
= sram_read(tp
, 0x80df);
7294 sram_write(tp
, 0x80df, data
);
7295 data
= sram_read(tp
, 0x80e1);
7297 sram_write(tp
, 0x80e1, data
);
7299 data
= ocp_reg_read(tp
, 0xbf06);
7302 ocp_reg_write(tp
, 0xbf06, data
);
7304 sram_write(tp
, 0x819f, 0xddb6);
7306 ocp_reg_write(tp
, 0xbc34, 0x5555);
7307 data
= ocp_reg_read(tp
, 0xbf0a);
7310 ocp_reg_write(tp
, 0xbf0a, data
);
7312 data
= ocp_reg_read(tp
, 0xbd2c);
7314 ocp_reg_write(tp
, 0xbd2c, data
);
7317 data
= ocp_reg_read(tp
, 0xad16);
7319 ocp_reg_write(tp
, 0xad16, data
);
7320 data
= ocp_reg_read(tp
, 0xad32);
7323 ocp_reg_write(tp
, 0xad32, data
);
7324 data
= ocp_reg_read(tp
, 0xac08);
7325 data
&= ~(BIT(12) | BIT(8));
7326 ocp_reg_write(tp
, 0xac08, data
);
7327 data
= ocp_reg_read(tp
, 0xacc0);
7330 ocp_reg_write(tp
, 0xacc0, data
);
7331 data
= ocp_reg_read(tp
, 0xad40);
7333 data
|= BIT(6) | BIT(2);
7334 ocp_reg_write(tp
, 0xad40, data
);
7335 data
= ocp_reg_read(tp
, 0xac14);
7337 ocp_reg_write(tp
, 0xac14, data
);
7338 data
= ocp_reg_read(tp
, 0xac80);
7339 data
&= ~(BIT(8) | BIT(9));
7340 ocp_reg_write(tp
, 0xac80, data
);
7341 data
= ocp_reg_read(tp
, 0xac5e);
7344 ocp_reg_write(tp
, 0xac5e, data
);
7345 ocp_reg_write(tp
, 0xad4c, 0x00a8);
7346 ocp_reg_write(tp
, 0xac5c, 0x01ff);
7347 data
= ocp_reg_read(tp
, 0xac8a);
7349 data
|= BIT(4) | BIT(5);
7350 ocp_reg_write(tp
, 0xac8a, data
);
7351 ocp_reg_write(tp
, 0xb87c, 0x8157);
7352 data
= ocp_reg_read(tp
, 0xb87e);
7355 ocp_reg_write(tp
, 0xb87e, data
);
7356 ocp_reg_write(tp
, 0xb87c, 0x8159);
7357 data
= ocp_reg_read(tp
, 0xb87e);
7360 ocp_reg_write(tp
, 0xb87e, data
);
7363 ocp_reg_write(tp
, 0xb87c, 0x80a2);
7364 ocp_reg_write(tp
, 0xb87e, 0x0153);
7365 ocp_reg_write(tp
, 0xb87c, 0x809c);
7366 ocp_reg_write(tp
, 0xb87e, 0x0153);
7369 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEE_TXTWSYS_2P5G
, 0x0056);
7371 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_USB_CFG
);
7372 ocp_data
|= EN_XG_LIP
| EN_G_LIP
;
7373 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_USB_CFG
, ocp_data
);
7375 sram_write(tp
, 0x8257, 0x020f); /* XG PLL */
7376 sram_write(tp
, 0x80ea, 0x7843); /* GIGA Master */
7378 if (rtl_phy_patch_request(tp
, true, true))
7382 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
);
7383 ocp_data
|= EEE_SPDWN_EN
;
7384 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
, ocp_data
);
7386 data
= ocp_reg_read(tp
, OCP_DOWN_SPEED
);
7387 data
&= ~(EN_EEE_100
| EN_EEE_1000
);
7388 data
|= EN_10M_CLKDIV
;
7389 ocp_reg_write(tp
, OCP_DOWN_SPEED
, data
);
7390 tp
->ups_info
._10m_ckdiv
= true;
7391 tp
->ups_info
.eee_plloff_100
= false;
7392 tp
->ups_info
.eee_plloff_giga
= false;
7394 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
7395 data
&= ~EEE_CLKDIV_EN
;
7396 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
7397 tp
->ups_info
.eee_ckdiv
= false;
7399 ocp_reg_write(tp
, OCP_SYSCLK_CFG
, 0);
7400 ocp_reg_write(tp
, OCP_SYSCLK_CFG
, sysclk_div_expo(5));
7401 tp
->ups_info
._250m_ckdiv
= false;
7403 rtl_phy_patch_request(tp
, false, true);
7405 /* enable ADC Ibias Cal */
7406 data
= ocp_reg_read(tp
, 0xd068);
7408 ocp_reg_write(tp
, 0xd068, data
);
7410 /* enable Thermal Sensor */
7411 data
= sram_read(tp
, 0x81a2);
7413 sram_write(tp
, 0x81a2, data
);
7414 data
= ocp_reg_read(tp
, 0xb54c);
7417 ocp_reg_write(tp
, 0xb54c, data
);
7419 /* Nway 2.5G Lite */
7420 data
= ocp_reg_read(tp
, 0xa454);
7422 ocp_reg_write(tp
, 0xa454, data
);
7424 /* CS DSP solution */
7425 data
= ocp_reg_read(tp
, OCP_10GBT_CTRL
);
7426 data
|= RTL_ADV2_5G_F_R
;
7427 ocp_reg_write(tp
, OCP_10GBT_CTRL
, data
);
7428 data
= ocp_reg_read(tp
, 0xad4e);
7430 ocp_reg_write(tp
, 0xad4e, data
);
7431 data
= ocp_reg_read(tp
, 0xa86a);
7433 ocp_reg_write(tp
, 0xa86a, data
);
7436 if ((ocp_read_word(tp
, MCU_TYPE_USB
, USB_UPS_CFG
) & MID_REVERSE
) &&
7437 (ocp_reg_read(tp
, 0xd068) & BIT(1))) {
7440 data
= ocp_reg_read(tp
, 0xd068);
7442 data
|= 0x1; /* p0 */
7443 ocp_reg_write(tp
, 0xd068, data
);
7444 swap_a
= ocp_reg_read(tp
, 0xd06a);
7446 data
|= 0x18; /* p3 */
7447 ocp_reg_write(tp
, 0xd068, data
);
7448 swap_b
= ocp_reg_read(tp
, 0xd06a);
7449 data
&= ~0x18; /* p0 */
7450 ocp_reg_write(tp
, 0xd068, data
);
7451 ocp_reg_write(tp
, 0xd06a,
7452 (swap_a
& ~0x7ff) | (swap_b
& 0x7ff));
7453 data
|= 0x18; /* p3 */
7454 ocp_reg_write(tp
, 0xd068, data
);
7455 ocp_reg_write(tp
, 0xd06a,
7456 (swap_b
& ~0x7ff) | (swap_a
& 0x7ff));
7458 data
|= 0x08; /* p1 */
7459 ocp_reg_write(tp
, 0xd068, data
);
7460 swap_a
= ocp_reg_read(tp
, 0xd06a);
7462 data
|= 0x10; /* p2 */
7463 ocp_reg_write(tp
, 0xd068, data
);
7464 swap_b
= ocp_reg_read(tp
, 0xd06a);
7466 data
|= 0x08; /* p1 */
7467 ocp_reg_write(tp
, 0xd068, data
);
7468 ocp_reg_write(tp
, 0xd06a,
7469 (swap_a
& ~0x7ff) | (swap_b
& 0x7ff));
7471 data
|= 0x10; /* p2 */
7472 ocp_reg_write(tp
, 0xd068, data
);
7473 ocp_reg_write(tp
, 0xd06a,
7474 (swap_b
& ~0x7ff) | (swap_a
& 0x7ff));
7475 swap_a
= ocp_reg_read(tp
, 0xbd5a);
7476 swap_b
= ocp_reg_read(tp
, 0xbd5c);
7477 ocp_reg_write(tp
, 0xbd5a, (swap_a
& ~0x1f1f) |
7478 ((swap_b
& 0x1f) << 8) |
7479 ((swap_b
>> 8) & 0x1f));
7480 ocp_reg_write(tp
, 0xbd5c, (swap_b
& ~0x1f1f) |
7481 ((swap_a
& 0x1f) << 8) |
7482 ((swap_a
>> 8) & 0x1f));
7483 swap_a
= ocp_reg_read(tp
, 0xbc18);
7484 swap_b
= ocp_reg_read(tp
, 0xbc1a);
7485 ocp_reg_write(tp
, 0xbc18, (swap_a
& ~0x1f1f) |
7486 ((swap_b
& 0x1f) << 8) |
7487 ((swap_b
>> 8) & 0x1f));
7488 ocp_reg_write(tp
, 0xbc1a, (swap_b
& ~0x1f1f) |
7489 ((swap_a
& 0x1f) << 8) |
7490 ((swap_a
>> 8) & 0x1f));
7497 rtl_green_en(tp
, test_bit(GREEN_ETHERNET
, &tp
->flags
));
7499 data
= ocp_reg_read(tp
, 0xa428);
7501 ocp_reg_write(tp
, 0xa428, data
);
7502 data
= ocp_reg_read(tp
, 0xa5ea);
7504 ocp_reg_write(tp
, 0xa5ea, data
);
7505 tp
->ups_info
.lite_mode
= 0;
7508 rtl_eee_enable(tp
, true);
7510 r8153_aldps_en(tp
, true);
7511 r8152b_enable_fc(tp
);
7512 r8153_u2p3en(tp
, true);
7514 set_bit(PHY_RESET
, &tp
->flags
);
7517 static void r8156b_hw_phy_cfg(struct r8152
*tp
)
7522 switch (tp
->version
) {
7524 ocp_reg_write(tp
, 0xbf86, 0x9000);
7525 data
= ocp_reg_read(tp
, 0xc402);
7527 ocp_reg_write(tp
, 0xc402, data
);
7529 ocp_reg_write(tp
, 0xc402, data
);
7530 ocp_reg_write(tp
, 0xbd86, 0x1010);
7531 ocp_reg_write(tp
, 0xbd88, 0x1010);
7532 data
= ocp_reg_read(tp
, 0xbd4e);
7533 data
&= ~(BIT(10) | BIT(11));
7535 ocp_reg_write(tp
, 0xbd4e, data
);
7536 data
= ocp_reg_read(tp
, 0xbf46);
7539 ocp_reg_write(tp
, 0xbf46, data
);
7543 r8156b_wait_loading_flash(tp
);
7549 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
7550 if (ocp_data
& PCUT_STATUS
) {
7551 ocp_data
&= ~PCUT_STATUS
;
7552 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MISC_0
, ocp_data
);
7555 data
= r8153_phy_status(tp
, 0);
7557 case PHY_STAT_EXT_INIT
:
7558 rtl8152_apply_firmware(tp
, true);
7560 data
= ocp_reg_read(tp
, 0xa466);
7562 ocp_reg_write(tp
, 0xa466, data
);
7564 data
= ocp_reg_read(tp
, 0xa468);
7565 data
&= ~(BIT(3) | BIT(1));
7566 ocp_reg_write(tp
, 0xa468, data
);
7568 case PHY_STAT_LAN_ON
:
7569 case PHY_STAT_PWRDN
:
7571 rtl8152_apply_firmware(tp
, false);
7575 data
= r8152_mdio_read(tp
, MII_BMCR
);
7576 if (data
& BMCR_PDOWN
) {
7577 data
&= ~BMCR_PDOWN
;
7578 r8152_mdio_write(tp
, MII_BMCR
, data
);
7581 /* disable ALDPS before updating the PHY parameters */
7582 r8153_aldps_en(tp
, false);
7584 /* disable EEE before updating the PHY parameters */
7585 rtl_eee_enable(tp
, false);
7587 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
7588 WARN_ON_ONCE(data
!= PHY_STAT_LAN_ON
);
7590 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
7591 ocp_data
|= PFM_PWM_SWITCH
;
7592 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
7594 switch (tp
->version
) {
7596 data
= ocp_reg_read(tp
, 0xbc08);
7597 data
|= BIT(3) | BIT(2);
7598 ocp_reg_write(tp
, 0xbc08, data
);
7600 data
= sram_read(tp
, 0x8fff);
7603 sram_write(tp
, 0x8fff, data
);
7605 data
= ocp_reg_read(tp
, 0xacda);
7607 ocp_reg_write(tp
, 0xacda, data
);
7608 data
= ocp_reg_read(tp
, 0xacde);
7610 ocp_reg_write(tp
, 0xacde, data
);
7611 ocp_reg_write(tp
, 0xac8c, 0x0ffc);
7612 ocp_reg_write(tp
, 0xac46, 0xb7b4);
7613 ocp_reg_write(tp
, 0xac50, 0x0fbc);
7614 ocp_reg_write(tp
, 0xac3c, 0x9240);
7615 ocp_reg_write(tp
, 0xac4e, 0x0db4);
7616 ocp_reg_write(tp
, 0xacc6, 0x0707);
7617 ocp_reg_write(tp
, 0xacc8, 0xa0d3);
7618 ocp_reg_write(tp
, 0xad08, 0x0007);
7620 ocp_reg_write(tp
, 0xb87c, 0x8560);
7621 ocp_reg_write(tp
, 0xb87e, 0x19cc);
7622 ocp_reg_write(tp
, 0xb87c, 0x8562);
7623 ocp_reg_write(tp
, 0xb87e, 0x19cc);
7624 ocp_reg_write(tp
, 0xb87c, 0x8564);
7625 ocp_reg_write(tp
, 0xb87e, 0x19cc);
7626 ocp_reg_write(tp
, 0xb87c, 0x8566);
7627 ocp_reg_write(tp
, 0xb87e, 0x147d);
7628 ocp_reg_write(tp
, 0xb87c, 0x8568);
7629 ocp_reg_write(tp
, 0xb87e, 0x147d);
7630 ocp_reg_write(tp
, 0xb87c, 0x856a);
7631 ocp_reg_write(tp
, 0xb87e, 0x147d);
7632 ocp_reg_write(tp
, 0xb87c, 0x8ffe);
7633 ocp_reg_write(tp
, 0xb87e, 0x0907);
7634 ocp_reg_write(tp
, 0xb87c, 0x80d6);
7635 ocp_reg_write(tp
, 0xb87e, 0x2801);
7636 ocp_reg_write(tp
, 0xb87c, 0x80f2);
7637 ocp_reg_write(tp
, 0xb87e, 0x2801);
7638 ocp_reg_write(tp
, 0xb87c, 0x80f4);
7639 ocp_reg_write(tp
, 0xb87e, 0x6077);
7640 ocp_reg_write(tp
, 0xb506, 0x01e7);
7642 ocp_reg_write(tp
, 0xb87c, 0x8013);
7643 ocp_reg_write(tp
, 0xb87e, 0x0700);
7644 ocp_reg_write(tp
, 0xb87c, 0x8fb9);
7645 ocp_reg_write(tp
, 0xb87e, 0x2801);
7646 ocp_reg_write(tp
, 0xb87c, 0x8fba);
7647 ocp_reg_write(tp
, 0xb87e, 0x0100);
7648 ocp_reg_write(tp
, 0xb87c, 0x8fbc);
7649 ocp_reg_write(tp
, 0xb87e, 0x1900);
7650 ocp_reg_write(tp
, 0xb87c, 0x8fbe);
7651 ocp_reg_write(tp
, 0xb87e, 0xe100);
7652 ocp_reg_write(tp
, 0xb87c, 0x8fc0);
7653 ocp_reg_write(tp
, 0xb87e, 0x0800);
7654 ocp_reg_write(tp
, 0xb87c, 0x8fc2);
7655 ocp_reg_write(tp
, 0xb87e, 0xe500);
7656 ocp_reg_write(tp
, 0xb87c, 0x8fc4);
7657 ocp_reg_write(tp
, 0xb87e, 0x0f00);
7658 ocp_reg_write(tp
, 0xb87c, 0x8fc6);
7659 ocp_reg_write(tp
, 0xb87e, 0xf100);
7660 ocp_reg_write(tp
, 0xb87c, 0x8fc8);
7661 ocp_reg_write(tp
, 0xb87e, 0x0400);
7662 ocp_reg_write(tp
, 0xb87c, 0x8fca);
7663 ocp_reg_write(tp
, 0xb87e, 0xf300);
7664 ocp_reg_write(tp
, 0xb87c, 0x8fcc);
7665 ocp_reg_write(tp
, 0xb87e, 0xfd00);
7666 ocp_reg_write(tp
, 0xb87c, 0x8fce);
7667 ocp_reg_write(tp
, 0xb87e, 0xff00);
7668 ocp_reg_write(tp
, 0xb87c, 0x8fd0);
7669 ocp_reg_write(tp
, 0xb87e, 0xfb00);
7670 ocp_reg_write(tp
, 0xb87c, 0x8fd2);
7671 ocp_reg_write(tp
, 0xb87e, 0x0100);
7672 ocp_reg_write(tp
, 0xb87c, 0x8fd4);
7673 ocp_reg_write(tp
, 0xb87e, 0xf400);
7674 ocp_reg_write(tp
, 0xb87c, 0x8fd6);
7675 ocp_reg_write(tp
, 0xb87e, 0xff00);
7676 ocp_reg_write(tp
, 0xb87c, 0x8fd8);
7677 ocp_reg_write(tp
, 0xb87e, 0xf600);
7679 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_USB_CFG
);
7680 ocp_data
|= EN_XG_LIP
| EN_G_LIP
;
7681 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_USB_CFG
, ocp_data
);
7682 ocp_reg_write(tp
, 0xb87c, 0x813d);
7683 ocp_reg_write(tp
, 0xb87e, 0x390e);
7684 ocp_reg_write(tp
, 0xb87c, 0x814f);
7685 ocp_reg_write(tp
, 0xb87e, 0x790e);
7686 ocp_reg_write(tp
, 0xb87c, 0x80b0);
7687 ocp_reg_write(tp
, 0xb87e, 0x0f31);
7688 data
= ocp_reg_read(tp
, 0xbf4c);
7690 ocp_reg_write(tp
, 0xbf4c, data
);
7691 data
= ocp_reg_read(tp
, 0xbcca);
7692 data
|= BIT(9) | BIT(8);
7693 ocp_reg_write(tp
, 0xbcca, data
);
7694 ocp_reg_write(tp
, 0xb87c, 0x8141);
7695 ocp_reg_write(tp
, 0xb87e, 0x320e);
7696 ocp_reg_write(tp
, 0xb87c, 0x8153);
7697 ocp_reg_write(tp
, 0xb87e, 0x720e);
7698 ocp_reg_write(tp
, 0xb87c, 0x8529);
7699 ocp_reg_write(tp
, 0xb87e, 0x050e);
7700 data
= ocp_reg_read(tp
, OCP_EEE_CFG
);
7701 data
&= ~CTAP_SHORT_EN
;
7702 ocp_reg_write(tp
, OCP_EEE_CFG
, data
);
7704 sram_write(tp
, 0x816c, 0xc4a0);
7705 sram_write(tp
, 0x8170, 0xc4a0);
7706 sram_write(tp
, 0x8174, 0x04a0);
7707 sram_write(tp
, 0x8178, 0x04a0);
7708 sram_write(tp
, 0x817c, 0x0719);
7709 sram_write(tp
, 0x8ff4, 0x0400);
7710 sram_write(tp
, 0x8ff1, 0x0404);
7712 ocp_reg_write(tp
, 0xbf4a, 0x001b);
7713 ocp_reg_write(tp
, 0xb87c, 0x8033);
7714 ocp_reg_write(tp
, 0xb87e, 0x7c13);
7715 ocp_reg_write(tp
, 0xb87c, 0x8037);
7716 ocp_reg_write(tp
, 0xb87e, 0x7c13);
7717 ocp_reg_write(tp
, 0xb87c, 0x803b);
7718 ocp_reg_write(tp
, 0xb87e, 0xfc32);
7719 ocp_reg_write(tp
, 0xb87c, 0x803f);
7720 ocp_reg_write(tp
, 0xb87e, 0x7c13);
7721 ocp_reg_write(tp
, 0xb87c, 0x8043);
7722 ocp_reg_write(tp
, 0xb87e, 0x7c13);
7723 ocp_reg_write(tp
, 0xb87c, 0x8047);
7724 ocp_reg_write(tp
, 0xb87e, 0x7c13);
7726 ocp_reg_write(tp
, 0xb87c, 0x8145);
7727 ocp_reg_write(tp
, 0xb87e, 0x370e);
7728 ocp_reg_write(tp
, 0xb87c, 0x8157);
7729 ocp_reg_write(tp
, 0xb87e, 0x770e);
7730 ocp_reg_write(tp
, 0xb87c, 0x8169);
7731 ocp_reg_write(tp
, 0xb87e, 0x0d0a);
7732 ocp_reg_write(tp
, 0xb87c, 0x817b);
7733 ocp_reg_write(tp
, 0xb87e, 0x1d0a);
7735 data
= sram_read(tp
, 0x8217);
7738 sram_write(tp
, 0x8217, data
);
7739 data
= sram_read(tp
, 0x821a);
7742 sram_write(tp
, 0x821a, data
);
7743 sram_write(tp
, 0x80da, 0x0403);
7744 data
= sram_read(tp
, 0x80dc);
7747 sram_write(tp
, 0x80dc, data
);
7748 sram_write(tp
, 0x80b3, 0x0384);
7749 sram_write(tp
, 0x80b7, 0x2007);
7750 data
= sram_read(tp
, 0x80ba);
7753 sram_write(tp
, 0x80ba, data
);
7754 sram_write(tp
, 0x80b5, 0xf009);
7755 data
= sram_read(tp
, 0x80bd);
7758 sram_write(tp
, 0x80bd, data
);
7759 sram_write(tp
, 0x80c7, 0xf083);
7760 sram_write(tp
, 0x80dd, 0x03f0);
7761 data
= sram_read(tp
, 0x80df);
7764 sram_write(tp
, 0x80df, data
);
7765 sram_write(tp
, 0x80cb, 0x2007);
7766 data
= sram_read(tp
, 0x80ce);
7769 sram_write(tp
, 0x80ce, data
);
7770 sram_write(tp
, 0x80c9, 0x8009);
7771 data
= sram_read(tp
, 0x80d1);
7774 sram_write(tp
, 0x80d1, data
);
7775 sram_write(tp
, 0x80a3, 0x200a);
7776 sram_write(tp
, 0x80a5, 0xf0ad);
7777 sram_write(tp
, 0x809f, 0x6073);
7778 sram_write(tp
, 0x80a1, 0x000b);
7779 data
= sram_read(tp
, 0x80a9);
7782 sram_write(tp
, 0x80a9, data
);
7784 if (rtl_phy_patch_request(tp
, true, true))
7787 data
= ocp_reg_read(tp
, 0xb896);
7789 ocp_reg_write(tp
, 0xb896, data
);
7790 data
= ocp_reg_read(tp
, 0xb892);
7792 ocp_reg_write(tp
, 0xb892, data
);
7793 ocp_reg_write(tp
, 0xb88e, 0xc23e);
7794 ocp_reg_write(tp
, 0xb890, 0x0000);
7795 ocp_reg_write(tp
, 0xb88e, 0xc240);
7796 ocp_reg_write(tp
, 0xb890, 0x0103);
7797 ocp_reg_write(tp
, 0xb88e, 0xc242);
7798 ocp_reg_write(tp
, 0xb890, 0x0507);
7799 ocp_reg_write(tp
, 0xb88e, 0xc244);
7800 ocp_reg_write(tp
, 0xb890, 0x090b);
7801 ocp_reg_write(tp
, 0xb88e, 0xc246);
7802 ocp_reg_write(tp
, 0xb890, 0x0c0e);
7803 ocp_reg_write(tp
, 0xb88e, 0xc248);
7804 ocp_reg_write(tp
, 0xb890, 0x1012);
7805 ocp_reg_write(tp
, 0xb88e, 0xc24a);
7806 ocp_reg_write(tp
, 0xb890, 0x1416);
7807 data
= ocp_reg_read(tp
, 0xb896);
7809 ocp_reg_write(tp
, 0xb896, data
);
7811 rtl_phy_patch_request(tp
, false, true);
7813 data
= ocp_reg_read(tp
, 0xa86a);
7815 ocp_reg_write(tp
, 0xa86a, data
);
7816 data
= ocp_reg_read(tp
, 0xa6f0);
7818 ocp_reg_write(tp
, 0xa6f0, data
);
7820 ocp_reg_write(tp
, 0xbfa0, 0xd70d);
7821 ocp_reg_write(tp
, 0xbfa2, 0x4100);
7822 ocp_reg_write(tp
, 0xbfa4, 0xe868);
7823 ocp_reg_write(tp
, 0xbfa6, 0xdc59);
7824 ocp_reg_write(tp
, 0xb54c, 0x3c18);
7825 data
= ocp_reg_read(tp
, 0xbfa4);
7827 ocp_reg_write(tp
, 0xbfa4, data
);
7828 data
= sram_read(tp
, 0x817d);
7830 sram_write(tp
, 0x817d, data
);
7834 data
= ocp_reg_read(tp
, 0xac46);
7837 ocp_reg_write(tp
, 0xac46, data
);
7838 data
= ocp_reg_read(tp
, 0xad30);
7841 ocp_reg_write(tp
, 0xad30, data
);
7845 ocp_reg_write(tp
, 0xb87c, 0x80f5);
7846 ocp_reg_write(tp
, 0xb87e, 0x760e);
7847 ocp_reg_write(tp
, 0xb87c, 0x8107);
7848 ocp_reg_write(tp
, 0xb87e, 0x360e);
7849 ocp_reg_write(tp
, 0xb87c, 0x8551);
7850 data
= ocp_reg_read(tp
, 0xb87e);
7853 ocp_reg_write(tp
, 0xb87e, data
);
7855 /* ADC_PGA parameter */
7856 data
= ocp_reg_read(tp
, 0xbf00);
7859 ocp_reg_write(tp
, 0xbf00, data
);
7860 data
= ocp_reg_read(tp
, 0xbf46);
7863 ocp_reg_write(tp
, 0xbf46, data
);
7865 /* Green Table-PGA, 1G full viterbi */
7866 sram_write(tp
, 0x8044, 0x2417);
7867 sram_write(tp
, 0x804a, 0x2417);
7868 sram_write(tp
, 0x8050, 0x2417);
7869 sram_write(tp
, 0x8056, 0x2417);
7870 sram_write(tp
, 0x805c, 0x2417);
7871 sram_write(tp
, 0x8062, 0x2417);
7872 sram_write(tp
, 0x8068, 0x2417);
7873 sram_write(tp
, 0x806e, 0x2417);
7874 sram_write(tp
, 0x8074, 0x2417);
7875 sram_write(tp
, 0x807a, 0x2417);
7878 data
= ocp_reg_read(tp
, 0xbf84);
7881 ocp_reg_write(tp
, 0xbf84, data
);
7887 if (rtl_phy_patch_request(tp
, true, true))
7890 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
);
7891 ocp_data
|= EEE_SPDWN_EN
;
7892 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
, ocp_data
);
7894 data
= ocp_reg_read(tp
, OCP_DOWN_SPEED
);
7895 data
&= ~(EN_EEE_100
| EN_EEE_1000
);
7896 data
|= EN_10M_CLKDIV
;
7897 ocp_reg_write(tp
, OCP_DOWN_SPEED
, data
);
7898 tp
->ups_info
._10m_ckdiv
= true;
7899 tp
->ups_info
.eee_plloff_100
= false;
7900 tp
->ups_info
.eee_plloff_giga
= false;
7902 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
7903 data
&= ~EEE_CLKDIV_EN
;
7904 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
7905 tp
->ups_info
.eee_ckdiv
= false;
7907 rtl_phy_patch_request(tp
, false, true);
7909 rtl_green_en(tp
, test_bit(GREEN_ETHERNET
, &tp
->flags
));
7911 data
= ocp_reg_read(tp
, 0xa428);
7913 ocp_reg_write(tp
, 0xa428, data
);
7914 data
= ocp_reg_read(tp
, 0xa5ea);
7916 ocp_reg_write(tp
, 0xa5ea, data
);
7917 tp
->ups_info
.lite_mode
= 0;
7920 rtl_eee_enable(tp
, true);
7922 r8153_aldps_en(tp
, true);
7923 r8152b_enable_fc(tp
);
7924 r8153_u2p3en(tp
, true);
7926 set_bit(PHY_RESET
, &tp
->flags
);
7929 static void r8156_init(struct r8152
*tp
)
7935 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
7938 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_ECM_OP
);
7939 ocp_data
&= ~EN_ALL_SPEED
;
7940 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_ECM_OP
, ocp_data
);
7942 ocp_write_word(tp
, MCU_TYPE_USB
, USB_SPEED_OPTION
, 0);
7944 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_ECM_OPTION
);
7945 ocp_data
|= BYPASS_MAC_RESET
;
7946 ocp_write_word(tp
, MCU_TYPE_USB
, USB_ECM_OPTION
, ocp_data
);
7948 r8153b_u1u2en(tp
, false);
7950 for (i
= 0; i
< 500; i
++) {
7951 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
7956 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
7960 data
= r8153_phy_status(tp
, 0);
7961 if (data
== PHY_STAT_EXT_INIT
) {
7962 data
= ocp_reg_read(tp
, 0xa468);
7963 data
&= ~(BIT(3) | BIT(1));
7964 ocp_reg_write(tp
, 0xa468, data
);
7967 data
= r8152_mdio_read(tp
, MII_BMCR
);
7968 if (data
& BMCR_PDOWN
) {
7969 data
&= ~BMCR_PDOWN
;
7970 r8152_mdio_write(tp
, MII_BMCR
, data
);
7973 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
7974 WARN_ON_ONCE(data
!= PHY_STAT_LAN_ON
);
7976 r8153_u2p3en(tp
, false);
7978 /* MSC timer = 0xfff * 8ms = 32760 ms */
7979 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MSC_TIMER
, 0x0fff);
7981 /* U1/U2/L1 idle timer. 500 us */
7982 ocp_write_word(tp
, MCU_TYPE_USB
, USB_U1U2_TIMER
, 500);
7984 r8153b_power_cut_en(tp
, false);
7985 r8156_ups_en(tp
, false);
7986 r8153_queue_wake(tp
, false);
7987 rtl_runtime_suspend_enable(tp
, false);
7989 if (tp
->udev
->speed
>= USB_SPEED_SUPER
)
7990 r8153b_u1u2en(tp
, true);
7992 usb_enable_lpm(tp
->udev
);
7994 r8156_mac_clk_spd(tp
, true);
7996 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
);
7997 ocp_data
&= ~PLA_MCU_SPDWN_EN
;
7998 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, ocp_data
);
8000 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
);
8001 if (rtl8152_get_speed(tp
) & LINK_STATUS
)
8002 ocp_data
|= CUR_LINK_OK
;
8004 ocp_data
&= ~CUR_LINK_OK
;
8005 ocp_data
|= POLL_LINK_CHG
;
8006 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
, ocp_data
);
8008 set_bit(GREEN_ETHERNET
, &tp
->flags
);
8010 /* rx aggregation */
8011 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
8012 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
8013 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
8015 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_BMU_CONFIG
);
8016 ocp_data
|= ACT_ODMA
;
8017 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_BMU_CONFIG
, ocp_data
);
8019 rtl_tally_reset(tp
);
8021 tp
->coalesce
= 15000; /* 15 us */
8024 static void r8156b_init(struct r8152
*tp
)
8030 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
8033 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_ECM_OP
);
8034 ocp_data
&= ~EN_ALL_SPEED
;
8035 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_ECM_OP
, ocp_data
);
8037 ocp_write_word(tp
, MCU_TYPE_USB
, USB_SPEED_OPTION
, 0);
8039 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_ECM_OPTION
);
8040 ocp_data
|= BYPASS_MAC_RESET
;
8041 ocp_write_word(tp
, MCU_TYPE_USB
, USB_ECM_OPTION
, ocp_data
);
8043 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_U2P3_CTRL
);
8044 ocp_data
|= RX_DETECT8
;
8045 ocp_write_word(tp
, MCU_TYPE_USB
, USB_U2P3_CTRL
, ocp_data
);
8047 r8153b_u1u2en(tp
, false);
8049 switch (tp
->version
) {
8052 r8156b_wait_loading_flash(tp
);
8058 for (i
= 0; i
< 500; i
++) {
8059 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
8064 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
8068 data
= r8153_phy_status(tp
, 0);
8069 if (data
== PHY_STAT_EXT_INIT
) {
8070 data
= ocp_reg_read(tp
, 0xa468);
8071 data
&= ~(BIT(3) | BIT(1));
8072 ocp_reg_write(tp
, 0xa468, data
);
8074 data
= ocp_reg_read(tp
, 0xa466);
8076 ocp_reg_write(tp
, 0xa466, data
);
8079 data
= r8152_mdio_read(tp
, MII_BMCR
);
8080 if (data
& BMCR_PDOWN
) {
8081 data
&= ~BMCR_PDOWN
;
8082 r8152_mdio_write(tp
, MII_BMCR
, data
);
8085 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
8087 r8153_u2p3en(tp
, false);
8089 /* MSC timer = 0xfff * 8ms = 32760 ms */
8090 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MSC_TIMER
, 0x0fff);
8092 /* U1/U2/L1 idle timer. 500 us */
8093 ocp_write_word(tp
, MCU_TYPE_USB
, USB_U1U2_TIMER
, 500);
8095 r8153b_power_cut_en(tp
, false);
8096 r8156_ups_en(tp
, false);
8097 r8153_queue_wake(tp
, false);
8098 rtl_runtime_suspend_enable(tp
, false);
8100 if (tp
->udev
->speed
>= USB_SPEED_SUPER
)
8101 r8153b_u1u2en(tp
, true);
8103 usb_enable_lpm(tp
->udev
);
8105 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_RCR
);
8106 ocp_data
&= ~SLOT_EN
;
8107 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
8109 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CPCR
);
8110 ocp_data
|= FLOW_CTRL_EN
;
8111 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CPCR
, ocp_data
);
8113 /* enable fc timer and set timer to 600 ms. */
8114 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FC_TIMER
,
8115 CTRL_TIMER_EN
| (600 / 8));
8117 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_CTRL
);
8118 if (!(ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_POL_GPIO_CTRL
) & DACK_DET_EN
))
8119 ocp_data
|= FLOW_CTRL_PATCH_2
;
8120 ocp_data
&= ~AUTO_SPEEDUP
;
8121 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_CTRL
, ocp_data
);
8123 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
);
8124 ocp_data
|= FC_PATCH_TASK
;
8125 ocp_write_word(tp
, MCU_TYPE_USB
, USB_FW_TASK
, ocp_data
);
8127 r8156_mac_clk_spd(tp
, true);
8129 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
);
8130 ocp_data
&= ~PLA_MCU_SPDWN_EN
;
8131 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, ocp_data
);
8133 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
);
8134 if (rtl8152_get_speed(tp
) & LINK_STATUS
)
8135 ocp_data
|= CUR_LINK_OK
;
8137 ocp_data
&= ~CUR_LINK_OK
;
8138 ocp_data
|= POLL_LINK_CHG
;
8139 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EXTRA_STATUS
, ocp_data
);
8141 set_bit(GREEN_ETHERNET
, &tp
->flags
);
8143 /* rx aggregation */
8144 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
8145 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
8146 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
8148 rtl_tally_reset(tp
);
8150 tp
->coalesce
= 15000; /* 15 us */
8153 static bool rtl_check_vendor_ok(struct usb_interface
*intf
)
8155 struct usb_host_interface
*alt
= intf
->cur_altsetting
;
8156 struct usb_endpoint_descriptor
*in
, *out
, *intr
;
8158 if (usb_find_common_endpoints(alt
, &in
, &out
, &intr
, NULL
) < 0) {
8159 dev_err(&intf
->dev
, "Expected endpoints are not found\n");
8163 /* Check Rx endpoint address */
8164 if (usb_endpoint_num(in
) != 1) {
8165 dev_err(&intf
->dev
, "Invalid Rx endpoint address\n");
8169 /* Check Tx endpoint address */
8170 if (usb_endpoint_num(out
) != 2) {
8171 dev_err(&intf
->dev
, "Invalid Tx endpoint address\n");
8175 /* Check interrupt endpoint address */
8176 if (usb_endpoint_num(intr
) != 3) {
8177 dev_err(&intf
->dev
, "Invalid interrupt endpoint address\n");
8184 static bool rtl_vendor_mode(struct usb_interface
*intf
)
8186 struct usb_host_interface
*alt
= intf
->cur_altsetting
;
8187 struct usb_device
*udev
;
8188 struct usb_host_config
*c
;
8191 if (alt
->desc
.bInterfaceClass
== USB_CLASS_VENDOR_SPEC
)
8192 return rtl_check_vendor_ok(intf
);
8194 /* The vendor mode is not always config #1, so to find it out. */
8195 udev
= interface_to_usbdev(intf
);
8197 num_configs
= udev
->descriptor
.bNumConfigurations
;
8198 if (num_configs
< 2)
8201 for (i
= 0; i
< num_configs
; (i
++, c
++)) {
8202 struct usb_interface_descriptor
*desc
= NULL
;
8204 if (c
->desc
.bNumInterfaces
> 0)
8205 desc
= &c
->intf_cache
[0]->altsetting
->desc
;
8209 if (desc
->bInterfaceClass
== USB_CLASS_VENDOR_SPEC
) {
8210 usb_driver_set_configuration(udev
, c
->desc
.bConfigurationValue
);
8215 if (i
== num_configs
)
8216 dev_err(&intf
->dev
, "Unexpected Device\n");
8221 static int rtl8152_pre_reset(struct usb_interface
*intf
)
8223 struct r8152
*tp
= usb_get_intfdata(intf
);
8224 struct net_device
*netdev
;
8229 netdev
= tp
->netdev
;
8230 if (!netif_running(netdev
))
8233 netif_stop_queue(netdev
);
8234 tasklet_disable(&tp
->tx_tl
);
8235 clear_bit(WORK_ENABLE
, &tp
->flags
);
8236 usb_kill_urb(tp
->intr_urb
);
8237 cancel_delayed_work_sync(&tp
->schedule
);
8238 napi_disable(&tp
->napi
);
8239 if (netif_carrier_ok(netdev
)) {
8240 mutex_lock(&tp
->control
);
8241 tp
->rtl_ops
.disable(tp
);
8242 mutex_unlock(&tp
->control
);
8248 static int rtl8152_post_reset(struct usb_interface
*intf
)
8250 struct r8152
*tp
= usb_get_intfdata(intf
);
8251 struct net_device
*netdev
;
8257 /* reset the MAC address in case of policy change */
8258 if (determine_ethernet_addr(tp
, &sa
) >= 0) {
8260 dev_set_mac_address (tp
->netdev
, &sa
, NULL
);
8264 netdev
= tp
->netdev
;
8265 if (!netif_running(netdev
))
8268 set_bit(WORK_ENABLE
, &tp
->flags
);
8269 if (netif_carrier_ok(netdev
)) {
8270 mutex_lock(&tp
->control
);
8271 tp
->rtl_ops
.enable(tp
);
8273 _rtl8152_set_rx_mode(netdev
);
8274 mutex_unlock(&tp
->control
);
8277 napi_enable(&tp
->napi
);
8278 tasklet_enable(&tp
->tx_tl
);
8279 netif_wake_queue(netdev
);
8280 usb_submit_urb(tp
->intr_urb
, GFP_KERNEL
);
8282 if (!list_empty(&tp
->rx_done
))
8283 napi_schedule(&tp
->napi
);
8288 static bool delay_autosuspend(struct r8152
*tp
)
8290 bool sw_linking
= !!netif_carrier_ok(tp
->netdev
);
8291 bool hw_linking
= !!(rtl8152_get_speed(tp
) & LINK_STATUS
);
8293 /* This means a linking change occurs and the driver doesn't detect it,
8294 * yet. If the driver has disabled tx/rx and hw is linking on, the
8295 * device wouldn't wake up by receiving any packet.
8297 if (work_busy(&tp
->schedule
.work
) || sw_linking
!= hw_linking
)
8300 /* If the linking down is occurred by nway, the device may miss the
8301 * linking change event. And it wouldn't wake when linking on.
8303 if (!sw_linking
&& tp
->rtl_ops
.in_nway(tp
))
8305 else if (!skb_queue_empty(&tp
->tx_queue
))
8311 static int rtl8152_runtime_resume(struct r8152
*tp
)
8313 struct net_device
*netdev
= tp
->netdev
;
8315 if (netif_running(netdev
) && netdev
->flags
& IFF_UP
) {
8316 struct napi_struct
*napi
= &tp
->napi
;
8318 tp
->rtl_ops
.autosuspend_en(tp
, false);
8320 set_bit(WORK_ENABLE
, &tp
->flags
);
8322 if (netif_carrier_ok(netdev
)) {
8323 if (rtl8152_get_speed(tp
) & LINK_STATUS
) {
8326 netif_carrier_off(netdev
);
8327 tp
->rtl_ops
.disable(tp
);
8328 netif_info(tp
, link
, netdev
, "linking down\n");
8333 clear_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
8334 smp_mb__after_atomic();
8336 if (!list_empty(&tp
->rx_done
))
8337 napi_schedule(&tp
->napi
);
8339 usb_submit_urb(tp
->intr_urb
, GFP_NOIO
);
8341 if (netdev
->flags
& IFF_UP
)
8342 tp
->rtl_ops
.autosuspend_en(tp
, false);
8344 clear_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
8350 static int rtl8152_system_resume(struct r8152
*tp
)
8352 struct net_device
*netdev
= tp
->netdev
;
8354 netif_device_attach(netdev
);
8356 if (netif_running(netdev
) && (netdev
->flags
& IFF_UP
)) {
8358 netif_carrier_off(netdev
);
8359 set_bit(WORK_ENABLE
, &tp
->flags
);
8360 usb_submit_urb(tp
->intr_urb
, GFP_NOIO
);
8366 static int rtl8152_runtime_suspend(struct r8152
*tp
)
8368 struct net_device
*netdev
= tp
->netdev
;
8371 if (!tp
->rtl_ops
.autosuspend_en
)
8374 set_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
8375 smp_mb__after_atomic();
8377 if (netif_running(netdev
) && test_bit(WORK_ENABLE
, &tp
->flags
)) {
8380 if (netif_carrier_ok(netdev
)) {
8383 rcr
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
8384 ocp_data
= rcr
& ~RCR_ACPT_ALL
;
8385 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
8386 rxdy_gated_en(tp
, true);
8387 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
,
8389 if (!(ocp_data
& RXFIFO_EMPTY
)) {
8390 rxdy_gated_en(tp
, false);
8391 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, rcr
);
8392 clear_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
8393 smp_mb__after_atomic();
8399 clear_bit(WORK_ENABLE
, &tp
->flags
);
8400 usb_kill_urb(tp
->intr_urb
);
8402 tp
->rtl_ops
.autosuspend_en(tp
, true);
8404 if (netif_carrier_ok(netdev
)) {
8405 struct napi_struct
*napi
= &tp
->napi
;
8409 rxdy_gated_en(tp
, false);
8410 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, rcr
);
8414 if (delay_autosuspend(tp
)) {
8415 rtl8152_runtime_resume(tp
);
8424 static int rtl8152_system_suspend(struct r8152
*tp
)
8426 struct net_device
*netdev
= tp
->netdev
;
8428 netif_device_detach(netdev
);
8430 if (netif_running(netdev
) && test_bit(WORK_ENABLE
, &tp
->flags
)) {
8431 struct napi_struct
*napi
= &tp
->napi
;
8433 clear_bit(WORK_ENABLE
, &tp
->flags
);
8434 usb_kill_urb(tp
->intr_urb
);
8435 tasklet_disable(&tp
->tx_tl
);
8437 cancel_delayed_work_sync(&tp
->schedule
);
8438 tp
->rtl_ops
.down(tp
);
8440 tasklet_enable(&tp
->tx_tl
);
8446 static int rtl8152_suspend(struct usb_interface
*intf
, pm_message_t message
)
8448 struct r8152
*tp
= usb_get_intfdata(intf
);
8451 mutex_lock(&tp
->control
);
8453 if (PMSG_IS_AUTO(message
))
8454 ret
= rtl8152_runtime_suspend(tp
);
8456 ret
= rtl8152_system_suspend(tp
);
8458 mutex_unlock(&tp
->control
);
8463 static int rtl8152_resume(struct usb_interface
*intf
)
8465 struct r8152
*tp
= usb_get_intfdata(intf
);
8468 mutex_lock(&tp
->control
);
8470 if (test_bit(SELECTIVE_SUSPEND
, &tp
->flags
))
8471 ret
= rtl8152_runtime_resume(tp
);
8473 ret
= rtl8152_system_resume(tp
);
8475 mutex_unlock(&tp
->control
);
8480 static int rtl8152_reset_resume(struct usb_interface
*intf
)
8482 struct r8152
*tp
= usb_get_intfdata(intf
);
8484 clear_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
8485 tp
->rtl_ops
.init(tp
);
8486 queue_delayed_work(system_long_wq
, &tp
->hw_phy_work
, 0);
8487 set_ethernet_addr(tp
, true);
8488 return rtl8152_resume(intf
);
8491 static void rtl8152_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
8493 struct r8152
*tp
= netdev_priv(dev
);
8495 if (usb_autopm_get_interface(tp
->intf
) < 0)
8498 if (!rtl_can_wakeup(tp
)) {
8502 mutex_lock(&tp
->control
);
8503 wol
->supported
= WAKE_ANY
;
8504 wol
->wolopts
= __rtl_get_wol(tp
);
8505 mutex_unlock(&tp
->control
);
8508 usb_autopm_put_interface(tp
->intf
);
8511 static int rtl8152_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
8513 struct r8152
*tp
= netdev_priv(dev
);
8516 if (!rtl_can_wakeup(tp
))
8519 if (wol
->wolopts
& ~WAKE_ANY
)
8522 ret
= usb_autopm_get_interface(tp
->intf
);
8526 mutex_lock(&tp
->control
);
8528 __rtl_set_wol(tp
, wol
->wolopts
);
8529 tp
->saved_wolopts
= wol
->wolopts
& WAKE_ANY
;
8531 mutex_unlock(&tp
->control
);
8533 usb_autopm_put_interface(tp
->intf
);
8539 static u32
rtl8152_get_msglevel(struct net_device
*dev
)
8541 struct r8152
*tp
= netdev_priv(dev
);
8543 return tp
->msg_enable
;
8546 static void rtl8152_set_msglevel(struct net_device
*dev
, u32 value
)
8548 struct r8152
*tp
= netdev_priv(dev
);
8550 tp
->msg_enable
= value
;
8553 static void rtl8152_get_drvinfo(struct net_device
*netdev
,
8554 struct ethtool_drvinfo
*info
)
8556 struct r8152
*tp
= netdev_priv(netdev
);
8558 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
8559 strlcpy(info
->version
, DRIVER_VERSION
, sizeof(info
->version
));
8560 usb_make_path(tp
->udev
, info
->bus_info
, sizeof(info
->bus_info
));
8561 if (!IS_ERR_OR_NULL(tp
->rtl_fw
.fw
))
8562 strlcpy(info
->fw_version
, tp
->rtl_fw
.version
,
8563 sizeof(info
->fw_version
));
8567 int rtl8152_get_link_ksettings(struct net_device
*netdev
,
8568 struct ethtool_link_ksettings
*cmd
)
8570 struct r8152
*tp
= netdev_priv(netdev
);
8573 if (!tp
->mii
.mdio_read
)
8576 ret
= usb_autopm_get_interface(tp
->intf
);
8580 mutex_lock(&tp
->control
);
8582 mii_ethtool_get_link_ksettings(&tp
->mii
, cmd
);
8584 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT
,
8585 cmd
->link_modes
.supported
, tp
->support_2500full
);
8587 if (tp
->support_2500full
) {
8588 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT
,
8589 cmd
->link_modes
.advertising
,
8590 ocp_reg_read(tp
, OCP_10GBT_CTRL
) & MDIO_AN_10GBT_CTRL_ADV2_5G
);
8592 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT
,
8593 cmd
->link_modes
.lp_advertising
,
8594 ocp_reg_read(tp
, OCP_10GBT_STAT
) & MDIO_AN_10GBT_STAT_LP2_5G
);
8596 if (is_speed_2500(rtl8152_get_speed(tp
)))
8597 cmd
->base
.speed
= SPEED_2500
;
8600 mutex_unlock(&tp
->control
);
8602 usb_autopm_put_interface(tp
->intf
);
8608 static int rtl8152_set_link_ksettings(struct net_device
*dev
,
8609 const struct ethtool_link_ksettings
*cmd
)
8611 struct r8152
*tp
= netdev_priv(dev
);
8612 u32 advertising
= 0;
8615 ret
= usb_autopm_get_interface(tp
->intf
);
8619 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT
,
8620 cmd
->link_modes
.advertising
))
8621 advertising
|= RTL_ADVERTISED_10_HALF
;
8623 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT
,
8624 cmd
->link_modes
.advertising
))
8625 advertising
|= RTL_ADVERTISED_10_FULL
;
8627 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT
,
8628 cmd
->link_modes
.advertising
))
8629 advertising
|= RTL_ADVERTISED_100_HALF
;
8631 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT
,
8632 cmd
->link_modes
.advertising
))
8633 advertising
|= RTL_ADVERTISED_100_FULL
;
8635 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT
,
8636 cmd
->link_modes
.advertising
))
8637 advertising
|= RTL_ADVERTISED_1000_HALF
;
8639 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT
,
8640 cmd
->link_modes
.advertising
))
8641 advertising
|= RTL_ADVERTISED_1000_FULL
;
8643 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT
,
8644 cmd
->link_modes
.advertising
))
8645 advertising
|= RTL_ADVERTISED_2500_FULL
;
8647 mutex_lock(&tp
->control
);
8649 ret
= rtl8152_set_speed(tp
, cmd
->base
.autoneg
, cmd
->base
.speed
,
8650 cmd
->base
.duplex
, advertising
);
8652 tp
->autoneg
= cmd
->base
.autoneg
;
8653 tp
->speed
= cmd
->base
.speed
;
8654 tp
->duplex
= cmd
->base
.duplex
;
8655 tp
->advertising
= advertising
;
8658 mutex_unlock(&tp
->control
);
8660 usb_autopm_put_interface(tp
->intf
);
8666 static const char rtl8152_gstrings
[][ETH_GSTRING_LEN
] = {
8673 "tx_single_collisions",
8674 "tx_multi_collisions",
8682 static int rtl8152_get_sset_count(struct net_device
*dev
, int sset
)
8686 return ARRAY_SIZE(rtl8152_gstrings
);
8692 static void rtl8152_get_ethtool_stats(struct net_device
*dev
,
8693 struct ethtool_stats
*stats
, u64
*data
)
8695 struct r8152
*tp
= netdev_priv(dev
);
8696 struct tally_counter tally
;
8698 if (usb_autopm_get_interface(tp
->intf
) < 0)
8701 generic_ocp_read(tp
, PLA_TALLYCNT
, sizeof(tally
), &tally
, MCU_TYPE_PLA
);
8703 usb_autopm_put_interface(tp
->intf
);
8705 data
[0] = le64_to_cpu(tally
.tx_packets
);
8706 data
[1] = le64_to_cpu(tally
.rx_packets
);
8707 data
[2] = le64_to_cpu(tally
.tx_errors
);
8708 data
[3] = le32_to_cpu(tally
.rx_errors
);
8709 data
[4] = le16_to_cpu(tally
.rx_missed
);
8710 data
[5] = le16_to_cpu(tally
.align_errors
);
8711 data
[6] = le32_to_cpu(tally
.tx_one_collision
);
8712 data
[7] = le32_to_cpu(tally
.tx_multi_collision
);
8713 data
[8] = le64_to_cpu(tally
.rx_unicast
);
8714 data
[9] = le64_to_cpu(tally
.rx_broadcast
);
8715 data
[10] = le32_to_cpu(tally
.rx_multicast
);
8716 data
[11] = le16_to_cpu(tally
.tx_aborted
);
8717 data
[12] = le16_to_cpu(tally
.tx_underrun
);
8720 static void rtl8152_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
8722 switch (stringset
) {
8724 memcpy(data
, rtl8152_gstrings
, sizeof(rtl8152_gstrings
));
8729 static int r8152_get_eee(struct r8152
*tp
, struct ethtool_eee
*eee
)
8731 u32 lp
, adv
, supported
= 0;
8734 val
= r8152_mmd_read(tp
, MDIO_MMD_PCS
, MDIO_PCS_EEE_ABLE
);
8735 supported
= mmd_eee_cap_to_ethtool_sup_t(val
);
8737 val
= r8152_mmd_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
);
8738 adv
= mmd_eee_adv_to_ethtool_adv_t(val
);
8740 val
= r8152_mmd_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_LPABLE
);
8741 lp
= mmd_eee_adv_to_ethtool_adv_t(val
);
8743 eee
->eee_enabled
= tp
->eee_en
;
8744 eee
->eee_active
= !!(supported
& adv
& lp
);
8745 eee
->supported
= supported
;
8746 eee
->advertised
= tp
->eee_adv
;
8747 eee
->lp_advertised
= lp
;
8752 static int r8152_set_eee(struct r8152
*tp
, struct ethtool_eee
*eee
)
8754 u16 val
= ethtool_adv_to_mmd_eee_adv_t(eee
->advertised
);
8756 tp
->eee_en
= eee
->eee_enabled
;
8759 rtl_eee_enable(tp
, tp
->eee_en
);
8764 static int r8153_get_eee(struct r8152
*tp
, struct ethtool_eee
*eee
)
8766 u32 lp
, adv
, supported
= 0;
8769 val
= ocp_reg_read(tp
, OCP_EEE_ABLE
);
8770 supported
= mmd_eee_cap_to_ethtool_sup_t(val
);
8772 val
= ocp_reg_read(tp
, OCP_EEE_ADV
);
8773 adv
= mmd_eee_adv_to_ethtool_adv_t(val
);
8775 val
= ocp_reg_read(tp
, OCP_EEE_LPABLE
);
8776 lp
= mmd_eee_adv_to_ethtool_adv_t(val
);
8778 eee
->eee_enabled
= tp
->eee_en
;
8779 eee
->eee_active
= !!(supported
& adv
& lp
);
8780 eee
->supported
= supported
;
8781 eee
->advertised
= tp
->eee_adv
;
8782 eee
->lp_advertised
= lp
;
8788 rtl_ethtool_get_eee(struct net_device
*net
, struct ethtool_eee
*edata
)
8790 struct r8152
*tp
= netdev_priv(net
);
8793 if (!tp
->rtl_ops
.eee_get
) {
8798 ret
= usb_autopm_get_interface(tp
->intf
);
8802 mutex_lock(&tp
->control
);
8804 ret
= tp
->rtl_ops
.eee_get(tp
, edata
);
8806 mutex_unlock(&tp
->control
);
8808 usb_autopm_put_interface(tp
->intf
);
8815 rtl_ethtool_set_eee(struct net_device
*net
, struct ethtool_eee
*edata
)
8817 struct r8152
*tp
= netdev_priv(net
);
8820 if (!tp
->rtl_ops
.eee_set
) {
8825 ret
= usb_autopm_get_interface(tp
->intf
);
8829 mutex_lock(&tp
->control
);
8831 ret
= tp
->rtl_ops
.eee_set(tp
, edata
);
8833 ret
= mii_nway_restart(&tp
->mii
);
8835 mutex_unlock(&tp
->control
);
8837 usb_autopm_put_interface(tp
->intf
);
8843 static int rtl8152_nway_reset(struct net_device
*dev
)
8845 struct r8152
*tp
= netdev_priv(dev
);
8848 ret
= usb_autopm_get_interface(tp
->intf
);
8852 mutex_lock(&tp
->control
);
8854 ret
= mii_nway_restart(&tp
->mii
);
8856 mutex_unlock(&tp
->control
);
8858 usb_autopm_put_interface(tp
->intf
);
8864 static int rtl8152_get_coalesce(struct net_device
*netdev
,
8865 struct ethtool_coalesce
*coalesce
,
8866 struct kernel_ethtool_coalesce
*kernel_coal
,
8867 struct netlink_ext_ack
*extack
)
8869 struct r8152
*tp
= netdev_priv(netdev
);
8871 switch (tp
->version
) {
8880 coalesce
->rx_coalesce_usecs
= tp
->coalesce
;
8885 static int rtl8152_set_coalesce(struct net_device
*netdev
,
8886 struct ethtool_coalesce
*coalesce
,
8887 struct kernel_ethtool_coalesce
*kernel_coal
,
8888 struct netlink_ext_ack
*extack
)
8890 struct r8152
*tp
= netdev_priv(netdev
);
8893 switch (tp
->version
) {
8902 if (coalesce
->rx_coalesce_usecs
> COALESCE_SLOW
)
8905 ret
= usb_autopm_get_interface(tp
->intf
);
8909 mutex_lock(&tp
->control
);
8911 if (tp
->coalesce
!= coalesce
->rx_coalesce_usecs
) {
8912 tp
->coalesce
= coalesce
->rx_coalesce_usecs
;
8914 if (netif_running(netdev
) && netif_carrier_ok(netdev
)) {
8915 netif_stop_queue(netdev
);
8916 napi_disable(&tp
->napi
);
8917 tp
->rtl_ops
.disable(tp
);
8918 tp
->rtl_ops
.enable(tp
);
8920 clear_bit(RTL8152_SET_RX_MODE
, &tp
->flags
);
8921 _rtl8152_set_rx_mode(netdev
);
8922 napi_enable(&tp
->napi
);
8923 netif_wake_queue(netdev
);
8927 mutex_unlock(&tp
->control
);
8929 usb_autopm_put_interface(tp
->intf
);
8934 static int rtl8152_get_tunable(struct net_device
*netdev
,
8935 const struct ethtool_tunable
*tunable
, void *d
)
8937 struct r8152
*tp
= netdev_priv(netdev
);
8939 switch (tunable
->id
) {
8940 case ETHTOOL_RX_COPYBREAK
:
8941 *(u32
*)d
= tp
->rx_copybreak
;
8950 static int rtl8152_set_tunable(struct net_device
*netdev
,
8951 const struct ethtool_tunable
*tunable
,
8954 struct r8152
*tp
= netdev_priv(netdev
);
8957 switch (tunable
->id
) {
8958 case ETHTOOL_RX_COPYBREAK
:
8960 if (val
< ETH_ZLEN
) {
8961 netif_err(tp
, rx_err
, netdev
,
8962 "Invalid rx copy break value\n");
8966 if (tp
->rx_copybreak
!= val
) {
8967 if (netdev
->flags
& IFF_UP
) {
8968 mutex_lock(&tp
->control
);
8969 napi_disable(&tp
->napi
);
8970 tp
->rx_copybreak
= val
;
8971 napi_enable(&tp
->napi
);
8972 mutex_unlock(&tp
->control
);
8974 tp
->rx_copybreak
= val
;
8985 static void rtl8152_get_ringparam(struct net_device
*netdev
,
8986 struct ethtool_ringparam
*ring
)
8988 struct r8152
*tp
= netdev_priv(netdev
);
8990 ring
->rx_max_pending
= RTL8152_RX_MAX_PENDING
;
8991 ring
->rx_pending
= tp
->rx_pending
;
8994 static int rtl8152_set_ringparam(struct net_device
*netdev
,
8995 struct ethtool_ringparam
*ring
)
8997 struct r8152
*tp
= netdev_priv(netdev
);
8999 if (ring
->rx_pending
< (RTL8152_MAX_RX
* 2))
9002 if (tp
->rx_pending
!= ring
->rx_pending
) {
9003 if (netdev
->flags
& IFF_UP
) {
9004 mutex_lock(&tp
->control
);
9005 napi_disable(&tp
->napi
);
9006 tp
->rx_pending
= ring
->rx_pending
;
9007 napi_enable(&tp
->napi
);
9008 mutex_unlock(&tp
->control
);
9010 tp
->rx_pending
= ring
->rx_pending
;
9017 static void rtl8152_get_pauseparam(struct net_device
*netdev
, struct ethtool_pauseparam
*pause
)
9019 struct r8152
*tp
= netdev_priv(netdev
);
9020 u16 bmcr
, lcladv
, rmtadv
;
9023 if (usb_autopm_get_interface(tp
->intf
) < 0)
9026 mutex_lock(&tp
->control
);
9028 bmcr
= r8152_mdio_read(tp
, MII_BMCR
);
9029 lcladv
= r8152_mdio_read(tp
, MII_ADVERTISE
);
9030 rmtadv
= r8152_mdio_read(tp
, MII_LPA
);
9032 mutex_unlock(&tp
->control
);
9034 usb_autopm_put_interface(tp
->intf
);
9036 if (!(bmcr
& BMCR_ANENABLE
)) {
9038 pause
->rx_pause
= 0;
9039 pause
->tx_pause
= 0;
9045 cap
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
9047 if (cap
& FLOW_CTRL_RX
)
9048 pause
->rx_pause
= 1;
9050 if (cap
& FLOW_CTRL_TX
)
9051 pause
->tx_pause
= 1;
9054 static int rtl8152_set_pauseparam(struct net_device
*netdev
, struct ethtool_pauseparam
*pause
)
9056 struct r8152
*tp
= netdev_priv(netdev
);
9061 ret
= usb_autopm_get_interface(tp
->intf
);
9065 mutex_lock(&tp
->control
);
9067 if (pause
->autoneg
&& !(r8152_mdio_read(tp
, MII_BMCR
) & BMCR_ANENABLE
)) {
9072 if (pause
->rx_pause
)
9073 cap
|= FLOW_CTRL_RX
;
9075 if (pause
->tx_pause
)
9076 cap
|= FLOW_CTRL_TX
;
9078 old
= r8152_mdio_read(tp
, MII_ADVERTISE
);
9079 new1
= (old
& ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) | mii_advertise_flowctrl(cap
);
9081 r8152_mdio_write(tp
, MII_ADVERTISE
, new1
);
9084 mutex_unlock(&tp
->control
);
9085 usb_autopm_put_interface(tp
->intf
);
9090 static const struct ethtool_ops ops
= {
9091 .supported_coalesce_params
= ETHTOOL_COALESCE_USECS
,
9092 .get_drvinfo
= rtl8152_get_drvinfo
,
9093 .get_link
= ethtool_op_get_link
,
9094 .nway_reset
= rtl8152_nway_reset
,
9095 .get_msglevel
= rtl8152_get_msglevel
,
9096 .set_msglevel
= rtl8152_set_msglevel
,
9097 .get_wol
= rtl8152_get_wol
,
9098 .set_wol
= rtl8152_set_wol
,
9099 .get_strings
= rtl8152_get_strings
,
9100 .get_sset_count
= rtl8152_get_sset_count
,
9101 .get_ethtool_stats
= rtl8152_get_ethtool_stats
,
9102 .get_coalesce
= rtl8152_get_coalesce
,
9103 .set_coalesce
= rtl8152_set_coalesce
,
9104 .get_eee
= rtl_ethtool_get_eee
,
9105 .set_eee
= rtl_ethtool_set_eee
,
9106 .get_link_ksettings
= rtl8152_get_link_ksettings
,
9107 .set_link_ksettings
= rtl8152_set_link_ksettings
,
9108 .get_tunable
= rtl8152_get_tunable
,
9109 .set_tunable
= rtl8152_set_tunable
,
9110 .get_ringparam
= rtl8152_get_ringparam
,
9111 .set_ringparam
= rtl8152_set_ringparam
,
9112 .get_pauseparam
= rtl8152_get_pauseparam
,
9113 .set_pauseparam
= rtl8152_set_pauseparam
,
9116 static int rtl8152_ioctl(struct net_device
*netdev
, struct ifreq
*rq
, int cmd
)
9118 struct r8152
*tp
= netdev_priv(netdev
);
9119 struct mii_ioctl_data
*data
= if_mii(rq
);
9122 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
9125 res
= usb_autopm_get_interface(tp
->intf
);
9131 data
->phy_id
= R8152_PHY_ID
; /* Internal PHY */
9135 mutex_lock(&tp
->control
);
9136 data
->val_out
= r8152_mdio_read(tp
, data
->reg_num
);
9137 mutex_unlock(&tp
->control
);
9141 if (!capable(CAP_NET_ADMIN
)) {
9145 mutex_lock(&tp
->control
);
9146 r8152_mdio_write(tp
, data
->reg_num
, data
->val_in
);
9147 mutex_unlock(&tp
->control
);
9154 usb_autopm_put_interface(tp
->intf
);
9160 static int rtl8152_change_mtu(struct net_device
*dev
, int new_mtu
)
9162 struct r8152
*tp
= netdev_priv(dev
);
9165 switch (tp
->version
) {
9175 ret
= usb_autopm_get_interface(tp
->intf
);
9179 mutex_lock(&tp
->control
);
9183 if (netif_running(dev
)) {
9184 if (tp
->rtl_ops
.change_mtu
)
9185 tp
->rtl_ops
.change_mtu(tp
);
9187 if (netif_carrier_ok(dev
)) {
9188 netif_stop_queue(dev
);
9189 napi_disable(&tp
->napi
);
9190 tasklet_disable(&tp
->tx_tl
);
9191 tp
->rtl_ops
.disable(tp
);
9192 tp
->rtl_ops
.enable(tp
);
9194 tasklet_enable(&tp
->tx_tl
);
9195 napi_enable(&tp
->napi
);
9196 rtl8152_set_rx_mode(dev
);
9197 netif_wake_queue(dev
);
9201 mutex_unlock(&tp
->control
);
9203 usb_autopm_put_interface(tp
->intf
);
9208 static const struct net_device_ops rtl8152_netdev_ops
= {
9209 .ndo_open
= rtl8152_open
,
9210 .ndo_stop
= rtl8152_close
,
9211 .ndo_eth_ioctl
= rtl8152_ioctl
,
9212 .ndo_start_xmit
= rtl8152_start_xmit
,
9213 .ndo_tx_timeout
= rtl8152_tx_timeout
,
9214 .ndo_set_features
= rtl8152_set_features
,
9215 .ndo_set_rx_mode
= rtl8152_set_rx_mode
,
9216 .ndo_set_mac_address
= rtl8152_set_mac_address
,
9217 .ndo_change_mtu
= rtl8152_change_mtu
,
9218 .ndo_validate_addr
= eth_validate_addr
,
9219 .ndo_features_check
= rtl8152_features_check
,
9222 static void rtl8152_unload(struct r8152
*tp
)
9224 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
9227 if (tp
->version
!= RTL_VER_01
)
9228 r8152_power_cut_en(tp
, true);
9231 static void rtl8153_unload(struct r8152
*tp
)
9233 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
9236 r8153_power_cut_en(tp
, false);
9239 static void rtl8153b_unload(struct r8152
*tp
)
9241 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
9244 r8153b_power_cut_en(tp
, false);
9247 static int rtl_ops_init(struct r8152
*tp
)
9249 struct rtl_ops
*ops
= &tp
->rtl_ops
;
9252 switch (tp
->version
) {
9256 ops
->init
= r8152b_init
;
9257 ops
->enable
= rtl8152_enable
;
9258 ops
->disable
= rtl8152_disable
;
9259 ops
->up
= rtl8152_up
;
9260 ops
->down
= rtl8152_down
;
9261 ops
->unload
= rtl8152_unload
;
9262 ops
->eee_get
= r8152_get_eee
;
9263 ops
->eee_set
= r8152_set_eee
;
9264 ops
->in_nway
= rtl8152_in_nway
;
9265 ops
->hw_phy_cfg
= r8152b_hw_phy_cfg
;
9266 ops
->autosuspend_en
= rtl_runtime_suspend_enable
;
9267 tp
->rx_buf_sz
= 16 * 1024;
9269 tp
->eee_adv
= MDIO_EEE_100TX
;
9276 ops
->init
= r8153_init
;
9277 ops
->enable
= rtl8153_enable
;
9278 ops
->disable
= rtl8153_disable
;
9279 ops
->up
= rtl8153_up
;
9280 ops
->down
= rtl8153_down
;
9281 ops
->unload
= rtl8153_unload
;
9282 ops
->eee_get
= r8153_get_eee
;
9283 ops
->eee_set
= r8152_set_eee
;
9284 ops
->in_nway
= rtl8153_in_nway
;
9285 ops
->hw_phy_cfg
= r8153_hw_phy_cfg
;
9286 ops
->autosuspend_en
= rtl8153_runtime_enable
;
9287 ops
->change_mtu
= rtl8153_change_mtu
;
9288 if (tp
->udev
->speed
< USB_SPEED_SUPER
)
9289 tp
->rx_buf_sz
= 16 * 1024;
9291 tp
->rx_buf_sz
= 32 * 1024;
9293 tp
->eee_adv
= MDIO_EEE_1000T
| MDIO_EEE_100TX
;
9298 ops
->init
= r8153b_init
;
9299 ops
->enable
= rtl8153_enable
;
9300 ops
->disable
= rtl8153_disable
;
9301 ops
->up
= rtl8153b_up
;
9302 ops
->down
= rtl8153b_down
;
9303 ops
->unload
= rtl8153b_unload
;
9304 ops
->eee_get
= r8153_get_eee
;
9305 ops
->eee_set
= r8152_set_eee
;
9306 ops
->in_nway
= rtl8153_in_nway
;
9307 ops
->hw_phy_cfg
= r8153b_hw_phy_cfg
;
9308 ops
->autosuspend_en
= rtl8153b_runtime_enable
;
9309 ops
->change_mtu
= rtl8153_change_mtu
;
9310 tp
->rx_buf_sz
= 32 * 1024;
9312 tp
->eee_adv
= MDIO_EEE_1000T
| MDIO_EEE_100TX
;
9317 tp
->eee_adv
= MDIO_EEE_1000T
| MDIO_EEE_100TX
;
9320 ops
->init
= r8156_init
;
9321 ops
->enable
= rtl8156_enable
;
9322 ops
->disable
= rtl8153_disable
;
9323 ops
->up
= rtl8156_up
;
9324 ops
->down
= rtl8156_down
;
9325 ops
->unload
= rtl8153_unload
;
9326 ops
->eee_get
= r8153_get_eee
;
9327 ops
->eee_set
= r8152_set_eee
;
9328 ops
->in_nway
= rtl8153_in_nway
;
9329 ops
->hw_phy_cfg
= r8156_hw_phy_cfg
;
9330 ops
->autosuspend_en
= rtl8156_runtime_enable
;
9331 ops
->change_mtu
= rtl8156_change_mtu
;
9332 tp
->rx_buf_sz
= 48 * 1024;
9333 tp
->support_2500full
= 1;
9338 tp
->support_2500full
= 1;
9342 tp
->eee_adv
= MDIO_EEE_1000T
| MDIO_EEE_100TX
;
9343 ops
->init
= r8156b_init
;
9344 ops
->enable
= rtl8156b_enable
;
9345 ops
->disable
= rtl8153_disable
;
9346 ops
->up
= rtl8156_up
;
9347 ops
->down
= rtl8156_down
;
9348 ops
->unload
= rtl8153_unload
;
9349 ops
->eee_get
= r8153_get_eee
;
9350 ops
->eee_set
= r8152_set_eee
;
9351 ops
->in_nway
= rtl8153_in_nway
;
9352 ops
->hw_phy_cfg
= r8156b_hw_phy_cfg
;
9353 ops
->autosuspend_en
= rtl8156_runtime_enable
;
9354 ops
->change_mtu
= rtl8156_change_mtu
;
9355 tp
->rx_buf_sz
= 48 * 1024;
9359 ops
->init
= r8153c_init
;
9360 ops
->enable
= rtl8153_enable
;
9361 ops
->disable
= rtl8153_disable
;
9362 ops
->up
= rtl8153c_up
;
9363 ops
->down
= rtl8153b_down
;
9364 ops
->unload
= rtl8153_unload
;
9365 ops
->eee_get
= r8153_get_eee
;
9366 ops
->eee_set
= r8152_set_eee
;
9367 ops
->in_nway
= rtl8153_in_nway
;
9368 ops
->hw_phy_cfg
= r8153c_hw_phy_cfg
;
9369 ops
->autosuspend_en
= rtl8153c_runtime_enable
;
9370 ops
->change_mtu
= rtl8153c_change_mtu
;
9371 tp
->rx_buf_sz
= 32 * 1024;
9373 tp
->eee_adv
= MDIO_EEE_1000T
| MDIO_EEE_100TX
;
9378 dev_err(&tp
->intf
->dev
, "Unknown Device\n");
9385 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9386 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9387 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9388 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9389 #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9390 #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9391 #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9393 MODULE_FIRMWARE(FIRMWARE_8153A_2
);
9394 MODULE_FIRMWARE(FIRMWARE_8153A_3
);
9395 MODULE_FIRMWARE(FIRMWARE_8153A_4
);
9396 MODULE_FIRMWARE(FIRMWARE_8153B_2
);
9397 MODULE_FIRMWARE(FIRMWARE_8153C_1
);
9398 MODULE_FIRMWARE(FIRMWARE_8156A_2
);
9399 MODULE_FIRMWARE(FIRMWARE_8156B_2
);
9401 static int rtl_fw_init(struct r8152
*tp
)
9403 struct rtl_fw
*rtl_fw
= &tp
->rtl_fw
;
9405 switch (tp
->version
) {
9407 rtl_fw
->fw_name
= FIRMWARE_8153A_2
;
9408 rtl_fw
->pre_fw
= r8153_pre_firmware_1
;
9409 rtl_fw
->post_fw
= r8153_post_firmware_1
;
9412 rtl_fw
->fw_name
= FIRMWARE_8153A_3
;
9413 rtl_fw
->pre_fw
= r8153_pre_firmware_2
;
9414 rtl_fw
->post_fw
= r8153_post_firmware_2
;
9417 rtl_fw
->fw_name
= FIRMWARE_8153A_4
;
9418 rtl_fw
->post_fw
= r8153_post_firmware_3
;
9421 rtl_fw
->fw_name
= FIRMWARE_8153B_2
;
9422 rtl_fw
->pre_fw
= r8153b_pre_firmware_1
;
9423 rtl_fw
->post_fw
= r8153b_post_firmware_1
;
9426 rtl_fw
->fw_name
= FIRMWARE_8156A_2
;
9427 rtl_fw
->post_fw
= r8156a_post_firmware_1
;
9431 rtl_fw
->fw_name
= FIRMWARE_8156B_2
;
9434 rtl_fw
->fw_name
= FIRMWARE_8153C_1
;
9435 rtl_fw
->pre_fw
= r8153b_pre_firmware_1
;
9436 rtl_fw
->post_fw
= r8153c_post_firmware_1
;
9445 u8
rtl8152_get_version(struct usb_interface
*intf
)
9447 struct usb_device
*udev
= interface_to_usbdev(intf
);
9453 tmp
= kmalloc(sizeof(*tmp
), GFP_KERNEL
);
9457 ret
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
9458 RTL8152_REQ_GET_REGS
, RTL8152_REQT_READ
,
9459 PLA_TCR0
, MCU_TYPE_PLA
, tmp
, sizeof(*tmp
), 500);
9461 ocp_data
= (__le32_to_cpu(*tmp
) >> 16) & VERSION_MASK
;
9467 version
= RTL_VER_01
;
9470 version
= RTL_VER_02
;
9473 version
= RTL_VER_03
;
9476 version
= RTL_VER_04
;
9479 version
= RTL_VER_05
;
9482 version
= RTL_VER_06
;
9485 version
= RTL_VER_07
;
9488 version
= RTL_VER_08
;
9491 version
= RTL_VER_09
;
9494 version
= RTL_TEST_01
;
9497 version
= RTL_VER_10
;
9500 version
= RTL_VER_11
;
9503 version
= RTL_VER_12
;
9506 version
= RTL_VER_13
;
9509 version
= RTL_VER_14
;
9512 version
= RTL_VER_15
;
9515 version
= RTL_VER_UNKNOWN
;
9516 dev_info(&intf
->dev
, "Unknown version 0x%04x\n", ocp_data
);
9520 dev_dbg(&intf
->dev
, "Detected version 0x%04x\n", version
);
9524 EXPORT_SYMBOL_GPL(rtl8152_get_version
);
9526 static int rtl8152_probe(struct usb_interface
*intf
,
9527 const struct usb_device_id
*id
)
9529 struct usb_device
*udev
= interface_to_usbdev(intf
);
9530 u8 version
= rtl8152_get_version(intf
);
9532 struct net_device
*netdev
;
9535 if (version
== RTL_VER_UNKNOWN
)
9538 if (!rtl_vendor_mode(intf
))
9541 usb_reset_device(udev
);
9542 netdev
= alloc_etherdev(sizeof(struct r8152
));
9544 dev_err(&intf
->dev
, "Out of memory\n");
9548 SET_NETDEV_DEV(netdev
, &intf
->dev
);
9549 tp
= netdev_priv(netdev
);
9550 tp
->msg_enable
= 0x7FFF;
9553 tp
->netdev
= netdev
;
9555 tp
->version
= version
;
9557 tp
->pipe_ctrl_in
= usb_rcvctrlpipe(udev
, 0);
9558 tp
->pipe_ctrl_out
= usb_sndctrlpipe(udev
, 0);
9559 tp
->pipe_in
= usb_rcvbulkpipe(udev
, 1);
9560 tp
->pipe_out
= usb_sndbulkpipe(udev
, 2);
9561 tp
->pipe_intr
= usb_rcvintpipe(udev
, 3);
9567 tp
->mii
.supports_gmii
= 0;
9570 tp
->mii
.supports_gmii
= 1;
9574 ret
= rtl_ops_init(tp
);
9580 mutex_init(&tp
->control
);
9581 INIT_DELAYED_WORK(&tp
->schedule
, rtl_work_func_t
);
9582 INIT_DELAYED_WORK(&tp
->hw_phy_work
, rtl_hw_phy_work_func_t
);
9583 tasklet_setup(&tp
->tx_tl
, bottom_half
);
9584 tasklet_disable(&tp
->tx_tl
);
9586 netdev
->netdev_ops
= &rtl8152_netdev_ops
;
9587 netdev
->watchdog_timeo
= RTL8152_TX_TIMEOUT
;
9589 netdev
->features
|= NETIF_F_RXCSUM
| NETIF_F_IP_CSUM
| NETIF_F_SG
|
9590 NETIF_F_TSO
| NETIF_F_FRAGLIST
| NETIF_F_IPV6_CSUM
|
9591 NETIF_F_TSO6
| NETIF_F_HW_VLAN_CTAG_RX
|
9592 NETIF_F_HW_VLAN_CTAG_TX
;
9593 netdev
->hw_features
= NETIF_F_RXCSUM
| NETIF_F_IP_CSUM
| NETIF_F_SG
|
9594 NETIF_F_TSO
| NETIF_F_FRAGLIST
|
9595 NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
|
9596 NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
;
9597 netdev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
9598 NETIF_F_HIGHDMA
| NETIF_F_FRAGLIST
|
9599 NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
9601 if (tp
->version
== RTL_VER_01
) {
9602 netdev
->features
&= ~NETIF_F_RXCSUM
;
9603 netdev
->hw_features
&= ~NETIF_F_RXCSUM
;
9606 if (le16_to_cpu(udev
->descriptor
.idVendor
) == VENDOR_ID_LENOVO
) {
9607 switch (le16_to_cpu(udev
->descriptor
.idProduct
)) {
9608 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2
:
9609 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2
:
9610 tp
->lenovo_macpassthru
= 1;
9614 if (le16_to_cpu(udev
->descriptor
.bcdDevice
) == 0x3011 && udev
->serial
&&
9615 (!strcmp(udev
->serial
, "000001000000") ||
9616 !strcmp(udev
->serial
, "000002000000"))) {
9617 dev_info(&udev
->dev
, "Dell TB16 Dock, disable RX aggregation");
9618 tp
->dell_tb_rx_agg_bug
= 1;
9621 netdev
->ethtool_ops
= &ops
;
9622 netif_set_gso_max_size(netdev
, RTL_LIMITED_TSO_SIZE
);
9624 /* MTU range: 68 - 1500 or 9194 */
9625 netdev
->min_mtu
= ETH_MIN_MTU
;
9626 switch (tp
->version
) {
9634 netdev
->max_mtu
= size_to_mtu(9 * 1024);
9638 netdev
->max_mtu
= size_to_mtu(15 * 1024);
9643 netdev
->max_mtu
= size_to_mtu(16 * 1024);
9649 netdev
->max_mtu
= ETH_DATA_LEN
;
9653 tp
->mii
.dev
= netdev
;
9654 tp
->mii
.mdio_read
= read_mii_word
;
9655 tp
->mii
.mdio_write
= write_mii_word
;
9656 tp
->mii
.phy_id_mask
= 0x3f;
9657 tp
->mii
.reg_num_mask
= 0x1f;
9658 tp
->mii
.phy_id
= R8152_PHY_ID
;
9660 tp
->autoneg
= AUTONEG_ENABLE
;
9661 tp
->speed
= SPEED_100
;
9662 tp
->advertising
= RTL_ADVERTISED_10_HALF
| RTL_ADVERTISED_10_FULL
|
9663 RTL_ADVERTISED_100_HALF
| RTL_ADVERTISED_100_FULL
;
9664 if (tp
->mii
.supports_gmii
) {
9665 if (tp
->support_2500full
&&
9666 tp
->udev
->speed
>= USB_SPEED_SUPER
) {
9667 tp
->speed
= SPEED_2500
;
9668 tp
->advertising
|= RTL_ADVERTISED_2500_FULL
;
9670 tp
->speed
= SPEED_1000
;
9672 tp
->advertising
|= RTL_ADVERTISED_1000_FULL
;
9674 tp
->duplex
= DUPLEX_FULL
;
9676 tp
->rx_copybreak
= RTL8152_RXFG_HEADSZ
;
9677 tp
->rx_pending
= 10 * RTL8152_MAX_RX
;
9679 intf
->needs_remote_wakeup
= 1;
9681 if (!rtl_can_wakeup(tp
))
9682 __rtl_set_wol(tp
, 0);
9684 tp
->saved_wolopts
= __rtl_get_wol(tp
);
9686 tp
->rtl_ops
.init(tp
);
9687 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9688 /* Retry in case request_firmware() is not ready yet. */
9689 tp
->rtl_fw
.retry
= true;
9691 queue_delayed_work(system_long_wq
, &tp
->hw_phy_work
, 0);
9692 set_ethernet_addr(tp
, false);
9694 usb_set_intfdata(intf
, tp
);
9696 if (tp
->support_2500full
)
9697 netif_napi_add(netdev
, &tp
->napi
, r8152_poll
, 256);
9699 netif_napi_add(netdev
, &tp
->napi
, r8152_poll
, 64);
9701 ret
= register_netdev(netdev
);
9703 dev_err(&intf
->dev
, "couldn't register the device\n");
9707 if (tp
->saved_wolopts
)
9708 device_set_wakeup_enable(&udev
->dev
, true);
9710 device_set_wakeup_enable(&udev
->dev
, false);
9712 netif_info(tp
, probe
, netdev
, "%s\n", DRIVER_VERSION
);
9717 tasklet_kill(&tp
->tx_tl
);
9718 usb_set_intfdata(intf
, NULL
);
9720 free_netdev(netdev
);
9724 static void rtl8152_disconnect(struct usb_interface
*intf
)
9726 struct r8152
*tp
= usb_get_intfdata(intf
);
9728 usb_set_intfdata(intf
, NULL
);
9732 unregister_netdev(tp
->netdev
);
9733 tasklet_kill(&tp
->tx_tl
);
9734 cancel_delayed_work_sync(&tp
->hw_phy_work
);
9735 if (tp
->rtl_ops
.unload
)
9736 tp
->rtl_ops
.unload(tp
);
9737 rtl8152_release_firmware(tp
);
9738 free_netdev(tp
->netdev
);
9742 #define REALTEK_USB_DEVICE(vend, prod) { \
9743 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
9746 USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
9747 USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
9750 /* table of devices that work with this driver */
9751 static const struct usb_device_id rtl8152_table
[] = {
9753 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8050),
9754 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8053),
9755 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8152),
9756 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8153),
9757 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8155),
9758 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8156),
9761 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT
, 0x07ab),
9762 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT
, 0x07c6),
9763 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT
, 0x0927),
9764 REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG
, 0xa101),
9765 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x304f),
9766 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x3062),
9767 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x3069),
9768 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x3082),
9769 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x7205),
9770 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x720c),
9771 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x7214),
9772 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x721e),
9773 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0xa387),
9774 REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS
, 0x0041),
9775 REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA
, 0x09ff),
9776 REALTEK_USB_DEVICE(VENDOR_ID_TPLINK
, 0x0601),
9780 MODULE_DEVICE_TABLE(usb
, rtl8152_table
);
9782 static struct usb_driver rtl8152_driver
= {
9784 .id_table
= rtl8152_table
,
9785 .probe
= rtl8152_probe
,
9786 .disconnect
= rtl8152_disconnect
,
9787 .suspend
= rtl8152_suspend
,
9788 .resume
= rtl8152_resume
,
9789 .reset_resume
= rtl8152_reset_resume
,
9790 .pre_reset
= rtl8152_pre_reset
,
9791 .post_reset
= rtl8152_post_reset
,
9792 .supports_autosuspend
= 1,
9793 .disable_hub_initiated_lpm
= 1,
9796 module_usb_driver(rtl8152_driver
);
9798 MODULE_AUTHOR(DRIVER_AUTHOR
);
9799 MODULE_DESCRIPTION(DRIVER_DESC
);
9800 MODULE_LICENSE("GPL");
9801 MODULE_VERSION(DRIVER_VERSION
);