2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "09"
34 /* Information for net */
35 #define NET_VERSION "9"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PAL_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_GPHY_INTR_IMR 0xe022
67 #define PLA_EEE_CR 0xe040
68 #define PLA_EEEP_CR 0xe080
69 #define PLA_MAC_PWR_CTRL 0xe0c0
70 #define PLA_MAC_PWR_CTRL2 0xe0ca
71 #define PLA_MAC_PWR_CTRL3 0xe0cc
72 #define PLA_MAC_PWR_CTRL4 0xe0ce
73 #define PLA_WDT6_CTRL 0xe428
74 #define PLA_TCR0 0xe610
75 #define PLA_TCR1 0xe612
76 #define PLA_MTPS 0xe615
77 #define PLA_TXFIFO_CTRL 0xe618
78 #define PLA_RSTTALLY 0xe800
80 #define PLA_CRWECR 0xe81c
81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5 0xe822
84 #define PLA_PHY_PWR 0xe84c
85 #define PLA_OOB_CTRL 0xe84f
86 #define PLA_CPCR 0xe854
87 #define PLA_MISC_0 0xe858
88 #define PLA_MISC_1 0xe85a
89 #define PLA_OCP_GPHY_BASE 0xe86c
90 #define PLA_TALLYCNT 0xe890
91 #define PLA_SFF_STS_7 0xe8de
92 #define PLA_PHYSTATUS 0xe908
93 #define PLA_BP_BA 0xfc26
94 #define PLA_BP_0 0xfc28
95 #define PLA_BP_1 0xfc2a
96 #define PLA_BP_2 0xfc2c
97 #define PLA_BP_3 0xfc2e
98 #define PLA_BP_4 0xfc30
99 #define PLA_BP_5 0xfc32
100 #define PLA_BP_6 0xfc34
101 #define PLA_BP_7 0xfc36
102 #define PLA_BP_EN 0xfc38
104 #define USB_USB2PHY 0xb41e
105 #define USB_SSPHYLINK2 0xb428
106 #define USB_U2P3_CTRL 0xb460
107 #define USB_CSR_DUMMY1 0xb464
108 #define USB_CSR_DUMMY2 0xb466
109 #define USB_DEV_STAT 0xb808
110 #define USB_CONNECT_TIMER 0xcbf8
111 #define USB_MSC_TIMER 0xcbfc
112 #define USB_BURST_SIZE 0xcfc0
113 #define USB_LPM_CONFIG 0xcfd8
114 #define USB_USB_CTRL 0xd406
115 #define USB_PHY_CTRL 0xd408
116 #define USB_TX_AGG 0xd40a
117 #define USB_RX_BUF_TH 0xd40c
118 #define USB_USB_TIMER 0xd428
119 #define USB_RX_EARLY_TIMEOUT 0xd42c
120 #define USB_RX_EARLY_SIZE 0xd42e
121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
123 #define USB_TX_DMA 0xd434
124 #define USB_UPT_RXDMA_OWN 0xd437
125 #define USB_TOLERANCE 0xd490
126 #define USB_LPM_CTRL 0xd41a
127 #define USB_BMU_RESET 0xd4b0
128 #define USB_U1U2_TIMER 0xd4da
129 #define USB_UPS_CTRL 0xd800
130 #define USB_POWER_CUT 0xd80a
131 #define USB_MISC_0 0xd81a
132 #define USB_AFE_CTRL2 0xd824
133 #define USB_UPS_CFG 0xd842
134 #define USB_UPS_FLAGS 0xd848
135 #define USB_WDT11_CTRL 0xe43c
136 #define USB_BP_BA 0xfc26
137 #define USB_BP_0 0xfc28
138 #define USB_BP_1 0xfc2a
139 #define USB_BP_2 0xfc2c
140 #define USB_BP_3 0xfc2e
141 #define USB_BP_4 0xfc30
142 #define USB_BP_5 0xfc32
143 #define USB_BP_6 0xfc34
144 #define USB_BP_7 0xfc36
145 #define USB_BP_EN 0xfc38
146 #define USB_BP_8 0xfc38
147 #define USB_BP_9 0xfc3a
148 #define USB_BP_10 0xfc3c
149 #define USB_BP_11 0xfc3e
150 #define USB_BP_12 0xfc40
151 #define USB_BP_13 0xfc42
152 #define USB_BP_14 0xfc44
153 #define USB_BP_15 0xfc46
154 #define USB_BP2_EN 0xfc48
157 #define OCP_ALDPS_CONFIG 0x2010
158 #define OCP_EEE_CONFIG1 0x2080
159 #define OCP_EEE_CONFIG2 0x2092
160 #define OCP_EEE_CONFIG3 0x2094
161 #define OCP_BASE_MII 0xa400
162 #define OCP_EEE_AR 0xa41a
163 #define OCP_EEE_DATA 0xa41c
164 #define OCP_PHY_STATUS 0xa420
165 #define OCP_NCTL_CFG 0xa42c
166 #define OCP_POWER_CFG 0xa430
167 #define OCP_EEE_CFG 0xa432
168 #define OCP_SRAM_ADDR 0xa436
169 #define OCP_SRAM_DATA 0xa438
170 #define OCP_DOWN_SPEED 0xa442
171 #define OCP_EEE_ABLE 0xa5c4
172 #define OCP_EEE_ADV 0xa5d0
173 #define OCP_EEE_LPABLE 0xa5d2
174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT 0xb800
176 #define OCP_PHY_PATCH_CMD 0xb820
177 #define OCP_ADC_IOFFSET 0xbcfc
178 #define OCP_ADC_CFG 0xbc06
179 #define OCP_SYSCLK_CFG 0xc416
182 #define SRAM_GREEN_CFG 0x8011
183 #define SRAM_LPF_CFG 0x8012
184 #define SRAM_10M_AMP1 0x8080
185 #define SRAM_10M_AMP2 0x8082
186 #define SRAM_IMPEDANCE 0x8084
189 #define RCR_AAP 0x00000001
190 #define RCR_APM 0x00000002
191 #define RCR_AM 0x00000004
192 #define RCR_AB 0x00000008
193 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL 0x00080002
197 #define RXFIFO_THR1_OOB 0x01800003
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL 0x00000060
201 #define RXFIFO_THR2_HIGH 0x00000038
202 #define RXFIFO_THR2_OOB 0x0000004a
203 #define RXFIFO_THR2_NORMAL 0x00a0
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL 0x00000078
207 #define RXFIFO_THR3_HIGH 0x00000048
208 #define RXFIFO_THR3_OOB 0x0000005a
209 #define RXFIFO_THR3_NORMAL 0x0110
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL 0x00400008
213 #define TXFIFO_THR_NORMAL2 0x01000008
216 #define ECM_ALDPS 0x0002
219 #define FMC_FCR_MCU_EN 0x0001
222 #define EEEP_CR_EEEP_TX 0x0002
225 #define WDT6_SET_MODE 0x0010
228 #define TCR0_TX_EMPTY 0x0800
229 #define TCR0_AUTO_FIFO 0x0080
232 #define VERSION_MASK 0x7cf0
235 #define MTPS_JUMBO (12 * 1024 / 64)
236 #define MTPS_DEFAULT (6 * 1024 / 64)
239 #define TALLY_RESET 0x0001
247 #define CRWECR_NORAML 0x00
248 #define CRWECR_CONFIG 0xc0
251 #define NOW_IS_OOB 0x80
252 #define TXFIFO_EMPTY 0x20
253 #define RXFIFO_EMPTY 0x10
254 #define LINK_LIST_READY 0x02
255 #define DIS_MCU_CLROOB 0x01
256 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
259 #define RXDY_GATED_EN 0x0008
262 #define RE_INIT_LL 0x8000
263 #define MCU_BORW_EN 0x4000
266 #define CPCR_RX_VLAN 0x0040
269 #define MAGIC_EN 0x0001
272 #define TEREDO_SEL 0x8000
273 #define TEREDO_WAKE_MASK 0x7f00
274 #define TEREDO_RS_EVENT_MASK 0x00fe
275 #define OOB_TEREDO_EN 0x0001
278 #define ALDPS_PROXY_MODE 0x0001
281 #define EFUSE_READ_CMD BIT(15)
282 #define EFUSE_DATA_BIT16 BIT(7)
285 #define LINK_ON_WAKE_EN 0x0010
286 #define LINK_OFF_WAKE_EN 0x0008
289 #define BWF_EN 0x0040
290 #define MWF_EN 0x0020
291 #define UWF_EN 0x0010
292 #define LAN_WAKE_EN 0x0002
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK 0x0700
298 #define TX_10M_IDLE_EN 0x0080
299 #define PFM_PWM_SWITCH 0x0040
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN 0x00004000
303 #define MCU_CLK_RATIO 0x07010f07
304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO 0x0f87
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO 0x8007
309 #define MAC_CLK_SPDWN_EN BIT(15)
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN 0x0100
313 #define SUSPEND_SPDWN_EN 0x0004
314 #define U1U2_SPDWN_EN 0x0002
315 #define L1_SPDWN_EN 0x0001
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN 0x1000
319 #define RXDV_SPDWN_EN 0x0800
320 #define TX10MIDLE_EN 0x0100
321 #define TP100_SPDWN_EN 0x0020
322 #define TP500_SPDWN_EN 0x0010
323 #define TP1000_SPDWN_EN 0x0008
324 #define EEE_SPDWN_EN 0x0001
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK 0x0001
328 #define SPEED_DOWN_MSK 0x0002
329 #define SPDWN_RXDV_MSK 0x0004
330 #define SPDWN_LINKCHG_MSK 0x0008
333 #define PHYAR_FLAG 0x80000000
336 #define EEE_RX_EN 0x0001
337 #define EEE_TX_EN 0x0002
340 #define AUTOLOAD_DONE 0x0002
343 #define USB2PHY_SUSPEND 0x0001
344 #define USB2PHY_L1 0x0002
347 #define pwd_dn_scale_mask 0x3ffe
348 #define pwd_dn_scale(x) ((x) << 1)
351 #define DYNAMIC_BURST 0x0001
354 #define EP4_FULL_FC 0x0001
357 #define STAT_SPEED_MASK 0x0006
358 #define STAT_SPEED_HIGH 0x0000
359 #define STAT_SPEED_FULL 0x0002
362 #define LPM_U1U2_EN BIT(0)
365 #define TX_AGG_MAX_THRESHOLD 0x03
368 #define RX_THR_SUPPER 0x0c350180
369 #define RX_THR_HIGH 0x7a120180
370 #define RX_THR_SLOW 0xffff0180
371 #define RX_THR_B 0x00010001
374 #define TEST_MODE_DISABLE 0x00000001
375 #define TX_SIZE_ADJUST1 0x00000100
378 #define BMU_RESET_EP_IN 0x01
379 #define BMU_RESET_EP_OUT 0x02
381 /* USB_UPT_RXDMA_OWN */
382 #define OWN_UPDATE BIT(0)
383 #define OWN_CLEAR BIT(1)
386 #define POWER_CUT 0x0100
388 /* USB_PM_CTRL_STATUS */
389 #define RESUME_INDICATE 0x0001
392 #define RX_AGG_DISABLE 0x0010
393 #define RX_ZERO_EN 0x0080
396 #define U2P3_ENABLE 0x0001
399 #define PWR_EN 0x0001
400 #define PHASE2_EN 0x0008
401 #define UPS_EN BIT(4)
402 #define USP_PREWAKE BIT(5)
405 #define PCUT_STATUS 0x0001
407 /* USB_RX_EARLY_TIMEOUT */
408 #define COALESCE_SUPER 85000U
409 #define COALESCE_HIGH 250000U
410 #define COALESCE_SLOW 524280U
413 #define TIMER11_EN 0x0001
416 /* bit 4 ~ 5: fifo empty boundary */
417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
418 /* bit 2 ~ 3: LMP timer */
419 #define LPM_TIMER_MASK 0x0c
420 #define LPM_TIMER_500MS 0x04 /* 500 ms */
421 #define LPM_TIMER_500US 0x0c /* 500 us */
422 #define ROK_EXIT_LPM 0x02
425 #define SEN_VAL_MASK 0xf800
426 #define SEN_VAL_NORMAL 0xa000
427 #define SEL_RXIDLE 0x0100
430 #define SAW_CNT_1MS_MASK 0x0fff
433 #define UPS_FLAGS_R_TUNE BIT(0)
434 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
435 #define UPS_FLAGS_250M_CKDIV BIT(2)
436 #define UPS_FLAGS_EN_ALDPS BIT(3)
437 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
438 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
439 #define ups_flags_speed(x) ((x) << 16)
440 #define UPS_FLAGS_EN_EEE BIT(20)
441 #define UPS_FLAGS_EN_500M_EEE BIT(21)
442 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
443 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
444 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
445 #define UPS_FLAGS_EN_GREEN BIT(26)
446 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
460 /* OCP_ALDPS_CONFIG */
461 #define ENPWRSAVE 0x8000
462 #define ENPDNPS 0x0200
463 #define LINKENA 0x0100
464 #define DIS_SDSAVE 0x0010
467 #define PHY_STAT_MASK 0x0007
468 #define PHY_STAT_EXT_INIT 2
469 #define PHY_STAT_LAN_ON 3
470 #define PHY_STAT_PWRDN 5
473 #define PGA_RETURN_EN BIT(1)
476 #define EEE_CLKDIV_EN 0x8000
477 #define EN_ALDPS 0x0004
478 #define EN_10M_PLLOFF 0x0001
480 /* OCP_EEE_CONFIG1 */
481 #define RG_TXLPI_MSK_HFDUP 0x8000
482 #define RG_MATCLR_EN 0x4000
483 #define EEE_10_CAP 0x2000
484 #define EEE_NWAY_EN 0x1000
485 #define TX_QUIET_EN 0x0200
486 #define RX_QUIET_EN 0x0100
487 #define sd_rise_time_mask 0x0070
488 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
489 #define RG_RXLPI_MSK_HFDUP 0x0008
490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
492 /* OCP_EEE_CONFIG2 */
493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
494 #define RG_DACQUIET_EN 0x0400
495 #define RG_LDVQUIET_EN 0x0200
496 #define RG_CKRSEL 0x0020
497 #define RG_EEEPRG_EN 0x0010
499 /* OCP_EEE_CONFIG3 */
500 #define fast_snr_mask 0xff80
501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
506 /* bit[15:14] function */
507 #define FUN_ADDR 0x0000
508 #define FUN_DATA 0x4000
509 /* bit[4:0] device addr */
512 #define CTAP_SHORT_EN 0x0040
513 #define EEE10_EN 0x0010
516 #define EN_EEE_CMODE BIT(14)
517 #define EN_EEE_1000 BIT(13)
518 #define EN_EEE_100 BIT(12)
519 #define EN_10M_CLKDIV BIT(11)
520 #define EN_10M_BGOFF 0x0080
523 #define TXDIS_STATE 0x01
524 #define ABD_STATE 0x02
526 /* OCP_PHY_PATCH_STAT */
527 #define PATCH_READY BIT(6)
529 /* OCP_PHY_PATCH_CMD */
530 #define PATCH_REQUEST BIT(4)
533 #define CKADSEL_L 0x0100
534 #define ADC_EN 0x0080
535 #define EN_EMI_L 0x0040
538 #define clk_div_expo(x) (min(x, 5) << 8)
541 #define GREEN_ETH_EN BIT(15)
542 #define R_TUNE_EN BIT(11)
545 #define LPF_AUTO_TUNE 0x8000
548 #define GDAC_IB_UPALL 0x0008
551 #define AMP_DN 0x0200
554 #define RX_DRIVING_MASK 0x6000
557 #define AD_MASK 0xfee0
559 #define PASS_THRU_MASK 0x1
561 enum rtl_register_content
{
569 #define RTL8152_MAX_TX 4
570 #define RTL8152_MAX_RX 10
575 #define INTR_LINK 0x0004
577 #define RTL8152_REQT_READ 0xc0
578 #define RTL8152_REQT_WRITE 0x40
579 #define RTL8152_REQ_GET_REGS 0x05
580 #define RTL8152_REQ_SET_REGS 0x05
582 #define BYTE_EN_DWORD 0xff
583 #define BYTE_EN_WORD 0x33
584 #define BYTE_EN_BYTE 0x11
585 #define BYTE_EN_SIX_BYTES 0x3f
586 #define BYTE_EN_START_MASK 0x0f
587 #define BYTE_EN_END_MASK 0xf0
589 #define RTL8153_MAX_PACKET 9216 /* 9K */
590 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
592 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
593 #define RTL8153_RMS RTL8153_MAX_PACKET
594 #define RTL8152_TX_TIMEOUT (5 * HZ)
595 #define RTL8152_NAPI_WEIGHT 64
596 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
597 sizeof(struct rx_desc) + RX_ALIGN)
611 /* Define these values to match your device */
612 #define VENDOR_ID_REALTEK 0x0bda
613 #define VENDOR_ID_MICROSOFT 0x045e
614 #define VENDOR_ID_SAMSUNG 0x04e8
615 #define VENDOR_ID_LENOVO 0x17ef
616 #define VENDOR_ID_LINKSYS 0x13b1
617 #define VENDOR_ID_NVIDIA 0x0955
618 #define VENDOR_ID_TPLINK 0x2357
620 #define MCU_TYPE_PLA 0x0100
621 #define MCU_TYPE_USB 0x0000
623 struct tally_counter
{
630 __le32 tx_one_collision
;
631 __le32 tx_multi_collision
;
641 #define RX_LEN_MASK 0x7fff
644 #define RD_UDP_CS BIT(23)
645 #define RD_TCP_CS BIT(22)
646 #define RD_IPV6_CS BIT(20)
647 #define RD_IPV4_CS BIT(19)
650 #define IPF BIT(23) /* IP checksum fail */
651 #define UDPF BIT(22) /* UDP checksum fail */
652 #define TCPF BIT(21) /* TCP checksum fail */
653 #define RX_VLAN_TAG BIT(16)
662 #define TX_FS BIT(31) /* First segment of a packet */
663 #define TX_LS BIT(30) /* Final segment of a packet */
664 #define GTSENDV4 BIT(28)
665 #define GTSENDV6 BIT(27)
666 #define GTTCPHO_SHIFT 18
667 #define GTTCPHO_MAX 0x7fU
668 #define TX_LEN_MAX 0x3ffffU
671 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
672 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
673 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
674 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
676 #define MSS_MAX 0x7ffU
677 #define TCPHO_SHIFT 17
678 #define TCPHO_MAX 0x7ffU
679 #define TX_VLAN_TAG BIT(16)
685 struct list_head list
;
687 struct r8152
*context
;
693 struct list_head list
;
695 struct r8152
*context
;
704 struct usb_device
*udev
;
705 struct napi_struct napi
;
706 struct usb_interface
*intf
;
707 struct net_device
*netdev
;
708 struct urb
*intr_urb
;
709 struct tx_agg tx_info
[RTL8152_MAX_TX
];
710 struct rx_agg rx_info
[RTL8152_MAX_RX
];
711 struct list_head rx_done
, tx_free
;
712 struct sk_buff_head tx_queue
, rx_queue
;
713 spinlock_t rx_lock
, tx_lock
;
714 struct delayed_work schedule
, hw_phy_work
;
715 struct mii_if_info mii
;
716 struct mutex control
; /* use for hw setting */
717 #ifdef CONFIG_PM_SLEEP
718 struct notifier_block pm_notifier
;
722 void (*init
)(struct r8152
*);
723 int (*enable
)(struct r8152
*);
724 void (*disable
)(struct r8152
*);
725 void (*up
)(struct r8152
*);
726 void (*down
)(struct r8152
*);
727 void (*unload
)(struct r8152
*);
728 int (*eee_get
)(struct r8152
*, struct ethtool_eee
*);
729 int (*eee_set
)(struct r8152
*, struct ethtool_eee
*);
730 bool (*in_nway
)(struct r8152
*);
731 void (*hw_phy_cfg
)(struct r8152
*);
732 void (*autosuspend_en
)(struct r8152
*tp
, bool enable
);
768 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
769 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
771 static const int multicast_filter_limit
= 32;
772 static unsigned int agg_buf_sz
= 16384;
774 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
775 VLAN_ETH_HLEN - ETH_FCS_LEN)
778 int get_registers(struct r8152
*tp
, u16 value
, u16 index
, u16 size
, void *data
)
783 tmp
= kmalloc(size
, GFP_KERNEL
);
787 ret
= usb_control_msg(tp
->udev
, usb_rcvctrlpipe(tp
->udev
, 0),
788 RTL8152_REQ_GET_REGS
, RTL8152_REQT_READ
,
789 value
, index
, tmp
, size
, 500);
791 memcpy(data
, tmp
, size
);
798 int set_registers(struct r8152
*tp
, u16 value
, u16 index
, u16 size
, void *data
)
803 tmp
= kmemdup(data
, size
, GFP_KERNEL
);
807 ret
= usb_control_msg(tp
->udev
, usb_sndctrlpipe(tp
->udev
, 0),
808 RTL8152_REQ_SET_REGS
, RTL8152_REQT_WRITE
,
809 value
, index
, tmp
, size
, 500);
816 static int generic_ocp_read(struct r8152
*tp
, u16 index
, u16 size
,
817 void *data
, u16 type
)
822 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
825 /* both size and indix must be 4 bytes align */
826 if ((size
& 3) || !size
|| (index
& 3) || !data
)
829 if ((u32
)index
+ (u32
)size
> 0xffff)
834 ret
= get_registers(tp
, index
, type
, limit
, data
);
842 ret
= get_registers(tp
, index
, type
, size
, data
);
854 set_bit(RTL8152_UNPLUG
, &tp
->flags
);
859 static int generic_ocp_write(struct r8152
*tp
, u16 index
, u16 byteen
,
860 u16 size
, void *data
, u16 type
)
863 u16 byteen_start
, byteen_end
, byen
;
866 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
869 /* both size and indix must be 4 bytes align */
870 if ((size
& 3) || !size
|| (index
& 3) || !data
)
873 if ((u32
)index
+ (u32
)size
> 0xffff)
876 byteen_start
= byteen
& BYTE_EN_START_MASK
;
877 byteen_end
= byteen
& BYTE_EN_END_MASK
;
879 byen
= byteen_start
| (byteen_start
<< 4);
880 ret
= set_registers(tp
, index
, type
| byen
, 4, data
);
893 ret
= set_registers(tp
, index
,
894 type
| BYTE_EN_DWORD
,
903 ret
= set_registers(tp
, index
,
904 type
| BYTE_EN_DWORD
,
916 byen
= byteen_end
| (byteen_end
>> 4);
917 ret
= set_registers(tp
, index
, type
| byen
, 4, data
);
924 set_bit(RTL8152_UNPLUG
, &tp
->flags
);
930 int pla_ocp_read(struct r8152
*tp
, u16 index
, u16 size
, void *data
)
932 return generic_ocp_read(tp
, index
, size
, data
, MCU_TYPE_PLA
);
936 int pla_ocp_write(struct r8152
*tp
, u16 index
, u16 byteen
, u16 size
, void *data
)
938 return generic_ocp_write(tp
, index
, byteen
, size
, data
, MCU_TYPE_PLA
);
942 int usb_ocp_write(struct r8152
*tp
, u16 index
, u16 byteen
, u16 size
, void *data
)
944 return generic_ocp_write(tp
, index
, byteen
, size
, data
, MCU_TYPE_USB
);
947 static u32
ocp_read_dword(struct r8152
*tp
, u16 type
, u16 index
)
951 generic_ocp_read(tp
, index
, sizeof(data
), &data
, type
);
953 return __le32_to_cpu(data
);
956 static void ocp_write_dword(struct r8152
*tp
, u16 type
, u16 index
, u32 data
)
958 __le32 tmp
= __cpu_to_le32(data
);
960 generic_ocp_write(tp
, index
, BYTE_EN_DWORD
, sizeof(tmp
), &tmp
, type
);
963 static u16
ocp_read_word(struct r8152
*tp
, u16 type
, u16 index
)
967 u16 byen
= BYTE_EN_WORD
;
968 u8 shift
= index
& 2;
973 generic_ocp_read(tp
, index
, sizeof(tmp
), &tmp
, type
| byen
);
975 data
= __le32_to_cpu(tmp
);
976 data
>>= (shift
* 8);
982 static void ocp_write_word(struct r8152
*tp
, u16 type
, u16 index
, u32 data
)
986 u16 byen
= BYTE_EN_WORD
;
987 u8 shift
= index
& 2;
993 mask
<<= (shift
* 8);
994 data
<<= (shift
* 8);
998 tmp
= __cpu_to_le32(data
);
1000 generic_ocp_write(tp
, index
, byen
, sizeof(tmp
), &tmp
, type
);
1003 static u8
ocp_read_byte(struct r8152
*tp
, u16 type
, u16 index
)
1007 u8 shift
= index
& 3;
1011 generic_ocp_read(tp
, index
, sizeof(tmp
), &tmp
, type
);
1013 data
= __le32_to_cpu(tmp
);
1014 data
>>= (shift
* 8);
1020 static void ocp_write_byte(struct r8152
*tp
, u16 type
, u16 index
, u32 data
)
1024 u16 byen
= BYTE_EN_BYTE
;
1025 u8 shift
= index
& 3;
1031 mask
<<= (shift
* 8);
1032 data
<<= (shift
* 8);
1036 tmp
= __cpu_to_le32(data
);
1038 generic_ocp_write(tp
, index
, byen
, sizeof(tmp
), &tmp
, type
);
1041 static u16
ocp_reg_read(struct r8152
*tp
, u16 addr
)
1043 u16 ocp_base
, ocp_index
;
1045 ocp_base
= addr
& 0xf000;
1046 if (ocp_base
!= tp
->ocp_base
) {
1047 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_OCP_GPHY_BASE
, ocp_base
);
1048 tp
->ocp_base
= ocp_base
;
1051 ocp_index
= (addr
& 0x0fff) | 0xb000;
1052 return ocp_read_word(tp
, MCU_TYPE_PLA
, ocp_index
);
1055 static void ocp_reg_write(struct r8152
*tp
, u16 addr
, u16 data
)
1057 u16 ocp_base
, ocp_index
;
1059 ocp_base
= addr
& 0xf000;
1060 if (ocp_base
!= tp
->ocp_base
) {
1061 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_OCP_GPHY_BASE
, ocp_base
);
1062 tp
->ocp_base
= ocp_base
;
1065 ocp_index
= (addr
& 0x0fff) | 0xb000;
1066 ocp_write_word(tp
, MCU_TYPE_PLA
, ocp_index
, data
);
1069 static inline void r8152_mdio_write(struct r8152
*tp
, u32 reg_addr
, u32 value
)
1071 ocp_reg_write(tp
, OCP_BASE_MII
+ reg_addr
* 2, value
);
1074 static inline int r8152_mdio_read(struct r8152
*tp
, u32 reg_addr
)
1076 return ocp_reg_read(tp
, OCP_BASE_MII
+ reg_addr
* 2);
1079 static void sram_write(struct r8152
*tp
, u16 addr
, u16 data
)
1081 ocp_reg_write(tp
, OCP_SRAM_ADDR
, addr
);
1082 ocp_reg_write(tp
, OCP_SRAM_DATA
, data
);
1085 static u16
sram_read(struct r8152
*tp
, u16 addr
)
1087 ocp_reg_write(tp
, OCP_SRAM_ADDR
, addr
);
1088 return ocp_reg_read(tp
, OCP_SRAM_DATA
);
1091 static int read_mii_word(struct net_device
*netdev
, int phy_id
, int reg
)
1093 struct r8152
*tp
= netdev_priv(netdev
);
1096 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1099 if (phy_id
!= R8152_PHY_ID
)
1102 ret
= r8152_mdio_read(tp
, reg
);
1108 void write_mii_word(struct net_device
*netdev
, int phy_id
, int reg
, int val
)
1110 struct r8152
*tp
= netdev_priv(netdev
);
1112 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1115 if (phy_id
!= R8152_PHY_ID
)
1118 r8152_mdio_write(tp
, reg
, val
);
1122 r8152_submit_rx(struct r8152
*tp
, struct rx_agg
*agg
, gfp_t mem_flags
);
1124 static int rtl8152_set_mac_address(struct net_device
*netdev
, void *p
)
1126 struct r8152
*tp
= netdev_priv(netdev
);
1127 struct sockaddr
*addr
= p
;
1128 int ret
= -EADDRNOTAVAIL
;
1130 if (!is_valid_ether_addr(addr
->sa_data
))
1133 ret
= usb_autopm_get_interface(tp
->intf
);
1137 mutex_lock(&tp
->control
);
1139 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1141 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
1142 pla_ocp_write(tp
, PLA_IDR
, BYTE_EN_SIX_BYTES
, 8, addr
->sa_data
);
1143 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
1145 mutex_unlock(&tp
->control
);
1147 usb_autopm_put_interface(tp
->intf
);
1152 /* Devices containing RTL8153-AD can support a persistent
1153 * host system provided MAC address.
1154 * Examples of this are Dell TB15 and Dell WD15 docks
1156 static int vendor_mac_passthru_addr_read(struct r8152
*tp
, struct sockaddr
*sa
)
1159 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
1160 union acpi_object
*obj
;
1163 unsigned char buf
[6];
1165 /* test for -AD variant of RTL8153 */
1166 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
1167 if ((ocp_data
& AD_MASK
) != 0x1000)
1170 /* test for MAC address pass-through bit */
1171 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, EFUSE
);
1172 if ((ocp_data
& PASS_THRU_MASK
) != 1)
1175 /* returns _AUXMAC_#AABBCCDDEEFF# */
1176 status
= acpi_evaluate_object(NULL
, "\\_SB.AMAC", NULL
, &buffer
);
1177 obj
= (union acpi_object
*)buffer
.pointer
;
1178 if (!ACPI_SUCCESS(status
))
1180 if (obj
->type
!= ACPI_TYPE_BUFFER
|| obj
->string
.length
!= 0x17) {
1181 netif_warn(tp
, probe
, tp
->netdev
,
1182 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1183 obj
->type
, obj
->string
.length
);
1186 if (strncmp(obj
->string
.pointer
, "_AUXMAC_#", 9) != 0 ||
1187 strncmp(obj
->string
.pointer
+ 0x15, "#", 1) != 0) {
1188 netif_warn(tp
, probe
, tp
->netdev
,
1189 "Invalid header when reading pass-thru MAC addr\n");
1192 ret
= hex2bin(buf
, obj
->string
.pointer
+ 9, 6);
1193 if (!(ret
== 0 && is_valid_ether_addr(buf
))) {
1194 netif_warn(tp
, probe
, tp
->netdev
,
1195 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1200 memcpy(sa
->sa_data
, buf
, 6);
1201 ether_addr_copy(tp
->netdev
->dev_addr
, sa
->sa_data
);
1202 netif_info(tp
, probe
, tp
->netdev
,
1203 "Using pass-thru MAC addr %pM\n", sa
->sa_data
);
1210 static int set_ethernet_addr(struct r8152
*tp
)
1212 struct net_device
*dev
= tp
->netdev
;
1216 if (tp
->version
== RTL_VER_01
) {
1217 ret
= pla_ocp_read(tp
, PLA_IDR
, 8, sa
.sa_data
);
1219 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1220 * or system doesn't provide valid _SB.AMAC this will be
1221 * be expected to non-zero
1223 ret
= vendor_mac_passthru_addr_read(tp
, &sa
);
1225 ret
= pla_ocp_read(tp
, PLA_BACKUP
, 8, sa
.sa_data
);
1229 netif_err(tp
, probe
, dev
, "Get ether addr fail\n");
1230 } else if (!is_valid_ether_addr(sa
.sa_data
)) {
1231 netif_err(tp
, probe
, dev
, "Invalid ether addr %pM\n",
1233 eth_hw_addr_random(dev
);
1234 ether_addr_copy(sa
.sa_data
, dev
->dev_addr
);
1235 ret
= rtl8152_set_mac_address(dev
, &sa
);
1236 netif_info(tp
, probe
, dev
, "Random ether addr %pM\n",
1239 if (tp
->version
== RTL_VER_01
)
1240 ether_addr_copy(dev
->dev_addr
, sa
.sa_data
);
1242 ret
= rtl8152_set_mac_address(dev
, &sa
);
1248 static void read_bulk_callback(struct urb
*urb
)
1250 struct net_device
*netdev
;
1251 int status
= urb
->status
;
1263 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1266 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
1269 netdev
= tp
->netdev
;
1271 /* When link down, the driver would cancel all bulks. */
1272 /* This avoid the re-submitting bulk */
1273 if (!netif_carrier_ok(netdev
))
1276 usb_mark_last_busy(tp
->udev
);
1280 if (urb
->actual_length
< ETH_ZLEN
)
1283 spin_lock(&tp
->rx_lock
);
1284 list_add_tail(&agg
->list
, &tp
->rx_done
);
1285 spin_unlock(&tp
->rx_lock
);
1286 napi_schedule(&tp
->napi
);
1289 set_bit(RTL8152_UNPLUG
, &tp
->flags
);
1290 netif_device_detach(tp
->netdev
);
1293 return; /* the urb is in unlink state */
1295 if (net_ratelimit())
1296 netdev_warn(netdev
, "maybe reset is needed?\n");
1299 if (net_ratelimit())
1300 netdev_warn(netdev
, "Rx status %d\n", status
);
1304 r8152_submit_rx(tp
, agg
, GFP_ATOMIC
);
1307 static void write_bulk_callback(struct urb
*urb
)
1309 struct net_device_stats
*stats
;
1310 struct net_device
*netdev
;
1313 int status
= urb
->status
;
1323 netdev
= tp
->netdev
;
1324 stats
= &netdev
->stats
;
1326 if (net_ratelimit())
1327 netdev_warn(netdev
, "Tx status %d\n", status
);
1328 stats
->tx_errors
+= agg
->skb_num
;
1330 stats
->tx_packets
+= agg
->skb_num
;
1331 stats
->tx_bytes
+= agg
->skb_len
;
1334 spin_lock(&tp
->tx_lock
);
1335 list_add_tail(&agg
->list
, &tp
->tx_free
);
1336 spin_unlock(&tp
->tx_lock
);
1338 usb_autopm_put_interface_async(tp
->intf
);
1340 if (!netif_carrier_ok(netdev
))
1343 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
1346 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1349 if (!skb_queue_empty(&tp
->tx_queue
))
1350 napi_schedule(&tp
->napi
);
1353 static void intr_callback(struct urb
*urb
)
1357 int status
= urb
->status
;
1364 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
1367 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
1371 case 0: /* success */
1373 case -ECONNRESET
: /* unlink */
1375 netif_device_detach(tp
->netdev
);
1378 netif_info(tp
, intr
, tp
->netdev
,
1379 "Stop submitting intr, status %d\n", status
);
1382 netif_info(tp
, intr
, tp
->netdev
, "intr status -EOVERFLOW\n");
1384 /* -EPIPE: should clear the halt */
1386 netif_info(tp
, intr
, tp
->netdev
, "intr status %d\n", status
);
1390 d
= urb
->transfer_buffer
;
1391 if (INTR_LINK
& __le16_to_cpu(d
[0])) {
1392 if (!netif_carrier_ok(tp
->netdev
)) {
1393 set_bit(RTL8152_LINK_CHG
, &tp
->flags
);
1394 schedule_delayed_work(&tp
->schedule
, 0);
1397 if (netif_carrier_ok(tp
->netdev
)) {
1398 netif_stop_queue(tp
->netdev
);
1399 set_bit(RTL8152_LINK_CHG
, &tp
->flags
);
1400 schedule_delayed_work(&tp
->schedule
, 0);
1405 res
= usb_submit_urb(urb
, GFP_ATOMIC
);
1406 if (res
== -ENODEV
) {
1407 set_bit(RTL8152_UNPLUG
, &tp
->flags
);
1408 netif_device_detach(tp
->netdev
);
1410 netif_err(tp
, intr
, tp
->netdev
,
1411 "can't resubmit intr, status %d\n", res
);
1415 static inline void *rx_agg_align(void *data
)
1417 return (void *)ALIGN((uintptr_t)data
, RX_ALIGN
);
1420 static inline void *tx_agg_align(void *data
)
1422 return (void *)ALIGN((uintptr_t)data
, TX_ALIGN
);
1425 static void free_all_mem(struct r8152
*tp
)
1429 for (i
= 0; i
< RTL8152_MAX_RX
; i
++) {
1430 usb_free_urb(tp
->rx_info
[i
].urb
);
1431 tp
->rx_info
[i
].urb
= NULL
;
1433 kfree(tp
->rx_info
[i
].buffer
);
1434 tp
->rx_info
[i
].buffer
= NULL
;
1435 tp
->rx_info
[i
].head
= NULL
;
1438 for (i
= 0; i
< RTL8152_MAX_TX
; i
++) {
1439 usb_free_urb(tp
->tx_info
[i
].urb
);
1440 tp
->tx_info
[i
].urb
= NULL
;
1442 kfree(tp
->tx_info
[i
].buffer
);
1443 tp
->tx_info
[i
].buffer
= NULL
;
1444 tp
->tx_info
[i
].head
= NULL
;
1447 usb_free_urb(tp
->intr_urb
);
1448 tp
->intr_urb
= NULL
;
1450 kfree(tp
->intr_buff
);
1451 tp
->intr_buff
= NULL
;
1454 static int alloc_all_mem(struct r8152
*tp
)
1456 struct net_device
*netdev
= tp
->netdev
;
1457 struct usb_interface
*intf
= tp
->intf
;
1458 struct usb_host_interface
*alt
= intf
->cur_altsetting
;
1459 struct usb_host_endpoint
*ep_intr
= alt
->endpoint
+ 2;
1464 node
= netdev
->dev
.parent
? dev_to_node(netdev
->dev
.parent
) : -1;
1466 spin_lock_init(&tp
->rx_lock
);
1467 spin_lock_init(&tp
->tx_lock
);
1468 INIT_LIST_HEAD(&tp
->tx_free
);
1469 INIT_LIST_HEAD(&tp
->rx_done
);
1470 skb_queue_head_init(&tp
->tx_queue
);
1471 skb_queue_head_init(&tp
->rx_queue
);
1473 for (i
= 0; i
< RTL8152_MAX_RX
; i
++) {
1474 buf
= kmalloc_node(agg_buf_sz
, GFP_KERNEL
, node
);
1478 if (buf
!= rx_agg_align(buf
)) {
1480 buf
= kmalloc_node(agg_buf_sz
+ RX_ALIGN
, GFP_KERNEL
,
1486 urb
= usb_alloc_urb(0, GFP_KERNEL
);
1492 INIT_LIST_HEAD(&tp
->rx_info
[i
].list
);
1493 tp
->rx_info
[i
].context
= tp
;
1494 tp
->rx_info
[i
].urb
= urb
;
1495 tp
->rx_info
[i
].buffer
= buf
;
1496 tp
->rx_info
[i
].head
= rx_agg_align(buf
);
1499 for (i
= 0; i
< RTL8152_MAX_TX
; i
++) {
1500 buf
= kmalloc_node(agg_buf_sz
, GFP_KERNEL
, node
);
1504 if (buf
!= tx_agg_align(buf
)) {
1506 buf
= kmalloc_node(agg_buf_sz
+ TX_ALIGN
, GFP_KERNEL
,
1512 urb
= usb_alloc_urb(0, GFP_KERNEL
);
1518 INIT_LIST_HEAD(&tp
->tx_info
[i
].list
);
1519 tp
->tx_info
[i
].context
= tp
;
1520 tp
->tx_info
[i
].urb
= urb
;
1521 tp
->tx_info
[i
].buffer
= buf
;
1522 tp
->tx_info
[i
].head
= tx_agg_align(buf
);
1524 list_add_tail(&tp
->tx_info
[i
].list
, &tp
->tx_free
);
1527 tp
->intr_urb
= usb_alloc_urb(0, GFP_KERNEL
);
1531 tp
->intr_buff
= kmalloc(INTBUFSIZE
, GFP_KERNEL
);
1535 tp
->intr_interval
= (int)ep_intr
->desc
.bInterval
;
1536 usb_fill_int_urb(tp
->intr_urb
, tp
->udev
, usb_rcvintpipe(tp
->udev
, 3),
1537 tp
->intr_buff
, INTBUFSIZE
, intr_callback
,
1538 tp
, tp
->intr_interval
);
1547 static struct tx_agg
*r8152_get_tx_agg(struct r8152
*tp
)
1549 struct tx_agg
*agg
= NULL
;
1550 unsigned long flags
;
1552 if (list_empty(&tp
->tx_free
))
1555 spin_lock_irqsave(&tp
->tx_lock
, flags
);
1556 if (!list_empty(&tp
->tx_free
)) {
1557 struct list_head
*cursor
;
1559 cursor
= tp
->tx_free
.next
;
1560 list_del_init(cursor
);
1561 agg
= list_entry(cursor
, struct tx_agg
, list
);
1563 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
1568 /* r8152_csum_workaround()
1569 * The hw limites the value the transport offset. When the offset is out of the
1570 * range, calculate the checksum by sw.
1572 static void r8152_csum_workaround(struct r8152
*tp
, struct sk_buff
*skb
,
1573 struct sk_buff_head
*list
)
1575 if (skb_shinfo(skb
)->gso_size
) {
1576 netdev_features_t features
= tp
->netdev
->features
;
1577 struct sk_buff_head seg_list
;
1578 struct sk_buff
*segs
, *nskb
;
1580 features
&= ~(NETIF_F_SG
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
);
1581 segs
= skb_gso_segment(skb
, features
);
1582 if (IS_ERR(segs
) || !segs
)
1585 __skb_queue_head_init(&seg_list
);
1591 __skb_queue_tail(&seg_list
, nskb
);
1594 skb_queue_splice(&seg_list
, list
);
1596 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1597 if (skb_checksum_help(skb
) < 0)
1600 __skb_queue_head(list
, skb
);
1602 struct net_device_stats
*stats
;
1605 stats
= &tp
->netdev
->stats
;
1606 stats
->tx_dropped
++;
1611 /* msdn_giant_send_check()
1612 * According to the document of microsoft, the TCP Pseudo Header excludes the
1613 * packet length for IPv6 TCP large packets.
1615 static int msdn_giant_send_check(struct sk_buff
*skb
)
1617 const struct ipv6hdr
*ipv6h
;
1621 ret
= skb_cow_head(skb
, 0);
1625 ipv6h
= ipv6_hdr(skb
);
1629 th
->check
= ~tcp_v6_check(0, &ipv6h
->saddr
, &ipv6h
->daddr
, 0);
1634 static inline void rtl_tx_vlan_tag(struct tx_desc
*desc
, struct sk_buff
*skb
)
1636 if (skb_vlan_tag_present(skb
)) {
1639 opts2
= TX_VLAN_TAG
| swab16(skb_vlan_tag_get(skb
));
1640 desc
->opts2
|= cpu_to_le32(opts2
);
1644 static inline void rtl_rx_vlan_tag(struct rx_desc
*desc
, struct sk_buff
*skb
)
1646 u32 opts2
= le32_to_cpu(desc
->opts2
);
1648 if (opts2
& RX_VLAN_TAG
)
1649 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
1650 swab16(opts2
& 0xffff));
1653 static int r8152_tx_csum(struct r8152
*tp
, struct tx_desc
*desc
,
1654 struct sk_buff
*skb
, u32 len
, u32 transport_offset
)
1656 u32 mss
= skb_shinfo(skb
)->gso_size
;
1657 u32 opts1
, opts2
= 0;
1658 int ret
= TX_CSUM_SUCCESS
;
1660 WARN_ON_ONCE(len
> TX_LEN_MAX
);
1662 opts1
= len
| TX_FS
| TX_LS
;
1665 if (transport_offset
> GTTCPHO_MAX
) {
1666 netif_warn(tp
, tx_err
, tp
->netdev
,
1667 "Invalid transport offset 0x%x for TSO\n",
1673 switch (vlan_get_protocol(skb
)) {
1674 case htons(ETH_P_IP
):
1678 case htons(ETH_P_IPV6
):
1679 if (msdn_giant_send_check(skb
)) {
1691 opts1
|= transport_offset
<< GTTCPHO_SHIFT
;
1692 opts2
|= min(mss
, MSS_MAX
) << MSS_SHIFT
;
1693 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1696 if (transport_offset
> TCPHO_MAX
) {
1697 netif_warn(tp
, tx_err
, tp
->netdev
,
1698 "Invalid transport offset 0x%x\n",
1704 switch (vlan_get_protocol(skb
)) {
1705 case htons(ETH_P_IP
):
1707 ip_protocol
= ip_hdr(skb
)->protocol
;
1710 case htons(ETH_P_IPV6
):
1712 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
1716 ip_protocol
= IPPROTO_RAW
;
1720 if (ip_protocol
== IPPROTO_TCP
)
1722 else if (ip_protocol
== IPPROTO_UDP
)
1727 opts2
|= transport_offset
<< TCPHO_SHIFT
;
1730 desc
->opts2
= cpu_to_le32(opts2
);
1731 desc
->opts1
= cpu_to_le32(opts1
);
1737 static int r8152_tx_agg_fill(struct r8152
*tp
, struct tx_agg
*agg
)
1739 struct sk_buff_head skb_head
, *tx_queue
= &tp
->tx_queue
;
1743 __skb_queue_head_init(&skb_head
);
1744 spin_lock(&tx_queue
->lock
);
1745 skb_queue_splice_init(tx_queue
, &skb_head
);
1746 spin_unlock(&tx_queue
->lock
);
1748 tx_data
= agg
->head
;
1751 remain
= agg_buf_sz
;
1753 while (remain
>= ETH_ZLEN
+ sizeof(struct tx_desc
)) {
1754 struct tx_desc
*tx_desc
;
1755 struct sk_buff
*skb
;
1759 skb
= __skb_dequeue(&skb_head
);
1763 len
= skb
->len
+ sizeof(*tx_desc
);
1766 __skb_queue_head(&skb_head
, skb
);
1770 tx_data
= tx_agg_align(tx_data
);
1771 tx_desc
= (struct tx_desc
*)tx_data
;
1773 offset
= (u32
)skb_transport_offset(skb
);
1775 if (r8152_tx_csum(tp
, tx_desc
, skb
, skb
->len
, offset
)) {
1776 r8152_csum_workaround(tp
, skb
, &skb_head
);
1780 rtl_tx_vlan_tag(tx_desc
, skb
);
1782 tx_data
+= sizeof(*tx_desc
);
1785 if (skb_copy_bits(skb
, 0, tx_data
, len
) < 0) {
1786 struct net_device_stats
*stats
= &tp
->netdev
->stats
;
1788 stats
->tx_dropped
++;
1789 dev_kfree_skb_any(skb
);
1790 tx_data
-= sizeof(*tx_desc
);
1795 agg
->skb_len
+= len
;
1798 dev_kfree_skb_any(skb
);
1800 remain
= agg_buf_sz
- (int)(tx_agg_align(tx_data
) - agg
->head
);
1803 if (!skb_queue_empty(&skb_head
)) {
1804 spin_lock(&tx_queue
->lock
);
1805 skb_queue_splice(&skb_head
, tx_queue
);
1806 spin_unlock(&tx_queue
->lock
);
1809 netif_tx_lock(tp
->netdev
);
1811 if (netif_queue_stopped(tp
->netdev
) &&
1812 skb_queue_len(&tp
->tx_queue
) < tp
->tx_qlen
)
1813 netif_wake_queue(tp
->netdev
);
1815 netif_tx_unlock(tp
->netdev
);
1817 ret
= usb_autopm_get_interface_async(tp
->intf
);
1821 usb_fill_bulk_urb(agg
->urb
, tp
->udev
, usb_sndbulkpipe(tp
->udev
, 2),
1822 agg
->head
, (int)(tx_data
- (u8
*)agg
->head
),
1823 (usb_complete_t
)write_bulk_callback
, agg
);
1825 ret
= usb_submit_urb(agg
->urb
, GFP_ATOMIC
);
1827 usb_autopm_put_interface_async(tp
->intf
);
1833 static u8
r8152_rx_csum(struct r8152
*tp
, struct rx_desc
*rx_desc
)
1835 u8 checksum
= CHECKSUM_NONE
;
1838 if (!(tp
->netdev
->features
& NETIF_F_RXCSUM
))
1841 opts2
= le32_to_cpu(rx_desc
->opts2
);
1842 opts3
= le32_to_cpu(rx_desc
->opts3
);
1844 if (opts2
& RD_IPV4_CS
) {
1846 checksum
= CHECKSUM_NONE
;
1847 else if ((opts2
& RD_UDP_CS
) && (opts3
& UDPF
))
1848 checksum
= CHECKSUM_NONE
;
1849 else if ((opts2
& RD_TCP_CS
) && (opts3
& TCPF
))
1850 checksum
= CHECKSUM_NONE
;
1852 checksum
= CHECKSUM_UNNECESSARY
;
1853 } else if (opts2
& RD_IPV6_CS
) {
1854 if ((opts2
& RD_UDP_CS
) && !(opts3
& UDPF
))
1855 checksum
= CHECKSUM_UNNECESSARY
;
1856 else if ((opts2
& RD_TCP_CS
) && !(opts3
& TCPF
))
1857 checksum
= CHECKSUM_UNNECESSARY
;
1864 static int rx_bottom(struct r8152
*tp
, int budget
)
1866 unsigned long flags
;
1867 struct list_head
*cursor
, *next
, rx_queue
;
1868 int ret
= 0, work_done
= 0;
1869 struct napi_struct
*napi
= &tp
->napi
;
1871 if (!skb_queue_empty(&tp
->rx_queue
)) {
1872 while (work_done
< budget
) {
1873 struct sk_buff
*skb
= __skb_dequeue(&tp
->rx_queue
);
1874 struct net_device
*netdev
= tp
->netdev
;
1875 struct net_device_stats
*stats
= &netdev
->stats
;
1876 unsigned int pkt_len
;
1882 napi_gro_receive(napi
, skb
);
1884 stats
->rx_packets
++;
1885 stats
->rx_bytes
+= pkt_len
;
1889 if (list_empty(&tp
->rx_done
))
1892 INIT_LIST_HEAD(&rx_queue
);
1893 spin_lock_irqsave(&tp
->rx_lock
, flags
);
1894 list_splice_init(&tp
->rx_done
, &rx_queue
);
1895 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
1897 list_for_each_safe(cursor
, next
, &rx_queue
) {
1898 struct rx_desc
*rx_desc
;
1904 list_del_init(cursor
);
1906 agg
= list_entry(cursor
, struct rx_agg
, list
);
1908 if (urb
->actual_length
< ETH_ZLEN
)
1911 rx_desc
= agg
->head
;
1912 rx_data
= agg
->head
;
1913 len_used
+= sizeof(struct rx_desc
);
1915 while (urb
->actual_length
> len_used
) {
1916 struct net_device
*netdev
= tp
->netdev
;
1917 struct net_device_stats
*stats
= &netdev
->stats
;
1918 unsigned int pkt_len
;
1919 struct sk_buff
*skb
;
1921 /* limite the skb numbers for rx_queue */
1922 if (unlikely(skb_queue_len(&tp
->rx_queue
) >= 1000))
1925 pkt_len
= le32_to_cpu(rx_desc
->opts1
) & RX_LEN_MASK
;
1926 if (pkt_len
< ETH_ZLEN
)
1929 len_used
+= pkt_len
;
1930 if (urb
->actual_length
< len_used
)
1933 pkt_len
-= ETH_FCS_LEN
;
1934 rx_data
+= sizeof(struct rx_desc
);
1936 skb
= napi_alloc_skb(napi
, pkt_len
);
1938 stats
->rx_dropped
++;
1942 skb
->ip_summed
= r8152_rx_csum(tp
, rx_desc
);
1943 memcpy(skb
->data
, rx_data
, pkt_len
);
1944 skb_put(skb
, pkt_len
);
1945 skb
->protocol
= eth_type_trans(skb
, netdev
);
1946 rtl_rx_vlan_tag(rx_desc
, skb
);
1947 if (work_done
< budget
) {
1948 napi_gro_receive(napi
, skb
);
1950 stats
->rx_packets
++;
1951 stats
->rx_bytes
+= pkt_len
;
1953 __skb_queue_tail(&tp
->rx_queue
, skb
);
1957 rx_data
= rx_agg_align(rx_data
+ pkt_len
+ ETH_FCS_LEN
);
1958 rx_desc
= (struct rx_desc
*)rx_data
;
1959 len_used
= (int)(rx_data
- (u8
*)agg
->head
);
1960 len_used
+= sizeof(struct rx_desc
);
1965 ret
= r8152_submit_rx(tp
, agg
, GFP_ATOMIC
);
1967 urb
->actual_length
= 0;
1968 list_add_tail(&agg
->list
, next
);
1972 if (!list_empty(&rx_queue
)) {
1973 spin_lock_irqsave(&tp
->rx_lock
, flags
);
1974 list_splice_tail(&rx_queue
, &tp
->rx_done
);
1975 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
1982 static void tx_bottom(struct r8152
*tp
)
1989 if (skb_queue_empty(&tp
->tx_queue
))
1992 agg
= r8152_get_tx_agg(tp
);
1996 res
= r8152_tx_agg_fill(tp
, agg
);
1998 struct net_device
*netdev
= tp
->netdev
;
2000 if (res
== -ENODEV
) {
2001 set_bit(RTL8152_UNPLUG
, &tp
->flags
);
2002 netif_device_detach(netdev
);
2004 struct net_device_stats
*stats
= &netdev
->stats
;
2005 unsigned long flags
;
2007 netif_warn(tp
, tx_err
, netdev
,
2008 "failed tx_urb %d\n", res
);
2009 stats
->tx_dropped
+= agg
->skb_num
;
2011 spin_lock_irqsave(&tp
->tx_lock
, flags
);
2012 list_add_tail(&agg
->list
, &tp
->tx_free
);
2013 spin_unlock_irqrestore(&tp
->tx_lock
, flags
);
2019 static void bottom_half(struct r8152
*tp
)
2021 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
2024 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
2027 /* When link down, the driver would cancel all bulks. */
2028 /* This avoid the re-submitting bulk */
2029 if (!netif_carrier_ok(tp
->netdev
))
2032 clear_bit(SCHEDULE_NAPI
, &tp
->flags
);
2037 static int r8152_poll(struct napi_struct
*napi
, int budget
)
2039 struct r8152
*tp
= container_of(napi
, struct r8152
, napi
);
2042 work_done
= rx_bottom(tp
, budget
);
2045 if (work_done
< budget
) {
2046 if (!napi_complete_done(napi
, work_done
))
2048 if (!list_empty(&tp
->rx_done
))
2049 napi_schedule(napi
);
2050 else if (!skb_queue_empty(&tp
->tx_queue
) &&
2051 !list_empty(&tp
->tx_free
))
2052 napi_schedule(napi
);
2060 int r8152_submit_rx(struct r8152
*tp
, struct rx_agg
*agg
, gfp_t mem_flags
)
2064 /* The rx would be stopped, so skip submitting */
2065 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
) ||
2066 !test_bit(WORK_ENABLE
, &tp
->flags
) || !netif_carrier_ok(tp
->netdev
))
2069 usb_fill_bulk_urb(agg
->urb
, tp
->udev
, usb_rcvbulkpipe(tp
->udev
, 1),
2070 agg
->head
, agg_buf_sz
,
2071 (usb_complete_t
)read_bulk_callback
, agg
);
2073 ret
= usb_submit_urb(agg
->urb
, mem_flags
);
2074 if (ret
== -ENODEV
) {
2075 set_bit(RTL8152_UNPLUG
, &tp
->flags
);
2076 netif_device_detach(tp
->netdev
);
2078 struct urb
*urb
= agg
->urb
;
2079 unsigned long flags
;
2081 urb
->actual_length
= 0;
2082 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2083 list_add_tail(&agg
->list
, &tp
->rx_done
);
2084 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2086 netif_err(tp
, rx_err
, tp
->netdev
,
2087 "Couldn't submit rx[%p], ret = %d\n", agg
, ret
);
2089 napi_schedule(&tp
->napi
);
2095 static void rtl_drop_queued_tx(struct r8152
*tp
)
2097 struct net_device_stats
*stats
= &tp
->netdev
->stats
;
2098 struct sk_buff_head skb_head
, *tx_queue
= &tp
->tx_queue
;
2099 struct sk_buff
*skb
;
2101 if (skb_queue_empty(tx_queue
))
2104 __skb_queue_head_init(&skb_head
);
2105 spin_lock_bh(&tx_queue
->lock
);
2106 skb_queue_splice_init(tx_queue
, &skb_head
);
2107 spin_unlock_bh(&tx_queue
->lock
);
2109 while ((skb
= __skb_dequeue(&skb_head
))) {
2111 stats
->tx_dropped
++;
2115 static void rtl8152_tx_timeout(struct net_device
*netdev
)
2117 struct r8152
*tp
= netdev_priv(netdev
);
2119 netif_warn(tp
, tx_err
, netdev
, "Tx timeout\n");
2121 usb_queue_reset_device(tp
->intf
);
2124 static void rtl8152_set_rx_mode(struct net_device
*netdev
)
2126 struct r8152
*tp
= netdev_priv(netdev
);
2128 if (netif_carrier_ok(netdev
)) {
2129 set_bit(RTL8152_SET_RX_MODE
, &tp
->flags
);
2130 schedule_delayed_work(&tp
->schedule
, 0);
2134 static void _rtl8152_set_rx_mode(struct net_device
*netdev
)
2136 struct r8152
*tp
= netdev_priv(netdev
);
2137 u32 mc_filter
[2]; /* Multicast hash filter */
2141 netif_stop_queue(netdev
);
2142 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
2143 ocp_data
&= ~RCR_ACPT_ALL
;
2144 ocp_data
|= RCR_AB
| RCR_APM
;
2146 if (netdev
->flags
& IFF_PROMISC
) {
2147 /* Unconditionally log net taps. */
2148 netif_notice(tp
, link
, netdev
, "Promiscuous mode enabled\n");
2149 ocp_data
|= RCR_AM
| RCR_AAP
;
2150 mc_filter
[1] = 0xffffffff;
2151 mc_filter
[0] = 0xffffffff;
2152 } else if ((netdev_mc_count(netdev
) > multicast_filter_limit
) ||
2153 (netdev
->flags
& IFF_ALLMULTI
)) {
2154 /* Too many to filter perfectly -- accept all multicasts. */
2156 mc_filter
[1] = 0xffffffff;
2157 mc_filter
[0] = 0xffffffff;
2159 struct netdev_hw_addr
*ha
;
2163 netdev_for_each_mc_addr(ha
, netdev
) {
2164 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
2166 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
2171 tmp
[0] = __cpu_to_le32(swab32(mc_filter
[1]));
2172 tmp
[1] = __cpu_to_le32(swab32(mc_filter
[0]));
2174 pla_ocp_write(tp
, PLA_MAR
, BYTE_EN_DWORD
, sizeof(tmp
), tmp
);
2175 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
2176 netif_wake_queue(netdev
);
2179 static netdev_features_t
2180 rtl8152_features_check(struct sk_buff
*skb
, struct net_device
*dev
,
2181 netdev_features_t features
)
2183 u32 mss
= skb_shinfo(skb
)->gso_size
;
2184 int max_offset
= mss
? GTTCPHO_MAX
: TCPHO_MAX
;
2185 int offset
= skb_transport_offset(skb
);
2187 if ((mss
|| skb
->ip_summed
== CHECKSUM_PARTIAL
) && offset
> max_offset
)
2188 features
&= ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
2189 else if ((skb
->len
+ sizeof(struct tx_desc
)) > agg_buf_sz
)
2190 features
&= ~NETIF_F_GSO_MASK
;
2195 static netdev_tx_t
rtl8152_start_xmit(struct sk_buff
*skb
,
2196 struct net_device
*netdev
)
2198 struct r8152
*tp
= netdev_priv(netdev
);
2200 skb_tx_timestamp(skb
);
2202 skb_queue_tail(&tp
->tx_queue
, skb
);
2204 if (!list_empty(&tp
->tx_free
)) {
2205 if (test_bit(SELECTIVE_SUSPEND
, &tp
->flags
)) {
2206 set_bit(SCHEDULE_NAPI
, &tp
->flags
);
2207 schedule_delayed_work(&tp
->schedule
, 0);
2209 usb_mark_last_busy(tp
->udev
);
2210 napi_schedule(&tp
->napi
);
2212 } else if (skb_queue_len(&tp
->tx_queue
) > tp
->tx_qlen
) {
2213 netif_stop_queue(netdev
);
2216 return NETDEV_TX_OK
;
2219 static void r8152b_reset_packet_filter(struct r8152
*tp
)
2223 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_FMC
);
2224 ocp_data
&= ~FMC_FCR_MCU_EN
;
2225 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_FMC
, ocp_data
);
2226 ocp_data
|= FMC_FCR_MCU_EN
;
2227 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_FMC
, ocp_data
);
2230 static void rtl8152_nic_reset(struct r8152
*tp
)
2234 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CR
, CR_RST
);
2236 for (i
= 0; i
< 1000; i
++) {
2237 if (!(ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CR
) & CR_RST
))
2239 usleep_range(100, 400);
2243 static void set_tx_qlen(struct r8152
*tp
)
2245 struct net_device
*netdev
= tp
->netdev
;
2247 tp
->tx_qlen
= agg_buf_sz
/ (netdev
->mtu
+ VLAN_ETH_HLEN
+ ETH_FCS_LEN
+
2248 sizeof(struct tx_desc
));
2251 static inline u8
rtl8152_get_speed(struct r8152
*tp
)
2253 return ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_PHYSTATUS
);
2256 static void rtl_set_eee_plus(struct r8152
*tp
)
2261 speed
= rtl8152_get_speed(tp
);
2262 if (speed
& _10bps
) {
2263 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEEP_CR
);
2264 ocp_data
|= EEEP_CR_EEEP_TX
;
2265 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEEP_CR
, ocp_data
);
2267 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEEP_CR
);
2268 ocp_data
&= ~EEEP_CR_EEEP_TX
;
2269 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEEP_CR
, ocp_data
);
2273 static void rxdy_gated_en(struct r8152
*tp
, bool enable
)
2277 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MISC_1
);
2279 ocp_data
|= RXDY_GATED_EN
;
2281 ocp_data
&= ~RXDY_GATED_EN
;
2282 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MISC_1
, ocp_data
);
2285 static int rtl_start_rx(struct r8152
*tp
)
2289 INIT_LIST_HEAD(&tp
->rx_done
);
2290 for (i
= 0; i
< RTL8152_MAX_RX
; i
++) {
2291 INIT_LIST_HEAD(&tp
->rx_info
[i
].list
);
2292 ret
= r8152_submit_rx(tp
, &tp
->rx_info
[i
], GFP_KERNEL
);
2297 if (ret
&& ++i
< RTL8152_MAX_RX
) {
2298 struct list_head rx_queue
;
2299 unsigned long flags
;
2301 INIT_LIST_HEAD(&rx_queue
);
2304 struct rx_agg
*agg
= &tp
->rx_info
[i
++];
2305 struct urb
*urb
= agg
->urb
;
2307 urb
->actual_length
= 0;
2308 list_add_tail(&agg
->list
, &rx_queue
);
2309 } while (i
< RTL8152_MAX_RX
);
2311 spin_lock_irqsave(&tp
->rx_lock
, flags
);
2312 list_splice_tail(&rx_queue
, &tp
->rx_done
);
2313 spin_unlock_irqrestore(&tp
->rx_lock
, flags
);
2319 static int rtl_stop_rx(struct r8152
*tp
)
2323 for (i
= 0; i
< RTL8152_MAX_RX
; i
++)
2324 usb_kill_urb(tp
->rx_info
[i
].urb
);
2326 while (!skb_queue_empty(&tp
->rx_queue
))
2327 dev_kfree_skb(__skb_dequeue(&tp
->rx_queue
));
2332 static int rtl_enable(struct r8152
*tp
)
2336 r8152b_reset_packet_filter(tp
);
2338 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_CR
);
2339 ocp_data
|= CR_RE
| CR_TE
;
2340 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CR
, ocp_data
);
2342 rxdy_gated_en(tp
, false);
2347 static int rtl8152_enable(struct r8152
*tp
)
2349 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
2353 rtl_set_eee_plus(tp
);
2355 return rtl_enable(tp
);
2358 static inline void r8153b_rx_agg_chg_indicate(struct r8152
*tp
)
2360 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_UPT_RXDMA_OWN
,
2361 OWN_UPDATE
| OWN_CLEAR
);
2364 static void r8153_set_rx_early_timeout(struct r8152
*tp
)
2366 u32 ocp_data
= tp
->coalesce
/ 8;
2368 switch (tp
->version
) {
2373 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_TIMEOUT
,
2379 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2380 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2382 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_TIMEOUT
,
2384 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EXTRA_AGGR_TMR
,
2386 r8153b_rx_agg_chg_indicate(tp
);
2394 static void r8153_set_rx_early_size(struct r8152
*tp
)
2396 u32 ocp_data
= agg_buf_sz
- rx_reserved_size(tp
->netdev
->mtu
);
2398 switch (tp
->version
) {
2403 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_SIZE
,
2408 ocp_write_word(tp
, MCU_TYPE_USB
, USB_RX_EARLY_SIZE
,
2410 r8153b_rx_agg_chg_indicate(tp
);
2418 static int rtl8153_enable(struct r8152
*tp
)
2420 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
2424 rtl_set_eee_plus(tp
);
2425 r8153_set_rx_early_timeout(tp
);
2426 r8153_set_rx_early_size(tp
);
2428 return rtl_enable(tp
);
2431 static void rtl_disable(struct r8152
*tp
)
2436 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
2437 rtl_drop_queued_tx(tp
);
2441 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
2442 ocp_data
&= ~RCR_ACPT_ALL
;
2443 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
2445 rtl_drop_queued_tx(tp
);
2447 for (i
= 0; i
< RTL8152_MAX_TX
; i
++)
2448 usb_kill_urb(tp
->tx_info
[i
].urb
);
2450 rxdy_gated_en(tp
, true);
2452 for (i
= 0; i
< 1000; i
++) {
2453 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
2454 if ((ocp_data
& FIFO_EMPTY
) == FIFO_EMPTY
)
2456 usleep_range(1000, 2000);
2459 for (i
= 0; i
< 1000; i
++) {
2460 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
) & TCR0_TX_EMPTY
)
2462 usleep_range(1000, 2000);
2467 rtl8152_nic_reset(tp
);
2470 static void r8152_power_cut_en(struct r8152
*tp
, bool enable
)
2474 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_UPS_CTRL
);
2476 ocp_data
|= POWER_CUT
;
2478 ocp_data
&= ~POWER_CUT
;
2479 ocp_write_word(tp
, MCU_TYPE_USB
, USB_UPS_CTRL
, ocp_data
);
2481 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_PM_CTRL_STATUS
);
2482 ocp_data
&= ~RESUME_INDICATE
;
2483 ocp_write_word(tp
, MCU_TYPE_USB
, USB_PM_CTRL_STATUS
, ocp_data
);
2486 static void rtl_rx_vlan_en(struct r8152
*tp
, bool enable
)
2490 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CPCR
);
2492 ocp_data
|= CPCR_RX_VLAN
;
2494 ocp_data
&= ~CPCR_RX_VLAN
;
2495 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CPCR
, ocp_data
);
2498 static int rtl8152_set_features(struct net_device
*dev
,
2499 netdev_features_t features
)
2501 netdev_features_t changed
= features
^ dev
->features
;
2502 struct r8152
*tp
= netdev_priv(dev
);
2505 ret
= usb_autopm_get_interface(tp
->intf
);
2509 mutex_lock(&tp
->control
);
2511 if (changed
& NETIF_F_HW_VLAN_CTAG_RX
) {
2512 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
2513 rtl_rx_vlan_en(tp
, true);
2515 rtl_rx_vlan_en(tp
, false);
2518 mutex_unlock(&tp
->control
);
2520 usb_autopm_put_interface(tp
->intf
);
2526 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2528 static u32
__rtl_get_wol(struct r8152
*tp
)
2533 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
2534 if (ocp_data
& LINK_ON_WAKE_EN
)
2535 wolopts
|= WAKE_PHY
;
2537 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG5
);
2538 if (ocp_data
& UWF_EN
)
2539 wolopts
|= WAKE_UCAST
;
2540 if (ocp_data
& BWF_EN
)
2541 wolopts
|= WAKE_BCAST
;
2542 if (ocp_data
& MWF_EN
)
2543 wolopts
|= WAKE_MCAST
;
2545 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CFG_WOL
);
2546 if (ocp_data
& MAGIC_EN
)
2547 wolopts
|= WAKE_MAGIC
;
2552 static void __rtl_set_wol(struct r8152
*tp
, u32 wolopts
)
2556 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
2558 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
2559 ocp_data
&= ~LINK_ON_WAKE_EN
;
2560 if (wolopts
& WAKE_PHY
)
2561 ocp_data
|= LINK_ON_WAKE_EN
;
2562 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
, ocp_data
);
2564 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG5
);
2565 ocp_data
&= ~(UWF_EN
| BWF_EN
| MWF_EN
);
2566 if (wolopts
& WAKE_UCAST
)
2568 if (wolopts
& WAKE_BCAST
)
2570 if (wolopts
& WAKE_MCAST
)
2572 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG5
, ocp_data
);
2574 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
2576 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CFG_WOL
);
2577 ocp_data
&= ~MAGIC_EN
;
2578 if (wolopts
& WAKE_MAGIC
)
2579 ocp_data
|= MAGIC_EN
;
2580 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CFG_WOL
, ocp_data
);
2582 if (wolopts
& WAKE_ANY
)
2583 device_set_wakeup_enable(&tp
->udev
->dev
, true);
2585 device_set_wakeup_enable(&tp
->udev
->dev
, false);
2588 static void r8153_mac_clk_spd(struct r8152
*tp
, bool enable
)
2590 /* MAC clock speed down */
2592 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL
,
2594 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
,
2596 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
,
2597 PKT_AVAIL_SPDWN_EN
| SUSPEND_SPDWN_EN
|
2598 U1U2_SPDWN_EN
| L1_SPDWN_EN
);
2599 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
,
2600 PWRSAVE_SPDWN_EN
| RXDV_SPDWN_EN
| TX10MIDLE_EN
|
2601 TP100_SPDWN_EN
| TP500_SPDWN_EN
| EEE_SPDWN_EN
|
2604 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL
, 0);
2605 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
, 0);
2606 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL3
, 0);
2607 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL4
, 0);
2611 static void r8153_u1u2en(struct r8152
*tp
, bool enable
)
2616 memset(u1u2
, 0xff, sizeof(u1u2
));
2618 memset(u1u2
, 0x00, sizeof(u1u2
));
2620 usb_ocp_write(tp
, USB_TOLERANCE
, BYTE_EN_SIX_BYTES
, sizeof(u1u2
), u1u2
);
2623 static void r8153b_u1u2en(struct r8152
*tp
, bool enable
)
2627 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_LPM_CONFIG
);
2629 ocp_data
|= LPM_U1U2_EN
;
2631 ocp_data
&= ~LPM_U1U2_EN
;
2633 ocp_write_word(tp
, MCU_TYPE_USB
, USB_LPM_CONFIG
, ocp_data
);
2636 static void r8153_u2p3en(struct r8152
*tp
, bool enable
)
2640 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_U2P3_CTRL
);
2642 ocp_data
|= U2P3_ENABLE
;
2644 ocp_data
&= ~U2P3_ENABLE
;
2645 ocp_write_word(tp
, MCU_TYPE_USB
, USB_U2P3_CTRL
, ocp_data
);
2648 static void r8153b_ups_flags_w1w0(struct r8152
*tp
, u32 set
, u32 clear
)
2652 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_USB
, USB_UPS_FLAGS
);
2655 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_UPS_FLAGS
, ocp_data
);
2658 static void r8153b_green_en(struct r8152
*tp
, bool enable
)
2663 sram_write(tp
, 0x8045, 0); /* 10M abiq&ldvbias */
2664 sram_write(tp
, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2665 sram_write(tp
, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2667 sram_write(tp
, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2668 sram_write(tp
, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2669 sram_write(tp
, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2672 data
= sram_read(tp
, SRAM_GREEN_CFG
);
2673 data
|= GREEN_ETH_EN
;
2674 sram_write(tp
, SRAM_GREEN_CFG
, data
);
2676 r8153b_ups_flags_w1w0(tp
, UPS_FLAGS_EN_GREEN
, 0);
2679 static u16
r8153_phy_status(struct r8152
*tp
, u16 desired
)
2684 for (i
= 0; i
< 500; i
++) {
2685 data
= ocp_reg_read(tp
, OCP_PHY_STATUS
);
2686 data
&= PHY_STAT_MASK
;
2688 if (data
== desired
)
2690 } else if (data
== PHY_STAT_LAN_ON
|| data
== PHY_STAT_PWRDN
||
2691 data
== PHY_STAT_EXT_INIT
) {
2701 static void r8153b_ups_en(struct r8152
*tp
, bool enable
)
2703 u32 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
);
2706 ocp_data
|= UPS_EN
| USP_PREWAKE
| PHASE2_EN
;
2707 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
2709 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, 0xcfff);
2711 ocp_write_byte(tp
, MCU_TYPE_USB
, 0xcfff, ocp_data
);
2715 ocp_data
&= ~(UPS_EN
| USP_PREWAKE
);
2716 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
2718 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, 0xcfff);
2719 ocp_data
&= ~BIT(0);
2720 ocp_write_byte(tp
, MCU_TYPE_USB
, 0xcfff, ocp_data
);
2722 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
2723 ocp_data
&= ~PCUT_STATUS
;
2724 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MISC_0
, ocp_data
);
2726 data
= r8153_phy_status(tp
, 0);
2729 case PHY_STAT_PWRDN
:
2730 case PHY_STAT_EXT_INIT
:
2732 test_bit(GREEN_ETHERNET
, &tp
->flags
));
2734 data
= r8152_mdio_read(tp
, MII_BMCR
);
2735 data
&= ~BMCR_PDOWN
;
2737 r8152_mdio_write(tp
, MII_BMCR
, data
);
2739 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
2742 if (data
!= PHY_STAT_LAN_ON
)
2743 netif_warn(tp
, link
, tp
->netdev
,
2750 static void r8153_power_cut_en(struct r8152
*tp
, bool enable
)
2754 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_POWER_CUT
);
2756 ocp_data
|= PWR_EN
| PHASE2_EN
;
2758 ocp_data
&= ~(PWR_EN
| PHASE2_EN
);
2759 ocp_write_word(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
2761 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
2762 ocp_data
&= ~PCUT_STATUS
;
2763 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MISC_0
, ocp_data
);
2766 static void r8153b_power_cut_en(struct r8152
*tp
, bool enable
)
2770 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_POWER_CUT
);
2772 ocp_data
|= PWR_EN
| PHASE2_EN
;
2774 ocp_data
&= ~PWR_EN
;
2775 ocp_write_word(tp
, MCU_TYPE_USB
, USB_POWER_CUT
, ocp_data
);
2777 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_MISC_0
);
2778 ocp_data
&= ~PCUT_STATUS
;
2779 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MISC_0
, ocp_data
);
2782 static void r8153b_queue_wake(struct r8152
*tp
, bool enable
)
2786 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, 0xd38a);
2790 ocp_data
&= ~BIT(0);
2791 ocp_write_byte(tp
, MCU_TYPE_PLA
, 0xd38a, ocp_data
);
2793 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, 0xd38c);
2794 ocp_data
&= ~BIT(0);
2795 ocp_write_byte(tp
, MCU_TYPE_PLA
, 0xd38c, ocp_data
);
2798 static bool rtl_can_wakeup(struct r8152
*tp
)
2800 struct usb_device
*udev
= tp
->udev
;
2802 return (udev
->actconfig
->desc
.bmAttributes
& USB_CONFIG_ATT_WAKEUP
);
2805 static void rtl_runtime_suspend_enable(struct r8152
*tp
, bool enable
)
2810 __rtl_set_wol(tp
, WAKE_ANY
);
2812 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
2814 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
2815 ocp_data
|= LINK_OFF_WAKE_EN
;
2816 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
, ocp_data
);
2818 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
2822 __rtl_set_wol(tp
, tp
->saved_wolopts
);
2824 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_CONFIG
);
2826 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
);
2827 ocp_data
&= ~LINK_OFF_WAKE_EN
;
2828 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_CONFIG34
, ocp_data
);
2830 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
2834 static void rtl8153_runtime_enable(struct r8152
*tp
, bool enable
)
2837 r8153_u1u2en(tp
, false);
2838 r8153_u2p3en(tp
, false);
2839 r8153_mac_clk_spd(tp
, true);
2840 rtl_runtime_suspend_enable(tp
, true);
2842 rtl_runtime_suspend_enable(tp
, false);
2843 r8153_mac_clk_spd(tp
, false);
2845 switch (tp
->version
) {
2852 r8153_u2p3en(tp
, true);
2856 r8153_u1u2en(tp
, true);
2860 static void rtl8153b_runtime_enable(struct r8152
*tp
, bool enable
)
2863 r8153b_queue_wake(tp
, true);
2864 r8153b_u1u2en(tp
, false);
2865 r8153_u2p3en(tp
, false);
2866 rtl_runtime_suspend_enable(tp
, true);
2867 r8153b_ups_en(tp
, true);
2869 r8153b_ups_en(tp
, false);
2870 r8153b_queue_wake(tp
, false);
2871 rtl_runtime_suspend_enable(tp
, false);
2872 r8153_u2p3en(tp
, true);
2873 r8153b_u1u2en(tp
, true);
2877 static void r8153_teredo_off(struct r8152
*tp
)
2881 switch (tp
->version
) {
2889 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
);
2890 ocp_data
&= ~(TEREDO_SEL
| TEREDO_RS_EVENT_MASK
|
2892 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
, ocp_data
);
2897 /* The bit 0 ~ 7 are relative with teredo settings. They are
2898 * W1C (write 1 to clear), so set all 1 to disable it.
2900 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
, 0xff);
2907 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_WDT6_CTRL
, WDT6_SET_MODE
);
2908 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_REALWOW_TIMER
, 0);
2909 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_TEREDO_TIMER
, 0);
2912 static void rtl_reset_bmu(struct r8152
*tp
)
2916 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_BMU_RESET
);
2917 ocp_data
&= ~(BMU_RESET_EP_IN
| BMU_RESET_EP_OUT
);
2918 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_BMU_RESET
, ocp_data
);
2919 ocp_data
|= BMU_RESET_EP_IN
| BMU_RESET_EP_OUT
;
2920 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_BMU_RESET
, ocp_data
);
2923 static void r8152_aldps_en(struct r8152
*tp
, bool enable
)
2926 ocp_reg_write(tp
, OCP_ALDPS_CONFIG
, ENPWRSAVE
| ENPDNPS
|
2927 LINKENA
| DIS_SDSAVE
);
2929 ocp_reg_write(tp
, OCP_ALDPS_CONFIG
, ENPDNPS
| LINKENA
|
2935 static inline void r8152_mmd_indirect(struct r8152
*tp
, u16 dev
, u16 reg
)
2937 ocp_reg_write(tp
, OCP_EEE_AR
, FUN_ADDR
| dev
);
2938 ocp_reg_write(tp
, OCP_EEE_DATA
, reg
);
2939 ocp_reg_write(tp
, OCP_EEE_AR
, FUN_DATA
| dev
);
2942 static u16
r8152_mmd_read(struct r8152
*tp
, u16 dev
, u16 reg
)
2946 r8152_mmd_indirect(tp
, dev
, reg
);
2947 data
= ocp_reg_read(tp
, OCP_EEE_DATA
);
2948 ocp_reg_write(tp
, OCP_EEE_AR
, 0x0000);
2953 static void r8152_mmd_write(struct r8152
*tp
, u16 dev
, u16 reg
, u16 data
)
2955 r8152_mmd_indirect(tp
, dev
, reg
);
2956 ocp_reg_write(tp
, OCP_EEE_DATA
, data
);
2957 ocp_reg_write(tp
, OCP_EEE_AR
, 0x0000);
2960 static void r8152_eee_en(struct r8152
*tp
, bool enable
)
2962 u16 config1
, config2
, config3
;
2965 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
);
2966 config1
= ocp_reg_read(tp
, OCP_EEE_CONFIG1
) & ~sd_rise_time_mask
;
2967 config2
= ocp_reg_read(tp
, OCP_EEE_CONFIG2
);
2968 config3
= ocp_reg_read(tp
, OCP_EEE_CONFIG3
) & ~fast_snr_mask
;
2971 ocp_data
|= EEE_RX_EN
| EEE_TX_EN
;
2972 config1
|= EEE_10_CAP
| EEE_NWAY_EN
| TX_QUIET_EN
| RX_QUIET_EN
;
2973 config1
|= sd_rise_time(1);
2974 config2
|= RG_DACQUIET_EN
| RG_LDVQUIET_EN
;
2975 config3
|= fast_snr(42);
2977 ocp_data
&= ~(EEE_RX_EN
| EEE_TX_EN
);
2978 config1
&= ~(EEE_10_CAP
| EEE_NWAY_EN
| TX_QUIET_EN
|
2980 config1
|= sd_rise_time(7);
2981 config2
&= ~(RG_DACQUIET_EN
| RG_LDVQUIET_EN
);
2982 config3
|= fast_snr(511);
2985 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
, ocp_data
);
2986 ocp_reg_write(tp
, OCP_EEE_CONFIG1
, config1
);
2987 ocp_reg_write(tp
, OCP_EEE_CONFIG2
, config2
);
2988 ocp_reg_write(tp
, OCP_EEE_CONFIG3
, config3
);
2991 static void r8152b_enable_eee(struct r8152
*tp
)
2993 r8152_eee_en(tp
, true);
2994 r8152_mmd_write(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, MDIO_EEE_100TX
);
2997 static void r8152b_enable_fc(struct r8152
*tp
)
3001 anar
= r8152_mdio_read(tp
, MII_ADVERTISE
);
3002 anar
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
3003 r8152_mdio_write(tp
, MII_ADVERTISE
, anar
);
3006 static void rtl8152_disable(struct r8152
*tp
)
3008 r8152_aldps_en(tp
, false);
3010 r8152_aldps_en(tp
, true);
3013 static void r8152b_hw_phy_cfg(struct r8152
*tp
)
3015 r8152b_enable_eee(tp
);
3016 r8152_aldps_en(tp
, true);
3017 r8152b_enable_fc(tp
);
3019 set_bit(PHY_RESET
, &tp
->flags
);
3022 static void r8152b_exit_oob(struct r8152
*tp
)
3027 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
3028 ocp_data
&= ~RCR_ACPT_ALL
;
3029 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
3031 rxdy_gated_en(tp
, true);
3032 r8153_teredo_off(tp
);
3033 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CRWECR
, CRWECR_NORAML
);
3034 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_CR
, 0x00);
3036 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3037 ocp_data
&= ~NOW_IS_OOB
;
3038 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
3040 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
3041 ocp_data
&= ~MCU_BORW_EN
;
3042 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
3044 for (i
= 0; i
< 1000; i
++) {
3045 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3046 if (ocp_data
& LINK_LIST_READY
)
3048 usleep_range(1000, 2000);
3051 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
3052 ocp_data
|= RE_INIT_LL
;
3053 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
3055 for (i
= 0; i
< 1000; i
++) {
3056 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3057 if (ocp_data
& LINK_LIST_READY
)
3059 usleep_range(1000, 2000);
3062 rtl8152_nic_reset(tp
);
3064 /* rx share fifo credit full threshold */
3065 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL0
, RXFIFO_THR1_NORMAL
);
3067 if (tp
->udev
->speed
== USB_SPEED_FULL
||
3068 tp
->udev
->speed
== USB_SPEED_LOW
) {
3069 /* rx share fifo credit near full threshold */
3070 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
,
3072 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
,
3075 /* rx share fifo credit near full threshold */
3076 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
,
3078 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
,
3082 /* TX share fifo free credit full threshold */
3083 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_CTRL
, TXFIFO_THR_NORMAL
);
3085 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_TX_AGG
, TX_AGG_MAX_THRESHOLD
);
3086 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_RX_BUF_TH
, RX_THR_HIGH
);
3087 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_TX_DMA
,
3088 TEST_MODE_DISABLE
| TX_SIZE_ADJUST1
);
3090 rtl_rx_vlan_en(tp
, tp
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
);
3092 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, RTL8152_RMS
);
3094 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
);
3095 ocp_data
|= TCR0_AUTO_FIFO
;
3096 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
, ocp_data
);
3099 static void r8152b_enter_oob(struct r8152
*tp
)
3104 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3105 ocp_data
&= ~NOW_IS_OOB
;
3106 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
3108 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL0
, RXFIFO_THR1_OOB
);
3109 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
, RXFIFO_THR2_OOB
);
3110 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
, RXFIFO_THR3_OOB
);
3114 for (i
= 0; i
< 1000; i
++) {
3115 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3116 if (ocp_data
& LINK_LIST_READY
)
3118 usleep_range(1000, 2000);
3121 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
3122 ocp_data
|= RE_INIT_LL
;
3123 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
3125 for (i
= 0; i
< 1000; i
++) {
3126 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3127 if (ocp_data
& LINK_LIST_READY
)
3129 usleep_range(1000, 2000);
3132 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, RTL8152_RMS
);
3134 rtl_rx_vlan_en(tp
, true);
3136 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PAL_BDC_CR
);
3137 ocp_data
|= ALDPS_PROXY_MODE
;
3138 ocp_write_word(tp
, MCU_TYPE_PLA
, PAL_BDC_CR
, ocp_data
);
3140 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3141 ocp_data
|= NOW_IS_OOB
| DIS_MCU_CLROOB
;
3142 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
3144 rxdy_gated_en(tp
, false);
3146 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
3147 ocp_data
|= RCR_APM
| RCR_AM
| RCR_AB
;
3148 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
3151 static int r8153_patch_request(struct r8152
*tp
, bool request
)
3156 data
= ocp_reg_read(tp
, OCP_PHY_PATCH_CMD
);
3158 data
|= PATCH_REQUEST
;
3160 data
&= ~PATCH_REQUEST
;
3161 ocp_reg_write(tp
, OCP_PHY_PATCH_CMD
, data
);
3163 for (i
= 0; request
&& i
< 5000; i
++) {
3164 usleep_range(1000, 2000);
3165 if (ocp_reg_read(tp
, OCP_PHY_PATCH_STAT
) & PATCH_READY
)
3169 if (request
&& !(ocp_reg_read(tp
, OCP_PHY_PATCH_STAT
) & PATCH_READY
)) {
3170 netif_err(tp
, drv
, tp
->netdev
, "patch request fail\n");
3171 r8153_patch_request(tp
, false);
3178 static void r8153_aldps_en(struct r8152
*tp
, bool enable
)
3182 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
3185 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
3190 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
3191 for (i
= 0; i
< 20; i
++) {
3192 usleep_range(1000, 2000);
3193 if (ocp_read_word(tp
, MCU_TYPE_PLA
, 0xe000) & 0x0100)
3199 static void r8153b_aldps_en(struct r8152
*tp
, bool enable
)
3201 r8153_aldps_en(tp
, enable
);
3204 r8153b_ups_flags_w1w0(tp
, UPS_FLAGS_EN_ALDPS
, 0);
3206 r8153b_ups_flags_w1w0(tp
, 0, UPS_FLAGS_EN_ALDPS
);
3209 static void r8153_eee_en(struct r8152
*tp
, bool enable
)
3214 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
);
3215 config
= ocp_reg_read(tp
, OCP_EEE_CFG
);
3218 ocp_data
|= EEE_RX_EN
| EEE_TX_EN
;
3221 ocp_data
&= ~(EEE_RX_EN
| EEE_TX_EN
);
3222 config
&= ~EEE10_EN
;
3225 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
, ocp_data
);
3226 ocp_reg_write(tp
, OCP_EEE_CFG
, config
);
3229 static void r8153b_eee_en(struct r8152
*tp
, bool enable
)
3231 r8153_eee_en(tp
, enable
);
3234 r8153b_ups_flags_w1w0(tp
, UPS_FLAGS_EN_EEE
, 0);
3236 r8153b_ups_flags_w1w0(tp
, 0, UPS_FLAGS_EN_EEE
);
3239 static void r8153b_enable_fc(struct r8152
*tp
)
3241 r8152b_enable_fc(tp
);
3242 r8153b_ups_flags_w1w0(tp
, UPS_FLAGS_EN_FLOW_CTR
, 0);
3245 static void r8153_hw_phy_cfg(struct r8152
*tp
)
3250 /* disable ALDPS before updating the PHY parameters */
3251 r8153_aldps_en(tp
, false);
3253 /* disable EEE before updating the PHY parameters */
3254 r8153_eee_en(tp
, false);
3255 ocp_reg_write(tp
, OCP_EEE_ADV
, 0);
3257 if (tp
->version
== RTL_VER_03
) {
3258 data
= ocp_reg_read(tp
, OCP_EEE_CFG
);
3259 data
&= ~CTAP_SHORT_EN
;
3260 ocp_reg_write(tp
, OCP_EEE_CFG
, data
);
3263 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
3264 data
|= EEE_CLKDIV_EN
;
3265 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
3267 data
= ocp_reg_read(tp
, OCP_DOWN_SPEED
);
3268 data
|= EN_10M_BGOFF
;
3269 ocp_reg_write(tp
, OCP_DOWN_SPEED
, data
);
3270 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
3271 data
|= EN_10M_PLLOFF
;
3272 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
3273 sram_write(tp
, SRAM_IMPEDANCE
, 0x0b13);
3275 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
3276 ocp_data
|= PFM_PWM_SWITCH
;
3277 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
3279 /* Enable LPF corner auto tune */
3280 sram_write(tp
, SRAM_LPF_CFG
, 0xf70f);
3282 /* Adjust 10M Amplitude */
3283 sram_write(tp
, SRAM_10M_AMP1
, 0x00af);
3284 sram_write(tp
, SRAM_10M_AMP2
, 0x0208);
3286 r8153_eee_en(tp
, true);
3287 ocp_reg_write(tp
, OCP_EEE_ADV
, MDIO_EEE_1000T
| MDIO_EEE_100TX
);
3289 r8153_aldps_en(tp
, true);
3290 r8152b_enable_fc(tp
);
3292 switch (tp
->version
) {
3299 r8153_u2p3en(tp
, true);
3303 set_bit(PHY_RESET
, &tp
->flags
);
3306 static u32
r8152_efuse_read(struct r8152
*tp
, u8 addr
)
3310 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_EFUSE_CMD
, EFUSE_READ_CMD
| addr
);
3311 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EFUSE_CMD
);
3312 ocp_data
= (ocp_data
& EFUSE_DATA_BIT16
) << 9; /* data of bit16 */
3313 ocp_data
|= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EFUSE_DATA
);
3318 static void r8153b_hw_phy_cfg(struct r8152
*tp
)
3320 u32 ocp_data
, ups_flags
= 0;
3323 /* disable ALDPS before updating the PHY parameters */
3324 r8153b_aldps_en(tp
, false);
3326 /* disable EEE before updating the PHY parameters */
3327 r8153b_eee_en(tp
, false);
3328 ocp_reg_write(tp
, OCP_EEE_ADV
, 0);
3330 r8153b_green_en(tp
, test_bit(GREEN_ETHERNET
, &tp
->flags
));
3332 data
= sram_read(tp
, SRAM_GREEN_CFG
);
3334 sram_write(tp
, SRAM_GREEN_CFG
, data
);
3335 data
= ocp_reg_read(tp
, OCP_NCTL_CFG
);
3336 data
|= PGA_RETURN_EN
;
3337 ocp_reg_write(tp
, OCP_NCTL_CFG
, data
);
3339 /* ADC Bias Calibration:
3340 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3341 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3344 ocp_data
= r8152_efuse_read(tp
, 0x7d);
3345 data
= (u16
)(((ocp_data
& 0x1fff0) >> 1) | (ocp_data
& 0x7));
3347 ocp_reg_write(tp
, OCP_ADC_IOFFSET
, data
);
3349 /* ups mode tx-link-pulse timing adjustment:
3350 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3351 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3353 ocp_data
= ocp_reg_read(tp
, 0xc426);
3356 u32 swr_cnt_1ms_ini
;
3358 swr_cnt_1ms_ini
= (16000000 / ocp_data
) & SAW_CNT_1MS_MASK
;
3359 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_UPS_CFG
);
3360 ocp_data
= (ocp_data
& ~SAW_CNT_1MS_MASK
) | swr_cnt_1ms_ini
;
3361 ocp_write_word(tp
, MCU_TYPE_USB
, USB_UPS_CFG
, ocp_data
);
3364 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
3365 ocp_data
|= PFM_PWM_SWITCH
;
3366 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
3369 if (!r8153_patch_request(tp
, true)) {
3370 data
= ocp_reg_read(tp
, OCP_POWER_CFG
);
3371 data
|= EEE_CLKDIV_EN
;
3372 ocp_reg_write(tp
, OCP_POWER_CFG
, data
);
3374 data
= ocp_reg_read(tp
, OCP_DOWN_SPEED
);
3375 data
|= EN_EEE_CMODE
| EN_EEE_1000
| EN_10M_CLKDIV
;
3376 ocp_reg_write(tp
, OCP_DOWN_SPEED
, data
);
3378 ocp_reg_write(tp
, OCP_SYSCLK_CFG
, 0);
3379 ocp_reg_write(tp
, OCP_SYSCLK_CFG
, clk_div_expo(5));
3381 ups_flags
|= UPS_FLAGS_EN_10M_CKDIV
| UPS_FLAGS_250M_CKDIV
|
3382 UPS_FLAGS_EN_EEE_CKDIV
| UPS_FLAGS_EEE_CMOD_LV_EN
|
3383 UPS_FLAGS_EEE_PLLOFF_GIGA
;
3385 r8153_patch_request(tp
, false);
3388 r8153b_ups_flags_w1w0(tp
, ups_flags
, 0);
3390 r8153b_eee_en(tp
, true);
3391 ocp_reg_write(tp
, OCP_EEE_ADV
, MDIO_EEE_1000T
| MDIO_EEE_100TX
);
3393 r8153b_aldps_en(tp
, true);
3394 r8153b_enable_fc(tp
);
3395 r8153_u2p3en(tp
, true);
3397 set_bit(PHY_RESET
, &tp
->flags
);
3400 static void r8153_first_init(struct r8152
*tp
)
3405 r8153_mac_clk_spd(tp
, false);
3406 rxdy_gated_en(tp
, true);
3407 r8153_teredo_off(tp
);
3409 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
3410 ocp_data
&= ~RCR_ACPT_ALL
;
3411 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
3413 rtl8152_nic_reset(tp
);
3416 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3417 ocp_data
&= ~NOW_IS_OOB
;
3418 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
3420 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
3421 ocp_data
&= ~MCU_BORW_EN
;
3422 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
3424 for (i
= 0; i
< 1000; i
++) {
3425 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3426 if (ocp_data
& LINK_LIST_READY
)
3428 usleep_range(1000, 2000);
3431 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
3432 ocp_data
|= RE_INIT_LL
;
3433 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
3435 for (i
= 0; i
< 1000; i
++) {
3436 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3437 if (ocp_data
& LINK_LIST_READY
)
3439 usleep_range(1000, 2000);
3442 rtl_rx_vlan_en(tp
, tp
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
);
3444 ocp_data
= tp
->netdev
->mtu
+ VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
3445 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, ocp_data
);
3446 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_MTPS
, MTPS_JUMBO
);
3448 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
);
3449 ocp_data
|= TCR0_AUTO_FIFO
;
3450 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TCR0
, ocp_data
);
3452 rtl8152_nic_reset(tp
);
3454 /* rx share fifo credit full threshold */
3455 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL0
, RXFIFO_THR1_NORMAL
);
3456 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL1
, RXFIFO_THR2_NORMAL
);
3457 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RXFIFO_CTRL2
, RXFIFO_THR3_NORMAL
);
3458 /* TX share fifo free credit full threshold */
3459 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_TXFIFO_CTRL
, TXFIFO_THR_NORMAL2
);
3462 static void r8153_enter_oob(struct r8152
*tp
)
3467 r8153_mac_clk_spd(tp
, true);
3469 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3470 ocp_data
&= ~NOW_IS_OOB
;
3471 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
3476 for (i
= 0; i
< 1000; i
++) {
3477 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3478 if (ocp_data
& LINK_LIST_READY
)
3480 usleep_range(1000, 2000);
3483 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
);
3484 ocp_data
|= RE_INIT_LL
;
3485 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_SFF_STS_7
, ocp_data
);
3487 for (i
= 0; i
< 1000; i
++) {
3488 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3489 if (ocp_data
& LINK_LIST_READY
)
3491 usleep_range(1000, 2000);
3494 ocp_data
= tp
->netdev
->mtu
+ VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
3495 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, ocp_data
);
3497 switch (tp
->version
) {
3502 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
);
3503 ocp_data
&= ~TEREDO_WAKE_MASK
;
3504 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_CFG
, ocp_data
);
3509 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3510 * type. Set it to zero. bits[7:0] are the W1C bits about
3511 * the events. Set them to all 1 to clear them.
3513 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_TEREDO_WAKE_BASE
, 0x00ff);
3520 rtl_rx_vlan_en(tp
, true);
3522 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PAL_BDC_CR
);
3523 ocp_data
|= ALDPS_PROXY_MODE
;
3524 ocp_write_word(tp
, MCU_TYPE_PLA
, PAL_BDC_CR
, ocp_data
);
3526 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
);
3527 ocp_data
|= NOW_IS_OOB
| DIS_MCU_CLROOB
;
3528 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_OOB_CTRL
, ocp_data
);
3530 rxdy_gated_en(tp
, false);
3532 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
3533 ocp_data
|= RCR_APM
| RCR_AM
| RCR_AB
;
3534 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
3537 static void rtl8153_disable(struct r8152
*tp
)
3539 r8153_aldps_en(tp
, false);
3542 r8153_aldps_en(tp
, true);
3545 static void rtl8153b_disable(struct r8152
*tp
)
3547 r8153b_aldps_en(tp
, false);
3550 r8153b_aldps_en(tp
, true);
3553 static int rtl8152_set_speed(struct r8152
*tp
, u8 autoneg
, u16 speed
, u8 duplex
)
3555 u16 bmcr
, anar
, gbcr
;
3556 enum spd_duplex speed_duplex
;
3559 anar
= r8152_mdio_read(tp
, MII_ADVERTISE
);
3560 anar
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
3561 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
3562 if (tp
->mii
.supports_gmii
) {
3563 gbcr
= r8152_mdio_read(tp
, MII_CTRL1000
);
3564 gbcr
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
3569 if (autoneg
== AUTONEG_DISABLE
) {
3570 if (speed
== SPEED_10
) {
3572 anar
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
3573 speed_duplex
= FORCE_10M_HALF
;
3574 } else if (speed
== SPEED_100
) {
3575 bmcr
= BMCR_SPEED100
;
3576 anar
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
3577 speed_duplex
= FORCE_100M_HALF
;
3578 } else if (speed
== SPEED_1000
&& tp
->mii
.supports_gmii
) {
3579 bmcr
= BMCR_SPEED1000
;
3580 gbcr
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
3581 speed_duplex
= NWAY_1000M_FULL
;
3587 if (duplex
== DUPLEX_FULL
) {
3588 bmcr
|= BMCR_FULLDPLX
;
3589 if (speed
!= SPEED_1000
)
3593 if (speed
== SPEED_10
) {
3594 if (duplex
== DUPLEX_FULL
) {
3595 anar
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
3596 speed_duplex
= NWAY_10M_FULL
;
3598 anar
|= ADVERTISE_10HALF
;
3599 speed_duplex
= NWAY_10M_HALF
;
3601 } else if (speed
== SPEED_100
) {
3602 if (duplex
== DUPLEX_FULL
) {
3603 anar
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
3604 anar
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
3605 speed_duplex
= NWAY_100M_FULL
;
3607 anar
|= ADVERTISE_10HALF
;
3608 anar
|= ADVERTISE_100HALF
;
3609 speed_duplex
= NWAY_100M_HALF
;
3611 } else if (speed
== SPEED_1000
&& tp
->mii
.supports_gmii
) {
3612 if (duplex
== DUPLEX_FULL
) {
3613 anar
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
3614 anar
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
3615 gbcr
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
3617 anar
|= ADVERTISE_10HALF
;
3618 anar
|= ADVERTISE_100HALF
;
3619 gbcr
|= ADVERTISE_1000HALF
;
3621 speed_duplex
= NWAY_1000M_FULL
;
3627 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
3630 if (test_and_clear_bit(PHY_RESET
, &tp
->flags
))
3633 if (tp
->mii
.supports_gmii
)
3634 r8152_mdio_write(tp
, MII_CTRL1000
, gbcr
);
3636 r8152_mdio_write(tp
, MII_ADVERTISE
, anar
);
3637 r8152_mdio_write(tp
, MII_BMCR
, bmcr
);
3639 switch (tp
->version
) {
3642 r8153b_ups_flags_w1w0(tp
, ups_flags_speed(speed_duplex
),
3643 UPS_FLAGS_SPEED_MASK
);
3650 if (bmcr
& BMCR_RESET
) {
3653 for (i
= 0; i
< 50; i
++) {
3655 if ((r8152_mdio_read(tp
, MII_BMCR
) & BMCR_RESET
) == 0)
3664 static void rtl8152_up(struct r8152
*tp
)
3666 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
3669 r8152_aldps_en(tp
, false);
3670 r8152b_exit_oob(tp
);
3671 r8152_aldps_en(tp
, true);
3674 static void rtl8152_down(struct r8152
*tp
)
3676 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
3677 rtl_drop_queued_tx(tp
);
3681 r8152_power_cut_en(tp
, false);
3682 r8152_aldps_en(tp
, false);
3683 r8152b_enter_oob(tp
);
3684 r8152_aldps_en(tp
, true);
3687 static void rtl8153_up(struct r8152
*tp
)
3689 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
3692 r8153_u1u2en(tp
, false);
3693 r8153_u2p3en(tp
, false);
3694 r8153_aldps_en(tp
, false);
3695 r8153_first_init(tp
);
3696 r8153_aldps_en(tp
, true);
3698 switch (tp
->version
) {
3705 r8153_u2p3en(tp
, true);
3709 r8153_u1u2en(tp
, true);
3712 static void rtl8153_down(struct r8152
*tp
)
3714 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
3715 rtl_drop_queued_tx(tp
);
3719 r8153_u1u2en(tp
, false);
3720 r8153_u2p3en(tp
, false);
3721 r8153_power_cut_en(tp
, false);
3722 r8153_aldps_en(tp
, false);
3723 r8153_enter_oob(tp
);
3724 r8153_aldps_en(tp
, true);
3727 static void rtl8153b_up(struct r8152
*tp
)
3729 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
3732 r8153b_u1u2en(tp
, false);
3733 r8153_u2p3en(tp
, false);
3734 r8153b_aldps_en(tp
, false);
3736 r8153_first_init(tp
);
3737 ocp_write_dword(tp
, MCU_TYPE_USB
, USB_RX_BUF_TH
, RX_THR_B
);
3739 r8153b_aldps_en(tp
, true);
3740 r8153_u2p3en(tp
, true);
3741 r8153b_u1u2en(tp
, true);
3744 static void rtl8153b_down(struct r8152
*tp
)
3746 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
3747 rtl_drop_queued_tx(tp
);
3751 r8153b_u1u2en(tp
, false);
3752 r8153_u2p3en(tp
, false);
3753 r8153b_power_cut_en(tp
, false);
3754 r8153b_aldps_en(tp
, false);
3755 r8153_enter_oob(tp
);
3756 r8153b_aldps_en(tp
, true);
3759 static bool rtl8152_in_nway(struct r8152
*tp
)
3763 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_OCP_GPHY_BASE
, 0x2000);
3764 tp
->ocp_base
= 0x2000;
3765 ocp_write_byte(tp
, MCU_TYPE_PLA
, 0xb014, 0x4c); /* phy state */
3766 nway_state
= ocp_read_word(tp
, MCU_TYPE_PLA
, 0xb01a);
3768 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3769 if (nway_state
& 0xc000)
3775 static bool rtl8153_in_nway(struct r8152
*tp
)
3777 u16 phy_state
= ocp_reg_read(tp
, OCP_PHY_STATE
) & 0xff;
3779 if (phy_state
== TXDIS_STATE
|| phy_state
== ABD_STATE
)
3785 static void set_carrier(struct r8152
*tp
)
3787 struct net_device
*netdev
= tp
->netdev
;
3788 struct napi_struct
*napi
= &tp
->napi
;
3791 speed
= rtl8152_get_speed(tp
);
3793 if (speed
& LINK_STATUS
) {
3794 if (!netif_carrier_ok(netdev
)) {
3795 tp
->rtl_ops
.enable(tp
);
3796 set_bit(RTL8152_SET_RX_MODE
, &tp
->flags
);
3797 netif_stop_queue(netdev
);
3799 netif_carrier_on(netdev
);
3801 napi_enable(&tp
->napi
);
3802 netif_wake_queue(netdev
);
3803 netif_info(tp
, link
, netdev
, "carrier on\n");
3804 } else if (netif_queue_stopped(netdev
) &&
3805 skb_queue_len(&tp
->tx_queue
) < tp
->tx_qlen
) {
3806 netif_wake_queue(netdev
);
3809 if (netif_carrier_ok(netdev
)) {
3810 netif_carrier_off(netdev
);
3812 tp
->rtl_ops
.disable(tp
);
3814 netif_info(tp
, link
, netdev
, "carrier off\n");
3819 static void rtl_work_func_t(struct work_struct
*work
)
3821 struct r8152
*tp
= container_of(work
, struct r8152
, schedule
.work
);
3823 /* If the device is unplugged or !netif_running(), the workqueue
3824 * doesn't need to wake the device, and could return directly.
3826 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
) || !netif_running(tp
->netdev
))
3829 if (usb_autopm_get_interface(tp
->intf
) < 0)
3832 if (!test_bit(WORK_ENABLE
, &tp
->flags
))
3835 if (!mutex_trylock(&tp
->control
)) {
3836 schedule_delayed_work(&tp
->schedule
, 0);
3840 if (test_and_clear_bit(RTL8152_LINK_CHG
, &tp
->flags
))
3843 if (test_and_clear_bit(RTL8152_SET_RX_MODE
, &tp
->flags
))
3844 _rtl8152_set_rx_mode(tp
->netdev
);
3846 /* don't schedule napi before linking */
3847 if (test_and_clear_bit(SCHEDULE_NAPI
, &tp
->flags
) &&
3848 netif_carrier_ok(tp
->netdev
))
3849 napi_schedule(&tp
->napi
);
3851 mutex_unlock(&tp
->control
);
3854 usb_autopm_put_interface(tp
->intf
);
3857 static void rtl_hw_phy_work_func_t(struct work_struct
*work
)
3859 struct r8152
*tp
= container_of(work
, struct r8152
, hw_phy_work
.work
);
3861 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
3864 if (usb_autopm_get_interface(tp
->intf
) < 0)
3867 mutex_lock(&tp
->control
);
3869 tp
->rtl_ops
.hw_phy_cfg(tp
);
3871 rtl8152_set_speed(tp
, tp
->autoneg
, tp
->speed
, tp
->duplex
);
3873 mutex_unlock(&tp
->control
);
3875 usb_autopm_put_interface(tp
->intf
);
3878 #ifdef CONFIG_PM_SLEEP
3879 static int rtl_notifier(struct notifier_block
*nb
, unsigned long action
,
3882 struct r8152
*tp
= container_of(nb
, struct r8152
, pm_notifier
);
3885 case PM_HIBERNATION_PREPARE
:
3886 case PM_SUSPEND_PREPARE
:
3887 usb_autopm_get_interface(tp
->intf
);
3890 case PM_POST_HIBERNATION
:
3891 case PM_POST_SUSPEND
:
3892 usb_autopm_put_interface(tp
->intf
);
3895 case PM_POST_RESTORE
:
3896 case PM_RESTORE_PREPARE
:
3905 static int rtl8152_open(struct net_device
*netdev
)
3907 struct r8152
*tp
= netdev_priv(netdev
);
3910 res
= alloc_all_mem(tp
);
3914 res
= usb_autopm_get_interface(tp
->intf
);
3918 mutex_lock(&tp
->control
);
3922 netif_carrier_off(netdev
);
3923 netif_start_queue(netdev
);
3924 set_bit(WORK_ENABLE
, &tp
->flags
);
3926 res
= usb_submit_urb(tp
->intr_urb
, GFP_KERNEL
);
3929 netif_device_detach(tp
->netdev
);
3930 netif_warn(tp
, ifup
, netdev
, "intr_urb submit failed: %d\n",
3934 napi_enable(&tp
->napi
);
3936 mutex_unlock(&tp
->control
);
3938 usb_autopm_put_interface(tp
->intf
);
3939 #ifdef CONFIG_PM_SLEEP
3940 tp
->pm_notifier
.notifier_call
= rtl_notifier
;
3941 register_pm_notifier(&tp
->pm_notifier
);
3946 mutex_unlock(&tp
->control
);
3947 usb_autopm_put_interface(tp
->intf
);
3954 static int rtl8152_close(struct net_device
*netdev
)
3956 struct r8152
*tp
= netdev_priv(netdev
);
3959 #ifdef CONFIG_PM_SLEEP
3960 unregister_pm_notifier(&tp
->pm_notifier
);
3962 napi_disable(&tp
->napi
);
3963 clear_bit(WORK_ENABLE
, &tp
->flags
);
3964 usb_kill_urb(tp
->intr_urb
);
3965 cancel_delayed_work_sync(&tp
->schedule
);
3966 netif_stop_queue(netdev
);
3968 res
= usb_autopm_get_interface(tp
->intf
);
3969 if (res
< 0 || test_bit(RTL8152_UNPLUG
, &tp
->flags
)) {
3970 rtl_drop_queued_tx(tp
);
3973 mutex_lock(&tp
->control
);
3975 tp
->rtl_ops
.down(tp
);
3977 mutex_unlock(&tp
->control
);
3979 usb_autopm_put_interface(tp
->intf
);
3987 static void rtl_tally_reset(struct r8152
*tp
)
3991 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_RSTTALLY
);
3992 ocp_data
|= TALLY_RESET
;
3993 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RSTTALLY
, ocp_data
);
3996 static void r8152b_init(struct r8152
*tp
)
4001 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
4004 data
= r8152_mdio_read(tp
, MII_BMCR
);
4005 if (data
& BMCR_PDOWN
) {
4006 data
&= ~BMCR_PDOWN
;
4007 r8152_mdio_write(tp
, MII_BMCR
, data
);
4010 r8152_aldps_en(tp
, false);
4012 if (tp
->version
== RTL_VER_01
) {
4013 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_LED_FEATURE
);
4014 ocp_data
&= ~LED_MODE_MASK
;
4015 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_LED_FEATURE
, ocp_data
);
4018 r8152_power_cut_en(tp
, false);
4020 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
);
4021 ocp_data
|= TX_10M_IDLE_EN
| PFM_PWM_SWITCH
;
4022 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_PHY_PWR
, ocp_data
);
4023 ocp_data
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL
);
4024 ocp_data
&= ~MCU_CLK_RATIO_MASK
;
4025 ocp_data
|= MCU_CLK_RATIO
| D3_CLK_GATED_EN
;
4026 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL
, ocp_data
);
4027 ocp_data
= GPHY_STS_MSK
| SPEED_DOWN_MSK
|
4028 SPDWN_RXDV_MSK
| SPDWN_LINKCHG_MSK
;
4029 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_GPHY_INTR_IMR
, ocp_data
);
4031 rtl_tally_reset(tp
);
4033 /* enable rx aggregation */
4034 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
4035 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
4036 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
4039 static void r8153_init(struct r8152
*tp
)
4045 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
4048 r8153_u1u2en(tp
, false);
4050 for (i
= 0; i
< 500; i
++) {
4051 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
4057 data
= r8153_phy_status(tp
, 0);
4059 if (tp
->version
== RTL_VER_03
|| tp
->version
== RTL_VER_04
||
4060 tp
->version
== RTL_VER_05
)
4061 ocp_reg_write(tp
, OCP_ADC_CFG
, CKADSEL_L
| ADC_EN
| EN_EMI_L
);
4063 data
= r8152_mdio_read(tp
, MII_BMCR
);
4064 if (data
& BMCR_PDOWN
) {
4065 data
&= ~BMCR_PDOWN
;
4066 r8152_mdio_write(tp
, MII_BMCR
, data
);
4069 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
4071 r8153_u2p3en(tp
, false);
4073 if (tp
->version
== RTL_VER_04
) {
4074 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_SSPHYLINK2
);
4075 ocp_data
&= ~pwd_dn_scale_mask
;
4076 ocp_data
|= pwd_dn_scale(96);
4077 ocp_write_word(tp
, MCU_TYPE_USB
, USB_SSPHYLINK2
, ocp_data
);
4079 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_USB2PHY
);
4080 ocp_data
|= USB2PHY_L1
| USB2PHY_SUSPEND
;
4081 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_USB2PHY
, ocp_data
);
4082 } else if (tp
->version
== RTL_VER_05
) {
4083 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
, PLA_DMY_REG0
);
4084 ocp_data
&= ~ECM_ALDPS
;
4085 ocp_write_byte(tp
, MCU_TYPE_PLA
, PLA_DMY_REG0
, ocp_data
);
4087 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY1
);
4088 if (ocp_read_word(tp
, MCU_TYPE_USB
, USB_BURST_SIZE
) == 0)
4089 ocp_data
&= ~DYNAMIC_BURST
;
4091 ocp_data
|= DYNAMIC_BURST
;
4092 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY1
, ocp_data
);
4093 } else if (tp
->version
== RTL_VER_06
) {
4094 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY1
);
4095 if (ocp_read_word(tp
, MCU_TYPE_USB
, USB_BURST_SIZE
) == 0)
4096 ocp_data
&= ~DYNAMIC_BURST
;
4098 ocp_data
|= DYNAMIC_BURST
;
4099 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY1
, ocp_data
);
4102 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY2
);
4103 ocp_data
|= EP4_FULL_FC
;
4104 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_CSR_DUMMY2
, ocp_data
);
4106 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_WDT11_CTRL
);
4107 ocp_data
&= ~TIMER11_EN
;
4108 ocp_write_word(tp
, MCU_TYPE_USB
, USB_WDT11_CTRL
, ocp_data
);
4110 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_LED_FEATURE
);
4111 ocp_data
&= ~LED_MODE_MASK
;
4112 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_LED_FEATURE
, ocp_data
);
4114 ocp_data
= FIFO_EMPTY_1FB
| ROK_EXIT_LPM
;
4115 if (tp
->version
== RTL_VER_04
&& tp
->udev
->speed
< USB_SPEED_SUPER
)
4116 ocp_data
|= LPM_TIMER_500MS
;
4118 ocp_data
|= LPM_TIMER_500US
;
4119 ocp_write_byte(tp
, MCU_TYPE_USB
, USB_LPM_CTRL
, ocp_data
);
4121 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_AFE_CTRL2
);
4122 ocp_data
&= ~SEN_VAL_MASK
;
4123 ocp_data
|= SEN_VAL_NORMAL
| SEL_RXIDLE
;
4124 ocp_write_word(tp
, MCU_TYPE_USB
, USB_AFE_CTRL2
, ocp_data
);
4126 ocp_write_word(tp
, MCU_TYPE_USB
, USB_CONNECT_TIMER
, 0x0001);
4128 r8153_power_cut_en(tp
, false);
4129 r8153_u1u2en(tp
, true);
4130 r8153_mac_clk_spd(tp
, false);
4131 usb_enable_lpm(tp
->udev
);
4133 /* rx aggregation */
4134 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
4135 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
4136 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
4138 rtl_tally_reset(tp
);
4140 switch (tp
->udev
->speed
) {
4141 case USB_SPEED_SUPER
:
4142 case USB_SPEED_SUPER_PLUS
:
4143 tp
->coalesce
= COALESCE_SUPER
;
4145 case USB_SPEED_HIGH
:
4146 tp
->coalesce
= COALESCE_HIGH
;
4149 tp
->coalesce
= COALESCE_SLOW
;
4154 static void r8153b_init(struct r8152
*tp
)
4160 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
4163 r8153b_u1u2en(tp
, false);
4165 for (i
= 0; i
< 500; i
++) {
4166 if (ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_BOOT_CTRL
) &
4172 data
= r8153_phy_status(tp
, 0);
4174 data
= r8152_mdio_read(tp
, MII_BMCR
);
4175 if (data
& BMCR_PDOWN
) {
4176 data
&= ~BMCR_PDOWN
;
4177 r8152_mdio_write(tp
, MII_BMCR
, data
);
4180 data
= r8153_phy_status(tp
, PHY_STAT_LAN_ON
);
4182 r8153_u2p3en(tp
, false);
4184 /* MSC timer = 0xfff * 8ms = 32760 ms */
4185 ocp_write_word(tp
, MCU_TYPE_USB
, USB_MSC_TIMER
, 0x0fff);
4187 /* U1/U2/L1 idle timer. 500 us */
4188 ocp_write_word(tp
, MCU_TYPE_USB
, USB_U1U2_TIMER
, 500);
4190 r8153b_power_cut_en(tp
, false);
4191 r8153b_ups_en(tp
, false);
4192 r8153b_queue_wake(tp
, false);
4193 rtl_runtime_suspend_enable(tp
, false);
4194 r8153b_u1u2en(tp
, true);
4195 usb_enable_lpm(tp
->udev
);
4197 /* MAC clock speed down */
4198 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
);
4199 ocp_data
|= MAC_CLK_SPDWN_EN
;
4200 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_MAC_PWR_CTRL2
, ocp_data
);
4202 set_bit(GREEN_ETHERNET
, &tp
->flags
);
4204 /* rx aggregation */
4205 ocp_data
= ocp_read_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
);
4206 ocp_data
&= ~(RX_AGG_DISABLE
| RX_ZERO_EN
);
4207 ocp_write_word(tp
, MCU_TYPE_USB
, USB_USB_CTRL
, ocp_data
);
4209 rtl_tally_reset(tp
);
4211 tp
->coalesce
= 15000; /* 15 us */
4214 static int rtl8152_pre_reset(struct usb_interface
*intf
)
4216 struct r8152
*tp
= usb_get_intfdata(intf
);
4217 struct net_device
*netdev
;
4222 netdev
= tp
->netdev
;
4223 if (!netif_running(netdev
))
4226 netif_stop_queue(netdev
);
4227 napi_disable(&tp
->napi
);
4228 clear_bit(WORK_ENABLE
, &tp
->flags
);
4229 usb_kill_urb(tp
->intr_urb
);
4230 cancel_delayed_work_sync(&tp
->schedule
);
4231 if (netif_carrier_ok(netdev
)) {
4232 mutex_lock(&tp
->control
);
4233 tp
->rtl_ops
.disable(tp
);
4234 mutex_unlock(&tp
->control
);
4240 static int rtl8152_post_reset(struct usb_interface
*intf
)
4242 struct r8152
*tp
= usb_get_intfdata(intf
);
4243 struct net_device
*netdev
;
4248 netdev
= tp
->netdev
;
4249 if (!netif_running(netdev
))
4252 set_bit(WORK_ENABLE
, &tp
->flags
);
4253 if (netif_carrier_ok(netdev
)) {
4254 mutex_lock(&tp
->control
);
4255 tp
->rtl_ops
.enable(tp
);
4257 rtl8152_set_rx_mode(netdev
);
4258 mutex_unlock(&tp
->control
);
4261 napi_enable(&tp
->napi
);
4262 netif_wake_queue(netdev
);
4263 usb_submit_urb(tp
->intr_urb
, GFP_KERNEL
);
4265 if (!list_empty(&tp
->rx_done
))
4266 napi_schedule(&tp
->napi
);
4271 static bool delay_autosuspend(struct r8152
*tp
)
4273 bool sw_linking
= !!netif_carrier_ok(tp
->netdev
);
4274 bool hw_linking
= !!(rtl8152_get_speed(tp
) & LINK_STATUS
);
4276 /* This means a linking change occurs and the driver doesn't detect it,
4277 * yet. If the driver has disabled tx/rx and hw is linking on, the
4278 * device wouldn't wake up by receiving any packet.
4280 if (work_busy(&tp
->schedule
.work
) || sw_linking
!= hw_linking
)
4283 /* If the linking down is occurred by nway, the device may miss the
4284 * linking change event. And it wouldn't wake when linking on.
4286 if (!sw_linking
&& tp
->rtl_ops
.in_nway(tp
))
4288 else if (!skb_queue_empty(&tp
->tx_queue
))
4294 static int rtl8152_runtime_resume(struct r8152
*tp
)
4296 struct net_device
*netdev
= tp
->netdev
;
4298 if (netif_running(netdev
) && netdev
->flags
& IFF_UP
) {
4299 struct napi_struct
*napi
= &tp
->napi
;
4301 tp
->rtl_ops
.autosuspend_en(tp
, false);
4303 set_bit(WORK_ENABLE
, &tp
->flags
);
4305 if (netif_carrier_ok(netdev
)) {
4306 if (rtl8152_get_speed(tp
) & LINK_STATUS
) {
4309 netif_carrier_off(netdev
);
4310 tp
->rtl_ops
.disable(tp
);
4311 netif_info(tp
, link
, netdev
, "linking down\n");
4316 clear_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
4317 smp_mb__after_atomic();
4319 if (!list_empty(&tp
->rx_done
))
4320 napi_schedule(&tp
->napi
);
4322 usb_submit_urb(tp
->intr_urb
, GFP_NOIO
);
4324 if (netdev
->flags
& IFF_UP
)
4325 tp
->rtl_ops
.autosuspend_en(tp
, false);
4327 clear_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
4333 static int rtl8152_system_resume(struct r8152
*tp
)
4335 struct net_device
*netdev
= tp
->netdev
;
4337 netif_device_attach(netdev
);
4339 if (netif_running(netdev
) && netdev
->flags
& IFF_UP
) {
4341 netif_carrier_off(netdev
);
4342 set_bit(WORK_ENABLE
, &tp
->flags
);
4343 usb_submit_urb(tp
->intr_urb
, GFP_NOIO
);
4349 static int rtl8152_runtime_suspend(struct r8152
*tp
)
4351 struct net_device
*netdev
= tp
->netdev
;
4354 set_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
4355 smp_mb__after_atomic();
4357 if (netif_running(netdev
) && test_bit(WORK_ENABLE
, &tp
->flags
)) {
4360 if (netif_carrier_ok(netdev
)) {
4363 rcr
= ocp_read_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
);
4364 ocp_data
= rcr
& ~RCR_ACPT_ALL
;
4365 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, ocp_data
);
4366 rxdy_gated_en(tp
, true);
4367 ocp_data
= ocp_read_byte(tp
, MCU_TYPE_PLA
,
4369 if (!(ocp_data
& RXFIFO_EMPTY
)) {
4370 rxdy_gated_en(tp
, false);
4371 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, rcr
);
4372 clear_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
4373 smp_mb__after_atomic();
4379 clear_bit(WORK_ENABLE
, &tp
->flags
);
4380 usb_kill_urb(tp
->intr_urb
);
4382 tp
->rtl_ops
.autosuspend_en(tp
, true);
4384 if (netif_carrier_ok(netdev
)) {
4385 struct napi_struct
*napi
= &tp
->napi
;
4389 rxdy_gated_en(tp
, false);
4390 ocp_write_dword(tp
, MCU_TYPE_PLA
, PLA_RCR
, rcr
);
4394 if (delay_autosuspend(tp
)) {
4395 rtl8152_runtime_resume(tp
);
4404 static int rtl8152_system_suspend(struct r8152
*tp
)
4406 struct net_device
*netdev
= tp
->netdev
;
4409 netif_device_detach(netdev
);
4411 if (netif_running(netdev
) && test_bit(WORK_ENABLE
, &tp
->flags
)) {
4412 struct napi_struct
*napi
= &tp
->napi
;
4414 clear_bit(WORK_ENABLE
, &tp
->flags
);
4415 usb_kill_urb(tp
->intr_urb
);
4417 cancel_delayed_work_sync(&tp
->schedule
);
4418 tp
->rtl_ops
.down(tp
);
4425 static int rtl8152_suspend(struct usb_interface
*intf
, pm_message_t message
)
4427 struct r8152
*tp
= usb_get_intfdata(intf
);
4430 mutex_lock(&tp
->control
);
4432 if (PMSG_IS_AUTO(message
))
4433 ret
= rtl8152_runtime_suspend(tp
);
4435 ret
= rtl8152_system_suspend(tp
);
4437 mutex_unlock(&tp
->control
);
4442 static int rtl8152_resume(struct usb_interface
*intf
)
4444 struct r8152
*tp
= usb_get_intfdata(intf
);
4447 mutex_lock(&tp
->control
);
4449 if (test_bit(SELECTIVE_SUSPEND
, &tp
->flags
))
4450 ret
= rtl8152_runtime_resume(tp
);
4452 ret
= rtl8152_system_resume(tp
);
4454 mutex_unlock(&tp
->control
);
4459 static int rtl8152_reset_resume(struct usb_interface
*intf
)
4461 struct r8152
*tp
= usb_get_intfdata(intf
);
4463 clear_bit(SELECTIVE_SUSPEND
, &tp
->flags
);
4464 mutex_lock(&tp
->control
);
4465 tp
->rtl_ops
.init(tp
);
4466 queue_delayed_work(system_long_wq
, &tp
->hw_phy_work
, 0);
4467 mutex_unlock(&tp
->control
);
4468 return rtl8152_resume(intf
);
4471 static void rtl8152_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
4473 struct r8152
*tp
= netdev_priv(dev
);
4475 if (usb_autopm_get_interface(tp
->intf
) < 0)
4478 if (!rtl_can_wakeup(tp
)) {
4482 mutex_lock(&tp
->control
);
4483 wol
->supported
= WAKE_ANY
;
4484 wol
->wolopts
= __rtl_get_wol(tp
);
4485 mutex_unlock(&tp
->control
);
4488 usb_autopm_put_interface(tp
->intf
);
4491 static int rtl8152_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
4493 struct r8152
*tp
= netdev_priv(dev
);
4496 if (!rtl_can_wakeup(tp
))
4499 ret
= usb_autopm_get_interface(tp
->intf
);
4503 mutex_lock(&tp
->control
);
4505 __rtl_set_wol(tp
, wol
->wolopts
);
4506 tp
->saved_wolopts
= wol
->wolopts
& WAKE_ANY
;
4508 mutex_unlock(&tp
->control
);
4510 usb_autopm_put_interface(tp
->intf
);
4516 static u32
rtl8152_get_msglevel(struct net_device
*dev
)
4518 struct r8152
*tp
= netdev_priv(dev
);
4520 return tp
->msg_enable
;
4523 static void rtl8152_set_msglevel(struct net_device
*dev
, u32 value
)
4525 struct r8152
*tp
= netdev_priv(dev
);
4527 tp
->msg_enable
= value
;
4530 static void rtl8152_get_drvinfo(struct net_device
*netdev
,
4531 struct ethtool_drvinfo
*info
)
4533 struct r8152
*tp
= netdev_priv(netdev
);
4535 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
4536 strlcpy(info
->version
, DRIVER_VERSION
, sizeof(info
->version
));
4537 usb_make_path(tp
->udev
, info
->bus_info
, sizeof(info
->bus_info
));
4541 int rtl8152_get_link_ksettings(struct net_device
*netdev
,
4542 struct ethtool_link_ksettings
*cmd
)
4544 struct r8152
*tp
= netdev_priv(netdev
);
4547 if (!tp
->mii
.mdio_read
)
4550 ret
= usb_autopm_get_interface(tp
->intf
);
4554 mutex_lock(&tp
->control
);
4556 mii_ethtool_get_link_ksettings(&tp
->mii
, cmd
);
4558 mutex_unlock(&tp
->control
);
4560 usb_autopm_put_interface(tp
->intf
);
4566 static int rtl8152_set_link_ksettings(struct net_device
*dev
,
4567 const struct ethtool_link_ksettings
*cmd
)
4569 struct r8152
*tp
= netdev_priv(dev
);
4572 ret
= usb_autopm_get_interface(tp
->intf
);
4576 mutex_lock(&tp
->control
);
4578 ret
= rtl8152_set_speed(tp
, cmd
->base
.autoneg
, cmd
->base
.speed
,
4581 tp
->autoneg
= cmd
->base
.autoneg
;
4582 tp
->speed
= cmd
->base
.speed
;
4583 tp
->duplex
= cmd
->base
.duplex
;
4586 mutex_unlock(&tp
->control
);
4588 usb_autopm_put_interface(tp
->intf
);
4594 static const char rtl8152_gstrings
[][ETH_GSTRING_LEN
] = {
4601 "tx_single_collisions",
4602 "tx_multi_collisions",
4610 static int rtl8152_get_sset_count(struct net_device
*dev
, int sset
)
4614 return ARRAY_SIZE(rtl8152_gstrings
);
4620 static void rtl8152_get_ethtool_stats(struct net_device
*dev
,
4621 struct ethtool_stats
*stats
, u64
*data
)
4623 struct r8152
*tp
= netdev_priv(dev
);
4624 struct tally_counter tally
;
4626 if (usb_autopm_get_interface(tp
->intf
) < 0)
4629 generic_ocp_read(tp
, PLA_TALLYCNT
, sizeof(tally
), &tally
, MCU_TYPE_PLA
);
4631 usb_autopm_put_interface(tp
->intf
);
4633 data
[0] = le64_to_cpu(tally
.tx_packets
);
4634 data
[1] = le64_to_cpu(tally
.rx_packets
);
4635 data
[2] = le64_to_cpu(tally
.tx_errors
);
4636 data
[3] = le32_to_cpu(tally
.rx_errors
);
4637 data
[4] = le16_to_cpu(tally
.rx_missed
);
4638 data
[5] = le16_to_cpu(tally
.align_errors
);
4639 data
[6] = le32_to_cpu(tally
.tx_one_collision
);
4640 data
[7] = le32_to_cpu(tally
.tx_multi_collision
);
4641 data
[8] = le64_to_cpu(tally
.rx_unicast
);
4642 data
[9] = le64_to_cpu(tally
.rx_broadcast
);
4643 data
[10] = le32_to_cpu(tally
.rx_multicast
);
4644 data
[11] = le16_to_cpu(tally
.tx_aborted
);
4645 data
[12] = le16_to_cpu(tally
.tx_underrun
);
4648 static void rtl8152_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
4650 switch (stringset
) {
4652 memcpy(data
, *rtl8152_gstrings
, sizeof(rtl8152_gstrings
));
4657 static int r8152_get_eee(struct r8152
*tp
, struct ethtool_eee
*eee
)
4659 u32 ocp_data
, lp
, adv
, supported
= 0;
4662 val
= r8152_mmd_read(tp
, MDIO_MMD_PCS
, MDIO_PCS_EEE_ABLE
);
4663 supported
= mmd_eee_cap_to_ethtool_sup_t(val
);
4665 val
= r8152_mmd_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
);
4666 adv
= mmd_eee_adv_to_ethtool_adv_t(val
);
4668 val
= r8152_mmd_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_LPABLE
);
4669 lp
= mmd_eee_adv_to_ethtool_adv_t(val
);
4671 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
);
4672 ocp_data
&= EEE_RX_EN
| EEE_TX_EN
;
4674 eee
->eee_enabled
= !!ocp_data
;
4675 eee
->eee_active
= !!(supported
& adv
& lp
);
4676 eee
->supported
= supported
;
4677 eee
->advertised
= adv
;
4678 eee
->lp_advertised
= lp
;
4683 static int r8152_set_eee(struct r8152
*tp
, struct ethtool_eee
*eee
)
4685 u16 val
= ethtool_adv_to_mmd_eee_adv_t(eee
->advertised
);
4687 r8152_eee_en(tp
, eee
->eee_enabled
);
4689 if (!eee
->eee_enabled
)
4692 r8152_mmd_write(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, val
);
4697 static int r8153_get_eee(struct r8152
*tp
, struct ethtool_eee
*eee
)
4699 u32 ocp_data
, lp
, adv
, supported
= 0;
4702 val
= ocp_reg_read(tp
, OCP_EEE_ABLE
);
4703 supported
= mmd_eee_cap_to_ethtool_sup_t(val
);
4705 val
= ocp_reg_read(tp
, OCP_EEE_ADV
);
4706 adv
= mmd_eee_adv_to_ethtool_adv_t(val
);
4708 val
= ocp_reg_read(tp
, OCP_EEE_LPABLE
);
4709 lp
= mmd_eee_adv_to_ethtool_adv_t(val
);
4711 ocp_data
= ocp_read_word(tp
, MCU_TYPE_PLA
, PLA_EEE_CR
);
4712 ocp_data
&= EEE_RX_EN
| EEE_TX_EN
;
4714 eee
->eee_enabled
= !!ocp_data
;
4715 eee
->eee_active
= !!(supported
& adv
& lp
);
4716 eee
->supported
= supported
;
4717 eee
->advertised
= adv
;
4718 eee
->lp_advertised
= lp
;
4723 static int r8153_set_eee(struct r8152
*tp
, struct ethtool_eee
*eee
)
4725 u16 val
= ethtool_adv_to_mmd_eee_adv_t(eee
->advertised
);
4727 r8153_eee_en(tp
, eee
->eee_enabled
);
4729 if (!eee
->eee_enabled
)
4732 ocp_reg_write(tp
, OCP_EEE_ADV
, val
);
4737 static int r8153b_set_eee(struct r8152
*tp
, struct ethtool_eee
*eee
)
4739 u16 val
= ethtool_adv_to_mmd_eee_adv_t(eee
->advertised
);
4741 r8153b_eee_en(tp
, eee
->eee_enabled
);
4743 if (!eee
->eee_enabled
)
4746 ocp_reg_write(tp
, OCP_EEE_ADV
, val
);
4752 rtl_ethtool_get_eee(struct net_device
*net
, struct ethtool_eee
*edata
)
4754 struct r8152
*tp
= netdev_priv(net
);
4757 ret
= usb_autopm_get_interface(tp
->intf
);
4761 mutex_lock(&tp
->control
);
4763 ret
= tp
->rtl_ops
.eee_get(tp
, edata
);
4765 mutex_unlock(&tp
->control
);
4767 usb_autopm_put_interface(tp
->intf
);
4774 rtl_ethtool_set_eee(struct net_device
*net
, struct ethtool_eee
*edata
)
4776 struct r8152
*tp
= netdev_priv(net
);
4779 ret
= usb_autopm_get_interface(tp
->intf
);
4783 mutex_lock(&tp
->control
);
4785 ret
= tp
->rtl_ops
.eee_set(tp
, edata
);
4787 ret
= mii_nway_restart(&tp
->mii
);
4789 mutex_unlock(&tp
->control
);
4791 usb_autopm_put_interface(tp
->intf
);
4797 static int rtl8152_nway_reset(struct net_device
*dev
)
4799 struct r8152
*tp
= netdev_priv(dev
);
4802 ret
= usb_autopm_get_interface(tp
->intf
);
4806 mutex_lock(&tp
->control
);
4808 ret
= mii_nway_restart(&tp
->mii
);
4810 mutex_unlock(&tp
->control
);
4812 usb_autopm_put_interface(tp
->intf
);
4818 static int rtl8152_get_coalesce(struct net_device
*netdev
,
4819 struct ethtool_coalesce
*coalesce
)
4821 struct r8152
*tp
= netdev_priv(netdev
);
4823 switch (tp
->version
) {
4832 coalesce
->rx_coalesce_usecs
= tp
->coalesce
;
4837 static int rtl8152_set_coalesce(struct net_device
*netdev
,
4838 struct ethtool_coalesce
*coalesce
)
4840 struct r8152
*tp
= netdev_priv(netdev
);
4843 switch (tp
->version
) {
4852 if (coalesce
->rx_coalesce_usecs
> COALESCE_SLOW
)
4855 ret
= usb_autopm_get_interface(tp
->intf
);
4859 mutex_lock(&tp
->control
);
4861 if (tp
->coalesce
!= coalesce
->rx_coalesce_usecs
) {
4862 tp
->coalesce
= coalesce
->rx_coalesce_usecs
;
4864 if (netif_running(tp
->netdev
) && netif_carrier_ok(netdev
))
4865 r8153_set_rx_early_timeout(tp
);
4868 mutex_unlock(&tp
->control
);
4870 usb_autopm_put_interface(tp
->intf
);
4875 static const struct ethtool_ops ops
= {
4876 .get_drvinfo
= rtl8152_get_drvinfo
,
4877 .get_link
= ethtool_op_get_link
,
4878 .nway_reset
= rtl8152_nway_reset
,
4879 .get_msglevel
= rtl8152_get_msglevel
,
4880 .set_msglevel
= rtl8152_set_msglevel
,
4881 .get_wol
= rtl8152_get_wol
,
4882 .set_wol
= rtl8152_set_wol
,
4883 .get_strings
= rtl8152_get_strings
,
4884 .get_sset_count
= rtl8152_get_sset_count
,
4885 .get_ethtool_stats
= rtl8152_get_ethtool_stats
,
4886 .get_coalesce
= rtl8152_get_coalesce
,
4887 .set_coalesce
= rtl8152_set_coalesce
,
4888 .get_eee
= rtl_ethtool_get_eee
,
4889 .set_eee
= rtl_ethtool_set_eee
,
4890 .get_link_ksettings
= rtl8152_get_link_ksettings
,
4891 .set_link_ksettings
= rtl8152_set_link_ksettings
,
4894 static int rtl8152_ioctl(struct net_device
*netdev
, struct ifreq
*rq
, int cmd
)
4896 struct r8152
*tp
= netdev_priv(netdev
);
4897 struct mii_ioctl_data
*data
= if_mii(rq
);
4900 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
4903 res
= usb_autopm_get_interface(tp
->intf
);
4909 data
->phy_id
= R8152_PHY_ID
; /* Internal PHY */
4913 mutex_lock(&tp
->control
);
4914 data
->val_out
= r8152_mdio_read(tp
, data
->reg_num
);
4915 mutex_unlock(&tp
->control
);
4919 if (!capable(CAP_NET_ADMIN
)) {
4923 mutex_lock(&tp
->control
);
4924 r8152_mdio_write(tp
, data
->reg_num
, data
->val_in
);
4925 mutex_unlock(&tp
->control
);
4932 usb_autopm_put_interface(tp
->intf
);
4938 static int rtl8152_change_mtu(struct net_device
*dev
, int new_mtu
)
4940 struct r8152
*tp
= netdev_priv(dev
);
4943 switch (tp
->version
) {
4953 ret
= usb_autopm_get_interface(tp
->intf
);
4957 mutex_lock(&tp
->control
);
4961 if (netif_running(dev
)) {
4962 u32 rms
= new_mtu
+ VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
4964 ocp_write_word(tp
, MCU_TYPE_PLA
, PLA_RMS
, rms
);
4966 if (netif_carrier_ok(dev
))
4967 r8153_set_rx_early_size(tp
);
4970 mutex_unlock(&tp
->control
);
4972 usb_autopm_put_interface(tp
->intf
);
4977 static const struct net_device_ops rtl8152_netdev_ops
= {
4978 .ndo_open
= rtl8152_open
,
4979 .ndo_stop
= rtl8152_close
,
4980 .ndo_do_ioctl
= rtl8152_ioctl
,
4981 .ndo_start_xmit
= rtl8152_start_xmit
,
4982 .ndo_tx_timeout
= rtl8152_tx_timeout
,
4983 .ndo_set_features
= rtl8152_set_features
,
4984 .ndo_set_rx_mode
= rtl8152_set_rx_mode
,
4985 .ndo_set_mac_address
= rtl8152_set_mac_address
,
4986 .ndo_change_mtu
= rtl8152_change_mtu
,
4987 .ndo_validate_addr
= eth_validate_addr
,
4988 .ndo_features_check
= rtl8152_features_check
,
4991 static void rtl8152_unload(struct r8152
*tp
)
4993 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
4996 if (tp
->version
!= RTL_VER_01
)
4997 r8152_power_cut_en(tp
, true);
5000 static void rtl8153_unload(struct r8152
*tp
)
5002 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
5005 r8153_power_cut_en(tp
, false);
5008 static void rtl8153b_unload(struct r8152
*tp
)
5010 if (test_bit(RTL8152_UNPLUG
, &tp
->flags
))
5013 r8153b_power_cut_en(tp
, false);
5016 static int rtl_ops_init(struct r8152
*tp
)
5018 struct rtl_ops
*ops
= &tp
->rtl_ops
;
5021 switch (tp
->version
) {
5025 ops
->init
= r8152b_init
;
5026 ops
->enable
= rtl8152_enable
;
5027 ops
->disable
= rtl8152_disable
;
5028 ops
->up
= rtl8152_up
;
5029 ops
->down
= rtl8152_down
;
5030 ops
->unload
= rtl8152_unload
;
5031 ops
->eee_get
= r8152_get_eee
;
5032 ops
->eee_set
= r8152_set_eee
;
5033 ops
->in_nway
= rtl8152_in_nway
;
5034 ops
->hw_phy_cfg
= r8152b_hw_phy_cfg
;
5035 ops
->autosuspend_en
= rtl_runtime_suspend_enable
;
5042 ops
->init
= r8153_init
;
5043 ops
->enable
= rtl8153_enable
;
5044 ops
->disable
= rtl8153_disable
;
5045 ops
->up
= rtl8153_up
;
5046 ops
->down
= rtl8153_down
;
5047 ops
->unload
= rtl8153_unload
;
5048 ops
->eee_get
= r8153_get_eee
;
5049 ops
->eee_set
= r8153_set_eee
;
5050 ops
->in_nway
= rtl8153_in_nway
;
5051 ops
->hw_phy_cfg
= r8153_hw_phy_cfg
;
5052 ops
->autosuspend_en
= rtl8153_runtime_enable
;
5057 ops
->init
= r8153b_init
;
5058 ops
->enable
= rtl8153_enable
;
5059 ops
->disable
= rtl8153b_disable
;
5060 ops
->up
= rtl8153b_up
;
5061 ops
->down
= rtl8153b_down
;
5062 ops
->unload
= rtl8153b_unload
;
5063 ops
->eee_get
= r8153_get_eee
;
5064 ops
->eee_set
= r8153b_set_eee
;
5065 ops
->in_nway
= rtl8153_in_nway
;
5066 ops
->hw_phy_cfg
= r8153b_hw_phy_cfg
;
5067 ops
->autosuspend_en
= rtl8153b_runtime_enable
;
5072 netif_err(tp
, probe
, tp
->netdev
, "Unknown Device\n");
5079 static u8
rtl_get_version(struct usb_interface
*intf
)
5081 struct usb_device
*udev
= interface_to_usbdev(intf
);
5087 tmp
= kmalloc(sizeof(*tmp
), GFP_KERNEL
);
5091 ret
= usb_control_msg(udev
, usb_rcvctrlpipe(udev
, 0),
5092 RTL8152_REQ_GET_REGS
, RTL8152_REQT_READ
,
5093 PLA_TCR0
, MCU_TYPE_PLA
, tmp
, sizeof(*tmp
), 500);
5095 ocp_data
= (__le32_to_cpu(*tmp
) >> 16) & VERSION_MASK
;
5101 version
= RTL_VER_01
;
5104 version
= RTL_VER_02
;
5107 version
= RTL_VER_03
;
5110 version
= RTL_VER_04
;
5113 version
= RTL_VER_05
;
5116 version
= RTL_VER_06
;
5119 version
= RTL_VER_07
;
5122 version
= RTL_VER_08
;
5125 version
= RTL_VER_09
;
5128 version
= RTL_VER_UNKNOWN
;
5129 dev_info(&intf
->dev
, "Unknown version 0x%04x\n", ocp_data
);
5133 dev_dbg(&intf
->dev
, "Detected version 0x%04x\n", version
);
5138 static int rtl8152_probe(struct usb_interface
*intf
,
5139 const struct usb_device_id
*id
)
5141 struct usb_device
*udev
= interface_to_usbdev(intf
);
5142 u8 version
= rtl_get_version(intf
);
5144 struct net_device
*netdev
;
5147 if (version
== RTL_VER_UNKNOWN
)
5150 if (udev
->actconfig
->desc
.bConfigurationValue
!= 1) {
5151 usb_driver_set_configuration(udev
, 1);
5155 usb_reset_device(udev
);
5156 netdev
= alloc_etherdev(sizeof(struct r8152
));
5158 dev_err(&intf
->dev
, "Out of memory\n");
5162 SET_NETDEV_DEV(netdev
, &intf
->dev
);
5163 tp
= netdev_priv(netdev
);
5164 tp
->msg_enable
= 0x7FFF;
5167 tp
->netdev
= netdev
;
5169 tp
->version
= version
;
5175 tp
->mii
.supports_gmii
= 0;
5178 tp
->mii
.supports_gmii
= 1;
5182 ret
= rtl_ops_init(tp
);
5186 mutex_init(&tp
->control
);
5187 INIT_DELAYED_WORK(&tp
->schedule
, rtl_work_func_t
);
5188 INIT_DELAYED_WORK(&tp
->hw_phy_work
, rtl_hw_phy_work_func_t
);
5190 netdev
->netdev_ops
= &rtl8152_netdev_ops
;
5191 netdev
->watchdog_timeo
= RTL8152_TX_TIMEOUT
;
5193 netdev
->features
|= NETIF_F_RXCSUM
| NETIF_F_IP_CSUM
| NETIF_F_SG
|
5194 NETIF_F_TSO
| NETIF_F_FRAGLIST
| NETIF_F_IPV6_CSUM
|
5195 NETIF_F_TSO6
| NETIF_F_HW_VLAN_CTAG_RX
|
5196 NETIF_F_HW_VLAN_CTAG_TX
;
5197 netdev
->hw_features
= NETIF_F_RXCSUM
| NETIF_F_IP_CSUM
| NETIF_F_SG
|
5198 NETIF_F_TSO
| NETIF_F_FRAGLIST
|
5199 NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
|
5200 NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
;
5201 netdev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
5202 NETIF_F_HIGHDMA
| NETIF_F_FRAGLIST
|
5203 NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
5205 if (tp
->version
== RTL_VER_01
) {
5206 netdev
->features
&= ~NETIF_F_RXCSUM
;
5207 netdev
->hw_features
&= ~NETIF_F_RXCSUM
;
5210 netdev
->ethtool_ops
= &ops
;
5211 netif_set_gso_max_size(netdev
, RTL_LIMITED_TSO_SIZE
);
5213 /* MTU range: 68 - 1500 or 9194 */
5214 netdev
->min_mtu
= ETH_MIN_MTU
;
5215 switch (tp
->version
) {
5218 netdev
->max_mtu
= ETH_DATA_LEN
;
5221 netdev
->max_mtu
= RTL8153_MAX_MTU
;
5225 tp
->mii
.dev
= netdev
;
5226 tp
->mii
.mdio_read
= read_mii_word
;
5227 tp
->mii
.mdio_write
= write_mii_word
;
5228 tp
->mii
.phy_id_mask
= 0x3f;
5229 tp
->mii
.reg_num_mask
= 0x1f;
5230 tp
->mii
.phy_id
= R8152_PHY_ID
;
5232 tp
->autoneg
= AUTONEG_ENABLE
;
5233 tp
->speed
= tp
->mii
.supports_gmii
? SPEED_1000
: SPEED_100
;
5234 tp
->duplex
= DUPLEX_FULL
;
5236 intf
->needs_remote_wakeup
= 1;
5238 tp
->rtl_ops
.init(tp
);
5239 queue_delayed_work(system_long_wq
, &tp
->hw_phy_work
, 0);
5240 set_ethernet_addr(tp
);
5242 usb_set_intfdata(intf
, tp
);
5243 netif_napi_add(netdev
, &tp
->napi
, r8152_poll
, RTL8152_NAPI_WEIGHT
);
5245 ret
= register_netdev(netdev
);
5247 netif_err(tp
, probe
, netdev
, "couldn't register the device\n");
5251 if (!rtl_can_wakeup(tp
))
5252 __rtl_set_wol(tp
, 0);
5254 tp
->saved_wolopts
= __rtl_get_wol(tp
);
5255 if (tp
->saved_wolopts
)
5256 device_set_wakeup_enable(&udev
->dev
, true);
5258 device_set_wakeup_enable(&udev
->dev
, false);
5260 netif_info(tp
, probe
, netdev
, "%s\n", DRIVER_VERSION
);
5265 netif_napi_del(&tp
->napi
);
5266 usb_set_intfdata(intf
, NULL
);
5268 free_netdev(netdev
);
5272 static void rtl8152_disconnect(struct usb_interface
*intf
)
5274 struct r8152
*tp
= usb_get_intfdata(intf
);
5276 usb_set_intfdata(intf
, NULL
);
5278 struct usb_device
*udev
= tp
->udev
;
5280 if (udev
->state
== USB_STATE_NOTATTACHED
)
5281 set_bit(RTL8152_UNPLUG
, &tp
->flags
);
5283 netif_napi_del(&tp
->napi
);
5284 unregister_netdev(tp
->netdev
);
5285 cancel_delayed_work_sync(&tp
->hw_phy_work
);
5286 tp
->rtl_ops
.unload(tp
);
5287 free_netdev(tp
->netdev
);
5291 #define REALTEK_USB_DEVICE(vend, prod) \
5292 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5293 USB_DEVICE_ID_MATCH_INT_CLASS, \
5294 .idVendor = (vend), \
5295 .idProduct = (prod), \
5296 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5299 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5300 USB_DEVICE_ID_MATCH_DEVICE, \
5301 .idVendor = (vend), \
5302 .idProduct = (prod), \
5303 .bInterfaceClass = USB_CLASS_COMM, \
5304 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5305 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5307 /* table of devices that work with this driver */
5308 static const struct usb_device_id rtl8152_table
[] = {
5309 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8050)},
5310 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8152)},
5311 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK
, 0x8153)},
5312 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT
, 0x07ab)},
5313 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT
, 0x07c6)},
5314 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG
, 0xa101)},
5315 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x304f)},
5316 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x3062)},
5317 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x3069)},
5318 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x7205)},
5319 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x720c)},
5320 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO
, 0x7214)},
5321 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS
, 0x0041)},
5322 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA
, 0x09ff)},
5323 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK
, 0x0601)},
5327 MODULE_DEVICE_TABLE(usb
, rtl8152_table
);
5329 static struct usb_driver rtl8152_driver
= {
5331 .id_table
= rtl8152_table
,
5332 .probe
= rtl8152_probe
,
5333 .disconnect
= rtl8152_disconnect
,
5334 .suspend
= rtl8152_suspend
,
5335 .resume
= rtl8152_resume
,
5336 .reset_resume
= rtl8152_reset_resume
,
5337 .pre_reset
= rtl8152_pre_reset
,
5338 .post_reset
= rtl8152_post_reset
,
5339 .supports_autosuspend
= 1,
5340 .disable_hub_initiated_lpm
= 1,
5343 module_usb_driver(rtl8152_driver
);
5345 MODULE_AUTHOR(DRIVER_AUTHOR
);
5346 MODULE_DESCRIPTION(DRIVER_DESC
);
5347 MODULE_LICENSE("GPL");
5348 MODULE_VERSION(DRIVER_VERSION
);