2 * FarSync WAN driver for Linux (2.6.x kernel version)
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/version.h>
21 #include <linux/pci.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
25 #include <linux/hdlc.h>
27 #include <asm/uaccess.h>
34 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
36 MODULE_LICENSE("GPL");
38 /* Driver configuration and global parameters
39 * ==========================================
42 /* Number of ports (per card) and cards supported
44 #define FST_MAX_PORTS 4
45 #define FST_MAX_CARDS 32
47 /* Default parameters for the link
49 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
50 * useful, the syncppp module forces
51 * this down assuming a slower line I
54 #define FST_TXQ_DEPTH 16 /* This one is for the buffering
55 * of frames on the way down to the card
56 * so that we can keep the card busy
57 * and maximise throughput
59 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
61 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
62 * control from network layer */
63 #define FST_MAX_MTU 8000 /* Huge but possible */
64 #define FST_DEF_MTU 1500 /* Common sane value */
66 #define FST_TX_TIMEOUT (2*HZ)
69 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
71 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
75 * Modules parameters and associated varaibles
77 int fst_txq_low
= FST_LOW_WATER_MARK
;
78 int fst_txq_high
= FST_HIGH_WATER_MARK
;
79 int fst_max_reads
= 7;
80 int fst_excluded_cards
= 0;
81 int fst_excluded_list
[FST_MAX_CARDS
];
83 module_param(fst_txq_low
, int, 0);
84 module_param(fst_txq_high
, int, 0);
85 module_param(fst_max_reads
, int, 0);
86 module_param(fst_excluded_cards
, int, 0);
87 module_param_array(fst_excluded_list
, int, NULL
, 0);
89 /* Card shared memory layout
90 * =========================
94 /* This information is derived in part from the FarSite FarSync Smc.h
95 * file. Unfortunately various name clashes and the non-portability of the
96 * bit field declarations in that file have meant that I have chosen to
97 * recreate the information here.
99 * The SMC (Shared Memory Configuration) has a version number that is
100 * incremented every time there is a significant change. This number can
101 * be used to check that we have not got out of step with the firmware
102 * contained in the .CDE files.
104 #define SMC_VERSION 24
106 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
108 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
109 * configuration structure */
110 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
113 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */
114 #define LEN_RX_BUFFER 8192
116 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
117 #define LEN_SMALL_RX_BUFFER 256
119 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
120 #define NUM_RX_BUFFER 8
122 /* Interrupt retry time in milliseconds */
123 #define INT_RETRY_TIME 2
125 /* The Am186CH/CC processors support a SmartDMA mode using circular pools
126 * of buffer descriptors. The structure is almost identical to that used
127 * in the LANCE Ethernet controllers. Details available as PDF from the
128 * AMD web site: http://www.amd.com/products/epd/processors/\
129 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
131 struct txdesc
{ /* Transmit descriptor */
132 volatile u16 ladr
; /* Low order address of packet. This is a
133 * linear address in the Am186 memory space
135 volatile u8 hadr
; /* High order address. Low 4 bits only, high 4
138 volatile u8 bits
; /* Status and config */
139 volatile u16 bcnt
; /* 2s complement of packet size in low 15 bits.
140 * Transmit terminal count interrupt enable in
143 u16 unused
; /* Not used in Tx */
146 struct rxdesc
{ /* Receive descriptor */
147 volatile u16 ladr
; /* Low order address of packet */
148 volatile u8 hadr
; /* High order address */
149 volatile u8 bits
; /* Status and config */
150 volatile u16 bcnt
; /* 2s complement of buffer size in low 15 bits.
151 * Receive terminal count interrupt enable in
154 volatile u16 mcnt
; /* Message byte count (15 bits) */
157 /* Convert a length into the 15 bit 2's complement */
158 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
159 /* Since we need to set the high bit to enable the completion interrupt this
160 * can be made a lot simpler
162 #define cnv_bcnt(len) (-(len))
164 /* Status and config bits for the above */
165 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
166 #define TX_STP 0x02 /* Tx: start of packet */
167 #define TX_ENP 0x01 /* Tx: end of packet */
168 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
169 #define RX_FRAM 0x20 /* Rx: framing error */
170 #define RX_OFLO 0x10 /* Rx: overflow error */
171 #define RX_CRC 0x08 /* Rx: CRC error */
172 #define RX_HBUF 0x04 /* Rx: buffer error */
173 #define RX_STP 0x02 /* Rx: start of packet */
174 #define RX_ENP 0x01 /* Rx: end of packet */
176 /* Interrupts from the card are caused by various events which are presented
177 * in a circular buffer as several events may be processed on one physical int
179 #define MAX_CIRBUFF 32
182 u8 rdindex
; /* read, then increment and wrap */
183 u8 wrindex
; /* write, then increment and wrap */
184 u8 evntbuff
[MAX_CIRBUFF
];
187 /* Interrupt event codes.
188 * Where appropriate the two low order bits indicate the port number
190 #define CTLA_CHG 0x18 /* Control signal changed */
191 #define CTLB_CHG 0x19
192 #define CTLC_CHG 0x1A
193 #define CTLD_CHG 0x1B
195 #define INIT_CPLT 0x20 /* Initialisation complete */
196 #define INIT_FAIL 0x21 /* Initialisation failed */
198 #define ABTA_SENT 0x24 /* Abort sent */
199 #define ABTB_SENT 0x25
200 #define ABTC_SENT 0x26
201 #define ABTD_SENT 0x27
203 #define TXA_UNDF 0x28 /* Transmission underflow */
204 #define TXB_UNDF 0x29
205 #define TXC_UNDF 0x2A
206 #define TXD_UNDF 0x2B
211 #define TE1_ALMA 0x30
213 /* Port physical configuration. See farsync.h for field values */
215 u16 lineInterface
; /* Physical interface type */
216 u8 x25op
; /* Unused at present */
217 u8 internalClock
; /* 1 => internal clock, 0 => external */
218 u8 transparentMode
; /* 1 => on, 0 => off */
219 u8 invertClock
; /* 0 => normal, 1 => inverted */
220 u8 padBytes
[6]; /* Padding */
221 u32 lineSpeed
; /* Speed in bps */
224 /* TE1 port physical configuration */
248 u32 receiveBufferDelay
;
249 u32 framingErrorCount
;
250 u32 codeViolationCount
;
255 u8 receiveRemoteAlarm
;
256 u8 alarmIndicationSignal
;
260 /* Finally sling all the above together into the shared memory structure.
261 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
262 * evolving under NT for some time so I guess we're stuck with it.
263 * The structure starts at offset SMC_BASE.
264 * See farsync.h for some field values.
267 /* DMA descriptor rings */
268 struct rxdesc rxDescrRing
[FST_MAX_PORTS
][NUM_RX_BUFFER
];
269 struct txdesc txDescrRing
[FST_MAX_PORTS
][NUM_TX_BUFFER
];
271 /* Obsolete small buffers */
272 u8 smallRxBuffer
[FST_MAX_PORTS
][NUM_RX_BUFFER
][LEN_SMALL_RX_BUFFER
];
273 u8 smallTxBuffer
[FST_MAX_PORTS
][NUM_TX_BUFFER
][LEN_SMALL_TX_BUFFER
];
275 u8 taskStatus
; /* 0x00 => initialising, 0x01 => running,
279 u8 interruptHandshake
; /* Set to 0x01 by adapter to signal interrupt,
280 * set to 0xEE by host to acknowledge interrupt
283 u16 smcVersion
; /* Must match SMC_VERSION */
285 u32 smcFirmwareVersion
; /* 0xIIVVRRBB where II = product ID, VV = major
286 * version, RR = revision and BB = build
289 u16 txa_done
; /* Obsolete completion flags */
298 u16 mailbox
[4]; /* Diagnostics mailbox. Not used */
300 struct cirbuff interruptEvent
; /* interrupt causes */
302 u32 v24IpSts
[FST_MAX_PORTS
]; /* V.24 control input status */
303 u32 v24OpSts
[FST_MAX_PORTS
]; /* V.24 control output status */
305 struct port_cfg portConfig
[FST_MAX_PORTS
];
307 u16 clockStatus
[FST_MAX_PORTS
]; /* lsb: 0=> present, 1=> absent */
309 u16 cableStatus
; /* lsb: 0=> present, 1=> absent */
311 u16 txDescrIndex
[FST_MAX_PORTS
]; /* transmit descriptor ring index */
312 u16 rxDescrIndex
[FST_MAX_PORTS
]; /* receive descriptor ring index */
314 u16 portMailbox
[FST_MAX_PORTS
][2]; /* command, modifier */
315 u16 cardMailbox
[4]; /* Not used */
317 /* Number of times the card thinks the host has
318 * missed an interrupt by not acknowledging
319 * within 2mS (I guess NT has problems)
321 u32 interruptRetryCount
;
323 /* Driver private data used as an ID. We'll not
324 * use this as I'd rather keep such things
325 * in main memory rather than on the PCI bus
327 u32 portHandle
[FST_MAX_PORTS
];
329 /* Count of Tx underflows for stats */
330 u32 transmitBufferUnderflow
[FST_MAX_PORTS
];
332 /* Debounced V.24 control input status */
333 u32 v24DebouncedSts
[FST_MAX_PORTS
];
335 /* Adapter debounce timers. Don't touch */
336 u32 ctsTimer
[FST_MAX_PORTS
];
337 u32 ctsTimerRun
[FST_MAX_PORTS
];
338 u32 dcdTimer
[FST_MAX_PORTS
];
339 u32 dcdTimerRun
[FST_MAX_PORTS
];
341 u32 numberOfPorts
; /* Number of ports detected at startup */
345 u16 cardMode
; /* Bit-mask to enable features:
346 * Bit 0: 1 enables LED identify mode
349 u16 portScheduleOffset
;
351 struct su_config suConfig
; /* TE1 Bits */
352 struct su_status suStatus
;
354 u32 endOfSmcSignature
; /* endOfSmcSignature MUST be the last member of
355 * the structure and marks the end of shared
356 * memory. Adapter code initializes it as
361 /* endOfSmcSignature value */
362 #define END_SIG 0x12345678
364 /* Mailbox values. (portMailbox) */
365 #define NOP 0 /* No operation */
366 #define ACK 1 /* Positive acknowledgement to PC driver */
367 #define NAK 2 /* Negative acknowledgement to PC driver */
368 #define STARTPORT 3 /* Start an HDLC port */
369 #define STOPPORT 4 /* Stop an HDLC port */
370 #define ABORTTX 5 /* Abort the transmitter for a port */
371 #define SETV24O 6 /* Set V24 outputs */
373 /* PLX Chip Register Offsets */
374 #define CNTRL_9052 0x50 /* Control Register */
375 #define CNTRL_9054 0x6c /* Control Register */
377 #define INTCSR_9052 0x4c /* Interrupt control/status register */
378 #define INTCSR_9054 0x68 /* Interrupt control/status register */
380 /* 9054 DMA Registers */
382 * Note that we will be using DMA Channel 0 for copying rx data
383 * and Channel 1 for copying tx data
385 #define DMAMODE0 0x80
386 #define DMAPADR0 0x84
387 #define DMALADR0 0x88
390 #define DMAMODE1 0x94
391 #define DMAPADR1 0x98
392 #define DMALADR1 0x9c
401 #define DMAMARBR 0xac
403 #define FST_MIN_DMA_LEN 64
404 #define FST_RX_DMA_INT 0x01
405 #define FST_TX_DMA_INT 0x02
406 #define FST_CARD_INT 0x04
408 /* Larger buffers are positioned in memory at offset BFM_BASE */
410 u8 txBuffer
[FST_MAX_PORTS
][NUM_TX_BUFFER
][LEN_TX_BUFFER
];
411 u8 rxBuffer
[FST_MAX_PORTS
][NUM_RX_BUFFER
][LEN_RX_BUFFER
];
414 /* Calculate offset of a buffer object within the shared memory window */
415 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
419 /* Device driver private information
420 * =================================
422 /* Per port (line or channel) information
424 struct fst_port_info
{
425 struct net_device
*dev
; /* Device struct - must be first */
426 struct fst_card_info
*card
; /* Card we're associated with */
427 int index
; /* Port index on the card */
428 int hwif
; /* Line hardware (lineInterface copy) */
429 int run
; /* Port is running */
430 int mode
; /* Normal or FarSync raw */
431 int rxpos
; /* Next Rx buffer to use */
432 int txpos
; /* Next Tx buffer to use */
433 int txipos
; /* Next Tx buffer to check for free */
434 int start
; /* Indication of start/stop to network */
436 * A sixteen entry transmit queue
438 int txqs
; /* index to get next buffer to tx */
439 int txqe
; /* index to queue next packet */
440 struct sk_buff
*txq
[FST_TXQ_DEPTH
]; /* The queue */
444 /* Per card information
446 struct fst_card_info
{
447 char __iomem
*mem
; /* Card memory mapped to kernel space */
448 char __iomem
*ctlmem
; /* Control memory for PCI cards */
449 unsigned int phys_mem
; /* Physical memory window address */
450 unsigned int phys_ctlmem
; /* Physical control memory address */
451 unsigned int irq
; /* Interrupt request line number */
452 unsigned int nports
; /* Number of serial ports */
453 unsigned int type
; /* Type index of card */
454 unsigned int state
; /* State of card */
455 spinlock_t card_lock
; /* Lock for SMP access */
456 unsigned short pci_conf
; /* PCI card config in I/O space */
458 struct fst_port_info ports
[FST_MAX_PORTS
];
459 struct pci_dev
*device
; /* Information about the pci device */
460 int card_no
; /* Inst of the card on the system */
461 int family
; /* TxP or TxU */
462 int dmarx_in_progress
;
463 int dmatx_in_progress
;
464 unsigned long int_count
;
465 unsigned long int_time_ave
;
466 void *rx_dma_handle_host
;
467 dma_addr_t rx_dma_handle_card
;
468 void *tx_dma_handle_host
;
469 dma_addr_t tx_dma_handle_card
;
470 struct sk_buff
*dma_skb_rx
;
471 struct fst_port_info
*dma_port_rx
;
472 struct fst_port_info
*dma_port_tx
;
479 /* Convert an HDLC device pointer into a port info pointer and similar */
480 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
481 #define port_to_dev(P) ((P)->dev)
485 * Shared memory window access macros
487 * We have a nice memory based structure above, which could be directly
488 * mapped on i386 but might not work on other architectures unless we use
489 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
490 * physical offsets so we have to convert. The only saving grace is that
491 * this should all collapse back to a simple indirection eventually.
493 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
495 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
496 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
497 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
499 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
500 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
501 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
508 static int fst_debug_mask
= { FST_DEBUG
};
510 /* Most common debug activity is to print something if the corresponding bit
511 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
512 * support variable numbers of macro parameters. The inverted if prevents us
513 * eating someone else's else clause.
515 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \
518 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A )
521 #define dbg(X...) /* NOP */
524 /* Printing short cuts
526 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A )
527 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A )
528 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A )
531 * PCI ID lookup table
533 static struct pci_device_id fst_pci_dev_id
[] __devinitdata
= {
534 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T2P
, PCI_ANY_ID
,
535 PCI_ANY_ID
, 0, 0, FST_TYPE_T2P
},
537 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T4P
, PCI_ANY_ID
,
538 PCI_ANY_ID
, 0, 0, FST_TYPE_T4P
},
540 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T1U
, PCI_ANY_ID
,
541 PCI_ANY_ID
, 0, 0, FST_TYPE_T1U
},
543 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T2U
, PCI_ANY_ID
,
544 PCI_ANY_ID
, 0, 0, FST_TYPE_T2U
},
546 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_T4U
, PCI_ANY_ID
,
547 PCI_ANY_ID
, 0, 0, FST_TYPE_T4U
},
549 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_TE1
, PCI_ANY_ID
,
550 PCI_ANY_ID
, 0, 0, FST_TYPE_TE1
},
552 {PCI_VENDOR_ID_FARSITE
, PCI_DEVICE_ID_FARSITE_TE1C
, PCI_ANY_ID
,
553 PCI_ANY_ID
, 0, 0, FST_TYPE_TE1
},
557 MODULE_DEVICE_TABLE(pci
, fst_pci_dev_id
);
560 * Device Driver Work Queues
562 * So that we don't spend too much time processing events in the
563 * Interrupt Service routine, we will declare a work queue per Card
564 * and make the ISR schedule a task in the queue for later execution.
565 * In the 2.4 Kernel we used to use the immediate queue for BH's
566 * Now that they are gone, tasklets seem to be much better than work
570 static void do_bottom_half_tx(struct fst_card_info
*card
);
571 static void do_bottom_half_rx(struct fst_card_info
*card
);
572 static void fst_process_tx_work_q(unsigned long work_q
);
573 static void fst_process_int_work_q(unsigned long work_q
);
575 DECLARE_TASKLET(fst_tx_task
, fst_process_tx_work_q
, 0);
576 DECLARE_TASKLET(fst_int_task
, fst_process_int_work_q
, 0);
578 struct fst_card_info
*fst_card_array
[FST_MAX_CARDS
];
579 spinlock_t fst_work_q_lock
;
584 fst_q_work_item(u64
* queue
, int card_index
)
590 * Grab the queue exclusively
592 spin_lock_irqsave(&fst_work_q_lock
, flags
);
595 * Making an entry in the queue is simply a matter of setting
596 * a bit for the card indicating that there is work to do in the
597 * bottom half for the card. Note the limitation of 64 cards.
598 * That ought to be enough
600 mask
= 1 << card_index
;
602 spin_unlock_irqrestore(&fst_work_q_lock
, flags
);
606 fst_process_tx_work_q(unsigned long /*void **/work_q
)
613 * Grab the queue exclusively
615 dbg(DBG_TX
, "fst_process_tx_work_q\n");
616 spin_lock_irqsave(&fst_work_q_lock
, flags
);
617 work_txq
= fst_work_txq
;
619 spin_unlock_irqrestore(&fst_work_q_lock
, flags
);
622 * Call the bottom half for each card with work waiting
624 for (i
= 0; i
< FST_MAX_CARDS
; i
++) {
625 if (work_txq
& 0x01) {
626 if (fst_card_array
[i
] != NULL
) {
627 dbg(DBG_TX
, "Calling tx bh for card %d\n", i
);
628 do_bottom_half_tx(fst_card_array
[i
]);
631 work_txq
= work_txq
>> 1;
636 fst_process_int_work_q(unsigned long /*void **/work_q
)
643 * Grab the queue exclusively
645 dbg(DBG_INTR
, "fst_process_int_work_q\n");
646 spin_lock_irqsave(&fst_work_q_lock
, flags
);
647 work_intq
= fst_work_intq
;
649 spin_unlock_irqrestore(&fst_work_q_lock
, flags
);
652 * Call the bottom half for each card with work waiting
654 for (i
= 0; i
< FST_MAX_CARDS
; i
++) {
655 if (work_intq
& 0x01) {
656 if (fst_card_array
[i
] != NULL
) {
658 "Calling rx & tx bh for card %d\n", i
);
659 do_bottom_half_rx(fst_card_array
[i
]);
660 do_bottom_half_tx(fst_card_array
[i
]);
663 work_intq
= work_intq
>> 1;
667 /* Card control functions
668 * ======================
670 /* Place the processor in reset state
672 * Used to be a simple write to card control space but a glitch in the latest
673 * AMD Am186CH processor means that we now have to do it by asserting and de-
674 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
675 * at offset 9052_CNTRL. Note the updates for the TXU.
678 fst_cpureset(struct fst_card_info
*card
)
680 unsigned char interrupt_line_register
;
681 unsigned long j
= jiffies
+ 1;
684 if (card
->family
== FST_FAMILY_TXU
) {
685 if (pci_read_config_byte
686 (card
->device
, PCI_INTERRUPT_LINE
, &interrupt_line_register
)) {
688 "Error in reading interrupt line register\n");
691 * Assert PLX software reset and Am186 hardware reset
692 * and then deassert the PLX software reset but 186 still in reset
694 outw(0x440f, card
->pci_conf
+ CNTRL_9054
+ 2);
695 outw(0x040f, card
->pci_conf
+ CNTRL_9054
+ 2);
697 * We are delaying here to allow the 9054 to reset itself
702 outw(0x240f, card
->pci_conf
+ CNTRL_9054
+ 2);
704 * We are delaying here to allow the 9054 to reload its eeprom
709 outw(0x040f, card
->pci_conf
+ CNTRL_9054
+ 2);
711 if (pci_write_config_byte
712 (card
->device
, PCI_INTERRUPT_LINE
, interrupt_line_register
)) {
714 "Error in writing interrupt line register\n");
718 regval
= inl(card
->pci_conf
+ CNTRL_9052
);
720 outl(regval
| 0x40000000, card
->pci_conf
+ CNTRL_9052
);
721 outl(regval
& ~0x40000000, card
->pci_conf
+ CNTRL_9052
);
725 /* Release the processor from reset
728 fst_cpurelease(struct fst_card_info
*card
)
730 if (card
->family
== FST_FAMILY_TXU
) {
732 * Force posted writes to complete
734 (void) readb(card
->mem
);
737 * Release LRESET DO = 1
738 * Then release Local Hold, DO = 1
740 outw(0x040e, card
->pci_conf
+ CNTRL_9054
+ 2);
741 outw(0x040f, card
->pci_conf
+ CNTRL_9054
+ 2);
743 (void) readb(card
->ctlmem
);
747 /* Clear the cards interrupt flag
750 fst_clear_intr(struct fst_card_info
*card
)
752 if (card
->family
== FST_FAMILY_TXU
) {
753 (void) readb(card
->ctlmem
);
755 /* Poke the appropriate PLX chip register (same as enabling interrupts)
757 outw(0x0543, card
->pci_conf
+ INTCSR_9052
);
761 /* Enable card interrupts
764 fst_enable_intr(struct fst_card_info
*card
)
766 if (card
->family
== FST_FAMILY_TXU
) {
767 outl(0x0f0c0900, card
->pci_conf
+ INTCSR_9054
);
769 outw(0x0543, card
->pci_conf
+ INTCSR_9052
);
773 /* Disable card interrupts
776 fst_disable_intr(struct fst_card_info
*card
)
778 if (card
->family
== FST_FAMILY_TXU
) {
779 outl(0x00000000, card
->pci_conf
+ INTCSR_9054
);
781 outw(0x0000, card
->pci_conf
+ INTCSR_9052
);
785 /* Process the result of trying to pass a received frame up the stack
788 fst_process_rx_status(int rx_status
, char *name
)
801 dbg(DBG_ASS
, "%s: Receive Low Congestion\n", name
);
807 dbg(DBG_ASS
, "%s: Receive Moderate Congestion\n", name
);
813 dbg(DBG_ASS
, "%s: Receive High Congestion\n", name
);
819 dbg(DBG_ASS
, "%s: Received packet dropped\n", name
);
825 /* Initilaise DMA for PLX 9054
828 fst_init_dma(struct fst_card_info
*card
)
831 * This is only required for the PLX 9054
833 if (card
->family
== FST_FAMILY_TXU
) {
834 pci_set_master(card
->device
);
835 outl(0x00020441, card
->pci_conf
+ DMAMODE0
);
836 outl(0x00020441, card
->pci_conf
+ DMAMODE1
);
837 outl(0x0, card
->pci_conf
+ DMATHR
);
841 /* Tx dma complete interrupt
844 fst_tx_dma_complete(struct fst_card_info
*card
, struct fst_port_info
*port
,
847 struct net_device
*dev
= port_to_dev(port
);
848 struct net_device_stats
*stats
= hdlc_stats(dev
);
851 * Everything is now set, just tell the card to go
853 dbg(DBG_TX
, "fst_tx_dma_complete\n");
854 FST_WRB(card
, txDescrRing
[port
->index
][txpos
].bits
,
855 DMA_OWN
| TX_STP
| TX_ENP
);
857 stats
->tx_bytes
+= len
;
858 dev
->trans_start
= jiffies
;
862 * Mark it for our own raw sockets interface
864 static unsigned short farsync_type_trans(struct sk_buff
*skb
,
865 struct net_device
*dev
)
868 skb
->mac
.raw
= skb
->data
;
869 skb
->pkt_type
= PACKET_HOST
;
870 return htons(ETH_P_CUST
);
873 /* Rx dma complete interrupt
876 fst_rx_dma_complete(struct fst_card_info
*card
, struct fst_port_info
*port
,
877 int len
, struct sk_buff
*skb
, int rxp
)
879 struct net_device
*dev
= port_to_dev(port
);
880 struct net_device_stats
*stats
= hdlc_stats(dev
);
884 dbg(DBG_TX
, "fst_rx_dma_complete\n");
886 memcpy(skb_put(skb
, len
), card
->rx_dma_handle_host
, len
);
888 /* Reset buffer descriptor */
889 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
893 stats
->rx_bytes
+= len
;
896 dbg(DBG_RX
, "Pushing the frame up the stack\n");
897 if (port
->mode
== FST_RAW
)
898 skb
->protocol
= farsync_type_trans(skb
, dev
);
900 skb
->protocol
= hdlc_type_trans(skb
, dev
);
901 rx_status
= netif_rx(skb
);
902 fst_process_rx_status(rx_status
, port_to_dev(port
)->name
);
903 if (rx_status
== NET_RX_DROP
)
905 dev
->last_rx
= jiffies
;
909 * Receive a frame through the DMA
912 fst_rx_dma(struct fst_card_info
*card
, unsigned char *skb
,
913 unsigned char *mem
, int len
)
916 * This routine will setup the DMA and start it
919 dbg(DBG_RX
, "In fst_rx_dma %p %p %d\n", skb
, mem
, len
);
920 if (card
->dmarx_in_progress
) {
921 dbg(DBG_ASS
, "In fst_rx_dma while dma in progress\n");
924 outl((unsigned long) skb
, card
->pci_conf
+ DMAPADR0
); /* Copy to here */
925 outl((unsigned long) mem
, card
->pci_conf
+ DMALADR0
); /* from here */
926 outl(len
, card
->pci_conf
+ DMASIZ0
); /* for this length */
927 outl(0x00000000c, card
->pci_conf
+ DMADPR0
); /* In this direction */
930 * We use the dmarx_in_progress flag to flag the channel as busy
932 card
->dmarx_in_progress
= 1;
933 outb(0x03, card
->pci_conf
+ DMACSR0
); /* Start the transfer */
937 * Send a frame through the DMA
940 fst_tx_dma(struct fst_card_info
*card
, unsigned char *skb
,
941 unsigned char *mem
, int len
)
944 * This routine will setup the DMA and start it.
947 dbg(DBG_TX
, "In fst_tx_dma %p %p %d\n", skb
, mem
, len
);
948 if (card
->dmatx_in_progress
) {
949 dbg(DBG_ASS
, "In fst_tx_dma while dma in progress\n");
952 outl((unsigned long) skb
, card
->pci_conf
+ DMAPADR1
); /* Copy from here */
953 outl((unsigned long) mem
, card
->pci_conf
+ DMALADR1
); /* to here */
954 outl(len
, card
->pci_conf
+ DMASIZ1
); /* for this length */
955 outl(0x000000004, card
->pci_conf
+ DMADPR1
); /* In this direction */
958 * We use the dmatx_in_progress to flag the channel as busy
960 card
->dmatx_in_progress
= 1;
961 outb(0x03, card
->pci_conf
+ DMACSR1
); /* Start the transfer */
964 /* Issue a Mailbox command for a port.
965 * Note we issue them on a fire and forget basis, not expecting to see an
966 * error and not waiting for completion.
969 fst_issue_cmd(struct fst_port_info
*port
, unsigned short cmd
)
971 struct fst_card_info
*card
;
972 unsigned short mbval
;
977 spin_lock_irqsave(&card
->card_lock
, flags
);
978 mbval
= FST_RDW(card
, portMailbox
[port
->index
][0]);
981 /* Wait for any previous command to complete */
982 while (mbval
> NAK
) {
983 spin_unlock_irqrestore(&card
->card_lock
, flags
);
984 set_current_state(TASK_UNINTERRUPTIBLE
);
986 spin_lock_irqsave(&card
->card_lock
, flags
);
988 if (++safety
> 2000) {
989 printk_err("Mailbox safety timeout\n");
993 mbval
= FST_RDW(card
, portMailbox
[port
->index
][0]);
996 dbg(DBG_CMD
, "Mailbox clear after %d jiffies\n", safety
);
999 dbg(DBG_CMD
, "issue_cmd: previous command was NAK'd\n");
1002 FST_WRW(card
, portMailbox
[port
->index
][0], cmd
);
1004 if (cmd
== ABORTTX
|| cmd
== STARTPORT
) {
1010 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1013 /* Port output signals control
1016 fst_op_raise(struct fst_port_info
*port
, unsigned int outputs
)
1018 outputs
|= FST_RDL(port
->card
, v24OpSts
[port
->index
]);
1019 FST_WRL(port
->card
, v24OpSts
[port
->index
], outputs
);
1022 fst_issue_cmd(port
, SETV24O
);
1026 fst_op_lower(struct fst_port_info
*port
, unsigned int outputs
)
1028 outputs
= ~outputs
& FST_RDL(port
->card
, v24OpSts
[port
->index
]);
1029 FST_WRL(port
->card
, v24OpSts
[port
->index
], outputs
);
1032 fst_issue_cmd(port
, SETV24O
);
1036 * Setup port Rx buffers
1039 fst_rx_config(struct fst_port_info
*port
)
1043 unsigned int offset
;
1044 unsigned long flags
;
1045 struct fst_card_info
*card
;
1049 spin_lock_irqsave(&card
->card_lock
, flags
);
1050 for (i
= 0; i
< NUM_RX_BUFFER
; i
++) {
1051 offset
= BUF_OFFSET(rxBuffer
[pi
][i
][0]);
1053 FST_WRW(card
, rxDescrRing
[pi
][i
].ladr
, (u16
) offset
);
1054 FST_WRB(card
, rxDescrRing
[pi
][i
].hadr
, (u8
) (offset
>> 16));
1055 FST_WRW(card
, rxDescrRing
[pi
][i
].bcnt
, cnv_bcnt(LEN_RX_BUFFER
));
1056 FST_WRW(card
, rxDescrRing
[pi
][i
].mcnt
, LEN_RX_BUFFER
);
1057 FST_WRB(card
, rxDescrRing
[pi
][i
].bits
, DMA_OWN
);
1060 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1064 * Setup port Tx buffers
1067 fst_tx_config(struct fst_port_info
*port
)
1071 unsigned int offset
;
1072 unsigned long flags
;
1073 struct fst_card_info
*card
;
1077 spin_lock_irqsave(&card
->card_lock
, flags
);
1078 for (i
= 0; i
< NUM_TX_BUFFER
; i
++) {
1079 offset
= BUF_OFFSET(txBuffer
[pi
][i
][0]);
1081 FST_WRW(card
, txDescrRing
[pi
][i
].ladr
, (u16
) offset
);
1082 FST_WRB(card
, txDescrRing
[pi
][i
].hadr
, (u8
) (offset
>> 16));
1083 FST_WRW(card
, txDescrRing
[pi
][i
].bcnt
, 0);
1084 FST_WRB(card
, txDescrRing
[pi
][i
].bits
, 0);
1089 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1092 /* TE1 Alarm change interrupt event
1095 fst_intr_te1_alarm(struct fst_card_info
*card
, struct fst_port_info
*port
)
1101 los
= FST_RDB(card
, suStatus
.lossOfSignal
);
1102 rra
= FST_RDB(card
, suStatus
.receiveRemoteAlarm
);
1103 ais
= FST_RDB(card
, suStatus
.alarmIndicationSignal
);
1109 if (netif_carrier_ok(port_to_dev(port
))) {
1110 dbg(DBG_INTR
, "Net carrier off\n");
1111 netif_carrier_off(port_to_dev(port
));
1117 if (!netif_carrier_ok(port_to_dev(port
))) {
1118 dbg(DBG_INTR
, "Net carrier on\n");
1119 netif_carrier_on(port_to_dev(port
));
1124 dbg(DBG_INTR
, "Assert LOS Alarm\n");
1126 dbg(DBG_INTR
, "De-assert LOS Alarm\n");
1128 dbg(DBG_INTR
, "Assert RRA Alarm\n");
1130 dbg(DBG_INTR
, "De-assert RRA Alarm\n");
1133 dbg(DBG_INTR
, "Assert AIS Alarm\n");
1135 dbg(DBG_INTR
, "De-assert AIS Alarm\n");
1138 /* Control signal change interrupt event
1141 fst_intr_ctlchg(struct fst_card_info
*card
, struct fst_port_info
*port
)
1145 signals
= FST_RDL(card
, v24DebouncedSts
[port
->index
]);
1147 if (signals
& (((port
->hwif
== X21
) || (port
->hwif
== X21D
))
1148 ? IPSTS_INDICATE
: IPSTS_DCD
)) {
1149 if (!netif_carrier_ok(port_to_dev(port
))) {
1150 dbg(DBG_INTR
, "DCD active\n");
1151 netif_carrier_on(port_to_dev(port
));
1154 if (netif_carrier_ok(port_to_dev(port
))) {
1155 dbg(DBG_INTR
, "DCD lost\n");
1156 netif_carrier_off(port_to_dev(port
));
1164 fst_log_rx_error(struct fst_card_info
*card
, struct fst_port_info
*port
,
1165 unsigned char dmabits
, int rxp
, unsigned short len
)
1167 struct net_device
*dev
= port_to_dev(port
);
1168 struct net_device_stats
*stats
= hdlc_stats(dev
);
1171 * Increment the appropriate error counter
1174 if (dmabits
& RX_OFLO
) {
1175 stats
->rx_fifo_errors
++;
1176 dbg(DBG_ASS
, "Rx fifo error on card %d port %d buffer %d\n",
1177 card
->card_no
, port
->index
, rxp
);
1179 if (dmabits
& RX_CRC
) {
1180 stats
->rx_crc_errors
++;
1181 dbg(DBG_ASS
, "Rx crc error on card %d port %d\n",
1182 card
->card_no
, port
->index
);
1184 if (dmabits
& RX_FRAM
) {
1185 stats
->rx_frame_errors
++;
1186 dbg(DBG_ASS
, "Rx frame error on card %d port %d\n",
1187 card
->card_no
, port
->index
);
1189 if (dmabits
== (RX_STP
| RX_ENP
)) {
1190 stats
->rx_length_errors
++;
1191 dbg(DBG_ASS
, "Rx length error (%d) on card %d port %d\n",
1192 len
, card
->card_no
, port
->index
);
1196 /* Rx Error Recovery
1199 fst_recover_rx_error(struct fst_card_info
*card
, struct fst_port_info
*port
,
1200 unsigned char dmabits
, int rxp
, unsigned short len
)
1207 * Discard buffer descriptors until we see the start of the
1208 * next frame. Note that for long frames this could be in
1209 * a subsequent interrupt.
1212 while ((dmabits
& (DMA_OWN
| RX_STP
)) == 0) {
1213 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1214 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1215 if (++i
> NUM_RX_BUFFER
) {
1216 dbg(DBG_ASS
, "intr_rx: Discarding more bufs"
1220 dmabits
= FST_RDB(card
, rxDescrRing
[pi
][rxp
].bits
);
1221 dbg(DBG_ASS
, "DMA Bits of next buffer was %x\n", dmabits
);
1223 dbg(DBG_ASS
, "There were %d subsequent buffers in error\n", i
);
1225 /* Discard the terminal buffer */
1226 if (!(dmabits
& DMA_OWN
)) {
1227 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1228 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1235 /* Rx complete interrupt
1238 fst_intr_rx(struct fst_card_info
*card
, struct fst_port_info
*port
)
1240 unsigned char dmabits
;
1245 struct sk_buff
*skb
;
1246 struct net_device
*dev
= port_to_dev(port
);
1247 struct net_device_stats
*stats
= hdlc_stats(dev
);
1249 /* Check we have a buffer to process */
1252 dmabits
= FST_RDB(card
, rxDescrRing
[pi
][rxp
].bits
);
1253 if (dmabits
& DMA_OWN
) {
1254 dbg(DBG_RX
| DBG_INTR
, "intr_rx: No buffer port %d pos %d\n",
1258 if (card
->dmarx_in_progress
) {
1262 /* Get buffer length */
1263 len
= FST_RDW(card
, rxDescrRing
[pi
][rxp
].mcnt
);
1264 /* Discard the CRC */
1268 * This seems to happen on the TE1 interface sometimes
1269 * so throw the frame away and log the event.
1271 printk_err("Frame received with 0 length. Card %d Port %d\n",
1272 card
->card_no
, port
->index
);
1273 /* Return descriptor to card */
1274 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1276 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1281 /* Check buffer length and for other errors. We insist on one packet
1282 * in one buffer. This simplifies things greatly and since we've
1283 * allocated 8K it shouldn't be a real world limitation
1285 dbg(DBG_RX
, "intr_rx: %d,%d: flags %x len %d\n", pi
, rxp
, dmabits
, len
);
1286 if (dmabits
!= (RX_STP
| RX_ENP
) || len
> LEN_RX_BUFFER
- 2) {
1287 fst_log_rx_error(card
, port
, dmabits
, rxp
, len
);
1288 fst_recover_rx_error(card
, port
, dmabits
, rxp
, len
);
1293 if ((skb
= dev_alloc_skb(len
)) == NULL
) {
1294 dbg(DBG_RX
, "intr_rx: can't allocate buffer\n");
1296 stats
->rx_dropped
++;
1298 /* Return descriptor to card */
1299 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1301 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1307 * We know the length we need to receive, len.
1308 * It's not worth using the DMA for reads of less than
1312 if ((len
< FST_MIN_DMA_LEN
) || (card
->family
== FST_FAMILY_TXP
)) {
1313 memcpy_fromio(skb_put(skb
, len
),
1314 card
->mem
+ BUF_OFFSET(rxBuffer
[pi
][rxp
][0]),
1317 /* Reset buffer descriptor */
1318 FST_WRB(card
, rxDescrRing
[pi
][rxp
].bits
, DMA_OWN
);
1321 stats
->rx_packets
++;
1322 stats
->rx_bytes
+= len
;
1325 dbg(DBG_RX
, "Pushing frame up the stack\n");
1326 if (port
->mode
== FST_RAW
)
1327 skb
->protocol
= farsync_type_trans(skb
, dev
);
1329 skb
->protocol
= hdlc_type_trans(skb
, dev
);
1330 rx_status
= netif_rx(skb
);
1331 fst_process_rx_status(rx_status
, port_to_dev(port
)->name
);
1332 if (rx_status
== NET_RX_DROP
) {
1333 stats
->rx_dropped
++;
1335 dev
->last_rx
= jiffies
;
1337 card
->dma_skb_rx
= skb
;
1338 card
->dma_port_rx
= port
;
1339 card
->dma_len_rx
= len
;
1340 card
->dma_rxpos
= rxp
;
1341 fst_rx_dma(card
, (char *) card
->rx_dma_handle_card
,
1342 (char *) BUF_OFFSET(rxBuffer
[pi
][rxp
][0]), len
);
1344 if (rxp
!= port
->rxpos
) {
1345 dbg(DBG_ASS
, "About to increment rxpos by more than 1\n");
1346 dbg(DBG_ASS
, "rxp = %d rxpos = %d\n", rxp
, port
->rxpos
);
1348 rxp
= (rxp
+1) % NUM_RX_BUFFER
;
1353 * The bottom halfs to the ISR
1358 do_bottom_half_tx(struct fst_card_info
*card
)
1360 struct fst_port_info
*port
;
1363 struct sk_buff
*skb
;
1364 unsigned long flags
;
1365 struct net_device
*dev
;
1366 struct net_device_stats
*stats
;
1369 * Find a free buffer for the transmit
1370 * Step through each port on this card
1373 dbg(DBG_TX
, "do_bottom_half_tx\n");
1374 for (pi
= 0, port
= card
->ports
; pi
< card
->nports
; pi
++, port
++) {
1378 dev
= port_to_dev(port
);
1379 stats
= hdlc_stats(dev
);
1381 (FST_RDB(card
, txDescrRing
[pi
][port
->txpos
].bits
) &
1383 && !(card
->dmatx_in_progress
)) {
1385 * There doesn't seem to be a txdone event per-se
1386 * We seem to have to deduce it, by checking the DMA_OWN
1387 * bit on the next buffer we think we can use
1389 spin_lock_irqsave(&card
->card_lock
, flags
);
1390 if ((txq_length
= port
->txqe
- port
->txqs
) < 0) {
1392 * This is the case where one has wrapped and the
1393 * maths gives us a negative number
1395 txq_length
= txq_length
+ FST_TXQ_DEPTH
;
1397 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1398 if (txq_length
> 0) {
1400 * There is something to send
1402 spin_lock_irqsave(&card
->card_lock
, flags
);
1403 skb
= port
->txq
[port
->txqs
];
1405 if (port
->txqs
== FST_TXQ_DEPTH
) {
1408 spin_unlock_irqrestore(&card
->card_lock
, flags
);
1410 * copy the data and set the required indicators on the
1413 FST_WRW(card
, txDescrRing
[pi
][port
->txpos
].bcnt
,
1414 cnv_bcnt(skb
->len
));
1415 if ((skb
->len
< FST_MIN_DMA_LEN
)
1416 || (card
->family
== FST_FAMILY_TXP
)) {
1417 /* Enqueue the packet with normal io */
1418 memcpy_toio(card
->mem
+
1419 BUF_OFFSET(txBuffer
[pi
]
1422 skb
->data
, skb
->len
);
1424 txDescrRing
[pi
][port
->txpos
].
1426 DMA_OWN
| TX_STP
| TX_ENP
);
1427 stats
->tx_packets
++;
1428 stats
->tx_bytes
+= skb
->len
;
1429 dev
->trans_start
= jiffies
;
1431 /* Or do it through dma */
1432 memcpy(card
->tx_dma_handle_host
,
1433 skb
->data
, skb
->len
);
1434 card
->dma_port_tx
= port
;
1435 card
->dma_len_tx
= skb
->len
;
1436 card
->dma_txpos
= port
->txpos
;
1441 BUF_OFFSET(txBuffer
[pi
]
1445 if (++port
->txpos
>= NUM_TX_BUFFER
)
1448 * If we have flow control on, can we now release it?
1451 if (txq_length
< fst_txq_low
) {
1452 netif_wake_queue(port_to_dev
1460 * Nothing to send so break out of the while loop
1469 do_bottom_half_rx(struct fst_card_info
*card
)
1471 struct fst_port_info
*port
;
1475 /* Check for rx completions on all ports on this card */
1476 dbg(DBG_RX
, "do_bottom_half_rx\n");
1477 for (pi
= 0, port
= card
->ports
; pi
< card
->nports
; pi
++, port
++) {
1481 while (!(FST_RDB(card
, rxDescrRing
[pi
][port
->rxpos
].bits
)
1482 & DMA_OWN
) && !(card
->dmarx_in_progress
)) {
1483 if (rx_count
> fst_max_reads
) {
1485 * Don't spend forever in receive processing
1486 * Schedule another event
1488 fst_q_work_item(&fst_work_intq
, card
->card_no
);
1489 tasklet_schedule(&fst_int_task
);
1490 break; /* Leave the loop */
1492 fst_intr_rx(card
, port
);
1499 * The interrupt service routine
1500 * Dev_id is our fst_card_info pointer
1503 fst_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
1505 struct fst_card_info
*card
;
1506 struct fst_port_info
*port
;
1507 int rdidx
; /* Event buffer indices */
1509 int event
; /* Actual event for processing */
1510 unsigned int dma_intcsr
= 0;
1511 unsigned int do_card_interrupt
;
1512 unsigned int int_retry_count
;
1514 if ((card
= dev_id
) == NULL
) {
1515 dbg(DBG_INTR
, "intr: spurious %d\n", irq
);
1520 * Check to see if the interrupt was for this card
1522 * Note that the call to clear the interrupt is important
1524 dbg(DBG_INTR
, "intr: %d %p\n", irq
, card
);
1525 if (card
->state
!= FST_RUNNING
) {
1527 ("Interrupt received for card %d in a non running state (%d)\n",
1528 card
->card_no
, card
->state
);
1531 * It is possible to really be running, i.e. we have re-loaded
1533 * Clear and reprime the interrupt source
1535 fst_clear_intr(card
);
1539 /* Clear and reprime the interrupt source */
1540 fst_clear_intr(card
);
1543 * Is the interrupt for this card (handshake == 1)
1545 do_card_interrupt
= 0;
1546 if (FST_RDB(card
, interruptHandshake
) == 1) {
1547 do_card_interrupt
+= FST_CARD_INT
;
1548 /* Set the software acknowledge */
1549 FST_WRB(card
, interruptHandshake
, 0xEE);
1551 if (card
->family
== FST_FAMILY_TXU
) {
1553 * Is it a DMA Interrupt
1555 dma_intcsr
= inl(card
->pci_conf
+ INTCSR_9054
);
1556 if (dma_intcsr
& 0x00200000) {
1558 * DMA Channel 0 (Rx transfer complete)
1560 dbg(DBG_RX
, "DMA Rx xfer complete\n");
1561 outb(0x8, card
->pci_conf
+ DMACSR0
);
1562 fst_rx_dma_complete(card
, card
->dma_port_rx
,
1563 card
->dma_len_rx
, card
->dma_skb_rx
,
1565 card
->dmarx_in_progress
= 0;
1566 do_card_interrupt
+= FST_RX_DMA_INT
;
1568 if (dma_intcsr
& 0x00400000) {
1570 * DMA Channel 1 (Tx transfer complete)
1572 dbg(DBG_TX
, "DMA Tx xfer complete\n");
1573 outb(0x8, card
->pci_conf
+ DMACSR1
);
1574 fst_tx_dma_complete(card
, card
->dma_port_tx
,
1575 card
->dma_len_tx
, card
->dma_txpos
);
1576 card
->dmatx_in_progress
= 0;
1577 do_card_interrupt
+= FST_TX_DMA_INT
;
1582 * Have we been missing Interrupts
1584 int_retry_count
= FST_RDL(card
, interruptRetryCount
);
1585 if (int_retry_count
) {
1586 dbg(DBG_ASS
, "Card %d int_retry_count is %d\n",
1587 card
->card_no
, int_retry_count
);
1588 FST_WRL(card
, interruptRetryCount
, 0);
1591 if (!do_card_interrupt
) {
1595 /* Scehdule the bottom half of the ISR */
1596 fst_q_work_item(&fst_work_intq
, card
->card_no
);
1597 tasklet_schedule(&fst_int_task
);
1599 /* Drain the event queue */
1600 rdidx
= FST_RDB(card
, interruptEvent
.rdindex
) & 0x1f;
1601 wridx
= FST_RDB(card
, interruptEvent
.wrindex
) & 0x1f;
1602 while (rdidx
!= wridx
) {
1603 event
= FST_RDB(card
, interruptEvent
.evntbuff
[rdidx
]);
1604 port
= &card
->ports
[event
& 0x03];
1606 dbg(DBG_INTR
, "Processing Interrupt event: %x\n", event
);
1610 dbg(DBG_INTR
, "TE1 Alarm intr\n");
1612 fst_intr_te1_alarm(card
, port
);
1620 fst_intr_ctlchg(card
, port
);
1627 dbg(DBG_TX
, "Abort complete port %d\n", port
->index
);
1634 /* Difficult to see how we'd get this given that we
1635 * always load up the entire packet for DMA.
1637 dbg(DBG_TX
, "Tx underflow port %d\n", port
->index
);
1638 hdlc_stats(port_to_dev(port
))->tx_errors
++;
1639 hdlc_stats(port_to_dev(port
))->tx_fifo_errors
++;
1640 dbg(DBG_ASS
, "Tx underflow on card %d port %d\n",
1641 card
->card_no
, port
->index
);
1645 dbg(DBG_INIT
, "Card init OK intr\n");
1649 dbg(DBG_INIT
, "Card init FAILED intr\n");
1650 card
->state
= FST_IFAILED
;
1654 printk_err("intr: unknown card event %d. ignored\n",
1659 /* Bump and wrap the index */
1660 if (++rdidx
>= MAX_CIRBUFF
)
1663 FST_WRB(card
, interruptEvent
.rdindex
, rdidx
);
1667 /* Check that the shared memory configuration is one that we can handle
1668 * and that some basic parameters are correct
1671 check_started_ok(struct fst_card_info
*card
)
1675 /* Check structure version and end marker */
1676 if (FST_RDW(card
, smcVersion
) != SMC_VERSION
) {
1677 printk_err("Bad shared memory version %d expected %d\n",
1678 FST_RDW(card
, smcVersion
), SMC_VERSION
);
1679 card
->state
= FST_BADVERSION
;
1682 if (FST_RDL(card
, endOfSmcSignature
) != END_SIG
) {
1683 printk_err("Missing shared memory signature\n");
1684 card
->state
= FST_BADVERSION
;
1687 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1688 if ((i
= FST_RDB(card
, taskStatus
)) == 0x01) {
1689 card
->state
= FST_RUNNING
;
1690 } else if (i
== 0xFF) {
1691 printk_err("Firmware initialisation failed. Card halted\n");
1692 card
->state
= FST_HALTED
;
1694 } else if (i
!= 0x00) {
1695 printk_err("Unknown firmware status 0x%x\n", i
);
1696 card
->state
= FST_HALTED
;
1700 /* Finally check the number of ports reported by firmware against the
1701 * number we assumed at card detection. Should never happen with
1702 * existing firmware etc so we just report it for the moment.
1704 if (FST_RDL(card
, numberOfPorts
) != card
->nports
) {
1705 printk_warn("Port count mismatch on card %d."
1706 " Firmware thinks %d we say %d\n", card
->card_no
,
1707 FST_RDL(card
, numberOfPorts
), card
->nports
);
1712 set_conf_from_info(struct fst_card_info
*card
, struct fst_port_info
*port
,
1713 struct fstioc_info
*info
)
1716 unsigned char my_framing
;
1718 /* Set things according to the user set valid flags
1719 * Several of the old options have been invalidated/replaced by the
1720 * generic hdlc package.
1723 if (info
->valid
& FSTVAL_PROTO
) {
1724 if (info
->proto
== FST_RAW
)
1725 port
->mode
= FST_RAW
;
1727 port
->mode
= FST_GEN_HDLC
;
1730 if (info
->valid
& FSTVAL_CABLE
)
1733 if (info
->valid
& FSTVAL_SPEED
)
1736 if (info
->valid
& FSTVAL_PHASE
)
1737 FST_WRB(card
, portConfig
[port
->index
].invertClock
,
1739 if (info
->valid
& FSTVAL_MODE
)
1740 FST_WRW(card
, cardMode
, info
->cardMode
);
1741 if (info
->valid
& FSTVAL_TE1
) {
1742 FST_WRL(card
, suConfig
.dataRate
, info
->lineSpeed
);
1743 FST_WRB(card
, suConfig
.clocking
, info
->clockSource
);
1744 my_framing
= FRAMING_E1
;
1745 if (info
->framing
== E1
)
1746 my_framing
= FRAMING_E1
;
1747 if (info
->framing
== T1
)
1748 my_framing
= FRAMING_T1
;
1749 if (info
->framing
== J1
)
1750 my_framing
= FRAMING_J1
;
1751 FST_WRB(card
, suConfig
.framing
, my_framing
);
1752 FST_WRB(card
, suConfig
.structure
, info
->structure
);
1753 FST_WRB(card
, suConfig
.interface
, info
->interface
);
1754 FST_WRB(card
, suConfig
.coding
, info
->coding
);
1755 FST_WRB(card
, suConfig
.lineBuildOut
, info
->lineBuildOut
);
1756 FST_WRB(card
, suConfig
.equalizer
, info
->equalizer
);
1757 FST_WRB(card
, suConfig
.transparentMode
, info
->transparentMode
);
1758 FST_WRB(card
, suConfig
.loopMode
, info
->loopMode
);
1759 FST_WRB(card
, suConfig
.range
, info
->range
);
1760 FST_WRB(card
, suConfig
.txBufferMode
, info
->txBufferMode
);
1761 FST_WRB(card
, suConfig
.rxBufferMode
, info
->rxBufferMode
);
1762 FST_WRB(card
, suConfig
.startingSlot
, info
->startingSlot
);
1763 FST_WRB(card
, suConfig
.losThreshold
, info
->losThreshold
);
1765 FST_WRB(card
, suConfig
.enableIdleCode
, 1);
1767 FST_WRB(card
, suConfig
.enableIdleCode
, 0);
1768 FST_WRB(card
, suConfig
.idleCode
, info
->idleCode
);
1770 if (info
->valid
& FSTVAL_TE1
) {
1771 printk("Setting TE1 data\n");
1772 printk("Line Speed = %d\n", info
->lineSpeed
);
1773 printk("Start slot = %d\n", info
->startingSlot
);
1774 printk("Clock source = %d\n", info
->clockSource
);
1775 printk("Framing = %d\n", my_framing
);
1776 printk("Structure = %d\n", info
->structure
);
1777 printk("interface = %d\n", info
->interface
);
1778 printk("Coding = %d\n", info
->coding
);
1779 printk("Line build out = %d\n", info
->lineBuildOut
);
1780 printk("Equaliser = %d\n", info
->equalizer
);
1781 printk("Transparent mode = %d\n",
1782 info
->transparentMode
);
1783 printk("Loop mode = %d\n", info
->loopMode
);
1784 printk("Range = %d\n", info
->range
);
1785 printk("Tx Buffer mode = %d\n", info
->txBufferMode
);
1786 printk("Rx Buffer mode = %d\n", info
->rxBufferMode
);
1787 printk("LOS Threshold = %d\n", info
->losThreshold
);
1788 printk("Idle Code = %d\n", info
->idleCode
);
1793 if (info
->valid
& FSTVAL_DEBUG
) {
1794 fst_debug_mask
= info
->debug
;
1802 gather_conf_info(struct fst_card_info
*card
, struct fst_port_info
*port
,
1803 struct fstioc_info
*info
)
1807 memset(info
, 0, sizeof (struct fstioc_info
));
1810 info
->kernelVersion
= LINUX_VERSION_CODE
;
1811 info
->nports
= card
->nports
;
1812 info
->type
= card
->type
;
1813 info
->state
= card
->state
;
1814 info
->proto
= FST_GEN_HDLC
;
1817 info
->debug
= fst_debug_mask
;
1820 /* Only mark information as valid if card is running.
1821 * Copy the data anyway in case it is useful for diagnostics
1823 info
->valid
= ((card
->state
== FST_RUNNING
) ? FSTVAL_ALL
: FSTVAL_CARD
)
1829 info
->lineInterface
= FST_RDW(card
, portConfig
[i
].lineInterface
);
1830 info
->internalClock
= FST_RDB(card
, portConfig
[i
].internalClock
);
1831 info
->lineSpeed
= FST_RDL(card
, portConfig
[i
].lineSpeed
);
1832 info
->invertClock
= FST_RDB(card
, portConfig
[i
].invertClock
);
1833 info
->v24IpSts
= FST_RDL(card
, v24IpSts
[i
]);
1834 info
->v24OpSts
= FST_RDL(card
, v24OpSts
[i
]);
1835 info
->clockStatus
= FST_RDW(card
, clockStatus
[i
]);
1836 info
->cableStatus
= FST_RDW(card
, cableStatus
);
1837 info
->cardMode
= FST_RDW(card
, cardMode
);
1838 info
->smcFirmwareVersion
= FST_RDL(card
, smcFirmwareVersion
);
1841 * The T2U can report cable presence for both A or B
1842 * in bits 0 and 1 of cableStatus. See which port we are and
1845 if (card
->family
== FST_FAMILY_TXU
) {
1846 if (port
->index
== 0) {
1850 info
->cableStatus
= info
->cableStatus
& 1;
1855 info
->cableStatus
= info
->cableStatus
>> 1;
1856 info
->cableStatus
= info
->cableStatus
& 1;
1860 * Some additional bits if we are TE1
1862 if (card
->type
== FST_TYPE_TE1
) {
1863 info
->lineSpeed
= FST_RDL(card
, suConfig
.dataRate
);
1864 info
->clockSource
= FST_RDB(card
, suConfig
.clocking
);
1865 info
->framing
= FST_RDB(card
, suConfig
.framing
);
1866 info
->structure
= FST_RDB(card
, suConfig
.structure
);
1867 info
->interface
= FST_RDB(card
, suConfig
.interface
);
1868 info
->coding
= FST_RDB(card
, suConfig
.coding
);
1869 info
->lineBuildOut
= FST_RDB(card
, suConfig
.lineBuildOut
);
1870 info
->equalizer
= FST_RDB(card
, suConfig
.equalizer
);
1871 info
->loopMode
= FST_RDB(card
, suConfig
.loopMode
);
1872 info
->range
= FST_RDB(card
, suConfig
.range
);
1873 info
->txBufferMode
= FST_RDB(card
, suConfig
.txBufferMode
);
1874 info
->rxBufferMode
= FST_RDB(card
, suConfig
.rxBufferMode
);
1875 info
->startingSlot
= FST_RDB(card
, suConfig
.startingSlot
);
1876 info
->losThreshold
= FST_RDB(card
, suConfig
.losThreshold
);
1877 if (FST_RDB(card
, suConfig
.enableIdleCode
))
1878 info
->idleCode
= FST_RDB(card
, suConfig
.idleCode
);
1881 info
->receiveBufferDelay
=
1882 FST_RDL(card
, suStatus
.receiveBufferDelay
);
1883 info
->framingErrorCount
=
1884 FST_RDL(card
, suStatus
.framingErrorCount
);
1885 info
->codeViolationCount
=
1886 FST_RDL(card
, suStatus
.codeViolationCount
);
1887 info
->crcErrorCount
= FST_RDL(card
, suStatus
.crcErrorCount
);
1888 info
->lineAttenuation
= FST_RDL(card
, suStatus
.lineAttenuation
);
1889 info
->lossOfSignal
= FST_RDB(card
, suStatus
.lossOfSignal
);
1890 info
->receiveRemoteAlarm
=
1891 FST_RDB(card
, suStatus
.receiveRemoteAlarm
);
1892 info
->alarmIndicationSignal
=
1893 FST_RDB(card
, suStatus
.alarmIndicationSignal
);
1898 fst_set_iface(struct fst_card_info
*card
, struct fst_port_info
*port
,
1901 sync_serial_settings sync
;
1904 if (ifr
->ifr_settings
.size
!= sizeof (sync
)) {
1909 (&sync
, ifr
->ifr_settings
.ifs_ifsu
.sync
, sizeof (sync
))) {
1918 switch (ifr
->ifr_settings
.type
) {
1920 FST_WRW(card
, portConfig
[i
].lineInterface
, V35
);
1925 FST_WRW(card
, portConfig
[i
].lineInterface
, V24
);
1930 FST_WRW(card
, portConfig
[i
].lineInterface
, X21
);
1935 FST_WRW(card
, portConfig
[i
].lineInterface
, X21D
);
1940 FST_WRW(card
, portConfig
[i
].lineInterface
, T1
);
1945 FST_WRW(card
, portConfig
[i
].lineInterface
, E1
);
1949 case IF_IFACE_SYNC_SERIAL
:
1956 switch (sync
.clock_type
) {
1958 FST_WRB(card
, portConfig
[i
].internalClock
, EXTCLK
);
1962 FST_WRB(card
, portConfig
[i
].internalClock
, INTCLK
);
1968 FST_WRL(card
, portConfig
[i
].lineSpeed
, sync
.clock_rate
);
1973 fst_get_iface(struct fst_card_info
*card
, struct fst_port_info
*port
,
1976 sync_serial_settings sync
;
1979 /* First check what line type is set, we'll default to reporting X.21
1980 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1983 switch (port
->hwif
) {
1985 ifr
->ifr_settings
.type
= IF_IFACE_E1
;
1988 ifr
->ifr_settings
.type
= IF_IFACE_T1
;
1991 ifr
->ifr_settings
.type
= IF_IFACE_V35
;
1994 ifr
->ifr_settings
.type
= IF_IFACE_V24
;
1997 ifr
->ifr_settings
.type
= IF_IFACE_X21D
;
2001 ifr
->ifr_settings
.type
= IF_IFACE_X21
;
2004 if (ifr
->ifr_settings
.size
== 0) {
2005 return 0; /* only type requested */
2007 if (ifr
->ifr_settings
.size
< sizeof (sync
)) {
2012 sync
.clock_rate
= FST_RDL(card
, portConfig
[i
].lineSpeed
);
2013 /* Lucky card and linux use same encoding here */
2014 sync
.clock_type
= FST_RDB(card
, portConfig
[i
].internalClock
) ==
2015 INTCLK
? CLOCK_INT
: CLOCK_EXT
;
2018 if (copy_to_user(ifr
->ifr_settings
.ifs_ifsu
.sync
, &sync
, sizeof (sync
))) {
2022 ifr
->ifr_settings
.size
= sizeof (sync
);
2027 fst_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2029 struct fst_card_info
*card
;
2030 struct fst_port_info
*port
;
2031 struct fstioc_write wrthdr
;
2032 struct fstioc_info info
;
2033 unsigned long flags
;
2035 dbg(DBG_IOCTL
, "ioctl: %x, %p\n", cmd
, ifr
->ifr_data
);
2037 port
= dev_to_port(dev
);
2040 if (!capable(CAP_NET_ADMIN
))
2046 card
->state
= FST_RESET
;
2050 fst_cpurelease(card
);
2051 card
->state
= FST_STARTING
;
2054 case FSTWRITE
: /* Code write (download) */
2056 /* First copy in the header with the length and offset of data
2059 if (ifr
->ifr_data
== NULL
) {
2062 if (copy_from_user(&wrthdr
, ifr
->ifr_data
,
2063 sizeof (struct fstioc_write
))) {
2067 /* Sanity check the parameters. We don't support partial writes
2068 * when going over the top
2070 if (wrthdr
.size
> FST_MEMSIZE
|| wrthdr
.offset
> FST_MEMSIZE
2071 || wrthdr
.size
+ wrthdr
.offset
> FST_MEMSIZE
) {
2075 /* Now copy the data to the card.
2076 * This will probably break on some architectures.
2077 * I'll fix it when I have something to test on.
2079 if (copy_from_user(card
->mem
+ wrthdr
.offset
,
2080 ifr
->ifr_data
+ sizeof (struct fstioc_write
),
2085 /* Writes to the memory of a card in the reset state constitute
2088 if (card
->state
== FST_RESET
) {
2089 card
->state
= FST_DOWNLOAD
;
2095 /* If card has just been started check the shared memory config
2096 * version and marker
2098 if (card
->state
== FST_STARTING
) {
2099 check_started_ok(card
);
2101 /* If everything checked out enable card interrupts */
2102 if (card
->state
== FST_RUNNING
) {
2103 spin_lock_irqsave(&card
->card_lock
, flags
);
2104 fst_enable_intr(card
);
2105 FST_WRB(card
, interruptHandshake
, 0xEE);
2106 spin_unlock_irqrestore(&card
->card_lock
, flags
);
2110 if (ifr
->ifr_data
== NULL
) {
2114 gather_conf_info(card
, port
, &info
);
2116 if (copy_to_user(ifr
->ifr_data
, &info
, sizeof (info
))) {
2124 * Most of the settings have been moved to the generic ioctls
2125 * this just covers debug and board ident now
2128 if (card
->state
!= FST_RUNNING
) {
2130 ("Attempt to configure card %d in non-running state (%d)\n",
2131 card
->card_no
, card
->state
);
2134 if (copy_from_user(&info
, ifr
->ifr_data
, sizeof (info
))) {
2138 return set_conf_from_info(card
, port
, &info
);
2141 switch (ifr
->ifr_settings
.type
) {
2143 return fst_get_iface(card
, port
, ifr
);
2145 case IF_IFACE_SYNC_SERIAL
:
2152 return fst_set_iface(card
, port
, ifr
);
2155 port
->mode
= FST_RAW
;
2159 if (port
->mode
== FST_RAW
) {
2160 ifr
->ifr_settings
.type
= IF_PROTO_RAW
;
2163 return hdlc_ioctl(dev
, ifr
, cmd
);
2166 port
->mode
= FST_GEN_HDLC
;
2167 dbg(DBG_IOCTL
, "Passing this type to hdlc %x\n",
2168 ifr
->ifr_settings
.type
);
2169 return hdlc_ioctl(dev
, ifr
, cmd
);
2173 /* Not one of ours. Pass through to HDLC package */
2174 return hdlc_ioctl(dev
, ifr
, cmd
);
2179 fst_openport(struct fst_port_info
*port
)
2184 /* Only init things if card is actually running. This allows open to
2185 * succeed for downloads etc.
2187 if (port
->card
->state
== FST_RUNNING
) {
2189 dbg(DBG_OPEN
, "open: found port already running\n");
2191 fst_issue_cmd(port
, STOPPORT
);
2195 fst_rx_config(port
);
2196 fst_tx_config(port
);
2197 fst_op_raise(port
, OPSTS_RTS
| OPSTS_DTR
);
2199 fst_issue_cmd(port
, STARTPORT
);
2202 signals
= FST_RDL(port
->card
, v24DebouncedSts
[port
->index
]);
2203 if (signals
& (((port
->hwif
== X21
) || (port
->hwif
== X21D
))
2204 ? IPSTS_INDICATE
: IPSTS_DCD
))
2205 netif_carrier_on(port_to_dev(port
));
2207 netif_carrier_off(port_to_dev(port
));
2209 txq_length
= port
->txqe
- port
->txqs
;
2217 fst_closeport(struct fst_port_info
*port
)
2219 if (port
->card
->state
== FST_RUNNING
) {
2222 fst_op_lower(port
, OPSTS_RTS
| OPSTS_DTR
);
2224 fst_issue_cmd(port
, STOPPORT
);
2226 dbg(DBG_OPEN
, "close: port not running\n");
2232 fst_open(struct net_device
*dev
)
2235 struct fst_port_info
*port
;
2237 port
= dev_to_port(dev
);
2238 if (!try_module_get(THIS_MODULE
))
2241 if (port
->mode
!= FST_RAW
) {
2242 err
= hdlc_open(dev
);
2248 netif_wake_queue(dev
);
2253 fst_close(struct net_device
*dev
)
2255 struct fst_port_info
*port
;
2256 struct fst_card_info
*card
;
2257 unsigned char tx_dma_done
;
2258 unsigned char rx_dma_done
;
2260 port
= dev_to_port(dev
);
2263 tx_dma_done
= inb(card
->pci_conf
+ DMACSR1
);
2264 rx_dma_done
= inb(card
->pci_conf
+ DMACSR0
);
2266 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2267 card
->dmatx_in_progress
, tx_dma_done
, card
->dmarx_in_progress
,
2270 netif_stop_queue(dev
);
2271 fst_closeport(dev_to_port(dev
));
2272 if (port
->mode
!= FST_RAW
) {
2275 module_put(THIS_MODULE
);
2280 fst_attach(struct net_device
*dev
, unsigned short encoding
, unsigned short parity
)
2283 * Setting currently fixed in FarSync card so we check and forget
2285 if (encoding
!= ENCODING_NRZ
|| parity
!= PARITY_CRC16_PR1_CCITT
)
2291 fst_tx_timeout(struct net_device
*dev
)
2293 struct fst_port_info
*port
;
2294 struct fst_card_info
*card
;
2295 struct net_device_stats
*stats
= hdlc_stats(dev
);
2297 port
= dev_to_port(dev
);
2300 stats
->tx_aborted_errors
++;
2301 dbg(DBG_ASS
, "Tx timeout card %d port %d\n",
2302 card
->card_no
, port
->index
);
2303 fst_issue_cmd(port
, ABORTTX
);
2305 dev
->trans_start
= jiffies
;
2306 netif_wake_queue(dev
);
2311 fst_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2313 struct fst_card_info
*card
;
2314 struct fst_port_info
*port
;
2315 struct net_device_stats
*stats
= hdlc_stats(dev
);
2316 unsigned long flags
;
2319 port
= dev_to_port(dev
);
2321 dbg(DBG_TX
, "fst_start_xmit: length = %d\n", skb
->len
);
2323 /* Drop packet with error if we don't have carrier */
2324 if (!netif_carrier_ok(dev
)) {
2327 stats
->tx_carrier_errors
++;
2329 "Tried to transmit but no carrier on card %d port %d\n",
2330 card
->card_no
, port
->index
);
2334 /* Drop it if it's too big! MTU failure ? */
2335 if (skb
->len
> LEN_TX_BUFFER
) {
2336 dbg(DBG_ASS
, "Packet too large %d vs %d\n", skb
->len
,
2344 * We are always going to queue the packet
2345 * so that the bottom half is the only place we tx from
2346 * Check there is room in the port txq
2348 spin_lock_irqsave(&card
->card_lock
, flags
);
2349 if ((txq_length
= port
->txqe
- port
->txqs
) < 0) {
2351 * This is the case where the next free has wrapped but the
2354 txq_length
= txq_length
+ FST_TXQ_DEPTH
;
2356 spin_unlock_irqrestore(&card
->card_lock
, flags
);
2357 if (txq_length
> fst_txq_high
) {
2359 * We have got enough buffers in the pipeline. Ask the network
2360 * layer to stop sending frames down
2362 netif_stop_queue(dev
);
2363 port
->start
= 1; /* I'm using this to signal stop sent up */
2366 if (txq_length
== FST_TXQ_DEPTH
- 1) {
2368 * This shouldn't have happened but such is life
2372 dbg(DBG_ASS
, "Tx queue overflow card %d port %d\n",
2373 card
->card_no
, port
->index
);
2380 spin_lock_irqsave(&card
->card_lock
, flags
);
2381 port
->txq
[port
->txqe
] = skb
;
2383 if (port
->txqe
== FST_TXQ_DEPTH
)
2385 spin_unlock_irqrestore(&card
->card_lock
, flags
);
2387 /* Scehdule the bottom half which now does transmit processing */
2388 fst_q_work_item(&fst_work_txq
, card
->card_no
);
2389 tasklet_schedule(&fst_tx_task
);
2395 * Card setup having checked hardware resources.
2396 * Should be pretty bizarre if we get an error here (kernel memory
2397 * exhaustion is one possibility). If we do see a problem we report it
2398 * via a printk and leave the corresponding interface and all that follow
2401 static char *type_strings
[] __devinitdata
= {
2402 "no hardware", /* Should never be seen */
2411 static void __devinit
2412 fst_init_card(struct fst_card_info
*card
)
2417 /* We're working on a number of ports based on the card ID. If the
2418 * firmware detects something different later (should never happen)
2419 * we'll have to revise it in some way then.
2421 for (i
= 0; i
< card
->nports
; i
++) {
2422 err
= register_hdlc_device(card
->ports
[i
].dev
);
2425 printk_err ("Cannot register HDLC device for port %d"
2426 " (errno %d)\n", i
, -err
);
2427 for (j
= i
; j
< card
->nports
; j
++) {
2428 free_netdev(card
->ports
[j
].dev
);
2429 card
->ports
[j
].dev
= NULL
;
2436 printk_info("%s-%s: %s IRQ%d, %d ports\n",
2437 port_to_dev(&card
->ports
[0])->name
,
2438 port_to_dev(&card
->ports
[card
->nports
- 1])->name
,
2439 type_strings
[card
->type
], card
->irq
, card
->nports
);
2443 * Initialise card when detected.
2444 * Returns 0 to indicate success, or errno otherwise.
2446 static int __devinit
2447 fst_add_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2449 static int firsttime_done
= 0;
2450 static int no_of_cards_added
= 0;
2451 struct fst_card_info
*card
;
2455 if (!firsttime_done
) {
2456 printk_info("FarSync WAN driver " FST_USER_VERSION
2457 " (c) 2001-2004 FarSite Communications Ltd.\n");
2459 dbg(DBG_ASS
, "The value of debug mask is %x\n", fst_debug_mask
);
2463 * We are going to be clever and allow certain cards not to be
2464 * configured. An exclude list can be provided in /etc/modules.conf
2466 if (fst_excluded_cards
!= 0) {
2468 * There are cards to exclude
2471 for (i
= 0; i
< fst_excluded_cards
; i
++) {
2472 if ((pdev
->devfn
) >> 3 == fst_excluded_list
[i
]) {
2473 printk_info("FarSync PCI device %d not assigned\n",
2474 (pdev
->devfn
) >> 3);
2480 /* Allocate driver private data */
2481 card
= kmalloc(sizeof (struct fst_card_info
), GFP_KERNEL
);
2483 printk_err("FarSync card found but insufficient memory for"
2484 " driver storage\n");
2487 memset(card
, 0, sizeof (struct fst_card_info
));
2489 /* Try to enable the device */
2490 if ((err
= pci_enable_device(pdev
)) != 0) {
2491 printk_err("Failed to enable card. Err %d\n", -err
);
2496 if ((err
= pci_request_regions(pdev
, "FarSync")) !=0) {
2497 printk_err("Failed to allocate regions. Err %d\n", -err
);
2498 pci_disable_device(pdev
);
2503 /* Get virtual addresses of memory regions */
2504 card
->pci_conf
= pci_resource_start(pdev
, 1);
2505 card
->phys_mem
= pci_resource_start(pdev
, 2);
2506 card
->phys_ctlmem
= pci_resource_start(pdev
, 3);
2507 if ((card
->mem
= ioremap(card
->phys_mem
, FST_MEMSIZE
)) == NULL
) {
2508 printk_err("Physical memory remap failed\n");
2509 pci_release_regions(pdev
);
2510 pci_disable_device(pdev
);
2514 if ((card
->ctlmem
= ioremap(card
->phys_ctlmem
, 0x10)) == NULL
) {
2515 printk_err("Control memory remap failed\n");
2516 pci_release_regions(pdev
);
2517 pci_disable_device(pdev
);
2521 dbg(DBG_PCI
, "kernel mem %p, ctlmem %p\n", card
->mem
, card
->ctlmem
);
2523 /* Register the interrupt handler */
2524 if (request_irq(pdev
->irq
, fst_intr
, SA_SHIRQ
, FST_DEV_NAME
, card
)) {
2525 printk_err("Unable to register interrupt %d\n", card
->irq
);
2526 pci_release_regions(pdev
);
2527 pci_disable_device(pdev
);
2528 iounmap(card
->ctlmem
);
2534 /* Record info we need */
2535 card
->irq
= pdev
->irq
;
2536 card
->type
= ent
->driver_data
;
2537 card
->family
= ((ent
->driver_data
== FST_TYPE_T2P
) ||
2538 (ent
->driver_data
== FST_TYPE_T4P
))
2539 ? FST_FAMILY_TXP
: FST_FAMILY_TXU
;
2540 if ((ent
->driver_data
== FST_TYPE_T1U
) ||
2541 (ent
->driver_data
== FST_TYPE_TE1
))
2544 card
->nports
= ((ent
->driver_data
== FST_TYPE_T2P
) ||
2545 (ent
->driver_data
== FST_TYPE_T2U
)) ? 2 : 4;
2547 card
->state
= FST_UNINIT
;
2548 spin_lock_init ( &card
->card_lock
);
2550 for ( i
= 0 ; i
< card
->nports
; i
++ ) {
2551 struct net_device
*dev
= alloc_hdlcdev(&card
->ports
[i
]);
2555 free_netdev(card
->ports
[i
].dev
);
2556 printk_err ("FarSync: out of memory\n");
2557 free_irq(card
->irq
, card
);
2558 pci_release_regions(pdev
);
2559 pci_disable_device(pdev
);
2560 iounmap(card
->ctlmem
);
2565 card
->ports
[i
].dev
= dev
;
2566 card
->ports
[i
].card
= card
;
2567 card
->ports
[i
].index
= i
;
2568 card
->ports
[i
].run
= 0;
2570 hdlc
= dev_to_hdlc(dev
);
2572 /* Fill in the net device info */
2573 /* Since this is a PCI setup this is purely
2574 * informational. Give them the buffer addresses
2575 * and basic card I/O.
2577 dev
->mem_start
= card
->phys_mem
2578 + BUF_OFFSET ( txBuffer
[i
][0][0]);
2579 dev
->mem_end
= card
->phys_mem
2580 + BUF_OFFSET ( txBuffer
[i
][NUM_TX_BUFFER
][0]);
2581 dev
->base_addr
= card
->pci_conf
;
2582 dev
->irq
= card
->irq
;
2584 dev
->tx_queue_len
= FST_TX_QUEUE_LEN
;
2585 dev
->open
= fst_open
;
2586 dev
->stop
= fst_close
;
2587 dev
->do_ioctl
= fst_ioctl
;
2588 dev
->watchdog_timeo
= FST_TX_TIMEOUT
;
2589 dev
->tx_timeout
= fst_tx_timeout
;
2590 hdlc
->attach
= fst_attach
;
2591 hdlc
->xmit
= fst_start_xmit
;
2594 card
->device
= pdev
;
2596 dbg(DBG_PCI
, "type %d nports %d irq %d\n", card
->type
,
2597 card
->nports
, card
->irq
);
2598 dbg(DBG_PCI
, "conf %04x mem %08x ctlmem %08x\n",
2599 card
->pci_conf
, card
->phys_mem
, card
->phys_ctlmem
);
2601 /* Reset the card's processor */
2603 card
->state
= FST_RESET
;
2605 /* Initialise DMA (if required) */
2608 /* Record driver data for later use */
2609 pci_set_drvdata(pdev
, card
);
2611 /* Remainder of card setup */
2612 fst_card_array
[no_of_cards_added
] = card
;
2613 card
->card_no
= no_of_cards_added
++; /* Record instance and bump it */
2614 fst_init_card(card
);
2615 if (card
->family
== FST_FAMILY_TXU
) {
2617 * Allocate a dma buffer for transmit and receives
2619 card
->rx_dma_handle_host
=
2620 pci_alloc_consistent(card
->device
, FST_MAX_MTU
,
2621 &card
->rx_dma_handle_card
);
2622 if (card
->rx_dma_handle_host
== NULL
) {
2623 printk_err("Could not allocate rx dma buffer\n");
2624 fst_disable_intr(card
);
2625 pci_release_regions(pdev
);
2626 pci_disable_device(pdev
);
2627 iounmap(card
->ctlmem
);
2632 card
->tx_dma_handle_host
=
2633 pci_alloc_consistent(card
->device
, FST_MAX_MTU
,
2634 &card
->tx_dma_handle_card
);
2635 if (card
->tx_dma_handle_host
== NULL
) {
2636 printk_err("Could not allocate tx dma buffer\n");
2637 fst_disable_intr(card
);
2638 pci_release_regions(pdev
);
2639 pci_disable_device(pdev
);
2640 iounmap(card
->ctlmem
);
2646 return 0; /* Success */
2650 * Cleanup and close down a card
2652 static void __devexit
2653 fst_remove_one(struct pci_dev
*pdev
)
2655 struct fst_card_info
*card
;
2658 card
= pci_get_drvdata(pdev
);
2660 for (i
= 0; i
< card
->nports
; i
++) {
2661 struct net_device
*dev
= port_to_dev(&card
->ports
[i
]);
2662 unregister_hdlc_device(dev
);
2665 fst_disable_intr(card
);
2666 free_irq(card
->irq
, card
);
2668 iounmap(card
->ctlmem
);
2670 pci_release_regions(pdev
);
2671 if (card
->family
== FST_FAMILY_TXU
) {
2675 pci_free_consistent(card
->device
, FST_MAX_MTU
,
2676 card
->rx_dma_handle_host
,
2677 card
->rx_dma_handle_card
);
2678 pci_free_consistent(card
->device
, FST_MAX_MTU
,
2679 card
->tx_dma_handle_host
,
2680 card
->tx_dma_handle_card
);
2682 fst_card_array
[card
->card_no
] = NULL
;
2685 static struct pci_driver fst_driver
= {
2687 .id_table
= fst_pci_dev_id
,
2688 .probe
= fst_add_one
,
2689 .remove
= __devexit_p(fst_remove_one
),
2699 for (i
= 0; i
< FST_MAX_CARDS
; i
++)
2700 fst_card_array
[i
] = NULL
;
2701 spin_lock_init(&fst_work_q_lock
);
2702 return pci_module_init(&fst_driver
);
2706 fst_cleanup_module(void)
2708 printk_info("FarSync WAN driver unloading\n");
2709 pci_unregister_driver(&fst_driver
);
2712 module_init(fst_init
);
2713 module_exit(fst_cleanup_module
);