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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/net/wan/fsl_ucc_hdlc.h
1 /* Freescale QUICC Engine HDLC Device Driver
3 * Copyright 2014 Freescale Semiconductor Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/list.h>
17 #include <soc/fsl/qe/immap_qe.h>
18 #include <soc/fsl/qe/qe.h>
20 #include <soc/fsl/qe/ucc.h>
21 #include <soc/fsl/qe/ucc_fast.h>
23 /* UCC HDLC event register */
24 #define UCCE_HDLC_RX_EVENTS \
25 (UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY)
26 #define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE)
28 struct ucc_hdlc_param
{
69 struct ucc_hdlc_private
{
71 struct ucc_tdm_info
*ut_info
;
72 struct ucc_fast_private
*uccf
;
74 struct net_device
*ndev
;
75 struct napi_struct napi
;
76 struct ucc_fast __iomem
*uf_regs
; /* UCC Fast registers */
77 struct ucc_hdlc_param __iomem
*ucc_pram
;
85 dma_addr_t dma_tx_addr
;
86 dma_addr_t dma_rx_addr
;
88 struct qe_bd
*tx_bd_base
;
89 struct qe_bd
*rx_bd_base
;
92 struct qe_bd
*curtx_bd
;
93 struct qe_bd
*currx_bd
;
94 struct qe_bd
*dirty_tx
;
97 struct sk_buff
**tx_skbuff
;
98 struct sk_buff
**rx_skbuff
;
101 unsigned short skb_dirtytx
;
103 unsigned short tx_ring_size
;
104 unsigned short rx_ring_size
;
107 unsigned short encoding
;
108 unsigned short parity
;
109 unsigned short hmask
;
111 spinlock_t lock
; /* lock for Tx BD and Tx buffer */
113 struct ucc_hdlc_param
*ucc_pram_bak
;
116 u32 cmxsi1cr_l
, cmxsi1cr_h
;
122 #define TX_BD_RING_LEN 0x10
123 #define RX_BD_RING_LEN 0x20
124 #define RX_CLEAN_MAX 0x10
126 #define MAX_RX_BUF_LENGTH (48 * 0x20)
127 #define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8)
128 #define ALIGNMENT_OF_UCC_HDLC_PRAM 64
129 #define SI_BANK_SIZE 128
130 #define MAX_HDLC_NUM 4
131 #define HDLC_HEAD_LEN 2
132 #define HDLC_CRC_SIZE 2
133 #define TX_RING_MOD_MASK(size) (size - 1)
134 #define RX_RING_MOD_MASK(size) (size - 1)
136 #define HDLC_HEAD_MASK 0x0000
137 #define DEFAULT_HDLC_HEAD 0xff44
138 #define DEFAULT_ADDR_MASK 0x00ff
139 #define DEFAULT_HDLC_ADDR 0x00ff
141 #define BMR_GBL 0x20000000
142 #define BMR_BIG_ENDIAN 0x10000000
143 #define CRC_16BIT_MASK 0x0000F0B8
144 #define CRC_16BIT_PRES 0x0000FFFF
145 #define DEFAULT_RFTHR 1
147 #define DEFAULT_PPP_HEAD 0xff03