drivers/net/wireless/admtek/adm8211.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef ADM8211_H
   3 #define ADM8211_H
   4
   5 /* ADM8211 Registers */
   6
   7 /* CR32 (SIG) signature */
   8 #define ADM8211_SIG1            0x82011317 /* ADM8211A */
   9 #define ADM8211_SIG2            0x82111317 /* ADM8211B/ADM8211C */
  10
  11 #define ADM8211_CSR_READ(r) ioread32(&priv->map->r)
  12 #define ADM8211_CSR_WRITE(r, val) iowrite32((val), &priv->map->r)
  13
  14 /* CSR (Host Control and Status Registers) */
  15 struct adm8211_csr {
  16         __le32 PAR;             /* 0x00 CSR0 */
  17         __le32 FRCTL;           /* 0x04 CSR0A */
  18         __le32 TDR;             /* 0x08 CSR1 */
  19         __le32 WTDP;            /* 0x0C CSR1A */
  20         __le32 RDR;             /* 0x10 CSR2 */
  21         __le32 WRDP;            /* 0x14 CSR2A */
  22         __le32 RDB;             /* 0x18 CSR3 */
  23         __le32 TDBH;            /* 0x1C CSR3A */
  24         __le32 TDBD;            /* 0x20 CSR4 */
  25         __le32 TDBP;            /* 0x24 CSR4A */
  26         __le32 STSR;            /* 0x28 CSR5 */
  27         __le32 TDBB;            /* 0x2C CSR5A */
  28         __le32 NAR;             /* 0x30 CSR6 */
  29         __le32 CSR6A;           /* reserved */
  30         __le32 IER;             /* 0x38 CSR7 */
  31         __le32 TKIPSCEP;        /* 0x3C CSR7A */
  32         __le32 LPC;             /* 0x40 CSR8 */
  33         __le32 CSR_TEST1;       /* 0x44 CSR8A */
  34         __le32 SPR;             /* 0x48 CSR9 */
  35         __le32 CSR_TEST0;       /* 0x4C CSR9A */
  36         __le32 WCSR;            /* 0x50 CSR10 */
  37         __le32 WPDR;            /* 0x54 CSR10A */
  38         __le32 GPTMR;           /* 0x58 CSR11 */
  39         __le32 GPIO;            /* 0x5C CSR11A */
  40         __le32 BBPCTL;          /* 0x60 CSR12 */
  41         __le32 SYNCTL;          /* 0x64 CSR12A */
  42         __le32 PLCPHD;          /* 0x68 CSR13 */
  43         __le32 MMIWA;           /* 0x6C CSR13A */
  44         __le32 MMIRD0;          /* 0x70 CSR14 */
  45         __le32 MMIRD1;          /* 0x74 CSR14A */
  46         __le32 TXBR;            /* 0x78 CSR15 */
  47         __le32 SYNDATA;         /* 0x7C CSR15A */
  48         __le32 ALCS;            /* 0x80 CSR16 */
  49         __le32 TOFS2;           /* 0x84 CSR17 */
  50         __le32 CMDR;            /* 0x88 CSR18 */
  51         __le32 PCIC;            /* 0x8C CSR19 */
  52         __le32 PMCSR;           /* 0x90 CSR20 */
  53         __le32 PAR0;            /* 0x94 CSR21 */
  54         __le32 PAR1;            /* 0x98 CSR22 */
  55         __le32 MAR0;            /* 0x9C CSR23 */
  56         __le32 MAR1;            /* 0xA0 CSR24 */
  57         __le32 ATIMDA0;         /* 0xA4 CSR25 */
  58         __le32 ABDA1;           /* 0xA8 CSR26 */
  59         __le32 BSSID0;          /* 0xAC CSR27 */
  60         __le32 TXLMT;           /* 0xB0 CSR28 */
  61         __le32 MIBCNT;          /* 0xB4 CSR29 */
  62         __le32 BCNT;            /* 0xB8 CSR30 */
  63         __le32 TSFTH;           /* 0xBC CSR31 */
  64         __le32 TSC;             /* 0xC0 CSR32 */
  65         __le32 SYNRF;           /* 0xC4 CSR33 */
  66         __le32 BPLI;            /* 0xC8 CSR34 */
  67         __le32 CAP0;            /* 0xCC CSR35 */
  68         __le32 CAP1;            /* 0xD0 CSR36 */
  69         __le32 RMD;             /* 0xD4 CSR37 */
  70         __le32 CFPP;            /* 0xD8 CSR38 */
  71         __le32 TOFS0;           /* 0xDC CSR39 */
  72         __le32 TOFS1;           /* 0xE0 CSR40 */
  73         __le32 IFST;            /* 0xE4 CSR41 */
  74         __le32 RSPT;            /* 0xE8 CSR42 */
  75         __le32 TSFTL;           /* 0xEC CSR43 */
  76         __le32 WEPCTL;          /* 0xF0 CSR44 */
  77         __le32 WESK;            /* 0xF4 CSR45 */
  78         __le32 WEPCNT;          /* 0xF8 CSR46 */
  79         __le32 MACTEST;         /* 0xFC CSR47 */
  80         __le32 FER;             /* 0x100 */
  81         __le32 FEMR;            /* 0x104 */
  82         __le32 FPSR;            /* 0x108 */
  83         __le32 FFER;            /* 0x10C */
  84 } __packed;
  85
  86 /* CSR0 - PAR (PCI Address Register) */
  87 #define ADM8211_PAR_MWIE        (1 << 24)
  88 #define ADM8211_PAR_MRLE        (1 << 23)
  89 #define ADM8211_PAR_MRME        (1 << 21)
  90 #define ADM8211_PAR_RAP         ((1 << 18) | (1 << 17))
  91 #define ADM8211_PAR_CAL         ((1 << 15) | (1 << 14))
  92 #define ADM8211_PAR_PBL         0x00003f00
  93 #define ADM8211_PAR_BLE         (1 << 7)
  94 #define ADM8211_PAR_DSL         0x0000007c
  95 #define ADM8211_PAR_BAR         (1 << 1)
  96 #define ADM8211_PAR_SWR         (1 << 0)
  97
  98 /* CSR1 - FRCTL (Frame Control Register) */
  99 #define ADM8211_FRCTL_PWRMGT    (1 << 31)
 100 #define ADM8211_FRCTL_MAXPSP    (1 << 27)
 101 #define ADM8211_FRCTL_DRVPRSP   (1 << 26)
 102 #define ADM8211_FRCTL_DRVBCON   (1 << 25)
 103 #define ADM8211_FRCTL_AID       0x0000ffff
 104 #define ADM8211_FRCTL_AID_ON    0x0000c000
 105
 106 /* CSR5 - STSR (Status Register) */
 107 #define ADM8211_STSR_PCF        (1 << 31)
 108 #define ADM8211_STSR_BCNTC      (1 << 30)
 109 #define ADM8211_STSR_GPINT      (1 << 29)
 110 #define ADM8211_STSR_LinkOff    (1 << 28)
 111 #define ADM8211_STSR_ATIMTC     (1 << 27)
 112 #define ADM8211_STSR_TSFTF      (1 << 26)
 113 #define ADM8211_STSR_TSCZ       (1 << 25)
 114 #define ADM8211_STSR_LinkOn     (1 << 24)
 115 #define ADM8211_STSR_SQL        (1 << 23)
 116 #define ADM8211_STSR_WEPTD      (1 << 22)
 117 #define ADM8211_STSR_ATIME      (1 << 21)
 118 #define ADM8211_STSR_TBTT       (1 << 20)
 119 #define ADM8211_STSR_NISS       (1 << 16)
 120 #define ADM8211_STSR_AISS       (1 << 15)
 121 #define ADM8211_STSR_TEIS       (1 << 14)
 122 #define ADM8211_STSR_FBE        (1 << 13)
 123 #define ADM8211_STSR_REIS       (1 << 12)
 124 #define ADM8211_STSR_GPTT       (1 << 11)
 125 #define ADM8211_STSR_RPS        (1 << 8)
 126 #define ADM8211_STSR_RDU        (1 << 7)
 127 #define ADM8211_STSR_RCI        (1 << 6)
 128 #define ADM8211_STSR_TUF        (1 << 5)
 129 #define ADM8211_STSR_TRT        (1 << 4)
 130 #define ADM8211_STSR_TLT        (1 << 3)
 131 #define ADM8211_STSR_TDU        (1 << 2)
 132 #define ADM8211_STSR_TPS        (1 << 1)
 133 #define ADM8211_STSR_TCI        (1 << 0)
 134
 135 /* CSR6 - NAR (Network Access Register) */
 136 #define ADM8211_NAR_TXCF        (1 << 31)
 137 #define ADM8211_NAR_HF          (1 << 30)
 138 #define ADM8211_NAR_UTR         (1 << 29)
 139 #define ADM8211_NAR_SQ          (1 << 28)
 140 #define ADM8211_NAR_CFP         (1 << 27)
 141 #define ADM8211_NAR_SF          (1 << 21)
 142 #define ADM8211_NAR_TR          ((1 << 15) | (1 << 14))
 143 #define ADM8211_NAR_ST          (1 << 13)
 144 #define ADM8211_NAR_OM          ((1 << 11) | (1 << 10))
 145 #define ADM8211_NAR_MM          (1 << 7)
 146 #define ADM8211_NAR_PR          (1 << 6)
 147 #define ADM8211_NAR_EA          (1 << 5)
 148 #define ADM8211_NAR_PB          (1 << 3)
 149 #define ADM8211_NAR_STPDMA      (1 << 2)
 150 #define ADM8211_NAR_SR          (1 << 1)
 151 #define ADM8211_NAR_CTX         (1 << 0)
 152
 153 #define ADM8211_IDLE()                                                     \
 154 do {                                                                       \
 155         if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) {               \
 156                 ADM8211_CSR_WRITE(NAR, priv->nar &                         \
 157                                        ~(ADM8211_NAR_SR | ADM8211_NAR_ST));\
 158                 ADM8211_CSR_READ(NAR);                                     \
 159                 msleep(20);                                                \
 160         }                                                                  \
 161 } while (0)
 162
 163 #define ADM8211_IDLE_RX()                                               \
 164 do {                                                                    \
 165         if (priv->nar & ADM8211_NAR_SR) {                               \
 166                 ADM8211_CSR_WRITE(NAR, priv->nar & ~ADM8211_NAR_SR);    \
 167                 ADM8211_CSR_READ(NAR);                                  \
 168                 mdelay(20);                                             \
 169         }                                                               \
 170 } while (0)
 171
 172 #define ADM8211_RESTORE()                                       \
 173 do {                                                            \
 174         if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST))      \
 175                 ADM8211_CSR_WRITE(NAR, priv->nar);              \
 176 } while (0)
 177
 178 /* CSR7 - IER (Interrupt Enable Register) */
 179 #define ADM8211_IER_PCFIE       (1 << 31)
 180 #define ADM8211_IER_BCNTCIE     (1 << 30)
 181 #define ADM8211_IER_GPIE        (1 << 29)
 182 #define ADM8211_IER_LinkOffIE   (1 << 28)
 183 #define ADM8211_IER_ATIMTCIE    (1 << 27)
 184 #define ADM8211_IER_TSFTFIE     (1 << 26)
 185 #define ADM8211_IER_TSCZE       (1 << 25)
 186 #define ADM8211_IER_LinkOnIE    (1 << 24)
 187 #define ADM8211_IER_SQLIE       (1 << 23)
 188 #define ADM8211_IER_WEPIE       (1 << 22)
 189 #define ADM8211_IER_ATIMEIE     (1 << 21)
 190 #define ADM8211_IER_TBTTIE      (1 << 20)
 191 #define ADM8211_IER_NIE         (1 << 16)
 192 #define ADM8211_IER_AIE         (1 << 15)
 193 #define ADM8211_IER_TEIE        (1 << 14)
 194 #define ADM8211_IER_FBEIE       (1 << 13)
 195 #define ADM8211_IER_REIE        (1 << 12)
 196 #define ADM8211_IER_GPTIE       (1 << 11)
 197 #define ADM8211_IER_RSIE        (1 << 8)
 198 #define ADM8211_IER_RUIE        (1 << 7)
 199 #define ADM8211_IER_RCIE        (1 << 6)
 200 #define ADM8211_IER_TUIE        (1 << 5)
 201 #define ADM8211_IER_TRTIE       (1 << 4)
 202 #define ADM8211_IER_TLTTIE      (1 << 3)
 203 #define ADM8211_IER_TDUIE       (1 << 2)
 204 #define ADM8211_IER_TPSIE       (1 << 1)
 205 #define ADM8211_IER_TCIE        (1 << 0)
 206
 207 /* CSR9 - SPR (Serial Port Register) */
 208 #define ADM8211_SPR_SRS         (1 << 11)
 209 #define ADM8211_SPR_SDO         (1 << 3)
 210 #define ADM8211_SPR_SDI         (1 << 2)
 211 #define ADM8211_SPR_SCLK        (1 << 1)
 212 #define ADM8211_SPR_SCS         (1 << 0)
 213
 214 /* CSR9A - CSR_TEST0 */
 215 #define ADM8211_CSR_TEST0_EPNE  (1 << 18)
 216 #define ADM8211_CSR_TEST0_EPSNM (1 << 17)
 217 #define ADM8211_CSR_TEST0_EPTYP (1 << 16)
 218 #define ADM8211_CSR_TEST0_EPRLD (1 << 15)
 219
 220 /* CSR10 - WCSR (Wake-up Control/Status Register) */
 221 #define ADM8211_WCSR_CRCT       (1 << 30)
 222 #define ADM8211_WCSR_TSFTWE     (1 << 20)
 223 #define ADM8211_WCSR_TIMWE      (1 << 19)
 224 #define ADM8211_WCSR_ATIMWE     (1 << 18)
 225 #define ADM8211_WCSR_KEYWE      (1 << 17)
 226 #define ADM8211_WCSR_MPRE       (1 << 9)
 227 #define ADM8211_WCSR_LSOE       (1 << 8)
 228 #define ADM8211_WCSR_KEYUP      (1 << 6)
 229 #define ADM8211_WCSR_TSFTW      (1 << 5)
 230 #define ADM8211_WCSR_TIMW       (1 << 4)
 231 #define ADM8211_WCSR_ATIMW      (1 << 3)
 232 #define ADM8211_WCSR_MPR        (1 << 1)
 233 #define ADM8211_WCSR_LSO        (1 << 0)
 234
 235 /* CSR11A - GPIO */
 236 #define ADM8211_CSR_GPIO_EN5    (1 << 17)
 237 #define ADM8211_CSR_GPIO_EN4    (1 << 16)
 238 #define ADM8211_CSR_GPIO_EN3    (1 << 15)
 239 #define ADM8211_CSR_GPIO_EN2    (1 << 14)
 240 #define ADM8211_CSR_GPIO_EN1    (1 << 13)
 241 #define ADM8211_CSR_GPIO_EN0    (1 << 12)
 242 #define ADM8211_CSR_GPIO_O5     (1 << 11)
 243 #define ADM8211_CSR_GPIO_O4     (1 << 10)
 244 #define ADM8211_CSR_GPIO_O3     (1 << 9)
 245 #define ADM8211_CSR_GPIO_O2     (1 << 8)
 246 #define ADM8211_CSR_GPIO_O1     (1 << 7)
 247 #define ADM8211_CSR_GPIO_O0     (1 << 6)
 248 #define ADM8211_CSR_GPIO_IN     0x0000003f
 249
 250 /* CSR12 - BBPCTL (BBP Control port) */
 251 #define ADM8211_BBPCTL_MMISEL   (1 << 31)
 252 #define ADM8211_BBPCTL_SPICADD  (0x7F << 24)
 253 #define ADM8211_BBPCTL_RF3000   (0x20 << 24)
 254 #define ADM8211_BBPCTL_TXCE     (1 << 23)
 255 #define ADM8211_BBPCTL_RXCE     (1 << 22)
 256 #define ADM8211_BBPCTL_CCAP     (1 << 21)
 257 #define ADM8211_BBPCTL_TYPE     0x001c0000
 258 #define ADM8211_BBPCTL_WR       (1 << 17)
 259 #define ADM8211_BBPCTL_RD       (1 << 16)
 260 #define ADM8211_BBPCTL_ADDR     0x0000ff00
 261 #define ADM8211_BBPCTL_DATA     0x000000ff
 262
 263 /* CSR12A - SYNCTL (Synthesizer Control port) */
 264 #define ADM8211_SYNCTL_WR       (1 << 31)
 265 #define ADM8211_SYNCTL_RD       (1 << 30)
 266 #define ADM8211_SYNCTL_CS0      (1 << 29)
 267 #define ADM8211_SYNCTL_CS1      (1 << 28)
 268 #define ADM8211_SYNCTL_CAL      (1 << 27)
 269 #define ADM8211_SYNCTL_SELCAL   (1 << 26)
 270 #define ADM8211_SYNCTL_RFtype   ((1 << 24) | (1 << 23) | (1 << 22))
 271 #define ADM8211_SYNCTL_RFMD     (1 << 22)
 272 #define ADM8211_SYNCTL_GENERAL  (0x7 << 22)
 273 /* SYNCTL 21:0 Data (Si4126: 18-bit data, 4-bit address) */
 274
 275 /* CSR18 - CMDR (Command Register) */
 276 #define ADM8211_CMDR_PM         (1 << 19)
 277 #define ADM8211_CMDR_APM        (1 << 18)
 278 #define ADM8211_CMDR_RTE        (1 << 4)
 279 #define ADM8211_CMDR_DRT        ((1 << 3) | (1 << 2))
 280 #define ADM8211_CMDR_DRT_8DW    (0x0 << 2)
 281 #define ADM8211_CMDR_DRT_16DW   (0x1 << 2)
 282 #define ADM8211_CMDR_DRT_SF     (0x2 << 2)
 283
 284 /* CSR33 - SYNRF (SYNRF direct control) */
 285 #define ADM8211_SYNRF_SELSYN    (1 << 31)
 286 #define ADM8211_SYNRF_SELRF     (1 << 30)
 287 #define ADM8211_SYNRF_LERF      (1 << 29)
 288 #define ADM8211_SYNRF_LEIF      (1 << 28)
 289 #define ADM8211_SYNRF_SYNCLK    (1 << 27)
 290 #define ADM8211_SYNRF_SYNDATA   (1 << 26)
 291 #define ADM8211_SYNRF_PE1       (1 << 25)
 292 #define ADM8211_SYNRF_PE2       (1 << 24)
 293 #define ADM8211_SYNRF_PA_PE     (1 << 23)
 294 #define ADM8211_SYNRF_TR_SW     (1 << 22)
 295 #define ADM8211_SYNRF_TR_SWN    (1 << 21)
 296 #define ADM8211_SYNRF_RADIO     (1 << 20)
 297 #define ADM8211_SYNRF_CAL_EN    (1 << 19)
 298 #define ADM8211_SYNRF_PHYRST    (1 << 18)
 299
 300 #define ADM8211_SYNRF_IF_SELECT_0       (1 << 31)
 301 #define ADM8211_SYNRF_IF_SELECT_1       ((1 << 31) | (1 << 28))
 302 #define ADM8211_SYNRF_WRITE_SYNDATA_0   (1 << 31)
 303 #define ADM8211_SYNRF_WRITE_SYNDATA_1   ((1 << 31) | (1 << 26))
 304 #define ADM8211_SYNRF_WRITE_CLOCK_0     (1 << 31)
 305 #define ADM8211_SYNRF_WRITE_CLOCK_1     ((1 << 31) | (1 << 27))
 306
 307 /* CSR44 - WEPCTL (WEP Control) */
 308 #define ADM8211_WEPCTL_WEPENABLE   (1 << 31)
 309 #define ADM8211_WEPCTL_WPAENABLE   (1 << 30)
 310 #define ADM8211_WEPCTL_CURRENT_TABLE (1 << 29)
 311 #define ADM8211_WEPCTL_TABLE_WR (1 << 28)
 312 #define ADM8211_WEPCTL_TABLE_RD (1 << 27)
 313 #define ADM8211_WEPCTL_WEPRXBYP (1 << 25)
 314 #define ADM8211_WEPCTL_SEL_WEPTABLE (1 << 23)
 315 #define ADM8211_WEPCTL_ADDR     (0x000001ff)
 316
 317 /* CSR45 - WESK (Data Entry for Share/Individual Key) */
 318 #define ADM8211_WESK_DATA       (0x0000ffff)
 319
 320 /* FER (Function Event Register) */
 321 #define ADM8211_FER_INTR_EV_ENT (1 << 15)
 322
 323
 324 /* Si4126 RF Synthesizer - Control Registers */
 325 #define SI4126_MAIN_CONF        0
 326 #define SI4126_PHASE_DET_GAIN   1
 327 #define SI4126_POWERDOWN        2
 328 #define SI4126_RF1_N_DIV        3 /* only Si4136 */
 329 #define SI4126_RF2_N_DIV        4
 330 #define SI4126_IF_N_DIV         5
 331 #define SI4126_RF1_R_DIV        6 /* only Si4136 */
 332 #define SI4126_RF2_R_DIV        7
 333 #define SI4126_IF_R_DIV         8
 334
 335 /* Main Configuration */
 336 #define SI4126_MAIN_XINDIV2     (1 << 6)
 337 #define SI4126_MAIN_IFDIV       ((1 << 11) | (1 << 10))
 338 /* Powerdown */
 339 #define SI4126_POWERDOWN_PDIB   (1 << 1)
 340 #define SI4126_POWERDOWN_PDRB   (1 << 0)
 341
 342
 343 /* RF3000 BBP - Control Port Registers */
 344 /* 0x00 - reserved */
 345 #define RF3000_MODEM_CTRL__RX_STATUS 0x01
 346 #define RF3000_CCA_CTRL 0x02
 347 #define RF3000_DIVERSITY__RSSI 0x03
 348 #define RF3000_RX_SIGNAL_FIELD 0x04
 349 #define RF3000_RX_LEN_MSB 0x05
 350 #define RF3000_RX_LEN_LSB 0x06
 351 #define RF3000_RX_SERVICE_FIELD 0x07
 352 #define RF3000_TX_VAR_GAIN__TX_LEN_EXT 0x11
 353 #define RF3000_TX_LEN_MSB 0x12
 354 #define RF3000_TX_LEN_LSB 0x13
 355 #define RF3000_LOW_GAIN_CALIB 0x14
 356 #define RF3000_HIGH_GAIN_CALIB 0x15
 357
 358 /* ADM8211 revisions */
 359 #define ADM8211_REV_AB 0x11
 360 #define ADM8211_REV_AF 0x15
 361 #define ADM8211_REV_BA 0x20
 362 #define ADM8211_REV_CA 0x30
 363
 364 struct adm8211_desc {
 365         __le32 status;
 366         __le32 length;
 367         __le32 buffer1;
 368         __le32 buffer2;
 369 };
 370
 371 #define RDES0_STATUS_OWN        (1 << 31)
 372 #define RDES0_STATUS_ES         (1 << 30)
 373 #define RDES0_STATUS_SQL        (1 << 29)
 374 #define RDES0_STATUS_DE         (1 << 28)
 375 #define RDES0_STATUS_FS         (1 << 27)
 376 #define RDES0_STATUS_LS         (1 << 26)
 377 #define RDES0_STATUS_PCF        (1 << 25)
 378 #define RDES0_STATUS_SFDE       (1 << 24)
 379 #define RDES0_STATUS_SIGE       (1 << 23)
 380 #define RDES0_STATUS_CRC16E     (1 << 22)
 381 #define RDES0_STATUS_RXTOE      (1 << 21)
 382 #define RDES0_STATUS_CRC32E     (1 << 20)
 383 #define RDES0_STATUS_ICVE       (1 << 19)
 384 #define RDES0_STATUS_DA1        (1 << 17)
 385 #define RDES0_STATUS_DA0        (1 << 16)
 386 #define RDES0_STATUS_RXDR       ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12))
 387 #define RDES0_STATUS_FL         (0x00000fff)
 388
 389 #define RDES1_CONTROL_RER       (1 << 25)
 390 #define RDES1_CONTROL_RCH       (1 << 24)
 391 #define RDES1_CONTROL_RBS2      (0x00fff000)
 392 #define RDES1_CONTROL_RBS1      (0x00000fff)
 393
 394 #define RDES1_STATUS_RSSI       (0x0000007f)
 395
 396
 397 #define TDES0_CONTROL_OWN       (1 << 31)
 398 #define TDES0_CONTROL_DONE      (1 << 30)
 399 #define TDES0_CONTROL_TXDR      (0x0ff00000)
 400
 401 #define TDES0_STATUS_OWN        (1 << 31)
 402 #define TDES0_STATUS_DONE       (1 << 30)
 403 #define TDES0_STATUS_ES         (1 << 29)
 404 #define TDES0_STATUS_TLT        (1 << 28)
 405 #define TDES0_STATUS_TRT        (1 << 27)
 406 #define TDES0_STATUS_TUF        (1 << 26)
 407 #define TDES0_STATUS_TRO        (1 << 25)
 408 #define TDES0_STATUS_SOFBR      (1 << 24)
 409 #define TDES0_STATUS_ACR        (0x00000fff)
 410
 411 #define TDES1_CONTROL_IC        (1 << 31)
 412 #define TDES1_CONTROL_LS        (1 << 30)
 413 #define TDES1_CONTROL_FS        (1 << 29)
 414 #define TDES1_CONTROL_TER       (1 << 25)
 415 #define TDES1_CONTROL_TCH       (1 << 24)
 416 #define TDES1_CONTROL_RBS2      (0x00fff000)
 417 #define TDES1_CONTROL_RBS1      (0x00000fff)
 418
 419 /* SRAM offsets */
 420 #define ADM8211_SRAM(x) (priv->pdev->revision < ADM8211_REV_BA ? \
 421         ADM8211_SRAM_A_ ## x : ADM8211_SRAM_B_ ## x)
 422
 423 #define ADM8211_SRAM_INDIV_KEY   0x0000
 424 #define ADM8211_SRAM_A_SHARE_KEY 0x0160
 425 #define ADM8211_SRAM_B_SHARE_KEY 0x00c0
 426
 427 #define ADM8211_SRAM_A_SSID      0x0180
 428 #define ADM8211_SRAM_B_SSID      0x00d4
 429 #define ADM8211_SRAM_SSID ADM8211_SRAM(SSID)
 430
 431 #define ADM8211_SRAM_A_SUPP_RATE 0x0191
 432 #define ADM8211_SRAM_B_SUPP_RATE 0x00dd
 433 #define ADM8211_SRAM_SUPP_RATE ADM8211_SRAM(SUPP_RATE)
 434
 435 #define ADM8211_SRAM_A_SIZE      0x0200
 436 #define ADM8211_SRAM_B_SIZE      0x01c0
 437 #define ADM8211_SRAM_SIZE ADM8211_SRAM(SIZE)
 438
 439 struct adm8211_rx_ring_info {
 440         struct sk_buff *skb;
 441         dma_addr_t mapping;
 442 };
 443
 444 struct adm8211_tx_ring_info {
 445         struct sk_buff *skb;
 446         dma_addr_t mapping;
 447         size_t hdrlen;
 448 };
 449
 450 #define PLCP_SIGNAL_1M          0x0a
 451 #define PLCP_SIGNAL_2M          0x14
 452 #define PLCP_SIGNAL_5M5         0x37
 453 #define PLCP_SIGNAL_11M         0x6e
 454
 455 struct adm8211_tx_hdr {
 456         u8 da[6];
 457         u8 signal; /* PLCP signal / TX rate in 100 Kbps */
 458         u8 service;
 459         __le16 frame_body_size;
 460         __le16 frame_control;
 461         __le16 plcp_frag_tail_len;
 462         __le16 plcp_frag_head_len;
 463         __le16 dur_frag_tail;
 464         __le16 dur_frag_head;
 465         u8 addr4[6];
 466
 467 #define ADM8211_TXHDRCTL_SHORT_PREAMBLE         (1 <<  0)
 468 #define ADM8211_TXHDRCTL_MORE_FRAG              (1 <<  1)
 469 #define ADM8211_TXHDRCTL_MORE_DATA              (1 <<  2)
 470 #define ADM8211_TXHDRCTL_FRAG_NO                (1 <<  3) /* ? */
 471 #define ADM8211_TXHDRCTL_ENABLE_RTS             (1 <<  4)
 472 #define ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE      (1 <<  5)
 473 #define ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER   (1 << 15) /* ? */
 474         __le16 header_control;
 475         __le16 frag;
 476         u8 reserved_0;
 477         u8 retry_limit;
 478
 479         u32 wep2key0;
 480         u32 wep2key1;
 481         u32 wep2key2;
 482         u32 wep2key3;
 483
 484         u8 keyid;
 485         u8 entry_control;       // huh??
 486         u16 reserved_1;
 487         u32 reserved_2;
 488 } __packed;
 489
 490
 491 #define RX_COPY_BREAK 128
 492 #define RX_PKT_SIZE 2500
 493
 494 struct adm8211_eeprom {
 495         __le16  signature;              /* 0x00 */
 496         u8      major_version;          /* 0x02 */
 497         u8      minor_version;          /* 0x03 */
 498         u8      reserved_1[4];          /* 0x04 */
 499         u8      hwaddr[6];              /* 0x08 */
 500         u8      reserved_2[8];          /* 0x1E */
 501         __le16  cr49;                   /* 0x16 */
 502         u8      cr03;                   /* 0x18 */
 503         u8      cr28;                   /* 0x19 */
 504         u8      cr29;                   /* 0x1A */
 505         u8      country_code;           /* 0x1B */
 506
 507 /* specific bbp types */
 508 #define ADM8211_BBP_RFMD3000    0x00
 509 #define ADM8211_BBP_RFMD3002    0x01
 510 #define ADM8211_BBP_ADM8011     0x04
 511         u8      specific_bbptype;       /* 0x1C */
 512         u8      specific_rftype;        /* 0x1D */
 513         u8      reserved_3[2];          /* 0x1E */
 514         __le16  device_id;              /* 0x20 */
 515         __le16  vendor_id;              /* 0x22 */
 516         __le16  subsystem_id;           /* 0x24 */
 517         __le16  subsystem_vendor_id;    /* 0x26 */
 518         u8      maxlat;                 /* 0x28 */
 519         u8      mingnt;                 /* 0x29 */
 520         __le16  cis_pointer_low;        /* 0x2A */
 521         __le16  cis_pointer_high;       /* 0x2C */
 522         __le16  csr18;                  /* 0x2E */
 523         u8      reserved_4[16];         /* 0x30 */
 524         u8      d1_pwrdara;             /* 0x40 */
 525         u8      d0_pwrdara;             /* 0x41 */
 526         u8      d3_pwrdara;             /* 0x42 */
 527         u8      d2_pwrdara;             /* 0x43 */
 528         u8      antenna_power[14];      /* 0x44 */
 529         __le16  cis_wordcnt;            /* 0x52 */
 530         u8      tx_power[14];           /* 0x54 */
 531         u8      lpf_cutoff[14];         /* 0x62 */
 532         u8      lnags_threshold[14];    /* 0x70 */
 533         __le16  checksum;               /* 0x7E */
 534         u8      cis_data[0];            /* 0x80, 384 bytes */
 535 } __packed;
 536
 537 struct adm8211_priv {
 538         struct pci_dev *pdev;
 539         spinlock_t lock;
 540         struct adm8211_csr __iomem *map;
 541         struct adm8211_desc *rx_ring;
 542         struct adm8211_desc *tx_ring;
 543         dma_addr_t rx_ring_dma;
 544         dma_addr_t tx_ring_dma;
 545         struct adm8211_rx_ring_info *rx_buffers;
 546         struct adm8211_tx_ring_info *tx_buffers;
 547         unsigned int rx_ring_size, tx_ring_size;
 548         unsigned int cur_tx, dirty_tx, cur_rx;
 549
 550         struct ieee80211_low_level_stats stats;
 551         struct ieee80211_supported_band band;
 552         struct ieee80211_channel channels[14];
 553         int mode;
 554
 555         int channel;
 556         u8 bssid[ETH_ALEN];
 557
 558         u8 soft_rx_crc;
 559         u8 retry_limit;
 560
 561         u8 ant_power;
 562         u8 tx_power;
 563         u8 lpf_cutoff;
 564         u8 lnags_threshold;
 565         struct adm8211_eeprom *eeprom;
 566         size_t eeprom_len;
 567
 568         u32 nar;
 569
 570 #define ADM8211_TYPE_INTERSIL   0x00
 571 #define ADM8211_TYPE_RFMD       0x01
 572 #define ADM8211_TYPE_MARVEL     0x02
 573 #define ADM8211_TYPE_AIROHA     0x03
 574 #define ADM8211_TYPE_ADMTEK     0x05
 575         unsigned int rf_type:3;
 576         unsigned int bbp_type:3;
 577
 578         u8 specific_bbptype;
 579         enum {
 580                 ADM8211_RFMD2948 = 0x0,
 581                 ADM8211_RFMD2958 = 0x1,
 582                 ADM8211_RFMD2958_RF3000_CONTROL_POWER = 0x2,
 583                 ADM8211_MAX2820 = 0x8,
 584                 ADM8211_AL2210L = 0xC,  /* Airoha */
 585         } transceiver_type;
 586 };
 587
 588 struct ieee80211_chan_range {
 589         u8 min;
 590         u8 max;
 591 };
 592
 593 static const struct ieee80211_chan_range cranges[] = {
 594         {1,  11},       /* FCC */
 595         {1,  11},       /* IC */
 596         {1,  13},       /* ETSI */
 597         {10, 11},       /* SPAIN */
 598         {10, 13},       /* FRANCE */
 599         {14, 14},       /* MMK */
 600         {1,  14},       /* MMK2 */
 601 };
 602
 603 #endif /* ADM8211_H */