]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/net/wireless/ath/ar9170/phy.c
projects / mirror_ubuntu-zesty-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Fix common misspellings
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ar9170 / phy.c
1 /*
2 * Atheros AR9170 driver
3 *
4 * PHY and RF code
5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
21 *
22 * This file incorporates work covered by the following copyright and
23 * permission notice:
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
25 *
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37 */
38
39 #include <linux/bitrev.h>
40 #include "ar9170.h"
41 #include "cmd.h"
42
43 static int ar9170_init_power_cal(struct ar9170 *ar)
44 {
45 ar9170_regwrite_begin(ar);
46
47 ar9170_regwrite(0x1bc000 + 0x993c, 0x7f);
48 ar9170_regwrite(0x1bc000 + 0x9934, 0x3f3f3f3f);
49 ar9170_regwrite(0x1bc000 + 0x9938, 0x3f3f3f3f);
50 ar9170_regwrite(0x1bc000 + 0xa234, 0x3f3f3f3f);
51 ar9170_regwrite(0x1bc000 + 0xa238, 0x3f3f3f3f);
52 ar9170_regwrite(0x1bc000 + 0xa38c, 0x3f3f3f3f);
53 ar9170_regwrite(0x1bc000 + 0xa390, 0x3f3f3f3f);
54 ar9170_regwrite(0x1bc000 + 0xa3cc, 0x3f3f3f3f);
55 ar9170_regwrite(0x1bc000 + 0xa3d0, 0x3f3f3f3f);
56 ar9170_regwrite(0x1bc000 + 0xa3d4, 0x3f3f3f3f);
57
58 ar9170_regwrite_finish();
59 return ar9170_regwrite_result();
60 }
61
62 struct ar9170_phy_init {
63 u32 reg, _5ghz_20, _5ghz_40, _2ghz_40, _2ghz_20;
64 };
65
66 static struct ar9170_phy_init ar5416_phy_init[] = {
67 { 0x1c5800, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
68 { 0x1c5804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, },
69 { 0x1c5808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
70 { 0x1c580c, 0xad848e19, 0xad848e19, 0xad848e19, 0xad848e19, },
71 { 0x1c5810, 0x7d14e000, 0x7d14e000, 0x7d14e000, 0x7d14e000, },
72 { 0x1c5814, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, },
73 { 0x1c5818, 0x00000090, 0x00000090, 0x00000090, 0x00000090, },
74 { 0x1c581c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
75 { 0x1c5820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, },
76 { 0x1c5824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, },
77 { 0x1c5828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, },
78 { 0x1c582c, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, },
79 { 0x1c5830, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
80 { 0x1c5834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, },
81 { 0x1c5838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
82 { 0x1c583c, 0x00200400, 0x00200400, 0x00200400, 0x00200400, },
83 { 0x1c5840, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e, },
84 { 0x1c5844, 0x1372161e, 0x13721c1e, 0x13721c24, 0x137216a4, },
85 { 0x1c5848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, },
86 { 0x1c584c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, },
87 { 0x1c5850, 0x6c48b4e4, 0x6c48b4e4, 0x6c48b0e4, 0x6c48b0e4, },
88 { 0x1c5854, 0x00000859, 0x00000859, 0x00000859, 0x00000859, },
89 { 0x1c5858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, },
90 { 0x1c585c, 0x31395c5e, 0x31395c5e, 0x31395c5e, 0x31395c5e, },
91 { 0x1c5860, 0x0004dd10, 0x0004dd10, 0x0004dd20, 0x0004dd20, },
92 { 0x1c5868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, },
93 { 0x1c586c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, },
94 { 0x1c5900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
95 { 0x1c5904, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
96 { 0x1c5908, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
97 { 0x1c590c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
98 { 0x1c5914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, },
99 { 0x1c5918, 0x00000118, 0x00000230, 0x00000268, 0x00000134, },
100 { 0x1c591c, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff, },
101 { 0x1c5920, 0x0510081c, 0x0510081c, 0x0510001c, 0x0510001c, },
102 { 0x1c5924, 0xd0058a15, 0xd0058a15, 0xd0058a15, 0xd0058a15, },
103 { 0x1c5928, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
104 { 0x1c592c, 0x00000004, 0x00000004, 0x00000004, 0x00000004, },
105 { 0x1c5934, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
106 { 0x1c5938, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
107 { 0x1c593c, 0x0000007f, 0x0000007f, 0x0000007f, 0x0000007f, },
108 { 0x1c5944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, },
109 { 0x1c5948, 0x9280b212, 0x9280b212, 0x9280b212, 0x9280b212, },
110 { 0x1c594c, 0x00020028, 0x00020028, 0x00020028, 0x00020028, },
111 { 0x1c5954, 0x5d50e188, 0x5d50e188, 0x5d50e188, 0x5d50e188, },
112 { 0x1c5958, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, },
113 { 0x1c5960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
114 { 0x1c5964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, },
115 { 0x1c5970, 0x190fb515, 0x190fb515, 0x190fb515, 0x190fb515, },
116 { 0x1c5974, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
117 { 0x1c5978, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
118 { 0x1c597c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
119 { 0x1c5980, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
120 { 0x1c5984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
121 { 0x1c5988, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
122 { 0x1c598c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
123 { 0x1c5990, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
124 { 0x1c5994, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
125 { 0x1c5998, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
126 { 0x1c599c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
127 { 0x1c59a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
128 { 0x1c59a4, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
129 { 0x1c59a8, 0x001fff00, 0x001fff00, 0x001fff00, 0x001fff00, },
130 { 0x1c59ac, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0x006f00c4, },
131 { 0x1c59b0, 0x03051000, 0x03051000, 0x03051000, 0x03051000, },
132 { 0x1c59b4, 0x00000820, 0x00000820, 0x00000820, 0x00000820, },
133 { 0x1c59c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, },
134 { 0x1c59c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, },
135 { 0x1c59c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, },
136 { 0x1c59cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, },
137 { 0x1c59d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, },
138 { 0x1c59d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
139 { 0x1c59d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
140 { 0x1c59dc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
141 { 0x1c59e0, 0x00000200, 0x00000200, 0x00000200, 0x00000200, },
142 { 0x1c59e4, 0x64646464, 0x64646464, 0x64646464, 0x64646464, },
143 { 0x1c59e8, 0x3c787878, 0x3c787878, 0x3c787878, 0x3c787878, },
144 { 0x1c59ec, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, },
145 { 0x1c59f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
146 { 0x1c59fc, 0x00001042, 0x00001042, 0x00001042, 0x00001042, },
147 { 0x1c5a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
148 { 0x1c5a04, 0x00000040, 0x00000040, 0x00000040, 0x00000040, },
149 { 0x1c5a08, 0x00000080, 0x00000080, 0x00000080, 0x00000080, },
150 { 0x1c5a0c, 0x000001a1, 0x000001a1, 0x00000141, 0x00000141, },
151 { 0x1c5a10, 0x000001e1, 0x000001e1, 0x00000181, 0x00000181, },
152 { 0x1c5a14, 0x00000021, 0x00000021, 0x000001c1, 0x000001c1, },
153 { 0x1c5a18, 0x00000061, 0x00000061, 0x00000001, 0x00000001, },
154 { 0x1c5a1c, 0x00000168, 0x00000168, 0x00000041, 0x00000041, },
155 { 0x1c5a20, 0x000001a8, 0x000001a8, 0x000001a8, 0x000001a8, },
156 { 0x1c5a24, 0x000001e8, 0x000001e8, 0x000001e8, 0x000001e8, },
157 { 0x1c5a28, 0x00000028, 0x00000028, 0x00000028, 0x00000028, },
158 { 0x1c5a2c, 0x00000068, 0x00000068, 0x00000068, 0x00000068, },
159 { 0x1c5a30, 0x00000189, 0x00000189, 0x000000a8, 0x000000a8, },
160 { 0x1c5a34, 0x000001c9, 0x000001c9, 0x00000169, 0x00000169, },
161 { 0x1c5a38, 0x00000009, 0x00000009, 0x000001a9, 0x000001a9, },
162 { 0x1c5a3c, 0x00000049, 0x00000049, 0x000001e9, 0x000001e9, },
163 { 0x1c5a40, 0x00000089, 0x00000089, 0x00000029, 0x00000029, },
164 { 0x1c5a44, 0x00000170, 0x00000170, 0x00000069, 0x00000069, },
165 { 0x1c5a48, 0x000001b0, 0x000001b0, 0x00000190, 0x00000190, },
166 { 0x1c5a4c, 0x000001f0, 0x000001f0, 0x000001d0, 0x000001d0, },
167 { 0x1c5a50, 0x00000030, 0x00000030, 0x00000010, 0x00000010, },
168 { 0x1c5a54, 0x00000070, 0x00000070, 0x00000050, 0x00000050, },
169 { 0x1c5a58, 0x00000191, 0x00000191, 0x00000090, 0x00000090, },
170 { 0x1c5a5c, 0x000001d1, 0x000001d1, 0x00000151, 0x00000151, },
171 { 0x1c5a60, 0x00000011, 0x00000011, 0x00000191, 0x00000191, },
172 { 0x1c5a64, 0x00000051, 0x00000051, 0x000001d1, 0x000001d1, },
173 { 0x1c5a68, 0x00000091, 0x00000091, 0x00000011, 0x00000011, },
174 { 0x1c5a6c, 0x000001b8, 0x000001b8, 0x00000051, 0x00000051, },
175 { 0x1c5a70, 0x000001f8, 0x000001f8, 0x00000198, 0x00000198, },
176 { 0x1c5a74, 0x00000038, 0x00000038, 0x000001d8, 0x000001d8, },
177 { 0x1c5a78, 0x00000078, 0x00000078, 0x00000018, 0x00000018, },
178 { 0x1c5a7c, 0x00000199, 0x00000199, 0x00000058, 0x00000058, },
179 { 0x1c5a80, 0x000001d9, 0x000001d9, 0x00000098, 0x00000098, },
180 { 0x1c5a84, 0x00000019, 0x00000019, 0x00000159, 0x00000159, },
181 { 0x1c5a88, 0x00000059, 0x00000059, 0x00000199, 0x00000199, },
182 { 0x1c5a8c, 0x00000099, 0x00000099, 0x000001d9, 0x000001d9, },
183 { 0x1c5a90, 0x000000d9, 0x000000d9, 0x00000019, 0x00000019, },
184 { 0x1c5a94, 0x000000f9, 0x000000f9, 0x00000059, 0x00000059, },
185 { 0x1c5a98, 0x000000f9, 0x000000f9, 0x00000099, 0x00000099, },
186 { 0x1c5a9c, 0x000000f9, 0x000000f9, 0x000000d9, 0x000000d9, },
187 { 0x1c5aa0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
188 { 0x1c5aa4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
189 { 0x1c5aa8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
190 { 0x1c5aac, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
191 { 0x1c5ab0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
192 { 0x1c5ab4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
193 { 0x1c5ab8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
194 { 0x1c5abc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
195 { 0x1c5ac0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
196 { 0x1c5ac4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
197 { 0x1c5ac8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
198 { 0x1c5acc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
199 { 0x1c5ad0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
200 { 0x1c5ad4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
201 { 0x1c5ad8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
202 { 0x1c5adc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
203 { 0x1c5ae0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
204 { 0x1c5ae4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
205 { 0x1c5ae8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
206 { 0x1c5aec, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
207 { 0x1c5af0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
208 { 0x1c5af4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
209 { 0x1c5af8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
210 { 0x1c5afc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
211 { 0x1c5b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
212 { 0x1c5b04, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
213 { 0x1c5b08, 0x00000002, 0x00000002, 0x00000002, 0x00000002, },
214 { 0x1c5b0c, 0x00000003, 0x00000003, 0x00000003, 0x00000003, },
215 { 0x1c5b10, 0x00000004, 0x00000004, 0x00000004, 0x00000004, },
216 { 0x1c5b14, 0x00000005, 0x00000005, 0x00000005, 0x00000005, },
217 { 0x1c5b18, 0x00000008, 0x00000008, 0x00000008, 0x00000008, },
218 { 0x1c5b1c, 0x00000009, 0x00000009, 0x00000009, 0x00000009, },
219 { 0x1c5b20, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, },
220 { 0x1c5b24, 0x0000000b, 0x0000000b, 0x0000000b, 0x0000000b, },
221 { 0x1c5b28, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, },
222 { 0x1c5b2c, 0x0000000d, 0x0000000d, 0x0000000d, 0x0000000d, },
223 { 0x1c5b30, 0x00000010, 0x00000010, 0x00000010, 0x00000010, },
224 { 0x1c5b34, 0x00000011, 0x00000011, 0x00000011, 0x00000011, },
225 { 0x1c5b38, 0x00000012, 0x00000012, 0x00000012, 0x00000012, },
226 { 0x1c5b3c, 0x00000013, 0x00000013, 0x00000013, 0x00000013, },
227 { 0x1c5b40, 0x00000014, 0x00000014, 0x00000014, 0x00000014, },
228 { 0x1c5b44, 0x00000015, 0x00000015, 0x00000015, 0x00000015, },
229 { 0x1c5b48, 0x00000018, 0x00000018, 0x00000018, 0x00000018, },
230 { 0x1c5b4c, 0x00000019, 0x00000019, 0x00000019, 0x00000019, },
231 { 0x1c5b50, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, },
232 { 0x1c5b54, 0x0000001b, 0x0000001b, 0x0000001b, 0x0000001b, },
233 { 0x1c5b58, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, },
234 { 0x1c5b5c, 0x0000001d, 0x0000001d, 0x0000001d, 0x0000001d, },
235 { 0x1c5b60, 0x00000020, 0x00000020, 0x00000020, 0x00000020, },
236 { 0x1c5b64, 0x00000021, 0x00000021, 0x00000021, 0x00000021, },
237 { 0x1c5b68, 0x00000022, 0x00000022, 0x00000022, 0x00000022, },
238 { 0x1c5b6c, 0x00000023, 0x00000023, 0x00000023, 0x00000023, },
239 { 0x1c5b70, 0x00000024, 0x00000024, 0x00000024, 0x00000024, },
240 { 0x1c5b74, 0x00000025, 0x00000025, 0x00000025, 0x00000025, },
241 { 0x1c5b78, 0x00000028, 0x00000028, 0x00000028, 0x00000028, },
242 { 0x1c5b7c, 0x00000029, 0x00000029, 0x00000029, 0x00000029, },
243 { 0x1c5b80, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a, },
244 { 0x1c5b84, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, },
245 { 0x1c5b88, 0x0000002c, 0x0000002c, 0x0000002c, 0x0000002c, },
246 { 0x1c5b8c, 0x0000002d, 0x0000002d, 0x0000002d, 0x0000002d, },
247 { 0x1c5b90, 0x00000030, 0x00000030, 0x00000030, 0x00000030, },
248 { 0x1c5b94, 0x00000031, 0x00000031, 0x00000031, 0x00000031, },
249 { 0x1c5b98, 0x00000032, 0x00000032, 0x00000032, 0x00000032, },
250 { 0x1c5b9c, 0x00000033, 0x00000033, 0x00000033, 0x00000033, },
251 { 0x1c5ba0, 0x00000034, 0x00000034, 0x00000034, 0x00000034, },
252 { 0x1c5ba4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
253 { 0x1c5ba8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
254 { 0x1c5bac, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
255 { 0x1c5bb0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
256 { 0x1c5bb4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
257 { 0x1c5bb8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
258 { 0x1c5bbc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
259 { 0x1c5bc0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
260 { 0x1c5bc4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
261 { 0x1c5bc8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
262 { 0x1c5bcc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
263 { 0x1c5bd0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
264 { 0x1c5bd4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
265 { 0x1c5bd8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
266 { 0x1c5bdc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
267 { 0x1c5be0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
268 { 0x1c5be4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
269 { 0x1c5be8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
270 { 0x1c5bec, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
271 { 0x1c5bf0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
272 { 0x1c5bf4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
273 { 0x1c5bf8, 0x00000010, 0x00000010, 0x00000010, 0x00000010, },
274 { 0x1c5bfc, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, },
275 { 0x1c5c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
276 { 0x1c5c0c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
277 { 0x1c5c10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
278 { 0x1c5c14, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
279 { 0x1c5c18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
280 { 0x1c5c1c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
281 { 0x1c5c20, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
282 { 0x1c5c24, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
283 { 0x1c5c28, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
284 { 0x1c5c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
285 { 0x1c5c30, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
286 { 0x1c5c34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
287 { 0x1c5c38, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
288 { 0x1c5c3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
289 { 0x1c5cf0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
290 { 0x1c5cf4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
291 { 0x1c5cf8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
292 { 0x1c5cfc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
293 { 0x1c6200, 0x00000008, 0x00000008, 0x0000000e, 0x0000000e, },
294 { 0x1c6204, 0x00000440, 0x00000440, 0x00000440, 0x00000440, },
295 { 0x1c6208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, },
296 { 0x1c620c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
297 { 0x1c6210, 0x40806333, 0x40806333, 0x40806333, 0x40806333, },
298 { 0x1c6214, 0x00106c10, 0x00106c10, 0x00106c10, 0x00106c10, },
299 { 0x1c6218, 0x009c4060, 0x009c4060, 0x009c4060, 0x009c4060, },
300 { 0x1c621c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, },
301 { 0x1c6220, 0x018830c6, 0x018830c6, 0x018830c6, 0x018830c6, },
302 { 0x1c6224, 0x00000400, 0x00000400, 0x00000400, 0x00000400, },
303 { 0x1c6228, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, },
304 { 0x1c622c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
305 { 0x1c6230, 0x00000108, 0x00000210, 0x00000210, 0x00000108, },
306 { 0x1c6234, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
307 { 0x1c6238, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
308 { 0x1c623c, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, },
309 { 0x1c6240, 0x38490a20, 0x38490a20, 0x38490a20, 0x38490a20, },
310 { 0x1c6244, 0x00007bb6, 0x00007bb6, 0x00007bb6, 0x00007bb6, },
311 { 0x1c6248, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, },
312 { 0x1c624c, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
313 { 0x1c6250, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, },
314 { 0x1c6254, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
315 { 0x1c6258, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, },
316 { 0x1c625c, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, },
317 { 0x1c6260, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, },
318 { 0x1c6264, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, },
319 { 0x1c6268, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
320 { 0x1c626c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
321 { 0x1c6274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, },
322 { 0x1c6278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
323 { 0x1c627c, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, },
324 { 0x1c6300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, },
325 { 0x1c6304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, },
326 { 0x1c6308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, },
327 { 0x1c630c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, },
328 { 0x1c6310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, },
329 { 0x1c6314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, },
330 { 0x1c6318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, },
331 { 0x1c631c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, },
332 { 0x1c6320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, },
333 { 0x1c6324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, },
334 { 0x1c6328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, },
335 { 0x1c632c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
336 { 0x1c6330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
337 { 0x1c6334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
338 { 0x1c6338, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
339 { 0x1c633c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
340 { 0x1c6340, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
341 { 0x1c6344, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
342 { 0x1c6348, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
343 { 0x1c634c, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
344 { 0x1c6350, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
345 { 0x1c6354, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, },
346 { 0x1c6358, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, },
347 { 0x1c6388, 0x08000000, 0x08000000, 0x08000000, 0x08000000, },
348 { 0x1c638c, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
349 { 0x1c6390, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
350 { 0x1c6394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
351 { 0x1c6398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, },
352 { 0x1c639c, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
353 { 0x1c63a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
354 { 0x1c63a4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
355 { 0x1c63a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
356 { 0x1c63ac, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
357 { 0x1c63b0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
358 { 0x1c63b4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
359 { 0x1c63b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
360 { 0x1c63bc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
361 { 0x1c63c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
362 { 0x1c63c4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
363 { 0x1c63c8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
364 { 0x1c63cc, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
365 { 0x1c63d0, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
366 { 0x1c63d4, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
367 { 0x1c63d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
368 { 0x1c63dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
369 { 0x1c63e0, 0x000000c0, 0x000000c0, 0x000000c0, 0x000000c0, },
370 { 0x1c6848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, },
371 { 0x1c6920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, },
372 { 0x1c6960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
373 { 0x1c720c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
374 { 0x1c726c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
375 { 0x1c7848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, },
376 { 0x1c7920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, },
377 { 0x1c7960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
378 { 0x1c820c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
379 { 0x1c826c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
380 /* { 0x1c8864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, }, */
381 { 0x1c8864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, },
382 { 0x1c895c, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, },
383 { 0x1c8968, 0x000003ce, 0x000003ce, 0x000003ce, 0x000003ce, },
384 { 0x1c89bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, },
385 { 0x1c9270, 0x00820820, 0x00820820, 0x00820820, 0x00820820, },
386 { 0x1c935c, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, },
387 { 0x1c9360, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, },
388 { 0x1c9364, 0x17601685, 0x17601685, 0x17601685, 0x17601685, },
389 { 0x1c9368, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, },
390 { 0x1c936c, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, },
391 { 0x1c9370, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, },
392 { 0x1c9374, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, },
393 { 0x1c9378, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, },
394 { 0x1c937c, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, },
395 { 0x1c9380, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, },
396 { 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, }
397 };
398
399 /*
400 * look up a certain register in ar5416_phy_init[] and return the init. value
401 * for the band and bandwidth given. Return 0 if register address not found.
402 */
403 static u32 ar9170_get_default_phy_reg_val(u32 reg, bool is_2ghz, bool is_40mhz)
404 {
405 unsigned int i;
406 for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
407 if (ar5416_phy_init[i].reg != reg)
408 continue;
409
410 if (is_2ghz) {
411 if (is_40mhz)
412 return ar5416_phy_init[i]._2ghz_40;
413 else
414 return ar5416_phy_init[i]._2ghz_20;
415 } else {
416 if (is_40mhz)
417 return ar5416_phy_init[i]._5ghz_40;
418 else
419 return ar5416_phy_init[i]._5ghz_20;
420 }
421 }
422 return 0;
423 }
424
425 /*
426 * initialize some phy regs from eeprom values in modal_header[]
427 * acc. to band and bandwidth
428 */
429 static int ar9170_init_phy_from_eeprom(struct ar9170 *ar,
430 bool is_2ghz, bool is_40mhz)
431 {
432 static const u8 xpd2pd[16] = {
433 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2,
434 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
435 };
436 u32 defval, newval;
437 /* pointer to the modal_header acc. to band */
438 struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz];
439
440 ar9170_regwrite_begin(ar);
441
442 /* ant common control (index 0) */
443 newval = le32_to_cpu(m->antCtrlCommon);
444 ar9170_regwrite(0x1c5964, newval);
445
446 /* ant control chain 0 (index 1) */
447 newval = le32_to_cpu(m->antCtrlChain[0]);
448 ar9170_regwrite(0x1c5960, newval);
449
450 /* ant control chain 2 (index 2) */
451 newval = le32_to_cpu(m->antCtrlChain[1]);
452 ar9170_regwrite(0x1c7960, newval);
453
454 /* SwSettle (index 3) */
455 if (!is_40mhz) {
456 defval = ar9170_get_default_phy_reg_val(0x1c5844,
457 is_2ghz, is_40mhz);
458 newval = (defval & ~0x3f80) |
459 ((m->switchSettling & 0x7f) << 7);
460 ar9170_regwrite(0x1c5844, newval);
461 }
462
463 /* adcDesired, pdaDesired (index 4) */
464 defval = ar9170_get_default_phy_reg_val(0x1c5850, is_2ghz, is_40mhz);
465 newval = (defval & ~0xffff) | ((u8)m->pgaDesiredSize << 8) |
466 ((u8)m->adcDesiredSize);
467 ar9170_regwrite(0x1c5850, newval);
468
469 /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */
470 defval = ar9170_get_default_phy_reg_val(0x1c5834, is_2ghz, is_40mhz);
471 newval = (m->txEndToXpaOff << 24) | (m->txEndToXpaOff << 16) |
472 (m->txFrameToXpaOn << 8) | m->txFrameToXpaOn;
473 ar9170_regwrite(0x1c5834, newval);
474
475 /* TxEndToRxOn (index 6) */
476 defval = ar9170_get_default_phy_reg_val(0x1c5828, is_2ghz, is_40mhz);
477 newval = (defval & ~0xff0000) | (m->txEndToRxOn << 16);
478 ar9170_regwrite(0x1c5828, newval);
479
480 /* thresh62 (index 7) */
481 defval = ar9170_get_default_phy_reg_val(0x1c8864, is_2ghz, is_40mhz);
482 newval = (defval & ~0x7f000) | (m->thresh62 << 12);
483 ar9170_regwrite(0x1c8864, newval);
484
485 /* tx/rx attenuation chain 0 (index 8) */
486 defval = ar9170_get_default_phy_reg_val(0x1c5848, is_2ghz, is_40mhz);
487 newval = (defval & ~0x3f000) | ((m->txRxAttenCh[0] & 0x3f) << 12);
488 ar9170_regwrite(0x1c5848, newval);
489
490 /* tx/rx attenuation chain 2 (index 9) */
491 defval = ar9170_get_default_phy_reg_val(0x1c7848, is_2ghz, is_40mhz);
492 newval = (defval & ~0x3f000) | ((m->txRxAttenCh[1] & 0x3f) << 12);
493 ar9170_regwrite(0x1c7848, newval);
494
495 /* tx/rx margin chain 0 (index 10) */
496 defval = ar9170_get_default_phy_reg_val(0x1c620c, is_2ghz, is_40mhz);
497 newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[0] & 0x3f) << 18);
498 /* bsw margin chain 0 for 5GHz only */
499 if (!is_2ghz)
500 newval = (newval & ~0x3c00) | ((m->bswMargin[0] & 0xf) << 10);
501 ar9170_regwrite(0x1c620c, newval);
502
503 /* tx/rx margin chain 2 (index 11) */
504 defval = ar9170_get_default_phy_reg_val(0x1c820c, is_2ghz, is_40mhz);
505 newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[1] & 0x3f) << 18);
506 ar9170_regwrite(0x1c820c, newval);
507
508 /* iqCall, iqCallq chain 0 (index 12) */
509 defval = ar9170_get_default_phy_reg_val(0x1c5920, is_2ghz, is_40mhz);
510 newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[0] & 0x3f) << 5) |
511 ((u8)m->iqCalQCh[0] & 0x1f);
512 ar9170_regwrite(0x1c5920, newval);
513
514 /* iqCall, iqCallq chain 2 (index 13) */
515 defval = ar9170_get_default_phy_reg_val(0x1c7920, is_2ghz, is_40mhz);
516 newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[1] & 0x3f) << 5) |
517 ((u8)m->iqCalQCh[1] & 0x1f);
518 ar9170_regwrite(0x1c7920, newval);
519
520 /* xpd gain mask (index 14) */
521 defval = ar9170_get_default_phy_reg_val(0x1c6258, is_2ghz, is_40mhz);
522 newval = (defval & ~0xf0000) | (xpd2pd[m->xpdGain & 0xf] << 16);
523 ar9170_regwrite(0x1c6258, newval);
524 ar9170_regwrite_finish();
525
526 return ar9170_regwrite_result();
527 }
528
529 int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
530 {
531 int i, err;
532 u32 val;
533 bool is_2ghz = band == IEEE80211_BAND_2GHZ;
534 bool is_40mhz = conf_is_ht40(&ar->hw->conf);
535
536 ar9170_regwrite_begin(ar);
537
538 for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
539 if (is_40mhz) {
540 if (is_2ghz)
541 val = ar5416_phy_init[i]._2ghz_40;
542 else
543 val = ar5416_phy_init[i]._5ghz_40;
544 } else {
545 if (is_2ghz)
546 val = ar5416_phy_init[i]._2ghz_20;
547 else
548 val = ar5416_phy_init[i]._5ghz_20;
549 }
550
551 ar9170_regwrite(ar5416_phy_init[i].reg, val);
552 }
553
554 ar9170_regwrite_finish();
555 err = ar9170_regwrite_result();
556 if (err)
557 return err;
558
559 err = ar9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
560 if (err)
561 return err;
562
563 err = ar9170_init_power_cal(ar);
564 if (err)
565 return err;
566
567 /* XXX: remove magic! */
568 if (is_2ghz)
569 err = ar9170_write_reg(ar, 0x1d4014, 0x5163);
570 else
571 err = ar9170_write_reg(ar, 0x1d4014, 0x5143);
572
573 return err;
574 }
575
576 struct ar9170_rf_init {
577 u32 reg, _5ghz, _2ghz;
578 };
579
580 static struct ar9170_rf_init ar9170_rf_init[] = {
581 /* bank 0 */
582 { 0x1c58b0, 0x1e5795e5, 0x1e5795e5},
583 { 0x1c58e0, 0x02008020, 0x02008020},
584 /* bank 1 */
585 { 0x1c58b0, 0x02108421, 0x02108421},
586 { 0x1c58ec, 0x00000008, 0x00000008},
587 /* bank 2 */
588 { 0x1c58b0, 0x0e73ff17, 0x0e73ff17},
589 { 0x1c58e0, 0x00000420, 0x00000420},
590 /* bank 3 */
591 { 0x1c58f0, 0x01400018, 0x01c00018},
592 /* bank 4 */
593 { 0x1c58b0, 0x000001a1, 0x000001a1},
594 { 0x1c58e8, 0x00000001, 0x00000001},
595 /* bank 5 */
596 { 0x1c58b0, 0x00000013, 0x00000013},
597 { 0x1c58e4, 0x00000002, 0x00000002},
598 /* bank 6 */
599 { 0x1c58b0, 0x00000000, 0x00000000},
600 { 0x1c58b0, 0x00000000, 0x00000000},
601 { 0x1c58b0, 0x00000000, 0x00000000},
602 { 0x1c58b0, 0x00000000, 0x00000000},
603 { 0x1c58b0, 0x00000000, 0x00000000},
604 { 0x1c58b0, 0x00004000, 0x00004000},
605 { 0x1c58b0, 0x00006c00, 0x00006c00},
606 { 0x1c58b0, 0x00002c00, 0x00002c00},
607 { 0x1c58b0, 0x00004800, 0x00004800},
608 { 0x1c58b0, 0x00004000, 0x00004000},
609 { 0x1c58b0, 0x00006000, 0x00006000},
610 { 0x1c58b0, 0x00001000, 0x00001000},
611 { 0x1c58b0, 0x00004000, 0x00004000},
612 { 0x1c58b0, 0x00007c00, 0x00007c00},
613 { 0x1c58b0, 0x00007c00, 0x00007c00},
614 { 0x1c58b0, 0x00007c00, 0x00007c00},
615 { 0x1c58b0, 0x00007c00, 0x00007c00},
616 { 0x1c58b0, 0x00007c00, 0x00007c00},
617 { 0x1c58b0, 0x00087c00, 0x00087c00},
618 { 0x1c58b0, 0x00007c00, 0x00007c00},
619 { 0x1c58b0, 0x00005400, 0x00005400},
620 { 0x1c58b0, 0x00000c00, 0x00000c00},
621 { 0x1c58b0, 0x00001800, 0x00001800},
622 { 0x1c58b0, 0x00007c00, 0x00007c00},
623 { 0x1c58b0, 0x00006c00, 0x00006c00},
624 { 0x1c58b0, 0x00006c00, 0x00006c00},
625 { 0x1c58b0, 0x00007c00, 0x00007c00},
626 { 0x1c58b0, 0x00002c00, 0x00002c00},
627 { 0x1c58b0, 0x00003c00, 0x00003c00},
628 { 0x1c58b0, 0x00003800, 0x00003800},
629 { 0x1c58b0, 0x00001c00, 0x00001c00},
630 { 0x1c58b0, 0x00000800, 0x00000800},
631 { 0x1c58b0, 0x00000408, 0x00000408},
632 { 0x1c58b0, 0x00004c15, 0x00004c15},
633 { 0x1c58b0, 0x00004188, 0x00004188},
634 { 0x1c58b0, 0x0000201e, 0x0000201e},
635 { 0x1c58b0, 0x00010408, 0x00010408},
636 { 0x1c58b0, 0x00000801, 0x00000801},
637 { 0x1c58b0, 0x00000c08, 0x00000c08},
638 { 0x1c58b0, 0x0000181e, 0x0000181e},
639 { 0x1c58b0, 0x00001016, 0x00001016},
640 { 0x1c58b0, 0x00002800, 0x00002800},
641 { 0x1c58b0, 0x00004010, 0x00004010},
642 { 0x1c58b0, 0x0000081c, 0x0000081c},
643 { 0x1c58b0, 0x00000115, 0x00000115},
644 { 0x1c58b0, 0x00000015, 0x00000015},
645 { 0x1c58b0, 0x00000066, 0x00000066},
646 { 0x1c58b0, 0x0000001c, 0x0000001c},
647 { 0x1c58b0, 0x00000000, 0x00000000},
648 { 0x1c58b0, 0x00000004, 0x00000004},
649 { 0x1c58b0, 0x00000015, 0x00000015},
650 { 0x1c58b0, 0x0000001f, 0x0000001f},
651 { 0x1c58e0, 0x00000000, 0x00000400},
652 /* bank 7 */
653 { 0x1c58b0, 0x000000a0, 0x000000a0},
654 { 0x1c58b0, 0x00000000, 0x00000000},
655 { 0x1c58b0, 0x00000040, 0x00000040},
656 { 0x1c58f0, 0x0000001c, 0x0000001c},
657 };
658
659 static int ar9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz)
660 {
661 int err, i;
662
663 ar9170_regwrite_begin(ar);
664
665 for (i = 0; i < ARRAY_SIZE(ar9170_rf_init); i++)
666 ar9170_regwrite(ar9170_rf_init[i].reg,
667 band5ghz ? ar9170_rf_init[i]._5ghz
668 : ar9170_rf_init[i]._2ghz);
669
670 ar9170_regwrite_finish();
671 err = ar9170_regwrite_result();
672 if (err)
673 wiphy_err(ar->hw->wiphy, "rf init failed\n");
674 return err;
675 }
676
677 static int ar9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz,
678 u32 freq, enum ar9170_bw bw)
679 {
680 int err;
681 u32 d0, d1, td0, td1, fd0, fd1;
682 u8 chansel;
683 u8 refsel0 = 1, refsel1 = 0;
684 u8 lf_synth = 0;
685
686 switch (bw) {
687 case AR9170_BW_40_ABOVE:
688 freq += 10;
689 break;
690 case AR9170_BW_40_BELOW:
691 freq -= 10;
692 break;
693 case AR9170_BW_20:
694 break;
695 case __AR9170_NUM_BW:
696 BUG();
697 }
698
699 if (band5ghz) {
700 if (freq % 10) {
701 chansel = (freq - 4800) / 5;
702 } else {
703 chansel = ((freq - 4800) / 10) * 2;
704 refsel0 = 0;
705 refsel1 = 1;
706 }
707 chansel = byte_rev_table[chansel];
708 } else {
709 if (freq == 2484) {
710 chansel = 10 + (freq - 2274) / 5;
711 lf_synth = 1;
712 } else
713 chansel = 16 + (freq - 2272) / 5;
714 chansel *= 4;
715 chansel = byte_rev_table[chansel];
716 }
717
718 d1 = chansel;
719 d0 = 0x21 |
720 refsel0 << 3 |
721 refsel1 << 2 |
722 lf_synth << 1;
723 td0 = d0 & 0x1f;
724 td1 = d1 & 0x1f;
725 fd0 = td1 << 5 | td0;
726
727 td0 = (d0 >> 5) & 0x7;
728 td1 = (d1 >> 5) & 0x7;
729 fd1 = td1 << 5 | td0;
730
731 ar9170_regwrite_begin(ar);
732
733 ar9170_regwrite(0x1c58b0, fd0);
734 ar9170_regwrite(0x1c58e8, fd1);
735
736 ar9170_regwrite_finish();
737 err = ar9170_regwrite_result();
738 if (err)
739 return err;
740
741 msleep(10);
742
743 return 0;
744 }
745
746 struct ar9170_phy_freq_params {
747 u8 coeff_exp;
748 u16 coeff_man;
749 u8 coeff_exp_shgi;
750 u16 coeff_man_shgi;
751 };
752
753 struct ar9170_phy_freq_entry {
754 u16 freq;
755 struct ar9170_phy_freq_params params[__AR9170_NUM_BW];
756 };
757
758 /* NB: must be in sync with channel tables in main! */
759 static const struct ar9170_phy_freq_entry ar9170_phy_freq_params[] = {
760 /*
761 * freq,
762 * 20MHz,
763 * 40MHz (below),
764 * 40Mhz (above),
765 */
766 { 2412, {
767 { 3, 21737, 3, 19563, },
768 { 3, 21827, 3, 19644, },
769 { 3, 21647, 3, 19482, },
770 } },
771 { 2417, {
772 { 3, 21692, 3, 19523, },
773 { 3, 21782, 3, 19604, },
774 { 3, 21602, 3, 19442, },
775 } },
776 { 2422, {
777 { 3, 21647, 3, 19482, },
778 { 3, 21737, 3, 19563, },
779 { 3, 21558, 3, 19402, },
780 } },
781 { 2427, {
782 { 3, 21602, 3, 19442, },
783 { 3, 21692, 3, 19523, },
784 { 3, 21514, 3, 19362, },
785 } },
786 { 2432, {
787 { 3, 21558, 3, 19402, },
788 { 3, 21647, 3, 19482, },
789 { 3, 21470, 3, 19323, },
790 } },
791 { 2437, {
792 { 3, 21514, 3, 19362, },
793 { 3, 21602, 3, 19442, },
794 { 3, 21426, 3, 19283, },
795 } },
796 { 2442, {
797 { 3, 21470, 3, 19323, },
798 { 3, 21558, 3, 19402, },
799 { 3, 21382, 3, 19244, },
800 } },
801 { 2447, {
802 { 3, 21426, 3, 19283, },
803 { 3, 21514, 3, 19362, },
804 { 3, 21339, 3, 19205, },
805 } },
806 { 2452, {
807 { 3, 21382, 3, 19244, },
808 { 3, 21470, 3, 19323, },
809 { 3, 21295, 3, 19166, },
810 } },
811 { 2457, {
812 { 3, 21339, 3, 19205, },
813 { 3, 21426, 3, 19283, },
814 { 3, 21252, 3, 19127, },
815 } },
816 { 2462, {
817 { 3, 21295, 3, 19166, },
818 { 3, 21382, 3, 19244, },
819 { 3, 21209, 3, 19088, },
820 } },
821 { 2467, {
822 { 3, 21252, 3, 19127, },
823 { 3, 21339, 3, 19205, },
824 { 3, 21166, 3, 19050, },
825 } },
826 { 2472, {
827 { 3, 21209, 3, 19088, },
828 { 3, 21295, 3, 19166, },
829 { 3, 21124, 3, 19011, },
830 } },
831 { 2484, {
832 { 3, 21107, 3, 18996, },
833 { 3, 21192, 3, 19073, },
834 { 3, 21022, 3, 18920, },
835 } },
836 { 4920, {
837 { 4, 21313, 4, 19181, },
838 { 4, 21356, 4, 19220, },
839 { 4, 21269, 4, 19142, },
840 } },
841 { 4940, {
842 { 4, 21226, 4, 19104, },
843 { 4, 21269, 4, 19142, },
844 { 4, 21183, 4, 19065, },
845 } },
846 { 4960, {
847 { 4, 21141, 4, 19027, },
848 { 4, 21183, 4, 19065, },
849 { 4, 21098, 4, 18988, },
850 } },
851 { 4980, {
852 { 4, 21056, 4, 18950, },
853 { 4, 21098, 4, 18988, },
854 { 4, 21014, 4, 18912, },
855 } },
856 { 5040, {
857 { 4, 20805, 4, 18725, },
858 { 4, 20846, 4, 18762, },
859 { 4, 20764, 4, 18687, },
860 } },
861 { 5060, {
862 { 4, 20723, 4, 18651, },
863 { 4, 20764, 4, 18687, },
864 { 4, 20682, 4, 18614, },
865 } },
866 { 5080, {
867 { 4, 20641, 4, 18577, },
868 { 4, 20682, 4, 18614, },
869 { 4, 20601, 4, 18541, },
870 } },
871 { 5180, {
872 { 4, 20243, 4, 18219, },
873 { 4, 20282, 4, 18254, },
874 { 4, 20204, 4, 18183, },
875 } },
876 { 5200, {
877 { 4, 20165, 4, 18148, },
878 { 4, 20204, 4, 18183, },
879 { 4, 20126, 4, 18114, },
880 } },
881 { 5220, {
882 { 4, 20088, 4, 18079, },
883 { 4, 20126, 4, 18114, },
884 { 4, 20049, 4, 18044, },
885 } },
886 { 5240, {
887 { 4, 20011, 4, 18010, },
888 { 4, 20049, 4, 18044, },
889 { 4, 19973, 4, 17976, },
890 } },
891 { 5260, {
892 { 4, 19935, 4, 17941, },
893 { 4, 19973, 4, 17976, },
894 { 4, 19897, 4, 17907, },
895 } },
896 { 5280, {
897 { 4, 19859, 4, 17873, },
898 { 4, 19897, 4, 17907, },
899 { 4, 19822, 4, 17840, },
900 } },
901 { 5300, {
902 { 4, 19784, 4, 17806, },
903 { 4, 19822, 4, 17840, },
904 { 4, 19747, 4, 17772, },
905 } },
906 { 5320, {
907 { 4, 19710, 4, 17739, },
908 { 4, 19747, 4, 17772, },
909 { 4, 19673, 4, 17706, },
910 } },
911 { 5500, {
912 { 4, 19065, 4, 17159, },
913 { 4, 19100, 4, 17190, },
914 { 4, 19030, 4, 17127, },
915 } },
916 { 5520, {
917 { 4, 18996, 4, 17096, },
918 { 4, 19030, 4, 17127, },
919 { 4, 18962, 4, 17065, },
920 } },
921 { 5540, {
922 { 4, 18927, 4, 17035, },
923 { 4, 18962, 4, 17065, },
924 { 4, 18893, 4, 17004, },
925 } },
926 { 5560, {
927 { 4, 18859, 4, 16973, },
928 { 4, 18893, 4, 17004, },
929 { 4, 18825, 4, 16943, },
930 } },
931 { 5580, {
932 { 4, 18792, 4, 16913, },
933 { 4, 18825, 4, 16943, },
934 { 4, 18758, 4, 16882, },
935 } },
936 { 5600, {
937 { 4, 18725, 4, 16852, },
938 { 4, 18758, 4, 16882, },
939 { 4, 18691, 4, 16822, },
940 } },
941 { 5620, {
942 { 4, 18658, 4, 16792, },
943 { 4, 18691, 4, 16822, },
944 { 4, 18625, 4, 16762, },
945 } },
946 { 5640, {
947 { 4, 18592, 4, 16733, },
948 { 4, 18625, 4, 16762, },
949 { 4, 18559, 4, 16703, },
950 } },
951 { 5660, {
952 { 4, 18526, 4, 16673, },
953 { 4, 18559, 4, 16703, },
954 { 4, 18493, 4, 16644, },
955 } },
956 { 5680, {
957 { 4, 18461, 4, 16615, },
958 { 4, 18493, 4, 16644, },
959 { 4, 18428, 4, 16586, },
960 } },
961 { 5700, {
962 { 4, 18396, 4, 16556, },
963 { 4, 18428, 4, 16586, },
964 { 4, 18364, 4, 16527, },
965 } },
966 { 5745, {
967 { 4, 18252, 4, 16427, },
968 { 4, 18284, 4, 16455, },
969 { 4, 18220, 4, 16398, },
970 } },
971 { 5765, {
972 { 4, 18189, 5, 32740, },
973 { 4, 18220, 4, 16398, },
974 { 4, 18157, 5, 32683, },
975 } },
976 { 5785, {
977 { 4, 18126, 5, 32626, },
978 { 4, 18157, 5, 32683, },
979 { 4, 18094, 5, 32570, },
980 } },
981 { 5805, {
982 { 4, 18063, 5, 32514, },
983 { 4, 18094, 5, 32570, },
984 { 4, 18032, 5, 32458, },
985 } },
986 { 5825, {
987 { 4, 18001, 5, 32402, },
988 { 4, 18032, 5, 32458, },
989 { 4, 17970, 5, 32347, },
990 } },
991 { 5170, {
992 { 4, 20282, 4, 18254, },
993 { 4, 20321, 4, 18289, },
994 { 4, 20243, 4, 18219, },
995 } },
996 { 5190, {
997 { 4, 20204, 4, 18183, },
998 { 4, 20243, 4, 18219, },
999 { 4, 20165, 4, 18148, },
1000 } },
1001 { 5210, {
1002 { 4, 20126, 4, 18114, },
1003 { 4, 20165, 4, 18148, },
1004 { 4, 20088, 4, 18079, },
1005 } },
1006 { 5230, {
1007 { 4, 20049, 4, 18044, },
1008 { 4, 20088, 4, 18079, },
1009 { 4, 20011, 4, 18010, },
1010 } },
1011 };
1012
1013 static const struct ar9170_phy_freq_params *
1014 ar9170_get_hw_dyn_params(struct ieee80211_channel *channel,
1015 enum ar9170_bw bw)
1016 {
1017 unsigned int chanidx = 0;
1018 u16 freq = 2412;
1019
1020 if (channel) {
1021 chanidx = channel->hw_value;
1022 freq = channel->center_freq;
1023 }
1024
1025 BUG_ON(chanidx >= ARRAY_SIZE(ar9170_phy_freq_params));
1026
1027 BUILD_BUG_ON(__AR9170_NUM_BW != 3);
1028
1029 WARN_ON(ar9170_phy_freq_params[chanidx].freq != freq);
1030
1031 return &ar9170_phy_freq_params[chanidx].params[bw];
1032 }
1033
1034
1035 int ar9170_init_rf(struct ar9170 *ar)
1036 {
1037 const struct ar9170_phy_freq_params *freqpar;
1038 __le32 cmd[7];
1039 int err;
1040
1041 err = ar9170_init_rf_banks_0_7(ar, false);
1042 if (err)
1043 return err;
1044
1045 err = ar9170_init_rf_bank4_pwr(ar, false, 2412, AR9170_BW_20);
1046 if (err)
1047 return err;
1048
1049 freqpar = ar9170_get_hw_dyn_params(NULL, AR9170_BW_20);
1050
1051 cmd[0] = cpu_to_le32(2412 * 1000);
1052 cmd[1] = cpu_to_le32(0);
1053 cmd[2] = cpu_to_le32(1);
1054 cmd[3] = cpu_to_le32(freqpar->coeff_exp);
1055 cmd[4] = cpu_to_le32(freqpar->coeff_man);
1056 cmd[5] = cpu_to_le32(freqpar->coeff_exp_shgi);
1057 cmd[6] = cpu_to_le32(freqpar->coeff_man_shgi);
1058
1059 /* RF_INIT echoes the command back to us */
1060 err = ar->exec_cmd(ar, AR9170_CMD_RF_INIT,
1061 sizeof(cmd), (u8 *)cmd,
1062 sizeof(cmd), (u8 *)cmd);
1063 if (err)
1064 return err;
1065
1066 msleep(1000);
1067
1068 return ar9170_echo_test(ar, 0xaabbccdd);
1069 }
1070
1071 static int ar9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f)
1072 {
1073 int idx = nfreqs - 2;
1074
1075 while (idx >= 0) {
1076 if (f >= freqs[idx])
1077 return idx;
1078 idx--;
1079 }
1080
1081 return 0;
1082 }
1083
1084 static s32 ar9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1085 {
1086 /* nothing to interpolate, it's horizontal */
1087 if (y2 == y1)
1088 return y1;
1089
1090 /* check if we hit one of the edges */
1091 if (x == x1)
1092 return y1;
1093 if (x == x2)
1094 return y2;
1095
1096 /* x1 == x2 is bad, hopefully == x */
1097 if (x2 == x1)
1098 return y1;
1099
1100 return y1 + (((y2 - y1) * (x - x1)) / (x2 - x1));
1101 }
1102
1103 static u8 ar9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2)
1104 {
1105 #define SHIFT 8
1106 s32 y;
1107
1108 y = ar9170_interpolate_s32(x << SHIFT,
1109 x1 << SHIFT, y1 << SHIFT,
1110 x2 << SHIFT, y2 << SHIFT);
1111
1112 /*
1113 * XXX: unwrap this expression
1114 * Isn't it just DIV_ROUND_UP(y, 1<<SHIFT)?
1115 * Can we rely on the compiler to optimise away the div?
1116 */
1117 return (y >> SHIFT) + ((y & (1<<(SHIFT-1))) >> (SHIFT - 1));
1118 #undef SHIFT
1119 }
1120
1121 static u8 ar9170_interpolate_val(u8 x, u8 *x_array, u8 *y_array)
1122 {
1123 int i;
1124
1125 for (i = 0; i < 3; i++)
1126 if (x <= x_array[i + 1])
1127 break;
1128
1129 return ar9170_interpolate_u8(x,
1130 x_array[i],
1131 y_array[i],
1132 x_array[i + 1],
1133 y_array[i + 1]);
1134 }
1135
1136 static int ar9170_set_freq_cal_data(struct ar9170 *ar,
1137 struct ieee80211_channel *channel)
1138 {
1139 u8 *cal_freq_pier;
1140 u8 vpds[2][AR5416_PD_GAIN_ICEPTS];
1141 u8 pwrs[2][AR5416_PD_GAIN_ICEPTS];
1142 int chain, idx, i;
1143 u32 phy_data = 0;
1144 u8 f, tmp;
1145
1146 switch (channel->band) {
1147 case IEEE80211_BAND_2GHZ:
1148 f = channel->center_freq - 2300;
1149 cal_freq_pier = ar->eeprom.cal_freq_pier_2G;
1150 i = AR5416_NUM_2G_CAL_PIERS - 1;
1151 break;
1152
1153 case IEEE80211_BAND_5GHZ:
1154 f = (channel->center_freq - 4800) / 5;
1155 cal_freq_pier = ar->eeprom.cal_freq_pier_5G;
1156 i = AR5416_NUM_5G_CAL_PIERS - 1;
1157 break;
1158
1159 default:
1160 return -EINVAL;
1161 break;
1162 }
1163
1164 for (; i >= 0; i--) {
1165 if (cal_freq_pier[i] != 0xff)
1166 break;
1167 }
1168 if (i < 0)
1169 return -EINVAL;
1170
1171 idx = ar9170_find_freq_idx(i, cal_freq_pier, f);
1172
1173 ar9170_regwrite_begin(ar);
1174
1175 for (chain = 0; chain < AR5416_MAX_CHAINS; chain++) {
1176 for (i = 0; i < AR5416_PD_GAIN_ICEPTS; i++) {
1177 struct ar9170_calibration_data_per_freq *cal_pier_data;
1178 int j;
1179
1180 switch (channel->band) {
1181 case IEEE80211_BAND_2GHZ:
1182 cal_pier_data = &ar->eeprom.
1183 cal_pier_data_2G[chain][idx];
1184 break;
1185
1186 case IEEE80211_BAND_5GHZ:
1187 cal_pier_data = &ar->eeprom.
1188 cal_pier_data_5G[chain][idx];
1189 break;
1190
1191 default:
1192 return -EINVAL;
1193 }
1194
1195 for (j = 0; j < 2; j++) {
1196 vpds[j][i] = ar9170_interpolate_u8(f,
1197 cal_freq_pier[idx],
1198 cal_pier_data->vpd_pdg[j][i],
1199 cal_freq_pier[idx + 1],
1200 cal_pier_data[1].vpd_pdg[j][i]);
1201
1202 pwrs[j][i] = ar9170_interpolate_u8(f,
1203 cal_freq_pier[idx],
1204 cal_pier_data->pwr_pdg[j][i],
1205 cal_freq_pier[idx + 1],
1206 cal_pier_data[1].pwr_pdg[j][i]) / 2;
1207 }
1208 }
1209
1210 for (i = 0; i < 76; i++) {
1211 if (i < 25) {
1212 tmp = ar9170_interpolate_val(i, &pwrs[0][0],
1213 &vpds[0][0]);
1214 } else {
1215 tmp = ar9170_interpolate_val(i - 12,
1216 &pwrs[1][0],
1217 &vpds[1][0]);
1218 }
1219
1220 phy_data |= tmp << ((i & 3) << 3);
1221 if ((i & 3) == 3) {
1222 ar9170_regwrite(0x1c6280 + chain * 0x1000 +
1223 (i & ~3), phy_data);
1224 phy_data = 0;
1225 }
1226 }
1227
1228 for (i = 19; i < 32; i++)
1229 ar9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2),
1230 0x0);
1231 }
1232
1233 ar9170_regwrite_finish();
1234 return ar9170_regwrite_result();
1235 }
1236
1237 static u8 ar9170_get_max_edge_power(struct ar9170 *ar,
1238 struct ar9170_calctl_edges edges[],
1239 u32 freq)
1240 {
1241 int i;
1242 u8 rc = AR5416_MAX_RATE_POWER;
1243 u8 f;
1244 if (freq < 3000)
1245 f = freq - 2300;
1246 else
1247 f = (freq - 4800) / 5;
1248
1249 for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
1250 if (edges[i].channel == 0xff)
1251 break;
1252 if (f == edges[i].channel) {
1253 /* exact freq match */
1254 rc = edges[i].power_flags & ~AR9170_CALCTL_EDGE_FLAGS;
1255 break;
1256 }
1257 if (i > 0 && f < edges[i].channel) {
1258 if (f > edges[i - 1].channel &&
1259 edges[i - 1].power_flags &
1260 AR9170_CALCTL_EDGE_FLAGS) {
1261 /* lower channel has the inband flag set */
1262 rc = edges[i - 1].power_flags &
1263 ~AR9170_CALCTL_EDGE_FLAGS;
1264 }
1265 break;
1266 }
1267 }
1268
1269 if (i == AR5416_NUM_BAND_EDGES) {
1270 if (f > edges[i - 1].channel &&
1271 edges[i - 1].power_flags & AR9170_CALCTL_EDGE_FLAGS) {
1272 /* lower channel has the inband flag set */
1273 rc = edges[i - 1].power_flags &
1274 ~AR9170_CALCTL_EDGE_FLAGS;
1275 }
1276 }
1277 return rc;
1278 }
1279
1280 static u8 ar9170_get_heavy_clip(struct ar9170 *ar,
1281 struct ar9170_calctl_edges edges[],
1282 u32 freq, enum ar9170_bw bw)
1283 {
1284 u8 f;
1285 int i;
1286 u8 rc = 0;
1287
1288 if (freq < 3000)
1289 f = freq - 2300;
1290 else
1291 f = (freq - 4800) / 5;
1292
1293 if (bw == AR9170_BW_40_BELOW || bw == AR9170_BW_40_ABOVE)
1294 rc |= 0xf0;
1295
1296 for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
1297 if (edges[i].channel == 0xff)
1298 break;
1299 if (f == edges[i].channel) {
1300 if (!(edges[i].power_flags & AR9170_CALCTL_EDGE_FLAGS))
1301 rc |= 0x0f;
1302 break;
1303 }
1304 }
1305
1306 return rc;
1307 }
1308
1309 /*
1310 * calculate the conformance test limits and the heavy clip parameter
1311 * and apply them to ar->power* (derived from otus hal/hpmain.c, line 3706)
1312 */
1313 static void ar9170_calc_ctl(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
1314 {
1315 u8 ctl_grp; /* CTL group */
1316 u8 ctl_idx; /* CTL index */
1317 int i, j;
1318 struct ctl_modes {
1319 u8 ctl_mode;
1320 u8 max_power;
1321 u8 *pwr_cal_data;
1322 int pwr_cal_len;
1323 } *modes;
1324
1325 /*
1326 * order is relevant in the mode_list_*: we fall back to the
1327 * lower indices if any mode is missed in the EEPROM.
1328 */
1329 struct ctl_modes mode_list_2ghz[] = {
1330 { CTL_11B, 0, ar->power_2G_cck, 4 },
1331 { CTL_11G, 0, ar->power_2G_ofdm, 4 },
1332 { CTL_2GHT20, 0, ar->power_2G_ht20, 8 },
1333 { CTL_2GHT40, 0, ar->power_2G_ht40, 8 },
1334 };
1335 struct ctl_modes mode_list_5ghz[] = {
1336 { CTL_11A, 0, ar->power_5G_leg, 4 },
1337 { CTL_5GHT20, 0, ar->power_5G_ht20, 8 },
1338 { CTL_5GHT40, 0, ar->power_5G_ht40, 8 },
1339 };
1340 int nr_modes;
1341
1342 #define EDGES(c, n) (ar->eeprom.ctl_data[c].control_edges[n])
1343
1344 ar->phy_heavy_clip = 0;
1345
1346 /*
1347 * TODO: investigate the differences between OTUS'
1348 * hpreg.c::zfHpGetRegulatoryDomain() and
1349 * ath/regd.c::ath_regd_get_band_ctl() -
1350 * e.g. for FCC3_WORLD the OTUS procedure
1351 * always returns CTL_FCC, while the one in ath/ delivers
1352 * CTL_ETSI for 2GHz and CTL_FCC for 5GHz.
1353 */
1354 ctl_grp = ath_regd_get_band_ctl(&ar->common.regulatory,
1355 ar->hw->conf.channel->band);
1356
1357 /* ctl group not found - either invalid band (NO_CTL) or ww roaming */
1358 if (ctl_grp == NO_CTL || ctl_grp == SD_NO_CTL)
1359 ctl_grp = CTL_FCC;
1360
1361 if (ctl_grp != CTL_FCC)
1362 /* skip CTL and heavy clip for CTL_MKK and CTL_ETSI */
1363 return;
1364
1365 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
1366 modes = mode_list_2ghz;
1367 nr_modes = ARRAY_SIZE(mode_list_2ghz);
1368 } else {
1369 modes = mode_list_5ghz;
1370 nr_modes = ARRAY_SIZE(mode_list_5ghz);
1371 }
1372
1373 for (i = 0; i < nr_modes; i++) {
1374 u8 c = ctl_grp | modes[i].ctl_mode;
1375 for (ctl_idx = 0; ctl_idx < AR5416_NUM_CTLS; ctl_idx++)
1376 if (c == ar->eeprom.ctl_index[ctl_idx])
1377 break;
1378 if (ctl_idx < AR5416_NUM_CTLS) {
1379 int f_off = 0;
1380
1381 /* determine heav clip parameter from
1382 the 11G edges array */
1383 if (modes[i].ctl_mode == CTL_11G) {
1384 ar->phy_heavy_clip =
1385 ar9170_get_heavy_clip(ar,
1386 EDGES(ctl_idx, 1),
1387 freq, bw);
1388 }
1389
1390 /* adjust freq for 40MHz */
1391 if (modes[i].ctl_mode == CTL_2GHT40 ||
1392 modes[i].ctl_mode == CTL_5GHT40) {
1393 if (bw == AR9170_BW_40_BELOW)
1394 f_off = -10;
1395 else
1396 f_off = 10;
1397 }
1398
1399 modes[i].max_power =
1400 ar9170_get_max_edge_power(ar, EDGES(ctl_idx, 1),
1401 freq+f_off);
1402
1403 /*
1404 * TODO: check if the regulatory max. power is
1405 * controlled by cfg80211 for DFS
1406 * (hpmain applies it to max_power itself for DFS freq)
1407 */
1408
1409 } else {
1410 /*
1411 * Workaround in otus driver, hpmain.c, line 3906:
1412 * if no data for 5GHT20 are found, take the
1413 * legacy 5G value.
1414 * We extend this here to fallback from any other *HT or
1415 * 11G, too.
1416 */
1417 int k = i;
1418
1419 modes[i].max_power = AR5416_MAX_RATE_POWER;
1420 while (k-- > 0) {
1421 if (modes[k].max_power !=
1422 AR5416_MAX_RATE_POWER) {
1423 modes[i].max_power = modes[k].max_power;
1424 break;
1425 }
1426 }
1427 }
1428
1429 /* apply max power to pwr_cal_data (ar->power_*) */
1430 for (j = 0; j < modes[i].pwr_cal_len; j++) {
1431 modes[i].pwr_cal_data[j] = min(modes[i].pwr_cal_data[j],
1432 modes[i].max_power);
1433 }
1434 }
1435
1436 if (ar->phy_heavy_clip & 0xf0) {
1437 ar->power_2G_ht40[0]--;
1438 ar->power_2G_ht40[1]--;
1439 ar->power_2G_ht40[2]--;
1440 }
1441 if (ar->phy_heavy_clip & 0xf) {
1442 ar->power_2G_ht20[0]++;
1443 ar->power_2G_ht20[1]++;
1444 ar->power_2G_ht20[2]++;
1445 }
1446
1447
1448 #undef EDGES
1449 }
1450
1451 static int ar9170_set_power_cal(struct ar9170 *ar, u32 freq, enum ar9170_bw bw)
1452 {
1453 struct ar9170_calibration_target_power_legacy *ctpl;
1454 struct ar9170_calibration_target_power_ht *ctph;
1455 u8 *ctpres;
1456 int ntargets;
1457 int idx, i, n;
1458 u8 ackpower, ackchains, f;
1459 u8 pwr_freqs[AR5416_MAX_NUM_TGT_PWRS];
1460
1461 if (freq < 3000)
1462 f = freq - 2300;
1463 else
1464 f = (freq - 4800)/5;
1465
1466 /*
1467 * cycle through the various modes
1468 *
1469 * legacy modes first: 5G, 2G CCK, 2G OFDM
1470 */
1471 for (i = 0; i < 3; i++) {
1472 switch (i) {
1473 case 0: /* 5 GHz legacy */
1474 ctpl = &ar->eeprom.cal_tgt_pwr_5G[0];
1475 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1476 ctpres = ar->power_5G_leg;
1477 break;
1478 case 1: /* 2.4 GHz CCK */
1479 ctpl = &ar->eeprom.cal_tgt_pwr_2G_cck[0];
1480 ntargets = AR5416_NUM_2G_CCK_TARGET_PWRS;
1481 ctpres = ar->power_2G_cck;
1482 break;
1483 case 2: /* 2.4 GHz OFDM */
1484 ctpl = &ar->eeprom.cal_tgt_pwr_2G_ofdm[0];
1485 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1486 ctpres = ar->power_2G_ofdm;
1487 break;
1488 default:
1489 BUG();
1490 }
1491
1492 for (n = 0; n < ntargets; n++) {
1493 if (ctpl[n].freq == 0xff)
1494 break;
1495 pwr_freqs[n] = ctpl[n].freq;
1496 }
1497 ntargets = n;
1498 idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f);
1499 for (n = 0; n < 4; n++)
1500 ctpres[n] = ar9170_interpolate_u8(
1501 f,
1502 ctpl[idx + 0].freq,
1503 ctpl[idx + 0].power[n],
1504 ctpl[idx + 1].freq,
1505 ctpl[idx + 1].power[n]);
1506 }
1507
1508 /*
1509 * HT modes now: 5G HT20, 5G HT40, 2G CCK, 2G OFDM, 2G HT20, 2G HT40
1510 */
1511 for (i = 0; i < 4; i++) {
1512 switch (i) {
1513 case 0: /* 5 GHz HT 20 */
1514 ctph = &ar->eeprom.cal_tgt_pwr_5G_ht20[0];
1515 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1516 ctpres = ar->power_5G_ht20;
1517 break;
1518 case 1: /* 5 GHz HT 40 */
1519 ctph = &ar->eeprom.cal_tgt_pwr_5G_ht40[0];
1520 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1521 ctpres = ar->power_5G_ht40;
1522 break;
1523 case 2: /* 2.4 GHz HT 20 */
1524 ctph = &ar->eeprom.cal_tgt_pwr_2G_ht20[0];
1525 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1526 ctpres = ar->power_2G_ht20;
1527 break;
1528 case 3: /* 2.4 GHz HT 40 */
1529 ctph = &ar->eeprom.cal_tgt_pwr_2G_ht40[0];
1530 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1531 ctpres = ar->power_2G_ht40;
1532 break;
1533 default:
1534 BUG();
1535 }
1536
1537 for (n = 0; n < ntargets; n++) {
1538 if (ctph[n].freq == 0xff)
1539 break;
1540 pwr_freqs[n] = ctph[n].freq;
1541 }
1542 ntargets = n;
1543 idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f);
1544 for (n = 0; n < 8; n++)
1545 ctpres[n] = ar9170_interpolate_u8(
1546 f,
1547 ctph[idx + 0].freq,
1548 ctph[idx + 0].power[n],
1549 ctph[idx + 1].freq,
1550 ctph[idx + 1].power[n]);
1551 }
1552
1553
1554 /* calc. conformance test limits and apply to ar->power*[] */
1555 ar9170_calc_ctl(ar, freq, bw);
1556
1557 /* set ACK/CTS TX power */
1558 ar9170_regwrite_begin(ar);
1559
1560 if (ar->eeprom.tx_mask != 1)
1561 ackchains = AR9170_TX_PHY_TXCHAIN_2;
1562 else
1563 ackchains = AR9170_TX_PHY_TXCHAIN_1;
1564
1565 if (freq < 3000)
1566 ackpower = ar->power_2G_ofdm[0] & 0x3f;
1567 else
1568 ackpower = ar->power_5G_leg[0] & 0x3f;
1569
1570 ar9170_regwrite(0x1c3694, ackpower << 20 | ackchains << 26);
1571 ar9170_regwrite(0x1c3bb4, ackpower << 5 | ackchains << 11 |
1572 ackpower << 21 | ackchains << 27);
1573
1574 ar9170_regwrite_finish();
1575 return ar9170_regwrite_result();
1576 }
1577
1578 static int ar9170_calc_noise_dbm(u32 raw_noise)
1579 {
1580 if (raw_noise & 0x100)
1581 return ~((raw_noise & 0x0ff) >> 1);
1582 else
1583 return (raw_noise & 0xff) >> 1;
1584 }
1585
1586 int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
1587 enum ar9170_rf_init_mode rfi, enum ar9170_bw bw)
1588 {
1589 const struct ar9170_phy_freq_params *freqpar;
1590 u32 cmd, tmp, offs;
1591 __le32 vals[8];
1592 int i, err;
1593 bool bandswitch;
1594
1595 /* clear BB heavy clip enable */
1596 err = ar9170_write_reg(ar, 0x1c59e0, 0x200);
1597 if (err)
1598 return err;
1599
1600 /* may be NULL at first setup */
1601 if (ar->channel)
1602 bandswitch = ar->channel->band != channel->band;
1603 else
1604 bandswitch = true;
1605
1606 /* HW workaround */
1607 if (!ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] &&
1608 channel->center_freq <= 2417)
1609 bandswitch = true;
1610
1611 err = ar->exec_cmd(ar, AR9170_CMD_FREQ_START, 0, NULL, 0, NULL);
1612 if (err)
1613 return err;
1614
1615 if (rfi != AR9170_RFI_NONE || bandswitch) {
1616 u32 val = 0x400;
1617
1618 if (rfi == AR9170_RFI_COLD)
1619 val = 0x800;
1620
1621 /* warm/cold reset BB/ADDA */
1622 err = ar9170_write_reg(ar, 0x1d4004, val);
1623 if (err)
1624 return err;
1625
1626 err = ar9170_write_reg(ar, 0x1d4004, 0x0);
1627 if (err)
1628 return err;
1629
1630 err = ar9170_init_phy(ar, channel->band);
1631 if (err)
1632 return err;
1633
1634 err = ar9170_init_rf_banks_0_7(ar,
1635 channel->band == IEEE80211_BAND_5GHZ);
1636 if (err)
1637 return err;
1638
1639 cmd = AR9170_CMD_RF_INIT;
1640 } else {
1641 cmd = AR9170_CMD_FREQUENCY;
1642 }
1643
1644 err = ar9170_init_rf_bank4_pwr(ar,
1645 channel->band == IEEE80211_BAND_5GHZ,
1646 channel->center_freq, bw);
1647 if (err)
1648 return err;
1649
1650 switch (bw) {
1651 case AR9170_BW_20:
1652 tmp = 0x240;
1653 offs = 0;
1654 break;
1655 case AR9170_BW_40_BELOW:
1656 tmp = 0x2c4;
1657 offs = 3;
1658 break;
1659 case AR9170_BW_40_ABOVE:
1660 tmp = 0x2d4;
1661 offs = 1;
1662 break;
1663 default:
1664 BUG();
1665 return -ENOSYS;
1666 }
1667
1668 if (ar->eeprom.tx_mask != 1)
1669 tmp |= 0x100;
1670
1671 err = ar9170_write_reg(ar, 0x1c5804, tmp);
1672 if (err)
1673 return err;
1674
1675 err = ar9170_set_freq_cal_data(ar, channel);
1676 if (err)
1677 return err;
1678
1679 err = ar9170_set_power_cal(ar, channel->center_freq, bw);
1680 if (err)
1681 return err;
1682
1683 freqpar = ar9170_get_hw_dyn_params(channel, bw);
1684
1685 vals[0] = cpu_to_le32(channel->center_freq * 1000);
1686 vals[1] = cpu_to_le32(conf_is_ht40(&ar->hw->conf));
1687 vals[2] = cpu_to_le32(offs << 2 | 1);
1688 vals[3] = cpu_to_le32(freqpar->coeff_exp);
1689 vals[4] = cpu_to_le32(freqpar->coeff_man);
1690 vals[5] = cpu_to_le32(freqpar->coeff_exp_shgi);
1691 vals[6] = cpu_to_le32(freqpar->coeff_man_shgi);
1692 vals[7] = cpu_to_le32(1000);
1693
1694 err = ar->exec_cmd(ar, cmd, sizeof(vals), (u8 *)vals,
1695 sizeof(vals), (u8 *)vals);
1696 if (err)
1697 return err;
1698
1699 if (ar->phy_heavy_clip) {
1700 err = ar9170_write_reg(ar, 0x1c59e0,
1701 0x200 | ar->phy_heavy_clip);
1702 if (err) {
1703 if (ar9170_nag_limiter(ar))
1704 wiphy_err(ar->hw->wiphy,
1705 "failed to set heavy clip\n");
1706 }
1707 }
1708
1709 for (i = 0; i < 2; i++) {
1710 ar->noise[i] = ar9170_calc_noise_dbm(
1711 (le32_to_cpu(vals[2 + i]) >> 19) & 0x1ff);
1712
1713 ar->noise[i + 2] = ar9170_calc_noise_dbm(
1714 (le32_to_cpu(vals[5 + i]) >> 23) & 0x1ff);
1715 }
1716
1717 ar->channel = channel;
1718 return 0;
1719 }
ubuntu-zesty-kernel mirror