drivers/net/wireless/ath/ath.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH_H
  18 #define ATH_H
  19
  20 #include <linux/skbuff.h>
  21 #include <linux/if_ether.h>
  22 #include <linux/spinlock.h>
  23 #include <net/mac80211.h>
  24
  25 /*
  26  * The key cache is used for h/w cipher state and also for
  27  * tracking station state such as the current tx antenna.
  28  * We also setup a mapping table between key cache slot indices
  29  * and station state to short-circuit node lookups on rx.
  30  * Different parts have different size key caches.  We handle
  31  * up to ATH_KEYMAX entries (could dynamically allocate state).
  32  */
  33 #define ATH_KEYMAX              128     /* max key cache size we handle */
  34
  35 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  36
  37 struct ath_ani {
  38         bool caldone;
  39         unsigned int longcal_timer;
  40         unsigned int shortcal_timer;
  41         unsigned int resetcal_timer;
  42         unsigned int checkani_timer;
  43         struct timer_list timer;
  44 };
  45
  46 struct ath_cycle_counters {
  47         u32 cycles;
  48         u32 rx_busy;
  49         u32 rx_frame;
  50         u32 tx_frame;
  51 };
  52
  53 enum ath_device_state {
  54         ATH_HW_UNAVAILABLE,
  55         ATH_HW_INITIALIZED,
  56 };
  57
  58 enum ath_bus_type {
  59         ATH_PCI,
  60         ATH_AHB,
  61         ATH_USB,
  62 };
  63
  64 struct reg_dmn_pair_mapping {
  65         u16 regDmnEnum;
  66         u16 reg_5ghz_ctl;
  67         u16 reg_2ghz_ctl;
  68 };
  69
  70 struct ath_regulatory {
  71         char alpha2[2];
  72         u16 country_code;
  73         u16 max_power_level;
  74         u32 tp_scale;
  75         u16 current_rd;
  76         u16 current_rd_ext;
  77         int16_t power_limit;
  78         struct reg_dmn_pair_mapping *regpair;
  79 };
  80
  81 enum ath_crypt_caps {
  82         ATH_CRYPT_CAP_CIPHER_AESCCM             = BIT(0),
  83         ATH_CRYPT_CAP_MIC_COMBINED              = BIT(1),
  84 };
  85
  86 struct ath_keyval {
  87         u8 kv_type;
  88         u8 kv_pad;
  89         u16 kv_len;
  90         u8 kv_val[16]; /* TK */
  91         u8 kv_mic[8]; /* Michael MIC key */
  92         u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
  93                          * supports both MIC keys in the same key cache entry;
  94                          * in that case, kv_mic is the RX key) */
  95 };
  96
  97 enum ath_cipher {
  98         ATH_CIPHER_WEP = 0,
  99         ATH_CIPHER_AES_OCB = 1,
 100         ATH_CIPHER_AES_CCM = 2,
 101         ATH_CIPHER_CKIP = 3,
 102         ATH_CIPHER_TKIP = 4,
 103         ATH_CIPHER_CLR = 5,
 104         ATH_CIPHER_MIC = 127
 105 };
 106
 107 /**
 108  * struct ath_ops - Register read/write operations
 109  *
 110  * @read: Register read
 111  * @multi_read: Multiple register read
 112  * @write: Register write
 113  * @enable_write_buffer: Enable multiple register writes
 114  * @write_flush: flush buffered register writes and disable buffering
 115  */
 116 struct ath_ops {
 117         unsigned int (*read)(void *, u32 reg_offset);
 118         void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
 119         void (*write)(void *, u32 val, u32 reg_offset);
 120         void (*enable_write_buffer)(void *);
 121         void (*write_flush) (void *);
 122         u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
 123 };
 124
 125 struct ath_common;
 126 struct ath_bus_ops;
 127
 128 struct ath_common {
 129         void *ah;
 130         void *priv;
 131         struct ieee80211_hw *hw;
 132         int debug_mask;
 133         enum ath_device_state state;
 134
 135         struct ath_ani ani;
 136
 137         u16 cachelsz;
 138         u16 curaid;
 139         u8 macaddr[ETH_ALEN];
 140         u8 curbssid[ETH_ALEN];
 141         u8 bssidmask[ETH_ALEN];
 142
 143         u8 tx_chainmask;
 144         u8 rx_chainmask;
 145
 146         u32 rx_bufsize;
 147
 148         u32 keymax;
 149         DECLARE_BITMAP(keymap, ATH_KEYMAX);
 150         DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
 151         enum ath_crypt_caps crypt_caps;
 152
 153         unsigned int clockrate;
 154
 155         spinlock_t cc_lock;
 156         struct ath_cycle_counters cc_ani;
 157         struct ath_cycle_counters cc_survey;
 158
 159         struct ath_regulatory regulatory;
 160         const struct ath_ops *ops;
 161         const struct ath_bus_ops *bus_ops;
 162
 163         bool btcoex_enabled;
 164         bool disable_ani;
 165 };
 166
 167 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
 168                                 u32 len,
 169                                 gfp_t gfp_mask);
 170
 171 void ath_hw_setbssidmask(struct ath_common *common);
 172 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
 173 int ath_key_config(struct ath_common *common,
 174                           struct ieee80211_vif *vif,
 175                           struct ieee80211_sta *sta,
 176                           struct ieee80211_key_conf *key);
 177 bool ath_hw_keyreset(struct ath_common *common, u16 entry);
 178 void ath_hw_cycle_counters_update(struct ath_common *common);
 179 int32_t ath_hw_get_listen_time(struct ath_common *common);
 180
 181 extern __attribute__ ((format (printf, 3, 4))) int
 182 ath_printk(const char *level, struct ath_common *common, const char *fmt, ...);
 183
 184 #define ath_emerg(common, fmt, ...)                             \
 185         ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
 186 #define ath_alert(common, fmt, ...)                             \
 187         ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
 188 #define ath_crit(common, fmt, ...)                              \
 189         ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
 190 #define ath_err(common, fmt, ...)                               \
 191         ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
 192 #define ath_warn(common, fmt, ...)                              \
 193         ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
 194 #define ath_notice(common, fmt, ...)                            \
 195         ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
 196 #define ath_info(common, fmt, ...)                              \
 197         ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
 198
 199 /**
 200  * enum ath_debug_level - atheros wireless debug level
 201  *
 202  * @ATH_DBG_RESET: reset processing
 203  * @ATH_DBG_QUEUE: hardware queue management
 204  * @ATH_DBG_EEPROM: eeprom processing
 205  * @ATH_DBG_CALIBRATE: periodic calibration
 206  * @ATH_DBG_INTERRUPT: interrupt processing
 207  * @ATH_DBG_REGULATORY: regulatory processing
 208  * @ATH_DBG_ANI: adaptive noise immunitive processing
 209  * @ATH_DBG_XMIT: basic xmit operation
 210  * @ATH_DBG_BEACON: beacon handling
 211  * @ATH_DBG_CONFIG: configuration of the hardware
 212  * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
 213  * @ATH_DBG_PS: power save processing
 214  * @ATH_DBG_HWTIMER: hardware timer handling
 215  * @ATH_DBG_BTCOEX: bluetooth coexistance
 216  * @ATH_DBG_BSTUCK: stuck beacons
 217  * @ATH_DBG_ANY: enable all debugging
 218  *
 219  * The debug level is used to control the amount and type of debugging output
 220  * we want to see. Each driver has its own method for enabling debugging and
 221  * modifying debug level states -- but this is typically done through a
 222  * module parameter 'debug' along with a respective 'debug' debugfs file
 223  * entry.
 224  */
 225 enum ATH_DEBUG {
 226         ATH_DBG_RESET           = 0x00000001,
 227         ATH_DBG_QUEUE           = 0x00000002,
 228         ATH_DBG_EEPROM          = 0x00000004,
 229         ATH_DBG_CALIBRATE       = 0x00000008,
 230         ATH_DBG_INTERRUPT       = 0x00000010,
 231         ATH_DBG_REGULATORY      = 0x00000020,
 232         ATH_DBG_ANI             = 0x00000040,
 233         ATH_DBG_XMIT            = 0x00000080,
 234         ATH_DBG_BEACON          = 0x00000100,
 235         ATH_DBG_CONFIG          = 0x00000200,
 236         ATH_DBG_FATAL           = 0x00000400,
 237         ATH_DBG_PS              = 0x00000800,
 238         ATH_DBG_HWTIMER         = 0x00001000,
 239         ATH_DBG_BTCOEX          = 0x00002000,
 240         ATH_DBG_WMI             = 0x00004000,
 241         ATH_DBG_BSTUCK          = 0x00008000,
 242         ATH_DBG_ANY             = 0xffffffff
 243 };
 244
 245 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
 246
 247 #ifdef CONFIG_ATH_DEBUG
 248
 249 #define ath_dbg(common, dbg_mask, fmt, ...)                     \
 250 ({                                                              \
 251         int rtn;                                                \
 252         if ((common)->debug_mask & dbg_mask)                    \
 253                 rtn = ath_printk(KERN_DEBUG, common, fmt,       \
 254                                  ##__VA_ARGS__);                \
 255         else                                                    \
 256                 rtn = 0;                                        \
 257                                                                 \
 258         rtn;                                                    \
 259 })
 260 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
 261 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
 262
 263 #else
 264
 265 static inline  __attribute__ ((format (printf, 3, 4))) int
 266 ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
 267         const char *fmt, ...)
 268 {
 269         return 0;
 270 }
 271 #define ATH_DBG_WARN(foo, arg...) do {} while (0)
 272 #define ATH_DBG_WARN_ON_ONCE(foo) ({                            \
 273         int __ret_warn_once = !!(foo);                          \
 274         unlikely(__ret_warn_once);                              \
 275 })
 276
 277 #endif /* CONFIG_ATH_DEBUG */
 278
 279 /** Returns string describing opmode, or NULL if unknown mode. */
 280 #ifdef CONFIG_ATH_DEBUG
 281 const char *ath_opmode_to_string(enum nl80211_iftype opmode);
 282 #else
 283 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
 284 {
 285         return "UNKNOWN";
 286 }
 287 #endif
 288
 289 #endif /* ATH_H */