2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/etherdevice.h>
25 void __ath10k_htt_tx_dec_pending(struct ath10k_htt
*htt
, bool limit_mgmt_desc
)
28 htt
->num_pending_mgmt_tx
--;
30 htt
->num_pending_tx
--;
31 if (htt
->num_pending_tx
== htt
->max_num_pending_tx
- 1)
32 ath10k_mac_tx_unlock(htt
->ar
, ATH10K_TX_PAUSE_Q_FULL
);
35 static void ath10k_htt_tx_dec_pending(struct ath10k_htt
*htt
,
38 spin_lock_bh(&htt
->tx_lock
);
39 __ath10k_htt_tx_dec_pending(htt
, limit_mgmt_desc
);
40 spin_unlock_bh(&htt
->tx_lock
);
43 static int ath10k_htt_tx_inc_pending(struct ath10k_htt
*htt
,
44 bool limit_mgmt_desc
, bool is_probe_resp
)
46 struct ath10k
*ar
= htt
->ar
;
49 spin_lock_bh(&htt
->tx_lock
);
51 if (htt
->num_pending_tx
>= htt
->max_num_pending_tx
) {
56 if (limit_mgmt_desc
) {
57 if (is_probe_resp
&& (htt
->num_pending_mgmt_tx
>
58 ar
->hw_params
.max_probe_resp_desc_thres
)) {
62 htt
->num_pending_mgmt_tx
++;
65 htt
->num_pending_tx
++;
66 if (htt
->num_pending_tx
== htt
->max_num_pending_tx
)
67 ath10k_mac_tx_lock(htt
->ar
, ATH10K_TX_PAUSE_Q_FULL
);
70 spin_unlock_bh(&htt
->tx_lock
);
74 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt
*htt
, struct sk_buff
*skb
)
76 struct ath10k
*ar
= htt
->ar
;
79 lockdep_assert_held(&htt
->tx_lock
);
81 ret
= idr_alloc(&htt
->pending_tx
, skb
, 0,
82 htt
->max_num_pending_tx
, GFP_ATOMIC
);
84 ath10k_dbg(ar
, ATH10K_DBG_HTT
, "htt tx alloc msdu_id %d\n", ret
);
89 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt
*htt
, u16 msdu_id
)
91 struct ath10k
*ar
= htt
->ar
;
93 lockdep_assert_held(&htt
->tx_lock
);
95 ath10k_dbg(ar
, ATH10K_DBG_HTT
, "htt tx free msdu_id %hu\n", msdu_id
);
97 idr_remove(&htt
->pending_tx
, msdu_id
);
100 int ath10k_htt_tx_alloc(struct ath10k_htt
*htt
)
102 struct ath10k
*ar
= htt
->ar
;
105 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "htt tx max num pending tx %d\n",
106 htt
->max_num_pending_tx
);
108 spin_lock_init(&htt
->tx_lock
);
109 idr_init(&htt
->pending_tx
);
111 htt
->tx_pool
= dma_pool_create("ath10k htt tx pool", htt
->ar
->dev
,
112 sizeof(struct ath10k_htt_txbuf
), 4, 0);
115 goto free_idr_pending_tx
;
118 if (!ar
->hw_params
.continuous_frag_desc
)
119 goto skip_frag_desc_alloc
;
121 size
= htt
->max_num_pending_tx
* sizeof(struct htt_msdu_ext_desc
);
122 htt
->frag_desc
.vaddr
= dma_alloc_coherent(ar
->dev
, size
,
123 &htt
->frag_desc
.paddr
,
125 if (!htt
->frag_desc
.vaddr
) {
126 ath10k_warn(ar
, "failed to alloc fragment desc memory\n");
131 skip_frag_desc_alloc
:
135 dma_pool_destroy(htt
->tx_pool
);
137 idr_destroy(&htt
->pending_tx
);
141 static int ath10k_htt_tx_clean_up_pending(int msdu_id
, void *skb
, void *ctx
)
143 struct ath10k
*ar
= ctx
;
144 struct ath10k_htt
*htt
= &ar
->htt
;
145 struct htt_tx_done tx_done
= {0};
147 ath10k_dbg(ar
, ATH10K_DBG_HTT
, "force cleanup msdu_id %hu\n", msdu_id
);
150 tx_done
.msdu_id
= msdu_id
;
152 ath10k_txrx_tx_unref(htt
, &tx_done
);
157 void ath10k_htt_tx_free(struct ath10k_htt
*htt
)
161 idr_for_each(&htt
->pending_tx
, ath10k_htt_tx_clean_up_pending
, htt
->ar
);
162 idr_destroy(&htt
->pending_tx
);
163 dma_pool_destroy(htt
->tx_pool
);
165 if (htt
->frag_desc
.vaddr
) {
166 size
= htt
->max_num_pending_tx
*
167 sizeof(struct htt_msdu_ext_desc
);
168 dma_free_coherent(htt
->ar
->dev
, size
, htt
->frag_desc
.vaddr
,
169 htt
->frag_desc
.paddr
);
173 void ath10k_htt_htc_tx_complete(struct ath10k
*ar
, struct sk_buff
*skb
)
175 dev_kfree_skb_any(skb
);
178 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt
*htt
)
180 struct ath10k
*ar
= htt
->ar
;
186 len
+= sizeof(cmd
->hdr
);
187 len
+= sizeof(cmd
->ver_req
);
189 skb
= ath10k_htc_alloc_skb(ar
, len
);
194 cmd
= (struct htt_cmd
*)skb
->data
;
195 cmd
->hdr
.msg_type
= HTT_H2T_MSG_TYPE_VERSION_REQ
;
197 ret
= ath10k_htc_send(&htt
->ar
->htc
, htt
->eid
, skb
);
199 dev_kfree_skb_any(skb
);
206 int ath10k_htt_h2t_stats_req(struct ath10k_htt
*htt
, u8 mask
, u64 cookie
)
208 struct ath10k
*ar
= htt
->ar
;
209 struct htt_stats_req
*req
;
214 len
+= sizeof(cmd
->hdr
);
215 len
+= sizeof(cmd
->stats_req
);
217 skb
= ath10k_htc_alloc_skb(ar
, len
);
222 cmd
= (struct htt_cmd
*)skb
->data
;
223 cmd
->hdr
.msg_type
= HTT_H2T_MSG_TYPE_STATS_REQ
;
225 req
= &cmd
->stats_req
;
227 memset(req
, 0, sizeof(*req
));
229 /* currently we support only max 8 bit masks so no need to worry
230 * about endian support */
231 req
->upload_types
[0] = mask
;
232 req
->reset_types
[0] = mask
;
233 req
->stat_type
= HTT_STATS_REQ_CFG_STAT_TYPE_INVALID
;
234 req
->cookie_lsb
= cpu_to_le32(cookie
& 0xffffffff);
235 req
->cookie_msb
= cpu_to_le32((cookie
& 0xffffffff00000000ULL
) >> 32);
237 ret
= ath10k_htc_send(&htt
->ar
->htc
, htt
->eid
, skb
);
239 ath10k_warn(ar
, "failed to send htt type stats request: %d",
241 dev_kfree_skb_any(skb
);
248 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt
*htt
)
250 struct ath10k
*ar
= htt
->ar
;
255 if (!ar
->hw_params
.continuous_frag_desc
)
258 if (!htt
->frag_desc
.paddr
) {
259 ath10k_warn(ar
, "invalid frag desc memory\n");
263 size
= sizeof(cmd
->hdr
) + sizeof(cmd
->frag_desc_bank_cfg
);
264 skb
= ath10k_htc_alloc_skb(ar
, size
);
269 cmd
= (struct htt_cmd
*)skb
->data
;
270 cmd
->hdr
.msg_type
= HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG
;
271 cmd
->frag_desc_bank_cfg
.info
= 0;
272 cmd
->frag_desc_bank_cfg
.num_banks
= 1;
273 cmd
->frag_desc_bank_cfg
.desc_size
= sizeof(struct htt_msdu_ext_desc
);
274 cmd
->frag_desc_bank_cfg
.bank_base_addrs
[0] =
275 __cpu_to_le32(htt
->frag_desc
.paddr
);
276 cmd
->frag_desc_bank_cfg
.bank_id
[0].bank_min_id
= 0;
277 cmd
->frag_desc_bank_cfg
.bank_id
[0].bank_max_id
=
278 __cpu_to_le16(htt
->max_num_pending_tx
- 1);
280 ret
= ath10k_htc_send(&htt
->ar
->htc
, htt
->eid
, skb
);
282 ath10k_warn(ar
, "failed to send frag desc bank cfg request: %d\n",
284 dev_kfree_skb_any(skb
);
291 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt
*htt
)
293 struct ath10k
*ar
= htt
->ar
;
296 struct htt_rx_ring_setup_ring
*ring
;
297 const int num_rx_ring
= 1;
304 * the HW expects the buffer to be an integral number of 4-byte
307 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE
, 4));
308 BUILD_BUG_ON((HTT_RX_BUF_SIZE
& HTT_MAX_CACHE_LINE_SIZE_MASK
) != 0);
310 len
= sizeof(cmd
->hdr
) + sizeof(cmd
->rx_setup
.hdr
)
311 + (sizeof(*ring
) * num_rx_ring
);
312 skb
= ath10k_htc_alloc_skb(ar
, len
);
318 cmd
= (struct htt_cmd
*)skb
->data
;
319 ring
= &cmd
->rx_setup
.rings
[0];
321 cmd
->hdr
.msg_type
= HTT_H2T_MSG_TYPE_RX_RING_CFG
;
322 cmd
->rx_setup
.hdr
.num_rings
= 1;
324 /* FIXME: do we need all of this? */
326 flags
|= HTT_RX_RING_FLAGS_MAC80211_HDR
;
327 flags
|= HTT_RX_RING_FLAGS_MSDU_PAYLOAD
;
328 flags
|= HTT_RX_RING_FLAGS_PPDU_START
;
329 flags
|= HTT_RX_RING_FLAGS_PPDU_END
;
330 flags
|= HTT_RX_RING_FLAGS_MPDU_START
;
331 flags
|= HTT_RX_RING_FLAGS_MPDU_END
;
332 flags
|= HTT_RX_RING_FLAGS_MSDU_START
;
333 flags
|= HTT_RX_RING_FLAGS_MSDU_END
;
334 flags
|= HTT_RX_RING_FLAGS_RX_ATTENTION
;
335 flags
|= HTT_RX_RING_FLAGS_FRAG_INFO
;
336 flags
|= HTT_RX_RING_FLAGS_UNICAST_RX
;
337 flags
|= HTT_RX_RING_FLAGS_MULTICAST_RX
;
338 flags
|= HTT_RX_RING_FLAGS_CTRL_RX
;
339 flags
|= HTT_RX_RING_FLAGS_MGMT_RX
;
340 flags
|= HTT_RX_RING_FLAGS_NULL_RX
;
341 flags
|= HTT_RX_RING_FLAGS_PHY_DATA_RX
;
343 fw_idx
= __le32_to_cpu(*htt
->rx_ring
.alloc_idx
.vaddr
);
345 ring
->fw_idx_shadow_reg_paddr
=
346 __cpu_to_le32(htt
->rx_ring
.alloc_idx
.paddr
);
347 ring
->rx_ring_base_paddr
= __cpu_to_le32(htt
->rx_ring
.base_paddr
);
348 ring
->rx_ring_len
= __cpu_to_le16(htt
->rx_ring
.size
);
349 ring
->rx_ring_bufsize
= __cpu_to_le16(HTT_RX_BUF_SIZE
);
350 ring
->flags
= __cpu_to_le16(flags
);
351 ring
->fw_idx_init_val
= __cpu_to_le16(fw_idx
);
353 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
355 ring
->mac80211_hdr_offset
= __cpu_to_le16(desc_offset(rx_hdr_status
));
356 ring
->msdu_payload_offset
= __cpu_to_le16(desc_offset(msdu_payload
));
357 ring
->ppdu_start_offset
= __cpu_to_le16(desc_offset(ppdu_start
));
358 ring
->ppdu_end_offset
= __cpu_to_le16(desc_offset(ppdu_end
));
359 ring
->mpdu_start_offset
= __cpu_to_le16(desc_offset(mpdu_start
));
360 ring
->mpdu_end_offset
= __cpu_to_le16(desc_offset(mpdu_end
));
361 ring
->msdu_start_offset
= __cpu_to_le16(desc_offset(msdu_start
));
362 ring
->msdu_end_offset
= __cpu_to_le16(desc_offset(msdu_end
));
363 ring
->rx_attention_offset
= __cpu_to_le16(desc_offset(attention
));
364 ring
->frag_info_offset
= __cpu_to_le16(desc_offset(frag_info
));
368 ret
= ath10k_htc_send(&htt
->ar
->htc
, htt
->eid
, skb
);
370 dev_kfree_skb_any(skb
);
377 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt
*htt
,
378 u8 max_subfrms_ampdu
,
379 u8 max_subfrms_amsdu
)
381 struct ath10k
*ar
= htt
->ar
;
382 struct htt_aggr_conf
*aggr_conf
;
388 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
390 if (max_subfrms_ampdu
== 0 || max_subfrms_ampdu
> 64)
393 if (max_subfrms_amsdu
== 0 || max_subfrms_amsdu
> 31)
396 len
= sizeof(cmd
->hdr
);
397 len
+= sizeof(cmd
->aggr_conf
);
399 skb
= ath10k_htc_alloc_skb(ar
, len
);
404 cmd
= (struct htt_cmd
*)skb
->data
;
405 cmd
->hdr
.msg_type
= HTT_H2T_MSG_TYPE_AGGR_CFG
;
407 aggr_conf
= &cmd
->aggr_conf
;
408 aggr_conf
->max_num_ampdu_subframes
= max_subfrms_ampdu
;
409 aggr_conf
->max_num_amsdu_subframes
= max_subfrms_amsdu
;
411 ath10k_dbg(ar
, ATH10K_DBG_HTT
, "htt h2t aggr cfg msg amsdu %d ampdu %d",
412 aggr_conf
->max_num_amsdu_subframes
,
413 aggr_conf
->max_num_ampdu_subframes
);
415 ret
= ath10k_htc_send(&htt
->ar
->htc
, htt
->eid
, skb
);
417 dev_kfree_skb_any(skb
);
424 int ath10k_htt_mgmt_tx(struct ath10k_htt
*htt
, struct sk_buff
*msdu
)
426 struct ath10k
*ar
= htt
->ar
;
427 struct device
*dev
= ar
->dev
;
428 struct sk_buff
*txdesc
= NULL
;
430 struct ath10k_skb_cb
*skb_cb
= ATH10K_SKB_CB(msdu
);
431 u8 vdev_id
= skb_cb
->vdev_id
;
435 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)msdu
->data
;
436 bool limit_mgmt_desc
= false;
437 bool is_probe_resp
= false;
439 if (ar
->hw_params
.max_probe_resp_desc_thres
) {
440 limit_mgmt_desc
= true;
442 if (ieee80211_is_probe_resp(hdr
->frame_control
))
443 is_probe_resp
= true;
446 res
= ath10k_htt_tx_inc_pending(htt
, limit_mgmt_desc
, is_probe_resp
);
451 len
+= sizeof(cmd
->hdr
);
452 len
+= sizeof(cmd
->mgmt_tx
);
454 spin_lock_bh(&htt
->tx_lock
);
455 res
= ath10k_htt_tx_alloc_msdu_id(htt
, msdu
);
456 spin_unlock_bh(&htt
->tx_lock
);
462 txdesc
= ath10k_htc_alloc_skb(ar
, len
);
465 goto err_free_msdu_id
;
468 skb_cb
->paddr
= dma_map_single(dev
, msdu
->data
, msdu
->len
,
470 res
= dma_mapping_error(dev
, skb_cb
->paddr
);
473 goto err_free_txdesc
;
476 skb_put(txdesc
, len
);
477 cmd
= (struct htt_cmd
*)txdesc
->data
;
480 cmd
->hdr
.msg_type
= HTT_H2T_MSG_TYPE_MGMT_TX
;
481 cmd
->mgmt_tx
.msdu_paddr
= __cpu_to_le32(ATH10K_SKB_CB(msdu
)->paddr
);
482 cmd
->mgmt_tx
.len
= __cpu_to_le32(msdu
->len
);
483 cmd
->mgmt_tx
.desc_id
= __cpu_to_le32(msdu_id
);
484 cmd
->mgmt_tx
.vdev_id
= __cpu_to_le32(vdev_id
);
485 memcpy(cmd
->mgmt_tx
.hdr
, msdu
->data
,
486 min_t(int, msdu
->len
, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN
));
488 skb_cb
->htt
.txbuf
= NULL
;
490 res
= ath10k_htc_send(&htt
->ar
->htc
, htt
->eid
, txdesc
);
497 dma_unmap_single(dev
, skb_cb
->paddr
, msdu
->len
, DMA_TO_DEVICE
);
499 dev_kfree_skb_any(txdesc
);
501 spin_lock_bh(&htt
->tx_lock
);
502 ath10k_htt_tx_free_msdu_id(htt
, msdu_id
);
503 spin_unlock_bh(&htt
->tx_lock
);
505 ath10k_htt_tx_dec_pending(htt
, limit_mgmt_desc
);
510 int ath10k_htt_tx(struct ath10k_htt
*htt
, struct sk_buff
*msdu
)
512 struct ath10k
*ar
= htt
->ar
;
513 struct device
*dev
= ar
->dev
;
514 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)msdu
->data
;
515 struct ath10k_skb_cb
*skb_cb
= ATH10K_SKB_CB(msdu
);
516 struct ath10k_hif_sg_item sg_items
[2];
517 struct htt_data_tx_desc_frag
*frags
;
518 u8 vdev_id
= skb_cb
->vdev_id
;
519 u8 tid
= skb_cb
->htt
.tid
;
523 u16 msdu_id
, flags1
= 0;
524 dma_addr_t paddr
= 0;
526 struct htt_msdu_ext_desc
*ext_desc
= NULL
;
527 bool limit_mgmt_desc
= false;
528 bool is_probe_resp
= false;
530 if (unlikely(ieee80211_is_mgmt(hdr
->frame_control
)) &&
531 ar
->hw_params
.max_probe_resp_desc_thres
) {
532 limit_mgmt_desc
= true;
534 if (ieee80211_is_probe_resp(hdr
->frame_control
))
535 is_probe_resp
= true;
538 res
= ath10k_htt_tx_inc_pending(htt
, limit_mgmt_desc
, is_probe_resp
);
542 spin_lock_bh(&htt
->tx_lock
);
543 res
= ath10k_htt_tx_alloc_msdu_id(htt
, msdu
);
544 spin_unlock_bh(&htt
->tx_lock
);
550 prefetch_len
= min(htt
->prefetch_len
, msdu
->len
);
551 prefetch_len
= roundup(prefetch_len
, 4);
553 skb_cb
->htt
.txbuf
= dma_pool_alloc(htt
->tx_pool
, GFP_ATOMIC
,
555 if (!skb_cb
->htt
.txbuf
) {
557 goto err_free_msdu_id
;
559 skb_cb
->htt
.txbuf_paddr
= paddr
;
561 if ((ieee80211_is_action(hdr
->frame_control
) ||
562 ieee80211_is_deauth(hdr
->frame_control
) ||
563 ieee80211_is_disassoc(hdr
->frame_control
)) &&
564 ieee80211_has_protected(hdr
->frame_control
)) {
565 skb_put(msdu
, IEEE80211_CCMP_MIC_LEN
);
566 } else if (!skb_cb
->htt
.nohwcrypt
&&
567 skb_cb
->txmode
== ATH10K_HW_TXRX_RAW
&&
568 ieee80211_has_protected(hdr
->frame_control
)) {
569 skb_put(msdu
, IEEE80211_CCMP_MIC_LEN
);
572 skb_cb
->paddr
= dma_map_single(dev
, msdu
->data
, msdu
->len
,
574 res
= dma_mapping_error(dev
, skb_cb
->paddr
);
580 switch (skb_cb
->txmode
) {
581 case ATH10K_HW_TXRX_RAW
:
582 case ATH10K_HW_TXRX_NATIVE_WIFI
:
583 flags0
|= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT
;
585 case ATH10K_HW_TXRX_ETHERNET
:
586 if (ar
->hw_params
.continuous_frag_desc
) {
587 memset(&htt
->frag_desc
.vaddr
[msdu_id
], 0,
588 sizeof(struct htt_msdu_ext_desc
));
589 frags
= (struct htt_data_tx_desc_frag
*)
590 &htt
->frag_desc
.vaddr
[msdu_id
].frags
;
591 ext_desc
= &htt
->frag_desc
.vaddr
[msdu_id
];
592 frags
[0].tword_addr
.paddr_lo
=
593 __cpu_to_le32(skb_cb
->paddr
);
594 frags
[0].tword_addr
.paddr_hi
= 0;
595 frags
[0].tword_addr
.len_16
= __cpu_to_le16(msdu
->len
);
597 frags_paddr
= htt
->frag_desc
.paddr
+
598 (sizeof(struct htt_msdu_ext_desc
) * msdu_id
);
600 frags
= skb_cb
->htt
.txbuf
->frags
;
601 frags
[0].dword_addr
.paddr
=
602 __cpu_to_le32(skb_cb
->paddr
);
603 frags
[0].dword_addr
.len
= __cpu_to_le32(msdu
->len
);
604 frags
[1].dword_addr
.paddr
= 0;
605 frags
[1].dword_addr
.len
= 0;
607 frags_paddr
= skb_cb
->htt
.txbuf_paddr
;
609 flags0
|= SM(skb_cb
->txmode
, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE
);
611 case ATH10K_HW_TXRX_MGMT
:
612 flags0
|= SM(ATH10K_HW_TXRX_MGMT
,
613 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE
);
614 flags0
|= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT
;
616 frags_paddr
= skb_cb
->paddr
;
620 /* Normally all commands go through HTC which manages tx credits for
621 * each endpoint and notifies when tx is completed.
623 * HTT endpoint is creditless so there's no need to care about HTC
624 * flags. In that case it is trivial to fill the HTC header here.
626 * MSDU transmission is considered completed upon HTT event. This
627 * implies no relevant resources can be freed until after the event is
628 * received. That's why HTC tx completion handler itself is ignored by
629 * setting NULL to transfer_context for all sg items.
631 * There is simply no point in pushing HTT TX_FRM through HTC tx path
632 * as it's a waste of resources. By bypassing HTC it is possible to
633 * avoid extra memory allocations, compress data structures and thus
634 * improve performance. */
636 skb_cb
->htt
.txbuf
->htc_hdr
.eid
= htt
->eid
;
637 skb_cb
->htt
.txbuf
->htc_hdr
.len
= __cpu_to_le16(
638 sizeof(skb_cb
->htt
.txbuf
->cmd_hdr
) +
639 sizeof(skb_cb
->htt
.txbuf
->cmd_tx
) +
641 skb_cb
->htt
.txbuf
->htc_hdr
.flags
= 0;
643 if (skb_cb
->htt
.nohwcrypt
)
644 flags0
|= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT
;
646 if (!skb_cb
->is_protected
)
647 flags0
|= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT
;
649 flags1
|= SM((u16
)vdev_id
, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID
);
650 flags1
|= SM((u16
)tid
, HTT_DATA_TX_DESC_FLAGS1_EXT_TID
);
651 if (msdu
->ip_summed
== CHECKSUM_PARTIAL
&&
652 !test_bit(ATH10K_FLAG_RAW_MODE
, &ar
->dev_flags
)) {
653 flags1
|= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD
;
654 flags1
|= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD
;
655 if (ar
->hw_params
.continuous_frag_desc
)
656 ext_desc
->flags
|= HTT_MSDU_CHECKSUM_ENABLE
;
659 /* Prevent firmware from sending up tx inspection requests. There's
660 * nothing ath10k can do with frames requested for inspection so force
661 * it to simply rely a regular tx completion with discard status.
663 flags1
|= HTT_DATA_TX_DESC_FLAGS1_POSTPONED
;
665 skb_cb
->htt
.txbuf
->cmd_hdr
.msg_type
= HTT_H2T_MSG_TYPE_TX_FRM
;
666 skb_cb
->htt
.txbuf
->cmd_tx
.flags0
= flags0
;
667 skb_cb
->htt
.txbuf
->cmd_tx
.flags1
= __cpu_to_le16(flags1
);
668 skb_cb
->htt
.txbuf
->cmd_tx
.len
= __cpu_to_le16(msdu
->len
);
669 skb_cb
->htt
.txbuf
->cmd_tx
.id
= __cpu_to_le16(msdu_id
);
670 skb_cb
->htt
.txbuf
->cmd_tx
.frags_paddr
= __cpu_to_le32(frags_paddr
);
671 skb_cb
->htt
.txbuf
->cmd_tx
.peerid
= __cpu_to_le16(HTT_INVALID_PEERID
);
672 skb_cb
->htt
.txbuf
->cmd_tx
.freq
= __cpu_to_le16(skb_cb
->htt
.freq
);
674 trace_ath10k_htt_tx(ar
, msdu_id
, msdu
->len
, vdev_id
, tid
);
675 ath10k_dbg(ar
, ATH10K_DBG_HTT
,
676 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n",
677 flags0
, flags1
, msdu
->len
, msdu_id
, frags_paddr
,
678 (u32
)skb_cb
->paddr
, vdev_id
, tid
, skb_cb
->htt
.freq
);
679 ath10k_dbg_dump(ar
, ATH10K_DBG_HTT_DUMP
, NULL
, "htt tx msdu: ",
680 msdu
->data
, msdu
->len
);
681 trace_ath10k_tx_hdr(ar
, msdu
->data
, msdu
->len
);
682 trace_ath10k_tx_payload(ar
, msdu
->data
, msdu
->len
);
684 sg_items
[0].transfer_id
= 0;
685 sg_items
[0].transfer_context
= NULL
;
686 sg_items
[0].vaddr
= &skb_cb
->htt
.txbuf
->htc_hdr
;
687 sg_items
[0].paddr
= skb_cb
->htt
.txbuf_paddr
+
688 sizeof(skb_cb
->htt
.txbuf
->frags
);
689 sg_items
[0].len
= sizeof(skb_cb
->htt
.txbuf
->htc_hdr
) +
690 sizeof(skb_cb
->htt
.txbuf
->cmd_hdr
) +
691 sizeof(skb_cb
->htt
.txbuf
->cmd_tx
);
693 sg_items
[1].transfer_id
= 0;
694 sg_items
[1].transfer_context
= NULL
;
695 sg_items
[1].vaddr
= msdu
->data
;
696 sg_items
[1].paddr
= skb_cb
->paddr
;
697 sg_items
[1].len
= prefetch_len
;
699 res
= ath10k_hif_tx_sg(htt
->ar
,
700 htt
->ar
->htc
.endpoint
[htt
->eid
].ul_pipe_id
,
701 sg_items
, ARRAY_SIZE(sg_items
));
708 dma_unmap_single(dev
, skb_cb
->paddr
, msdu
->len
, DMA_TO_DEVICE
);
710 dma_pool_free(htt
->tx_pool
,
712 skb_cb
->htt
.txbuf_paddr
);
714 spin_lock_bh(&htt
->tx_lock
);
715 ath10k_htt_tx_free_msdu_id(htt
, msdu_id
);
716 spin_unlock_bh(&htt
->tx_lock
);
718 ath10k_htt_tx_dec_pending(htt
, limit_mgmt_desc
);