2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "targaddrs.h"
23 #define ATH10K_FW_DIR "ath10k"
25 /* QCA988X 1.0 definitions (unsupported) */
26 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
28 /* QCA988X 2.0 definitions */
29 #define QCA988X_HW_2_0_VERSION 0x4100016c
30 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
31 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
32 #define QCA988X_HW_2_0_FW_FILE "firmware.bin"
33 #define QCA988X_HW_2_0_OTP_FILE "otp.bin"
34 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
35 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
37 #define ATH10K_FW_API2_FILE "firmware-2.bin"
38 #define ATH10K_FW_API3_FILE "firmware-3.bin"
40 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
41 #define ATH10K_FW_API4_FILE "firmware-4.bin"
43 #define ATH10K_FW_UTF_FILE "utf.bin"
45 /* includes also the null byte */
46 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
48 #define REG_DUMP_COUNT_QCA988X 60
50 #define QCA988X_CAL_DATA_LEN 2116
58 enum ath10k_fw_ie_type
{
59 ATH10K_FW_IE_FW_VERSION
= 0,
60 ATH10K_FW_IE_TIMESTAMP
= 1,
61 ATH10K_FW_IE_FEATURES
= 2,
62 ATH10K_FW_IE_FW_IMAGE
= 3,
63 ATH10K_FW_IE_OTP_IMAGE
= 4,
65 /* WMI "operations" interface version, 32 bit value. Supported from
68 ATH10K_FW_IE_WMI_OP_VERSION
= 5,
71 enum ath10k_fw_wmi_op_version
{
72 ATH10K_FW_WMI_OP_VERSION_UNSET
= 0,
74 ATH10K_FW_WMI_OP_VERSION_MAIN
= 1,
75 ATH10K_FW_WMI_OP_VERSION_10_1
= 2,
76 ATH10K_FW_WMI_OP_VERSION_10_2
= 3,
77 ATH10K_FW_WMI_OP_VERSION_TLV
= 4,
78 ATH10K_FW_WMI_OP_VERSION_10_2_4
= 5,
81 ATH10K_FW_WMI_OP_VERSION_MAX
,
84 /* Known pecularities:
85 * - current FW doesn't support raw rx mode (last tested v599)
86 * - current FW dumps upon raw tx mode (last tested v599)
87 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
88 * - raw have FCS, nwifi doesn't
89 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
90 * param, llc/snap) are aligned to 4byte boundaries each */
91 enum ath10k_hw_txrx_mode
{
92 ATH10K_HW_TXRX_RAW
= 0,
93 ATH10K_HW_TXRX_NATIVE_WIFI
= 1,
94 ATH10K_HW_TXRX_ETHERNET
= 2,
96 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
97 ATH10K_HW_TXRX_MGMT
= 3,
100 enum ath10k_mcast2ucast_mode
{
101 ATH10K_MCAST2UCAST_DISABLED
= 0,
102 ATH10K_MCAST2UCAST_ENABLED
= 1,
105 struct ath10k_pktlog_hdr
{
114 /* Target specific defines for MAIN firmware */
115 #define TARGET_NUM_VDEVS 8
116 #define TARGET_NUM_PEER_AST 2
117 #define TARGET_NUM_WDS_ENTRIES 32
118 #define TARGET_DMA_BURST_SIZE 0
119 #define TARGET_MAC_AGGR_DELIM 0
120 #define TARGET_AST_SKID_LIMIT 16
121 #define TARGET_NUM_STATIONS 16
122 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \
124 #define TARGET_NUM_OFFLOAD_PEERS 0
125 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
126 #define TARGET_NUM_PEER_KEYS 2
127 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2)
128 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
129 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
130 #define TARGET_RX_TIMEOUT_LO_PRI 100
131 #define TARGET_RX_TIMEOUT_HI_PRI 40
133 /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
134 * avoid a very expensive re-alignment in mac80211. */
135 #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
137 #define TARGET_SCAN_MAX_PENDING_REQS 4
138 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
139 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
140 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
141 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
142 #define TARGET_NUM_MCAST_GROUPS 0
143 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
144 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
145 #define TARGET_TX_DBG_LOG_SIZE 1024
146 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
147 #define TARGET_VOW_CONFIG 0
148 #define TARGET_NUM_MSDU_DESC (1024 + 400)
149 #define TARGET_MAX_FRAG_ENTRIES 0
151 /* Target specific defines for 10.X firmware */
152 #define TARGET_10X_NUM_VDEVS 16
153 #define TARGET_10X_NUM_PEER_AST 2
154 #define TARGET_10X_NUM_WDS_ENTRIES 32
155 #define TARGET_10X_DMA_BURST_SIZE 0
156 #define TARGET_10X_MAC_AGGR_DELIM 0
157 #define TARGET_10X_AST_SKID_LIMIT 16
158 #define TARGET_10X_NUM_STATIONS 128
159 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \
160 (TARGET_10X_NUM_VDEVS))
161 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
162 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
163 #define TARGET_10X_NUM_PEER_KEYS 2
164 #define TARGET_10X_NUM_TIDS_MAX 256
165 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
166 (TARGET_10X_NUM_PEERS) * 2)
167 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
168 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
169 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100
170 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40
171 #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
172 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4
173 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
174 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
175 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
176 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
177 #define TARGET_10X_NUM_MCAST_GROUPS 0
178 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
179 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
180 #define TARGET_10X_TX_DBG_LOG_SIZE 1024
181 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
182 #define TARGET_10X_VOW_CONFIG 0
183 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
184 #define TARGET_10X_MAX_FRAG_ENTRIES 0
186 /* Target specific defines for WMI-TLV firmware */
187 #define TARGET_TLV_NUM_VDEVS 3
188 #define TARGET_TLV_NUM_STATIONS 32
189 #define TARGET_TLV_NUM_PEERS ((TARGET_TLV_NUM_STATIONS) + \
190 (TARGET_TLV_NUM_VDEVS) + \
192 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2)
193 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32)
195 /* Number of Copy Engines supported */
199 * Total number of PCIe MSI interrupts requested for all interrupt sources.
200 * PCIe standard forces this to be a power of 2.
201 * Some Host OS's limit MSI requests that can be granted to 8
202 * so for now we abide by this limit and avoid requesting more
205 #define MSI_NUM_REQUEST_LOG2 3
206 #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
209 * Granted MSIs are assigned as follows:
210 * Firmware uses the first
211 * Remaining MSIs, if any, are used by Copy Engines
212 * This mapping is known to both Target firmware and Host software.
213 * It may be changed as long as Host and Target are kept in sync.
215 /* MSI for firmware (errors, etc.) */
216 #define MSI_ASSIGN_FW 0
218 /* MSIs for Copy Engines */
219 #define MSI_ASSIGN_CE_INITIAL 1
220 #define MSI_ASSIGN_CE_MAX 7
223 #define RTC_STATE_V_ON 3
225 #define RTC_STATE_COLD_RESET_MASK 0x00000400
226 #define RTC_STATE_V_LSB 0
227 #define RTC_STATE_V_MASK 0x00000007
228 #define RTC_STATE_ADDRESS 0x0000
229 #define PCIE_SOC_WAKE_V_MASK 0x00000001
230 #define PCIE_SOC_WAKE_ADDRESS 0x0004
231 #define PCIE_SOC_WAKE_RESET 0x00000000
232 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
234 #define RTC_SOC_BASE_ADDRESS 0x00004000
235 #define RTC_WMAC_BASE_ADDRESS 0x00005000
236 #define MAC_COEX_BASE_ADDRESS 0x00006000
237 #define BT_COEX_BASE_ADDRESS 0x00007000
238 #define SOC_PCIE_BASE_ADDRESS 0x00008000
239 #define SOC_CORE_BASE_ADDRESS 0x00009000
240 #define WLAN_UART_BASE_ADDRESS 0x0000c000
241 #define WLAN_SI_BASE_ADDRESS 0x00010000
242 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
243 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
244 #define WLAN_MAC_BASE_ADDRESS 0x00020000
245 #define EFUSE_BASE_ADDRESS 0x00030000
246 #define FPGA_REG_BASE_ADDRESS 0x00039000
247 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
248 #define CE_WRAPPER_BASE_ADDRESS 0x00057000
249 #define CE0_BASE_ADDRESS 0x00057400
250 #define CE1_BASE_ADDRESS 0x00057800
251 #define CE2_BASE_ADDRESS 0x00057c00
252 #define CE3_BASE_ADDRESS 0x00058000
253 #define CE4_BASE_ADDRESS 0x00058400
254 #define CE5_BASE_ADDRESS 0x00058800
255 #define CE6_BASE_ADDRESS 0x00058c00
256 #define CE7_BASE_ADDRESS 0x00059000
257 #define DBI_BASE_ADDRESS 0x00060000
258 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
259 #define PCIE_LOCAL_BASE_ADDRESS 0x00080000
261 #define SOC_RESET_CONTROL_ADDRESS 0x00000000
262 #define SOC_RESET_CONTROL_OFFSET 0x00000000
263 #define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001
264 #define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000
265 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
266 #define SOC_CPU_CLOCK_OFFSET 0x00000020
267 #define SOC_CPU_CLOCK_STANDARD_LSB 0
268 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
269 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
270 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
271 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
272 #define SOC_LPO_CAL_OFFSET 0x000000e0
273 #define SOC_LPO_CAL_ENABLE_LSB 20
274 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
275 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
276 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
278 #define SOC_CHIP_ID_ADDRESS 0x000000ec
279 #define SOC_CHIP_ID_REV_LSB 8
280 #define SOC_CHIP_ID_REV_MASK 0x00000f00
282 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
283 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
284 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
285 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
287 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
288 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
289 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
290 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
291 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
292 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
293 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
294 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
296 #define CLOCK_GPIO_OFFSET 0xffffffff
297 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
298 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
300 #define SI_CONFIG_OFFSET 0x00000000
301 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18
302 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
303 #define SI_CONFIG_I2C_LSB 16
304 #define SI_CONFIG_I2C_MASK 0x00010000
305 #define SI_CONFIG_POS_SAMPLE_LSB 7
306 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
307 #define SI_CONFIG_INACTIVE_DATA_LSB 5
308 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
309 #define SI_CONFIG_INACTIVE_CLK_LSB 4
310 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
311 #define SI_CONFIG_DIVIDER_LSB 0
312 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
313 #define SI_CS_OFFSET 0x00000004
314 #define SI_CS_DONE_ERR_MASK 0x00000400
315 #define SI_CS_DONE_INT_MASK 0x00000200
316 #define SI_CS_START_LSB 8
317 #define SI_CS_START_MASK 0x00000100
318 #define SI_CS_RX_CNT_LSB 4
319 #define SI_CS_RX_CNT_MASK 0x000000f0
320 #define SI_CS_TX_CNT_LSB 0
321 #define SI_CS_TX_CNT_MASK 0x0000000f
323 #define SI_TX_DATA0_OFFSET 0x00000008
324 #define SI_TX_DATA1_OFFSET 0x0000000c
325 #define SI_RX_DATA0_OFFSET 0x00000010
326 #define SI_RX_DATA1_OFFSET 0x00000014
328 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
329 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
330 #define CORE_CTRL_ADDRESS 0x0000
331 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
332 #define PCIE_INTR_CAUSE_ADDRESS 0x000c
333 #define PCIE_INTR_CLR_ADDRESS 0x0014
334 #define SCRATCH_3_ADDRESS 0x0030
335 #define CPU_INTR_ADDRESS 0x0010
337 /* Firmware indications to the Host via SCRATCH_3 register. */
338 #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
339 #define FW_IND_EVENT_PENDING 1
340 #define FW_IND_INITIALIZED 2
342 /* HOST_REG interrupt from firmware */
343 #define PCIE_INTR_FIRMWARE_MASK 0x00000400
344 #define PCIE_INTR_CE_MASK_ALL 0x0007f800
346 #define DRAM_BASE_ADDRESS 0x00400000
350 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
351 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
352 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
353 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
354 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
355 #define RESET_CONTROL_MBOX_RST_MASK MISSING
356 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
357 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
358 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
359 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
360 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
361 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
362 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
363 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
364 #define LOCAL_SCRATCH_OFFSET 0x18
365 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
366 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
367 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
368 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
369 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
370 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
371 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
372 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
373 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
374 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
375 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
376 #define MBOX_BASE_ADDRESS MISSING
377 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
378 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
379 #define INT_STATUS_ENABLE_CPU_LSB MISSING
380 #define INT_STATUS_ENABLE_CPU_MASK MISSING
381 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
382 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
383 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
384 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
385 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
386 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
387 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
388 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
389 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
390 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
391 #define INT_STATUS_ENABLE_ADDRESS MISSING
392 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
393 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
394 #define HOST_INT_STATUS_ADDRESS MISSING
395 #define CPU_INT_STATUS_ADDRESS MISSING
396 #define ERROR_INT_STATUS_ADDRESS MISSING
397 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
398 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
399 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
400 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
401 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
402 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
403 #define COUNT_DEC_ADDRESS MISSING
404 #define HOST_INT_STATUS_CPU_MASK MISSING
405 #define HOST_INT_STATUS_CPU_LSB MISSING
406 #define HOST_INT_STATUS_ERROR_MASK MISSING
407 #define HOST_INT_STATUS_ERROR_LSB MISSING
408 #define HOST_INT_STATUS_COUNTER_MASK MISSING
409 #define HOST_INT_STATUS_COUNTER_LSB MISSING
410 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
411 #define WINDOW_DATA_ADDRESS MISSING
412 #define WINDOW_READ_ADDR_ADDRESS MISSING
413 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
415 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)