2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_reset_mode
{
37 ATH10K_PCI_RESET_AUTO
= 0,
38 ATH10K_PCI_RESET_WARM_ONLY
= 1,
41 static unsigned int ath10k_pci_irq_mode
= ATH10K_PCI_IRQ_AUTO
;
42 static unsigned int ath10k_pci_reset_mode
= ATH10K_PCI_RESET_AUTO
;
44 module_param_named(irq_mode
, ath10k_pci_irq_mode
, uint
, 0644);
45 MODULE_PARM_DESC(irq_mode
, "0: auto, 1: legacy, 2: msi (default: 0)");
47 module_param_named(reset_mode
, ath10k_pci_reset_mode
, uint
, 0644);
48 MODULE_PARM_DESC(reset_mode
, "0: auto, 1: warm only (default: 0)");
50 /* how long wait to wait for target to initialise, in ms */
51 #define ATH10K_PCI_TARGET_WAIT 3000
52 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
54 static const struct pci_device_id ath10k_pci_id_table
[] = {
55 { PCI_VDEVICE(ATHEROS
, QCA988X_2_0_DEVICE_ID
) }, /* PCI-E QCA988X V2 */
56 { PCI_VDEVICE(ATHEROS
, QCA6164_2_1_DEVICE_ID
) }, /* PCI-E QCA6164 V2.1 */
57 { PCI_VDEVICE(ATHEROS
, QCA6174_2_1_DEVICE_ID
) }, /* PCI-E QCA6174 V2.1 */
58 { PCI_VDEVICE(ATHEROS
, QCA99X0_2_0_DEVICE_ID
) }, /* PCI-E QCA99X0 V2 */
59 { PCI_VDEVICE(ATHEROS
, QCA9888_2_0_DEVICE_ID
) }, /* PCI-E QCA9888 V2 */
60 { PCI_VDEVICE(ATHEROS
, QCA9984_1_0_DEVICE_ID
) }, /* PCI-E QCA9984 V1 */
61 { PCI_VDEVICE(ATHEROS
, QCA9377_1_0_DEVICE_ID
) }, /* PCI-E QCA9377 V1 */
62 { PCI_VDEVICE(ATHEROS
, QCA9887_1_0_DEVICE_ID
) }, /* PCI-E QCA9887 */
66 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips
[] = {
67 /* QCA988X pre 2.0 chips are not supported because they need some nasty
68 * hacks. ath10k doesn't have them and these devices crash horribly
71 { QCA988X_2_0_DEVICE_ID
, QCA988X_HW_2_0_CHIP_ID_REV
},
73 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_2_1_CHIP_ID_REV
},
74 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_2_2_CHIP_ID_REV
},
75 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_3_0_CHIP_ID_REV
},
76 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_3_1_CHIP_ID_REV
},
77 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_3_2_CHIP_ID_REV
},
79 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_2_1_CHIP_ID_REV
},
80 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_2_2_CHIP_ID_REV
},
81 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_0_CHIP_ID_REV
},
82 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_1_CHIP_ID_REV
},
83 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_2_CHIP_ID_REV
},
85 { QCA99X0_2_0_DEVICE_ID
, QCA99X0_HW_2_0_CHIP_ID_REV
},
87 { QCA9984_1_0_DEVICE_ID
, QCA9984_HW_1_0_CHIP_ID_REV
},
89 { QCA9888_2_0_DEVICE_ID
, QCA9888_HW_2_0_CHIP_ID_REV
},
91 { QCA9377_1_0_DEVICE_ID
, QCA9377_HW_1_0_CHIP_ID_REV
},
92 { QCA9377_1_0_DEVICE_ID
, QCA9377_HW_1_1_CHIP_ID_REV
},
94 { QCA9887_1_0_DEVICE_ID
, QCA9887_HW_1_0_CHIP_ID_REV
},
97 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
);
98 static int ath10k_pci_cold_reset(struct ath10k
*ar
);
99 static int ath10k_pci_safe_chip_reset(struct ath10k
*ar
);
100 static int ath10k_pci_init_irq(struct ath10k
*ar
);
101 static int ath10k_pci_deinit_irq(struct ath10k
*ar
);
102 static int ath10k_pci_request_irq(struct ath10k
*ar
);
103 static void ath10k_pci_free_irq(struct ath10k
*ar
);
104 static int ath10k_pci_bmi_wait(struct ath10k
*ar
,
105 struct ath10k_ce_pipe
*tx_pipe
,
106 struct ath10k_ce_pipe
*rx_pipe
,
107 struct bmi_xfer
*xfer
);
108 static int ath10k_pci_qca99x0_chip_reset(struct ath10k
*ar
);
109 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe
*ce_state
);
110 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
);
111 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe
*ce_state
);
112 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe
*ce_state
);
113 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
);
114 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe
*ce_state
);
116 static struct ce_attr host_ce_config_wlan
[] = {
117 /* CE0: host->target HTC control and raw streams */
119 .flags
= CE_ATTR_FLAGS
,
123 .send_cb
= ath10k_pci_htc_tx_cb
,
126 /* CE1: target->host HTT + HTC control */
128 .flags
= CE_ATTR_FLAGS
,
131 .dest_nentries
= 512,
132 .recv_cb
= ath10k_pci_htt_htc_rx_cb
,
135 /* CE2: target->host WMI */
137 .flags
= CE_ATTR_FLAGS
,
140 .dest_nentries
= 128,
141 .recv_cb
= ath10k_pci_htc_rx_cb
,
144 /* CE3: host->target WMI */
146 .flags
= CE_ATTR_FLAGS
,
150 .send_cb
= ath10k_pci_htc_tx_cb
,
153 /* CE4: host->target HTT */
155 .flags
= CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
,
156 .src_nentries
= CE_HTT_H2T_MSG_SRC_NENTRIES
,
159 .send_cb
= ath10k_pci_htt_tx_cb
,
162 /* CE5: target->host HTT (HIF->HTT) */
164 .flags
= CE_ATTR_FLAGS
,
167 .dest_nentries
= 512,
168 .recv_cb
= ath10k_pci_htt_rx_cb
,
171 /* CE6: target autonomous hif_memcpy */
173 .flags
= CE_ATTR_FLAGS
,
179 /* CE7: ce_diag, the Diagnostic Window */
181 .flags
= CE_ATTR_FLAGS
,
183 .src_sz_max
= DIAG_TRANSFER_LIMIT
,
187 /* CE8: target->host pktlog */
189 .flags
= CE_ATTR_FLAGS
,
192 .dest_nentries
= 128,
193 .recv_cb
= ath10k_pci_pktlog_rx_cb
,
196 /* CE9 target autonomous qcache memcpy */
198 .flags
= CE_ATTR_FLAGS
,
204 /* CE10: target autonomous hif memcpy */
206 .flags
= CE_ATTR_FLAGS
,
212 /* CE11: target autonomous hif memcpy */
214 .flags
= CE_ATTR_FLAGS
,
221 /* Target firmware's Copy Engine configuration. */
222 static struct ce_pipe_config target_ce_config_wlan
[] = {
223 /* CE0: host->target HTC control and raw streams */
225 .pipenum
= __cpu_to_le32(0),
226 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
227 .nentries
= __cpu_to_le32(32),
228 .nbytes_max
= __cpu_to_le32(256),
229 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
230 .reserved
= __cpu_to_le32(0),
233 /* CE1: target->host HTT + HTC control */
235 .pipenum
= __cpu_to_le32(1),
236 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
237 .nentries
= __cpu_to_le32(32),
238 .nbytes_max
= __cpu_to_le32(2048),
239 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
240 .reserved
= __cpu_to_le32(0),
243 /* CE2: target->host WMI */
245 .pipenum
= __cpu_to_le32(2),
246 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
247 .nentries
= __cpu_to_le32(64),
248 .nbytes_max
= __cpu_to_le32(2048),
249 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
250 .reserved
= __cpu_to_le32(0),
253 /* CE3: host->target WMI */
255 .pipenum
= __cpu_to_le32(3),
256 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
257 .nentries
= __cpu_to_le32(32),
258 .nbytes_max
= __cpu_to_le32(2048),
259 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
260 .reserved
= __cpu_to_le32(0),
263 /* CE4: host->target HTT */
265 .pipenum
= __cpu_to_le32(4),
266 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
267 .nentries
= __cpu_to_le32(256),
268 .nbytes_max
= __cpu_to_le32(256),
269 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
270 .reserved
= __cpu_to_le32(0),
273 /* NB: 50% of src nentries, since tx has 2 frags */
275 /* CE5: target->host HTT (HIF->HTT) */
277 .pipenum
= __cpu_to_le32(5),
278 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
279 .nentries
= __cpu_to_le32(32),
280 .nbytes_max
= __cpu_to_le32(512),
281 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
282 .reserved
= __cpu_to_le32(0),
285 /* CE6: Reserved for target autonomous hif_memcpy */
287 .pipenum
= __cpu_to_le32(6),
288 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
289 .nentries
= __cpu_to_le32(32),
290 .nbytes_max
= __cpu_to_le32(4096),
291 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
292 .reserved
= __cpu_to_le32(0),
295 /* CE7 used only by Host */
297 .pipenum
= __cpu_to_le32(7),
298 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
299 .nentries
= __cpu_to_le32(0),
300 .nbytes_max
= __cpu_to_le32(0),
301 .flags
= __cpu_to_le32(0),
302 .reserved
= __cpu_to_le32(0),
305 /* CE8 target->host packtlog */
307 .pipenum
= __cpu_to_le32(8),
308 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
309 .nentries
= __cpu_to_le32(64),
310 .nbytes_max
= __cpu_to_le32(2048),
311 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
),
312 .reserved
= __cpu_to_le32(0),
315 /* CE9 target autonomous qcache memcpy */
317 .pipenum
= __cpu_to_le32(9),
318 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
319 .nentries
= __cpu_to_le32(32),
320 .nbytes_max
= __cpu_to_le32(2048),
321 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
),
322 .reserved
= __cpu_to_le32(0),
325 /* It not necessary to send target wlan configuration for CE10 & CE11
326 * as these CEs are not actively used in target.
331 * Map from service/endpoint to Copy Engine.
332 * This table is derived from the CE_PCI TABLE, above.
333 * It is passed to the Target at startup for use by firmware.
335 static struct service_to_pipe target_service_to_ce_map_wlan
[] = {
337 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
338 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
342 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
343 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
348 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
353 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
358 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
363 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
368 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
372 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
373 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
377 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
378 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
382 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
383 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
387 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
388 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
392 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
393 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
397 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
398 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
402 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
403 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
407 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
408 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
412 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
413 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
417 /* (Additions here) */
426 static bool ath10k_pci_is_awake(struct ath10k
*ar
)
428 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
429 u32 val
= ioread32(ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
432 return RTC_STATE_V_GET(val
) == RTC_STATE_V_ON
;
435 static void __ath10k_pci_wake(struct ath10k
*ar
)
437 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
439 lockdep_assert_held(&ar_pci
->ps_lock
);
441 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps wake reg refcount %lu awake %d\n",
442 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
444 iowrite32(PCIE_SOC_WAKE_V_MASK
,
445 ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
446 PCIE_SOC_WAKE_ADDRESS
);
449 static void __ath10k_pci_sleep(struct ath10k
*ar
)
451 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
453 lockdep_assert_held(&ar_pci
->ps_lock
);
455 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps sleep reg refcount %lu awake %d\n",
456 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
458 iowrite32(PCIE_SOC_WAKE_RESET
,
459 ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
460 PCIE_SOC_WAKE_ADDRESS
);
461 ar_pci
->ps_awake
= false;
464 static int ath10k_pci_wake_wait(struct ath10k
*ar
)
469 while (tot_delay
< PCIE_WAKE_TIMEOUT
) {
470 if (ath10k_pci_is_awake(ar
)) {
471 if (tot_delay
> PCIE_WAKE_LATE_US
)
472 ath10k_warn(ar
, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
478 tot_delay
+= curr_delay
;
487 static int ath10k_pci_force_wake(struct ath10k
*ar
)
489 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
496 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
498 if (!ar_pci
->ps_awake
) {
499 iowrite32(PCIE_SOC_WAKE_V_MASK
,
500 ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
501 PCIE_SOC_WAKE_ADDRESS
);
503 ret
= ath10k_pci_wake_wait(ar
);
505 ar_pci
->ps_awake
= true;
508 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
513 static void ath10k_pci_force_sleep(struct ath10k
*ar
)
515 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
518 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
520 iowrite32(PCIE_SOC_WAKE_RESET
,
521 ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
522 PCIE_SOC_WAKE_ADDRESS
);
523 ar_pci
->ps_awake
= false;
525 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
528 static int ath10k_pci_wake(struct ath10k
*ar
)
530 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
534 if (ar_pci
->pci_ps
== 0)
537 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
539 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps wake refcount %lu awake %d\n",
540 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
542 /* This function can be called very frequently. To avoid excessive
543 * CPU stalls for MMIO reads use a cache var to hold the device state.
545 if (!ar_pci
->ps_awake
) {
546 __ath10k_pci_wake(ar
);
548 ret
= ath10k_pci_wake_wait(ar
);
550 ar_pci
->ps_awake
= true;
554 ar_pci
->ps_wake_refcount
++;
555 WARN_ON(ar_pci
->ps_wake_refcount
== 0);
558 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
563 static void ath10k_pci_sleep(struct ath10k
*ar
)
565 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
568 if (ar_pci
->pci_ps
== 0)
571 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
573 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps sleep refcount %lu awake %d\n",
574 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
576 if (WARN_ON(ar_pci
->ps_wake_refcount
== 0))
579 ar_pci
->ps_wake_refcount
--;
581 mod_timer(&ar_pci
->ps_timer
, jiffies
+
582 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC
));
585 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
588 static void ath10k_pci_ps_timer(unsigned long ptr
)
590 struct ath10k
*ar
= (void *)ptr
;
591 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
594 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
596 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps timer refcount %lu awake %d\n",
597 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
599 if (ar_pci
->ps_wake_refcount
> 0)
602 __ath10k_pci_sleep(ar
);
605 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
608 static void ath10k_pci_sleep_sync(struct ath10k
*ar
)
610 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
613 if (ar_pci
->pci_ps
== 0) {
614 ath10k_pci_force_sleep(ar
);
618 del_timer_sync(&ar_pci
->ps_timer
);
620 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
621 WARN_ON(ar_pci
->ps_wake_refcount
> 0);
622 __ath10k_pci_sleep(ar
);
623 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
626 static void ath10k_bus_pci_write32(struct ath10k
*ar
, u32 offset
, u32 value
)
628 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
631 if (unlikely(offset
+ sizeof(value
) > ar_pci
->mem_len
)) {
632 ath10k_warn(ar
, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
633 offset
, offset
+ sizeof(value
), ar_pci
->mem_len
);
637 ret
= ath10k_pci_wake(ar
);
639 ath10k_warn(ar
, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
644 iowrite32(value
, ar_pci
->mem
+ offset
);
645 ath10k_pci_sleep(ar
);
648 static u32
ath10k_bus_pci_read32(struct ath10k
*ar
, u32 offset
)
650 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
654 if (unlikely(offset
+ sizeof(val
) > ar_pci
->mem_len
)) {
655 ath10k_warn(ar
, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
656 offset
, offset
+ sizeof(val
), ar_pci
->mem_len
);
660 ret
= ath10k_pci_wake(ar
);
662 ath10k_warn(ar
, "failed to wake target for read32 at 0x%08x: %d\n",
667 val
= ioread32(ar_pci
->mem
+ offset
);
668 ath10k_pci_sleep(ar
);
673 inline void ath10k_pci_write32(struct ath10k
*ar
, u32 offset
, u32 value
)
675 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
677 ce
->bus_ops
->write32(ar
, offset
, value
);
680 inline u32
ath10k_pci_read32(struct ath10k
*ar
, u32 offset
)
682 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
684 return ce
->bus_ops
->read32(ar
, offset
);
687 u32
ath10k_pci_soc_read32(struct ath10k
*ar
, u32 addr
)
689 return ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+ addr
);
692 void ath10k_pci_soc_write32(struct ath10k
*ar
, u32 addr
, u32 val
)
694 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ addr
, val
);
697 u32
ath10k_pci_reg_read32(struct ath10k
*ar
, u32 addr
)
699 return ath10k_pci_read32(ar
, PCIE_LOCAL_BASE_ADDRESS
+ addr
);
702 void ath10k_pci_reg_write32(struct ath10k
*ar
, u32 addr
, u32 val
)
704 ath10k_pci_write32(ar
, PCIE_LOCAL_BASE_ADDRESS
+ addr
, val
);
707 bool ath10k_pci_irq_pending(struct ath10k
*ar
)
711 /* Check if the shared legacy irq is for us */
712 cause
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
713 PCIE_INTR_CAUSE_ADDRESS
);
714 if (cause
& (PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
))
720 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k
*ar
)
722 /* IMPORTANT: INTR_CLR register has to be set after
723 * INTR_ENABLE is set to 0, otherwise interrupt can not be
726 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
728 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_CLR_ADDRESS
,
729 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
731 /* IMPORTANT: this extra read transaction is required to
732 * flush the posted write buffer.
734 (void)ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
735 PCIE_INTR_ENABLE_ADDRESS
);
738 void ath10k_pci_enable_legacy_irq(struct ath10k
*ar
)
740 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+
741 PCIE_INTR_ENABLE_ADDRESS
,
742 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
744 /* IMPORTANT: this extra read transaction is required to
745 * flush the posted write buffer.
747 (void)ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
748 PCIE_INTR_ENABLE_ADDRESS
);
751 static inline const char *ath10k_pci_get_irq_method(struct ath10k
*ar
)
753 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
755 if (ar_pci
->oper_irq_mode
== ATH10K_PCI_IRQ_MSI
)
761 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe
*pipe
)
763 struct ath10k
*ar
= pipe
->hif_ce_state
;
764 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
765 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
770 skb
= dev_alloc_skb(pipe
->buf_sz
);
774 WARN_ONCE((unsigned long)skb
->data
& 3, "unaligned skb");
776 paddr
= dma_map_single(ar
->dev
, skb
->data
,
777 skb
->len
+ skb_tailroom(skb
),
779 if (unlikely(dma_mapping_error(ar
->dev
, paddr
))) {
780 ath10k_warn(ar
, "failed to dma map pci rx buf\n");
781 dev_kfree_skb_any(skb
);
785 ATH10K_SKB_RXCB(skb
)->paddr
= paddr
;
787 spin_lock_bh(&ce
->ce_lock
);
788 ret
= __ath10k_ce_rx_post_buf(ce_pipe
, skb
, paddr
);
789 spin_unlock_bh(&ce
->ce_lock
);
791 dma_unmap_single(ar
->dev
, paddr
, skb
->len
+ skb_tailroom(skb
),
793 dev_kfree_skb_any(skb
);
800 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe
*pipe
)
802 struct ath10k
*ar
= pipe
->hif_ce_state
;
803 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
804 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
805 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
808 if (pipe
->buf_sz
== 0)
811 if (!ce_pipe
->dest_ring
)
814 spin_lock_bh(&ce
->ce_lock
);
815 num
= __ath10k_ce_rx_num_free_bufs(ce_pipe
);
816 spin_unlock_bh(&ce
->ce_lock
);
819 ret
= __ath10k_pci_rx_post_buf(pipe
);
823 ath10k_warn(ar
, "failed to post pci rx buf: %d\n", ret
);
824 mod_timer(&ar_pci
->rx_post_retry
, jiffies
+
825 ATH10K_PCI_RX_POST_RETRY_MS
);
832 void ath10k_pci_rx_post(struct ath10k
*ar
)
834 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
837 for (i
= 0; i
< CE_COUNT
; i
++)
838 ath10k_pci_rx_post_pipe(&ar_pci
->pipe_info
[i
]);
841 void ath10k_pci_rx_replenish_retry(unsigned long ptr
)
843 struct ath10k
*ar
= (void *)ptr
;
845 ath10k_pci_rx_post(ar
);
848 static u32
ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k
*ar
, u32 addr
)
850 u32 val
= 0, region
= addr
& 0xfffff;
852 val
= (ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
)
854 val
|= 0x100000 | region
;
858 static u32
ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k
*ar
, u32 addr
)
860 u32 val
= 0, region
= addr
& 0xfffff;
862 val
= ath10k_pci_read32(ar
, PCIE_BAR_REG_ADDRESS
);
863 val
|= 0x100000 | region
;
867 static u32
ath10k_pci_targ_cpu_to_ce_addr(struct ath10k
*ar
, u32 addr
)
869 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
871 if (WARN_ON_ONCE(!ar_pci
->targ_cpu_to_ce_addr
))
874 return ar_pci
->targ_cpu_to_ce_addr(ar
, addr
);
878 * Diagnostic read/write access is provided for startup/config/debug usage.
879 * Caller must guarantee proper alignment, when applicable, and single user
882 static int ath10k_pci_diag_read_mem(struct ath10k
*ar
, u32 address
, void *data
,
885 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
886 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
889 unsigned int completed_nbytes
, alloc_nbytes
, remaining_bytes
;
890 struct ath10k_ce_pipe
*ce_diag
;
891 /* Host buffer address in CE space */
893 dma_addr_t ce_data_base
= 0;
894 void *data_buf
= NULL
;
897 spin_lock_bh(&ce
->ce_lock
);
899 ce_diag
= ar_pci
->ce_diag
;
902 * Allocate a temporary bounce buffer to hold caller's data
903 * to be DMA'ed from Target. This guarantees
904 * 1) 4-byte alignment
905 * 2) Buffer in DMA-able space
907 alloc_nbytes
= min_t(unsigned int, nbytes
, DIAG_TRANSFER_LIMIT
);
909 data_buf
= (unsigned char *)dma_zalloc_coherent(ar
->dev
,
919 remaining_bytes
= nbytes
;
920 ce_data
= ce_data_base
;
921 while (remaining_bytes
) {
922 nbytes
= min_t(unsigned int, remaining_bytes
,
923 DIAG_TRANSFER_LIMIT
);
925 ret
= __ath10k_ce_rx_post_buf(ce_diag
, &ce_data
, ce_data
);
929 /* Request CE to send from Target(!) address to Host buffer */
931 * The address supplied by the caller is in the
932 * Target CPU virtual address space.
934 * In order to use this address with the diagnostic CE,
935 * convert it from Target CPU virtual address space
936 * to CE address space
938 address
= ath10k_pci_targ_cpu_to_ce_addr(ar
, address
);
940 ret
= ath10k_ce_send_nolock(ce_diag
, NULL
, (u32
)address
, nbytes
, 0,
946 while (ath10k_ce_completed_send_next_nolock(ce_diag
,
949 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
956 while (ath10k_ce_completed_recv_next_nolock(ce_diag
,
962 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
968 if (nbytes
!= completed_nbytes
) {
973 if (*buf
!= ce_data
) {
978 remaining_bytes
-= nbytes
;
979 memcpy(data
, data_buf
, nbytes
);
988 dma_free_coherent(ar
->dev
, alloc_nbytes
, data_buf
,
991 spin_unlock_bh(&ce
->ce_lock
);
996 static int ath10k_pci_diag_read32(struct ath10k
*ar
, u32 address
, u32
*value
)
1001 ret
= ath10k_pci_diag_read_mem(ar
, address
, &val
, sizeof(val
));
1002 *value
= __le32_to_cpu(val
);
1007 static int __ath10k_pci_diag_read_hi(struct ath10k
*ar
, void *dest
,
1010 u32 host_addr
, addr
;
1013 host_addr
= host_interest_item_address(src
);
1015 ret
= ath10k_pci_diag_read32(ar
, host_addr
, &addr
);
1017 ath10k_warn(ar
, "failed to get memcpy hi address for firmware address %d: %d\n",
1022 ret
= ath10k_pci_diag_read_mem(ar
, addr
, dest
, len
);
1024 ath10k_warn(ar
, "failed to memcpy firmware memory from %d (%d B): %d\n",
1032 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1033 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1035 int ath10k_pci_diag_write_mem(struct ath10k
*ar
, u32 address
,
1036 const void *data
, int nbytes
)
1038 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1039 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
1042 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
1043 struct ath10k_ce_pipe
*ce_diag
;
1044 void *data_buf
= NULL
;
1045 u32 ce_data
; /* Host buffer address in CE space */
1046 dma_addr_t ce_data_base
= 0;
1049 spin_lock_bh(&ce
->ce_lock
);
1051 ce_diag
= ar_pci
->ce_diag
;
1054 * Allocate a temporary bounce buffer to hold caller's data
1055 * to be DMA'ed to Target. This guarantees
1056 * 1) 4-byte alignment
1057 * 2) Buffer in DMA-able space
1059 orig_nbytes
= nbytes
;
1060 data_buf
= (unsigned char *)dma_alloc_coherent(ar
->dev
,
1069 /* Copy caller's data to allocated DMA buf */
1070 memcpy(data_buf
, data
, orig_nbytes
);
1073 * The address supplied by the caller is in the
1074 * Target CPU virtual address space.
1076 * In order to use this address with the diagnostic CE,
1078 * Target CPU virtual address space
1082 address
= ath10k_pci_targ_cpu_to_ce_addr(ar
, address
);
1084 remaining_bytes
= orig_nbytes
;
1085 ce_data
= ce_data_base
;
1086 while (remaining_bytes
) {
1087 /* FIXME: check cast */
1088 nbytes
= min_t(int, remaining_bytes
, DIAG_TRANSFER_LIMIT
);
1090 /* Set up to receive directly into Target(!) address */
1091 ret
= __ath10k_ce_rx_post_buf(ce_diag
, &address
, address
);
1096 * Request CE to send caller-supplied data that
1097 * was copied to bounce buffer to Target(!) address.
1099 ret
= ath10k_ce_send_nolock(ce_diag
, NULL
, (u32
)ce_data
,
1105 while (ath10k_ce_completed_send_next_nolock(ce_diag
,
1109 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
1116 while (ath10k_ce_completed_recv_next_nolock(ce_diag
,
1122 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
1128 if (nbytes
!= completed_nbytes
) {
1133 if (*buf
!= address
) {
1138 remaining_bytes
-= nbytes
;
1145 dma_free_coherent(ar
->dev
, orig_nbytes
, data_buf
,
1150 ath10k_warn(ar
, "failed to write diag value at 0x%x: %d\n",
1153 spin_unlock_bh(&ce
->ce_lock
);
1158 static int ath10k_pci_diag_write32(struct ath10k
*ar
, u32 address
, u32 value
)
1160 __le32 val
= __cpu_to_le32(value
);
1162 return ath10k_pci_diag_write_mem(ar
, address
, &val
, sizeof(val
));
1165 /* Called by lower (CE) layer when a send to Target completes. */
1166 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe
*ce_state
)
1168 struct ath10k
*ar
= ce_state
->ar
;
1169 struct sk_buff_head list
;
1170 struct sk_buff
*skb
;
1172 __skb_queue_head_init(&list
);
1173 while (ath10k_ce_completed_send_next(ce_state
, (void **)&skb
) == 0) {
1174 /* no need to call tx completion for NULL pointers */
1178 __skb_queue_tail(&list
, skb
);
1181 while ((skb
= __skb_dequeue(&list
)))
1182 ath10k_htc_tx_completion_handler(ar
, skb
);
1185 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe
*ce_state
,
1186 void (*callback
)(struct ath10k
*ar
,
1187 struct sk_buff
*skb
))
1189 struct ath10k
*ar
= ce_state
->ar
;
1190 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1191 struct ath10k_pci_pipe
*pipe_info
= &ar_pci
->pipe_info
[ce_state
->id
];
1192 struct sk_buff
*skb
;
1193 struct sk_buff_head list
;
1194 void *transfer_context
;
1195 unsigned int nbytes
, max_nbytes
;
1197 __skb_queue_head_init(&list
);
1198 while (ath10k_ce_completed_recv_next(ce_state
, &transfer_context
,
1200 skb
= transfer_context
;
1201 max_nbytes
= skb
->len
+ skb_tailroom(skb
);
1202 dma_unmap_single(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1203 max_nbytes
, DMA_FROM_DEVICE
);
1205 if (unlikely(max_nbytes
< nbytes
)) {
1206 ath10k_warn(ar
, "rxed more than expected (nbytes %d, max %d)",
1207 nbytes
, max_nbytes
);
1208 dev_kfree_skb_any(skb
);
1212 skb_put(skb
, nbytes
);
1213 __skb_queue_tail(&list
, skb
);
1216 while ((skb
= __skb_dequeue(&list
))) {
1217 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci rx ce pipe %d len %d\n",
1218 ce_state
->id
, skb
->len
);
1219 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci rx: ",
1220 skb
->data
, skb
->len
);
1225 ath10k_pci_rx_post_pipe(pipe_info
);
1228 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe
*ce_state
,
1229 void (*callback
)(struct ath10k
*ar
,
1230 struct sk_buff
*skb
))
1232 struct ath10k
*ar
= ce_state
->ar
;
1233 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1234 struct ath10k_pci_pipe
*pipe_info
= &ar_pci
->pipe_info
[ce_state
->id
];
1235 struct ath10k_ce_pipe
*ce_pipe
= pipe_info
->ce_hdl
;
1236 struct sk_buff
*skb
;
1237 struct sk_buff_head list
;
1238 void *transfer_context
;
1239 unsigned int nbytes
, max_nbytes
, nentries
;
1242 /* No need to aquire ce_lock for CE5, since this is the only place CE5
1243 * is processed other than init and deinit. Before releasing CE5
1244 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1246 __skb_queue_head_init(&list
);
1247 while (ath10k_ce_completed_recv_next_nolock(ce_state
, &transfer_context
,
1249 skb
= transfer_context
;
1250 max_nbytes
= skb
->len
+ skb_tailroom(skb
);
1252 if (unlikely(max_nbytes
< nbytes
)) {
1253 ath10k_warn(ar
, "rxed more than expected (nbytes %d, max %d)",
1254 nbytes
, max_nbytes
);
1258 dma_sync_single_for_cpu(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1259 max_nbytes
, DMA_FROM_DEVICE
);
1260 skb_put(skb
, nbytes
);
1261 __skb_queue_tail(&list
, skb
);
1264 nentries
= skb_queue_len(&list
);
1265 while ((skb
= __skb_dequeue(&list
))) {
1266 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci rx ce pipe %d len %d\n",
1267 ce_state
->id
, skb
->len
);
1268 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci rx: ",
1269 skb
->data
, skb
->len
);
1271 orig_len
= skb
->len
;
1273 skb_push(skb
, orig_len
- skb
->len
);
1274 skb_reset_tail_pointer(skb
);
1277 /*let device gain the buffer again*/
1278 dma_sync_single_for_device(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1279 skb
->len
+ skb_tailroom(skb
),
1282 ath10k_ce_rx_update_write_idx(ce_pipe
, nentries
);
1285 /* Called by lower (CE) layer when data is received from the Target. */
1286 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
)
1288 ath10k_pci_process_rx_cb(ce_state
, ath10k_htc_rx_completion_handler
);
1291 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
)
1293 /* CE4 polling needs to be done whenever CE pipe which transports
1294 * HTT Rx (target->host) is processed.
1296 ath10k_ce_per_engine_service(ce_state
->ar
, 4);
1298 ath10k_pci_process_rx_cb(ce_state
, ath10k_htc_rx_completion_handler
);
1301 /* Called by lower (CE) layer when data is received from the Target.
1302 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1304 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe
*ce_state
)
1306 ath10k_pci_process_rx_cb(ce_state
,
1307 ath10k_htt_rx_pktlog_completion_handler
);
1310 /* Called by lower (CE) layer when a send to HTT Target completes. */
1311 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe
*ce_state
)
1313 struct ath10k
*ar
= ce_state
->ar
;
1314 struct sk_buff
*skb
;
1316 while (ath10k_ce_completed_send_next(ce_state
, (void **)&skb
) == 0) {
1317 /* no need to call tx completion for NULL pointers */
1321 dma_unmap_single(ar
->dev
, ATH10K_SKB_CB(skb
)->paddr
,
1322 skb
->len
, DMA_TO_DEVICE
);
1323 ath10k_htt_hif_tx_complete(ar
, skb
);
1327 static void ath10k_pci_htt_rx_deliver(struct ath10k
*ar
, struct sk_buff
*skb
)
1329 skb_pull(skb
, sizeof(struct ath10k_htc_hdr
));
1330 ath10k_htt_t2h_msg_handler(ar
, skb
);
1333 /* Called by lower (CE) layer when HTT data is received from the Target. */
1334 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe
*ce_state
)
1336 /* CE4 polling needs to be done whenever CE pipe which transports
1337 * HTT Rx (target->host) is processed.
1339 ath10k_ce_per_engine_service(ce_state
->ar
, 4);
1341 ath10k_pci_process_htt_rx_cb(ce_state
, ath10k_pci_htt_rx_deliver
);
1344 int ath10k_pci_hif_tx_sg(struct ath10k
*ar
, u8 pipe_id
,
1345 struct ath10k_hif_sg_item
*items
, int n_items
)
1347 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1348 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
1349 struct ath10k_pci_pipe
*pci_pipe
= &ar_pci
->pipe_info
[pipe_id
];
1350 struct ath10k_ce_pipe
*ce_pipe
= pci_pipe
->ce_hdl
;
1351 struct ath10k_ce_ring
*src_ring
= ce_pipe
->src_ring
;
1352 unsigned int nentries_mask
;
1353 unsigned int sw_index
;
1354 unsigned int write_index
;
1357 spin_lock_bh(&ce
->ce_lock
);
1359 nentries_mask
= src_ring
->nentries_mask
;
1360 sw_index
= src_ring
->sw_index
;
1361 write_index
= src_ring
->write_index
;
1363 if (unlikely(CE_RING_DELTA(nentries_mask
,
1364 write_index
, sw_index
- 1) < n_items
)) {
1369 for (i
= 0; i
< n_items
- 1; i
++) {
1370 ath10k_dbg(ar
, ATH10K_DBG_PCI
,
1371 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1372 i
, items
[i
].paddr
, items
[i
].len
, n_items
);
1373 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci tx data: ",
1374 items
[i
].vaddr
, items
[i
].len
);
1376 err
= ath10k_ce_send_nolock(ce_pipe
,
1377 items
[i
].transfer_context
,
1380 items
[i
].transfer_id
,
1381 CE_SEND_FLAG_GATHER
);
1386 /* `i` is equal to `n_items -1` after for() */
1388 ath10k_dbg(ar
, ATH10K_DBG_PCI
,
1389 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1390 i
, items
[i
].paddr
, items
[i
].len
, n_items
);
1391 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci tx data: ",
1392 items
[i
].vaddr
, items
[i
].len
);
1394 err
= ath10k_ce_send_nolock(ce_pipe
,
1395 items
[i
].transfer_context
,
1398 items
[i
].transfer_id
,
1403 spin_unlock_bh(&ce
->ce_lock
);
1408 __ath10k_ce_send_revert(ce_pipe
);
1410 spin_unlock_bh(&ce
->ce_lock
);
1414 int ath10k_pci_hif_diag_read(struct ath10k
*ar
, u32 address
, void *buf
,
1417 return ath10k_pci_diag_read_mem(ar
, address
, buf
, buf_len
);
1420 u16
ath10k_pci_hif_get_free_queue_number(struct ath10k
*ar
, u8 pipe
)
1422 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1424 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif get free queue number\n");
1426 return ath10k_ce_num_free_src_entries(ar_pci
->pipe_info
[pipe
].ce_hdl
);
1429 static void ath10k_pci_dump_registers(struct ath10k
*ar
,
1430 struct ath10k_fw_crash_data
*crash_data
)
1432 __le32 reg_dump_values
[REG_DUMP_COUNT_QCA988X
] = {};
1435 lockdep_assert_held(&ar
->data_lock
);
1437 ret
= ath10k_pci_diag_read_hi(ar
, ®_dump_values
[0],
1439 REG_DUMP_COUNT_QCA988X
* sizeof(__le32
));
1441 ath10k_err(ar
, "failed to read firmware dump area: %d\n", ret
);
1445 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X
% 4);
1447 ath10k_err(ar
, "firmware register dump:\n");
1448 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
+= 4)
1449 ath10k_err(ar
, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1451 __le32_to_cpu(reg_dump_values
[i
]),
1452 __le32_to_cpu(reg_dump_values
[i
+ 1]),
1453 __le32_to_cpu(reg_dump_values
[i
+ 2]),
1454 __le32_to_cpu(reg_dump_values
[i
+ 3]));
1459 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
++)
1460 crash_data
->registers
[i
] = reg_dump_values
[i
];
1463 static void ath10k_pci_fw_crashed_dump(struct ath10k
*ar
)
1465 struct ath10k_fw_crash_data
*crash_data
;
1466 char guid
[UUID_STRING_LEN
+ 1];
1468 spin_lock_bh(&ar
->data_lock
);
1470 ar
->stats
.fw_crash_counter
++;
1472 crash_data
= ath10k_debug_get_new_fw_crash_data(ar
);
1475 scnprintf(guid
, sizeof(guid
), "%pUl", &crash_data
->guid
);
1477 scnprintf(guid
, sizeof(guid
), "n/a");
1479 ath10k_err(ar
, "firmware crashed! (guid %s)\n", guid
);
1480 ath10k_print_driver_info(ar
);
1481 ath10k_pci_dump_registers(ar
, crash_data
);
1482 ath10k_ce_dump_registers(ar
, crash_data
);
1484 spin_unlock_bh(&ar
->data_lock
);
1486 queue_work(ar
->workqueue
, &ar
->restart_work
);
1489 void ath10k_pci_hif_send_complete_check(struct ath10k
*ar
, u8 pipe
,
1492 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif send complete check\n");
1497 * Decide whether to actually poll for completions, or just
1498 * wait for a later chance.
1499 * If there seem to be plenty of resources left, then just wait
1500 * since checking involves reading a CE register, which is a
1501 * relatively expensive operation.
1503 resources
= ath10k_pci_hif_get_free_queue_number(ar
, pipe
);
1506 * If at least 50% of the total resources are still available,
1507 * don't bother checking again yet.
1509 if (resources
> (host_ce_config_wlan
[pipe
].src_nentries
>> 1))
1512 ath10k_ce_per_engine_service(ar
, pipe
);
1515 static void ath10k_pci_rx_retry_sync(struct ath10k
*ar
)
1517 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1519 del_timer_sync(&ar_pci
->rx_post_retry
);
1522 int ath10k_pci_hif_map_service_to_pipe(struct ath10k
*ar
, u16 service_id
,
1523 u8
*ul_pipe
, u8
*dl_pipe
)
1525 const struct service_to_pipe
*entry
;
1526 bool ul_set
= false, dl_set
= false;
1529 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif map service\n");
1531 for (i
= 0; i
< ARRAY_SIZE(target_service_to_ce_map_wlan
); i
++) {
1532 entry
= &target_service_to_ce_map_wlan
[i
];
1534 if (__le32_to_cpu(entry
->service_id
) != service_id
)
1537 switch (__le32_to_cpu(entry
->pipedir
)) {
1542 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
1547 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
1553 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
1554 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
1561 if (WARN_ON(!ul_set
|| !dl_set
))
1567 void ath10k_pci_hif_get_default_pipe(struct ath10k
*ar
,
1568 u8
*ul_pipe
, u8
*dl_pipe
)
1570 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif get default pipe\n");
1572 (void)ath10k_pci_hif_map_service_to_pipe(ar
,
1573 ATH10K_HTC_SVC_ID_RSVD_CTRL
,
1577 void ath10k_pci_irq_msi_fw_mask(struct ath10k
*ar
)
1581 switch (ar
->hw_rev
) {
1582 case ATH10K_HW_QCA988X
:
1583 case ATH10K_HW_QCA9887
:
1584 case ATH10K_HW_QCA6174
:
1585 case ATH10K_HW_QCA9377
:
1586 val
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
1588 val
&= ~CORE_CTRL_PCIE_REG_31_MASK
;
1589 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+
1590 CORE_CTRL_ADDRESS
, val
);
1592 case ATH10K_HW_QCA99X0
:
1593 case ATH10K_HW_QCA9984
:
1594 case ATH10K_HW_QCA9888
:
1595 case ATH10K_HW_QCA4019
:
1596 /* TODO: Find appropriate register configuration for QCA99X0
1600 case ATH10K_HW_WCN3990
:
1605 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k
*ar
)
1609 switch (ar
->hw_rev
) {
1610 case ATH10K_HW_QCA988X
:
1611 case ATH10K_HW_QCA9887
:
1612 case ATH10K_HW_QCA6174
:
1613 case ATH10K_HW_QCA9377
:
1614 val
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
1616 val
|= CORE_CTRL_PCIE_REG_31_MASK
;
1617 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+
1618 CORE_CTRL_ADDRESS
, val
);
1620 case ATH10K_HW_QCA99X0
:
1621 case ATH10K_HW_QCA9984
:
1622 case ATH10K_HW_QCA9888
:
1623 case ATH10K_HW_QCA4019
:
1624 /* TODO: Find appropriate register configuration for QCA99X0
1625 * to unmask irq/MSI.
1628 case ATH10K_HW_WCN3990
:
1633 static void ath10k_pci_irq_disable(struct ath10k
*ar
)
1635 ath10k_ce_disable_interrupts(ar
);
1636 ath10k_pci_disable_and_clear_legacy_irq(ar
);
1637 ath10k_pci_irq_msi_fw_mask(ar
);
1640 static void ath10k_pci_irq_sync(struct ath10k
*ar
)
1642 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1644 synchronize_irq(ar_pci
->pdev
->irq
);
1647 static void ath10k_pci_irq_enable(struct ath10k
*ar
)
1649 ath10k_ce_enable_interrupts(ar
);
1650 ath10k_pci_enable_legacy_irq(ar
);
1651 ath10k_pci_irq_msi_fw_unmask(ar
);
1654 static int ath10k_pci_hif_start(struct ath10k
*ar
)
1656 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1658 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif start\n");
1660 napi_enable(&ar
->napi
);
1662 ath10k_pci_irq_enable(ar
);
1663 ath10k_pci_rx_post(ar
);
1665 pcie_capability_write_word(ar_pci
->pdev
, PCI_EXP_LNKCTL
,
1671 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe
*pci_pipe
)
1674 struct ath10k_ce_pipe
*ce_pipe
;
1675 struct ath10k_ce_ring
*ce_ring
;
1676 struct sk_buff
*skb
;
1679 ar
= pci_pipe
->hif_ce_state
;
1680 ce_pipe
= pci_pipe
->ce_hdl
;
1681 ce_ring
= ce_pipe
->dest_ring
;
1686 if (!pci_pipe
->buf_sz
)
1689 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
1690 skb
= ce_ring
->per_transfer_context
[i
];
1694 ce_ring
->per_transfer_context
[i
] = NULL
;
1696 dma_unmap_single(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1697 skb
->len
+ skb_tailroom(skb
),
1699 dev_kfree_skb_any(skb
);
1703 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe
*pci_pipe
)
1706 struct ath10k_ce_pipe
*ce_pipe
;
1707 struct ath10k_ce_ring
*ce_ring
;
1708 struct sk_buff
*skb
;
1711 ar
= pci_pipe
->hif_ce_state
;
1712 ce_pipe
= pci_pipe
->ce_hdl
;
1713 ce_ring
= ce_pipe
->src_ring
;
1718 if (!pci_pipe
->buf_sz
)
1721 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
1722 skb
= ce_ring
->per_transfer_context
[i
];
1726 ce_ring
->per_transfer_context
[i
] = NULL
;
1728 ath10k_htc_tx_completion_handler(ar
, skb
);
1733 * Cleanup residual buffers for device shutdown:
1734 * buffers that were enqueued for receive
1735 * buffers that were to be sent
1736 * Note: Buffers that had completed but which were
1737 * not yet processed are on a completion queue. They
1738 * are handled when the completion thread shuts down.
1740 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
)
1742 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1745 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
1746 struct ath10k_pci_pipe
*pipe_info
;
1748 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1749 ath10k_pci_rx_pipe_cleanup(pipe_info
);
1750 ath10k_pci_tx_pipe_cleanup(pipe_info
);
1754 void ath10k_pci_ce_deinit(struct ath10k
*ar
)
1758 for (i
= 0; i
< CE_COUNT
; i
++)
1759 ath10k_ce_deinit_pipe(ar
, i
);
1762 void ath10k_pci_flush(struct ath10k
*ar
)
1764 ath10k_pci_rx_retry_sync(ar
);
1765 ath10k_pci_buffer_cleanup(ar
);
1768 static void ath10k_pci_hif_stop(struct ath10k
*ar
)
1770 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1771 unsigned long flags
;
1773 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif stop\n");
1775 /* Most likely the device has HTT Rx ring configured. The only way to
1776 * prevent the device from accessing (and possible corrupting) host
1777 * memory is to reset the chip now.
1779 * There's also no known way of masking MSI interrupts on the device.
1780 * For ranged MSI the CE-related interrupts can be masked. However
1781 * regardless how many MSI interrupts are assigned the first one
1782 * is always used for firmware indications (crashes) and cannot be
1783 * masked. To prevent the device from asserting the interrupt reset it
1784 * before proceeding with cleanup.
1786 ath10k_pci_safe_chip_reset(ar
);
1788 ath10k_pci_irq_disable(ar
);
1789 ath10k_pci_irq_sync(ar
);
1790 ath10k_pci_flush(ar
);
1791 napi_synchronize(&ar
->napi
);
1792 napi_disable(&ar
->napi
);
1794 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
1795 WARN_ON(ar_pci
->ps_wake_refcount
> 0);
1796 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
1799 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k
*ar
,
1800 void *req
, u32 req_len
,
1801 void *resp
, u32
*resp_len
)
1803 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1804 struct ath10k_pci_pipe
*pci_tx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_TARG
];
1805 struct ath10k_pci_pipe
*pci_rx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_HOST
];
1806 struct ath10k_ce_pipe
*ce_tx
= pci_tx
->ce_hdl
;
1807 struct ath10k_ce_pipe
*ce_rx
= pci_rx
->ce_hdl
;
1808 dma_addr_t req_paddr
= 0;
1809 dma_addr_t resp_paddr
= 0;
1810 struct bmi_xfer xfer
= {};
1811 void *treq
, *tresp
= NULL
;
1816 if (resp
&& !resp_len
)
1819 if (resp
&& resp_len
&& *resp_len
== 0)
1822 treq
= kmemdup(req
, req_len
, GFP_KERNEL
);
1826 req_paddr
= dma_map_single(ar
->dev
, treq
, req_len
, DMA_TO_DEVICE
);
1827 ret
= dma_mapping_error(ar
->dev
, req_paddr
);
1833 if (resp
&& resp_len
) {
1834 tresp
= kzalloc(*resp_len
, GFP_KERNEL
);
1840 resp_paddr
= dma_map_single(ar
->dev
, tresp
, *resp_len
,
1842 ret
= dma_mapping_error(ar
->dev
, resp_paddr
);
1848 xfer
.wait_for_resp
= true;
1851 ath10k_ce_rx_post_buf(ce_rx
, &xfer
, resp_paddr
);
1854 ret
= ath10k_ce_send(ce_tx
, &xfer
, req_paddr
, req_len
, -1, 0);
1858 ret
= ath10k_pci_bmi_wait(ar
, ce_tx
, ce_rx
, &xfer
);
1861 unsigned int unused_nbytes
;
1862 unsigned int unused_id
;
1864 ath10k_ce_cancel_send_next(ce_tx
, NULL
, &unused_buffer
,
1865 &unused_nbytes
, &unused_id
);
1867 /* non-zero means we did not time out */
1875 ath10k_ce_revoke_recv_next(ce_rx
, NULL
, &unused_buffer
);
1876 dma_unmap_single(ar
->dev
, resp_paddr
,
1877 *resp_len
, DMA_FROM_DEVICE
);
1880 dma_unmap_single(ar
->dev
, req_paddr
, req_len
, DMA_TO_DEVICE
);
1882 if (ret
== 0 && resp_len
) {
1883 *resp_len
= min(*resp_len
, xfer
.resp_len
);
1884 memcpy(resp
, tresp
, xfer
.resp_len
);
1893 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe
*ce_state
)
1895 struct bmi_xfer
*xfer
;
1897 if (ath10k_ce_completed_send_next(ce_state
, (void **)&xfer
))
1900 xfer
->tx_done
= true;
1903 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe
*ce_state
)
1905 struct ath10k
*ar
= ce_state
->ar
;
1906 struct bmi_xfer
*xfer
;
1907 unsigned int nbytes
;
1909 if (ath10k_ce_completed_recv_next(ce_state
, (void **)&xfer
,
1913 if (WARN_ON_ONCE(!xfer
))
1916 if (!xfer
->wait_for_resp
) {
1917 ath10k_warn(ar
, "unexpected: BMI data received; ignoring\n");
1921 xfer
->resp_len
= nbytes
;
1922 xfer
->rx_done
= true;
1925 static int ath10k_pci_bmi_wait(struct ath10k
*ar
,
1926 struct ath10k_ce_pipe
*tx_pipe
,
1927 struct ath10k_ce_pipe
*rx_pipe
,
1928 struct bmi_xfer
*xfer
)
1930 unsigned long timeout
= jiffies
+ BMI_COMMUNICATION_TIMEOUT_HZ
;
1931 unsigned long started
= jiffies
;
1935 while (time_before_eq(jiffies
, timeout
)) {
1936 ath10k_pci_bmi_send_done(tx_pipe
);
1937 ath10k_pci_bmi_recv_data(rx_pipe
);
1939 if (xfer
->tx_done
&& (xfer
->rx_done
== xfer
->wait_for_resp
)) {
1950 dur
= jiffies
- started
;
1952 ath10k_dbg(ar
, ATH10K_DBG_BMI
,
1953 "bmi cmd took %lu jiffies hz %d ret %d\n",
1959 * Send an interrupt to the device to wake up the Target CPU
1960 * so it has an opportunity to notice any changed state.
1962 static int ath10k_pci_wake_target_cpu(struct ath10k
*ar
)
1966 addr
= SOC_CORE_BASE_ADDRESS
+ CORE_CTRL_ADDRESS
;
1967 val
= ath10k_pci_read32(ar
, addr
);
1968 val
|= CORE_CTRL_CPU_INTR_MASK
;
1969 ath10k_pci_write32(ar
, addr
, val
);
1974 static int ath10k_pci_get_num_banks(struct ath10k
*ar
)
1976 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1978 switch (ar_pci
->pdev
->device
) {
1979 case QCA988X_2_0_DEVICE_ID
:
1980 case QCA99X0_2_0_DEVICE_ID
:
1981 case QCA9888_2_0_DEVICE_ID
:
1982 case QCA9984_1_0_DEVICE_ID
:
1983 case QCA9887_1_0_DEVICE_ID
:
1985 case QCA6164_2_1_DEVICE_ID
:
1986 case QCA6174_2_1_DEVICE_ID
:
1987 switch (MS(ar
->chip_id
, SOC_CHIP_ID_REV
)) {
1988 case QCA6174_HW_1_0_CHIP_ID_REV
:
1989 case QCA6174_HW_1_1_CHIP_ID_REV
:
1990 case QCA6174_HW_2_1_CHIP_ID_REV
:
1991 case QCA6174_HW_2_2_CHIP_ID_REV
:
1993 case QCA6174_HW_1_3_CHIP_ID_REV
:
1995 case QCA6174_HW_3_0_CHIP_ID_REV
:
1996 case QCA6174_HW_3_1_CHIP_ID_REV
:
1997 case QCA6174_HW_3_2_CHIP_ID_REV
:
2001 case QCA9377_1_0_DEVICE_ID
:
2005 ath10k_warn(ar
, "unknown number of banks, assuming 1\n");
2009 static int ath10k_bus_get_num_banks(struct ath10k
*ar
)
2011 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
2013 return ce
->bus_ops
->get_num_banks(ar
);
2016 int ath10k_pci_init_config(struct ath10k
*ar
)
2018 u32 interconnect_targ_addr
;
2019 u32 pcie_state_targ_addr
= 0;
2020 u32 pipe_cfg_targ_addr
= 0;
2021 u32 svc_to_pipe_map
= 0;
2022 u32 pcie_config_flags
= 0;
2024 u32 ealloc_targ_addr
;
2026 u32 flag2_targ_addr
;
2029 /* Download to Target the CE Config and the service-to-CE map */
2030 interconnect_targ_addr
=
2031 host_interest_item_address(HI_ITEM(hi_interconnect_state
));
2033 /* Supply Target-side CE configuration */
2034 ret
= ath10k_pci_diag_read32(ar
, interconnect_targ_addr
,
2035 &pcie_state_targ_addr
);
2037 ath10k_err(ar
, "Failed to get pcie state addr: %d\n", ret
);
2041 if (pcie_state_targ_addr
== 0) {
2043 ath10k_err(ar
, "Invalid pcie state addr\n");
2047 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
2048 offsetof(struct pcie_state
,
2050 &pipe_cfg_targ_addr
);
2052 ath10k_err(ar
, "Failed to get pipe cfg addr: %d\n", ret
);
2056 if (pipe_cfg_targ_addr
== 0) {
2058 ath10k_err(ar
, "Invalid pipe cfg addr\n");
2062 ret
= ath10k_pci_diag_write_mem(ar
, pipe_cfg_targ_addr
,
2063 target_ce_config_wlan
,
2064 sizeof(struct ce_pipe_config
) *
2065 NUM_TARGET_CE_CONFIG_WLAN
);
2068 ath10k_err(ar
, "Failed to write pipe cfg: %d\n", ret
);
2072 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
2073 offsetof(struct pcie_state
,
2077 ath10k_err(ar
, "Failed to get svc/pipe map: %d\n", ret
);
2081 if (svc_to_pipe_map
== 0) {
2083 ath10k_err(ar
, "Invalid svc_to_pipe map\n");
2087 ret
= ath10k_pci_diag_write_mem(ar
, svc_to_pipe_map
,
2088 target_service_to_ce_map_wlan
,
2089 sizeof(target_service_to_ce_map_wlan
));
2091 ath10k_err(ar
, "Failed to write svc/pipe map: %d\n", ret
);
2095 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
2096 offsetof(struct pcie_state
,
2098 &pcie_config_flags
);
2100 ath10k_err(ar
, "Failed to get pcie config_flags: %d\n", ret
);
2104 pcie_config_flags
&= ~PCIE_CONFIG_FLAG_ENABLE_L1
;
2106 ret
= ath10k_pci_diag_write32(ar
, (pcie_state_targ_addr
+
2107 offsetof(struct pcie_state
,
2111 ath10k_err(ar
, "Failed to write pcie config_flags: %d\n", ret
);
2115 /* configure early allocation */
2116 ealloc_targ_addr
= host_interest_item_address(HI_ITEM(hi_early_alloc
));
2118 ret
= ath10k_pci_diag_read32(ar
, ealloc_targ_addr
, &ealloc_value
);
2120 ath10k_err(ar
, "Failed to get early alloc val: %d\n", ret
);
2124 /* first bank is switched to IRAM */
2125 ealloc_value
|= ((HI_EARLY_ALLOC_MAGIC
<< HI_EARLY_ALLOC_MAGIC_SHIFT
) &
2126 HI_EARLY_ALLOC_MAGIC_MASK
);
2127 ealloc_value
|= ((ath10k_bus_get_num_banks(ar
) <<
2128 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT
) &
2129 HI_EARLY_ALLOC_IRAM_BANKS_MASK
);
2131 ret
= ath10k_pci_diag_write32(ar
, ealloc_targ_addr
, ealloc_value
);
2133 ath10k_err(ar
, "Failed to set early alloc val: %d\n", ret
);
2137 /* Tell Target to proceed with initialization */
2138 flag2_targ_addr
= host_interest_item_address(HI_ITEM(hi_option_flag2
));
2140 ret
= ath10k_pci_diag_read32(ar
, flag2_targ_addr
, &flag2_value
);
2142 ath10k_err(ar
, "Failed to get option val: %d\n", ret
);
2146 flag2_value
|= HI_OPTION_EARLY_CFG_DONE
;
2148 ret
= ath10k_pci_diag_write32(ar
, flag2_targ_addr
, flag2_value
);
2150 ath10k_err(ar
, "Failed to set option val: %d\n", ret
);
2157 static void ath10k_pci_override_ce_config(struct ath10k
*ar
)
2159 struct ce_attr
*attr
;
2160 struct ce_pipe_config
*config
;
2162 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2163 * since it is currently used for other feature.
2166 /* Override Host's Copy Engine 5 configuration */
2167 attr
= &host_ce_config_wlan
[5];
2168 attr
->src_sz_max
= 0;
2169 attr
->dest_nentries
= 0;
2171 /* Override Target firmware's Copy Engine configuration */
2172 config
= &target_ce_config_wlan
[5];
2173 config
->pipedir
= __cpu_to_le32(PIPEDIR_OUT
);
2174 config
->nbytes_max
= __cpu_to_le32(2048);
2176 /* Map from service/endpoint to Copy Engine */
2177 target_service_to_ce_map_wlan
[15].pipenum
= __cpu_to_le32(1);
2180 int ath10k_pci_alloc_pipes(struct ath10k
*ar
)
2182 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2183 struct ath10k_pci_pipe
*pipe
;
2184 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
2187 for (i
= 0; i
< CE_COUNT
; i
++) {
2188 pipe
= &ar_pci
->pipe_info
[i
];
2189 pipe
->ce_hdl
= &ce
->ce_states
[i
];
2191 pipe
->hif_ce_state
= ar
;
2193 ret
= ath10k_ce_alloc_pipe(ar
, i
, &host_ce_config_wlan
[i
]);
2195 ath10k_err(ar
, "failed to allocate copy engine pipe %d: %d\n",
2200 /* Last CE is Diagnostic Window */
2201 if (i
== CE_DIAG_PIPE
) {
2202 ar_pci
->ce_diag
= pipe
->ce_hdl
;
2206 pipe
->buf_sz
= (size_t)(host_ce_config_wlan
[i
].src_sz_max
);
2212 void ath10k_pci_free_pipes(struct ath10k
*ar
)
2216 for (i
= 0; i
< CE_COUNT
; i
++)
2217 ath10k_ce_free_pipe(ar
, i
);
2220 int ath10k_pci_init_pipes(struct ath10k
*ar
)
2224 for (i
= 0; i
< CE_COUNT
; i
++) {
2225 ret
= ath10k_ce_init_pipe(ar
, i
, &host_ce_config_wlan
[i
]);
2227 ath10k_err(ar
, "failed to initialize copy engine pipe %d: %d\n",
2236 static bool ath10k_pci_has_fw_crashed(struct ath10k
*ar
)
2238 return ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
) &
2239 FW_IND_EVENT_PENDING
;
2242 static void ath10k_pci_fw_crashed_clear(struct ath10k
*ar
)
2246 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
2247 val
&= ~FW_IND_EVENT_PENDING
;
2248 ath10k_pci_write32(ar
, FW_INDICATOR_ADDRESS
, val
);
2251 static bool ath10k_pci_has_device_gone(struct ath10k
*ar
)
2255 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
2256 return (val
== 0xffffffff);
2259 /* this function effectively clears target memory controller assert line */
2260 static void ath10k_pci_warm_reset_si0(struct ath10k
*ar
)
2264 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
2265 ath10k_pci_soc_write32(ar
, SOC_RESET_CONTROL_ADDRESS
,
2266 val
| SOC_RESET_CONTROL_SI0_RST_MASK
);
2267 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
2271 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
2272 ath10k_pci_soc_write32(ar
, SOC_RESET_CONTROL_ADDRESS
,
2273 val
& ~SOC_RESET_CONTROL_SI0_RST_MASK
);
2274 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
2279 static void ath10k_pci_warm_reset_cpu(struct ath10k
*ar
)
2283 ath10k_pci_write32(ar
, FW_INDICATOR_ADDRESS
, 0);
2285 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
2286 SOC_RESET_CONTROL_ADDRESS
);
2287 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
2288 val
| SOC_RESET_CONTROL_CPU_WARM_RST_MASK
);
2291 static void ath10k_pci_warm_reset_ce(struct ath10k
*ar
)
2295 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
2296 SOC_RESET_CONTROL_ADDRESS
);
2298 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
2299 val
| SOC_RESET_CONTROL_CE_RST_MASK
);
2301 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
2302 val
& ~SOC_RESET_CONTROL_CE_RST_MASK
);
2305 static void ath10k_pci_warm_reset_clear_lf(struct ath10k
*ar
)
2309 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
2310 SOC_LF_TIMER_CONTROL0_ADDRESS
);
2311 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+
2312 SOC_LF_TIMER_CONTROL0_ADDRESS
,
2313 val
& ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK
);
2316 static int ath10k_pci_warm_reset(struct ath10k
*ar
)
2320 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot warm reset\n");
2322 spin_lock_bh(&ar
->data_lock
);
2323 ar
->stats
.fw_warm_reset_counter
++;
2324 spin_unlock_bh(&ar
->data_lock
);
2326 ath10k_pci_irq_disable(ar
);
2328 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2329 * were to access copy engine while host performs copy engine reset
2330 * then it is possible for the device to confuse pci-e controller to
2331 * the point of bringing host system to a complete stop (i.e. hang).
2333 ath10k_pci_warm_reset_si0(ar
);
2334 ath10k_pci_warm_reset_cpu(ar
);
2335 ath10k_pci_init_pipes(ar
);
2336 ath10k_pci_wait_for_target_init(ar
);
2338 ath10k_pci_warm_reset_clear_lf(ar
);
2339 ath10k_pci_warm_reset_ce(ar
);
2340 ath10k_pci_warm_reset_cpu(ar
);
2341 ath10k_pci_init_pipes(ar
);
2343 ret
= ath10k_pci_wait_for_target_init(ar
);
2345 ath10k_warn(ar
, "failed to wait for target init: %d\n", ret
);
2349 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot warm reset complete\n");
2354 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k
*ar
)
2356 ath10k_pci_irq_disable(ar
);
2357 return ath10k_pci_qca99x0_chip_reset(ar
);
2360 static int ath10k_pci_safe_chip_reset(struct ath10k
*ar
)
2362 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2364 if (!ar_pci
->pci_soft_reset
)
2367 return ar_pci
->pci_soft_reset(ar
);
2370 static int ath10k_pci_qca988x_chip_reset(struct ath10k
*ar
)
2375 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot 988x chip reset\n");
2377 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2378 * It is thus preferred to use warm reset which is safer but may not be
2379 * able to recover the device from all possible fail scenarios.
2381 * Warm reset doesn't always work on first try so attempt it a few
2382 * times before giving up.
2384 for (i
= 0; i
< ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
; i
++) {
2385 ret
= ath10k_pci_warm_reset(ar
);
2387 ath10k_warn(ar
, "failed to warm reset attempt %d of %d: %d\n",
2388 i
+ 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
,
2393 /* FIXME: Sometimes copy engine doesn't recover after warm
2394 * reset. In most cases this needs cold reset. In some of these
2395 * cases the device is in such a state that a cold reset may
2398 * Reading any host interest register via copy engine is
2399 * sufficient to verify if device is capable of booting
2402 ret
= ath10k_pci_init_pipes(ar
);
2404 ath10k_warn(ar
, "failed to init copy engine: %d\n",
2409 ret
= ath10k_pci_diag_read32(ar
, QCA988X_HOST_INTEREST_ADDRESS
,
2412 ath10k_warn(ar
, "failed to poke copy engine: %d\n",
2417 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot chip reset complete (warm)\n");
2421 if (ath10k_pci_reset_mode
== ATH10K_PCI_RESET_WARM_ONLY
) {
2422 ath10k_warn(ar
, "refusing cold reset as requested\n");
2426 ret
= ath10k_pci_cold_reset(ar
);
2428 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
2432 ret
= ath10k_pci_wait_for_target_init(ar
);
2434 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
2439 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca988x chip reset complete (cold)\n");
2444 static int ath10k_pci_qca6174_chip_reset(struct ath10k
*ar
)
2448 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca6174 chip reset\n");
2450 /* FIXME: QCA6174 requires cold + warm reset to work. */
2452 ret
= ath10k_pci_cold_reset(ar
);
2454 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
2458 ret
= ath10k_pci_wait_for_target_init(ar
);
2460 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
2465 ret
= ath10k_pci_warm_reset(ar
);
2467 ath10k_warn(ar
, "failed to warm reset: %d\n", ret
);
2471 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca6174 chip reset complete (cold)\n");
2476 static int ath10k_pci_qca99x0_chip_reset(struct ath10k
*ar
)
2480 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca99x0 chip reset\n");
2482 ret
= ath10k_pci_cold_reset(ar
);
2484 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
2488 ret
= ath10k_pci_wait_for_target_init(ar
);
2490 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
2495 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca99x0 chip reset complete (cold)\n");
2500 static int ath10k_pci_chip_reset(struct ath10k
*ar
)
2502 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2504 if (WARN_ON(!ar_pci
->pci_hard_reset
))
2507 return ar_pci
->pci_hard_reset(ar
);
2510 static int ath10k_pci_hif_power_up(struct ath10k
*ar
)
2512 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2515 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power up\n");
2517 pcie_capability_read_word(ar_pci
->pdev
, PCI_EXP_LNKCTL
,
2519 pcie_capability_write_word(ar_pci
->pdev
, PCI_EXP_LNKCTL
,
2520 ar_pci
->link_ctl
& ~PCI_EXP_LNKCTL_ASPMC
);
2523 * Bring the target up cleanly.
2525 * The target may be in an undefined state with an AUX-powered Target
2526 * and a Host in WoW mode. If the Host crashes, loses power, or is
2527 * restarted (without unloading the driver) then the Target is left
2528 * (aux) powered and running. On a subsequent driver load, the Target
2529 * is in an unexpected state. We try to catch that here in order to
2530 * reset the Target and retry the probe.
2532 ret
= ath10k_pci_chip_reset(ar
);
2534 if (ath10k_pci_has_fw_crashed(ar
)) {
2535 ath10k_warn(ar
, "firmware crashed during chip reset\n");
2536 ath10k_pci_fw_crashed_clear(ar
);
2537 ath10k_pci_fw_crashed_dump(ar
);
2540 ath10k_err(ar
, "failed to reset chip: %d\n", ret
);
2544 ret
= ath10k_pci_init_pipes(ar
);
2546 ath10k_err(ar
, "failed to initialize CE: %d\n", ret
);
2550 ret
= ath10k_pci_init_config(ar
);
2552 ath10k_err(ar
, "failed to setup init config: %d\n", ret
);
2556 ret
= ath10k_pci_wake_target_cpu(ar
);
2558 ath10k_err(ar
, "could not wake up target CPU: %d\n", ret
);
2565 ath10k_pci_ce_deinit(ar
);
2571 void ath10k_pci_hif_power_down(struct ath10k
*ar
)
2573 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power down\n");
2575 /* Currently hif_power_up performs effectively a reset and hif_stop
2576 * resets the chip as well so there's no point in resetting here.
2582 static int ath10k_pci_hif_suspend(struct ath10k
*ar
)
2584 /* The grace timer can still be counting down and ar->ps_awake be true.
2585 * It is known that the device may be asleep after resuming regardless
2586 * of the SoC powersave state before suspending. Hence make sure the
2587 * device is asleep before proceeding.
2589 ath10k_pci_sleep_sync(ar
);
2594 static int ath10k_pci_hif_resume(struct ath10k
*ar
)
2596 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2597 struct pci_dev
*pdev
= ar_pci
->pdev
;
2601 ret
= ath10k_pci_force_wake(ar
);
2603 ath10k_err(ar
, "failed to wake up target: %d\n", ret
);
2607 /* Suspend/Resume resets the PCI configuration space, so we have to
2608 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2609 * from interfering with C3 CPU state. pci_restore_state won't help
2610 * here since it only restores the first 64 bytes pci config header.
2612 pci_read_config_dword(pdev
, 0x40, &val
);
2613 if ((val
& 0x0000ff00) != 0)
2614 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
2620 static bool ath10k_pci_validate_cal(void *data
, size_t size
)
2622 __le16
*cal_words
= data
;
2629 for (i
= 0; i
< size
/ 2; i
++)
2630 checksum
^= le16_to_cpu(cal_words
[i
]);
2632 return checksum
== 0xffff;
2635 static void ath10k_pci_enable_eeprom(struct ath10k
*ar
)
2637 /* Enable SI clock */
2638 ath10k_pci_soc_write32(ar
, CLOCK_CONTROL_OFFSET
, 0x0);
2640 /* Configure GPIOs for I2C operation */
2641 ath10k_pci_write32(ar
,
2642 GPIO_BASE_ADDRESS
+ GPIO_PIN0_OFFSET
+
2643 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN
,
2644 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG
,
2646 SM(1, GPIO_PIN0_PAD_PULL
));
2648 ath10k_pci_write32(ar
,
2649 GPIO_BASE_ADDRESS
+ GPIO_PIN0_OFFSET
+
2650 4 * QCA9887_1_0_SI_CLK_GPIO_PIN
,
2651 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG
, GPIO_PIN0_CONFIG
) |
2652 SM(1, GPIO_PIN0_PAD_PULL
));
2654 ath10k_pci_write32(ar
,
2656 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS
,
2657 1u << QCA9887_1_0_SI_CLK_GPIO_PIN
);
2659 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
2660 ath10k_pci_write32(ar
,
2661 SI_BASE_ADDRESS
+ SI_CONFIG_OFFSET
,
2662 SM(1, SI_CONFIG_ERR_INT
) |
2663 SM(1, SI_CONFIG_BIDIR_OD_DATA
) |
2664 SM(1, SI_CONFIG_I2C
) |
2665 SM(1, SI_CONFIG_POS_SAMPLE
) |
2666 SM(1, SI_CONFIG_INACTIVE_DATA
) |
2667 SM(1, SI_CONFIG_INACTIVE_CLK
) |
2668 SM(8, SI_CONFIG_DIVIDER
));
2671 static int ath10k_pci_read_eeprom(struct ath10k
*ar
, u16 addr
, u8
*out
)
2676 /* set device select byte and for the read operation */
2677 reg
= QCA9887_EEPROM_SELECT_READ
|
2678 SM(addr
, QCA9887_EEPROM_ADDR_LO
) |
2679 SM(addr
>> 8, QCA9887_EEPROM_ADDR_HI
);
2680 ath10k_pci_write32(ar
, SI_BASE_ADDRESS
+ SI_TX_DATA0_OFFSET
, reg
);
2682 /* write transmit data, transfer length, and START bit */
2683 ath10k_pci_write32(ar
, SI_BASE_ADDRESS
+ SI_CS_OFFSET
,
2684 SM(1, SI_CS_START
) | SM(1, SI_CS_RX_CNT
) |
2685 SM(4, SI_CS_TX_CNT
));
2687 /* wait max 1 sec */
2688 wait_limit
= 100000;
2690 /* wait for SI_CS_DONE_INT */
2692 reg
= ath10k_pci_read32(ar
, SI_BASE_ADDRESS
+ SI_CS_OFFSET
);
2693 if (MS(reg
, SI_CS_DONE_INT
))
2698 } while (wait_limit
> 0);
2700 if (!MS(reg
, SI_CS_DONE_INT
)) {
2701 ath10k_err(ar
, "timeout while reading device EEPROM at %04x\n",
2706 /* clear SI_CS_DONE_INT */
2707 ath10k_pci_write32(ar
, SI_BASE_ADDRESS
+ SI_CS_OFFSET
, reg
);
2709 if (MS(reg
, SI_CS_DONE_ERR
)) {
2710 ath10k_err(ar
, "failed to read device EEPROM at %04x\n", addr
);
2714 /* extract receive data */
2715 reg
= ath10k_pci_read32(ar
, SI_BASE_ADDRESS
+ SI_RX_DATA0_OFFSET
);
2721 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k
*ar
, void **data
,
2728 if (!QCA_REV_9887(ar
))
2731 calsize
= ar
->hw_params
.cal_data_len
;
2732 caldata
= kmalloc(calsize
, GFP_KERNEL
);
2736 ath10k_pci_enable_eeprom(ar
);
2738 for (i
= 0; i
< calsize
; i
++) {
2739 ret
= ath10k_pci_read_eeprom(ar
, i
, &caldata
[i
]);
2744 if (!ath10k_pci_validate_cal(caldata
, calsize
))
2748 *data_len
= calsize
;
2758 static const struct ath10k_hif_ops ath10k_pci_hif_ops
= {
2759 .tx_sg
= ath10k_pci_hif_tx_sg
,
2760 .diag_read
= ath10k_pci_hif_diag_read
,
2761 .diag_write
= ath10k_pci_diag_write_mem
,
2762 .exchange_bmi_msg
= ath10k_pci_hif_exchange_bmi_msg
,
2763 .start
= ath10k_pci_hif_start
,
2764 .stop
= ath10k_pci_hif_stop
,
2765 .map_service_to_pipe
= ath10k_pci_hif_map_service_to_pipe
,
2766 .get_default_pipe
= ath10k_pci_hif_get_default_pipe
,
2767 .send_complete_check
= ath10k_pci_hif_send_complete_check
,
2768 .get_free_queue_number
= ath10k_pci_hif_get_free_queue_number
,
2769 .power_up
= ath10k_pci_hif_power_up
,
2770 .power_down
= ath10k_pci_hif_power_down
,
2771 .read32
= ath10k_pci_read32
,
2772 .write32
= ath10k_pci_write32
,
2774 .suspend
= ath10k_pci_hif_suspend
,
2775 .resume
= ath10k_pci_hif_resume
,
2777 .fetch_cal_eeprom
= ath10k_pci_hif_fetch_cal_eeprom
,
2781 * Top-level interrupt handler for all PCI interrupts from a Target.
2782 * When a block of MSI interrupts is allocated, this top-level handler
2783 * is not used; instead, we directly call the correct sub-handler.
2785 static irqreturn_t
ath10k_pci_interrupt_handler(int irq
, void *arg
)
2787 struct ath10k
*ar
= arg
;
2788 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2791 if (ath10k_pci_has_device_gone(ar
))
2794 ret
= ath10k_pci_force_wake(ar
);
2796 ath10k_warn(ar
, "failed to wake device up on irq: %d\n", ret
);
2800 if ((ar_pci
->oper_irq_mode
== ATH10K_PCI_IRQ_LEGACY
) &&
2801 !ath10k_pci_irq_pending(ar
))
2804 ath10k_pci_disable_and_clear_legacy_irq(ar
);
2805 ath10k_pci_irq_msi_fw_mask(ar
);
2806 napi_schedule(&ar
->napi
);
2811 static int ath10k_pci_napi_poll(struct napi_struct
*ctx
, int budget
)
2813 struct ath10k
*ar
= container_of(ctx
, struct ath10k
, napi
);
2816 if (ath10k_pci_has_fw_crashed(ar
)) {
2817 ath10k_pci_fw_crashed_clear(ar
);
2818 ath10k_pci_fw_crashed_dump(ar
);
2823 ath10k_ce_per_engine_service_any(ar
);
2825 done
= ath10k_htt_txrx_compl_task(ar
, budget
);
2827 if (done
< budget
) {
2828 napi_complete_done(ctx
, done
);
2829 /* In case of MSI, it is possible that interrupts are received
2830 * while NAPI poll is inprogress. So pending interrupts that are
2831 * received after processing all copy engine pipes by NAPI poll
2832 * will not be handled again. This is causing failure to
2833 * complete boot sequence in x86 platform. So before enabling
2834 * interrupts safer to check for pending interrupts for
2835 * immediate servicing.
2837 if (ath10k_ce_interrupt_summary(ar
)) {
2838 napi_reschedule(ctx
);
2841 ath10k_pci_enable_legacy_irq(ar
);
2842 ath10k_pci_irq_msi_fw_unmask(ar
);
2849 static int ath10k_pci_request_irq_msi(struct ath10k
*ar
)
2851 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2854 ret
= request_irq(ar_pci
->pdev
->irq
,
2855 ath10k_pci_interrupt_handler
,
2856 IRQF_SHARED
, "ath10k_pci", ar
);
2858 ath10k_warn(ar
, "failed to request MSI irq %d: %d\n",
2859 ar_pci
->pdev
->irq
, ret
);
2866 static int ath10k_pci_request_irq_legacy(struct ath10k
*ar
)
2868 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2871 ret
= request_irq(ar_pci
->pdev
->irq
,
2872 ath10k_pci_interrupt_handler
,
2873 IRQF_SHARED
, "ath10k_pci", ar
);
2875 ath10k_warn(ar
, "failed to request legacy irq %d: %d\n",
2876 ar_pci
->pdev
->irq
, ret
);
2883 static int ath10k_pci_request_irq(struct ath10k
*ar
)
2885 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2887 switch (ar_pci
->oper_irq_mode
) {
2888 case ATH10K_PCI_IRQ_LEGACY
:
2889 return ath10k_pci_request_irq_legacy(ar
);
2890 case ATH10K_PCI_IRQ_MSI
:
2891 return ath10k_pci_request_irq_msi(ar
);
2897 static void ath10k_pci_free_irq(struct ath10k
*ar
)
2899 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2901 free_irq(ar_pci
->pdev
->irq
, ar
);
2904 void ath10k_pci_init_napi(struct ath10k
*ar
)
2906 netif_napi_add(&ar
->napi_dev
, &ar
->napi
, ath10k_pci_napi_poll
,
2907 ATH10K_NAPI_BUDGET
);
2910 static int ath10k_pci_init_irq(struct ath10k
*ar
)
2912 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2915 ath10k_pci_init_napi(ar
);
2917 if (ath10k_pci_irq_mode
!= ATH10K_PCI_IRQ_AUTO
)
2918 ath10k_info(ar
, "limiting irq mode to: %d\n",
2919 ath10k_pci_irq_mode
);
2922 if (ath10k_pci_irq_mode
!= ATH10K_PCI_IRQ_LEGACY
) {
2923 ar_pci
->oper_irq_mode
= ATH10K_PCI_IRQ_MSI
;
2924 ret
= pci_enable_msi(ar_pci
->pdev
);
2933 * A potential race occurs here: The CORE_BASE write
2934 * depends on target correctly decoding AXI address but
2935 * host won't know when target writes BAR to CORE_CTRL.
2936 * This write might get lost if target has NOT written BAR.
2937 * For now, fix the race by repeating the write in below
2938 * synchronization checking.
2940 ar_pci
->oper_irq_mode
= ATH10K_PCI_IRQ_LEGACY
;
2942 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
2943 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
2948 static void ath10k_pci_deinit_irq_legacy(struct ath10k
*ar
)
2950 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
2954 static int ath10k_pci_deinit_irq(struct ath10k
*ar
)
2956 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2958 switch (ar_pci
->oper_irq_mode
) {
2959 case ATH10K_PCI_IRQ_LEGACY
:
2960 ath10k_pci_deinit_irq_legacy(ar
);
2963 pci_disable_msi(ar_pci
->pdev
);
2970 int ath10k_pci_wait_for_target_init(struct ath10k
*ar
)
2972 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2973 unsigned long timeout
;
2976 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot waiting target to initialise\n");
2978 timeout
= jiffies
+ msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT
);
2981 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
2983 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot target indicator %x\n",
2986 /* target should never return this */
2987 if (val
== 0xffffffff)
2990 /* the device has crashed so don't bother trying anymore */
2991 if (val
& FW_IND_EVENT_PENDING
)
2994 if (val
& FW_IND_INITIALIZED
)
2997 if (ar_pci
->oper_irq_mode
== ATH10K_PCI_IRQ_LEGACY
)
2998 /* Fix potential race by repeating CORE_BASE writes */
2999 ath10k_pci_enable_legacy_irq(ar
);
3002 } while (time_before(jiffies
, timeout
));
3004 ath10k_pci_disable_and_clear_legacy_irq(ar
);
3005 ath10k_pci_irq_msi_fw_mask(ar
);
3007 if (val
== 0xffffffff) {
3008 ath10k_err(ar
, "failed to read device register, device is gone\n");
3012 if (val
& FW_IND_EVENT_PENDING
) {
3013 ath10k_warn(ar
, "device has crashed during init\n");
3017 if (!(val
& FW_IND_INITIALIZED
)) {
3018 ath10k_err(ar
, "failed to receive initialized event from target: %08x\n",
3023 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot target initialised\n");
3027 static int ath10k_pci_cold_reset(struct ath10k
*ar
)
3031 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot cold reset\n");
3033 spin_lock_bh(&ar
->data_lock
);
3035 ar
->stats
.fw_cold_reset_counter
++;
3037 spin_unlock_bh(&ar
->data_lock
);
3039 /* Put Target, including PCIe, into RESET. */
3040 val
= ath10k_pci_reg_read32(ar
, SOC_GLOBAL_RESET_ADDRESS
);
3042 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
3044 /* After writing into SOC_GLOBAL_RESET to put device into
3045 * reset and pulling out of reset pcie may not be stable
3046 * for any immediate pcie register access and cause bus error,
3047 * add delay before any pcie access request to fix this issue.
3051 /* Pull Target, including PCIe, out of RESET. */
3053 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
3057 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot cold reset complete\n");
3062 static int ath10k_pci_claim(struct ath10k
*ar
)
3064 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
3065 struct pci_dev
*pdev
= ar_pci
->pdev
;
3068 pci_set_drvdata(pdev
, ar
);
3070 ret
= pci_enable_device(pdev
);
3072 ath10k_err(ar
, "failed to enable pci device: %d\n", ret
);
3076 ret
= pci_request_region(pdev
, BAR_NUM
, "ath");
3078 ath10k_err(ar
, "failed to request region BAR%d: %d\n", BAR_NUM
,
3083 /* Target expects 32 bit DMA. Enforce it. */
3084 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3086 ath10k_err(ar
, "failed to set dma mask to 32-bit: %d\n", ret
);
3090 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
3092 ath10k_err(ar
, "failed to set consistent dma mask to 32-bit: %d\n",
3097 pci_set_master(pdev
);
3099 /* Arrange for access to Target SoC registers. */
3100 ar_pci
->mem_len
= pci_resource_len(pdev
, BAR_NUM
);
3101 ar_pci
->mem
= pci_iomap(pdev
, BAR_NUM
, 0);
3103 ath10k_err(ar
, "failed to iomap BAR%d\n", BAR_NUM
);
3108 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot pci_mem 0x%pK\n", ar_pci
->mem
);
3112 pci_clear_master(pdev
);
3115 pci_release_region(pdev
, BAR_NUM
);
3118 pci_disable_device(pdev
);
3123 static void ath10k_pci_release(struct ath10k
*ar
)
3125 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
3126 struct pci_dev
*pdev
= ar_pci
->pdev
;
3128 pci_iounmap(pdev
, ar_pci
->mem
);
3129 pci_release_region(pdev
, BAR_NUM
);
3130 pci_clear_master(pdev
);
3131 pci_disable_device(pdev
);
3134 static bool ath10k_pci_chip_is_supported(u32 dev_id
, u32 chip_id
)
3136 const struct ath10k_pci_supp_chip
*supp_chip
;
3138 u32 rev_id
= MS(chip_id
, SOC_CHIP_ID_REV
);
3140 for (i
= 0; i
< ARRAY_SIZE(ath10k_pci_supp_chips
); i
++) {
3141 supp_chip
= &ath10k_pci_supp_chips
[i
];
3143 if (supp_chip
->dev_id
== dev_id
&&
3144 supp_chip
->rev_id
== rev_id
)
3151 int ath10k_pci_setup_resource(struct ath10k
*ar
)
3153 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
3154 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
3157 spin_lock_init(&ce
->ce_lock
);
3158 spin_lock_init(&ar_pci
->ps_lock
);
3160 setup_timer(&ar_pci
->rx_post_retry
, ath10k_pci_rx_replenish_retry
,
3163 if (QCA_REV_6174(ar
) || QCA_REV_9377(ar
))
3164 ath10k_pci_override_ce_config(ar
);
3166 ret
= ath10k_pci_alloc_pipes(ar
);
3168 ath10k_err(ar
, "failed to allocate copy engine pipes: %d\n",
3176 void ath10k_pci_release_resource(struct ath10k
*ar
)
3178 ath10k_pci_rx_retry_sync(ar
);
3179 netif_napi_del(&ar
->napi
);
3180 ath10k_pci_ce_deinit(ar
);
3181 ath10k_pci_free_pipes(ar
);
3184 static const struct ath10k_bus_ops ath10k_pci_bus_ops
= {
3185 .read32
= ath10k_bus_pci_read32
,
3186 .write32
= ath10k_bus_pci_write32
,
3187 .get_num_banks
= ath10k_pci_get_num_banks
,
3190 static int ath10k_pci_probe(struct pci_dev
*pdev
,
3191 const struct pci_device_id
*pci_dev
)
3195 struct ath10k_pci
*ar_pci
;
3196 enum ath10k_hw_rev hw_rev
;
3199 int (*pci_soft_reset
)(struct ath10k
*ar
);
3200 int (*pci_hard_reset
)(struct ath10k
*ar
);
3201 u32 (*targ_cpu_to_ce_addr
)(struct ath10k
*ar
, u32 addr
);
3203 switch (pci_dev
->device
) {
3204 case QCA988X_2_0_DEVICE_ID
:
3205 hw_rev
= ATH10K_HW_QCA988X
;
3207 pci_soft_reset
= ath10k_pci_warm_reset
;
3208 pci_hard_reset
= ath10k_pci_qca988x_chip_reset
;
3209 targ_cpu_to_ce_addr
= ath10k_pci_qca988x_targ_cpu_to_ce_addr
;
3211 case QCA9887_1_0_DEVICE_ID
:
3212 hw_rev
= ATH10K_HW_QCA9887
;
3214 pci_soft_reset
= ath10k_pci_warm_reset
;
3215 pci_hard_reset
= ath10k_pci_qca988x_chip_reset
;
3216 targ_cpu_to_ce_addr
= ath10k_pci_qca988x_targ_cpu_to_ce_addr
;
3218 case QCA6164_2_1_DEVICE_ID
:
3219 case QCA6174_2_1_DEVICE_ID
:
3220 hw_rev
= ATH10K_HW_QCA6174
;
3222 pci_soft_reset
= ath10k_pci_warm_reset
;
3223 pci_hard_reset
= ath10k_pci_qca6174_chip_reset
;
3224 targ_cpu_to_ce_addr
= ath10k_pci_qca988x_targ_cpu_to_ce_addr
;
3226 case QCA99X0_2_0_DEVICE_ID
:
3227 hw_rev
= ATH10K_HW_QCA99X0
;
3229 pci_soft_reset
= ath10k_pci_qca99x0_soft_chip_reset
;
3230 pci_hard_reset
= ath10k_pci_qca99x0_chip_reset
;
3231 targ_cpu_to_ce_addr
= ath10k_pci_qca99x0_targ_cpu_to_ce_addr
;
3233 case QCA9984_1_0_DEVICE_ID
:
3234 hw_rev
= ATH10K_HW_QCA9984
;
3236 pci_soft_reset
= ath10k_pci_qca99x0_soft_chip_reset
;
3237 pci_hard_reset
= ath10k_pci_qca99x0_chip_reset
;
3238 targ_cpu_to_ce_addr
= ath10k_pci_qca99x0_targ_cpu_to_ce_addr
;
3240 case QCA9888_2_0_DEVICE_ID
:
3241 hw_rev
= ATH10K_HW_QCA9888
;
3243 pci_soft_reset
= ath10k_pci_qca99x0_soft_chip_reset
;
3244 pci_hard_reset
= ath10k_pci_qca99x0_chip_reset
;
3245 targ_cpu_to_ce_addr
= ath10k_pci_qca99x0_targ_cpu_to_ce_addr
;
3247 case QCA9377_1_0_DEVICE_ID
:
3248 hw_rev
= ATH10K_HW_QCA9377
;
3250 pci_soft_reset
= NULL
;
3251 pci_hard_reset
= ath10k_pci_qca6174_chip_reset
;
3252 targ_cpu_to_ce_addr
= ath10k_pci_qca988x_targ_cpu_to_ce_addr
;
3259 ar
= ath10k_core_create(sizeof(*ar_pci
), &pdev
->dev
, ATH10K_BUS_PCI
,
3260 hw_rev
, &ath10k_pci_hif_ops
);
3262 dev_err(&pdev
->dev
, "failed to allocate core\n");
3266 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "pci probe %04x:%04x %04x:%04x\n",
3267 pdev
->vendor
, pdev
->device
,
3268 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
3270 ar_pci
= ath10k_pci_priv(ar
);
3271 ar_pci
->pdev
= pdev
;
3272 ar_pci
->dev
= &pdev
->dev
;
3274 ar
->dev_id
= pci_dev
->device
;
3275 ar_pci
->pci_ps
= pci_ps
;
3276 ar_pci
->ce
.bus_ops
= &ath10k_pci_bus_ops
;
3277 ar_pci
->pci_soft_reset
= pci_soft_reset
;
3278 ar_pci
->pci_hard_reset
= pci_hard_reset
;
3279 ar_pci
->targ_cpu_to_ce_addr
= targ_cpu_to_ce_addr
;
3280 ar
->ce_priv
= &ar_pci
->ce
;
3282 ar
->id
.vendor
= pdev
->vendor
;
3283 ar
->id
.device
= pdev
->device
;
3284 ar
->id
.subsystem_vendor
= pdev
->subsystem_vendor
;
3285 ar
->id
.subsystem_device
= pdev
->subsystem_device
;
3287 setup_timer(&ar_pci
->ps_timer
, ath10k_pci_ps_timer
,
3290 ret
= ath10k_pci_setup_resource(ar
);
3292 ath10k_err(ar
, "failed to setup resource: %d\n", ret
);
3293 goto err_core_destroy
;
3296 ret
= ath10k_pci_claim(ar
);
3298 ath10k_err(ar
, "failed to claim device: %d\n", ret
);
3299 goto err_free_pipes
;
3302 ret
= ath10k_pci_force_wake(ar
);
3304 ath10k_warn(ar
, "failed to wake up device : %d\n", ret
);
3308 ath10k_pci_ce_deinit(ar
);
3309 ath10k_pci_irq_disable(ar
);
3311 ret
= ath10k_pci_init_irq(ar
);
3313 ath10k_err(ar
, "failed to init irqs: %d\n", ret
);
3317 ath10k_info(ar
, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3318 ath10k_pci_get_irq_method(ar
), ar_pci
->oper_irq_mode
,
3319 ath10k_pci_irq_mode
, ath10k_pci_reset_mode
);
3321 ret
= ath10k_pci_request_irq(ar
);
3323 ath10k_warn(ar
, "failed to request irqs: %d\n", ret
);
3324 goto err_deinit_irq
;
3327 ret
= ath10k_pci_chip_reset(ar
);
3329 ath10k_err(ar
, "failed to reset chip: %d\n", ret
);
3333 chip_id
= ath10k_pci_soc_read32(ar
, SOC_CHIP_ID_ADDRESS
);
3334 if (chip_id
== 0xffffffff) {
3335 ath10k_err(ar
, "failed to get chip id\n");
3339 if (!ath10k_pci_chip_is_supported(pdev
->device
, chip_id
)) {
3340 ath10k_err(ar
, "device %04x with chip_id %08x isn't supported\n",
3341 pdev
->device
, chip_id
);
3345 ret
= ath10k_core_register(ar
, chip_id
);
3347 ath10k_err(ar
, "failed to register driver core: %d\n", ret
);
3354 ath10k_pci_free_irq(ar
);
3355 ath10k_pci_rx_retry_sync(ar
);
3358 ath10k_pci_deinit_irq(ar
);
3361 ath10k_pci_sleep_sync(ar
);
3362 ath10k_pci_release(ar
);
3365 ath10k_pci_free_pipes(ar
);
3368 ath10k_core_destroy(ar
);
3373 static void ath10k_pci_remove(struct pci_dev
*pdev
)
3375 struct ath10k
*ar
= pci_get_drvdata(pdev
);
3376 struct ath10k_pci
*ar_pci
;
3378 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci remove\n");
3383 ar_pci
= ath10k_pci_priv(ar
);
3388 ath10k_core_unregister(ar
);
3389 ath10k_pci_free_irq(ar
);
3390 ath10k_pci_deinit_irq(ar
);
3391 ath10k_pci_release_resource(ar
);
3392 ath10k_pci_sleep_sync(ar
);
3393 ath10k_pci_release(ar
);
3394 ath10k_core_destroy(ar
);
3397 MODULE_DEVICE_TABLE(pci
, ath10k_pci_id_table
);
3399 static struct pci_driver ath10k_pci_driver
= {
3400 .name
= "ath10k_pci",
3401 .id_table
= ath10k_pci_id_table
,
3402 .probe
= ath10k_pci_probe
,
3403 .remove
= ath10k_pci_remove
,
3406 static int __init
ath10k_pci_init(void)
3410 ret
= pci_register_driver(&ath10k_pci_driver
);
3412 printk(KERN_ERR
"failed to register ath10k pci driver: %d\n",
3415 ret
= ath10k_ahb_init();
3417 printk(KERN_ERR
"ahb init failed: %d\n", ret
);
3421 module_init(ath10k_pci_init
);
3423 static void __exit
ath10k_pci_exit(void)
3425 pci_unregister_driver(&ath10k_pci_driver
);
3429 module_exit(ath10k_pci_exit
);
3431 MODULE_AUTHOR("Qualcomm Atheros");
3432 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3433 MODULE_LICENSE("Dual BSD/GPL");
3435 /* QCA988x 2.0 firmware files */
3436 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API2_FILE
);
3437 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API3_FILE
);
3438 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API4_FILE
);
3439 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3440 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_BOARD_DATA_FILE
);
3441 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_BOARD_API2_FILE
);
3443 /* QCA9887 1.0 firmware files */
3444 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3445 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR
"/" QCA9887_HW_1_0_BOARD_DATA_FILE
);
3446 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR
"/" ATH10K_BOARD_API2_FILE
);
3448 /* QCA6174 2.1 firmware files */
3449 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" ATH10K_FW_API4_FILE
);
3450 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3451 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" QCA6174_HW_2_1_BOARD_DATA_FILE
);
3452 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" ATH10K_BOARD_API2_FILE
);
3454 /* QCA6174 3.1 firmware files */
3455 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" ATH10K_FW_API4_FILE
);
3456 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3457 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" ATH10K_FW_API6_FILE
);
3458 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" QCA6174_HW_3_0_BOARD_DATA_FILE
);
3459 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" ATH10K_BOARD_API2_FILE
);
3461 /* QCA9377 1.0 firmware files */
3462 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3463 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR
"/" QCA9377_HW_1_0_BOARD_DATA_FILE
);