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Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath10k / pci.c
1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 */
6
7 #include <linux/pci.h>
8 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/spinlock.h>
11 #include <linux/bitops.h>
12
13 #include "core.h"
14 #include "debug.h"
15 #include "coredump.h"
16
17 #include "targaddrs.h"
18 #include "bmi.h"
19
20 #include "hif.h"
21 #include "htc.h"
22
23 #include "ce.h"
24 #include "pci.h"
25
26 enum ath10k_pci_reset_mode {
27 ATH10K_PCI_RESET_AUTO = 0,
28 ATH10K_PCI_RESET_WARM_ONLY = 1,
29 };
30
31 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
32 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
33
34 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
35 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
36
37 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
38 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
39
40 /* how long wait to wait for target to initialise, in ms */
41 #define ATH10K_PCI_TARGET_WAIT 3000
42 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
43
44 /* Maximum number of bytes that can be handled atomically by
45 * diag read and write.
46 */
47 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000
48
49 #define QCA99X0_PCIE_BAR0_START_REG 0x81030
50 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c
51 #define QCA99X0_CPU_MEM_DATA_REG 0x4d010
52
53 static const struct pci_device_id ath10k_pci_id_table[] = {
54 /* PCI-E QCA988X V2 (Ubiquiti branded) */
55 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) },
56
57 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
58 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
59 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
60 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
61 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
62 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
63 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
64 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
65 {0}
66 };
67
68 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
69 /* QCA988X pre 2.0 chips are not supported because they need some nasty
70 * hacks. ath10k doesn't have them and these devices crash horribly
71 * because of that.
72 */
73 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV },
74 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
75
76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
78 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
79 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
80 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
81
82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
84 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
85 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
86 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
87
88 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
89
90 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
91
92 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },
93
94 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
95 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
96
97 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
98 };
99
100 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
101 static int ath10k_pci_cold_reset(struct ath10k *ar);
102 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
103 static int ath10k_pci_init_irq(struct ath10k *ar);
104 static int ath10k_pci_deinit_irq(struct ath10k *ar);
105 static int ath10k_pci_request_irq(struct ath10k *ar);
106 static void ath10k_pci_free_irq(struct ath10k *ar);
107 static int ath10k_pci_bmi_wait(struct ath10k *ar,
108 struct ath10k_ce_pipe *tx_pipe,
109 struct ath10k_ce_pipe *rx_pipe,
110 struct bmi_xfer *xfer);
111 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
112 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
113 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
114 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
115 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
116 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
117 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
118
119 static struct ce_attr host_ce_config_wlan[] = {
120 /* CE0: host->target HTC control and raw streams */
121 {
122 .flags = CE_ATTR_FLAGS,
123 .src_nentries = 16,
124 .src_sz_max = 256,
125 .dest_nentries = 0,
126 .send_cb = ath10k_pci_htc_tx_cb,
127 },
128
129 /* CE1: target->host HTT + HTC control */
130 {
131 .flags = CE_ATTR_FLAGS,
132 .src_nentries = 0,
133 .src_sz_max = 2048,
134 .dest_nentries = 512,
135 .recv_cb = ath10k_pci_htt_htc_rx_cb,
136 },
137
138 /* CE2: target->host WMI */
139 {
140 .flags = CE_ATTR_FLAGS,
141 .src_nentries = 0,
142 .src_sz_max = 2048,
143 .dest_nentries = 128,
144 .recv_cb = ath10k_pci_htc_rx_cb,
145 },
146
147 /* CE3: host->target WMI */
148 {
149 .flags = CE_ATTR_FLAGS,
150 .src_nentries = 32,
151 .src_sz_max = 2048,
152 .dest_nentries = 0,
153 .send_cb = ath10k_pci_htc_tx_cb,
154 },
155
156 /* CE4: host->target HTT */
157 {
158 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
159 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
160 .src_sz_max = 256,
161 .dest_nentries = 0,
162 .send_cb = ath10k_pci_htt_tx_cb,
163 },
164
165 /* CE5: target->host HTT (HIF->HTT) */
166 {
167 .flags = CE_ATTR_FLAGS,
168 .src_nentries = 0,
169 .src_sz_max = 512,
170 .dest_nentries = 512,
171 .recv_cb = ath10k_pci_htt_rx_cb,
172 },
173
174 /* CE6: target autonomous hif_memcpy */
175 {
176 .flags = CE_ATTR_FLAGS,
177 .src_nentries = 0,
178 .src_sz_max = 0,
179 .dest_nentries = 0,
180 },
181
182 /* CE7: ce_diag, the Diagnostic Window */
183 {
184 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL,
185 .src_nentries = 2,
186 .src_sz_max = DIAG_TRANSFER_LIMIT,
187 .dest_nentries = 2,
188 },
189
190 /* CE8: target->host pktlog */
191 {
192 .flags = CE_ATTR_FLAGS,
193 .src_nentries = 0,
194 .src_sz_max = 2048,
195 .dest_nentries = 128,
196 .recv_cb = ath10k_pci_pktlog_rx_cb,
197 },
198
199 /* CE9 target autonomous qcache memcpy */
200 {
201 .flags = CE_ATTR_FLAGS,
202 .src_nentries = 0,
203 .src_sz_max = 0,
204 .dest_nentries = 0,
205 },
206
207 /* CE10: target autonomous hif memcpy */
208 {
209 .flags = CE_ATTR_FLAGS,
210 .src_nentries = 0,
211 .src_sz_max = 0,
212 .dest_nentries = 0,
213 },
214
215 /* CE11: target autonomous hif memcpy */
216 {
217 .flags = CE_ATTR_FLAGS,
218 .src_nentries = 0,
219 .src_sz_max = 0,
220 .dest_nentries = 0,
221 },
222 };
223
224 /* Target firmware's Copy Engine configuration. */
225 static struct ce_pipe_config target_ce_config_wlan[] = {
226 /* CE0: host->target HTC control and raw streams */
227 {
228 .pipenum = __cpu_to_le32(0),
229 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
230 .nentries = __cpu_to_le32(32),
231 .nbytes_max = __cpu_to_le32(256),
232 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
233 .reserved = __cpu_to_le32(0),
234 },
235
236 /* CE1: target->host HTT + HTC control */
237 {
238 .pipenum = __cpu_to_le32(1),
239 .pipedir = __cpu_to_le32(PIPEDIR_IN),
240 .nentries = __cpu_to_le32(32),
241 .nbytes_max = __cpu_to_le32(2048),
242 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
243 .reserved = __cpu_to_le32(0),
244 },
245
246 /* CE2: target->host WMI */
247 {
248 .pipenum = __cpu_to_le32(2),
249 .pipedir = __cpu_to_le32(PIPEDIR_IN),
250 .nentries = __cpu_to_le32(64),
251 .nbytes_max = __cpu_to_le32(2048),
252 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
253 .reserved = __cpu_to_le32(0),
254 },
255
256 /* CE3: host->target WMI */
257 {
258 .pipenum = __cpu_to_le32(3),
259 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
260 .nentries = __cpu_to_le32(32),
261 .nbytes_max = __cpu_to_le32(2048),
262 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
263 .reserved = __cpu_to_le32(0),
264 },
265
266 /* CE4: host->target HTT */
267 {
268 .pipenum = __cpu_to_le32(4),
269 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
270 .nentries = __cpu_to_le32(256),
271 .nbytes_max = __cpu_to_le32(256),
272 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
273 .reserved = __cpu_to_le32(0),
274 },
275
276 /* NB: 50% of src nentries, since tx has 2 frags */
277
278 /* CE5: target->host HTT (HIF->HTT) */
279 {
280 .pipenum = __cpu_to_le32(5),
281 .pipedir = __cpu_to_le32(PIPEDIR_IN),
282 .nentries = __cpu_to_le32(32),
283 .nbytes_max = __cpu_to_le32(512),
284 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
285 .reserved = __cpu_to_le32(0),
286 },
287
288 /* CE6: Reserved for target autonomous hif_memcpy */
289 {
290 .pipenum = __cpu_to_le32(6),
291 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
292 .nentries = __cpu_to_le32(32),
293 .nbytes_max = __cpu_to_le32(4096),
294 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
295 .reserved = __cpu_to_le32(0),
296 },
297
298 /* CE7 used only by Host */
299 {
300 .pipenum = __cpu_to_le32(7),
301 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
302 .nentries = __cpu_to_le32(0),
303 .nbytes_max = __cpu_to_le32(0),
304 .flags = __cpu_to_le32(0),
305 .reserved = __cpu_to_le32(0),
306 },
307
308 /* CE8 target->host packtlog */
309 {
310 .pipenum = __cpu_to_le32(8),
311 .pipedir = __cpu_to_le32(PIPEDIR_IN),
312 .nentries = __cpu_to_le32(64),
313 .nbytes_max = __cpu_to_le32(2048),
314 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
315 .reserved = __cpu_to_le32(0),
316 },
317
318 /* CE9 target autonomous qcache memcpy */
319 {
320 .pipenum = __cpu_to_le32(9),
321 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
322 .nentries = __cpu_to_le32(32),
323 .nbytes_max = __cpu_to_le32(2048),
324 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
325 .reserved = __cpu_to_le32(0),
326 },
327
328 /* It not necessary to send target wlan configuration for CE10 & CE11
329 * as these CEs are not actively used in target.
330 */
331 };
332
333 /*
334 * Map from service/endpoint to Copy Engine.
335 * This table is derived from the CE_PCI TABLE, above.
336 * It is passed to the Target at startup for use by firmware.
337 */
338 static struct service_to_pipe target_service_to_ce_map_wlan[] = {
339 {
340 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
341 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
342 __cpu_to_le32(3),
343 },
344 {
345 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
346 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
347 __cpu_to_le32(2),
348 },
349 {
350 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
351 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
352 __cpu_to_le32(3),
353 },
354 {
355 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
356 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
357 __cpu_to_le32(2),
358 },
359 {
360 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
361 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
362 __cpu_to_le32(3),
363 },
364 {
365 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
366 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
367 __cpu_to_le32(2),
368 },
369 {
370 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
371 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
372 __cpu_to_le32(3),
373 },
374 {
375 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
376 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
377 __cpu_to_le32(2),
378 },
379 {
380 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
381 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
382 __cpu_to_le32(3),
383 },
384 {
385 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
386 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
387 __cpu_to_le32(2),
388 },
389 {
390 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
391 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
392 __cpu_to_le32(0),
393 },
394 {
395 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
396 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
397 __cpu_to_le32(1),
398 },
399 { /* not used */
400 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
401 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
402 __cpu_to_le32(0),
403 },
404 { /* not used */
405 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
406 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
407 __cpu_to_le32(1),
408 },
409 {
410 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
411 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
412 __cpu_to_le32(4),
413 },
414 {
415 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
416 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
417 __cpu_to_le32(5),
418 },
419
420 /* (Additions here) */
421
422 { /* must be last */
423 __cpu_to_le32(0),
424 __cpu_to_le32(0),
425 __cpu_to_le32(0),
426 },
427 };
428
429 static bool ath10k_pci_is_awake(struct ath10k *ar)
430 {
431 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
432 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
433 RTC_STATE_ADDRESS);
434
435 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
436 }
437
438 static void __ath10k_pci_wake(struct ath10k *ar)
439 {
440 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
441
442 lockdep_assert_held(&ar_pci->ps_lock);
443
444 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
445 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
446
447 iowrite32(PCIE_SOC_WAKE_V_MASK,
448 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
449 PCIE_SOC_WAKE_ADDRESS);
450 }
451
452 static void __ath10k_pci_sleep(struct ath10k *ar)
453 {
454 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
455
456 lockdep_assert_held(&ar_pci->ps_lock);
457
458 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
459 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
460
461 iowrite32(PCIE_SOC_WAKE_RESET,
462 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
463 PCIE_SOC_WAKE_ADDRESS);
464 ar_pci->ps_awake = false;
465 }
466
467 static int ath10k_pci_wake_wait(struct ath10k *ar)
468 {
469 int tot_delay = 0;
470 int curr_delay = 5;
471
472 while (tot_delay < PCIE_WAKE_TIMEOUT) {
473 if (ath10k_pci_is_awake(ar)) {
474 if (tot_delay > PCIE_WAKE_LATE_US)
475 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
476 tot_delay / 1000);
477 return 0;
478 }
479
480 udelay(curr_delay);
481 tot_delay += curr_delay;
482
483 if (curr_delay < 50)
484 curr_delay += 5;
485 }
486
487 return -ETIMEDOUT;
488 }
489
490 static int ath10k_pci_force_wake(struct ath10k *ar)
491 {
492 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
493 unsigned long flags;
494 int ret = 0;
495
496 if (ar_pci->pci_ps)
497 return ret;
498
499 spin_lock_irqsave(&ar_pci->ps_lock, flags);
500
501 if (!ar_pci->ps_awake) {
502 iowrite32(PCIE_SOC_WAKE_V_MASK,
503 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
504 PCIE_SOC_WAKE_ADDRESS);
505
506 ret = ath10k_pci_wake_wait(ar);
507 if (ret == 0)
508 ar_pci->ps_awake = true;
509 }
510
511 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
512
513 return ret;
514 }
515
516 static void ath10k_pci_force_sleep(struct ath10k *ar)
517 {
518 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
519 unsigned long flags;
520
521 spin_lock_irqsave(&ar_pci->ps_lock, flags);
522
523 iowrite32(PCIE_SOC_WAKE_RESET,
524 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
525 PCIE_SOC_WAKE_ADDRESS);
526 ar_pci->ps_awake = false;
527
528 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
529 }
530
531 static int ath10k_pci_wake(struct ath10k *ar)
532 {
533 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
534 unsigned long flags;
535 int ret = 0;
536
537 if (ar_pci->pci_ps == 0)
538 return ret;
539
540 spin_lock_irqsave(&ar_pci->ps_lock, flags);
541
542 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
543 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
544
545 /* This function can be called very frequently. To avoid excessive
546 * CPU stalls for MMIO reads use a cache var to hold the device state.
547 */
548 if (!ar_pci->ps_awake) {
549 __ath10k_pci_wake(ar);
550
551 ret = ath10k_pci_wake_wait(ar);
552 if (ret == 0)
553 ar_pci->ps_awake = true;
554 }
555
556 if (ret == 0) {
557 ar_pci->ps_wake_refcount++;
558 WARN_ON(ar_pci->ps_wake_refcount == 0);
559 }
560
561 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
562
563 return ret;
564 }
565
566 static void ath10k_pci_sleep(struct ath10k *ar)
567 {
568 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
569 unsigned long flags;
570
571 if (ar_pci->pci_ps == 0)
572 return;
573
574 spin_lock_irqsave(&ar_pci->ps_lock, flags);
575
576 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
577 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
578
579 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
580 goto skip;
581
582 ar_pci->ps_wake_refcount--;
583
584 mod_timer(&ar_pci->ps_timer, jiffies +
585 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
586
587 skip:
588 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
589 }
590
591 static void ath10k_pci_ps_timer(struct timer_list *t)
592 {
593 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer);
594 struct ath10k *ar = ar_pci->ar;
595 unsigned long flags;
596
597 spin_lock_irqsave(&ar_pci->ps_lock, flags);
598
599 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
600 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
601
602 if (ar_pci->ps_wake_refcount > 0)
603 goto skip;
604
605 __ath10k_pci_sleep(ar);
606
607 skip:
608 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
609 }
610
611 static void ath10k_pci_sleep_sync(struct ath10k *ar)
612 {
613 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
614 unsigned long flags;
615
616 if (ar_pci->pci_ps == 0) {
617 ath10k_pci_force_sleep(ar);
618 return;
619 }
620
621 del_timer_sync(&ar_pci->ps_timer);
622
623 spin_lock_irqsave(&ar_pci->ps_lock, flags);
624 WARN_ON(ar_pci->ps_wake_refcount > 0);
625 __ath10k_pci_sleep(ar);
626 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
627 }
628
629 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
630 {
631 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
632 int ret;
633
634 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
635 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
636 offset, offset + sizeof(value), ar_pci->mem_len);
637 return;
638 }
639
640 ret = ath10k_pci_wake(ar);
641 if (ret) {
642 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
643 value, offset, ret);
644 return;
645 }
646
647 iowrite32(value, ar_pci->mem + offset);
648 ath10k_pci_sleep(ar);
649 }
650
651 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
652 {
653 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
654 u32 val;
655 int ret;
656
657 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
658 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
659 offset, offset + sizeof(val), ar_pci->mem_len);
660 return 0;
661 }
662
663 ret = ath10k_pci_wake(ar);
664 if (ret) {
665 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
666 offset, ret);
667 return 0xffffffff;
668 }
669
670 val = ioread32(ar_pci->mem + offset);
671 ath10k_pci_sleep(ar);
672
673 return val;
674 }
675
676 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
677 {
678 struct ath10k_ce *ce = ath10k_ce_priv(ar);
679
680 ce->bus_ops->write32(ar, offset, value);
681 }
682
683 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
684 {
685 struct ath10k_ce *ce = ath10k_ce_priv(ar);
686
687 return ce->bus_ops->read32(ar, offset);
688 }
689
690 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
691 {
692 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
693 }
694
695 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
696 {
697 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
698 }
699
700 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
701 {
702 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
703 }
704
705 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
706 {
707 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
708 }
709
710 bool ath10k_pci_irq_pending(struct ath10k *ar)
711 {
712 u32 cause;
713
714 /* Check if the shared legacy irq is for us */
715 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
716 PCIE_INTR_CAUSE_ADDRESS);
717 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
718 return true;
719
720 return false;
721 }
722
723 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
724 {
725 /* IMPORTANT: INTR_CLR register has to be set after
726 * INTR_ENABLE is set to 0, otherwise interrupt can not be
727 * really cleared.
728 */
729 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
730 0);
731 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
732 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
733
734 /* IMPORTANT: this extra read transaction is required to
735 * flush the posted write buffer.
736 */
737 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
738 PCIE_INTR_ENABLE_ADDRESS);
739 }
740
741 void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
742 {
743 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
744 PCIE_INTR_ENABLE_ADDRESS,
745 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
746
747 /* IMPORTANT: this extra read transaction is required to
748 * flush the posted write buffer.
749 */
750 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
751 PCIE_INTR_ENABLE_ADDRESS);
752 }
753
754 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
755 {
756 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
757
758 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
759 return "msi";
760
761 return "legacy";
762 }
763
764 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
765 {
766 struct ath10k *ar = pipe->hif_ce_state;
767 struct ath10k_ce *ce = ath10k_ce_priv(ar);
768 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
769 struct sk_buff *skb;
770 dma_addr_t paddr;
771 int ret;
772
773 skb = dev_alloc_skb(pipe->buf_sz);
774 if (!skb)
775 return -ENOMEM;
776
777 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
778
779 paddr = dma_map_single(ar->dev, skb->data,
780 skb->len + skb_tailroom(skb),
781 DMA_FROM_DEVICE);
782 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
783 ath10k_warn(ar, "failed to dma map pci rx buf\n");
784 dev_kfree_skb_any(skb);
785 return -EIO;
786 }
787
788 ATH10K_SKB_RXCB(skb)->paddr = paddr;
789
790 spin_lock_bh(&ce->ce_lock);
791 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
792 spin_unlock_bh(&ce->ce_lock);
793 if (ret) {
794 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
795 DMA_FROM_DEVICE);
796 dev_kfree_skb_any(skb);
797 return ret;
798 }
799
800 return 0;
801 }
802
803 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
804 {
805 struct ath10k *ar = pipe->hif_ce_state;
806 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
807 struct ath10k_ce *ce = ath10k_ce_priv(ar);
808 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
809 int ret, num;
810
811 if (pipe->buf_sz == 0)
812 return;
813
814 if (!ce_pipe->dest_ring)
815 return;
816
817 spin_lock_bh(&ce->ce_lock);
818 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
819 spin_unlock_bh(&ce->ce_lock);
820
821 while (num >= 0) {
822 ret = __ath10k_pci_rx_post_buf(pipe);
823 if (ret) {
824 if (ret == -ENOSPC)
825 break;
826 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
827 mod_timer(&ar_pci->rx_post_retry, jiffies +
828 ATH10K_PCI_RX_POST_RETRY_MS);
829 break;
830 }
831 num--;
832 }
833 }
834
835 void ath10k_pci_rx_post(struct ath10k *ar)
836 {
837 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
838 int i;
839
840 for (i = 0; i < CE_COUNT; i++)
841 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
842 }
843
844 void ath10k_pci_rx_replenish_retry(struct timer_list *t)
845 {
846 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry);
847 struct ath10k *ar = ar_pci->ar;
848
849 ath10k_pci_rx_post(ar);
850 }
851
852 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
853 {
854 u32 val = 0, region = addr & 0xfffff;
855
856 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
857 & 0x7ff) << 21;
858 val |= 0x100000 | region;
859 return val;
860 }
861
862 /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr.
863 * Support to access target space below 1M for qca6174 and qca9377.
864 * If target space is below 1M, the bit[20] of converted CE addr is 0.
865 * Otherwise bit[20] of converted CE addr is 1.
866 */
867 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
868 {
869 u32 val = 0, region = addr & 0xfffff;
870
871 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
872 & 0x7ff) << 21;
873 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region;
874 return val;
875 }
876
877 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
878 {
879 u32 val = 0, region = addr & 0xfffff;
880
881 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
882 val |= 0x100000 | region;
883 return val;
884 }
885
886 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
887 {
888 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
889
890 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr))
891 return -ENOTSUPP;
892
893 return ar_pci->targ_cpu_to_ce_addr(ar, addr);
894 }
895
896 /*
897 * Diagnostic read/write access is provided for startup/config/debug usage.
898 * Caller must guarantee proper alignment, when applicable, and single user
899 * at any moment.
900 */
901 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
902 int nbytes)
903 {
904 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
905 int ret = 0;
906 u32 *buf;
907 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
908 struct ath10k_ce_pipe *ce_diag;
909 /* Host buffer address in CE space */
910 u32 ce_data;
911 dma_addr_t ce_data_base = 0;
912 void *data_buf = NULL;
913 int i;
914
915 mutex_lock(&ar_pci->ce_diag_mutex);
916 ce_diag = ar_pci->ce_diag;
917
918 /*
919 * Allocate a temporary bounce buffer to hold caller's data
920 * to be DMA'ed from Target. This guarantees
921 * 1) 4-byte alignment
922 * 2) Buffer in DMA-able space
923 */
924 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
925
926 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, alloc_nbytes,
927 &ce_data_base,
928 GFP_ATOMIC);
929
930 if (!data_buf) {
931 ret = -ENOMEM;
932 goto done;
933 }
934
935 /* The address supplied by the caller is in the
936 * Target CPU virtual address space.
937 *
938 * In order to use this address with the diagnostic CE,
939 * convert it from Target CPU virtual address space
940 * to CE address space
941 */
942 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
943
944 remaining_bytes = nbytes;
945 ce_data = ce_data_base;
946 while (remaining_bytes) {
947 nbytes = min_t(unsigned int, remaining_bytes,
948 DIAG_TRANSFER_LIMIT);
949
950 ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data);
951 if (ret != 0)
952 goto done;
953
954 /* Request CE to send from Target(!) address to Host buffer */
955 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0);
956 if (ret)
957 goto done;
958
959 i = 0;
960 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) {
961 udelay(DIAG_ACCESS_CE_WAIT_US);
962 i += DIAG_ACCESS_CE_WAIT_US;
963
964 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
965 ret = -EBUSY;
966 goto done;
967 }
968 }
969
970 i = 0;
971 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf,
972 &completed_nbytes) != 0) {
973 udelay(DIAG_ACCESS_CE_WAIT_US);
974 i += DIAG_ACCESS_CE_WAIT_US;
975
976 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
977 ret = -EBUSY;
978 goto done;
979 }
980 }
981
982 if (nbytes != completed_nbytes) {
983 ret = -EIO;
984 goto done;
985 }
986
987 if (*buf != ce_data) {
988 ret = -EIO;
989 goto done;
990 }
991
992 remaining_bytes -= nbytes;
993 memcpy(data, data_buf, nbytes);
994
995 address += nbytes;
996 data += nbytes;
997 }
998
999 done:
1000
1001 if (data_buf)
1002 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1003 ce_data_base);
1004
1005 mutex_unlock(&ar_pci->ce_diag_mutex);
1006
1007 return ret;
1008 }
1009
1010 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
1011 {
1012 __le32 val = 0;
1013 int ret;
1014
1015 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
1016 *value = __le32_to_cpu(val);
1017
1018 return ret;
1019 }
1020
1021 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1022 u32 src, u32 len)
1023 {
1024 u32 host_addr, addr;
1025 int ret;
1026
1027 host_addr = host_interest_item_address(src);
1028
1029 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1030 if (ret != 0) {
1031 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1032 src, ret);
1033 return ret;
1034 }
1035
1036 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1037 if (ret != 0) {
1038 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1039 addr, len, ret);
1040 return ret;
1041 }
1042
1043 return 0;
1044 }
1045
1046 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1047 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1048
1049 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1050 const void *data, int nbytes)
1051 {
1052 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1053 int ret = 0;
1054 u32 *buf;
1055 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
1056 struct ath10k_ce_pipe *ce_diag;
1057 void *data_buf = NULL;
1058 dma_addr_t ce_data_base = 0;
1059 int i;
1060
1061 mutex_lock(&ar_pci->ce_diag_mutex);
1062 ce_diag = ar_pci->ce_diag;
1063
1064 /*
1065 * Allocate a temporary bounce buffer to hold caller's data
1066 * to be DMA'ed to Target. This guarantees
1067 * 1) 4-byte alignment
1068 * 2) Buffer in DMA-able space
1069 */
1070 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
1071
1072 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1073 alloc_nbytes,
1074 &ce_data_base,
1075 GFP_ATOMIC);
1076 if (!data_buf) {
1077 ret = -ENOMEM;
1078 goto done;
1079 }
1080
1081 /*
1082 * The address supplied by the caller is in the
1083 * Target CPU virtual address space.
1084 *
1085 * In order to use this address with the diagnostic CE,
1086 * convert it from
1087 * Target CPU virtual address space
1088 * to
1089 * CE address space
1090 */
1091 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1092
1093 remaining_bytes = nbytes;
1094 while (remaining_bytes) {
1095 /* FIXME: check cast */
1096 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1097
1098 /* Copy caller's data to allocated DMA buf */
1099 memcpy(data_buf, data, nbytes);
1100
1101 /* Set up to receive directly into Target(!) address */
1102 ret = ath10k_ce_rx_post_buf(ce_diag, &address, address);
1103 if (ret != 0)
1104 goto done;
1105
1106 /*
1107 * Request CE to send caller-supplied data that
1108 * was copied to bounce buffer to Target(!) address.
1109 */
1110 ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0);
1111 if (ret != 0)
1112 goto done;
1113
1114 i = 0;
1115 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) {
1116 udelay(DIAG_ACCESS_CE_WAIT_US);
1117 i += DIAG_ACCESS_CE_WAIT_US;
1118
1119 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1120 ret = -EBUSY;
1121 goto done;
1122 }
1123 }
1124
1125 i = 0;
1126 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf,
1127 &completed_nbytes) != 0) {
1128 udelay(DIAG_ACCESS_CE_WAIT_US);
1129 i += DIAG_ACCESS_CE_WAIT_US;
1130
1131 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1132 ret = -EBUSY;
1133 goto done;
1134 }
1135 }
1136
1137 if (nbytes != completed_nbytes) {
1138 ret = -EIO;
1139 goto done;
1140 }
1141
1142 if (*buf != address) {
1143 ret = -EIO;
1144 goto done;
1145 }
1146
1147 remaining_bytes -= nbytes;
1148 address += nbytes;
1149 data += nbytes;
1150 }
1151
1152 done:
1153 if (data_buf) {
1154 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1155 ce_data_base);
1156 }
1157
1158 if (ret != 0)
1159 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1160 address, ret);
1161
1162 mutex_unlock(&ar_pci->ce_diag_mutex);
1163
1164 return ret;
1165 }
1166
1167 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1168 {
1169 __le32 val = __cpu_to_le32(value);
1170
1171 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1172 }
1173
1174 /* Called by lower (CE) layer when a send to Target completes. */
1175 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1176 {
1177 struct ath10k *ar = ce_state->ar;
1178 struct sk_buff_head list;
1179 struct sk_buff *skb;
1180
1181 __skb_queue_head_init(&list);
1182 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1183 /* no need to call tx completion for NULL pointers */
1184 if (skb == NULL)
1185 continue;
1186
1187 __skb_queue_tail(&list, skb);
1188 }
1189
1190 while ((skb = __skb_dequeue(&list)))
1191 ath10k_htc_tx_completion_handler(ar, skb);
1192 }
1193
1194 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1195 void (*callback)(struct ath10k *ar,
1196 struct sk_buff *skb))
1197 {
1198 struct ath10k *ar = ce_state->ar;
1199 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1200 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1201 struct sk_buff *skb;
1202 struct sk_buff_head list;
1203 void *transfer_context;
1204 unsigned int nbytes, max_nbytes;
1205
1206 __skb_queue_head_init(&list);
1207 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1208 &nbytes) == 0) {
1209 skb = transfer_context;
1210 max_nbytes = skb->len + skb_tailroom(skb);
1211 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1212 max_nbytes, DMA_FROM_DEVICE);
1213
1214 if (unlikely(max_nbytes < nbytes)) {
1215 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1216 nbytes, max_nbytes);
1217 dev_kfree_skb_any(skb);
1218 continue;
1219 }
1220
1221 skb_put(skb, nbytes);
1222 __skb_queue_tail(&list, skb);
1223 }
1224
1225 while ((skb = __skb_dequeue(&list))) {
1226 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1227 ce_state->id, skb->len);
1228 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1229 skb->data, skb->len);
1230
1231 callback(ar, skb);
1232 }
1233
1234 ath10k_pci_rx_post_pipe(pipe_info);
1235 }
1236
1237 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
1238 void (*callback)(struct ath10k *ar,
1239 struct sk_buff *skb))
1240 {
1241 struct ath10k *ar = ce_state->ar;
1242 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1243 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1244 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
1245 struct sk_buff *skb;
1246 struct sk_buff_head list;
1247 void *transfer_context;
1248 unsigned int nbytes, max_nbytes, nentries;
1249 int orig_len;
1250
1251 /* No need to aquire ce_lock for CE5, since this is the only place CE5
1252 * is processed other than init and deinit. Before releasing CE5
1253 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1254 */
1255 __skb_queue_head_init(&list);
1256 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
1257 &nbytes) == 0) {
1258 skb = transfer_context;
1259 max_nbytes = skb->len + skb_tailroom(skb);
1260
1261 if (unlikely(max_nbytes < nbytes)) {
1262 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1263 nbytes, max_nbytes);
1264 continue;
1265 }
1266
1267 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1268 max_nbytes, DMA_FROM_DEVICE);
1269 skb_put(skb, nbytes);
1270 __skb_queue_tail(&list, skb);
1271 }
1272
1273 nentries = skb_queue_len(&list);
1274 while ((skb = __skb_dequeue(&list))) {
1275 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1276 ce_state->id, skb->len);
1277 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1278 skb->data, skb->len);
1279
1280 orig_len = skb->len;
1281 callback(ar, skb);
1282 skb_push(skb, orig_len - skb->len);
1283 skb_reset_tail_pointer(skb);
1284 skb_trim(skb, 0);
1285
1286 /*let device gain the buffer again*/
1287 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1288 skb->len + skb_tailroom(skb),
1289 DMA_FROM_DEVICE);
1290 }
1291 ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
1292 }
1293
1294 /* Called by lower (CE) layer when data is received from the Target. */
1295 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1296 {
1297 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1298 }
1299
1300 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1301 {
1302 /* CE4 polling needs to be done whenever CE pipe which transports
1303 * HTT Rx (target->host) is processed.
1304 */
1305 ath10k_ce_per_engine_service(ce_state->ar, 4);
1306
1307 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1308 }
1309
1310 /* Called by lower (CE) layer when data is received from the Target.
1311 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1312 */
1313 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1314 {
1315 ath10k_pci_process_rx_cb(ce_state,
1316 ath10k_htt_rx_pktlog_completion_handler);
1317 }
1318
1319 /* Called by lower (CE) layer when a send to HTT Target completes. */
1320 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1321 {
1322 struct ath10k *ar = ce_state->ar;
1323 struct sk_buff *skb;
1324
1325 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1326 /* no need to call tx completion for NULL pointers */
1327 if (!skb)
1328 continue;
1329
1330 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1331 skb->len, DMA_TO_DEVICE);
1332 ath10k_htt_hif_tx_complete(ar, skb);
1333 }
1334 }
1335
1336 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1337 {
1338 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1339 ath10k_htt_t2h_msg_handler(ar, skb);
1340 }
1341
1342 /* Called by lower (CE) layer when HTT data is received from the Target. */
1343 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1344 {
1345 /* CE4 polling needs to be done whenever CE pipe which transports
1346 * HTT Rx (target->host) is processed.
1347 */
1348 ath10k_ce_per_engine_service(ce_state->ar, 4);
1349
1350 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1351 }
1352
1353 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1354 struct ath10k_hif_sg_item *items, int n_items)
1355 {
1356 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1357 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1358 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1359 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1360 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1361 unsigned int nentries_mask;
1362 unsigned int sw_index;
1363 unsigned int write_index;
1364 int err, i = 0;
1365
1366 spin_lock_bh(&ce->ce_lock);
1367
1368 nentries_mask = src_ring->nentries_mask;
1369 sw_index = src_ring->sw_index;
1370 write_index = src_ring->write_index;
1371
1372 if (unlikely(CE_RING_DELTA(nentries_mask,
1373 write_index, sw_index - 1) < n_items)) {
1374 err = -ENOBUFS;
1375 goto err;
1376 }
1377
1378 for (i = 0; i < n_items - 1; i++) {
1379 ath10k_dbg(ar, ATH10K_DBG_PCI,
1380 "pci tx item %d paddr %pad len %d n_items %d\n",
1381 i, &items[i].paddr, items[i].len, n_items);
1382 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1383 items[i].vaddr, items[i].len);
1384
1385 err = ath10k_ce_send_nolock(ce_pipe,
1386 items[i].transfer_context,
1387 items[i].paddr,
1388 items[i].len,
1389 items[i].transfer_id,
1390 CE_SEND_FLAG_GATHER);
1391 if (err)
1392 goto err;
1393 }
1394
1395 /* `i` is equal to `n_items -1` after for() */
1396
1397 ath10k_dbg(ar, ATH10K_DBG_PCI,
1398 "pci tx item %d paddr %pad len %d n_items %d\n",
1399 i, &items[i].paddr, items[i].len, n_items);
1400 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1401 items[i].vaddr, items[i].len);
1402
1403 err = ath10k_ce_send_nolock(ce_pipe,
1404 items[i].transfer_context,
1405 items[i].paddr,
1406 items[i].len,
1407 items[i].transfer_id,
1408 0);
1409 if (err)
1410 goto err;
1411
1412 spin_unlock_bh(&ce->ce_lock);
1413 return 0;
1414
1415 err:
1416 for (; i > 0; i--)
1417 __ath10k_ce_send_revert(ce_pipe);
1418
1419 spin_unlock_bh(&ce->ce_lock);
1420 return err;
1421 }
1422
1423 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1424 size_t buf_len)
1425 {
1426 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1427 }
1428
1429 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1430 {
1431 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1432
1433 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1434
1435 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1436 }
1437
1438 static void ath10k_pci_dump_registers(struct ath10k *ar,
1439 struct ath10k_fw_crash_data *crash_data)
1440 {
1441 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1442 int i, ret;
1443
1444 lockdep_assert_held(&ar->dump_mutex);
1445
1446 ret = ath10k_pci_diag_read_hi(ar, &reg_dump_values[0],
1447 hi_failure_state,
1448 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1449 if (ret) {
1450 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1451 return;
1452 }
1453
1454 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1455
1456 ath10k_err(ar, "firmware register dump:\n");
1457 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1458 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1459 i,
1460 __le32_to_cpu(reg_dump_values[i]),
1461 __le32_to_cpu(reg_dump_values[i + 1]),
1462 __le32_to_cpu(reg_dump_values[i + 2]),
1463 __le32_to_cpu(reg_dump_values[i + 3]));
1464
1465 if (!crash_data)
1466 return;
1467
1468 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1469 crash_data->registers[i] = reg_dump_values[i];
1470 }
1471
1472 static int ath10k_pci_dump_memory_section(struct ath10k *ar,
1473 const struct ath10k_mem_region *mem_region,
1474 u8 *buf, size_t buf_len)
1475 {
1476 const struct ath10k_mem_section *cur_section, *next_section;
1477 unsigned int count, section_size, skip_size;
1478 int ret, i, j;
1479
1480 if (!mem_region || !buf)
1481 return 0;
1482
1483 cur_section = &mem_region->section_table.sections[0];
1484
1485 if (mem_region->start > cur_section->start) {
1486 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n",
1487 mem_region->start, cur_section->start);
1488 return 0;
1489 }
1490
1491 skip_size = cur_section->start - mem_region->start;
1492
1493 /* fill the gap between the first register section and register
1494 * start address
1495 */
1496 for (i = 0; i < skip_size; i++) {
1497 *buf = ATH10K_MAGIC_NOT_COPIED;
1498 buf++;
1499 }
1500
1501 count = 0;
1502
1503 for (i = 0; cur_section != NULL; i++) {
1504 section_size = cur_section->end - cur_section->start;
1505
1506 if (section_size <= 0) {
1507 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n",
1508 cur_section->start,
1509 cur_section->end);
1510 break;
1511 }
1512
1513 if ((i + 1) == mem_region->section_table.size) {
1514 /* last section */
1515 next_section = NULL;
1516 skip_size = 0;
1517 } else {
1518 next_section = cur_section + 1;
1519
1520 if (cur_section->end > next_section->start) {
1521 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n",
1522 next_section->start,
1523 cur_section->end);
1524 break;
1525 }
1526
1527 skip_size = next_section->start - cur_section->end;
1528 }
1529
1530 if (buf_len < (skip_size + section_size)) {
1531 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len);
1532 break;
1533 }
1534
1535 buf_len -= skip_size + section_size;
1536
1537 /* read section to dest memory */
1538 ret = ath10k_pci_diag_read_mem(ar, cur_section->start,
1539 buf, section_size);
1540 if (ret) {
1541 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n",
1542 cur_section->start, ret);
1543 break;
1544 }
1545
1546 buf += section_size;
1547 count += section_size;
1548
1549 /* fill in the gap between this section and the next */
1550 for (j = 0; j < skip_size; j++) {
1551 *buf = ATH10K_MAGIC_NOT_COPIED;
1552 buf++;
1553 }
1554
1555 count += skip_size;
1556
1557 if (!next_section)
1558 /* this was the last section */
1559 break;
1560
1561 cur_section = next_section;
1562 }
1563
1564 return count;
1565 }
1566
1567 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config)
1568 {
1569 u32 val;
1570
1571 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1572 FW_RAM_CONFIG_ADDRESS, config);
1573
1574 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1575 FW_RAM_CONFIG_ADDRESS);
1576 if (val != config) {
1577 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n",
1578 val, config);
1579 return -EIO;
1580 }
1581
1582 return 0;
1583 }
1584
1585 /* if an error happened returns < 0, otherwise the length */
1586 static int ath10k_pci_dump_memory_sram(struct ath10k *ar,
1587 const struct ath10k_mem_region *region,
1588 u8 *buf)
1589 {
1590 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1591 u32 base_addr, i;
1592
1593 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG);
1594 base_addr += region->start;
1595
1596 for (i = 0; i < region->len; i += 4) {
1597 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG);
1598 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG);
1599 }
1600
1601 return region->len;
1602 }
1603
1604 /* if an error happened returns < 0, otherwise the length */
1605 static int ath10k_pci_dump_memory_reg(struct ath10k *ar,
1606 const struct ath10k_mem_region *region,
1607 u8 *buf)
1608 {
1609 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1610 u32 i;
1611
1612 for (i = 0; i < region->len; i += 4)
1613 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i);
1614
1615 return region->len;
1616 }
1617
1618 /* if an error happened returns < 0, otherwise the length */
1619 static int ath10k_pci_dump_memory_generic(struct ath10k *ar,
1620 const struct ath10k_mem_region *current_region,
1621 u8 *buf)
1622 {
1623 int ret;
1624
1625 if (current_region->section_table.size > 0)
1626 /* Copy each section individually. */
1627 return ath10k_pci_dump_memory_section(ar,
1628 current_region,
1629 buf,
1630 current_region->len);
1631
1632 /* No individiual memory sections defined so we can
1633 * copy the entire memory region.
1634 */
1635 ret = ath10k_pci_diag_read_mem(ar,
1636 current_region->start,
1637 buf,
1638 current_region->len);
1639 if (ret) {
1640 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n",
1641 current_region->name, ret);
1642 return ret;
1643 }
1644
1645 return current_region->len;
1646 }
1647
1648 static void ath10k_pci_dump_memory(struct ath10k *ar,
1649 struct ath10k_fw_crash_data *crash_data)
1650 {
1651 const struct ath10k_hw_mem_layout *mem_layout;
1652 const struct ath10k_mem_region *current_region;
1653 struct ath10k_dump_ram_data_hdr *hdr;
1654 u32 count, shift;
1655 size_t buf_len;
1656 int ret, i;
1657 u8 *buf;
1658
1659 lockdep_assert_held(&ar->dump_mutex);
1660
1661 if (!crash_data)
1662 return;
1663
1664 mem_layout = ath10k_coredump_get_mem_layout(ar);
1665 if (!mem_layout)
1666 return;
1667
1668 current_region = &mem_layout->region_table.regions[0];
1669
1670 buf = crash_data->ramdump_buf;
1671 buf_len = crash_data->ramdump_buf_len;
1672
1673 memset(buf, 0, buf_len);
1674
1675 for (i = 0; i < mem_layout->region_table.size; i++) {
1676 count = 0;
1677
1678 if (current_region->len > buf_len) {
1679 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n",
1680 current_region->name,
1681 current_region->len,
1682 buf_len);
1683 break;
1684 }
1685
1686 /* To get IRAM dump, the host driver needs to switch target
1687 * ram config from DRAM to IRAM.
1688 */
1689 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 ||
1690 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) {
1691 shift = current_region->start >> 20;
1692
1693 ret = ath10k_pci_set_ram_config(ar, shift);
1694 if (ret) {
1695 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n",
1696 current_region->name, ret);
1697 break;
1698 }
1699 }
1700
1701 /* Reserve space for the header. */
1702 hdr = (void *)buf;
1703 buf += sizeof(*hdr);
1704 buf_len -= sizeof(*hdr);
1705
1706 switch (current_region->type) {
1707 case ATH10K_MEM_REGION_TYPE_IOSRAM:
1708 count = ath10k_pci_dump_memory_sram(ar, current_region, buf);
1709 break;
1710 case ATH10K_MEM_REGION_TYPE_IOREG:
1711 count = ath10k_pci_dump_memory_reg(ar, current_region, buf);
1712 break;
1713 default:
1714 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf);
1715 if (ret < 0)
1716 break;
1717
1718 count = ret;
1719 break;
1720 }
1721
1722 hdr->region_type = cpu_to_le32(current_region->type);
1723 hdr->start = cpu_to_le32(current_region->start);
1724 hdr->length = cpu_to_le32(count);
1725
1726 if (count == 0)
1727 /* Note: the header remains, just with zero length. */
1728 break;
1729
1730 buf += count;
1731 buf_len -= count;
1732
1733 current_region++;
1734 }
1735 }
1736
1737 static void ath10k_pci_fw_dump_work(struct work_struct *work)
1738 {
1739 struct ath10k_pci *ar_pci = container_of(work, struct ath10k_pci,
1740 dump_work);
1741 struct ath10k_fw_crash_data *crash_data;
1742 struct ath10k *ar = ar_pci->ar;
1743 char guid[UUID_STRING_LEN + 1];
1744
1745 mutex_lock(&ar->dump_mutex);
1746
1747 spin_lock_bh(&ar->data_lock);
1748 ar->stats.fw_crash_counter++;
1749 spin_unlock_bh(&ar->data_lock);
1750
1751 crash_data = ath10k_coredump_new(ar);
1752
1753 if (crash_data)
1754 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1755 else
1756 scnprintf(guid, sizeof(guid), "n/a");
1757
1758 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1759 ath10k_print_driver_info(ar);
1760 ath10k_pci_dump_registers(ar, crash_data);
1761 ath10k_ce_dump_registers(ar, crash_data);
1762 ath10k_pci_dump_memory(ar, crash_data);
1763
1764 mutex_unlock(&ar->dump_mutex);
1765
1766 queue_work(ar->workqueue, &ar->restart_work);
1767 }
1768
1769 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1770 {
1771 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1772
1773 queue_work(ar->workqueue, &ar_pci->dump_work);
1774 }
1775
1776 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1777 int force)
1778 {
1779 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1780
1781 if (!force) {
1782 int resources;
1783 /*
1784 * Decide whether to actually poll for completions, or just
1785 * wait for a later chance.
1786 * If there seem to be plenty of resources left, then just wait
1787 * since checking involves reading a CE register, which is a
1788 * relatively expensive operation.
1789 */
1790 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1791
1792 /*
1793 * If at least 50% of the total resources are still available,
1794 * don't bother checking again yet.
1795 */
1796 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1797 return;
1798 }
1799 ath10k_ce_per_engine_service(ar, pipe);
1800 }
1801
1802 static void ath10k_pci_rx_retry_sync(struct ath10k *ar)
1803 {
1804 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1805
1806 del_timer_sync(&ar_pci->rx_post_retry);
1807 }
1808
1809 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1810 u8 *ul_pipe, u8 *dl_pipe)
1811 {
1812 const struct service_to_pipe *entry;
1813 bool ul_set = false, dl_set = false;
1814 int i;
1815
1816 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1817
1818 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1819 entry = &target_service_to_ce_map_wlan[i];
1820
1821 if (__le32_to_cpu(entry->service_id) != service_id)
1822 continue;
1823
1824 switch (__le32_to_cpu(entry->pipedir)) {
1825 case PIPEDIR_NONE:
1826 break;
1827 case PIPEDIR_IN:
1828 WARN_ON(dl_set);
1829 *dl_pipe = __le32_to_cpu(entry->pipenum);
1830 dl_set = true;
1831 break;
1832 case PIPEDIR_OUT:
1833 WARN_ON(ul_set);
1834 *ul_pipe = __le32_to_cpu(entry->pipenum);
1835 ul_set = true;
1836 break;
1837 case PIPEDIR_INOUT:
1838 WARN_ON(dl_set);
1839 WARN_ON(ul_set);
1840 *dl_pipe = __le32_to_cpu(entry->pipenum);
1841 *ul_pipe = __le32_to_cpu(entry->pipenum);
1842 dl_set = true;
1843 ul_set = true;
1844 break;
1845 }
1846 }
1847
1848 if (!ul_set || !dl_set)
1849 return -ENOENT;
1850
1851 return 0;
1852 }
1853
1854 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1855 u8 *ul_pipe, u8 *dl_pipe)
1856 {
1857 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1858
1859 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1860 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1861 ul_pipe, dl_pipe);
1862 }
1863
1864 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1865 {
1866 u32 val;
1867
1868 switch (ar->hw_rev) {
1869 case ATH10K_HW_QCA988X:
1870 case ATH10K_HW_QCA9887:
1871 case ATH10K_HW_QCA6174:
1872 case ATH10K_HW_QCA9377:
1873 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1874 CORE_CTRL_ADDRESS);
1875 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1876 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1877 CORE_CTRL_ADDRESS, val);
1878 break;
1879 case ATH10K_HW_QCA99X0:
1880 case ATH10K_HW_QCA9984:
1881 case ATH10K_HW_QCA9888:
1882 case ATH10K_HW_QCA4019:
1883 /* TODO: Find appropriate register configuration for QCA99X0
1884 * to mask irq/MSI.
1885 */
1886 break;
1887 case ATH10K_HW_WCN3990:
1888 break;
1889 }
1890 }
1891
1892 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1893 {
1894 u32 val;
1895
1896 switch (ar->hw_rev) {
1897 case ATH10K_HW_QCA988X:
1898 case ATH10K_HW_QCA9887:
1899 case ATH10K_HW_QCA6174:
1900 case ATH10K_HW_QCA9377:
1901 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1902 CORE_CTRL_ADDRESS);
1903 val |= CORE_CTRL_PCIE_REG_31_MASK;
1904 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1905 CORE_CTRL_ADDRESS, val);
1906 break;
1907 case ATH10K_HW_QCA99X0:
1908 case ATH10K_HW_QCA9984:
1909 case ATH10K_HW_QCA9888:
1910 case ATH10K_HW_QCA4019:
1911 /* TODO: Find appropriate register configuration for QCA99X0
1912 * to unmask irq/MSI.
1913 */
1914 break;
1915 case ATH10K_HW_WCN3990:
1916 break;
1917 }
1918 }
1919
1920 static void ath10k_pci_irq_disable(struct ath10k *ar)
1921 {
1922 ath10k_ce_disable_interrupts(ar);
1923 ath10k_pci_disable_and_clear_legacy_irq(ar);
1924 ath10k_pci_irq_msi_fw_mask(ar);
1925 }
1926
1927 static void ath10k_pci_irq_sync(struct ath10k *ar)
1928 {
1929 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1930
1931 synchronize_irq(ar_pci->pdev->irq);
1932 }
1933
1934 static void ath10k_pci_irq_enable(struct ath10k *ar)
1935 {
1936 ath10k_ce_enable_interrupts(ar);
1937 ath10k_pci_enable_legacy_irq(ar);
1938 ath10k_pci_irq_msi_fw_unmask(ar);
1939 }
1940
1941 static int ath10k_pci_hif_start(struct ath10k *ar)
1942 {
1943 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1944
1945 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1946
1947 napi_enable(&ar->napi);
1948
1949 ath10k_pci_irq_enable(ar);
1950 ath10k_pci_rx_post(ar);
1951
1952 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1953 ar_pci->link_ctl);
1954
1955 return 0;
1956 }
1957
1958 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1959 {
1960 struct ath10k *ar;
1961 struct ath10k_ce_pipe *ce_pipe;
1962 struct ath10k_ce_ring *ce_ring;
1963 struct sk_buff *skb;
1964 int i;
1965
1966 ar = pci_pipe->hif_ce_state;
1967 ce_pipe = pci_pipe->ce_hdl;
1968 ce_ring = ce_pipe->dest_ring;
1969
1970 if (!ce_ring)
1971 return;
1972
1973 if (!pci_pipe->buf_sz)
1974 return;
1975
1976 for (i = 0; i < ce_ring->nentries; i++) {
1977 skb = ce_ring->per_transfer_context[i];
1978 if (!skb)
1979 continue;
1980
1981 ce_ring->per_transfer_context[i] = NULL;
1982
1983 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1984 skb->len + skb_tailroom(skb),
1985 DMA_FROM_DEVICE);
1986 dev_kfree_skb_any(skb);
1987 }
1988 }
1989
1990 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1991 {
1992 struct ath10k *ar;
1993 struct ath10k_ce_pipe *ce_pipe;
1994 struct ath10k_ce_ring *ce_ring;
1995 struct sk_buff *skb;
1996 int i;
1997
1998 ar = pci_pipe->hif_ce_state;
1999 ce_pipe = pci_pipe->ce_hdl;
2000 ce_ring = ce_pipe->src_ring;
2001
2002 if (!ce_ring)
2003 return;
2004
2005 if (!pci_pipe->buf_sz)
2006 return;
2007
2008 for (i = 0; i < ce_ring->nentries; i++) {
2009 skb = ce_ring->per_transfer_context[i];
2010 if (!skb)
2011 continue;
2012
2013 ce_ring->per_transfer_context[i] = NULL;
2014
2015 ath10k_htc_tx_completion_handler(ar, skb);
2016 }
2017 }
2018
2019 /*
2020 * Cleanup residual buffers for device shutdown:
2021 * buffers that were enqueued for receive
2022 * buffers that were to be sent
2023 * Note: Buffers that had completed but which were
2024 * not yet processed are on a completion queue. They
2025 * are handled when the completion thread shuts down.
2026 */
2027 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
2028 {
2029 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2030 int pipe_num;
2031
2032 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
2033 struct ath10k_pci_pipe *pipe_info;
2034
2035 pipe_info = &ar_pci->pipe_info[pipe_num];
2036 ath10k_pci_rx_pipe_cleanup(pipe_info);
2037 ath10k_pci_tx_pipe_cleanup(pipe_info);
2038 }
2039 }
2040
2041 void ath10k_pci_ce_deinit(struct ath10k *ar)
2042 {
2043 int i;
2044
2045 for (i = 0; i < CE_COUNT; i++)
2046 ath10k_ce_deinit_pipe(ar, i);
2047 }
2048
2049 void ath10k_pci_flush(struct ath10k *ar)
2050 {
2051 ath10k_pci_rx_retry_sync(ar);
2052 ath10k_pci_buffer_cleanup(ar);
2053 }
2054
2055 static void ath10k_pci_hif_stop(struct ath10k *ar)
2056 {
2057 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2058 unsigned long flags;
2059
2060 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
2061
2062 /* Most likely the device has HTT Rx ring configured. The only way to
2063 * prevent the device from accessing (and possible corrupting) host
2064 * memory is to reset the chip now.
2065 *
2066 * There's also no known way of masking MSI interrupts on the device.
2067 * For ranged MSI the CE-related interrupts can be masked. However
2068 * regardless how many MSI interrupts are assigned the first one
2069 * is always used for firmware indications (crashes) and cannot be
2070 * masked. To prevent the device from asserting the interrupt reset it
2071 * before proceeding with cleanup.
2072 */
2073 ath10k_pci_safe_chip_reset(ar);
2074
2075 ath10k_pci_irq_disable(ar);
2076 ath10k_pci_irq_sync(ar);
2077 napi_synchronize(&ar->napi);
2078 napi_disable(&ar->napi);
2079 ath10k_pci_flush(ar);
2080
2081 spin_lock_irqsave(&ar_pci->ps_lock, flags);
2082 WARN_ON(ar_pci->ps_wake_refcount > 0);
2083 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
2084 }
2085
2086 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
2087 void *req, u32 req_len,
2088 void *resp, u32 *resp_len)
2089 {
2090 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2091 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
2092 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
2093 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
2094 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
2095 dma_addr_t req_paddr = 0;
2096 dma_addr_t resp_paddr = 0;
2097 struct bmi_xfer xfer = {};
2098 void *treq, *tresp = NULL;
2099 int ret = 0;
2100
2101 might_sleep();
2102
2103 if (resp && !resp_len)
2104 return -EINVAL;
2105
2106 if (resp && resp_len && *resp_len == 0)
2107 return -EINVAL;
2108
2109 treq = kmemdup(req, req_len, GFP_KERNEL);
2110 if (!treq)
2111 return -ENOMEM;
2112
2113 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
2114 ret = dma_mapping_error(ar->dev, req_paddr);
2115 if (ret) {
2116 ret = -EIO;
2117 goto err_dma;
2118 }
2119
2120 if (resp && resp_len) {
2121 tresp = kzalloc(*resp_len, GFP_KERNEL);
2122 if (!tresp) {
2123 ret = -ENOMEM;
2124 goto err_req;
2125 }
2126
2127 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
2128 DMA_FROM_DEVICE);
2129 ret = dma_mapping_error(ar->dev, resp_paddr);
2130 if (ret) {
2131 ret = -EIO;
2132 goto err_req;
2133 }
2134
2135 xfer.wait_for_resp = true;
2136 xfer.resp_len = 0;
2137
2138 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
2139 }
2140
2141 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
2142 if (ret)
2143 goto err_resp;
2144
2145 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer);
2146 if (ret) {
2147 dma_addr_t unused_buffer;
2148 unsigned int unused_nbytes;
2149 unsigned int unused_id;
2150
2151 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
2152 &unused_nbytes, &unused_id);
2153 } else {
2154 /* non-zero means we did not time out */
2155 ret = 0;
2156 }
2157
2158 err_resp:
2159 if (resp) {
2160 dma_addr_t unused_buffer;
2161
2162 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
2163 dma_unmap_single(ar->dev, resp_paddr,
2164 *resp_len, DMA_FROM_DEVICE);
2165 }
2166 err_req:
2167 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
2168
2169 if (ret == 0 && resp_len) {
2170 *resp_len = min(*resp_len, xfer.resp_len);
2171 memcpy(resp, tresp, xfer.resp_len);
2172 }
2173 err_dma:
2174 kfree(treq);
2175 kfree(tresp);
2176
2177 return ret;
2178 }
2179
2180 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
2181 {
2182 struct bmi_xfer *xfer;
2183
2184 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
2185 return;
2186
2187 xfer->tx_done = true;
2188 }
2189
2190 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
2191 {
2192 struct ath10k *ar = ce_state->ar;
2193 struct bmi_xfer *xfer;
2194 unsigned int nbytes;
2195
2196 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
2197 &nbytes))
2198 return;
2199
2200 if (WARN_ON_ONCE(!xfer))
2201 return;
2202
2203 if (!xfer->wait_for_resp) {
2204 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
2205 return;
2206 }
2207
2208 xfer->resp_len = nbytes;
2209 xfer->rx_done = true;
2210 }
2211
2212 static int ath10k_pci_bmi_wait(struct ath10k *ar,
2213 struct ath10k_ce_pipe *tx_pipe,
2214 struct ath10k_ce_pipe *rx_pipe,
2215 struct bmi_xfer *xfer)
2216 {
2217 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
2218 unsigned long started = jiffies;
2219 unsigned long dur;
2220 int ret;
2221
2222 while (time_before_eq(jiffies, timeout)) {
2223 ath10k_pci_bmi_send_done(tx_pipe);
2224 ath10k_pci_bmi_recv_data(rx_pipe);
2225
2226 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) {
2227 ret = 0;
2228 goto out;
2229 }
2230
2231 schedule();
2232 }
2233
2234 ret = -ETIMEDOUT;
2235
2236 out:
2237 dur = jiffies - started;
2238 if (dur > HZ)
2239 ath10k_dbg(ar, ATH10K_DBG_BMI,
2240 "bmi cmd took %lu jiffies hz %d ret %d\n",
2241 dur, HZ, ret);
2242 return ret;
2243 }
2244
2245 /*
2246 * Send an interrupt to the device to wake up the Target CPU
2247 * so it has an opportunity to notice any changed state.
2248 */
2249 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
2250 {
2251 u32 addr, val;
2252
2253 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
2254 val = ath10k_pci_read32(ar, addr);
2255 val |= CORE_CTRL_CPU_INTR_MASK;
2256 ath10k_pci_write32(ar, addr, val);
2257
2258 return 0;
2259 }
2260
2261 static int ath10k_pci_get_num_banks(struct ath10k *ar)
2262 {
2263 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2264
2265 switch (ar_pci->pdev->device) {
2266 case QCA988X_2_0_DEVICE_ID_UBNT:
2267 case QCA988X_2_0_DEVICE_ID:
2268 case QCA99X0_2_0_DEVICE_ID:
2269 case QCA9888_2_0_DEVICE_ID:
2270 case QCA9984_1_0_DEVICE_ID:
2271 case QCA9887_1_0_DEVICE_ID:
2272 return 1;
2273 case QCA6164_2_1_DEVICE_ID:
2274 case QCA6174_2_1_DEVICE_ID:
2275 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) {
2276 case QCA6174_HW_1_0_CHIP_ID_REV:
2277 case QCA6174_HW_1_1_CHIP_ID_REV:
2278 case QCA6174_HW_2_1_CHIP_ID_REV:
2279 case QCA6174_HW_2_2_CHIP_ID_REV:
2280 return 3;
2281 case QCA6174_HW_1_3_CHIP_ID_REV:
2282 return 2;
2283 case QCA6174_HW_3_0_CHIP_ID_REV:
2284 case QCA6174_HW_3_1_CHIP_ID_REV:
2285 case QCA6174_HW_3_2_CHIP_ID_REV:
2286 return 9;
2287 }
2288 break;
2289 case QCA9377_1_0_DEVICE_ID:
2290 return 9;
2291 }
2292
2293 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
2294 return 1;
2295 }
2296
2297 static int ath10k_bus_get_num_banks(struct ath10k *ar)
2298 {
2299 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2300
2301 return ce->bus_ops->get_num_banks(ar);
2302 }
2303
2304 int ath10k_pci_init_config(struct ath10k *ar)
2305 {
2306 u32 interconnect_targ_addr;
2307 u32 pcie_state_targ_addr = 0;
2308 u32 pipe_cfg_targ_addr = 0;
2309 u32 svc_to_pipe_map = 0;
2310 u32 pcie_config_flags = 0;
2311 u32 ealloc_value;
2312 u32 ealloc_targ_addr;
2313 u32 flag2_value;
2314 u32 flag2_targ_addr;
2315 int ret = 0;
2316
2317 /* Download to Target the CE Config and the service-to-CE map */
2318 interconnect_targ_addr =
2319 host_interest_item_address(HI_ITEM(hi_interconnect_state));
2320
2321 /* Supply Target-side CE configuration */
2322 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
2323 &pcie_state_targ_addr);
2324 if (ret != 0) {
2325 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2326 return ret;
2327 }
2328
2329 if (pcie_state_targ_addr == 0) {
2330 ret = -EIO;
2331 ath10k_err(ar, "Invalid pcie state addr\n");
2332 return ret;
2333 }
2334
2335 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2336 offsetof(struct pcie_state,
2337 pipe_cfg_addr)),
2338 &pipe_cfg_targ_addr);
2339 if (ret != 0) {
2340 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2341 return ret;
2342 }
2343
2344 if (pipe_cfg_targ_addr == 0) {
2345 ret = -EIO;
2346 ath10k_err(ar, "Invalid pipe cfg addr\n");
2347 return ret;
2348 }
2349
2350 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2351 target_ce_config_wlan,
2352 sizeof(struct ce_pipe_config) *
2353 NUM_TARGET_CE_CONFIG_WLAN);
2354
2355 if (ret != 0) {
2356 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2357 return ret;
2358 }
2359
2360 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2361 offsetof(struct pcie_state,
2362 svc_to_pipe_map)),
2363 &svc_to_pipe_map);
2364 if (ret != 0) {
2365 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2366 return ret;
2367 }
2368
2369 if (svc_to_pipe_map == 0) {
2370 ret = -EIO;
2371 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2372 return ret;
2373 }
2374
2375 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2376 target_service_to_ce_map_wlan,
2377 sizeof(target_service_to_ce_map_wlan));
2378 if (ret != 0) {
2379 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2380 return ret;
2381 }
2382
2383 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2384 offsetof(struct pcie_state,
2385 config_flags)),
2386 &pcie_config_flags);
2387 if (ret != 0) {
2388 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2389 return ret;
2390 }
2391
2392 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2393
2394 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2395 offsetof(struct pcie_state,
2396 config_flags)),
2397 pcie_config_flags);
2398 if (ret != 0) {
2399 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2400 return ret;
2401 }
2402
2403 /* configure early allocation */
2404 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2405
2406 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2407 if (ret != 0) {
2408 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2409 return ret;
2410 }
2411
2412 /* first bank is switched to IRAM */
2413 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2414 HI_EARLY_ALLOC_MAGIC_MASK);
2415 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2416 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2417 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2418
2419 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2420 if (ret != 0) {
2421 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2422 return ret;
2423 }
2424
2425 /* Tell Target to proceed with initialization */
2426 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2427
2428 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2429 if (ret != 0) {
2430 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2431 return ret;
2432 }
2433
2434 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2435
2436 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2437 if (ret != 0) {
2438 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2439 return ret;
2440 }
2441
2442 return 0;
2443 }
2444
2445 static void ath10k_pci_override_ce_config(struct ath10k *ar)
2446 {
2447 struct ce_attr *attr;
2448 struct ce_pipe_config *config;
2449
2450 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2451 * since it is currently used for other feature.
2452 */
2453
2454 /* Override Host's Copy Engine 5 configuration */
2455 attr = &host_ce_config_wlan[5];
2456 attr->src_sz_max = 0;
2457 attr->dest_nentries = 0;
2458
2459 /* Override Target firmware's Copy Engine configuration */
2460 config = &target_ce_config_wlan[5];
2461 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2462 config->nbytes_max = __cpu_to_le32(2048);
2463
2464 /* Map from service/endpoint to Copy Engine */
2465 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2466 }
2467
2468 int ath10k_pci_alloc_pipes(struct ath10k *ar)
2469 {
2470 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2471 struct ath10k_pci_pipe *pipe;
2472 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2473 int i, ret;
2474
2475 for (i = 0; i < CE_COUNT; i++) {
2476 pipe = &ar_pci->pipe_info[i];
2477 pipe->ce_hdl = &ce->ce_states[i];
2478 pipe->pipe_num = i;
2479 pipe->hif_ce_state = ar;
2480
2481 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2482 if (ret) {
2483 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2484 i, ret);
2485 return ret;
2486 }
2487
2488 /* Last CE is Diagnostic Window */
2489 if (i == CE_DIAG_PIPE) {
2490 ar_pci->ce_diag = pipe->ce_hdl;
2491 continue;
2492 }
2493
2494 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2495 }
2496
2497 return 0;
2498 }
2499
2500 void ath10k_pci_free_pipes(struct ath10k *ar)
2501 {
2502 int i;
2503
2504 for (i = 0; i < CE_COUNT; i++)
2505 ath10k_ce_free_pipe(ar, i);
2506 }
2507
2508 int ath10k_pci_init_pipes(struct ath10k *ar)
2509 {
2510 int i, ret;
2511
2512 for (i = 0; i < CE_COUNT; i++) {
2513 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2514 if (ret) {
2515 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2516 i, ret);
2517 return ret;
2518 }
2519 }
2520
2521 return 0;
2522 }
2523
2524 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2525 {
2526 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2527 FW_IND_EVENT_PENDING;
2528 }
2529
2530 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2531 {
2532 u32 val;
2533
2534 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2535 val &= ~FW_IND_EVENT_PENDING;
2536 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2537 }
2538
2539 static bool ath10k_pci_has_device_gone(struct ath10k *ar)
2540 {
2541 u32 val;
2542
2543 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2544 return (val == 0xffffffff);
2545 }
2546
2547 /* this function effectively clears target memory controller assert line */
2548 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2549 {
2550 u32 val;
2551
2552 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2553 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2554 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2555 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2556
2557 msleep(10);
2558
2559 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2560 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2561 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2562 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2563
2564 msleep(10);
2565 }
2566
2567 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2568 {
2569 u32 val;
2570
2571 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2572
2573 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2574 SOC_RESET_CONTROL_ADDRESS);
2575 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2576 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2577 }
2578
2579 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2580 {
2581 u32 val;
2582
2583 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2584 SOC_RESET_CONTROL_ADDRESS);
2585
2586 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2587 val | SOC_RESET_CONTROL_CE_RST_MASK);
2588 msleep(10);
2589 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2590 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2591 }
2592
2593 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2594 {
2595 u32 val;
2596
2597 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2598 SOC_LF_TIMER_CONTROL0_ADDRESS);
2599 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2600 SOC_LF_TIMER_CONTROL0_ADDRESS,
2601 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2602 }
2603
2604 static int ath10k_pci_warm_reset(struct ath10k *ar)
2605 {
2606 int ret;
2607
2608 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2609
2610 spin_lock_bh(&ar->data_lock);
2611 ar->stats.fw_warm_reset_counter++;
2612 spin_unlock_bh(&ar->data_lock);
2613
2614 ath10k_pci_irq_disable(ar);
2615
2616 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2617 * were to access copy engine while host performs copy engine reset
2618 * then it is possible for the device to confuse pci-e controller to
2619 * the point of bringing host system to a complete stop (i.e. hang).
2620 */
2621 ath10k_pci_warm_reset_si0(ar);
2622 ath10k_pci_warm_reset_cpu(ar);
2623 ath10k_pci_init_pipes(ar);
2624 ath10k_pci_wait_for_target_init(ar);
2625
2626 ath10k_pci_warm_reset_clear_lf(ar);
2627 ath10k_pci_warm_reset_ce(ar);
2628 ath10k_pci_warm_reset_cpu(ar);
2629 ath10k_pci_init_pipes(ar);
2630
2631 ret = ath10k_pci_wait_for_target_init(ar);
2632 if (ret) {
2633 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2634 return ret;
2635 }
2636
2637 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2638
2639 return 0;
2640 }
2641
2642 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
2643 {
2644 ath10k_pci_irq_disable(ar);
2645 return ath10k_pci_qca99x0_chip_reset(ar);
2646 }
2647
2648 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2649 {
2650 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2651
2652 if (!ar_pci->pci_soft_reset)
2653 return -ENOTSUPP;
2654
2655 return ar_pci->pci_soft_reset(ar);
2656 }
2657
2658 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2659 {
2660 int i, ret;
2661 u32 val;
2662
2663 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2664
2665 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2666 * It is thus preferred to use warm reset which is safer but may not be
2667 * able to recover the device from all possible fail scenarios.
2668 *
2669 * Warm reset doesn't always work on first try so attempt it a few
2670 * times before giving up.
2671 */
2672 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2673 ret = ath10k_pci_warm_reset(ar);
2674 if (ret) {
2675 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2676 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2677 ret);
2678 continue;
2679 }
2680
2681 /* FIXME: Sometimes copy engine doesn't recover after warm
2682 * reset. In most cases this needs cold reset. In some of these
2683 * cases the device is in such a state that a cold reset may
2684 * lock up the host.
2685 *
2686 * Reading any host interest register via copy engine is
2687 * sufficient to verify if device is capable of booting
2688 * firmware blob.
2689 */
2690 ret = ath10k_pci_init_pipes(ar);
2691 if (ret) {
2692 ath10k_warn(ar, "failed to init copy engine: %d\n",
2693 ret);
2694 continue;
2695 }
2696
2697 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2698 &val);
2699 if (ret) {
2700 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2701 ret);
2702 continue;
2703 }
2704
2705 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2706 return 0;
2707 }
2708
2709 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2710 ath10k_warn(ar, "refusing cold reset as requested\n");
2711 return -EPERM;
2712 }
2713
2714 ret = ath10k_pci_cold_reset(ar);
2715 if (ret) {
2716 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2717 return ret;
2718 }
2719
2720 ret = ath10k_pci_wait_for_target_init(ar);
2721 if (ret) {
2722 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2723 ret);
2724 return ret;
2725 }
2726
2727 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2728
2729 return 0;
2730 }
2731
2732 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2733 {
2734 int ret;
2735
2736 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2737
2738 /* FIXME: QCA6174 requires cold + warm reset to work. */
2739
2740 ret = ath10k_pci_cold_reset(ar);
2741 if (ret) {
2742 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2743 return ret;
2744 }
2745
2746 ret = ath10k_pci_wait_for_target_init(ar);
2747 if (ret) {
2748 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2749 ret);
2750 return ret;
2751 }
2752
2753 ret = ath10k_pci_warm_reset(ar);
2754 if (ret) {
2755 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2756 return ret;
2757 }
2758
2759 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2760
2761 return 0;
2762 }
2763
2764 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2765 {
2766 int ret;
2767
2768 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2769
2770 ret = ath10k_pci_cold_reset(ar);
2771 if (ret) {
2772 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2773 return ret;
2774 }
2775
2776 ret = ath10k_pci_wait_for_target_init(ar);
2777 if (ret) {
2778 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2779 ret);
2780 return ret;
2781 }
2782
2783 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2784
2785 return 0;
2786 }
2787
2788 static int ath10k_pci_chip_reset(struct ath10k *ar)
2789 {
2790 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2791
2792 if (WARN_ON(!ar_pci->pci_hard_reset))
2793 return -ENOTSUPP;
2794
2795 return ar_pci->pci_hard_reset(ar);
2796 }
2797
2798 static int ath10k_pci_hif_power_up(struct ath10k *ar,
2799 enum ath10k_firmware_mode fw_mode)
2800 {
2801 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2802 int ret;
2803
2804 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2805
2806 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2807 &ar_pci->link_ctl);
2808 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2809 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2810
2811 /*
2812 * Bring the target up cleanly.
2813 *
2814 * The target may be in an undefined state with an AUX-powered Target
2815 * and a Host in WoW mode. If the Host crashes, loses power, or is
2816 * restarted (without unloading the driver) then the Target is left
2817 * (aux) powered and running. On a subsequent driver load, the Target
2818 * is in an unexpected state. We try to catch that here in order to
2819 * reset the Target and retry the probe.
2820 */
2821 ret = ath10k_pci_chip_reset(ar);
2822 if (ret) {
2823 if (ath10k_pci_has_fw_crashed(ar)) {
2824 ath10k_warn(ar, "firmware crashed during chip reset\n");
2825 ath10k_pci_fw_crashed_clear(ar);
2826 ath10k_pci_fw_crashed_dump(ar);
2827 }
2828
2829 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2830 goto err_sleep;
2831 }
2832
2833 ret = ath10k_pci_init_pipes(ar);
2834 if (ret) {
2835 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2836 goto err_sleep;
2837 }
2838
2839 ret = ath10k_pci_init_config(ar);
2840 if (ret) {
2841 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2842 goto err_ce;
2843 }
2844
2845 ret = ath10k_pci_wake_target_cpu(ar);
2846 if (ret) {
2847 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2848 goto err_ce;
2849 }
2850
2851 return 0;
2852
2853 err_ce:
2854 ath10k_pci_ce_deinit(ar);
2855
2856 err_sleep:
2857 return ret;
2858 }
2859
2860 void ath10k_pci_hif_power_down(struct ath10k *ar)
2861 {
2862 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2863
2864 /* Currently hif_power_up performs effectively a reset and hif_stop
2865 * resets the chip as well so there's no point in resetting here.
2866 */
2867 }
2868
2869 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2870 {
2871 /* Nothing to do; the important stuff is in the driver suspend. */
2872 return 0;
2873 }
2874
2875 static int ath10k_pci_suspend(struct ath10k *ar)
2876 {
2877 /* The grace timer can still be counting down and ar->ps_awake be true.
2878 * It is known that the device may be asleep after resuming regardless
2879 * of the SoC powersave state before suspending. Hence make sure the
2880 * device is asleep before proceeding.
2881 */
2882 ath10k_pci_sleep_sync(ar);
2883
2884 return 0;
2885 }
2886
2887 static int ath10k_pci_hif_resume(struct ath10k *ar)
2888 {
2889 /* Nothing to do; the important stuff is in the driver resume. */
2890 return 0;
2891 }
2892
2893 static int ath10k_pci_resume(struct ath10k *ar)
2894 {
2895 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2896 struct pci_dev *pdev = ar_pci->pdev;
2897 u32 val;
2898 int ret = 0;
2899
2900 ret = ath10k_pci_force_wake(ar);
2901 if (ret) {
2902 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2903 return ret;
2904 }
2905
2906 /* Suspend/Resume resets the PCI configuration space, so we have to
2907 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2908 * from interfering with C3 CPU state. pci_restore_state won't help
2909 * here since it only restores the first 64 bytes pci config header.
2910 */
2911 pci_read_config_dword(pdev, 0x40, &val);
2912 if ((val & 0x0000ff00) != 0)
2913 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2914
2915 return ret;
2916 }
2917
2918 static bool ath10k_pci_validate_cal(void *data, size_t size)
2919 {
2920 __le16 *cal_words = data;
2921 u16 checksum = 0;
2922 size_t i;
2923
2924 if (size % 2 != 0)
2925 return false;
2926
2927 for (i = 0; i < size / 2; i++)
2928 checksum ^= le16_to_cpu(cal_words[i]);
2929
2930 return checksum == 0xffff;
2931 }
2932
2933 static void ath10k_pci_enable_eeprom(struct ath10k *ar)
2934 {
2935 /* Enable SI clock */
2936 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);
2937
2938 /* Configure GPIOs for I2C operation */
2939 ath10k_pci_write32(ar,
2940 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2941 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
2942 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
2943 GPIO_PIN0_CONFIG) |
2944 SM(1, GPIO_PIN0_PAD_PULL));
2945
2946 ath10k_pci_write32(ar,
2947 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2948 4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
2949 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
2950 SM(1, GPIO_PIN0_PAD_PULL));
2951
2952 ath10k_pci_write32(ar,
2953 GPIO_BASE_ADDRESS +
2954 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
2955 1u << QCA9887_1_0_SI_CLK_GPIO_PIN);
2956
2957 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
2958 ath10k_pci_write32(ar,
2959 SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
2960 SM(1, SI_CONFIG_ERR_INT) |
2961 SM(1, SI_CONFIG_BIDIR_OD_DATA) |
2962 SM(1, SI_CONFIG_I2C) |
2963 SM(1, SI_CONFIG_POS_SAMPLE) |
2964 SM(1, SI_CONFIG_INACTIVE_DATA) |
2965 SM(1, SI_CONFIG_INACTIVE_CLK) |
2966 SM(8, SI_CONFIG_DIVIDER));
2967 }
2968
2969 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
2970 {
2971 u32 reg;
2972 int wait_limit;
2973
2974 /* set device select byte and for the read operation */
2975 reg = QCA9887_EEPROM_SELECT_READ |
2976 SM(addr, QCA9887_EEPROM_ADDR_LO) |
2977 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
2978 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
2979
2980 /* write transmit data, transfer length, and START bit */
2981 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
2982 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
2983 SM(4, SI_CS_TX_CNT));
2984
2985 /* wait max 1 sec */
2986 wait_limit = 100000;
2987
2988 /* wait for SI_CS_DONE_INT */
2989 do {
2990 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
2991 if (MS(reg, SI_CS_DONE_INT))
2992 break;
2993
2994 wait_limit--;
2995 udelay(10);
2996 } while (wait_limit > 0);
2997
2998 if (!MS(reg, SI_CS_DONE_INT)) {
2999 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
3000 addr);
3001 return -ETIMEDOUT;
3002 }
3003
3004 /* clear SI_CS_DONE_INT */
3005 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
3006
3007 if (MS(reg, SI_CS_DONE_ERR)) {
3008 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
3009 return -EIO;
3010 }
3011
3012 /* extract receive data */
3013 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
3014 *out = reg;
3015
3016 return 0;
3017 }
3018
3019 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
3020 size_t *data_len)
3021 {
3022 u8 *caldata = NULL;
3023 size_t calsize, i;
3024 int ret;
3025
3026 if (!QCA_REV_9887(ar))
3027 return -EOPNOTSUPP;
3028
3029 calsize = ar->hw_params.cal_data_len;
3030 caldata = kmalloc(calsize, GFP_KERNEL);
3031 if (!caldata)
3032 return -ENOMEM;
3033
3034 ath10k_pci_enable_eeprom(ar);
3035
3036 for (i = 0; i < calsize; i++) {
3037 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
3038 if (ret)
3039 goto err_free;
3040 }
3041
3042 if (!ath10k_pci_validate_cal(caldata, calsize))
3043 goto err_free;
3044
3045 *data = caldata;
3046 *data_len = calsize;
3047
3048 return 0;
3049
3050 err_free:
3051 kfree(caldata);
3052
3053 return -EINVAL;
3054 }
3055
3056 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
3057 .tx_sg = ath10k_pci_hif_tx_sg,
3058 .diag_read = ath10k_pci_hif_diag_read,
3059 .diag_write = ath10k_pci_diag_write_mem,
3060 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
3061 .start = ath10k_pci_hif_start,
3062 .stop = ath10k_pci_hif_stop,
3063 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
3064 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
3065 .send_complete_check = ath10k_pci_hif_send_complete_check,
3066 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
3067 .power_up = ath10k_pci_hif_power_up,
3068 .power_down = ath10k_pci_hif_power_down,
3069 .read32 = ath10k_pci_read32,
3070 .write32 = ath10k_pci_write32,
3071 .suspend = ath10k_pci_hif_suspend,
3072 .resume = ath10k_pci_hif_resume,
3073 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom,
3074 };
3075
3076 /*
3077 * Top-level interrupt handler for all PCI interrupts from a Target.
3078 * When a block of MSI interrupts is allocated, this top-level handler
3079 * is not used; instead, we directly call the correct sub-handler.
3080 */
3081 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
3082 {
3083 struct ath10k *ar = arg;
3084 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3085 int ret;
3086
3087 if (ath10k_pci_has_device_gone(ar))
3088 return IRQ_NONE;
3089
3090 ret = ath10k_pci_force_wake(ar);
3091 if (ret) {
3092 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
3093 return IRQ_NONE;
3094 }
3095
3096 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) &&
3097 !ath10k_pci_irq_pending(ar))
3098 return IRQ_NONE;
3099
3100 ath10k_pci_disable_and_clear_legacy_irq(ar);
3101 ath10k_pci_irq_msi_fw_mask(ar);
3102 napi_schedule(&ar->napi);
3103
3104 return IRQ_HANDLED;
3105 }
3106
3107 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
3108 {
3109 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
3110 int done = 0;
3111
3112 if (ath10k_pci_has_fw_crashed(ar)) {
3113 ath10k_pci_fw_crashed_clear(ar);
3114 ath10k_pci_fw_crashed_dump(ar);
3115 napi_complete(ctx);
3116 return done;
3117 }
3118
3119 ath10k_ce_per_engine_service_any(ar);
3120
3121 done = ath10k_htt_txrx_compl_task(ar, budget);
3122
3123 if (done < budget) {
3124 napi_complete_done(ctx, done);
3125 /* In case of MSI, it is possible that interrupts are received
3126 * while NAPI poll is inprogress. So pending interrupts that are
3127 * received after processing all copy engine pipes by NAPI poll
3128 * will not be handled again. This is causing failure to
3129 * complete boot sequence in x86 platform. So before enabling
3130 * interrupts safer to check for pending interrupts for
3131 * immediate servicing.
3132 */
3133 if (ath10k_ce_interrupt_summary(ar)) {
3134 napi_reschedule(ctx);
3135 goto out;
3136 }
3137 ath10k_pci_enable_legacy_irq(ar);
3138 ath10k_pci_irq_msi_fw_unmask(ar);
3139 }
3140
3141 out:
3142 return done;
3143 }
3144
3145 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
3146 {
3147 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3148 int ret;
3149
3150 ret = request_irq(ar_pci->pdev->irq,
3151 ath10k_pci_interrupt_handler,
3152 IRQF_SHARED, "ath10k_pci", ar);
3153 if (ret) {
3154 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
3155 ar_pci->pdev->irq, ret);
3156 return ret;
3157 }
3158
3159 return 0;
3160 }
3161
3162 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
3163 {
3164 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3165 int ret;
3166
3167 ret = request_irq(ar_pci->pdev->irq,
3168 ath10k_pci_interrupt_handler,
3169 IRQF_SHARED, "ath10k_pci", ar);
3170 if (ret) {
3171 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
3172 ar_pci->pdev->irq, ret);
3173 return ret;
3174 }
3175
3176 return 0;
3177 }
3178
3179 static int ath10k_pci_request_irq(struct ath10k *ar)
3180 {
3181 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3182
3183 switch (ar_pci->oper_irq_mode) {
3184 case ATH10K_PCI_IRQ_LEGACY:
3185 return ath10k_pci_request_irq_legacy(ar);
3186 case ATH10K_PCI_IRQ_MSI:
3187 return ath10k_pci_request_irq_msi(ar);
3188 default:
3189 return -EINVAL;
3190 }
3191 }
3192
3193 static void ath10k_pci_free_irq(struct ath10k *ar)
3194 {
3195 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3196
3197 free_irq(ar_pci->pdev->irq, ar);
3198 }
3199
3200 void ath10k_pci_init_napi(struct ath10k *ar)
3201 {
3202 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll,
3203 ATH10K_NAPI_BUDGET);
3204 }
3205
3206 static int ath10k_pci_init_irq(struct ath10k *ar)
3207 {
3208 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3209 int ret;
3210
3211 ath10k_pci_init_napi(ar);
3212
3213 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
3214 ath10k_info(ar, "limiting irq mode to: %d\n",
3215 ath10k_pci_irq_mode);
3216
3217 /* Try MSI */
3218 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
3219 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
3220 ret = pci_enable_msi(ar_pci->pdev);
3221 if (ret == 0)
3222 return 0;
3223
3224 /* fall-through */
3225 }
3226
3227 /* Try legacy irq
3228 *
3229 * A potential race occurs here: The CORE_BASE write
3230 * depends on target correctly decoding AXI address but
3231 * host won't know when target writes BAR to CORE_CTRL.
3232 * This write might get lost if target has NOT written BAR.
3233 * For now, fix the race by repeating the write in below
3234 * synchronization checking.
3235 */
3236 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
3237
3238 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3239 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
3240
3241 return 0;
3242 }
3243
3244 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
3245 {
3246 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3247 0);
3248 }
3249
3250 static int ath10k_pci_deinit_irq(struct ath10k *ar)
3251 {
3252 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3253
3254 switch (ar_pci->oper_irq_mode) {
3255 case ATH10K_PCI_IRQ_LEGACY:
3256 ath10k_pci_deinit_irq_legacy(ar);
3257 break;
3258 default:
3259 pci_disable_msi(ar_pci->pdev);
3260 break;
3261 }
3262
3263 return 0;
3264 }
3265
3266 int ath10k_pci_wait_for_target_init(struct ath10k *ar)
3267 {
3268 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3269 unsigned long timeout;
3270 u32 val;
3271
3272 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
3273
3274 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
3275
3276 do {
3277 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
3278
3279 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
3280 val);
3281
3282 /* target should never return this */
3283 if (val == 0xffffffff)
3284 continue;
3285
3286 /* the device has crashed so don't bother trying anymore */
3287 if (val & FW_IND_EVENT_PENDING)
3288 break;
3289
3290 if (val & FW_IND_INITIALIZED)
3291 break;
3292
3293 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
3294 /* Fix potential race by repeating CORE_BASE writes */
3295 ath10k_pci_enable_legacy_irq(ar);
3296
3297 mdelay(10);
3298 } while (time_before(jiffies, timeout));
3299
3300 ath10k_pci_disable_and_clear_legacy_irq(ar);
3301 ath10k_pci_irq_msi_fw_mask(ar);
3302
3303 if (val == 0xffffffff) {
3304 ath10k_err(ar, "failed to read device register, device is gone\n");
3305 return -EIO;
3306 }
3307
3308 if (val & FW_IND_EVENT_PENDING) {
3309 ath10k_warn(ar, "device has crashed during init\n");
3310 return -ECOMM;
3311 }
3312
3313 if (!(val & FW_IND_INITIALIZED)) {
3314 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
3315 val);
3316 return -ETIMEDOUT;
3317 }
3318
3319 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
3320 return 0;
3321 }
3322
3323 static int ath10k_pci_cold_reset(struct ath10k *ar)
3324 {
3325 u32 val;
3326
3327 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
3328
3329 spin_lock_bh(&ar->data_lock);
3330
3331 ar->stats.fw_cold_reset_counter++;
3332
3333 spin_unlock_bh(&ar->data_lock);
3334
3335 /* Put Target, including PCIe, into RESET. */
3336 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3337 val |= 1;
3338 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3339
3340 /* After writing into SOC_GLOBAL_RESET to put device into
3341 * reset and pulling out of reset pcie may not be stable
3342 * for any immediate pcie register access and cause bus error,
3343 * add delay before any pcie access request to fix this issue.
3344 */
3345 msleep(20);
3346
3347 /* Pull Target, including PCIe, out of RESET. */
3348 val &= ~1;
3349 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3350
3351 msleep(20);
3352
3353 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
3354
3355 return 0;
3356 }
3357
3358 static int ath10k_pci_claim(struct ath10k *ar)
3359 {
3360 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3361 struct pci_dev *pdev = ar_pci->pdev;
3362 int ret;
3363
3364 pci_set_drvdata(pdev, ar);
3365
3366 ret = pci_enable_device(pdev);
3367 if (ret) {
3368 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3369 return ret;
3370 }
3371
3372 ret = pci_request_region(pdev, BAR_NUM, "ath");
3373 if (ret) {
3374 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3375 ret);
3376 goto err_device;
3377 }
3378
3379 /* Target expects 32 bit DMA. Enforce it. */
3380 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3381 if (ret) {
3382 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3383 goto err_region;
3384 }
3385
3386 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3387 if (ret) {
3388 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
3389 ret);
3390 goto err_region;
3391 }
3392
3393 pci_set_master(pdev);
3394
3395 /* Arrange for access to Target SoC registers. */
3396 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3397 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
3398 if (!ar_pci->mem) {
3399 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3400 ret = -EIO;
3401 goto err_master;
3402 }
3403
3404 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem);
3405 return 0;
3406
3407 err_master:
3408 pci_clear_master(pdev);
3409
3410 err_region:
3411 pci_release_region(pdev, BAR_NUM);
3412
3413 err_device:
3414 pci_disable_device(pdev);
3415
3416 return ret;
3417 }
3418
3419 static void ath10k_pci_release(struct ath10k *ar)
3420 {
3421 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3422 struct pci_dev *pdev = ar_pci->pdev;
3423
3424 pci_iounmap(pdev, ar_pci->mem);
3425 pci_release_region(pdev, BAR_NUM);
3426 pci_clear_master(pdev);
3427 pci_disable_device(pdev);
3428 }
3429
3430 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3431 {
3432 const struct ath10k_pci_supp_chip *supp_chip;
3433 int i;
3434 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3435
3436 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3437 supp_chip = &ath10k_pci_supp_chips[i];
3438
3439 if (supp_chip->dev_id == dev_id &&
3440 supp_chip->rev_id == rev_id)
3441 return true;
3442 }
3443
3444 return false;
3445 }
3446
3447 int ath10k_pci_setup_resource(struct ath10k *ar)
3448 {
3449 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3450 struct ath10k_ce *ce = ath10k_ce_priv(ar);
3451 int ret;
3452
3453 spin_lock_init(&ce->ce_lock);
3454 spin_lock_init(&ar_pci->ps_lock);
3455 mutex_init(&ar_pci->ce_diag_mutex);
3456
3457 INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work);
3458
3459 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0);
3460
3461 if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
3462 ath10k_pci_override_ce_config(ar);
3463
3464 ret = ath10k_pci_alloc_pipes(ar);
3465 if (ret) {
3466 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3467 ret);
3468 return ret;
3469 }
3470
3471 return 0;
3472 }
3473
3474 void ath10k_pci_release_resource(struct ath10k *ar)
3475 {
3476 ath10k_pci_rx_retry_sync(ar);
3477 netif_napi_del(&ar->napi);
3478 ath10k_pci_ce_deinit(ar);
3479 ath10k_pci_free_pipes(ar);
3480 }
3481
3482 static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3483 .read32 = ath10k_bus_pci_read32,
3484 .write32 = ath10k_bus_pci_write32,
3485 .get_num_banks = ath10k_pci_get_num_banks,
3486 };
3487
3488 static int ath10k_pci_probe(struct pci_dev *pdev,
3489 const struct pci_device_id *pci_dev)
3490 {
3491 int ret = 0;
3492 struct ath10k *ar;
3493 struct ath10k_pci *ar_pci;
3494 enum ath10k_hw_rev hw_rev;
3495 struct ath10k_bus_params bus_params = {};
3496 bool pci_ps;
3497 int (*pci_soft_reset)(struct ath10k *ar);
3498 int (*pci_hard_reset)(struct ath10k *ar);
3499 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
3500
3501 switch (pci_dev->device) {
3502 case QCA988X_2_0_DEVICE_ID_UBNT:
3503 case QCA988X_2_0_DEVICE_ID:
3504 hw_rev = ATH10K_HW_QCA988X;
3505 pci_ps = false;
3506 pci_soft_reset = ath10k_pci_warm_reset;
3507 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3508 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3509 break;
3510 case QCA9887_1_0_DEVICE_ID:
3511 hw_rev = ATH10K_HW_QCA9887;
3512 pci_ps = false;
3513 pci_soft_reset = ath10k_pci_warm_reset;
3514 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3515 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3516 break;
3517 case QCA6164_2_1_DEVICE_ID:
3518 case QCA6174_2_1_DEVICE_ID:
3519 hw_rev = ATH10K_HW_QCA6174;
3520 pci_ps = true;
3521 pci_soft_reset = ath10k_pci_warm_reset;
3522 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3523 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
3524 break;
3525 case QCA99X0_2_0_DEVICE_ID:
3526 hw_rev = ATH10K_HW_QCA99X0;
3527 pci_ps = false;
3528 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3529 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3530 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3531 break;
3532 case QCA9984_1_0_DEVICE_ID:
3533 hw_rev = ATH10K_HW_QCA9984;
3534 pci_ps = false;
3535 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3536 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3537 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3538 break;
3539 case QCA9888_2_0_DEVICE_ID:
3540 hw_rev = ATH10K_HW_QCA9888;
3541 pci_ps = false;
3542 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3543 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3544 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3545 break;
3546 case QCA9377_1_0_DEVICE_ID:
3547 hw_rev = ATH10K_HW_QCA9377;
3548 pci_ps = true;
3549 pci_soft_reset = ath10k_pci_warm_reset;
3550 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3551 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
3552 break;
3553 default:
3554 WARN_ON(1);
3555 return -ENOTSUPP;
3556 }
3557
3558 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3559 hw_rev, &ath10k_pci_hif_ops);
3560 if (!ar) {
3561 dev_err(&pdev->dev, "failed to allocate core\n");
3562 return -ENOMEM;
3563 }
3564
3565 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3566 pdev->vendor, pdev->device,
3567 pdev->subsystem_vendor, pdev->subsystem_device);
3568
3569 ar_pci = ath10k_pci_priv(ar);
3570 ar_pci->pdev = pdev;
3571 ar_pci->dev = &pdev->dev;
3572 ar_pci->ar = ar;
3573 ar->dev_id = pci_dev->device;
3574 ar_pci->pci_ps = pci_ps;
3575 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
3576 ar_pci->pci_soft_reset = pci_soft_reset;
3577 ar_pci->pci_hard_reset = pci_hard_reset;
3578 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
3579 ar->ce_priv = &ar_pci->ce;
3580
3581 ar->id.vendor = pdev->vendor;
3582 ar->id.device = pdev->device;
3583 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3584 ar->id.subsystem_device = pdev->subsystem_device;
3585
3586 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0);
3587
3588 ret = ath10k_pci_setup_resource(ar);
3589 if (ret) {
3590 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3591 goto err_core_destroy;
3592 }
3593
3594 ret = ath10k_pci_claim(ar);
3595 if (ret) {
3596 ath10k_err(ar, "failed to claim device: %d\n", ret);
3597 goto err_free_pipes;
3598 }
3599
3600 ret = ath10k_pci_force_wake(ar);
3601 if (ret) {
3602 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3603 goto err_sleep;
3604 }
3605
3606 ath10k_pci_ce_deinit(ar);
3607 ath10k_pci_irq_disable(ar);
3608
3609 ret = ath10k_pci_init_irq(ar);
3610 if (ret) {
3611 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3612 goto err_sleep;
3613 }
3614
3615 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3616 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3617 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3618
3619 ret = ath10k_pci_request_irq(ar);
3620 if (ret) {
3621 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3622 goto err_deinit_irq;
3623 }
3624
3625 ret = ath10k_pci_chip_reset(ar);
3626 if (ret) {
3627 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3628 goto err_free_irq;
3629 }
3630
3631 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
3632 bus_params.link_can_suspend = true;
3633 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3634 if (bus_params.chip_id == 0xffffffff) {
3635 ath10k_err(ar, "failed to get chip id\n");
3636 goto err_free_irq;
3637 }
3638
3639 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
3640 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3641 pdev->device, bus_params.chip_id);
3642 goto err_free_irq;
3643 }
3644
3645 ret = ath10k_core_register(ar, &bus_params);
3646 if (ret) {
3647 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3648 goto err_free_irq;
3649 }
3650
3651 return 0;
3652
3653 err_free_irq:
3654 ath10k_pci_free_irq(ar);
3655 ath10k_pci_rx_retry_sync(ar);
3656
3657 err_deinit_irq:
3658 ath10k_pci_deinit_irq(ar);
3659
3660 err_sleep:
3661 ath10k_pci_sleep_sync(ar);
3662 ath10k_pci_release(ar);
3663
3664 err_free_pipes:
3665 ath10k_pci_free_pipes(ar);
3666
3667 err_core_destroy:
3668 ath10k_core_destroy(ar);
3669
3670 return ret;
3671 }
3672
3673 static void ath10k_pci_remove(struct pci_dev *pdev)
3674 {
3675 struct ath10k *ar = pci_get_drvdata(pdev);
3676 struct ath10k_pci *ar_pci;
3677
3678 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3679
3680 if (!ar)
3681 return;
3682
3683 ar_pci = ath10k_pci_priv(ar);
3684
3685 if (!ar_pci)
3686 return;
3687
3688 ath10k_core_unregister(ar);
3689 ath10k_pci_free_irq(ar);
3690 ath10k_pci_deinit_irq(ar);
3691 ath10k_pci_release_resource(ar);
3692 ath10k_pci_sleep_sync(ar);
3693 ath10k_pci_release(ar);
3694 ath10k_core_destroy(ar);
3695 }
3696
3697 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3698
3699 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev)
3700 {
3701 struct ath10k *ar = dev_get_drvdata(dev);
3702 int ret;
3703
3704 ret = ath10k_pci_suspend(ar);
3705 if (ret)
3706 ath10k_warn(ar, "failed to suspend hif: %d\n", ret);
3707
3708 return ret;
3709 }
3710
3711 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev)
3712 {
3713 struct ath10k *ar = dev_get_drvdata(dev);
3714 int ret;
3715
3716 ret = ath10k_pci_resume(ar);
3717 if (ret)
3718 ath10k_warn(ar, "failed to resume hif: %d\n", ret);
3719
3720 return ret;
3721 }
3722
3723 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops,
3724 ath10k_pci_pm_suspend,
3725 ath10k_pci_pm_resume);
3726
3727 static struct pci_driver ath10k_pci_driver = {
3728 .name = "ath10k_pci",
3729 .id_table = ath10k_pci_id_table,
3730 .probe = ath10k_pci_probe,
3731 .remove = ath10k_pci_remove,
3732 #ifdef CONFIG_PM
3733 .driver.pm = &ath10k_pci_pm_ops,
3734 #endif
3735 };
3736
3737 static int __init ath10k_pci_init(void)
3738 {
3739 int ret;
3740
3741 ret = pci_register_driver(&ath10k_pci_driver);
3742 if (ret)
3743 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3744 ret);
3745
3746 ret = ath10k_ahb_init();
3747 if (ret)
3748 printk(KERN_ERR "ahb init failed: %d\n", ret);
3749
3750 return ret;
3751 }
3752 module_init(ath10k_pci_init);
3753
3754 static void __exit ath10k_pci_exit(void)
3755 {
3756 pci_unregister_driver(&ath10k_pci_driver);
3757 ath10k_ahb_exit();
3758 }
3759
3760 module_exit(ath10k_pci_exit);
3761
3762 MODULE_AUTHOR("Qualcomm Atheros");
3763 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3764 MODULE_LICENSE("Dual BSD/GPL");
3765
3766 /* QCA988x 2.0 firmware files */
3767 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3768 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3769 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3770 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3771 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3772 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3773
3774 /* QCA9887 1.0 firmware files */
3775 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3776 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE);
3777 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3778
3779 /* QCA6174 2.1 firmware files */
3780 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3781 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3782 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3783 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3784
3785 /* QCA6174 3.1 firmware files */
3786 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3787 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3788 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3789 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3790 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3791
3792 /* QCA9377 1.0 firmware files */
3793 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3794 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3795 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);
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