2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_reset_mode
{
37 ATH10K_PCI_RESET_AUTO
= 0,
38 ATH10K_PCI_RESET_WARM_ONLY
= 1,
41 static unsigned int ath10k_pci_irq_mode
= ATH10K_PCI_IRQ_AUTO
;
42 static unsigned int ath10k_pci_reset_mode
= ATH10K_PCI_RESET_AUTO
;
44 module_param_named(irq_mode
, ath10k_pci_irq_mode
, uint
, 0644);
45 MODULE_PARM_DESC(irq_mode
, "0: auto, 1: legacy, 2: msi (default: 0)");
47 module_param_named(reset_mode
, ath10k_pci_reset_mode
, uint
, 0644);
48 MODULE_PARM_DESC(reset_mode
, "0: auto, 1: warm only (default: 0)");
50 /* how long wait to wait for target to initialise, in ms */
51 #define ATH10K_PCI_TARGET_WAIT 3000
52 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
54 static const struct pci_device_id ath10k_pci_id_table
[] = {
55 { PCI_VDEVICE(ATHEROS
, QCA988X_2_0_DEVICE_ID
) }, /* PCI-E QCA988X V2 */
56 { PCI_VDEVICE(ATHEROS
, QCA6164_2_1_DEVICE_ID
) }, /* PCI-E QCA6164 V2.1 */
57 { PCI_VDEVICE(ATHEROS
, QCA6174_2_1_DEVICE_ID
) }, /* PCI-E QCA6174 V2.1 */
58 { PCI_VDEVICE(ATHEROS
, QCA99X0_2_0_DEVICE_ID
) }, /* PCI-E QCA99X0 V2 */
59 { PCI_VDEVICE(ATHEROS
, QCA9377_1_0_DEVICE_ID
) }, /* PCI-E QCA9377 V1 */
63 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips
[] = {
64 /* QCA988X pre 2.0 chips are not supported because they need some nasty
65 * hacks. ath10k doesn't have them and these devices crash horribly
68 { QCA988X_2_0_DEVICE_ID
, QCA988X_HW_2_0_CHIP_ID_REV
},
70 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_2_1_CHIP_ID_REV
},
71 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_2_2_CHIP_ID_REV
},
72 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_3_0_CHIP_ID_REV
},
73 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_3_1_CHIP_ID_REV
},
74 { QCA6164_2_1_DEVICE_ID
, QCA6174_HW_3_2_CHIP_ID_REV
},
76 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_2_1_CHIP_ID_REV
},
77 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_2_2_CHIP_ID_REV
},
78 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_0_CHIP_ID_REV
},
79 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_1_CHIP_ID_REV
},
80 { QCA6174_2_1_DEVICE_ID
, QCA6174_HW_3_2_CHIP_ID_REV
},
82 { QCA99X0_2_0_DEVICE_ID
, QCA99X0_HW_2_0_CHIP_ID_REV
},
84 { QCA9377_1_0_DEVICE_ID
, QCA9377_HW_1_0_CHIP_ID_REV
},
85 { QCA9377_1_0_DEVICE_ID
, QCA9377_HW_1_1_CHIP_ID_REV
},
88 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
);
89 static int ath10k_pci_cold_reset(struct ath10k
*ar
);
90 static int ath10k_pci_safe_chip_reset(struct ath10k
*ar
);
91 static int ath10k_pci_init_irq(struct ath10k
*ar
);
92 static int ath10k_pci_deinit_irq(struct ath10k
*ar
);
93 static int ath10k_pci_request_irq(struct ath10k
*ar
);
94 static void ath10k_pci_free_irq(struct ath10k
*ar
);
95 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe
*tx_pipe
,
96 struct ath10k_ce_pipe
*rx_pipe
,
97 struct bmi_xfer
*xfer
);
98 static int ath10k_pci_qca99x0_chip_reset(struct ath10k
*ar
);
99 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe
*ce_state
);
100 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
);
101 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe
*ce_state
);
102 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe
*ce_state
);
103 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
);
104 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe
*ce_state
);
106 static struct ce_attr host_ce_config_wlan
[] = {
107 /* CE0: host->target HTC control and raw streams */
109 .flags
= CE_ATTR_FLAGS
,
113 .send_cb
= ath10k_pci_htc_tx_cb
,
116 /* CE1: target->host HTT + HTC control */
118 .flags
= CE_ATTR_FLAGS
,
121 .dest_nentries
= 512,
122 .recv_cb
= ath10k_pci_htt_htc_rx_cb
,
125 /* CE2: target->host WMI */
127 .flags
= CE_ATTR_FLAGS
,
130 .dest_nentries
= 128,
131 .recv_cb
= ath10k_pci_htc_rx_cb
,
134 /* CE3: host->target WMI */
136 .flags
= CE_ATTR_FLAGS
,
140 .send_cb
= ath10k_pci_htc_tx_cb
,
143 /* CE4: host->target HTT */
145 .flags
= CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
,
146 .src_nentries
= CE_HTT_H2T_MSG_SRC_NENTRIES
,
149 .send_cb
= ath10k_pci_htt_tx_cb
,
152 /* CE5: target->host HTT (HIF->HTT) */
154 .flags
= CE_ATTR_FLAGS
,
157 .dest_nentries
= 512,
158 .recv_cb
= ath10k_pci_htt_rx_cb
,
161 /* CE6: target autonomous hif_memcpy */
163 .flags
= CE_ATTR_FLAGS
,
169 /* CE7: ce_diag, the Diagnostic Window */
171 .flags
= CE_ATTR_FLAGS
,
173 .src_sz_max
= DIAG_TRANSFER_LIMIT
,
177 /* CE8: target->host pktlog */
179 .flags
= CE_ATTR_FLAGS
,
182 .dest_nentries
= 128,
183 .recv_cb
= ath10k_pci_pktlog_rx_cb
,
186 /* CE9 target autonomous qcache memcpy */
188 .flags
= CE_ATTR_FLAGS
,
194 /* CE10: target autonomous hif memcpy */
196 .flags
= CE_ATTR_FLAGS
,
202 /* CE11: target autonomous hif memcpy */
204 .flags
= CE_ATTR_FLAGS
,
211 /* Target firmware's Copy Engine configuration. */
212 static struct ce_pipe_config target_ce_config_wlan
[] = {
213 /* CE0: host->target HTC control and raw streams */
215 .pipenum
= __cpu_to_le32(0),
216 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
217 .nentries
= __cpu_to_le32(32),
218 .nbytes_max
= __cpu_to_le32(256),
219 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
220 .reserved
= __cpu_to_le32(0),
223 /* CE1: target->host HTT + HTC control */
225 .pipenum
= __cpu_to_le32(1),
226 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
227 .nentries
= __cpu_to_le32(32),
228 .nbytes_max
= __cpu_to_le32(2048),
229 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
230 .reserved
= __cpu_to_le32(0),
233 /* CE2: target->host WMI */
235 .pipenum
= __cpu_to_le32(2),
236 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
237 .nentries
= __cpu_to_le32(64),
238 .nbytes_max
= __cpu_to_le32(2048),
239 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
240 .reserved
= __cpu_to_le32(0),
243 /* CE3: host->target WMI */
245 .pipenum
= __cpu_to_le32(3),
246 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
247 .nentries
= __cpu_to_le32(32),
248 .nbytes_max
= __cpu_to_le32(2048),
249 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
250 .reserved
= __cpu_to_le32(0),
253 /* CE4: host->target HTT */
255 .pipenum
= __cpu_to_le32(4),
256 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
257 .nentries
= __cpu_to_le32(256),
258 .nbytes_max
= __cpu_to_le32(256),
259 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
260 .reserved
= __cpu_to_le32(0),
263 /* NB: 50% of src nentries, since tx has 2 frags */
265 /* CE5: target->host HTT (HIF->HTT) */
267 .pipenum
= __cpu_to_le32(5),
268 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
269 .nentries
= __cpu_to_le32(32),
270 .nbytes_max
= __cpu_to_le32(512),
271 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
272 .reserved
= __cpu_to_le32(0),
275 /* CE6: Reserved for target autonomous hif_memcpy */
277 .pipenum
= __cpu_to_le32(6),
278 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
279 .nentries
= __cpu_to_le32(32),
280 .nbytes_max
= __cpu_to_le32(4096),
281 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
282 .reserved
= __cpu_to_le32(0),
285 /* CE7 used only by Host */
287 .pipenum
= __cpu_to_le32(7),
288 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
289 .nentries
= __cpu_to_le32(0),
290 .nbytes_max
= __cpu_to_le32(0),
291 .flags
= __cpu_to_le32(0),
292 .reserved
= __cpu_to_le32(0),
295 /* CE8 target->host packtlog */
297 .pipenum
= __cpu_to_le32(8),
298 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
299 .nentries
= __cpu_to_le32(64),
300 .nbytes_max
= __cpu_to_le32(2048),
301 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
),
302 .reserved
= __cpu_to_le32(0),
305 /* CE9 target autonomous qcache memcpy */
307 .pipenum
= __cpu_to_le32(9),
308 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
309 .nentries
= __cpu_to_le32(32),
310 .nbytes_max
= __cpu_to_le32(2048),
311 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
),
312 .reserved
= __cpu_to_le32(0),
315 /* It not necessary to send target wlan configuration for CE10 & CE11
316 * as these CEs are not actively used in target.
321 * Map from service/endpoint to Copy Engine.
322 * This table is derived from the CE_PCI TABLE, above.
323 * It is passed to the Target at startup for use by firmware.
325 static struct service_to_pipe target_service_to_ce_map_wlan
[] = {
327 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
328 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
332 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
333 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
337 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
338 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
342 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
343 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
348 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
353 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
358 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
363 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
368 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
372 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
373 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
377 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
378 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
382 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
383 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
387 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
388 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
392 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
393 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
397 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
398 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
402 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
403 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
407 /* (Additions here) */
416 static bool ath10k_pci_is_awake(struct ath10k
*ar
)
418 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
419 u32 val
= ioread32(ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
422 return RTC_STATE_V_GET(val
) == RTC_STATE_V_ON
;
425 static void __ath10k_pci_wake(struct ath10k
*ar
)
427 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
429 lockdep_assert_held(&ar_pci
->ps_lock
);
431 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps wake reg refcount %lu awake %d\n",
432 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
434 iowrite32(PCIE_SOC_WAKE_V_MASK
,
435 ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
436 PCIE_SOC_WAKE_ADDRESS
);
439 static void __ath10k_pci_sleep(struct ath10k
*ar
)
441 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
443 lockdep_assert_held(&ar_pci
->ps_lock
);
445 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps sleep reg refcount %lu awake %d\n",
446 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
448 iowrite32(PCIE_SOC_WAKE_RESET
,
449 ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
450 PCIE_SOC_WAKE_ADDRESS
);
451 ar_pci
->ps_awake
= false;
454 static int ath10k_pci_wake_wait(struct ath10k
*ar
)
459 while (tot_delay
< PCIE_WAKE_TIMEOUT
) {
460 if (ath10k_pci_is_awake(ar
)) {
461 if (tot_delay
> PCIE_WAKE_LATE_US
)
462 ath10k_warn(ar
, "device wakeup took %d ms which is unusally long, otherwise it works normally.\n",
468 tot_delay
+= curr_delay
;
477 static int ath10k_pci_force_wake(struct ath10k
*ar
)
479 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
486 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
488 if (!ar_pci
->ps_awake
) {
489 iowrite32(PCIE_SOC_WAKE_V_MASK
,
490 ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
491 PCIE_SOC_WAKE_ADDRESS
);
493 ret
= ath10k_pci_wake_wait(ar
);
495 ar_pci
->ps_awake
= true;
498 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
503 static void ath10k_pci_force_sleep(struct ath10k
*ar
)
505 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
508 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
510 iowrite32(PCIE_SOC_WAKE_RESET
,
511 ar_pci
->mem
+ PCIE_LOCAL_BASE_ADDRESS
+
512 PCIE_SOC_WAKE_ADDRESS
);
513 ar_pci
->ps_awake
= false;
515 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
518 static int ath10k_pci_wake(struct ath10k
*ar
)
520 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
524 if (ar_pci
->pci_ps
== 0)
527 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
529 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps wake refcount %lu awake %d\n",
530 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
532 /* This function can be called very frequently. To avoid excessive
533 * CPU stalls for MMIO reads use a cache var to hold the device state.
535 if (!ar_pci
->ps_awake
) {
536 __ath10k_pci_wake(ar
);
538 ret
= ath10k_pci_wake_wait(ar
);
540 ar_pci
->ps_awake
= true;
544 ar_pci
->ps_wake_refcount
++;
545 WARN_ON(ar_pci
->ps_wake_refcount
== 0);
548 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
553 static void ath10k_pci_sleep(struct ath10k
*ar
)
555 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
558 if (ar_pci
->pci_ps
== 0)
561 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
563 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps sleep refcount %lu awake %d\n",
564 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
566 if (WARN_ON(ar_pci
->ps_wake_refcount
== 0))
569 ar_pci
->ps_wake_refcount
--;
571 mod_timer(&ar_pci
->ps_timer
, jiffies
+
572 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC
));
575 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
578 static void ath10k_pci_ps_timer(unsigned long ptr
)
580 struct ath10k
*ar
= (void *)ptr
;
581 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
584 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
586 ath10k_dbg(ar
, ATH10K_DBG_PCI_PS
, "pci ps timer refcount %lu awake %d\n",
587 ar_pci
->ps_wake_refcount
, ar_pci
->ps_awake
);
589 if (ar_pci
->ps_wake_refcount
> 0)
592 __ath10k_pci_sleep(ar
);
595 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
598 static void ath10k_pci_sleep_sync(struct ath10k
*ar
)
600 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
603 if (ar_pci
->pci_ps
== 0) {
604 ath10k_pci_force_sleep(ar
);
608 del_timer_sync(&ar_pci
->ps_timer
);
610 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
611 WARN_ON(ar_pci
->ps_wake_refcount
> 0);
612 __ath10k_pci_sleep(ar
);
613 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
616 static void ath10k_bus_pci_write32(struct ath10k
*ar
, u32 offset
, u32 value
)
618 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
621 if (unlikely(offset
+ sizeof(value
) > ar_pci
->mem_len
)) {
622 ath10k_warn(ar
, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
623 offset
, offset
+ sizeof(value
), ar_pci
->mem_len
);
627 ret
= ath10k_pci_wake(ar
);
629 ath10k_warn(ar
, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
634 iowrite32(value
, ar_pci
->mem
+ offset
);
635 ath10k_pci_sleep(ar
);
638 static u32
ath10k_bus_pci_read32(struct ath10k
*ar
, u32 offset
)
640 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
644 if (unlikely(offset
+ sizeof(val
) > ar_pci
->mem_len
)) {
645 ath10k_warn(ar
, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
646 offset
, offset
+ sizeof(val
), ar_pci
->mem_len
);
650 ret
= ath10k_pci_wake(ar
);
652 ath10k_warn(ar
, "failed to wake target for read32 at 0x%08x: %d\n",
657 val
= ioread32(ar_pci
->mem
+ offset
);
658 ath10k_pci_sleep(ar
);
663 inline void ath10k_pci_write32(struct ath10k
*ar
, u32 offset
, u32 value
)
665 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
667 ar_pci
->bus_ops
->write32(ar
, offset
, value
);
670 inline u32
ath10k_pci_read32(struct ath10k
*ar
, u32 offset
)
672 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
674 return ar_pci
->bus_ops
->read32(ar
, offset
);
677 u32
ath10k_pci_soc_read32(struct ath10k
*ar
, u32 addr
)
679 return ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+ addr
);
682 void ath10k_pci_soc_write32(struct ath10k
*ar
, u32 addr
, u32 val
)
684 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ addr
, val
);
687 u32
ath10k_pci_reg_read32(struct ath10k
*ar
, u32 addr
)
689 return ath10k_pci_read32(ar
, PCIE_LOCAL_BASE_ADDRESS
+ addr
);
692 void ath10k_pci_reg_write32(struct ath10k
*ar
, u32 addr
, u32 val
)
694 ath10k_pci_write32(ar
, PCIE_LOCAL_BASE_ADDRESS
+ addr
, val
);
697 bool ath10k_pci_irq_pending(struct ath10k
*ar
)
701 /* Check if the shared legacy irq is for us */
702 cause
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
703 PCIE_INTR_CAUSE_ADDRESS
);
704 if (cause
& (PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
))
710 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k
*ar
)
712 /* IMPORTANT: INTR_CLR register has to be set after
713 * INTR_ENABLE is set to 0, otherwise interrupt can not be
715 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
717 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_CLR_ADDRESS
,
718 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
720 /* IMPORTANT: this extra read transaction is required to
721 * flush the posted write buffer. */
722 (void)ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
723 PCIE_INTR_ENABLE_ADDRESS
);
726 void ath10k_pci_enable_legacy_irq(struct ath10k
*ar
)
728 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+
729 PCIE_INTR_ENABLE_ADDRESS
,
730 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
732 /* IMPORTANT: this extra read transaction is required to
733 * flush the posted write buffer. */
734 (void)ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
735 PCIE_INTR_ENABLE_ADDRESS
);
738 static inline const char *ath10k_pci_get_irq_method(struct ath10k
*ar
)
740 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
742 if (ar_pci
->oper_irq_mode
== ATH10K_PCI_IRQ_MSI
)
748 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe
*pipe
)
750 struct ath10k
*ar
= pipe
->hif_ce_state
;
751 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
752 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
757 skb
= dev_alloc_skb(pipe
->buf_sz
);
761 WARN_ONCE((unsigned long)skb
->data
& 3, "unaligned skb");
763 paddr
= dma_map_single(ar
->dev
, skb
->data
,
764 skb
->len
+ skb_tailroom(skb
),
766 if (unlikely(dma_mapping_error(ar
->dev
, paddr
))) {
767 ath10k_warn(ar
, "failed to dma map pci rx buf\n");
768 dev_kfree_skb_any(skb
);
772 ATH10K_SKB_RXCB(skb
)->paddr
= paddr
;
774 spin_lock_bh(&ar_pci
->ce_lock
);
775 ret
= __ath10k_ce_rx_post_buf(ce_pipe
, skb
, paddr
);
776 spin_unlock_bh(&ar_pci
->ce_lock
);
778 dma_unmap_single(ar
->dev
, paddr
, skb
->len
+ skb_tailroom(skb
),
780 dev_kfree_skb_any(skb
);
787 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe
*pipe
)
789 struct ath10k
*ar
= pipe
->hif_ce_state
;
790 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
791 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
794 if (pipe
->buf_sz
== 0)
797 if (!ce_pipe
->dest_ring
)
800 spin_lock_bh(&ar_pci
->ce_lock
);
801 num
= __ath10k_ce_rx_num_free_bufs(ce_pipe
);
802 spin_unlock_bh(&ar_pci
->ce_lock
);
805 ret
= __ath10k_pci_rx_post_buf(pipe
);
809 ath10k_warn(ar
, "failed to post pci rx buf: %d\n", ret
);
810 mod_timer(&ar_pci
->rx_post_retry
, jiffies
+
811 ATH10K_PCI_RX_POST_RETRY_MS
);
818 void ath10k_pci_rx_post(struct ath10k
*ar
)
820 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
823 for (i
= 0; i
< CE_COUNT
; i
++)
824 ath10k_pci_rx_post_pipe(&ar_pci
->pipe_info
[i
]);
827 void ath10k_pci_rx_replenish_retry(unsigned long ptr
)
829 struct ath10k
*ar
= (void *)ptr
;
831 ath10k_pci_rx_post(ar
);
834 static u32
ath10k_pci_targ_cpu_to_ce_addr(struct ath10k
*ar
, u32 addr
)
838 switch (ar
->hw_rev
) {
839 case ATH10K_HW_QCA988X
:
840 case ATH10K_HW_QCA6174
:
841 case ATH10K_HW_QCA9377
:
842 val
= (ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
846 case ATH10K_HW_QCA99X0
:
847 case ATH10K_HW_QCA4019
:
848 val
= ath10k_pci_read32(ar
, PCIE_BAR_REG_ADDRESS
);
852 val
|= 0x100000 | (addr
& 0xfffff);
857 * Diagnostic read/write access is provided for startup/config/debug usage.
858 * Caller must guarantee proper alignment, when applicable, and single user
861 static int ath10k_pci_diag_read_mem(struct ath10k
*ar
, u32 address
, void *data
,
864 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
867 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
868 struct ath10k_ce_pipe
*ce_diag
;
869 /* Host buffer address in CE space */
871 dma_addr_t ce_data_base
= 0;
872 void *data_buf
= NULL
;
875 spin_lock_bh(&ar_pci
->ce_lock
);
877 ce_diag
= ar_pci
->ce_diag
;
880 * Allocate a temporary bounce buffer to hold caller's data
881 * to be DMA'ed from Target. This guarantees
882 * 1) 4-byte alignment
883 * 2) Buffer in DMA-able space
885 orig_nbytes
= nbytes
;
886 data_buf
= (unsigned char *)dma_alloc_coherent(ar
->dev
,
895 memset(data_buf
, 0, orig_nbytes
);
897 remaining_bytes
= orig_nbytes
;
898 ce_data
= ce_data_base
;
899 while (remaining_bytes
) {
900 nbytes
= min_t(unsigned int, remaining_bytes
,
901 DIAG_TRANSFER_LIMIT
);
903 ret
= __ath10k_ce_rx_post_buf(ce_diag
, &ce_data
, ce_data
);
907 /* Request CE to send from Target(!) address to Host buffer */
909 * The address supplied by the caller is in the
910 * Target CPU virtual address space.
912 * In order to use this address with the diagnostic CE,
913 * convert it from Target CPU virtual address space
914 * to CE address space
916 address
= ath10k_pci_targ_cpu_to_ce_addr(ar
, address
);
918 ret
= ath10k_ce_send_nolock(ce_diag
, NULL
, (u32
)address
, nbytes
, 0,
924 while (ath10k_ce_completed_send_next_nolock(ce_diag
,
927 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
934 while (ath10k_ce_completed_recv_next_nolock(ce_diag
,
940 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
946 if (nbytes
!= completed_nbytes
) {
951 if (*buf
!= ce_data
) {
956 remaining_bytes
-= nbytes
;
963 memcpy(data
, data_buf
, orig_nbytes
);
965 ath10k_warn(ar
, "failed to read diag value at 0x%x: %d\n",
969 dma_free_coherent(ar
->dev
, orig_nbytes
, data_buf
,
972 spin_unlock_bh(&ar_pci
->ce_lock
);
977 static int ath10k_pci_diag_read32(struct ath10k
*ar
, u32 address
, u32
*value
)
982 ret
= ath10k_pci_diag_read_mem(ar
, address
, &val
, sizeof(val
));
983 *value
= __le32_to_cpu(val
);
988 static int __ath10k_pci_diag_read_hi(struct ath10k
*ar
, void *dest
,
994 host_addr
= host_interest_item_address(src
);
996 ret
= ath10k_pci_diag_read32(ar
, host_addr
, &addr
);
998 ath10k_warn(ar
, "failed to get memcpy hi address for firmware address %d: %d\n",
1003 ret
= ath10k_pci_diag_read_mem(ar
, addr
, dest
, len
);
1005 ath10k_warn(ar
, "failed to memcpy firmware memory from %d (%d B): %d\n",
1013 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1014 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1016 int ath10k_pci_diag_write_mem(struct ath10k
*ar
, u32 address
,
1017 const void *data
, int nbytes
)
1019 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1022 unsigned int completed_nbytes
, orig_nbytes
, remaining_bytes
;
1023 struct ath10k_ce_pipe
*ce_diag
;
1024 void *data_buf
= NULL
;
1025 u32 ce_data
; /* Host buffer address in CE space */
1026 dma_addr_t ce_data_base
= 0;
1029 spin_lock_bh(&ar_pci
->ce_lock
);
1031 ce_diag
= ar_pci
->ce_diag
;
1034 * Allocate a temporary bounce buffer to hold caller's data
1035 * to be DMA'ed to Target. This guarantees
1036 * 1) 4-byte alignment
1037 * 2) Buffer in DMA-able space
1039 orig_nbytes
= nbytes
;
1040 data_buf
= (unsigned char *)dma_alloc_coherent(ar
->dev
,
1049 /* Copy caller's data to allocated DMA buf */
1050 memcpy(data_buf
, data
, orig_nbytes
);
1053 * The address supplied by the caller is in the
1054 * Target CPU virtual address space.
1056 * In order to use this address with the diagnostic CE,
1058 * Target CPU virtual address space
1062 address
= ath10k_pci_targ_cpu_to_ce_addr(ar
, address
);
1064 remaining_bytes
= orig_nbytes
;
1065 ce_data
= ce_data_base
;
1066 while (remaining_bytes
) {
1067 /* FIXME: check cast */
1068 nbytes
= min_t(int, remaining_bytes
, DIAG_TRANSFER_LIMIT
);
1070 /* Set up to receive directly into Target(!) address */
1071 ret
= __ath10k_ce_rx_post_buf(ce_diag
, &address
, address
);
1076 * Request CE to send caller-supplied data that
1077 * was copied to bounce buffer to Target(!) address.
1079 ret
= ath10k_ce_send_nolock(ce_diag
, NULL
, (u32
)ce_data
,
1085 while (ath10k_ce_completed_send_next_nolock(ce_diag
,
1089 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
1096 while (ath10k_ce_completed_recv_next_nolock(ce_diag
,
1102 if (i
++ > DIAG_ACCESS_CE_TIMEOUT_MS
) {
1108 if (nbytes
!= completed_nbytes
) {
1113 if (*buf
!= address
) {
1118 remaining_bytes
-= nbytes
;
1125 dma_free_coherent(ar
->dev
, orig_nbytes
, data_buf
,
1130 ath10k_warn(ar
, "failed to write diag value at 0x%x: %d\n",
1133 spin_unlock_bh(&ar_pci
->ce_lock
);
1138 static int ath10k_pci_diag_write32(struct ath10k
*ar
, u32 address
, u32 value
)
1140 __le32 val
= __cpu_to_le32(value
);
1142 return ath10k_pci_diag_write_mem(ar
, address
, &val
, sizeof(val
));
1145 /* Called by lower (CE) layer when a send to Target completes. */
1146 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe
*ce_state
)
1148 struct ath10k
*ar
= ce_state
->ar
;
1149 struct sk_buff_head list
;
1150 struct sk_buff
*skb
;
1152 __skb_queue_head_init(&list
);
1153 while (ath10k_ce_completed_send_next(ce_state
, (void **)&skb
) == 0) {
1154 /* no need to call tx completion for NULL pointers */
1158 __skb_queue_tail(&list
, skb
);
1161 while ((skb
= __skb_dequeue(&list
)))
1162 ath10k_htc_tx_completion_handler(ar
, skb
);
1165 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe
*ce_state
,
1166 void (*callback
)(struct ath10k
*ar
,
1167 struct sk_buff
*skb
))
1169 struct ath10k
*ar
= ce_state
->ar
;
1170 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1171 struct ath10k_pci_pipe
*pipe_info
= &ar_pci
->pipe_info
[ce_state
->id
];
1172 struct sk_buff
*skb
;
1173 struct sk_buff_head list
;
1174 void *transfer_context
;
1175 unsigned int nbytes
, max_nbytes
;
1177 __skb_queue_head_init(&list
);
1178 while (ath10k_ce_completed_recv_next(ce_state
, &transfer_context
,
1180 skb
= transfer_context
;
1181 max_nbytes
= skb
->len
+ skb_tailroom(skb
);
1182 dma_unmap_single(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1183 max_nbytes
, DMA_FROM_DEVICE
);
1185 if (unlikely(max_nbytes
< nbytes
)) {
1186 ath10k_warn(ar
, "rxed more than expected (nbytes %d, max %d)",
1187 nbytes
, max_nbytes
);
1188 dev_kfree_skb_any(skb
);
1192 skb_put(skb
, nbytes
);
1193 __skb_queue_tail(&list
, skb
);
1196 while ((skb
= __skb_dequeue(&list
))) {
1197 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci rx ce pipe %d len %d\n",
1198 ce_state
->id
, skb
->len
);
1199 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci rx: ",
1200 skb
->data
, skb
->len
);
1205 ath10k_pci_rx_post_pipe(pipe_info
);
1208 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe
*ce_state
,
1209 void (*callback
)(struct ath10k
*ar
,
1210 struct sk_buff
*skb
))
1212 struct ath10k
*ar
= ce_state
->ar
;
1213 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1214 struct ath10k_pci_pipe
*pipe_info
= &ar_pci
->pipe_info
[ce_state
->id
];
1215 struct ath10k_ce_pipe
*ce_pipe
= pipe_info
->ce_hdl
;
1216 struct sk_buff
*skb
;
1217 struct sk_buff_head list
;
1218 void *transfer_context
;
1219 unsigned int nbytes
, max_nbytes
, nentries
;
1222 /* No need to aquire ce_lock for CE5, since this is the only place CE5
1223 * is processed other than init and deinit. Before releasing CE5
1224 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1226 __skb_queue_head_init(&list
);
1227 while (ath10k_ce_completed_recv_next_nolock(ce_state
, &transfer_context
,
1229 skb
= transfer_context
;
1230 max_nbytes
= skb
->len
+ skb_tailroom(skb
);
1232 if (unlikely(max_nbytes
< nbytes
)) {
1233 ath10k_warn(ar
, "rxed more than expected (nbytes %d, max %d)",
1234 nbytes
, max_nbytes
);
1238 dma_sync_single_for_cpu(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1239 max_nbytes
, DMA_FROM_DEVICE
);
1240 skb_put(skb
, nbytes
);
1241 __skb_queue_tail(&list
, skb
);
1244 nentries
= skb_queue_len(&list
);
1245 while ((skb
= __skb_dequeue(&list
))) {
1246 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci rx ce pipe %d len %d\n",
1247 ce_state
->id
, skb
->len
);
1248 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci rx: ",
1249 skb
->data
, skb
->len
);
1251 orig_len
= skb
->len
;
1253 skb_push(skb
, orig_len
- skb
->len
);
1254 skb_reset_tail_pointer(skb
);
1257 /*let device gain the buffer again*/
1258 dma_sync_single_for_device(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1259 skb
->len
+ skb_tailroom(skb
),
1262 ath10k_ce_rx_update_write_idx(ce_pipe
, nentries
);
1265 /* Called by lower (CE) layer when data is received from the Target. */
1266 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
)
1268 ath10k_pci_process_rx_cb(ce_state
, ath10k_htc_rx_completion_handler
);
1271 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
)
1273 /* CE4 polling needs to be done whenever CE pipe which transports
1274 * HTT Rx (target->host) is processed.
1276 ath10k_ce_per_engine_service(ce_state
->ar
, 4);
1278 ath10k_pci_process_rx_cb(ce_state
, ath10k_htc_rx_completion_handler
);
1281 /* Called by lower (CE) layer when data is received from the Target.
1282 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1284 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe
*ce_state
)
1286 ath10k_pci_process_rx_cb(ce_state
,
1287 ath10k_htt_rx_pktlog_completion_handler
);
1290 /* Called by lower (CE) layer when a send to HTT Target completes. */
1291 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe
*ce_state
)
1293 struct ath10k
*ar
= ce_state
->ar
;
1294 struct sk_buff
*skb
;
1296 while (ath10k_ce_completed_send_next(ce_state
, (void **)&skb
) == 0) {
1297 /* no need to call tx completion for NULL pointers */
1301 dma_unmap_single(ar
->dev
, ATH10K_SKB_CB(skb
)->paddr
,
1302 skb
->len
, DMA_TO_DEVICE
);
1303 ath10k_htt_hif_tx_complete(ar
, skb
);
1307 static void ath10k_pci_htt_rx_deliver(struct ath10k
*ar
, struct sk_buff
*skb
)
1309 skb_pull(skb
, sizeof(struct ath10k_htc_hdr
));
1310 ath10k_htt_t2h_msg_handler(ar
, skb
);
1313 /* Called by lower (CE) layer when HTT data is received from the Target. */
1314 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe
*ce_state
)
1316 /* CE4 polling needs to be done whenever CE pipe which transports
1317 * HTT Rx (target->host) is processed.
1319 ath10k_ce_per_engine_service(ce_state
->ar
, 4);
1321 ath10k_pci_process_htt_rx_cb(ce_state
, ath10k_pci_htt_rx_deliver
);
1324 int ath10k_pci_hif_tx_sg(struct ath10k
*ar
, u8 pipe_id
,
1325 struct ath10k_hif_sg_item
*items
, int n_items
)
1327 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1328 struct ath10k_pci_pipe
*pci_pipe
= &ar_pci
->pipe_info
[pipe_id
];
1329 struct ath10k_ce_pipe
*ce_pipe
= pci_pipe
->ce_hdl
;
1330 struct ath10k_ce_ring
*src_ring
= ce_pipe
->src_ring
;
1331 unsigned int nentries_mask
;
1332 unsigned int sw_index
;
1333 unsigned int write_index
;
1336 spin_lock_bh(&ar_pci
->ce_lock
);
1338 nentries_mask
= src_ring
->nentries_mask
;
1339 sw_index
= src_ring
->sw_index
;
1340 write_index
= src_ring
->write_index
;
1342 if (unlikely(CE_RING_DELTA(nentries_mask
,
1343 write_index
, sw_index
- 1) < n_items
)) {
1348 for (i
= 0; i
< n_items
- 1; i
++) {
1349 ath10k_dbg(ar
, ATH10K_DBG_PCI
,
1350 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1351 i
, items
[i
].paddr
, items
[i
].len
, n_items
);
1352 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci tx data: ",
1353 items
[i
].vaddr
, items
[i
].len
);
1355 err
= ath10k_ce_send_nolock(ce_pipe
,
1356 items
[i
].transfer_context
,
1359 items
[i
].transfer_id
,
1360 CE_SEND_FLAG_GATHER
);
1365 /* `i` is equal to `n_items -1` after for() */
1367 ath10k_dbg(ar
, ATH10K_DBG_PCI
,
1368 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1369 i
, items
[i
].paddr
, items
[i
].len
, n_items
);
1370 ath10k_dbg_dump(ar
, ATH10K_DBG_PCI_DUMP
, NULL
, "pci tx data: ",
1371 items
[i
].vaddr
, items
[i
].len
);
1373 err
= ath10k_ce_send_nolock(ce_pipe
,
1374 items
[i
].transfer_context
,
1377 items
[i
].transfer_id
,
1382 spin_unlock_bh(&ar_pci
->ce_lock
);
1387 __ath10k_ce_send_revert(ce_pipe
);
1389 spin_unlock_bh(&ar_pci
->ce_lock
);
1393 int ath10k_pci_hif_diag_read(struct ath10k
*ar
, u32 address
, void *buf
,
1396 return ath10k_pci_diag_read_mem(ar
, address
, buf
, buf_len
);
1399 u16
ath10k_pci_hif_get_free_queue_number(struct ath10k
*ar
, u8 pipe
)
1401 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1403 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif get free queue number\n");
1405 return ath10k_ce_num_free_src_entries(ar_pci
->pipe_info
[pipe
].ce_hdl
);
1408 static void ath10k_pci_dump_registers(struct ath10k
*ar
,
1409 struct ath10k_fw_crash_data
*crash_data
)
1411 __le32 reg_dump_values
[REG_DUMP_COUNT_QCA988X
] = {};
1414 lockdep_assert_held(&ar
->data_lock
);
1416 ret
= ath10k_pci_diag_read_hi(ar
, ®_dump_values
[0],
1418 REG_DUMP_COUNT_QCA988X
* sizeof(__le32
));
1420 ath10k_err(ar
, "failed to read firmware dump area: %d\n", ret
);
1424 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X
% 4);
1426 ath10k_err(ar
, "firmware register dump:\n");
1427 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
+= 4)
1428 ath10k_err(ar
, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1430 __le32_to_cpu(reg_dump_values
[i
]),
1431 __le32_to_cpu(reg_dump_values
[i
+ 1]),
1432 __le32_to_cpu(reg_dump_values
[i
+ 2]),
1433 __le32_to_cpu(reg_dump_values
[i
+ 3]));
1438 for (i
= 0; i
< REG_DUMP_COUNT_QCA988X
; i
++)
1439 crash_data
->registers
[i
] = reg_dump_values
[i
];
1442 static void ath10k_pci_fw_crashed_dump(struct ath10k
*ar
)
1444 struct ath10k_fw_crash_data
*crash_data
;
1447 spin_lock_bh(&ar
->data_lock
);
1449 ar
->stats
.fw_crash_counter
++;
1451 crash_data
= ath10k_debug_get_new_fw_crash_data(ar
);
1454 scnprintf(uuid
, sizeof(uuid
), "%pUl", &crash_data
->uuid
);
1456 scnprintf(uuid
, sizeof(uuid
), "n/a");
1458 ath10k_err(ar
, "firmware crashed! (uuid %s)\n", uuid
);
1459 ath10k_print_driver_info(ar
);
1460 ath10k_pci_dump_registers(ar
, crash_data
);
1462 spin_unlock_bh(&ar
->data_lock
);
1464 queue_work(ar
->workqueue
, &ar
->restart_work
);
1467 void ath10k_pci_hif_send_complete_check(struct ath10k
*ar
, u8 pipe
,
1470 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif send complete check\n");
1475 * Decide whether to actually poll for completions, or just
1476 * wait for a later chance.
1477 * If there seem to be plenty of resources left, then just wait
1478 * since checking involves reading a CE register, which is a
1479 * relatively expensive operation.
1481 resources
= ath10k_pci_hif_get_free_queue_number(ar
, pipe
);
1484 * If at least 50% of the total resources are still available,
1485 * don't bother checking again yet.
1487 if (resources
> (host_ce_config_wlan
[pipe
].src_nentries
>> 1))
1490 ath10k_ce_per_engine_service(ar
, pipe
);
1493 void ath10k_pci_kill_tasklet(struct ath10k
*ar
)
1495 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1497 tasklet_kill(&ar_pci
->intr_tq
);
1499 del_timer_sync(&ar_pci
->rx_post_retry
);
1502 int ath10k_pci_hif_map_service_to_pipe(struct ath10k
*ar
, u16 service_id
,
1503 u8
*ul_pipe
, u8
*dl_pipe
)
1505 const struct service_to_pipe
*entry
;
1506 bool ul_set
= false, dl_set
= false;
1509 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif map service\n");
1511 for (i
= 0; i
< ARRAY_SIZE(target_service_to_ce_map_wlan
); i
++) {
1512 entry
= &target_service_to_ce_map_wlan
[i
];
1514 if (__le32_to_cpu(entry
->service_id
) != service_id
)
1517 switch (__le32_to_cpu(entry
->pipedir
)) {
1522 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
1527 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
1533 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
1534 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
1541 if (WARN_ON(!ul_set
|| !dl_set
))
1547 void ath10k_pci_hif_get_default_pipe(struct ath10k
*ar
,
1548 u8
*ul_pipe
, u8
*dl_pipe
)
1550 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci hif get default pipe\n");
1552 (void)ath10k_pci_hif_map_service_to_pipe(ar
,
1553 ATH10K_HTC_SVC_ID_RSVD_CTRL
,
1557 static void ath10k_pci_irq_msi_fw_mask(struct ath10k
*ar
)
1561 switch (ar
->hw_rev
) {
1562 case ATH10K_HW_QCA988X
:
1563 case ATH10K_HW_QCA6174
:
1564 case ATH10K_HW_QCA9377
:
1565 val
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
1567 val
&= ~CORE_CTRL_PCIE_REG_31_MASK
;
1568 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+
1569 CORE_CTRL_ADDRESS
, val
);
1571 case ATH10K_HW_QCA99X0
:
1572 case ATH10K_HW_QCA4019
:
1573 /* TODO: Find appropriate register configuration for QCA99X0
1580 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k
*ar
)
1584 switch (ar
->hw_rev
) {
1585 case ATH10K_HW_QCA988X
:
1586 case ATH10K_HW_QCA6174
:
1587 case ATH10K_HW_QCA9377
:
1588 val
= ath10k_pci_read32(ar
, SOC_CORE_BASE_ADDRESS
+
1590 val
|= CORE_CTRL_PCIE_REG_31_MASK
;
1591 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+
1592 CORE_CTRL_ADDRESS
, val
);
1594 case ATH10K_HW_QCA99X0
:
1595 case ATH10K_HW_QCA4019
:
1596 /* TODO: Find appropriate register configuration for QCA99X0
1597 * to unmask irq/MSI.
1603 static void ath10k_pci_irq_disable(struct ath10k
*ar
)
1605 ath10k_ce_disable_interrupts(ar
);
1606 ath10k_pci_disable_and_clear_legacy_irq(ar
);
1607 ath10k_pci_irq_msi_fw_mask(ar
);
1610 static void ath10k_pci_irq_sync(struct ath10k
*ar
)
1612 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1614 synchronize_irq(ar_pci
->pdev
->irq
);
1617 static void ath10k_pci_irq_enable(struct ath10k
*ar
)
1619 ath10k_ce_enable_interrupts(ar
);
1620 ath10k_pci_enable_legacy_irq(ar
);
1621 ath10k_pci_irq_msi_fw_unmask(ar
);
1624 static int ath10k_pci_hif_start(struct ath10k
*ar
)
1626 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1628 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif start\n");
1630 ath10k_pci_irq_enable(ar
);
1631 ath10k_pci_rx_post(ar
);
1633 pcie_capability_write_word(ar_pci
->pdev
, PCI_EXP_LNKCTL
,
1639 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe
*pci_pipe
)
1642 struct ath10k_ce_pipe
*ce_pipe
;
1643 struct ath10k_ce_ring
*ce_ring
;
1644 struct sk_buff
*skb
;
1647 ar
= pci_pipe
->hif_ce_state
;
1648 ce_pipe
= pci_pipe
->ce_hdl
;
1649 ce_ring
= ce_pipe
->dest_ring
;
1654 if (!pci_pipe
->buf_sz
)
1657 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
1658 skb
= ce_ring
->per_transfer_context
[i
];
1662 ce_ring
->per_transfer_context
[i
] = NULL
;
1664 dma_unmap_single(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
1665 skb
->len
+ skb_tailroom(skb
),
1667 dev_kfree_skb_any(skb
);
1671 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe
*pci_pipe
)
1674 struct ath10k_pci
*ar_pci
;
1675 struct ath10k_ce_pipe
*ce_pipe
;
1676 struct ath10k_ce_ring
*ce_ring
;
1677 struct sk_buff
*skb
;
1680 ar
= pci_pipe
->hif_ce_state
;
1681 ar_pci
= ath10k_pci_priv(ar
);
1682 ce_pipe
= pci_pipe
->ce_hdl
;
1683 ce_ring
= ce_pipe
->src_ring
;
1688 if (!pci_pipe
->buf_sz
)
1691 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
1692 skb
= ce_ring
->per_transfer_context
[i
];
1696 ce_ring
->per_transfer_context
[i
] = NULL
;
1698 ath10k_htc_tx_completion_handler(ar
, skb
);
1703 * Cleanup residual buffers for device shutdown:
1704 * buffers that were enqueued for receive
1705 * buffers that were to be sent
1706 * Note: Buffers that had completed but which were
1707 * not yet processed are on a completion queue. They
1708 * are handled when the completion thread shuts down.
1710 static void ath10k_pci_buffer_cleanup(struct ath10k
*ar
)
1712 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1715 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
1716 struct ath10k_pci_pipe
*pipe_info
;
1718 pipe_info
= &ar_pci
->pipe_info
[pipe_num
];
1719 ath10k_pci_rx_pipe_cleanup(pipe_info
);
1720 ath10k_pci_tx_pipe_cleanup(pipe_info
);
1724 void ath10k_pci_ce_deinit(struct ath10k
*ar
)
1728 for (i
= 0; i
< CE_COUNT
; i
++)
1729 ath10k_ce_deinit_pipe(ar
, i
);
1732 void ath10k_pci_flush(struct ath10k
*ar
)
1734 ath10k_pci_kill_tasklet(ar
);
1735 ath10k_pci_buffer_cleanup(ar
);
1738 static void ath10k_pci_hif_stop(struct ath10k
*ar
)
1740 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1741 unsigned long flags
;
1743 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif stop\n");
1745 /* Most likely the device has HTT Rx ring configured. The only way to
1746 * prevent the device from accessing (and possible corrupting) host
1747 * memory is to reset the chip now.
1749 * There's also no known way of masking MSI interrupts on the device.
1750 * For ranged MSI the CE-related interrupts can be masked. However
1751 * regardless how many MSI interrupts are assigned the first one
1752 * is always used for firmware indications (crashes) and cannot be
1753 * masked. To prevent the device from asserting the interrupt reset it
1754 * before proceeding with cleanup.
1756 ath10k_pci_safe_chip_reset(ar
);
1758 ath10k_pci_irq_disable(ar
);
1759 ath10k_pci_irq_sync(ar
);
1760 ath10k_pci_flush(ar
);
1762 spin_lock_irqsave(&ar_pci
->ps_lock
, flags
);
1763 WARN_ON(ar_pci
->ps_wake_refcount
> 0);
1764 spin_unlock_irqrestore(&ar_pci
->ps_lock
, flags
);
1767 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k
*ar
,
1768 void *req
, u32 req_len
,
1769 void *resp
, u32
*resp_len
)
1771 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1772 struct ath10k_pci_pipe
*pci_tx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_TARG
];
1773 struct ath10k_pci_pipe
*pci_rx
= &ar_pci
->pipe_info
[BMI_CE_NUM_TO_HOST
];
1774 struct ath10k_ce_pipe
*ce_tx
= pci_tx
->ce_hdl
;
1775 struct ath10k_ce_pipe
*ce_rx
= pci_rx
->ce_hdl
;
1776 dma_addr_t req_paddr
= 0;
1777 dma_addr_t resp_paddr
= 0;
1778 struct bmi_xfer xfer
= {};
1779 void *treq
, *tresp
= NULL
;
1784 if (resp
&& !resp_len
)
1787 if (resp
&& resp_len
&& *resp_len
== 0)
1790 treq
= kmemdup(req
, req_len
, GFP_KERNEL
);
1794 req_paddr
= dma_map_single(ar
->dev
, treq
, req_len
, DMA_TO_DEVICE
);
1795 ret
= dma_mapping_error(ar
->dev
, req_paddr
);
1801 if (resp
&& resp_len
) {
1802 tresp
= kzalloc(*resp_len
, GFP_KERNEL
);
1808 resp_paddr
= dma_map_single(ar
->dev
, tresp
, *resp_len
,
1810 ret
= dma_mapping_error(ar
->dev
, resp_paddr
);
1816 xfer
.wait_for_resp
= true;
1819 ath10k_ce_rx_post_buf(ce_rx
, &xfer
, resp_paddr
);
1822 ret
= ath10k_ce_send(ce_tx
, &xfer
, req_paddr
, req_len
, -1, 0);
1826 ret
= ath10k_pci_bmi_wait(ce_tx
, ce_rx
, &xfer
);
1829 unsigned int unused_nbytes
;
1830 unsigned int unused_id
;
1832 ath10k_ce_cancel_send_next(ce_tx
, NULL
, &unused_buffer
,
1833 &unused_nbytes
, &unused_id
);
1835 /* non-zero means we did not time out */
1843 ath10k_ce_revoke_recv_next(ce_rx
, NULL
, &unused_buffer
);
1844 dma_unmap_single(ar
->dev
, resp_paddr
,
1845 *resp_len
, DMA_FROM_DEVICE
);
1848 dma_unmap_single(ar
->dev
, req_paddr
, req_len
, DMA_TO_DEVICE
);
1850 if (ret
== 0 && resp_len
) {
1851 *resp_len
= min(*resp_len
, xfer
.resp_len
);
1852 memcpy(resp
, tresp
, xfer
.resp_len
);
1861 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe
*ce_state
)
1863 struct bmi_xfer
*xfer
;
1865 if (ath10k_ce_completed_send_next(ce_state
, (void **)&xfer
))
1868 xfer
->tx_done
= true;
1871 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe
*ce_state
)
1873 struct ath10k
*ar
= ce_state
->ar
;
1874 struct bmi_xfer
*xfer
;
1875 unsigned int nbytes
;
1877 if (ath10k_ce_completed_recv_next(ce_state
, (void **)&xfer
,
1881 if (WARN_ON_ONCE(!xfer
))
1884 if (!xfer
->wait_for_resp
) {
1885 ath10k_warn(ar
, "unexpected: BMI data received; ignoring\n");
1889 xfer
->resp_len
= nbytes
;
1890 xfer
->rx_done
= true;
1893 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe
*tx_pipe
,
1894 struct ath10k_ce_pipe
*rx_pipe
,
1895 struct bmi_xfer
*xfer
)
1897 unsigned long timeout
= jiffies
+ BMI_COMMUNICATION_TIMEOUT_HZ
;
1899 while (time_before_eq(jiffies
, timeout
)) {
1900 ath10k_pci_bmi_send_done(tx_pipe
);
1901 ath10k_pci_bmi_recv_data(rx_pipe
);
1903 if (xfer
->tx_done
&& (xfer
->rx_done
== xfer
->wait_for_resp
))
1913 * Send an interrupt to the device to wake up the Target CPU
1914 * so it has an opportunity to notice any changed state.
1916 static int ath10k_pci_wake_target_cpu(struct ath10k
*ar
)
1920 addr
= SOC_CORE_BASE_ADDRESS
| CORE_CTRL_ADDRESS
;
1921 val
= ath10k_pci_read32(ar
, addr
);
1922 val
|= CORE_CTRL_CPU_INTR_MASK
;
1923 ath10k_pci_write32(ar
, addr
, val
);
1928 static int ath10k_pci_get_num_banks(struct ath10k
*ar
)
1930 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1932 switch (ar_pci
->pdev
->device
) {
1933 case QCA988X_2_0_DEVICE_ID
:
1934 case QCA99X0_2_0_DEVICE_ID
:
1936 case QCA6164_2_1_DEVICE_ID
:
1937 case QCA6174_2_1_DEVICE_ID
:
1938 switch (MS(ar
->chip_id
, SOC_CHIP_ID_REV
)) {
1939 case QCA6174_HW_1_0_CHIP_ID_REV
:
1940 case QCA6174_HW_1_1_CHIP_ID_REV
:
1941 case QCA6174_HW_2_1_CHIP_ID_REV
:
1942 case QCA6174_HW_2_2_CHIP_ID_REV
:
1944 case QCA6174_HW_1_3_CHIP_ID_REV
:
1946 case QCA6174_HW_3_0_CHIP_ID_REV
:
1947 case QCA6174_HW_3_1_CHIP_ID_REV
:
1948 case QCA6174_HW_3_2_CHIP_ID_REV
:
1952 case QCA9377_1_0_DEVICE_ID
:
1956 ath10k_warn(ar
, "unknown number of banks, assuming 1\n");
1960 static int ath10k_bus_get_num_banks(struct ath10k
*ar
)
1962 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
1964 return ar_pci
->bus_ops
->get_num_banks(ar
);
1967 int ath10k_pci_init_config(struct ath10k
*ar
)
1969 u32 interconnect_targ_addr
;
1970 u32 pcie_state_targ_addr
= 0;
1971 u32 pipe_cfg_targ_addr
= 0;
1972 u32 svc_to_pipe_map
= 0;
1973 u32 pcie_config_flags
= 0;
1975 u32 ealloc_targ_addr
;
1977 u32 flag2_targ_addr
;
1980 /* Download to Target the CE Config and the service-to-CE map */
1981 interconnect_targ_addr
=
1982 host_interest_item_address(HI_ITEM(hi_interconnect_state
));
1984 /* Supply Target-side CE configuration */
1985 ret
= ath10k_pci_diag_read32(ar
, interconnect_targ_addr
,
1986 &pcie_state_targ_addr
);
1988 ath10k_err(ar
, "Failed to get pcie state addr: %d\n", ret
);
1992 if (pcie_state_targ_addr
== 0) {
1994 ath10k_err(ar
, "Invalid pcie state addr\n");
1998 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
1999 offsetof(struct pcie_state
,
2001 &pipe_cfg_targ_addr
);
2003 ath10k_err(ar
, "Failed to get pipe cfg addr: %d\n", ret
);
2007 if (pipe_cfg_targ_addr
== 0) {
2009 ath10k_err(ar
, "Invalid pipe cfg addr\n");
2013 ret
= ath10k_pci_diag_write_mem(ar
, pipe_cfg_targ_addr
,
2014 target_ce_config_wlan
,
2015 sizeof(struct ce_pipe_config
) *
2016 NUM_TARGET_CE_CONFIG_WLAN
);
2019 ath10k_err(ar
, "Failed to write pipe cfg: %d\n", ret
);
2023 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
2024 offsetof(struct pcie_state
,
2028 ath10k_err(ar
, "Failed to get svc/pipe map: %d\n", ret
);
2032 if (svc_to_pipe_map
== 0) {
2034 ath10k_err(ar
, "Invalid svc_to_pipe map\n");
2038 ret
= ath10k_pci_diag_write_mem(ar
, svc_to_pipe_map
,
2039 target_service_to_ce_map_wlan
,
2040 sizeof(target_service_to_ce_map_wlan
));
2042 ath10k_err(ar
, "Failed to write svc/pipe map: %d\n", ret
);
2046 ret
= ath10k_pci_diag_read32(ar
, (pcie_state_targ_addr
+
2047 offsetof(struct pcie_state
,
2049 &pcie_config_flags
);
2051 ath10k_err(ar
, "Failed to get pcie config_flags: %d\n", ret
);
2055 pcie_config_flags
&= ~PCIE_CONFIG_FLAG_ENABLE_L1
;
2057 ret
= ath10k_pci_diag_write32(ar
, (pcie_state_targ_addr
+
2058 offsetof(struct pcie_state
,
2062 ath10k_err(ar
, "Failed to write pcie config_flags: %d\n", ret
);
2066 /* configure early allocation */
2067 ealloc_targ_addr
= host_interest_item_address(HI_ITEM(hi_early_alloc
));
2069 ret
= ath10k_pci_diag_read32(ar
, ealloc_targ_addr
, &ealloc_value
);
2071 ath10k_err(ar
, "Faile to get early alloc val: %d\n", ret
);
2075 /* first bank is switched to IRAM */
2076 ealloc_value
|= ((HI_EARLY_ALLOC_MAGIC
<< HI_EARLY_ALLOC_MAGIC_SHIFT
) &
2077 HI_EARLY_ALLOC_MAGIC_MASK
);
2078 ealloc_value
|= ((ath10k_bus_get_num_banks(ar
) <<
2079 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT
) &
2080 HI_EARLY_ALLOC_IRAM_BANKS_MASK
);
2082 ret
= ath10k_pci_diag_write32(ar
, ealloc_targ_addr
, ealloc_value
);
2084 ath10k_err(ar
, "Failed to set early alloc val: %d\n", ret
);
2088 /* Tell Target to proceed with initialization */
2089 flag2_targ_addr
= host_interest_item_address(HI_ITEM(hi_option_flag2
));
2091 ret
= ath10k_pci_diag_read32(ar
, flag2_targ_addr
, &flag2_value
);
2093 ath10k_err(ar
, "Failed to get option val: %d\n", ret
);
2097 flag2_value
|= HI_OPTION_EARLY_CFG_DONE
;
2099 ret
= ath10k_pci_diag_write32(ar
, flag2_targ_addr
, flag2_value
);
2101 ath10k_err(ar
, "Failed to set option val: %d\n", ret
);
2108 static void ath10k_pci_override_ce_config(struct ath10k
*ar
)
2110 struct ce_attr
*attr
;
2111 struct ce_pipe_config
*config
;
2113 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2114 * since it is currently used for other feature.
2117 /* Override Host's Copy Engine 5 configuration */
2118 attr
= &host_ce_config_wlan
[5];
2119 attr
->src_sz_max
= 0;
2120 attr
->dest_nentries
= 0;
2122 /* Override Target firmware's Copy Engine configuration */
2123 config
= &target_ce_config_wlan
[5];
2124 config
->pipedir
= __cpu_to_le32(PIPEDIR_OUT
);
2125 config
->nbytes_max
= __cpu_to_le32(2048);
2127 /* Map from service/endpoint to Copy Engine */
2128 target_service_to_ce_map_wlan
[15].pipenum
= __cpu_to_le32(1);
2131 int ath10k_pci_alloc_pipes(struct ath10k
*ar
)
2133 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2134 struct ath10k_pci_pipe
*pipe
;
2137 for (i
= 0; i
< CE_COUNT
; i
++) {
2138 pipe
= &ar_pci
->pipe_info
[i
];
2139 pipe
->ce_hdl
= &ar_pci
->ce_states
[i
];
2141 pipe
->hif_ce_state
= ar
;
2143 ret
= ath10k_ce_alloc_pipe(ar
, i
, &host_ce_config_wlan
[i
]);
2145 ath10k_err(ar
, "failed to allocate copy engine pipe %d: %d\n",
2150 /* Last CE is Diagnostic Window */
2151 if (i
== CE_DIAG_PIPE
) {
2152 ar_pci
->ce_diag
= pipe
->ce_hdl
;
2156 pipe
->buf_sz
= (size_t)(host_ce_config_wlan
[i
].src_sz_max
);
2162 void ath10k_pci_free_pipes(struct ath10k
*ar
)
2166 for (i
= 0; i
< CE_COUNT
; i
++)
2167 ath10k_ce_free_pipe(ar
, i
);
2170 int ath10k_pci_init_pipes(struct ath10k
*ar
)
2174 for (i
= 0; i
< CE_COUNT
; i
++) {
2175 ret
= ath10k_ce_init_pipe(ar
, i
, &host_ce_config_wlan
[i
]);
2177 ath10k_err(ar
, "failed to initialize copy engine pipe %d: %d\n",
2186 static bool ath10k_pci_has_fw_crashed(struct ath10k
*ar
)
2188 return ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
) &
2189 FW_IND_EVENT_PENDING
;
2192 static void ath10k_pci_fw_crashed_clear(struct ath10k
*ar
)
2196 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
2197 val
&= ~FW_IND_EVENT_PENDING
;
2198 ath10k_pci_write32(ar
, FW_INDICATOR_ADDRESS
, val
);
2201 /* this function effectively clears target memory controller assert line */
2202 static void ath10k_pci_warm_reset_si0(struct ath10k
*ar
)
2206 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
2207 ath10k_pci_soc_write32(ar
, SOC_RESET_CONTROL_ADDRESS
,
2208 val
| SOC_RESET_CONTROL_SI0_RST_MASK
);
2209 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
2213 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
2214 ath10k_pci_soc_write32(ar
, SOC_RESET_CONTROL_ADDRESS
,
2215 val
& ~SOC_RESET_CONTROL_SI0_RST_MASK
);
2216 val
= ath10k_pci_soc_read32(ar
, SOC_RESET_CONTROL_ADDRESS
);
2221 static void ath10k_pci_warm_reset_cpu(struct ath10k
*ar
)
2225 ath10k_pci_write32(ar
, FW_INDICATOR_ADDRESS
, 0);
2227 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
2228 SOC_RESET_CONTROL_ADDRESS
);
2229 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
2230 val
| SOC_RESET_CONTROL_CPU_WARM_RST_MASK
);
2233 static void ath10k_pci_warm_reset_ce(struct ath10k
*ar
)
2237 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
2238 SOC_RESET_CONTROL_ADDRESS
);
2240 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
2241 val
| SOC_RESET_CONTROL_CE_RST_MASK
);
2243 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+ SOC_RESET_CONTROL_ADDRESS
,
2244 val
& ~SOC_RESET_CONTROL_CE_RST_MASK
);
2247 static void ath10k_pci_warm_reset_clear_lf(struct ath10k
*ar
)
2251 val
= ath10k_pci_read32(ar
, RTC_SOC_BASE_ADDRESS
+
2252 SOC_LF_TIMER_CONTROL0_ADDRESS
);
2253 ath10k_pci_write32(ar
, RTC_SOC_BASE_ADDRESS
+
2254 SOC_LF_TIMER_CONTROL0_ADDRESS
,
2255 val
& ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK
);
2258 static int ath10k_pci_warm_reset(struct ath10k
*ar
)
2262 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot warm reset\n");
2264 spin_lock_bh(&ar
->data_lock
);
2265 ar
->stats
.fw_warm_reset_counter
++;
2266 spin_unlock_bh(&ar
->data_lock
);
2268 ath10k_pci_irq_disable(ar
);
2270 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2271 * were to access copy engine while host performs copy engine reset
2272 * then it is possible for the device to confuse pci-e controller to
2273 * the point of bringing host system to a complete stop (i.e. hang).
2275 ath10k_pci_warm_reset_si0(ar
);
2276 ath10k_pci_warm_reset_cpu(ar
);
2277 ath10k_pci_init_pipes(ar
);
2278 ath10k_pci_wait_for_target_init(ar
);
2280 ath10k_pci_warm_reset_clear_lf(ar
);
2281 ath10k_pci_warm_reset_ce(ar
);
2282 ath10k_pci_warm_reset_cpu(ar
);
2283 ath10k_pci_init_pipes(ar
);
2285 ret
= ath10k_pci_wait_for_target_init(ar
);
2287 ath10k_warn(ar
, "failed to wait for target init: %d\n", ret
);
2291 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot warm reset complete\n");
2296 static int ath10k_pci_safe_chip_reset(struct ath10k
*ar
)
2298 if (QCA_REV_988X(ar
) || QCA_REV_6174(ar
)) {
2299 return ath10k_pci_warm_reset(ar
);
2300 } else if (QCA_REV_99X0(ar
)) {
2301 ath10k_pci_irq_disable(ar
);
2302 return ath10k_pci_qca99x0_chip_reset(ar
);
2308 static int ath10k_pci_qca988x_chip_reset(struct ath10k
*ar
)
2313 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot 988x chip reset\n");
2315 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2316 * It is thus preferred to use warm reset which is safer but may not be
2317 * able to recover the device from all possible fail scenarios.
2319 * Warm reset doesn't always work on first try so attempt it a few
2320 * times before giving up.
2322 for (i
= 0; i
< ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
; i
++) {
2323 ret
= ath10k_pci_warm_reset(ar
);
2325 ath10k_warn(ar
, "failed to warm reset attempt %d of %d: %d\n",
2326 i
+ 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
,
2331 /* FIXME: Sometimes copy engine doesn't recover after warm
2332 * reset. In most cases this needs cold reset. In some of these
2333 * cases the device is in such a state that a cold reset may
2336 * Reading any host interest register via copy engine is
2337 * sufficient to verify if device is capable of booting
2340 ret
= ath10k_pci_init_pipes(ar
);
2342 ath10k_warn(ar
, "failed to init copy engine: %d\n",
2347 ret
= ath10k_pci_diag_read32(ar
, QCA988X_HOST_INTEREST_ADDRESS
,
2350 ath10k_warn(ar
, "failed to poke copy engine: %d\n",
2355 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot chip reset complete (warm)\n");
2359 if (ath10k_pci_reset_mode
== ATH10K_PCI_RESET_WARM_ONLY
) {
2360 ath10k_warn(ar
, "refusing cold reset as requested\n");
2364 ret
= ath10k_pci_cold_reset(ar
);
2366 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
2370 ret
= ath10k_pci_wait_for_target_init(ar
);
2372 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
2377 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca988x chip reset complete (cold)\n");
2382 static int ath10k_pci_qca6174_chip_reset(struct ath10k
*ar
)
2386 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca6174 chip reset\n");
2388 /* FIXME: QCA6174 requires cold + warm reset to work. */
2390 ret
= ath10k_pci_cold_reset(ar
);
2392 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
2396 ret
= ath10k_pci_wait_for_target_init(ar
);
2398 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
2403 ret
= ath10k_pci_warm_reset(ar
);
2405 ath10k_warn(ar
, "failed to warm reset: %d\n", ret
);
2409 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca6174 chip reset complete (cold)\n");
2414 static int ath10k_pci_qca99x0_chip_reset(struct ath10k
*ar
)
2418 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca99x0 chip reset\n");
2420 ret
= ath10k_pci_cold_reset(ar
);
2422 ath10k_warn(ar
, "failed to cold reset: %d\n", ret
);
2426 ret
= ath10k_pci_wait_for_target_init(ar
);
2428 ath10k_warn(ar
, "failed to wait for target after cold reset: %d\n",
2433 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot qca99x0 chip reset complete (cold)\n");
2438 static int ath10k_pci_chip_reset(struct ath10k
*ar
)
2440 if (QCA_REV_988X(ar
))
2441 return ath10k_pci_qca988x_chip_reset(ar
);
2442 else if (QCA_REV_6174(ar
))
2443 return ath10k_pci_qca6174_chip_reset(ar
);
2444 else if (QCA_REV_9377(ar
))
2445 return ath10k_pci_qca6174_chip_reset(ar
);
2446 else if (QCA_REV_99X0(ar
))
2447 return ath10k_pci_qca99x0_chip_reset(ar
);
2452 static int ath10k_pci_hif_power_up(struct ath10k
*ar
)
2454 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2457 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power up\n");
2459 pcie_capability_read_word(ar_pci
->pdev
, PCI_EXP_LNKCTL
,
2461 pcie_capability_write_word(ar_pci
->pdev
, PCI_EXP_LNKCTL
,
2462 ar_pci
->link_ctl
& ~PCI_EXP_LNKCTL_ASPMC
);
2465 * Bring the target up cleanly.
2467 * The target may be in an undefined state with an AUX-powered Target
2468 * and a Host in WoW mode. If the Host crashes, loses power, or is
2469 * restarted (without unloading the driver) then the Target is left
2470 * (aux) powered and running. On a subsequent driver load, the Target
2471 * is in an unexpected state. We try to catch that here in order to
2472 * reset the Target and retry the probe.
2474 ret
= ath10k_pci_chip_reset(ar
);
2476 if (ath10k_pci_has_fw_crashed(ar
)) {
2477 ath10k_warn(ar
, "firmware crashed during chip reset\n");
2478 ath10k_pci_fw_crashed_clear(ar
);
2479 ath10k_pci_fw_crashed_dump(ar
);
2482 ath10k_err(ar
, "failed to reset chip: %d\n", ret
);
2486 ret
= ath10k_pci_init_pipes(ar
);
2488 ath10k_err(ar
, "failed to initialize CE: %d\n", ret
);
2492 ret
= ath10k_pci_init_config(ar
);
2494 ath10k_err(ar
, "failed to setup init config: %d\n", ret
);
2498 ret
= ath10k_pci_wake_target_cpu(ar
);
2500 ath10k_err(ar
, "could not wake up target CPU: %d\n", ret
);
2507 ath10k_pci_ce_deinit(ar
);
2513 void ath10k_pci_hif_power_down(struct ath10k
*ar
)
2515 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power down\n");
2517 /* Currently hif_power_up performs effectively a reset and hif_stop
2518 * resets the chip as well so there's no point in resetting here.
2524 static int ath10k_pci_hif_suspend(struct ath10k
*ar
)
2526 /* The grace timer can still be counting down and ar->ps_awake be true.
2527 * It is known that the device may be asleep after resuming regardless
2528 * of the SoC powersave state before suspending. Hence make sure the
2529 * device is asleep before proceeding.
2531 ath10k_pci_sleep_sync(ar
);
2536 static int ath10k_pci_hif_resume(struct ath10k
*ar
)
2538 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2539 struct pci_dev
*pdev
= ar_pci
->pdev
;
2543 ret
= ath10k_pci_force_wake(ar
);
2545 ath10k_err(ar
, "failed to wake up target: %d\n", ret
);
2549 /* Suspend/Resume resets the PCI configuration space, so we have to
2550 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2551 * from interfering with C3 CPU state. pci_restore_state won't help
2552 * here since it only restores the first 64 bytes pci config header.
2554 pci_read_config_dword(pdev
, 0x40, &val
);
2555 if ((val
& 0x0000ff00) != 0)
2556 pci_write_config_dword(pdev
, 0x40, val
& 0xffff00ff);
2562 static const struct ath10k_hif_ops ath10k_pci_hif_ops
= {
2563 .tx_sg
= ath10k_pci_hif_tx_sg
,
2564 .diag_read
= ath10k_pci_hif_diag_read
,
2565 .diag_write
= ath10k_pci_diag_write_mem
,
2566 .exchange_bmi_msg
= ath10k_pci_hif_exchange_bmi_msg
,
2567 .start
= ath10k_pci_hif_start
,
2568 .stop
= ath10k_pci_hif_stop
,
2569 .map_service_to_pipe
= ath10k_pci_hif_map_service_to_pipe
,
2570 .get_default_pipe
= ath10k_pci_hif_get_default_pipe
,
2571 .send_complete_check
= ath10k_pci_hif_send_complete_check
,
2572 .get_free_queue_number
= ath10k_pci_hif_get_free_queue_number
,
2573 .power_up
= ath10k_pci_hif_power_up
,
2574 .power_down
= ath10k_pci_hif_power_down
,
2575 .read32
= ath10k_pci_read32
,
2576 .write32
= ath10k_pci_write32
,
2578 .suspend
= ath10k_pci_hif_suspend
,
2579 .resume
= ath10k_pci_hif_resume
,
2584 * Top-level interrupt handler for all PCI interrupts from a Target.
2585 * When a block of MSI interrupts is allocated, this top-level handler
2586 * is not used; instead, we directly call the correct sub-handler.
2588 static irqreturn_t
ath10k_pci_interrupt_handler(int irq
, void *arg
)
2590 struct ath10k
*ar
= arg
;
2591 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2594 ret
= ath10k_pci_force_wake(ar
);
2596 ath10k_warn(ar
, "failed to wake device up on irq: %d\n", ret
);
2600 if (ar_pci
->oper_irq_mode
== ATH10K_PCI_IRQ_LEGACY
) {
2601 if (!ath10k_pci_irq_pending(ar
))
2604 ath10k_pci_disable_and_clear_legacy_irq(ar
);
2607 tasklet_schedule(&ar_pci
->intr_tq
);
2612 static void ath10k_pci_tasklet(unsigned long data
)
2614 struct ath10k
*ar
= (struct ath10k
*)data
;
2615 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2617 if (ath10k_pci_has_fw_crashed(ar
)) {
2618 ath10k_pci_irq_disable(ar
);
2619 ath10k_pci_fw_crashed_clear(ar
);
2620 ath10k_pci_fw_crashed_dump(ar
);
2624 ath10k_ce_per_engine_service_any(ar
);
2626 /* Re-enable legacy irq that was disabled in the irq handler */
2627 if (ar_pci
->oper_irq_mode
== ATH10K_PCI_IRQ_LEGACY
)
2628 ath10k_pci_enable_legacy_irq(ar
);
2631 static int ath10k_pci_request_irq_msi(struct ath10k
*ar
)
2633 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2636 ret
= request_irq(ar_pci
->pdev
->irq
,
2637 ath10k_pci_interrupt_handler
,
2638 IRQF_SHARED
, "ath10k_pci", ar
);
2640 ath10k_warn(ar
, "failed to request MSI irq %d: %d\n",
2641 ar_pci
->pdev
->irq
, ret
);
2648 static int ath10k_pci_request_irq_legacy(struct ath10k
*ar
)
2650 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2653 ret
= request_irq(ar_pci
->pdev
->irq
,
2654 ath10k_pci_interrupt_handler
,
2655 IRQF_SHARED
, "ath10k_pci", ar
);
2657 ath10k_warn(ar
, "failed to request legacy irq %d: %d\n",
2658 ar_pci
->pdev
->irq
, ret
);
2665 static int ath10k_pci_request_irq(struct ath10k
*ar
)
2667 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2669 switch (ar_pci
->oper_irq_mode
) {
2670 case ATH10K_PCI_IRQ_LEGACY
:
2671 return ath10k_pci_request_irq_legacy(ar
);
2672 case ATH10K_PCI_IRQ_MSI
:
2673 return ath10k_pci_request_irq_msi(ar
);
2679 static void ath10k_pci_free_irq(struct ath10k
*ar
)
2681 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2683 free_irq(ar_pci
->pdev
->irq
, ar
);
2686 void ath10k_pci_init_irq_tasklets(struct ath10k
*ar
)
2688 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2690 tasklet_init(&ar_pci
->intr_tq
, ath10k_pci_tasklet
, (unsigned long)ar
);
2693 static int ath10k_pci_init_irq(struct ath10k
*ar
)
2695 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2698 ath10k_pci_init_irq_tasklets(ar
);
2700 if (ath10k_pci_irq_mode
!= ATH10K_PCI_IRQ_AUTO
)
2701 ath10k_info(ar
, "limiting irq mode to: %d\n",
2702 ath10k_pci_irq_mode
);
2705 if (ath10k_pci_irq_mode
!= ATH10K_PCI_IRQ_LEGACY
) {
2706 ar_pci
->oper_irq_mode
= ATH10K_PCI_IRQ_MSI
;
2707 ret
= pci_enable_msi(ar_pci
->pdev
);
2716 * A potential race occurs here: The CORE_BASE write
2717 * depends on target correctly decoding AXI address but
2718 * host won't know when target writes BAR to CORE_CTRL.
2719 * This write might get lost if target has NOT written BAR.
2720 * For now, fix the race by repeating the write in below
2721 * synchronization checking. */
2722 ar_pci
->oper_irq_mode
= ATH10K_PCI_IRQ_LEGACY
;
2724 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
2725 PCIE_INTR_FIRMWARE_MASK
| PCIE_INTR_CE_MASK_ALL
);
2730 static void ath10k_pci_deinit_irq_legacy(struct ath10k
*ar
)
2732 ath10k_pci_write32(ar
, SOC_CORE_BASE_ADDRESS
+ PCIE_INTR_ENABLE_ADDRESS
,
2736 static int ath10k_pci_deinit_irq(struct ath10k
*ar
)
2738 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2740 switch (ar_pci
->oper_irq_mode
) {
2741 case ATH10K_PCI_IRQ_LEGACY
:
2742 ath10k_pci_deinit_irq_legacy(ar
);
2745 pci_disable_msi(ar_pci
->pdev
);
2752 int ath10k_pci_wait_for_target_init(struct ath10k
*ar
)
2754 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2755 unsigned long timeout
;
2758 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot waiting target to initialise\n");
2760 timeout
= jiffies
+ msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT
);
2763 val
= ath10k_pci_read32(ar
, FW_INDICATOR_ADDRESS
);
2765 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot target indicator %x\n",
2768 /* target should never return this */
2769 if (val
== 0xffffffff)
2772 /* the device has crashed so don't bother trying anymore */
2773 if (val
& FW_IND_EVENT_PENDING
)
2776 if (val
& FW_IND_INITIALIZED
)
2779 if (ar_pci
->oper_irq_mode
== ATH10K_PCI_IRQ_LEGACY
)
2780 /* Fix potential race by repeating CORE_BASE writes */
2781 ath10k_pci_enable_legacy_irq(ar
);
2784 } while (time_before(jiffies
, timeout
));
2786 ath10k_pci_disable_and_clear_legacy_irq(ar
);
2787 ath10k_pci_irq_msi_fw_mask(ar
);
2789 if (val
== 0xffffffff) {
2790 ath10k_err(ar
, "failed to read device register, device is gone\n");
2794 if (val
& FW_IND_EVENT_PENDING
) {
2795 ath10k_warn(ar
, "device has crashed during init\n");
2799 if (!(val
& FW_IND_INITIALIZED
)) {
2800 ath10k_err(ar
, "failed to receive initialized event from target: %08x\n",
2805 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot target initialised\n");
2809 static int ath10k_pci_cold_reset(struct ath10k
*ar
)
2813 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot cold reset\n");
2815 spin_lock_bh(&ar
->data_lock
);
2817 ar
->stats
.fw_cold_reset_counter
++;
2819 spin_unlock_bh(&ar
->data_lock
);
2821 /* Put Target, including PCIe, into RESET. */
2822 val
= ath10k_pci_reg_read32(ar
, SOC_GLOBAL_RESET_ADDRESS
);
2824 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
2826 /* After writing into SOC_GLOBAL_RESET to put device into
2827 * reset and pulling out of reset pcie may not be stable
2828 * for any immediate pcie register access and cause bus error,
2829 * add delay before any pcie access request to fix this issue.
2833 /* Pull Target, including PCIe, out of RESET. */
2835 ath10k_pci_reg_write32(ar
, SOC_GLOBAL_RESET_ADDRESS
, val
);
2839 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot cold reset complete\n");
2844 static int ath10k_pci_claim(struct ath10k
*ar
)
2846 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2847 struct pci_dev
*pdev
= ar_pci
->pdev
;
2850 pci_set_drvdata(pdev
, ar
);
2852 ret
= pci_enable_device(pdev
);
2854 ath10k_err(ar
, "failed to enable pci device: %d\n", ret
);
2858 ret
= pci_request_region(pdev
, BAR_NUM
, "ath");
2860 ath10k_err(ar
, "failed to request region BAR%d: %d\n", BAR_NUM
,
2865 /* Target expects 32 bit DMA. Enforce it. */
2866 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2868 ath10k_err(ar
, "failed to set dma mask to 32-bit: %d\n", ret
);
2872 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2874 ath10k_err(ar
, "failed to set consistent dma mask to 32-bit: %d\n",
2879 pci_set_master(pdev
);
2881 /* Arrange for access to Target SoC registers. */
2882 ar_pci
->mem_len
= pci_resource_len(pdev
, BAR_NUM
);
2883 ar_pci
->mem
= pci_iomap(pdev
, BAR_NUM
, 0);
2885 ath10k_err(ar
, "failed to iomap BAR%d\n", BAR_NUM
);
2890 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot pci_mem 0x%p\n", ar_pci
->mem
);
2894 pci_clear_master(pdev
);
2897 pci_release_region(pdev
, BAR_NUM
);
2900 pci_disable_device(pdev
);
2905 static void ath10k_pci_release(struct ath10k
*ar
)
2907 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2908 struct pci_dev
*pdev
= ar_pci
->pdev
;
2910 pci_iounmap(pdev
, ar_pci
->mem
);
2911 pci_release_region(pdev
, BAR_NUM
);
2912 pci_clear_master(pdev
);
2913 pci_disable_device(pdev
);
2916 static bool ath10k_pci_chip_is_supported(u32 dev_id
, u32 chip_id
)
2918 const struct ath10k_pci_supp_chip
*supp_chip
;
2920 u32 rev_id
= MS(chip_id
, SOC_CHIP_ID_REV
);
2922 for (i
= 0; i
< ARRAY_SIZE(ath10k_pci_supp_chips
); i
++) {
2923 supp_chip
= &ath10k_pci_supp_chips
[i
];
2925 if (supp_chip
->dev_id
== dev_id
&&
2926 supp_chip
->rev_id
== rev_id
)
2933 int ath10k_pci_setup_resource(struct ath10k
*ar
)
2935 struct ath10k_pci
*ar_pci
= ath10k_pci_priv(ar
);
2938 spin_lock_init(&ar_pci
->ce_lock
);
2939 spin_lock_init(&ar_pci
->ps_lock
);
2941 setup_timer(&ar_pci
->rx_post_retry
, ath10k_pci_rx_replenish_retry
,
2944 if (QCA_REV_6174(ar
))
2945 ath10k_pci_override_ce_config(ar
);
2947 ret
= ath10k_pci_alloc_pipes(ar
);
2949 ath10k_err(ar
, "failed to allocate copy engine pipes: %d\n",
2957 void ath10k_pci_release_resource(struct ath10k
*ar
)
2959 ath10k_pci_kill_tasklet(ar
);
2960 ath10k_pci_ce_deinit(ar
);
2961 ath10k_pci_free_pipes(ar
);
2964 static const struct ath10k_bus_ops ath10k_pci_bus_ops
= {
2965 .read32
= ath10k_bus_pci_read32
,
2966 .write32
= ath10k_bus_pci_write32
,
2967 .get_num_banks
= ath10k_pci_get_num_banks
,
2970 static int ath10k_pci_probe(struct pci_dev
*pdev
,
2971 const struct pci_device_id
*pci_dev
)
2975 struct ath10k_pci
*ar_pci
;
2976 enum ath10k_hw_rev hw_rev
;
2980 switch (pci_dev
->device
) {
2981 case QCA988X_2_0_DEVICE_ID
:
2982 hw_rev
= ATH10K_HW_QCA988X
;
2985 case QCA6164_2_1_DEVICE_ID
:
2986 case QCA6174_2_1_DEVICE_ID
:
2987 hw_rev
= ATH10K_HW_QCA6174
;
2990 case QCA99X0_2_0_DEVICE_ID
:
2991 hw_rev
= ATH10K_HW_QCA99X0
;
2994 case QCA9377_1_0_DEVICE_ID
:
2995 hw_rev
= ATH10K_HW_QCA9377
;
3003 ar
= ath10k_core_create(sizeof(*ar_pci
), &pdev
->dev
, ATH10K_BUS_PCI
,
3004 hw_rev
, &ath10k_pci_hif_ops
);
3006 dev_err(&pdev
->dev
, "failed to allocate core\n");
3010 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "pci probe %04x:%04x %04x:%04x\n",
3011 pdev
->vendor
, pdev
->device
,
3012 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
3014 ar_pci
= ath10k_pci_priv(ar
);
3015 ar_pci
->pdev
= pdev
;
3016 ar_pci
->dev
= &pdev
->dev
;
3018 ar
->dev_id
= pci_dev
->device
;
3019 ar_pci
->pci_ps
= pci_ps
;
3020 ar_pci
->bus_ops
= &ath10k_pci_bus_ops
;
3022 ar
->id
.vendor
= pdev
->vendor
;
3023 ar
->id
.device
= pdev
->device
;
3024 ar
->id
.subsystem_vendor
= pdev
->subsystem_vendor
;
3025 ar
->id
.subsystem_device
= pdev
->subsystem_device
;
3027 setup_timer(&ar_pci
->ps_timer
, ath10k_pci_ps_timer
,
3030 ret
= ath10k_pci_setup_resource(ar
);
3032 ath10k_err(ar
, "failed to setup resource: %d\n", ret
);
3033 goto err_core_destroy
;
3036 ret
= ath10k_pci_claim(ar
);
3038 ath10k_err(ar
, "failed to claim device: %d\n", ret
);
3039 goto err_free_pipes
;
3042 ret
= ath10k_pci_force_wake(ar
);
3044 ath10k_warn(ar
, "failed to wake up device : %d\n", ret
);
3048 ath10k_pci_ce_deinit(ar
);
3049 ath10k_pci_irq_disable(ar
);
3051 ret
= ath10k_pci_init_irq(ar
);
3053 ath10k_err(ar
, "failed to init irqs: %d\n", ret
);
3057 ath10k_info(ar
, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3058 ath10k_pci_get_irq_method(ar
), ar_pci
->oper_irq_mode
,
3059 ath10k_pci_irq_mode
, ath10k_pci_reset_mode
);
3061 ret
= ath10k_pci_request_irq(ar
);
3063 ath10k_warn(ar
, "failed to request irqs: %d\n", ret
);
3064 goto err_deinit_irq
;
3067 ret
= ath10k_pci_chip_reset(ar
);
3069 ath10k_err(ar
, "failed to reset chip: %d\n", ret
);
3073 chip_id
= ath10k_pci_soc_read32(ar
, SOC_CHIP_ID_ADDRESS
);
3074 if (chip_id
== 0xffffffff) {
3075 ath10k_err(ar
, "failed to get chip id\n");
3079 if (!ath10k_pci_chip_is_supported(pdev
->device
, chip_id
)) {
3080 ath10k_err(ar
, "device %04x with chip_id %08x isn't supported\n",
3081 pdev
->device
, chip_id
);
3085 ret
= ath10k_core_register(ar
, chip_id
);
3087 ath10k_err(ar
, "failed to register driver core: %d\n", ret
);
3094 ath10k_pci_free_irq(ar
);
3095 ath10k_pci_kill_tasklet(ar
);
3098 ath10k_pci_deinit_irq(ar
);
3101 ath10k_pci_sleep_sync(ar
);
3102 ath10k_pci_release(ar
);
3105 ath10k_pci_free_pipes(ar
);
3108 ath10k_core_destroy(ar
);
3113 static void ath10k_pci_remove(struct pci_dev
*pdev
)
3115 struct ath10k
*ar
= pci_get_drvdata(pdev
);
3116 struct ath10k_pci
*ar_pci
;
3118 ath10k_dbg(ar
, ATH10K_DBG_PCI
, "pci remove\n");
3123 ar_pci
= ath10k_pci_priv(ar
);
3128 ath10k_core_unregister(ar
);
3129 ath10k_pci_free_irq(ar
);
3130 ath10k_pci_deinit_irq(ar
);
3131 ath10k_pci_release_resource(ar
);
3132 ath10k_pci_sleep_sync(ar
);
3133 ath10k_pci_release(ar
);
3134 ath10k_core_destroy(ar
);
3137 MODULE_DEVICE_TABLE(pci
, ath10k_pci_id_table
);
3139 static struct pci_driver ath10k_pci_driver
= {
3140 .name
= "ath10k_pci",
3141 .id_table
= ath10k_pci_id_table
,
3142 .probe
= ath10k_pci_probe
,
3143 .remove
= ath10k_pci_remove
,
3146 static int __init
ath10k_pci_init(void)
3150 ret
= pci_register_driver(&ath10k_pci_driver
);
3152 printk(KERN_ERR
"failed to register ath10k pci driver: %d\n",
3155 ret
= ath10k_ahb_init();
3157 printk(KERN_ERR
"ahb init failed: %d\n", ret
);
3161 module_init(ath10k_pci_init
);
3163 static void __exit
ath10k_pci_exit(void)
3165 pci_unregister_driver(&ath10k_pci_driver
);
3169 module_exit(ath10k_pci_exit
);
3171 MODULE_AUTHOR("Qualcomm Atheros");
3172 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
3173 MODULE_LICENSE("Dual BSD/GPL");
3175 /* QCA988x 2.0 firmware files */
3176 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API2_FILE
);
3177 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API3_FILE
);
3178 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API4_FILE
);
3179 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3180 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" QCA988X_HW_2_0_BOARD_DATA_FILE
);
3181 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR
"/" ATH10K_BOARD_API2_FILE
);
3183 /* QCA6174 2.1 firmware files */
3184 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" ATH10K_FW_API4_FILE
);
3185 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3186 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" QCA6174_HW_2_1_BOARD_DATA_FILE
);
3187 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR
"/" ATH10K_BOARD_API2_FILE
);
3189 /* QCA6174 3.1 firmware files */
3190 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" ATH10K_FW_API4_FILE
);
3191 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3192 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" QCA6174_HW_3_0_BOARD_DATA_FILE
);
3193 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR
"/" ATH10K_BOARD_API2_FILE
);
3195 /* QCA9377 1.0 firmware files */
3196 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR
"/" ATH10K_FW_API5_FILE
);
3197 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR
"/" QCA9377_HW_1_0_BOARD_DATA_FILE
);