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ath10k: don't show MSI registration warnings
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath10k / pci.c
1 /*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22
23 #include "core.h"
24 #include "debug.h"
25
26 #include "targaddrs.h"
27 #include "bmi.h"
28
29 #include "hif.h"
30 #include "htc.h"
31
32 #include "ce.h"
33 #include "pci.h"
34
35 static unsigned int ath10k_target_ps;
36 module_param(ath10k_target_ps, uint, 0644);
37 MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
38
39 #define QCA988X_2_0_DEVICE_ID (0x003c)
40
41 static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
42 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
43 {0}
44 };
45
46 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
47 u32 *data);
48
49 static void ath10k_pci_process_ce(struct ath10k *ar);
50 static int ath10k_pci_post_rx(struct ath10k *ar);
51 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
52 int num);
53 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
54 static void ath10k_pci_stop_ce(struct ath10k *ar);
55 static int ath10k_pci_device_reset(struct ath10k *ar);
56 static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
57 static int ath10k_pci_start_intr(struct ath10k *ar);
58 static void ath10k_pci_stop_intr(struct ath10k *ar);
59
60 static const struct ce_attr host_ce_config_wlan[] = {
61 /* CE0: host->target HTC control and raw streams */
62 {
63 .flags = CE_ATTR_FLAGS,
64 .src_nentries = 16,
65 .src_sz_max = 256,
66 .dest_nentries = 0,
67 },
68
69 /* CE1: target->host HTT + HTC control */
70 {
71 .flags = CE_ATTR_FLAGS,
72 .src_nentries = 0,
73 .src_sz_max = 512,
74 .dest_nentries = 512,
75 },
76
77 /* CE2: target->host WMI */
78 {
79 .flags = CE_ATTR_FLAGS,
80 .src_nentries = 0,
81 .src_sz_max = 2048,
82 .dest_nentries = 32,
83 },
84
85 /* CE3: host->target WMI */
86 {
87 .flags = CE_ATTR_FLAGS,
88 .src_nentries = 32,
89 .src_sz_max = 2048,
90 .dest_nentries = 0,
91 },
92
93 /* CE4: host->target HTT */
94 {
95 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
96 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
97 .src_sz_max = 256,
98 .dest_nentries = 0,
99 },
100
101 /* CE5: unused */
102 {
103 .flags = CE_ATTR_FLAGS,
104 .src_nentries = 0,
105 .src_sz_max = 0,
106 .dest_nentries = 0,
107 },
108
109 /* CE6: target autonomous hif_memcpy */
110 {
111 .flags = CE_ATTR_FLAGS,
112 .src_nentries = 0,
113 .src_sz_max = 0,
114 .dest_nentries = 0,
115 },
116
117 /* CE7: ce_diag, the Diagnostic Window */
118 {
119 .flags = CE_ATTR_FLAGS,
120 .src_nentries = 2,
121 .src_sz_max = DIAG_TRANSFER_LIMIT,
122 .dest_nentries = 2,
123 },
124 };
125
126 /* Target firmware's Copy Engine configuration. */
127 static const struct ce_pipe_config target_ce_config_wlan[] = {
128 /* CE0: host->target HTC control and raw streams */
129 {
130 .pipenum = 0,
131 .pipedir = PIPEDIR_OUT,
132 .nentries = 32,
133 .nbytes_max = 256,
134 .flags = CE_ATTR_FLAGS,
135 .reserved = 0,
136 },
137
138 /* CE1: target->host HTT + HTC control */
139 {
140 .pipenum = 1,
141 .pipedir = PIPEDIR_IN,
142 .nentries = 32,
143 .nbytes_max = 512,
144 .flags = CE_ATTR_FLAGS,
145 .reserved = 0,
146 },
147
148 /* CE2: target->host WMI */
149 {
150 .pipenum = 2,
151 .pipedir = PIPEDIR_IN,
152 .nentries = 32,
153 .nbytes_max = 2048,
154 .flags = CE_ATTR_FLAGS,
155 .reserved = 0,
156 },
157
158 /* CE3: host->target WMI */
159 {
160 .pipenum = 3,
161 .pipedir = PIPEDIR_OUT,
162 .nentries = 32,
163 .nbytes_max = 2048,
164 .flags = CE_ATTR_FLAGS,
165 .reserved = 0,
166 },
167
168 /* CE4: host->target HTT */
169 {
170 .pipenum = 4,
171 .pipedir = PIPEDIR_OUT,
172 .nentries = 256,
173 .nbytes_max = 256,
174 .flags = CE_ATTR_FLAGS,
175 .reserved = 0,
176 },
177
178 /* NB: 50% of src nentries, since tx has 2 frags */
179
180 /* CE5: unused */
181 {
182 .pipenum = 5,
183 .pipedir = PIPEDIR_OUT,
184 .nentries = 32,
185 .nbytes_max = 2048,
186 .flags = CE_ATTR_FLAGS,
187 .reserved = 0,
188 },
189
190 /* CE6: Reserved for target autonomous hif_memcpy */
191 {
192 .pipenum = 6,
193 .pipedir = PIPEDIR_INOUT,
194 .nentries = 32,
195 .nbytes_max = 4096,
196 .flags = CE_ATTR_FLAGS,
197 .reserved = 0,
198 },
199
200 /* CE7 used only by Host */
201 };
202
203 /*
204 * Diagnostic read/write access is provided for startup/config/debug usage.
205 * Caller must guarantee proper alignment, when applicable, and single user
206 * at any moment.
207 */
208 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
209 int nbytes)
210 {
211 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
212 int ret = 0;
213 u32 buf;
214 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
215 unsigned int id;
216 unsigned int flags;
217 struct ath10k_ce_pipe *ce_diag;
218 /* Host buffer address in CE space */
219 u32 ce_data;
220 dma_addr_t ce_data_base = 0;
221 void *data_buf = NULL;
222 int i;
223
224 /*
225 * This code cannot handle reads to non-memory space. Redirect to the
226 * register read fn but preserve the multi word read capability of
227 * this fn
228 */
229 if (address < DRAM_BASE_ADDRESS) {
230 if (!IS_ALIGNED(address, 4) ||
231 !IS_ALIGNED((unsigned long)data, 4))
232 return -EIO;
233
234 while ((nbytes >= 4) && ((ret = ath10k_pci_diag_read_access(
235 ar, address, (u32 *)data)) == 0)) {
236 nbytes -= sizeof(u32);
237 address += sizeof(u32);
238 data += sizeof(u32);
239 }
240 return ret;
241 }
242
243 ce_diag = ar_pci->ce_diag;
244
245 /*
246 * Allocate a temporary bounce buffer to hold caller's data
247 * to be DMA'ed from Target. This guarantees
248 * 1) 4-byte alignment
249 * 2) Buffer in DMA-able space
250 */
251 orig_nbytes = nbytes;
252 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
253 orig_nbytes,
254 &ce_data_base);
255
256 if (!data_buf) {
257 ret = -ENOMEM;
258 goto done;
259 }
260 memset(data_buf, 0, orig_nbytes);
261
262 remaining_bytes = orig_nbytes;
263 ce_data = ce_data_base;
264 while (remaining_bytes) {
265 nbytes = min_t(unsigned int, remaining_bytes,
266 DIAG_TRANSFER_LIMIT);
267
268 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data);
269 if (ret != 0)
270 goto done;
271
272 /* Request CE to send from Target(!) address to Host buffer */
273 /*
274 * The address supplied by the caller is in the
275 * Target CPU virtual address space.
276 *
277 * In order to use this address with the diagnostic CE,
278 * convert it from Target CPU virtual address space
279 * to CE address space
280 */
281 ath10k_pci_wake(ar);
282 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
283 address);
284 ath10k_pci_sleep(ar);
285
286 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
287 0);
288 if (ret)
289 goto done;
290
291 i = 0;
292 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
293 &completed_nbytes,
294 &id) != 0) {
295 mdelay(1);
296 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
297 ret = -EBUSY;
298 goto done;
299 }
300 }
301
302 if (nbytes != completed_nbytes) {
303 ret = -EIO;
304 goto done;
305 }
306
307 if (buf != (u32) address) {
308 ret = -EIO;
309 goto done;
310 }
311
312 i = 0;
313 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
314 &completed_nbytes,
315 &id, &flags) != 0) {
316 mdelay(1);
317
318 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
319 ret = -EBUSY;
320 goto done;
321 }
322 }
323
324 if (nbytes != completed_nbytes) {
325 ret = -EIO;
326 goto done;
327 }
328
329 if (buf != ce_data) {
330 ret = -EIO;
331 goto done;
332 }
333
334 remaining_bytes -= nbytes;
335 address += nbytes;
336 ce_data += nbytes;
337 }
338
339 done:
340 if (ret == 0) {
341 /* Copy data from allocated DMA buf to caller's buf */
342 WARN_ON_ONCE(orig_nbytes & 3);
343 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) {
344 ((u32 *)data)[i] =
345 __le32_to_cpu(((__le32 *)data_buf)[i]);
346 }
347 } else
348 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n",
349 __func__, address);
350
351 if (data_buf)
352 pci_free_consistent(ar_pci->pdev, orig_nbytes,
353 data_buf, ce_data_base);
354
355 return ret;
356 }
357
358 /* Read 4-byte aligned data from Target memory or register */
359 static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
360 u32 *data)
361 {
362 /* Assume range doesn't cross this boundary */
363 if (address >= DRAM_BASE_ADDRESS)
364 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32));
365
366 ath10k_pci_wake(ar);
367 *data = ath10k_pci_read32(ar, address);
368 ath10k_pci_sleep(ar);
369 return 0;
370 }
371
372 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
373 const void *data, int nbytes)
374 {
375 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
376 int ret = 0;
377 u32 buf;
378 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
379 unsigned int id;
380 unsigned int flags;
381 struct ath10k_ce_pipe *ce_diag;
382 void *data_buf = NULL;
383 u32 ce_data; /* Host buffer address in CE space */
384 dma_addr_t ce_data_base = 0;
385 int i;
386
387 ce_diag = ar_pci->ce_diag;
388
389 /*
390 * Allocate a temporary bounce buffer to hold caller's data
391 * to be DMA'ed to Target. This guarantees
392 * 1) 4-byte alignment
393 * 2) Buffer in DMA-able space
394 */
395 orig_nbytes = nbytes;
396 data_buf = (unsigned char *)pci_alloc_consistent(ar_pci->pdev,
397 orig_nbytes,
398 &ce_data_base);
399 if (!data_buf) {
400 ret = -ENOMEM;
401 goto done;
402 }
403
404 /* Copy caller's data to allocated DMA buf */
405 WARN_ON_ONCE(orig_nbytes & 3);
406 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
407 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
408
409 /*
410 * The address supplied by the caller is in the
411 * Target CPU virtual address space.
412 *
413 * In order to use this address with the diagnostic CE,
414 * convert it from
415 * Target CPU virtual address space
416 * to
417 * CE address space
418 */
419 ath10k_pci_wake(ar);
420 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
421 ath10k_pci_sleep(ar);
422
423 remaining_bytes = orig_nbytes;
424 ce_data = ce_data_base;
425 while (remaining_bytes) {
426 /* FIXME: check cast */
427 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
428
429 /* Set up to receive directly into Target(!) address */
430 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address);
431 if (ret != 0)
432 goto done;
433
434 /*
435 * Request CE to send caller-supplied data that
436 * was copied to bounce buffer to Target(!) address.
437 */
438 ret = ath10k_ce_send(ce_diag, NULL, (u32) ce_data,
439 nbytes, 0, 0);
440 if (ret != 0)
441 goto done;
442
443 i = 0;
444 while (ath10k_ce_completed_send_next(ce_diag, NULL, &buf,
445 &completed_nbytes,
446 &id) != 0) {
447 mdelay(1);
448
449 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
450 ret = -EBUSY;
451 goto done;
452 }
453 }
454
455 if (nbytes != completed_nbytes) {
456 ret = -EIO;
457 goto done;
458 }
459
460 if (buf != ce_data) {
461 ret = -EIO;
462 goto done;
463 }
464
465 i = 0;
466 while (ath10k_ce_completed_recv_next(ce_diag, NULL, &buf,
467 &completed_nbytes,
468 &id, &flags) != 0) {
469 mdelay(1);
470
471 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
472 ret = -EBUSY;
473 goto done;
474 }
475 }
476
477 if (nbytes != completed_nbytes) {
478 ret = -EIO;
479 goto done;
480 }
481
482 if (buf != address) {
483 ret = -EIO;
484 goto done;
485 }
486
487 remaining_bytes -= nbytes;
488 address += nbytes;
489 ce_data += nbytes;
490 }
491
492 done:
493 if (data_buf) {
494 pci_free_consistent(ar_pci->pdev, orig_nbytes, data_buf,
495 ce_data_base);
496 }
497
498 if (ret != 0)
499 ath10k_dbg(ATH10K_DBG_PCI, "%s failure (0x%x)\n", __func__,
500 address);
501
502 return ret;
503 }
504
505 /* Write 4B data to Target memory or register */
506 static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
507 u32 data)
508 {
509 /* Assume range doesn't cross this boundary */
510 if (address >= DRAM_BASE_ADDRESS)
511 return ath10k_pci_diag_write_mem(ar, address, &data,
512 sizeof(u32));
513
514 ath10k_pci_wake(ar);
515 ath10k_pci_write32(ar, address, data);
516 ath10k_pci_sleep(ar);
517 return 0;
518 }
519
520 static bool ath10k_pci_target_is_awake(struct ath10k *ar)
521 {
522 void __iomem *mem = ath10k_pci_priv(ar)->mem;
523 u32 val;
524 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS +
525 RTC_STATE_ADDRESS);
526 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
527 }
528
529 int ath10k_do_pci_wake(struct ath10k *ar)
530 {
531 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
532 void __iomem *pci_addr = ar_pci->mem;
533 int tot_delay = 0;
534 int curr_delay = 5;
535
536 if (atomic_read(&ar_pci->keep_awake_count) == 0) {
537 /* Force AWAKE */
538 iowrite32(PCIE_SOC_WAKE_V_MASK,
539 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
540 PCIE_SOC_WAKE_ADDRESS);
541 }
542 atomic_inc(&ar_pci->keep_awake_count);
543
544 if (ar_pci->verified_awake)
545 return 0;
546
547 for (;;) {
548 if (ath10k_pci_target_is_awake(ar)) {
549 ar_pci->verified_awake = true;
550 return 0;
551 }
552
553 if (tot_delay > PCIE_WAKE_TIMEOUT) {
554 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
555 PCIE_WAKE_TIMEOUT,
556 atomic_read(&ar_pci->keep_awake_count));
557 return -ETIMEDOUT;
558 }
559
560 udelay(curr_delay);
561 tot_delay += curr_delay;
562
563 if (curr_delay < 50)
564 curr_delay += 5;
565 }
566 }
567
568 void ath10k_do_pci_sleep(struct ath10k *ar)
569 {
570 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
571 void __iomem *pci_addr = ar_pci->mem;
572
573 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) {
574 /* Allow sleep */
575 ar_pci->verified_awake = false;
576 iowrite32(PCIE_SOC_WAKE_RESET,
577 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
578 PCIE_SOC_WAKE_ADDRESS);
579 }
580 }
581
582 /*
583 * FIXME: Handle OOM properly.
584 */
585 static inline
586 struct ath10k_pci_compl *get_free_compl(struct ath10k_pci_pipe *pipe_info)
587 {
588 struct ath10k_pci_compl *compl = NULL;
589
590 spin_lock_bh(&pipe_info->pipe_lock);
591 if (list_empty(&pipe_info->compl_free)) {
592 ath10k_warn("Completion buffers are full\n");
593 goto exit;
594 }
595 compl = list_first_entry(&pipe_info->compl_free,
596 struct ath10k_pci_compl, list);
597 list_del(&compl->list);
598 exit:
599 spin_unlock_bh(&pipe_info->pipe_lock);
600 return compl;
601 }
602
603 /* Called by lower (CE) layer when a send to Target completes. */
604 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
605 {
606 struct ath10k *ar = ce_state->ar;
607 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
608 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
609 struct ath10k_pci_compl *compl;
610 void *transfer_context;
611 u32 ce_data;
612 unsigned int nbytes;
613 unsigned int transfer_id;
614
615 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
616 &ce_data, &nbytes,
617 &transfer_id) == 0) {
618 compl = get_free_compl(pipe_info);
619 if (!compl)
620 break;
621
622 compl->state = ATH10K_PCI_COMPL_SEND;
623 compl->ce_state = ce_state;
624 compl->pipe_info = pipe_info;
625 compl->skb = transfer_context;
626 compl->nbytes = nbytes;
627 compl->transfer_id = transfer_id;
628 compl->flags = 0;
629
630 /*
631 * Add the completion to the processing queue.
632 */
633 spin_lock_bh(&ar_pci->compl_lock);
634 list_add_tail(&compl->list, &ar_pci->compl_process);
635 spin_unlock_bh(&ar_pci->compl_lock);
636 }
637
638 ath10k_pci_process_ce(ar);
639 }
640
641 /* Called by lower (CE) layer when data is received from the Target. */
642 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
643 {
644 struct ath10k *ar = ce_state->ar;
645 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
646 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
647 struct ath10k_pci_compl *compl;
648 struct sk_buff *skb;
649 void *transfer_context;
650 u32 ce_data;
651 unsigned int nbytes;
652 unsigned int transfer_id;
653 unsigned int flags;
654
655 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
656 &ce_data, &nbytes, &transfer_id,
657 &flags) == 0) {
658 compl = get_free_compl(pipe_info);
659 if (!compl)
660 break;
661
662 compl->state = ATH10K_PCI_COMPL_RECV;
663 compl->ce_state = ce_state;
664 compl->pipe_info = pipe_info;
665 compl->skb = transfer_context;
666 compl->nbytes = nbytes;
667 compl->transfer_id = transfer_id;
668 compl->flags = flags;
669
670 skb = transfer_context;
671 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
672 skb->len + skb_tailroom(skb),
673 DMA_FROM_DEVICE);
674 /*
675 * Add the completion to the processing queue.
676 */
677 spin_lock_bh(&ar_pci->compl_lock);
678 list_add_tail(&compl->list, &ar_pci->compl_process);
679 spin_unlock_bh(&ar_pci->compl_lock);
680 }
681
682 ath10k_pci_process_ce(ar);
683 }
684
685 /* Send the first nbytes bytes of the buffer */
686 static int ath10k_pci_hif_send_head(struct ath10k *ar, u8 pipe_id,
687 unsigned int transfer_id,
688 unsigned int bytes, struct sk_buff *nbuf)
689 {
690 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(nbuf);
691 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
692 struct ath10k_pci_pipe *pipe_info = &(ar_pci->pipe_info[pipe_id]);
693 struct ath10k_ce_pipe *ce_hdl = pipe_info->ce_hdl;
694 unsigned int len;
695 u32 flags = 0;
696 int ret;
697
698 len = min(bytes, nbuf->len);
699 bytes -= len;
700
701 if (len & 3)
702 ath10k_warn("skb not aligned to 4-byte boundary (%d)\n", len);
703
704 ath10k_dbg(ATH10K_DBG_PCI,
705 "pci send data vaddr %p paddr 0x%llx len %d as %d bytes\n",
706 nbuf->data, (unsigned long long) skb_cb->paddr,
707 nbuf->len, len);
708 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
709 "ath10k tx: data: ",
710 nbuf->data, nbuf->len);
711
712 ret = ath10k_ce_send(ce_hdl, nbuf, skb_cb->paddr, len, transfer_id,
713 flags);
714 if (ret)
715 ath10k_warn("failed to send sk_buff to CE: %p\n", nbuf);
716
717 return ret;
718 }
719
720 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
721 {
722 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
723 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
724 }
725
726 static void ath10k_pci_hif_dump_area(struct ath10k *ar)
727 {
728 u32 reg_dump_area = 0;
729 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
730 u32 host_addr;
731 int ret;
732 u32 i;
733
734 ath10k_err("firmware crashed!\n");
735 ath10k_err("hardware name %s version 0x%x\n",
736 ar->hw_params.name, ar->target_version);
737 ath10k_err("firmware version: %u.%u.%u.%u\n", ar->fw_version_major,
738 ar->fw_version_minor, ar->fw_version_release,
739 ar->fw_version_build);
740
741 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state));
742 ret = ath10k_pci_diag_read_mem(ar, host_addr,
743 &reg_dump_area, sizeof(u32));
744 if (ret) {
745 ath10k_err("failed to read FW dump area address: %d\n", ret);
746 return;
747 }
748
749 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
750
751 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
752 &reg_dump_values[0],
753 REG_DUMP_COUNT_QCA988X * sizeof(u32));
754 if (ret != 0) {
755 ath10k_err("failed to read FW dump area: %d\n", ret);
756 return;
757 }
758
759 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
760
761 ath10k_err("target Register Dump\n");
762 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
763 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
764 i,
765 reg_dump_values[i],
766 reg_dump_values[i + 1],
767 reg_dump_values[i + 2],
768 reg_dump_values[i + 3]);
769
770 queue_work(ar->workqueue, &ar->restart_work);
771 }
772
773 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
774 int force)
775 {
776 if (!force) {
777 int resources;
778 /*
779 * Decide whether to actually poll for completions, or just
780 * wait for a later chance.
781 * If there seem to be plenty of resources left, then just wait
782 * since checking involves reading a CE register, which is a
783 * relatively expensive operation.
784 */
785 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
786
787 /*
788 * If at least 50% of the total resources are still available,
789 * don't bother checking again yet.
790 */
791 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
792 return;
793 }
794 ath10k_ce_per_engine_service(ar, pipe);
795 }
796
797 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
798 struct ath10k_hif_cb *callbacks)
799 {
800 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
801
802 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
803
804 memcpy(&ar_pci->msg_callbacks_current, callbacks,
805 sizeof(ar_pci->msg_callbacks_current));
806 }
807
808 static int ath10k_pci_start_ce(struct ath10k *ar)
809 {
810 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
811 struct ath10k_ce_pipe *ce_diag = ar_pci->ce_diag;
812 const struct ce_attr *attr;
813 struct ath10k_pci_pipe *pipe_info;
814 struct ath10k_pci_compl *compl;
815 int i, pipe_num, completions, disable_interrupts;
816
817 spin_lock_init(&ar_pci->compl_lock);
818 INIT_LIST_HEAD(&ar_pci->compl_process);
819
820 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
821 pipe_info = &ar_pci->pipe_info[pipe_num];
822
823 spin_lock_init(&pipe_info->pipe_lock);
824 INIT_LIST_HEAD(&pipe_info->compl_free);
825
826 /* Handle Diagnostic CE specially */
827 if (pipe_info->ce_hdl == ce_diag)
828 continue;
829
830 attr = &host_ce_config_wlan[pipe_num];
831 completions = 0;
832
833 if (attr->src_nentries) {
834 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
835 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
836 ath10k_pci_ce_send_done,
837 disable_interrupts);
838 completions += attr->src_nentries;
839 }
840
841 if (attr->dest_nentries) {
842 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
843 ath10k_pci_ce_recv_data);
844 completions += attr->dest_nentries;
845 }
846
847 if (completions == 0)
848 continue;
849
850 for (i = 0; i < completions; i++) {
851 compl = kmalloc(sizeof(*compl), GFP_KERNEL);
852 if (!compl) {
853 ath10k_warn("No memory for completion state\n");
854 ath10k_pci_stop_ce(ar);
855 return -ENOMEM;
856 }
857
858 compl->state = ATH10K_PCI_COMPL_FREE;
859 list_add_tail(&compl->list, &pipe_info->compl_free);
860 }
861 }
862
863 return 0;
864 }
865
866 static void ath10k_pci_kill_tasklet(struct ath10k *ar)
867 {
868 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
869 int i;
870
871 tasklet_kill(&ar_pci->intr_tq);
872 tasklet_kill(&ar_pci->msi_fw_err);
873
874 for (i = 0; i < CE_COUNT; i++)
875 tasklet_kill(&ar_pci->pipe_info[i].intr);
876 }
877
878 static void ath10k_pci_stop_ce(struct ath10k *ar)
879 {
880 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
881 struct ath10k_pci_compl *compl;
882 struct sk_buff *skb;
883 int ret;
884
885 ret = ath10k_ce_disable_interrupts(ar);
886 if (ret)
887 ath10k_warn("failed to disable CE interrupts: %d\n", ret);
888
889 ath10k_pci_kill_tasklet(ar);
890
891 /* Mark pending completions as aborted, so that upper layers free up
892 * their associated resources */
893 spin_lock_bh(&ar_pci->compl_lock);
894 list_for_each_entry(compl, &ar_pci->compl_process, list) {
895 skb = compl->skb;
896 ATH10K_SKB_CB(skb)->is_aborted = true;
897 }
898 spin_unlock_bh(&ar_pci->compl_lock);
899 }
900
901 static void ath10k_pci_cleanup_ce(struct ath10k *ar)
902 {
903 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
904 struct ath10k_pci_compl *compl, *tmp;
905 struct ath10k_pci_pipe *pipe_info;
906 struct sk_buff *netbuf;
907 int pipe_num;
908
909 /* Free pending completions. */
910 spin_lock_bh(&ar_pci->compl_lock);
911 if (!list_empty(&ar_pci->compl_process))
912 ath10k_warn("pending completions still present! possible memory leaks.\n");
913
914 list_for_each_entry_safe(compl, tmp, &ar_pci->compl_process, list) {
915 list_del(&compl->list);
916 netbuf = compl->skb;
917 dev_kfree_skb_any(netbuf);
918 kfree(compl);
919 }
920 spin_unlock_bh(&ar_pci->compl_lock);
921
922 /* Free unused completions for each pipe. */
923 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
924 pipe_info = &ar_pci->pipe_info[pipe_num];
925
926 spin_lock_bh(&pipe_info->pipe_lock);
927 list_for_each_entry_safe(compl, tmp,
928 &pipe_info->compl_free, list) {
929 list_del(&compl->list);
930 kfree(compl);
931 }
932 spin_unlock_bh(&pipe_info->pipe_lock);
933 }
934 }
935
936 static void ath10k_pci_process_ce(struct ath10k *ar)
937 {
938 struct ath10k_pci *ar_pci = ar->hif.priv;
939 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
940 struct ath10k_pci_compl *compl;
941 struct sk_buff *skb;
942 unsigned int nbytes;
943 int ret, send_done = 0;
944
945 /* Upper layers aren't ready to handle tx/rx completions in parallel so
946 * we must serialize all completion processing. */
947
948 spin_lock_bh(&ar_pci->compl_lock);
949 if (ar_pci->compl_processing) {
950 spin_unlock_bh(&ar_pci->compl_lock);
951 return;
952 }
953 ar_pci->compl_processing = true;
954 spin_unlock_bh(&ar_pci->compl_lock);
955
956 for (;;) {
957 spin_lock_bh(&ar_pci->compl_lock);
958 if (list_empty(&ar_pci->compl_process)) {
959 spin_unlock_bh(&ar_pci->compl_lock);
960 break;
961 }
962 compl = list_first_entry(&ar_pci->compl_process,
963 struct ath10k_pci_compl, list);
964 list_del(&compl->list);
965 spin_unlock_bh(&ar_pci->compl_lock);
966
967 switch (compl->state) {
968 case ATH10K_PCI_COMPL_SEND:
969 cb->tx_completion(ar,
970 compl->skb,
971 compl->transfer_id);
972 send_done = 1;
973 break;
974 case ATH10K_PCI_COMPL_RECV:
975 ret = ath10k_pci_post_rx_pipe(compl->pipe_info, 1);
976 if (ret) {
977 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
978 compl->pipe_info->pipe_num, ret);
979 break;
980 }
981
982 skb = compl->skb;
983 nbytes = compl->nbytes;
984
985 ath10k_dbg(ATH10K_DBG_PCI,
986 "ath10k_pci_ce_recv_data netbuf=%p nbytes=%d\n",
987 skb, nbytes);
988 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL,
989 "ath10k rx: ", skb->data, nbytes);
990
991 if (skb->len + skb_tailroom(skb) >= nbytes) {
992 skb_trim(skb, 0);
993 skb_put(skb, nbytes);
994 cb->rx_completion(ar, skb,
995 compl->pipe_info->pipe_num);
996 } else {
997 ath10k_warn("rxed more than expected (nbytes %d, max %d)",
998 nbytes,
999 skb->len + skb_tailroom(skb));
1000 }
1001 break;
1002 case ATH10K_PCI_COMPL_FREE:
1003 ath10k_warn("free completion cannot be processed\n");
1004 break;
1005 default:
1006 ath10k_warn("invalid completion state (%d)\n",
1007 compl->state);
1008 break;
1009 }
1010
1011 compl->state = ATH10K_PCI_COMPL_FREE;
1012
1013 /*
1014 * Add completion back to the pipe's free list.
1015 */
1016 spin_lock_bh(&compl->pipe_info->pipe_lock);
1017 list_add_tail(&compl->list, &compl->pipe_info->compl_free);
1018 spin_unlock_bh(&compl->pipe_info->pipe_lock);
1019 }
1020
1021 spin_lock_bh(&ar_pci->compl_lock);
1022 ar_pci->compl_processing = false;
1023 spin_unlock_bh(&ar_pci->compl_lock);
1024 }
1025
1026 /* TODO - temporary mapping while we have too few CE's */
1027 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1028 u16 service_id, u8 *ul_pipe,
1029 u8 *dl_pipe, int *ul_is_polled,
1030 int *dl_is_polled)
1031 {
1032 int ret = 0;
1033
1034 /* polling for received messages not supported */
1035 *dl_is_polled = 0;
1036
1037 switch (service_id) {
1038 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1039 /*
1040 * Host->target HTT gets its own pipe, so it can be polled
1041 * while other pipes are interrupt driven.
1042 */
1043 *ul_pipe = 4;
1044 /*
1045 * Use the same target->host pipe for HTC ctrl, HTC raw
1046 * streams, and HTT.
1047 */
1048 *dl_pipe = 1;
1049 break;
1050
1051 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1052 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS:
1053 /*
1054 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
1055 * HTC_CTRL_RSVD_SVC could share the same pipe as the
1056 * WMI services. So, if another CE is needed, change
1057 * this to *ul_pipe = 3, which frees up CE 0.
1058 */
1059 /* *ul_pipe = 3; */
1060 *ul_pipe = 0;
1061 *dl_pipe = 1;
1062 break;
1063
1064 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
1065 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
1066 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
1067 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
1068
1069 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1070 *ul_pipe = 3;
1071 *dl_pipe = 2;
1072 break;
1073
1074 /* pipe 5 unused */
1075 /* pipe 6 reserved */
1076 /* pipe 7 reserved */
1077
1078 default:
1079 ret = -1;
1080 break;
1081 }
1082 *ul_is_polled =
1083 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1084
1085 return ret;
1086 }
1087
1088 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1089 u8 *ul_pipe, u8 *dl_pipe)
1090 {
1091 int ul_is_polled, dl_is_polled;
1092
1093 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1094 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1095 ul_pipe,
1096 dl_pipe,
1097 &ul_is_polled,
1098 &dl_is_polled);
1099 }
1100
1101 static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
1102 int num)
1103 {
1104 struct ath10k *ar = pipe_info->hif_ce_state;
1105 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1106 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl;
1107 struct sk_buff *skb;
1108 dma_addr_t ce_data;
1109 int i, ret = 0;
1110
1111 if (pipe_info->buf_sz == 0)
1112 return 0;
1113
1114 for (i = 0; i < num; i++) {
1115 skb = dev_alloc_skb(pipe_info->buf_sz);
1116 if (!skb) {
1117 ath10k_warn("failed to allocate skbuff for pipe %d\n",
1118 num);
1119 ret = -ENOMEM;
1120 goto err;
1121 }
1122
1123 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1124
1125 ce_data = dma_map_single(ar->dev, skb->data,
1126 skb->len + skb_tailroom(skb),
1127 DMA_FROM_DEVICE);
1128
1129 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1130 ath10k_warn("failed to DMA map sk_buff\n");
1131 dev_kfree_skb_any(skb);
1132 ret = -EIO;
1133 goto err;
1134 }
1135
1136 ATH10K_SKB_CB(skb)->paddr = ce_data;
1137
1138 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1139 pipe_info->buf_sz,
1140 PCI_DMA_FROMDEVICE);
1141
1142 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb,
1143 ce_data);
1144 if (ret) {
1145 ath10k_warn("failed to enqueue to pipe %d: %d\n",
1146 num, ret);
1147 goto err;
1148 }
1149 }
1150
1151 return ret;
1152
1153 err:
1154 ath10k_pci_rx_pipe_cleanup(pipe_info);
1155 return ret;
1156 }
1157
1158 static int ath10k_pci_post_rx(struct ath10k *ar)
1159 {
1160 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1161 struct ath10k_pci_pipe *pipe_info;
1162 const struct ce_attr *attr;
1163 int pipe_num, ret = 0;
1164
1165 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1166 pipe_info = &ar_pci->pipe_info[pipe_num];
1167 attr = &host_ce_config_wlan[pipe_num];
1168
1169 if (attr->dest_nentries == 0)
1170 continue;
1171
1172 ret = ath10k_pci_post_rx_pipe(pipe_info,
1173 attr->dest_nentries - 1);
1174 if (ret) {
1175 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1176 pipe_num, ret);
1177
1178 for (; pipe_num >= 0; pipe_num--) {
1179 pipe_info = &ar_pci->pipe_info[pipe_num];
1180 ath10k_pci_rx_pipe_cleanup(pipe_info);
1181 }
1182 return ret;
1183 }
1184 }
1185
1186 return 0;
1187 }
1188
1189 static int ath10k_pci_hif_start(struct ath10k *ar)
1190 {
1191 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1192 int ret;
1193
1194 ret = ath10k_pci_start_ce(ar);
1195 if (ret) {
1196 ath10k_warn("failed to start CE: %d\n", ret);
1197 return ret;
1198 }
1199
1200 /* Post buffers once to start things off. */
1201 ret = ath10k_pci_post_rx(ar);
1202 if (ret) {
1203 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1204 ret);
1205 return ret;
1206 }
1207
1208 ar_pci->started = 1;
1209 return 0;
1210 }
1211
1212 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1213 {
1214 struct ath10k *ar;
1215 struct ath10k_pci *ar_pci;
1216 struct ath10k_ce_pipe *ce_hdl;
1217 u32 buf_sz;
1218 struct sk_buff *netbuf;
1219 u32 ce_data;
1220
1221 buf_sz = pipe_info->buf_sz;
1222
1223 /* Unused Copy Engine */
1224 if (buf_sz == 0)
1225 return;
1226
1227 ar = pipe_info->hif_ce_state;
1228 ar_pci = ath10k_pci_priv(ar);
1229
1230 if (!ar_pci->started)
1231 return;
1232
1233 ce_hdl = pipe_info->ce_hdl;
1234
1235 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1236 &ce_data) == 0) {
1237 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1238 netbuf->len + skb_tailroom(netbuf),
1239 DMA_FROM_DEVICE);
1240 dev_kfree_skb_any(netbuf);
1241 }
1242 }
1243
1244 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1245 {
1246 struct ath10k *ar;
1247 struct ath10k_pci *ar_pci;
1248 struct ath10k_ce_pipe *ce_hdl;
1249 struct sk_buff *netbuf;
1250 u32 ce_data;
1251 unsigned int nbytes;
1252 unsigned int id;
1253 u32 buf_sz;
1254
1255 buf_sz = pipe_info->buf_sz;
1256
1257 /* Unused Copy Engine */
1258 if (buf_sz == 0)
1259 return;
1260
1261 ar = pipe_info->hif_ce_state;
1262 ar_pci = ath10k_pci_priv(ar);
1263
1264 if (!ar_pci->started)
1265 return;
1266
1267 ce_hdl = pipe_info->ce_hdl;
1268
1269 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1270 &ce_data, &nbytes, &id) == 0) {
1271 /*
1272 * Indicate the completion to higer layer to free
1273 * the buffer
1274 */
1275
1276 if (!netbuf) {
1277 ath10k_warn("invalid sk_buff on CE %d - NULL pointer. firmware crashed?\n",
1278 ce_hdl->id);
1279 continue;
1280 }
1281
1282 ATH10K_SKB_CB(netbuf)->is_aborted = true;
1283 ar_pci->msg_callbacks_current.tx_completion(ar,
1284 netbuf,
1285 id);
1286 }
1287 }
1288
1289 /*
1290 * Cleanup residual buffers for device shutdown:
1291 * buffers that were enqueued for receive
1292 * buffers that were to be sent
1293 * Note: Buffers that had completed but which were
1294 * not yet processed are on a completion queue. They
1295 * are handled when the completion thread shuts down.
1296 */
1297 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1298 {
1299 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1300 int pipe_num;
1301
1302 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1303 struct ath10k_pci_pipe *pipe_info;
1304
1305 pipe_info = &ar_pci->pipe_info[pipe_num];
1306 ath10k_pci_rx_pipe_cleanup(pipe_info);
1307 ath10k_pci_tx_pipe_cleanup(pipe_info);
1308 }
1309 }
1310
1311 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1312 {
1313 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1314 struct ath10k_pci_pipe *pipe_info;
1315 int pipe_num;
1316
1317 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1318 pipe_info = &ar_pci->pipe_info[pipe_num];
1319 if (pipe_info->ce_hdl) {
1320 ath10k_ce_deinit(pipe_info->ce_hdl);
1321 pipe_info->ce_hdl = NULL;
1322 pipe_info->buf_sz = 0;
1323 }
1324 }
1325 }
1326
1327 static void ath10k_pci_disable_irqs(struct ath10k *ar)
1328 {
1329 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1330 int i;
1331
1332 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1333 disable_irq(ar_pci->pdev->irq + i);
1334 }
1335
1336 static void ath10k_pci_hif_stop(struct ath10k *ar)
1337 {
1338 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1339
1340 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
1341
1342 /* Irqs are never explicitly re-enabled. They are implicitly re-enabled
1343 * by ath10k_pci_start_intr(). */
1344 ath10k_pci_disable_irqs(ar);
1345
1346 ath10k_pci_stop_ce(ar);
1347
1348 /* At this point, asynchronous threads are stopped, the target should
1349 * not DMA nor interrupt. We process the leftovers and then free
1350 * everything else up. */
1351
1352 ath10k_pci_process_ce(ar);
1353 ath10k_pci_cleanup_ce(ar);
1354 ath10k_pci_buffer_cleanup(ar);
1355
1356 /* Make the sure the device won't access any structures on the host by
1357 * resetting it. The device was fed with PCI CE ringbuffer
1358 * configuration during init. If ringbuffers are freed and the device
1359 * were to access them this could lead to memory corruption on the
1360 * host. */
1361 ath10k_pci_device_reset(ar);
1362
1363 ar_pci->started = 0;
1364 }
1365
1366 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1367 void *req, u32 req_len,
1368 void *resp, u32 *resp_len)
1369 {
1370 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1371 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1372 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1373 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1374 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1375 dma_addr_t req_paddr = 0;
1376 dma_addr_t resp_paddr = 0;
1377 struct bmi_xfer xfer = {};
1378 void *treq, *tresp = NULL;
1379 int ret = 0;
1380
1381 if (resp && !resp_len)
1382 return -EINVAL;
1383
1384 if (resp && resp_len && *resp_len == 0)
1385 return -EINVAL;
1386
1387 treq = kmemdup(req, req_len, GFP_KERNEL);
1388 if (!treq)
1389 return -ENOMEM;
1390
1391 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1392 ret = dma_mapping_error(ar->dev, req_paddr);
1393 if (ret)
1394 goto err_dma;
1395
1396 if (resp && resp_len) {
1397 tresp = kzalloc(*resp_len, GFP_KERNEL);
1398 if (!tresp) {
1399 ret = -ENOMEM;
1400 goto err_req;
1401 }
1402
1403 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1404 DMA_FROM_DEVICE);
1405 ret = dma_mapping_error(ar->dev, resp_paddr);
1406 if (ret)
1407 goto err_req;
1408
1409 xfer.wait_for_resp = true;
1410 xfer.resp_len = 0;
1411
1412 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr);
1413 }
1414
1415 init_completion(&xfer.done);
1416
1417 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1418 if (ret)
1419 goto err_resp;
1420
1421 ret = wait_for_completion_timeout(&xfer.done,
1422 BMI_COMMUNICATION_TIMEOUT_HZ);
1423 if (ret <= 0) {
1424 u32 unused_buffer;
1425 unsigned int unused_nbytes;
1426 unsigned int unused_id;
1427
1428 ret = -ETIMEDOUT;
1429 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1430 &unused_nbytes, &unused_id);
1431 } else {
1432 /* non-zero means we did not time out */
1433 ret = 0;
1434 }
1435
1436 err_resp:
1437 if (resp) {
1438 u32 unused_buffer;
1439
1440 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1441 dma_unmap_single(ar->dev, resp_paddr,
1442 *resp_len, DMA_FROM_DEVICE);
1443 }
1444 err_req:
1445 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1446
1447 if (ret == 0 && resp_len) {
1448 *resp_len = min(*resp_len, xfer.resp_len);
1449 memcpy(resp, tresp, xfer.resp_len);
1450 }
1451 err_dma:
1452 kfree(treq);
1453 kfree(tresp);
1454
1455 return ret;
1456 }
1457
1458 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1459 {
1460 struct bmi_xfer *xfer;
1461 u32 ce_data;
1462 unsigned int nbytes;
1463 unsigned int transfer_id;
1464
1465 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1466 &nbytes, &transfer_id))
1467 return;
1468
1469 if (xfer->wait_for_resp)
1470 return;
1471
1472 complete(&xfer->done);
1473 }
1474
1475 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1476 {
1477 struct bmi_xfer *xfer;
1478 u32 ce_data;
1479 unsigned int nbytes;
1480 unsigned int transfer_id;
1481 unsigned int flags;
1482
1483 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1484 &nbytes, &transfer_id, &flags))
1485 return;
1486
1487 if (!xfer->wait_for_resp) {
1488 ath10k_warn("unexpected: BMI data received; ignoring\n");
1489 return;
1490 }
1491
1492 xfer->resp_len = nbytes;
1493 complete(&xfer->done);
1494 }
1495
1496 /*
1497 * Map from service/endpoint to Copy Engine.
1498 * This table is derived from the CE_PCI TABLE, above.
1499 * It is passed to the Target at startup for use by firmware.
1500 */
1501 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1502 {
1503 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1504 PIPEDIR_OUT, /* out = UL = host -> target */
1505 3,
1506 },
1507 {
1508 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1509 PIPEDIR_IN, /* in = DL = target -> host */
1510 2,
1511 },
1512 {
1513 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1514 PIPEDIR_OUT, /* out = UL = host -> target */
1515 3,
1516 },
1517 {
1518 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1519 PIPEDIR_IN, /* in = DL = target -> host */
1520 2,
1521 },
1522 {
1523 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1524 PIPEDIR_OUT, /* out = UL = host -> target */
1525 3,
1526 },
1527 {
1528 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1529 PIPEDIR_IN, /* in = DL = target -> host */
1530 2,
1531 },
1532 {
1533 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1534 PIPEDIR_OUT, /* out = UL = host -> target */
1535 3,
1536 },
1537 {
1538 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1539 PIPEDIR_IN, /* in = DL = target -> host */
1540 2,
1541 },
1542 {
1543 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1544 PIPEDIR_OUT, /* out = UL = host -> target */
1545 3,
1546 },
1547 {
1548 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1549 PIPEDIR_IN, /* in = DL = target -> host */
1550 2,
1551 },
1552 {
1553 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1554 PIPEDIR_OUT, /* out = UL = host -> target */
1555 0, /* could be moved to 3 (share with WMI) */
1556 },
1557 {
1558 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1559 PIPEDIR_IN, /* in = DL = target -> host */
1560 1,
1561 },
1562 {
1563 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1564 PIPEDIR_OUT, /* out = UL = host -> target */
1565 0,
1566 },
1567 {
1568 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1569 PIPEDIR_IN, /* in = DL = target -> host */
1570 1,
1571 },
1572 {
1573 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1574 PIPEDIR_OUT, /* out = UL = host -> target */
1575 4,
1576 },
1577 {
1578 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1579 PIPEDIR_IN, /* in = DL = target -> host */
1580 1,
1581 },
1582
1583 /* (Additions here) */
1584
1585 { /* Must be last */
1586 0,
1587 0,
1588 0,
1589 },
1590 };
1591
1592 /*
1593 * Send an interrupt to the device to wake up the Target CPU
1594 * so it has an opportunity to notice any changed state.
1595 */
1596 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1597 {
1598 int ret;
1599 u32 core_ctrl;
1600
1601 ret = ath10k_pci_diag_read_access(ar, SOC_CORE_BASE_ADDRESS |
1602 CORE_CTRL_ADDRESS,
1603 &core_ctrl);
1604 if (ret) {
1605 ath10k_warn("failed to read core_ctrl: %d\n", ret);
1606 return ret;
1607 }
1608
1609 /* A_INUM_FIRMWARE interrupt to Target CPU */
1610 core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
1611
1612 ret = ath10k_pci_diag_write_access(ar, SOC_CORE_BASE_ADDRESS |
1613 CORE_CTRL_ADDRESS,
1614 core_ctrl);
1615 if (ret) {
1616 ath10k_warn("failed to set target CPU interrupt mask: %d\n",
1617 ret);
1618 return ret;
1619 }
1620
1621 return 0;
1622 }
1623
1624 static int ath10k_pci_init_config(struct ath10k *ar)
1625 {
1626 u32 interconnect_targ_addr;
1627 u32 pcie_state_targ_addr = 0;
1628 u32 pipe_cfg_targ_addr = 0;
1629 u32 svc_to_pipe_map = 0;
1630 u32 pcie_config_flags = 0;
1631 u32 ealloc_value;
1632 u32 ealloc_targ_addr;
1633 u32 flag2_value;
1634 u32 flag2_targ_addr;
1635 int ret = 0;
1636
1637 /* Download to Target the CE Config and the service-to-CE map */
1638 interconnect_targ_addr =
1639 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1640
1641 /* Supply Target-side CE configuration */
1642 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1643 &pcie_state_targ_addr);
1644 if (ret != 0) {
1645 ath10k_err("Failed to get pcie state addr: %d\n", ret);
1646 return ret;
1647 }
1648
1649 if (pcie_state_targ_addr == 0) {
1650 ret = -EIO;
1651 ath10k_err("Invalid pcie state addr\n");
1652 return ret;
1653 }
1654
1655 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1656 offsetof(struct pcie_state,
1657 pipe_cfg_addr),
1658 &pipe_cfg_targ_addr);
1659 if (ret != 0) {
1660 ath10k_err("Failed to get pipe cfg addr: %d\n", ret);
1661 return ret;
1662 }
1663
1664 if (pipe_cfg_targ_addr == 0) {
1665 ret = -EIO;
1666 ath10k_err("Invalid pipe cfg addr\n");
1667 return ret;
1668 }
1669
1670 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1671 target_ce_config_wlan,
1672 sizeof(target_ce_config_wlan));
1673
1674 if (ret != 0) {
1675 ath10k_err("Failed to write pipe cfg: %d\n", ret);
1676 return ret;
1677 }
1678
1679 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1680 offsetof(struct pcie_state,
1681 svc_to_pipe_map),
1682 &svc_to_pipe_map);
1683 if (ret != 0) {
1684 ath10k_err("Failed to get svc/pipe map: %d\n", ret);
1685 return ret;
1686 }
1687
1688 if (svc_to_pipe_map == 0) {
1689 ret = -EIO;
1690 ath10k_err("Invalid svc_to_pipe map\n");
1691 return ret;
1692 }
1693
1694 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1695 target_service_to_ce_map_wlan,
1696 sizeof(target_service_to_ce_map_wlan));
1697 if (ret != 0) {
1698 ath10k_err("Failed to write svc/pipe map: %d\n", ret);
1699 return ret;
1700 }
1701
1702 ret = ath10k_pci_diag_read_access(ar, pcie_state_targ_addr +
1703 offsetof(struct pcie_state,
1704 config_flags),
1705 &pcie_config_flags);
1706 if (ret != 0) {
1707 ath10k_err("Failed to get pcie config_flags: %d\n", ret);
1708 return ret;
1709 }
1710
1711 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1712
1713 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr +
1714 offsetof(struct pcie_state, config_flags),
1715 &pcie_config_flags,
1716 sizeof(pcie_config_flags));
1717 if (ret != 0) {
1718 ath10k_err("Failed to write pcie config_flags: %d\n", ret);
1719 return ret;
1720 }
1721
1722 /* configure early allocation */
1723 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1724
1725 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1726 if (ret != 0) {
1727 ath10k_err("Faile to get early alloc val: %d\n", ret);
1728 return ret;
1729 }
1730
1731 /* first bank is switched to IRAM */
1732 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1733 HI_EARLY_ALLOC_MAGIC_MASK);
1734 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1735 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1736
1737 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1738 if (ret != 0) {
1739 ath10k_err("Failed to set early alloc val: %d\n", ret);
1740 return ret;
1741 }
1742
1743 /* Tell Target to proceed with initialization */
1744 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1745
1746 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1747 if (ret != 0) {
1748 ath10k_err("Failed to get option val: %d\n", ret);
1749 return ret;
1750 }
1751
1752 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1753
1754 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1755 if (ret != 0) {
1756 ath10k_err("Failed to set option val: %d\n", ret);
1757 return ret;
1758 }
1759
1760 return 0;
1761 }
1762
1763
1764
1765 static int ath10k_pci_ce_init(struct ath10k *ar)
1766 {
1767 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1768 struct ath10k_pci_pipe *pipe_info;
1769 const struct ce_attr *attr;
1770 int pipe_num;
1771
1772 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1773 pipe_info = &ar_pci->pipe_info[pipe_num];
1774 pipe_info->pipe_num = pipe_num;
1775 pipe_info->hif_ce_state = ar;
1776 attr = &host_ce_config_wlan[pipe_num];
1777
1778 pipe_info->ce_hdl = ath10k_ce_init(ar, pipe_num, attr);
1779 if (pipe_info->ce_hdl == NULL) {
1780 ath10k_err("failed to initialize CE for pipe: %d\n",
1781 pipe_num);
1782
1783 /* It is safe to call it here. It checks if ce_hdl is
1784 * valid for each pipe */
1785 ath10k_pci_ce_deinit(ar);
1786 return -1;
1787 }
1788
1789 if (pipe_num == CE_COUNT - 1) {
1790 /*
1791 * Reserve the ultimate CE for
1792 * diagnostic Window support
1793 */
1794 ar_pci->ce_diag = pipe_info->ce_hdl;
1795 continue;
1796 }
1797
1798 pipe_info->buf_sz = (size_t) (attr->src_sz_max);
1799 }
1800
1801 return 0;
1802 }
1803
1804 static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
1805 {
1806 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1807 u32 fw_indicator_address, fw_indicator;
1808
1809 ath10k_pci_wake(ar);
1810
1811 fw_indicator_address = ar_pci->fw_indicator_address;
1812 fw_indicator = ath10k_pci_read32(ar, fw_indicator_address);
1813
1814 if (fw_indicator & FW_IND_EVENT_PENDING) {
1815 /* ACK: clear Target-side pending event */
1816 ath10k_pci_write32(ar, fw_indicator_address,
1817 fw_indicator & ~FW_IND_EVENT_PENDING);
1818
1819 if (ar_pci->started) {
1820 ath10k_pci_hif_dump_area(ar);
1821 } else {
1822 /*
1823 * Probable Target failure before we're prepared
1824 * to handle it. Generally unexpected.
1825 */
1826 ath10k_warn("early firmware event indicated\n");
1827 }
1828 }
1829
1830 ath10k_pci_sleep(ar);
1831 }
1832
1833 static void ath10k_pci_start_bmi(struct ath10k *ar)
1834 {
1835 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1836 struct ath10k_pci_pipe *pipe;
1837
1838 /*
1839 * Initially, establish CE completion handlers for use with BMI.
1840 * These are overwritten with generic handlers after we exit BMI phase.
1841 */
1842 pipe = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1843 ath10k_ce_send_cb_register(pipe->ce_hdl, ath10k_pci_bmi_send_done, 0);
1844
1845 pipe = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1846 ath10k_ce_recv_cb_register(pipe->ce_hdl, ath10k_pci_bmi_recv_data);
1847
1848 ath10k_dbg(ATH10K_DBG_BOOT, "boot start bmi\n");
1849 }
1850
1851 static int ath10k_pci_hif_power_up(struct ath10k *ar)
1852 {
1853 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1854 const char *irq_mode;
1855 int ret;
1856
1857 /*
1858 * Bring the target up cleanly.
1859 *
1860 * The target may be in an undefined state with an AUX-powered Target
1861 * and a Host in WoW mode. If the Host crashes, loses power, or is
1862 * restarted (without unloading the driver) then the Target is left
1863 * (aux) powered and running. On a subsequent driver load, the Target
1864 * is in an unexpected state. We try to catch that here in order to
1865 * reset the Target and retry the probe.
1866 */
1867 ret = ath10k_pci_device_reset(ar);
1868 if (ret) {
1869 ath10k_err("failed to reset target: %d\n", ret);
1870 goto err;
1871 }
1872
1873 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1874 /* Force AWAKE forever */
1875 ath10k_do_pci_wake(ar);
1876
1877 ret = ath10k_pci_ce_init(ar);
1878 if (ret) {
1879 ath10k_err("failed to initialize CE: %d\n", ret);
1880 goto err_ps;
1881 }
1882
1883 ret = ath10k_ce_disable_interrupts(ar);
1884 if (ret) {
1885 ath10k_err("failed to disable CE interrupts: %d\n", ret);
1886 goto err_ce;
1887 }
1888
1889 ret = ath10k_pci_start_intr(ar);
1890 if (ret) {
1891 ath10k_err("failed to start interrupt handling: %d\n", ret);
1892 goto err_ce;
1893 }
1894
1895 ret = ath10k_pci_wait_for_target_init(ar);
1896 if (ret) {
1897 ath10k_err("failed to wait for target to init: %d\n", ret);
1898 goto err_irq;
1899 }
1900
1901 ret = ath10k_ce_enable_err_irq(ar);
1902 if (ret) {
1903 ath10k_err("failed to enable CE error irq: %d\n", ret);
1904 goto err_irq;
1905 }
1906
1907 ret = ath10k_pci_init_config(ar);
1908 if (ret) {
1909 ath10k_err("failed to setup init config: %d\n", ret);
1910 goto err_irq;
1911 }
1912
1913 ret = ath10k_pci_wake_target_cpu(ar);
1914 if (ret) {
1915 ath10k_err("could not wake up target CPU: %d\n", ret);
1916 goto err_irq;
1917 }
1918
1919 ath10k_pci_start_bmi(ar);
1920
1921 if (ar_pci->num_msi_intrs > 1)
1922 irq_mode = "MSI-X";
1923 else if (ar_pci->num_msi_intrs == 1)
1924 irq_mode = "MSI";
1925 else
1926 irq_mode = "legacy";
1927
1928 ath10k_info("pci irq %s\n", irq_mode);
1929
1930 return 0;
1931
1932 err_irq:
1933 ath10k_ce_disable_interrupts(ar);
1934 ath10k_pci_stop_intr(ar);
1935 ath10k_pci_kill_tasklet(ar);
1936 ath10k_pci_device_reset(ar);
1937 err_ce:
1938 ath10k_pci_ce_deinit(ar);
1939 err_ps:
1940 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1941 ath10k_do_pci_sleep(ar);
1942 err:
1943 return ret;
1944 }
1945
1946 static void ath10k_pci_hif_power_down(struct ath10k *ar)
1947 {
1948 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1949
1950 ath10k_pci_stop_intr(ar);
1951 ath10k_pci_device_reset(ar);
1952
1953 ath10k_pci_ce_deinit(ar);
1954 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1955 ath10k_do_pci_sleep(ar);
1956 }
1957
1958 #ifdef CONFIG_PM
1959
1960 #define ATH10K_PCI_PM_CONTROL 0x44
1961
1962 static int ath10k_pci_hif_suspend(struct ath10k *ar)
1963 {
1964 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1965 struct pci_dev *pdev = ar_pci->pdev;
1966 u32 val;
1967
1968 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1969
1970 if ((val & 0x000000ff) != 0x3) {
1971 pci_save_state(pdev);
1972 pci_disable_device(pdev);
1973 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1974 (val & 0xffffff00) | 0x03);
1975 }
1976
1977 return 0;
1978 }
1979
1980 static int ath10k_pci_hif_resume(struct ath10k *ar)
1981 {
1982 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1983 struct pci_dev *pdev = ar_pci->pdev;
1984 u32 val;
1985
1986 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1987
1988 if ((val & 0x000000ff) != 0) {
1989 pci_restore_state(pdev);
1990 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1991 val & 0xffffff00);
1992 /*
1993 * Suspend/Resume resets the PCI configuration space,
1994 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1995 * to keep PCI Tx retries from interfering with C3 CPU state
1996 */
1997 pci_read_config_dword(pdev, 0x40, &val);
1998
1999 if ((val & 0x0000ff00) != 0)
2000 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2001 }
2002
2003 return 0;
2004 }
2005 #endif
2006
2007 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2008 .send_head = ath10k_pci_hif_send_head,
2009 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2010 .start = ath10k_pci_hif_start,
2011 .stop = ath10k_pci_hif_stop,
2012 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2013 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2014 .send_complete_check = ath10k_pci_hif_send_complete_check,
2015 .set_callbacks = ath10k_pci_hif_set_callbacks,
2016 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2017 .power_up = ath10k_pci_hif_power_up,
2018 .power_down = ath10k_pci_hif_power_down,
2019 #ifdef CONFIG_PM
2020 .suspend = ath10k_pci_hif_suspend,
2021 .resume = ath10k_pci_hif_resume,
2022 #endif
2023 };
2024
2025 static void ath10k_pci_ce_tasklet(unsigned long ptr)
2026 {
2027 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2028 struct ath10k_pci *ar_pci = pipe->ar_pci;
2029
2030 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2031 }
2032
2033 static void ath10k_msi_err_tasklet(unsigned long data)
2034 {
2035 struct ath10k *ar = (struct ath10k *)data;
2036
2037 ath10k_pci_fw_interrupt_handler(ar);
2038 }
2039
2040 /*
2041 * Handler for a per-engine interrupt on a PARTICULAR CE.
2042 * This is used in cases where each CE has a private MSI interrupt.
2043 */
2044 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2045 {
2046 struct ath10k *ar = arg;
2047 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2048 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2049
2050 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2051 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id);
2052 return IRQ_HANDLED;
2053 }
2054
2055 /*
2056 * NOTE: We are able to derive ce_id from irq because we
2057 * use a one-to-one mapping for CE's 0..5.
2058 * CE's 6 & 7 do not use interrupts at all.
2059 *
2060 * This mapping must be kept in sync with the mapping
2061 * used by firmware.
2062 */
2063 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2064 return IRQ_HANDLED;
2065 }
2066
2067 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2068 {
2069 struct ath10k *ar = arg;
2070 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2071
2072 tasklet_schedule(&ar_pci->msi_fw_err);
2073 return IRQ_HANDLED;
2074 }
2075
2076 /*
2077 * Top-level interrupt handler for all PCI interrupts from a Target.
2078 * When a block of MSI interrupts is allocated, this top-level handler
2079 * is not used; instead, we directly call the correct sub-handler.
2080 */
2081 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2082 {
2083 struct ath10k *ar = arg;
2084 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2085
2086 if (ar_pci->num_msi_intrs == 0) {
2087 /*
2088 * IMPORTANT: INTR_CLR regiser has to be set after
2089 * INTR_ENABLE is set to 0, otherwise interrupt can not be
2090 * really cleared.
2091 */
2092 iowrite32(0, ar_pci->mem +
2093 (SOC_CORE_BASE_ADDRESS |
2094 PCIE_INTR_ENABLE_ADDRESS));
2095 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2096 PCIE_INTR_CE_MASK_ALL,
2097 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2098 PCIE_INTR_CLR_ADDRESS));
2099 /*
2100 * IMPORTANT: this extra read transaction is required to
2101 * flush the posted write buffer.
2102 */
2103 (void) ioread32(ar_pci->mem +
2104 (SOC_CORE_BASE_ADDRESS |
2105 PCIE_INTR_ENABLE_ADDRESS));
2106 }
2107
2108 tasklet_schedule(&ar_pci->intr_tq);
2109
2110 return IRQ_HANDLED;
2111 }
2112
2113 static void ath10k_pci_tasklet(unsigned long data)
2114 {
2115 struct ath10k *ar = (struct ath10k *)data;
2116 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2117
2118 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2119 ath10k_ce_per_engine_service_any(ar);
2120
2121 if (ar_pci->num_msi_intrs == 0) {
2122 /* Enable Legacy PCI line interrupts */
2123 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2124 PCIE_INTR_CE_MASK_ALL,
2125 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2126 PCIE_INTR_ENABLE_ADDRESS));
2127 /*
2128 * IMPORTANT: this extra read transaction is required to
2129 * flush the posted write buffer
2130 */
2131 (void) ioread32(ar_pci->mem +
2132 (SOC_CORE_BASE_ADDRESS |
2133 PCIE_INTR_ENABLE_ADDRESS));
2134 }
2135 }
2136
2137 static int ath10k_pci_start_intr_msix(struct ath10k *ar, int num)
2138 {
2139 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2140 int ret;
2141 int i;
2142
2143 ret = pci_enable_msi_block(ar_pci->pdev, num);
2144 if (ret)
2145 return ret;
2146
2147 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2148 ath10k_pci_msi_fw_handler,
2149 IRQF_SHARED, "ath10k_pci", ar);
2150 if (ret) {
2151 ath10k_warn("request_irq(%d) failed %d\n",
2152 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2153
2154 pci_disable_msi(ar_pci->pdev);
2155 return ret;
2156 }
2157
2158 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2159 ret = request_irq(ar_pci->pdev->irq + i,
2160 ath10k_pci_per_engine_handler,
2161 IRQF_SHARED, "ath10k_pci", ar);
2162 if (ret) {
2163 ath10k_warn("request_irq(%d) failed %d\n",
2164 ar_pci->pdev->irq + i, ret);
2165
2166 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2167 free_irq(ar_pci->pdev->irq + i, ar);
2168
2169 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2170 pci_disable_msi(ar_pci->pdev);
2171 return ret;
2172 }
2173 }
2174
2175 ath10k_dbg(ATH10K_DBG_BOOT,
2176 "MSI-X interrupt handling (%d intrs)\n", num);
2177 return 0;
2178 }
2179
2180 static int ath10k_pci_start_intr_msi(struct ath10k *ar)
2181 {
2182 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2183 int ret;
2184
2185 ret = pci_enable_msi(ar_pci->pdev);
2186 if (ret < 0)
2187 return ret;
2188
2189 ret = request_irq(ar_pci->pdev->irq,
2190 ath10k_pci_interrupt_handler,
2191 IRQF_SHARED, "ath10k_pci", ar);
2192 if (ret < 0) {
2193 pci_disable_msi(ar_pci->pdev);
2194 return ret;
2195 }
2196
2197 ath10k_dbg(ATH10K_DBG_BOOT, "MSI interrupt handling\n");
2198 return 0;
2199 }
2200
2201 static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
2202 {
2203 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2204 int ret;
2205
2206 ret = request_irq(ar_pci->pdev->irq,
2207 ath10k_pci_interrupt_handler,
2208 IRQF_SHARED, "ath10k_pci", ar);
2209 if (ret < 0)
2210 return ret;
2211
2212 ret = ath10k_pci_wake(ar);
2213 if (ret) {
2214 free_irq(ar_pci->pdev->irq, ar);
2215 ath10k_err("failed to wake up target: %d\n", ret);
2216 return ret;
2217 }
2218
2219 /*
2220 * A potential race occurs here: The CORE_BASE write
2221 * depends on target correctly decoding AXI address but
2222 * host won't know when target writes BAR to CORE_CTRL.
2223 * This write might get lost if target has NOT written BAR.
2224 * For now, fix the race by repeating the write in below
2225 * synchronization checking.
2226 */
2227 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2228 PCIE_INTR_CE_MASK_ALL,
2229 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2230 PCIE_INTR_ENABLE_ADDRESS));
2231
2232 ath10k_pci_sleep(ar);
2233 ath10k_dbg(ATH10K_DBG_BOOT, "legacy interrupt handling\n");
2234 return 0;
2235 }
2236
2237 static int ath10k_pci_start_intr(struct ath10k *ar)
2238 {
2239 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2240 int num = MSI_NUM_REQUEST;
2241 int ret;
2242 int i;
2243
2244 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long) ar);
2245 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2246 (unsigned long) ar);
2247
2248 for (i = 0; i < CE_COUNT; i++) {
2249 ar_pci->pipe_info[i].ar_pci = ar_pci;
2250 tasklet_init(&ar_pci->pipe_info[i].intr,
2251 ath10k_pci_ce_tasklet,
2252 (unsigned long)&ar_pci->pipe_info[i]);
2253 }
2254
2255 if (!test_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features))
2256 num = 1;
2257
2258 if (num > 1) {
2259 ret = ath10k_pci_start_intr_msix(ar, num);
2260 if (ret == 0)
2261 goto exit;
2262
2263 ath10k_dbg(ATH10K_DBG_BOOT,
2264 "MSI-X didn't succeed (%d), trying MSI\n", ret);
2265 num = 1;
2266 }
2267
2268 if (num == 1) {
2269 ret = ath10k_pci_start_intr_msi(ar);
2270 if (ret == 0)
2271 goto exit;
2272
2273 ath10k_dbg(ATH10K_DBG_BOOT,
2274 "MSI didn't succeed (%d), trying legacy INTR\n",
2275 ret);
2276 num = 0;
2277 }
2278
2279 ret = ath10k_pci_start_intr_legacy(ar);
2280 if (ret) {
2281 ath10k_warn("Failed to start legacy interrupts: %d\n", ret);
2282 return ret;
2283 }
2284
2285 exit:
2286 ar_pci->num_msi_intrs = num;
2287 return ret;
2288 }
2289
2290 static void ath10k_pci_stop_intr(struct ath10k *ar)
2291 {
2292 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2293 int i;
2294
2295 /* There's at least one interrupt irregardless whether its legacy INTR
2296 * or MSI or MSI-X */
2297 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2298 free_irq(ar_pci->pdev->irq + i, ar);
2299
2300 if (ar_pci->num_msi_intrs > 0)
2301 pci_disable_msi(ar_pci->pdev);
2302 }
2303
2304 static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2305 {
2306 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2307 int wait_limit = 300; /* 3 sec */
2308 int ret;
2309
2310 ret = ath10k_pci_wake(ar);
2311 if (ret) {
2312 ath10k_err("failed to wake up target: %d\n", ret);
2313 return ret;
2314 }
2315
2316 while (wait_limit-- &&
2317 !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
2318 FW_IND_INITIALIZED)) {
2319 if (ar_pci->num_msi_intrs == 0)
2320 /* Fix potential race by repeating CORE_BASE writes */
2321 iowrite32(PCIE_INTR_FIRMWARE_MASK |
2322 PCIE_INTR_CE_MASK_ALL,
2323 ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
2324 PCIE_INTR_ENABLE_ADDRESS));
2325 mdelay(10);
2326 }
2327
2328 if (wait_limit < 0) {
2329 ath10k_err("target stalled\n");
2330 ret = -EIO;
2331 goto out;
2332 }
2333
2334 out:
2335 ath10k_pci_sleep(ar);
2336 return ret;
2337 }
2338
2339 static int ath10k_pci_device_reset(struct ath10k *ar)
2340 {
2341 int i, ret;
2342 u32 val;
2343
2344 ret = ath10k_do_pci_wake(ar);
2345 if (ret) {
2346 ath10k_err("failed to wake up target: %d\n",
2347 ret);
2348 return ret;
2349 }
2350
2351 /* Put Target, including PCIe, into RESET. */
2352 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2353 val |= 1;
2354 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2355
2356 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2357 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2358 RTC_STATE_COLD_RESET_MASK)
2359 break;
2360 msleep(1);
2361 }
2362
2363 /* Pull Target, including PCIe, out of RESET. */
2364 val &= ~1;
2365 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2366
2367 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2368 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2369 RTC_STATE_COLD_RESET_MASK))
2370 break;
2371 msleep(1);
2372 }
2373
2374 ath10k_do_pci_sleep(ar);
2375 return 0;
2376 }
2377
2378 static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci)
2379 {
2380 int i;
2381
2382 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2383 if (!test_bit(i, ar_pci->features))
2384 continue;
2385
2386 switch (i) {
2387 case ATH10K_PCI_FEATURE_MSI_X:
2388 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
2389 break;
2390 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
2391 ath10k_dbg(ATH10K_DBG_BOOT, "QCA98XX SoC power save enabled\n");
2392 break;
2393 }
2394 }
2395 }
2396
2397 static int ath10k_pci_probe(struct pci_dev *pdev,
2398 const struct pci_device_id *pci_dev)
2399 {
2400 void __iomem *mem;
2401 int ret = 0;
2402 struct ath10k *ar;
2403 struct ath10k_pci *ar_pci;
2404 u32 lcr_val, chip_id;
2405
2406 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2407
2408 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2409 if (ar_pci == NULL)
2410 return -ENOMEM;
2411
2412 ar_pci->pdev = pdev;
2413 ar_pci->dev = &pdev->dev;
2414
2415 switch (pci_dev->device) {
2416 case QCA988X_2_0_DEVICE_ID:
2417 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2418 break;
2419 default:
2420 ret = -ENODEV;
2421 ath10k_err("Unkown device ID: %d\n", pci_dev->device);
2422 goto err_ar_pci;
2423 }
2424
2425 if (ath10k_target_ps)
2426 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2427
2428 ath10k_pci_dump_features(ar_pci);
2429
2430 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
2431 if (!ar) {
2432 ath10k_err("failed to create driver core\n");
2433 ret = -EINVAL;
2434 goto err_ar_pci;
2435 }
2436
2437 ar_pci->ar = ar;
2438 ar_pci->fw_indicator_address = FW_INDICATOR_ADDRESS;
2439 atomic_set(&ar_pci->keep_awake_count, 0);
2440
2441 pci_set_drvdata(pdev, ar);
2442
2443 /*
2444 * Without any knowledge of the Host, the Target may have been reset or
2445 * power cycled and its Config Space may no longer reflect the PCI
2446 * address space that was assigned earlier by the PCI infrastructure.
2447 * Refresh it now.
2448 */
2449 ret = pci_assign_resource(pdev, BAR_NUM);
2450 if (ret) {
2451 ath10k_err("failed to assign PCI space: %d\n", ret);
2452 goto err_ar;
2453 }
2454
2455 ret = pci_enable_device(pdev);
2456 if (ret) {
2457 ath10k_err("failed to enable PCI device: %d\n", ret);
2458 goto err_ar;
2459 }
2460
2461 /* Request MMIO resources */
2462 ret = pci_request_region(pdev, BAR_NUM, "ath");
2463 if (ret) {
2464 ath10k_err("failed to request MMIO region: %d\n", ret);
2465 goto err_device;
2466 }
2467
2468 /*
2469 * Target structures have a limit of 32 bit DMA pointers.
2470 * DMA pointers can be wider than 32 bits by default on some systems.
2471 */
2472 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2473 if (ret) {
2474 ath10k_err("failed to set DMA mask to 32-bit: %d\n", ret);
2475 goto err_region;
2476 }
2477
2478 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2479 if (ret) {
2480 ath10k_err("failed to set consistent DMA mask to 32-bit\n");
2481 goto err_region;
2482 }
2483
2484 /* Set bus master bit in PCI_COMMAND to enable DMA */
2485 pci_set_master(pdev);
2486
2487 /*
2488 * Temporary FIX: disable ASPM
2489 * Will be removed after the OTP is programmed
2490 */
2491 pci_read_config_dword(pdev, 0x80, &lcr_val);
2492 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2493
2494 /* Arrange for access to Target SoC registers. */
2495 mem = pci_iomap(pdev, BAR_NUM, 0);
2496 if (!mem) {
2497 ath10k_err("failed to perform IOMAP for BAR%d\n", BAR_NUM);
2498 ret = -EIO;
2499 goto err_master;
2500 }
2501
2502 ar_pci->mem = mem;
2503
2504 spin_lock_init(&ar_pci->ce_lock);
2505
2506 ret = ath10k_do_pci_wake(ar);
2507 if (ret) {
2508 ath10k_err("Failed to get chip id: %d\n", ret);
2509 goto err_iomap;
2510 }
2511
2512 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
2513
2514 ath10k_do_pci_sleep(ar);
2515
2516 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2517
2518 ret = ath10k_core_register(ar, chip_id);
2519 if (ret) {
2520 ath10k_err("failed to register driver core: %d\n", ret);
2521 goto err_iomap;
2522 }
2523
2524 return 0;
2525
2526 err_iomap:
2527 pci_iounmap(pdev, mem);
2528 err_master:
2529 pci_clear_master(pdev);
2530 err_region:
2531 pci_release_region(pdev, BAR_NUM);
2532 err_device:
2533 pci_disable_device(pdev);
2534 err_ar:
2535 ath10k_core_destroy(ar);
2536 err_ar_pci:
2537 /* call HIF PCI free here */
2538 kfree(ar_pci);
2539
2540 return ret;
2541 }
2542
2543 static void ath10k_pci_remove(struct pci_dev *pdev)
2544 {
2545 struct ath10k *ar = pci_get_drvdata(pdev);
2546 struct ath10k_pci *ar_pci;
2547
2548 ath10k_dbg(ATH10K_DBG_PCI, "%s\n", __func__);
2549
2550 if (!ar)
2551 return;
2552
2553 ar_pci = ath10k_pci_priv(ar);
2554
2555 if (!ar_pci)
2556 return;
2557
2558 tasklet_kill(&ar_pci->msi_fw_err);
2559
2560 ath10k_core_unregister(ar);
2561
2562 pci_iounmap(pdev, ar_pci->mem);
2563 pci_release_region(pdev, BAR_NUM);
2564 pci_clear_master(pdev);
2565 pci_disable_device(pdev);
2566
2567 ath10k_core_destroy(ar);
2568 kfree(ar_pci);
2569 }
2570
2571 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2572
2573 static struct pci_driver ath10k_pci_driver = {
2574 .name = "ath10k_pci",
2575 .id_table = ath10k_pci_id_table,
2576 .probe = ath10k_pci_probe,
2577 .remove = ath10k_pci_remove,
2578 };
2579
2580 static int __init ath10k_pci_init(void)
2581 {
2582 int ret;
2583
2584 ret = pci_register_driver(&ath10k_pci_driver);
2585 if (ret)
2586 ath10k_err("failed to register PCI driver: %d\n", ret);
2587
2588 return ret;
2589 }
2590 module_init(ath10k_pci_init);
2591
2592 static void __exit ath10k_pci_exit(void)
2593 {
2594 pci_unregister_driver(&ath10k_pci_driver);
2595 }
2596
2597 module_exit(ath10k_pci_exit);
2598
2599 MODULE_AUTHOR("Qualcomm Atheros");
2600 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2601 MODULE_LICENSE("Dual BSD/GPL");
2602 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
2603 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_OTP_FILE);
2604 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
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