1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
7 #include <linux/kernel.h>
8 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/property.h>
13 #include <linux/regulator/consumer.h>
22 #define ATH10K_SNOC_RX_POST_RETRY_MS 50
23 #define CE_POLL_PIPE 4
24 #define ATH10K_SNOC_WAKE_IRQ 2
26 static char *const ce_name
[] = {
41 static const char * const ath10k_regulators
[] = {
48 static const char * const ath10k_clocks
[] = {
52 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe
*ce_state
);
53 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe
*ce_state
);
54 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
);
55 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe
*ce_state
);
56 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
);
57 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe
*ce_state
);
59 static const struct ath10k_snoc_drv_priv drv_priv
= {
60 .hw_rev
= ATH10K_HW_WCN3990
,
61 .dma_mask
= DMA_BIT_MASK(35),
65 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C
66 #define WCN3990_DST_WR_IDX_OFFSET 0x40
68 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map
[] = {
70 .ce_id
= __cpu_to_le16(0),
71 .reg_offset
= __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET
),
75 .ce_id
= __cpu_to_le16(3),
76 .reg_offset
= __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET
),
80 .ce_id
= __cpu_to_le16(4),
81 .reg_offset
= __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET
),
85 .ce_id
= __cpu_to_le16(5),
86 .reg_offset
= __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET
),
90 .ce_id
= __cpu_to_le16(7),
91 .reg_offset
= __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET
),
95 .ce_id
= __cpu_to_le16(1),
96 .reg_offset
= __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET
),
100 .ce_id
= __cpu_to_le16(2),
101 .reg_offset
= __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET
),
105 .ce_id
= __cpu_to_le16(7),
106 .reg_offset
= __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET
),
110 .ce_id
= __cpu_to_le16(8),
111 .reg_offset
= __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET
),
115 .ce_id
= __cpu_to_le16(9),
116 .reg_offset
= __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET
),
120 .ce_id
= __cpu_to_le16(10),
121 .reg_offset
= __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET
),
125 .ce_id
= __cpu_to_le16(11),
126 .reg_offset
= __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET
),
130 static struct ce_attr host_ce_config_wlan
[] = {
131 /* CE0: host->target HTC control streams */
133 .flags
= CE_ATTR_FLAGS
,
137 .send_cb
= ath10k_snoc_htc_tx_cb
,
140 /* CE1: target->host HTT + HTC control */
142 .flags
= CE_ATTR_FLAGS
,
145 .dest_nentries
= 512,
146 .recv_cb
= ath10k_snoc_htt_htc_rx_cb
,
149 /* CE2: target->host WMI */
151 .flags
= CE_ATTR_FLAGS
,
155 .recv_cb
= ath10k_snoc_htc_rx_cb
,
158 /* CE3: host->target WMI */
160 .flags
= CE_ATTR_FLAGS
,
164 .send_cb
= ath10k_snoc_htc_tx_cb
,
167 /* CE4: host->target HTT */
169 .flags
= CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
,
170 .src_nentries
= 2048,
173 .send_cb
= ath10k_snoc_htt_tx_cb
,
176 /* CE5: target->host HTT (ipa_uc->target ) */
178 .flags
= CE_ATTR_FLAGS
,
181 .dest_nentries
= 512,
182 .recv_cb
= ath10k_snoc_htt_rx_cb
,
185 /* CE6: target autonomous hif_memcpy */
187 .flags
= CE_ATTR_FLAGS
,
193 /* CE7: ce_diag, the Diagnostic Window */
195 .flags
= CE_ATTR_FLAGS
,
201 /* CE8: Target to uMC */
203 .flags
= CE_ATTR_FLAGS
,
206 .dest_nentries
= 128,
209 /* CE9 target->host HTT */
211 .flags
= CE_ATTR_FLAGS
,
214 .dest_nentries
= 512,
215 .recv_cb
= ath10k_snoc_htt_htc_rx_cb
,
218 /* CE10: target->host HTT */
220 .flags
= CE_ATTR_FLAGS
,
223 .dest_nentries
= 512,
224 .recv_cb
= ath10k_snoc_htt_htc_rx_cb
,
227 /* CE11: target -> host PKTLOG */
229 .flags
= CE_ATTR_FLAGS
,
232 .dest_nentries
= 512,
233 .recv_cb
= ath10k_snoc_pktlog_rx_cb
,
237 static struct ce_pipe_config target_ce_config_wlan
[] = {
238 /* CE0: host->target HTC control and raw streams */
240 .pipenum
= __cpu_to_le32(0),
241 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
242 .nentries
= __cpu_to_le32(32),
243 .nbytes_max
= __cpu_to_le32(2048),
244 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
245 .reserved
= __cpu_to_le32(0),
248 /* CE1: target->host HTT + HTC control */
250 .pipenum
= __cpu_to_le32(1),
251 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
252 .nentries
= __cpu_to_le32(32),
253 .nbytes_max
= __cpu_to_le32(2048),
254 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
255 .reserved
= __cpu_to_le32(0),
258 /* CE2: target->host WMI */
260 .pipenum
= __cpu_to_le32(2),
261 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
262 .nentries
= __cpu_to_le32(64),
263 .nbytes_max
= __cpu_to_le32(2048),
264 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
265 .reserved
= __cpu_to_le32(0),
268 /* CE3: host->target WMI */
270 .pipenum
= __cpu_to_le32(3),
271 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
272 .nentries
= __cpu_to_le32(32),
273 .nbytes_max
= __cpu_to_le32(2048),
274 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
275 .reserved
= __cpu_to_le32(0),
278 /* CE4: host->target HTT */
280 .pipenum
= __cpu_to_le32(4),
281 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
282 .nentries
= __cpu_to_le32(256),
283 .nbytes_max
= __cpu_to_le32(256),
284 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
),
285 .reserved
= __cpu_to_le32(0),
288 /* CE5: target->host HTT (HIF->HTT) */
290 .pipenum
= __cpu_to_le32(5),
291 .pipedir
= __cpu_to_le32(PIPEDIR_OUT
),
292 .nentries
= __cpu_to_le32(1024),
293 .nbytes_max
= __cpu_to_le32(64),
294 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
),
295 .reserved
= __cpu_to_le32(0),
298 /* CE6: Reserved for target autonomous hif_memcpy */
300 .pipenum
= __cpu_to_le32(6),
301 .pipedir
= __cpu_to_le32(PIPEDIR_INOUT
),
302 .nentries
= __cpu_to_le32(32),
303 .nbytes_max
= __cpu_to_le32(16384),
304 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
305 .reserved
= __cpu_to_le32(0),
308 /* CE7 used only by Host */
310 .pipenum
= __cpu_to_le32(7),
311 .pipedir
= __cpu_to_le32(4),
312 .nentries
= __cpu_to_le32(0),
313 .nbytes_max
= __cpu_to_le32(0),
314 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
| CE_ATTR_DIS_INTR
),
315 .reserved
= __cpu_to_le32(0),
318 /* CE8 Target to uMC */
320 .pipenum
= __cpu_to_le32(8),
321 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
322 .nentries
= __cpu_to_le32(32),
323 .nbytes_max
= __cpu_to_le32(2048),
324 .flags
= __cpu_to_le32(0),
325 .reserved
= __cpu_to_le32(0),
328 /* CE9 target->host HTT */
330 .pipenum
= __cpu_to_le32(9),
331 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
332 .nentries
= __cpu_to_le32(32),
333 .nbytes_max
= __cpu_to_le32(2048),
334 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
335 .reserved
= __cpu_to_le32(0),
338 /* CE10 target->host HTT */
340 .pipenum
= __cpu_to_le32(10),
341 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
342 .nentries
= __cpu_to_le32(32),
343 .nbytes_max
= __cpu_to_le32(2048),
344 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
345 .reserved
= __cpu_to_le32(0),
348 /* CE11 target autonomous qcache memcpy */
350 .pipenum
= __cpu_to_le32(11),
351 .pipedir
= __cpu_to_le32(PIPEDIR_IN
),
352 .nentries
= __cpu_to_le32(32),
353 .nbytes_max
= __cpu_to_le32(2048),
354 .flags
= __cpu_to_le32(CE_ATTR_FLAGS
),
355 .reserved
= __cpu_to_le32(0),
359 static struct service_to_pipe target_service_to_ce_map_wlan
[] = {
361 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
362 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO
),
367 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
372 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK
),
377 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
382 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
386 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE
),
387 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
391 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
392 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
396 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI
),
397 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
401 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
402 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
406 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL
),
407 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
411 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
412 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
416 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL
),
417 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
421 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
422 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
426 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
427 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
431 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
432 __cpu_to_le32(PIPEDIR_OUT
), /* out = UL = host -> target */
436 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG
),
437 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
441 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
),
442 __cpu_to_le32(PIPEDIR_OUT
),
445 { /* in = DL = target -> host */
446 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG
),
447 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
450 { /* in = DL = target -> host */
451 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG
),
452 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
455 { /* in = DL = target -> host pktlog */
456 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG
),
457 __cpu_to_le32(PIPEDIR_IN
), /* in = DL = target -> host */
460 /* (Additions here) */
469 static void ath10k_snoc_write32(struct ath10k
*ar
, u32 offset
, u32 value
)
471 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
473 iowrite32(value
, ar_snoc
->mem
+ offset
);
476 static u32
ath10k_snoc_read32(struct ath10k
*ar
, u32 offset
)
478 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
481 val
= ioread32(ar_snoc
->mem
+ offset
);
486 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe
*pipe
)
488 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
489 struct ath10k
*ar
= pipe
->hif_ce_state
;
490 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
495 skb
= dev_alloc_skb(pipe
->buf_sz
);
499 WARN_ONCE((unsigned long)skb
->data
& 3, "unaligned skb");
501 paddr
= dma_map_single(ar
->dev
, skb
->data
,
502 skb
->len
+ skb_tailroom(skb
),
504 if (unlikely(dma_mapping_error(ar
->dev
, paddr
))) {
505 ath10k_warn(ar
, "failed to dma map snoc rx buf\n");
506 dev_kfree_skb_any(skb
);
510 ATH10K_SKB_RXCB(skb
)->paddr
= paddr
;
512 spin_lock_bh(&ce
->ce_lock
);
513 ret
= ce_pipe
->ops
->ce_rx_post_buf(ce_pipe
, skb
, paddr
);
514 spin_unlock_bh(&ce
->ce_lock
);
516 dma_unmap_single(ar
->dev
, paddr
, skb
->len
+ skb_tailroom(skb
),
518 dev_kfree_skb_any(skb
);
525 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe
*pipe
)
527 struct ath10k
*ar
= pipe
->hif_ce_state
;
528 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
529 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
530 struct ath10k_ce_pipe
*ce_pipe
= pipe
->ce_hdl
;
533 if (pipe
->buf_sz
== 0)
536 if (!ce_pipe
->dest_ring
)
539 spin_lock_bh(&ce
->ce_lock
);
540 num
= __ath10k_ce_rx_num_free_bufs(ce_pipe
);
541 spin_unlock_bh(&ce
->ce_lock
);
543 ret
= __ath10k_snoc_rx_post_buf(pipe
);
547 ath10k_warn(ar
, "failed to post rx buf: %d\n", ret
);
548 mod_timer(&ar_snoc
->rx_post_retry
, jiffies
+
549 ATH10K_SNOC_RX_POST_RETRY_MS
);
555 static void ath10k_snoc_rx_post(struct ath10k
*ar
)
557 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
560 for (i
= 0; i
< CE_COUNT
; i
++)
561 ath10k_snoc_rx_post_pipe(&ar_snoc
->pipe_info
[i
]);
564 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe
*ce_state
,
565 void (*callback
)(struct ath10k
*ar
,
566 struct sk_buff
*skb
))
568 struct ath10k
*ar
= ce_state
->ar
;
569 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
570 struct ath10k_snoc_pipe
*pipe_info
= &ar_snoc
->pipe_info
[ce_state
->id
];
572 struct sk_buff_head list
;
573 void *transfer_context
;
574 unsigned int nbytes
, max_nbytes
;
576 __skb_queue_head_init(&list
);
577 while (ath10k_ce_completed_recv_next(ce_state
, &transfer_context
,
579 skb
= transfer_context
;
580 max_nbytes
= skb
->len
+ skb_tailroom(skb
);
581 dma_unmap_single(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
582 max_nbytes
, DMA_FROM_DEVICE
);
584 if (unlikely(max_nbytes
< nbytes
)) {
585 ath10k_warn(ar
, "rxed more than expected (nbytes %d, max %d)",
587 dev_kfree_skb_any(skb
);
591 skb_put(skb
, nbytes
);
592 __skb_queue_tail(&list
, skb
);
595 while ((skb
= __skb_dequeue(&list
))) {
596 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc rx ce pipe %d len %d\n",
597 ce_state
->id
, skb
->len
);
602 ath10k_snoc_rx_post_pipe(pipe_info
);
605 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
)
607 ath10k_snoc_process_rx_cb(ce_state
, ath10k_htc_rx_completion_handler
);
610 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe
*ce_state
)
612 /* CE4 polling needs to be done whenever CE pipe which transports
613 * HTT Rx (target->host) is processed.
615 ath10k_ce_per_engine_service(ce_state
->ar
, CE_POLL_PIPE
);
617 ath10k_snoc_process_rx_cb(ce_state
, ath10k_htc_rx_completion_handler
);
620 /* Called by lower (CE) layer when data is received from the Target.
621 * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data.
623 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe
*ce_state
)
625 ath10k_snoc_process_rx_cb(ce_state
, ath10k_htc_rx_completion_handler
);
628 static void ath10k_snoc_htt_rx_deliver(struct ath10k
*ar
, struct sk_buff
*skb
)
630 skb_pull(skb
, sizeof(struct ath10k_htc_hdr
));
631 ath10k_htt_t2h_msg_handler(ar
, skb
);
634 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe
*ce_state
)
636 ath10k_ce_per_engine_service(ce_state
->ar
, CE_POLL_PIPE
);
637 ath10k_snoc_process_rx_cb(ce_state
, ath10k_snoc_htt_rx_deliver
);
640 static void ath10k_snoc_rx_replenish_retry(struct timer_list
*t
)
642 struct ath10k_snoc
*ar_snoc
= from_timer(ar_snoc
, t
, rx_post_retry
);
643 struct ath10k
*ar
= ar_snoc
->ar
;
645 ath10k_snoc_rx_post(ar
);
648 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe
*ce_state
)
650 struct ath10k
*ar
= ce_state
->ar
;
651 struct sk_buff_head list
;
654 __skb_queue_head_init(&list
);
655 while (ath10k_ce_completed_send_next(ce_state
, (void **)&skb
) == 0) {
659 __skb_queue_tail(&list
, skb
);
662 while ((skb
= __skb_dequeue(&list
)))
663 ath10k_htc_tx_completion_handler(ar
, skb
);
666 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe
*ce_state
)
668 struct ath10k
*ar
= ce_state
->ar
;
671 while (ath10k_ce_completed_send_next(ce_state
, (void **)&skb
) == 0) {
675 dma_unmap_single(ar
->dev
, ATH10K_SKB_CB(skb
)->paddr
,
676 skb
->len
, DMA_TO_DEVICE
);
677 ath10k_htt_hif_tx_complete(ar
, skb
);
681 static int ath10k_snoc_hif_tx_sg(struct ath10k
*ar
, u8 pipe_id
,
682 struct ath10k_hif_sg_item
*items
, int n_items
)
684 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
685 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
686 struct ath10k_snoc_pipe
*snoc_pipe
;
687 struct ath10k_ce_pipe
*ce_pipe
;
690 snoc_pipe
= &ar_snoc
->pipe_info
[pipe_id
];
691 ce_pipe
= snoc_pipe
->ce_hdl
;
692 spin_lock_bh(&ce
->ce_lock
);
694 for (i
= 0; i
< n_items
- 1; i
++) {
695 ath10k_dbg(ar
, ATH10K_DBG_SNOC
,
696 "snoc tx item %d paddr %pad len %d n_items %d\n",
697 i
, &items
[i
].paddr
, items
[i
].len
, n_items
);
699 err
= ath10k_ce_send_nolock(ce_pipe
,
700 items
[i
].transfer_context
,
703 items
[i
].transfer_id
,
704 CE_SEND_FLAG_GATHER
);
709 ath10k_dbg(ar
, ATH10K_DBG_SNOC
,
710 "snoc tx item %d paddr %pad len %d n_items %d\n",
711 i
, &items
[i
].paddr
, items
[i
].len
, n_items
);
713 err
= ath10k_ce_send_nolock(ce_pipe
,
714 items
[i
].transfer_context
,
717 items
[i
].transfer_id
,
722 spin_unlock_bh(&ce
->ce_lock
);
728 __ath10k_ce_send_revert(ce_pipe
);
730 spin_unlock_bh(&ce
->ce_lock
);
734 static int ath10k_snoc_hif_get_target_info(struct ath10k
*ar
,
735 struct bmi_target_info
*target_info
)
737 target_info
->version
= ATH10K_HW_WCN3990
;
738 target_info
->type
= ATH10K_HW_WCN3990
;
743 static u16
ath10k_snoc_hif_get_free_queue_number(struct ath10k
*ar
, u8 pipe
)
745 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
747 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "hif get free queue number\n");
749 return ath10k_ce_num_free_src_entries(ar_snoc
->pipe_info
[pipe
].ce_hdl
);
752 static void ath10k_snoc_hif_send_complete_check(struct ath10k
*ar
, u8 pipe
,
757 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc hif send complete check\n");
760 resources
= ath10k_snoc_hif_get_free_queue_number(ar
, pipe
);
762 if (resources
> (host_ce_config_wlan
[pipe
].src_nentries
>> 1))
765 ath10k_ce_per_engine_service(ar
, pipe
);
768 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k
*ar
,
770 u8
*ul_pipe
, u8
*dl_pipe
)
772 const struct service_to_pipe
*entry
;
773 bool ul_set
= false, dl_set
= false;
776 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc hif map service\n");
778 for (i
= 0; i
< ARRAY_SIZE(target_service_to_ce_map_wlan
); i
++) {
779 entry
= &target_service_to_ce_map_wlan
[i
];
781 if (__le32_to_cpu(entry
->service_id
) != service_id
)
784 switch (__le32_to_cpu(entry
->pipedir
)) {
789 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
794 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
800 *dl_pipe
= __le32_to_cpu(entry
->pipenum
);
801 *ul_pipe
= __le32_to_cpu(entry
->pipenum
);
808 if (!ul_set
|| !dl_set
)
814 static void ath10k_snoc_hif_get_default_pipe(struct ath10k
*ar
,
815 u8
*ul_pipe
, u8
*dl_pipe
)
817 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc hif get default pipe\n");
819 (void)ath10k_snoc_hif_map_service_to_pipe(ar
,
820 ATH10K_HTC_SVC_ID_RSVD_CTRL
,
824 static inline void ath10k_snoc_irq_disable(struct ath10k
*ar
)
826 ath10k_ce_disable_interrupts(ar
);
829 static inline void ath10k_snoc_irq_enable(struct ath10k
*ar
)
831 ath10k_ce_enable_interrupts(ar
);
834 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe
*snoc_pipe
)
836 struct ath10k_ce_pipe
*ce_pipe
;
837 struct ath10k_ce_ring
*ce_ring
;
842 ar
= snoc_pipe
->hif_ce_state
;
843 ce_pipe
= snoc_pipe
->ce_hdl
;
844 ce_ring
= ce_pipe
->dest_ring
;
849 if (!snoc_pipe
->buf_sz
)
852 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
853 skb
= ce_ring
->per_transfer_context
[i
];
857 ce_ring
->per_transfer_context
[i
] = NULL
;
859 dma_unmap_single(ar
->dev
, ATH10K_SKB_RXCB(skb
)->paddr
,
860 skb
->len
+ skb_tailroom(skb
),
862 dev_kfree_skb_any(skb
);
866 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe
*snoc_pipe
)
868 struct ath10k_ce_pipe
*ce_pipe
;
869 struct ath10k_ce_ring
*ce_ring
;
874 ar
= snoc_pipe
->hif_ce_state
;
875 ce_pipe
= snoc_pipe
->ce_hdl
;
876 ce_ring
= ce_pipe
->src_ring
;
881 if (!snoc_pipe
->buf_sz
)
884 for (i
= 0; i
< ce_ring
->nentries
; i
++) {
885 skb
= ce_ring
->per_transfer_context
[i
];
889 ce_ring
->per_transfer_context
[i
] = NULL
;
891 ath10k_htc_tx_completion_handler(ar
, skb
);
895 static void ath10k_snoc_buffer_cleanup(struct ath10k
*ar
)
897 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
898 struct ath10k_snoc_pipe
*pipe_info
;
901 del_timer_sync(&ar_snoc
->rx_post_retry
);
902 for (pipe_num
= 0; pipe_num
< CE_COUNT
; pipe_num
++) {
903 pipe_info
= &ar_snoc
->pipe_info
[pipe_num
];
904 ath10k_snoc_rx_pipe_cleanup(pipe_info
);
905 ath10k_snoc_tx_pipe_cleanup(pipe_info
);
909 static void ath10k_snoc_hif_stop(struct ath10k
*ar
)
911 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH
, &ar
->dev_flags
))
912 ath10k_snoc_irq_disable(ar
);
914 napi_synchronize(&ar
->napi
);
915 napi_disable(&ar
->napi
);
916 ath10k_snoc_buffer_cleanup(ar
);
917 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif stop\n");
920 static int ath10k_snoc_hif_start(struct ath10k
*ar
)
922 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
924 napi_enable(&ar
->napi
);
925 ath10k_snoc_irq_enable(ar
);
926 ath10k_snoc_rx_post(ar
);
928 clear_bit(ATH10K_SNOC_FLAG_RECOVERY
, &ar_snoc
->flags
);
930 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif start\n");
935 static int ath10k_snoc_init_pipes(struct ath10k
*ar
)
939 for (i
= 0; i
< CE_COUNT
; i
++) {
940 ret
= ath10k_ce_init_pipe(ar
, i
, &host_ce_config_wlan
[i
]);
942 ath10k_err(ar
, "failed to initialize copy engine pipe %d: %d\n",
951 static int ath10k_snoc_wlan_enable(struct ath10k
*ar
,
952 enum ath10k_firmware_mode fw_mode
)
954 struct ath10k_tgt_pipe_cfg tgt_cfg
[CE_COUNT_MAX
];
955 struct ath10k_qmi_wlan_enable_cfg cfg
;
956 enum wlfw_driver_mode_enum_v01 mode
;
959 for (pipe_num
= 0; pipe_num
< CE_COUNT_MAX
; pipe_num
++) {
960 tgt_cfg
[pipe_num
].pipe_num
=
961 target_ce_config_wlan
[pipe_num
].pipenum
;
962 tgt_cfg
[pipe_num
].pipe_dir
=
963 target_ce_config_wlan
[pipe_num
].pipedir
;
964 tgt_cfg
[pipe_num
].nentries
=
965 target_ce_config_wlan
[pipe_num
].nentries
;
966 tgt_cfg
[pipe_num
].nbytes_max
=
967 target_ce_config_wlan
[pipe_num
].nbytes_max
;
968 tgt_cfg
[pipe_num
].flags
=
969 target_ce_config_wlan
[pipe_num
].flags
;
970 tgt_cfg
[pipe_num
].reserved
= 0;
973 cfg
.num_ce_tgt_cfg
= sizeof(target_ce_config_wlan
) /
974 sizeof(struct ath10k_tgt_pipe_cfg
);
975 cfg
.ce_tgt_cfg
= (struct ath10k_tgt_pipe_cfg
*)
977 cfg
.num_ce_svc_pipe_cfg
= sizeof(target_service_to_ce_map_wlan
) /
978 sizeof(struct ath10k_svc_pipe_cfg
);
979 cfg
.ce_svc_cfg
= (struct ath10k_svc_pipe_cfg
*)
980 &target_service_to_ce_map_wlan
;
981 cfg
.num_shadow_reg_cfg
= ARRAY_SIZE(target_shadow_reg_cfg_map
);
982 cfg
.shadow_reg_cfg
= (struct ath10k_shadow_reg_cfg
*)
983 &target_shadow_reg_cfg_map
;
986 case ATH10K_FIRMWARE_MODE_NORMAL
:
987 mode
= QMI_WLFW_MISSION_V01
;
989 case ATH10K_FIRMWARE_MODE_UTF
:
990 mode
= QMI_WLFW_FTM_V01
;
993 ath10k_err(ar
, "invalid firmware mode %d\n", fw_mode
);
997 return ath10k_qmi_wlan_enable(ar
, &cfg
, mode
,
1001 static void ath10k_snoc_wlan_disable(struct ath10k
*ar
)
1003 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1005 /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY
1006 * flags are not set, it means that the driver has restarted
1007 * due to a crash inject via debugfs. In this case, the driver
1008 * needs to restart the firmware and hence send qmi wlan disable,
1009 * during the driver restart sequence.
1011 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH
, &ar
->dev_flags
) ||
1012 !test_bit(ATH10K_SNOC_FLAG_RECOVERY
, &ar_snoc
->flags
))
1013 ath10k_qmi_wlan_disable(ar
);
1016 static void ath10k_snoc_hif_power_down(struct ath10k
*ar
)
1018 ath10k_dbg(ar
, ATH10K_DBG_BOOT
, "boot hif power down\n");
1020 ath10k_snoc_wlan_disable(ar
);
1021 ath10k_ce_free_rri(ar
);
1024 static int ath10k_snoc_hif_power_up(struct ath10k
*ar
,
1025 enum ath10k_firmware_mode fw_mode
)
1029 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "%s:WCN3990 driver state = %d\n",
1030 __func__
, ar
->state
);
1032 ret
= ath10k_snoc_wlan_enable(ar
, fw_mode
);
1034 ath10k_err(ar
, "failed to enable wcn3990: %d\n", ret
);
1038 ath10k_ce_alloc_rri(ar
);
1040 ret
= ath10k_snoc_init_pipes(ar
);
1042 ath10k_err(ar
, "failed to initialize CE: %d\n", ret
);
1043 goto err_wlan_enable
;
1049 ath10k_snoc_wlan_disable(ar
);
1054 static int ath10k_snoc_hif_set_target_log_mode(struct ath10k
*ar
,
1060 fw_dbg_mode
= ATH10K_ENABLE_FW_LOG_CE
;
1062 fw_dbg_mode
= ATH10K_ENABLE_FW_LOG_DIAG
;
1064 return ath10k_qmi_set_fw_log_mode(ar
, fw_dbg_mode
);
1068 static int ath10k_snoc_hif_suspend(struct ath10k
*ar
)
1070 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1073 if (!device_may_wakeup(ar
->dev
))
1076 ret
= enable_irq_wake(ar_snoc
->ce_irqs
[ATH10K_SNOC_WAKE_IRQ
].irq_line
);
1078 ath10k_err(ar
, "failed to enable wakeup irq :%d\n", ret
);
1082 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc device suspended\n");
1087 static int ath10k_snoc_hif_resume(struct ath10k
*ar
)
1089 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1092 if (!device_may_wakeup(ar
->dev
))
1095 ret
= disable_irq_wake(ar_snoc
->ce_irqs
[ATH10K_SNOC_WAKE_IRQ
].irq_line
);
1097 ath10k_err(ar
, "failed to disable wakeup irq: %d\n", ret
);
1101 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc device resumed\n");
1107 static const struct ath10k_hif_ops ath10k_snoc_hif_ops
= {
1108 .read32
= ath10k_snoc_read32
,
1109 .write32
= ath10k_snoc_write32
,
1110 .start
= ath10k_snoc_hif_start
,
1111 .stop
= ath10k_snoc_hif_stop
,
1112 .map_service_to_pipe
= ath10k_snoc_hif_map_service_to_pipe
,
1113 .get_default_pipe
= ath10k_snoc_hif_get_default_pipe
,
1114 .power_up
= ath10k_snoc_hif_power_up
,
1115 .power_down
= ath10k_snoc_hif_power_down
,
1116 .tx_sg
= ath10k_snoc_hif_tx_sg
,
1117 .send_complete_check
= ath10k_snoc_hif_send_complete_check
,
1118 .get_free_queue_number
= ath10k_snoc_hif_get_free_queue_number
,
1119 .get_target_info
= ath10k_snoc_hif_get_target_info
,
1120 .set_target_log_mode
= ath10k_snoc_hif_set_target_log_mode
,
1123 .suspend
= ath10k_snoc_hif_suspend
,
1124 .resume
= ath10k_snoc_hif_resume
,
1128 static const struct ath10k_bus_ops ath10k_snoc_bus_ops
= {
1129 .read32
= ath10k_snoc_read32
,
1130 .write32
= ath10k_snoc_write32
,
1133 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k
*ar
, int irq
)
1135 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1138 for (i
= 0; i
< CE_COUNT_MAX
; i
++) {
1139 if (ar_snoc
->ce_irqs
[i
].irq_line
== irq
)
1142 ath10k_err(ar
, "No matching CE id for irq %d\n", irq
);
1147 static irqreturn_t
ath10k_snoc_per_engine_handler(int irq
, void *arg
)
1149 struct ath10k
*ar
= arg
;
1150 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1151 int ce_id
= ath10k_snoc_get_ce_id_from_irq(ar
, irq
);
1153 if (ce_id
< 0 || ce_id
>= ARRAY_SIZE(ar_snoc
->pipe_info
)) {
1154 ath10k_warn(ar
, "unexpected/invalid irq %d ce_id %d\n", irq
,
1159 ath10k_snoc_irq_disable(ar
);
1160 napi_schedule(&ar
->napi
);
1165 static int ath10k_snoc_napi_poll(struct napi_struct
*ctx
, int budget
)
1167 struct ath10k
*ar
= container_of(ctx
, struct ath10k
, napi
);
1170 if (test_bit(ATH10K_FLAG_CRASH_FLUSH
, &ar
->dev_flags
)) {
1175 ath10k_ce_per_engine_service_any(ar
);
1176 done
= ath10k_htt_txrx_compl_task(ar
, budget
);
1178 if (done
< budget
) {
1180 ath10k_snoc_irq_enable(ar
);
1186 static void ath10k_snoc_init_napi(struct ath10k
*ar
)
1188 netif_napi_add(&ar
->napi_dev
, &ar
->napi
, ath10k_snoc_napi_poll
,
1189 ATH10K_NAPI_BUDGET
);
1192 static int ath10k_snoc_request_irq(struct ath10k
*ar
)
1194 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1195 int irqflags
= IRQF_TRIGGER_RISING
;
1198 for (id
= 0; id
< CE_COUNT_MAX
; id
++) {
1199 ret
= request_irq(ar_snoc
->ce_irqs
[id
].irq_line
,
1200 ath10k_snoc_per_engine_handler
,
1201 irqflags
, ce_name
[id
], ar
);
1204 "failed to register IRQ handler for CE %d: %d",
1213 for (id
-= 1; id
>= 0; id
--)
1214 free_irq(ar_snoc
->ce_irqs
[id
].irq_line
, ar
);
1219 static void ath10k_snoc_free_irq(struct ath10k
*ar
)
1221 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1224 for (id
= 0; id
< CE_COUNT_MAX
; id
++)
1225 free_irq(ar_snoc
->ce_irqs
[id
].irq_line
, ar
);
1228 static int ath10k_snoc_resource_init(struct ath10k
*ar
)
1230 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1231 struct platform_device
*pdev
;
1232 struct resource
*res
;
1235 pdev
= ar_snoc
->dev
;
1236 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "membase");
1238 ath10k_err(ar
, "Memory base not found in DT\n");
1242 ar_snoc
->mem_pa
= res
->start
;
1243 ar_snoc
->mem
= devm_ioremap(&pdev
->dev
, ar_snoc
->mem_pa
,
1244 resource_size(res
));
1245 if (!ar_snoc
->mem
) {
1246 ath10k_err(ar
, "Memory base ioremap failed with physical address %pa\n",
1251 for (i
= 0; i
< CE_COUNT
; i
++) {
1252 res
= platform_get_resource(ar_snoc
->dev
, IORESOURCE_IRQ
, i
);
1254 ath10k_err(ar
, "failed to get IRQ%d\n", i
);
1258 ar_snoc
->ce_irqs
[i
].irq_line
= res
->start
;
1261 ret
= device_property_read_u32(&pdev
->dev
, "qcom,xo-cal-data",
1262 &ar_snoc
->xo_cal_data
);
1263 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc xo-cal-data return %d\n", ret
);
1265 ar_snoc
->xo_cal_supported
= true;
1266 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "xo cal data %x\n",
1267 ar_snoc
->xo_cal_data
);
1275 static void ath10k_snoc_quirks_init(struct ath10k
*ar
)
1277 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1278 struct device
*dev
= &ar_snoc
->dev
->dev
;
1280 if (of_property_read_bool(dev
->of_node
, "qcom,snoc-host-cap-8bit-quirk"))
1281 set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK
, &ar_snoc
->flags
);
1284 int ath10k_snoc_fw_indication(struct ath10k
*ar
, u64 type
)
1286 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1287 struct ath10k_bus_params bus_params
= {};
1290 if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING
, &ar_snoc
->flags
))
1294 case ATH10K_QMI_EVENT_FW_READY_IND
:
1295 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED
, &ar_snoc
->flags
)) {
1296 queue_work(ar
->workqueue
, &ar
->restart_work
);
1300 bus_params
.dev_type
= ATH10K_DEV_TYPE_LL
;
1301 bus_params
.chip_id
= ar_snoc
->target_info
.soc_version
;
1302 ret
= ath10k_core_register(ar
, &bus_params
);
1304 ath10k_err(ar
, "Failed to register driver core: %d\n",
1308 set_bit(ATH10K_SNOC_FLAG_REGISTERED
, &ar_snoc
->flags
);
1310 case ATH10K_QMI_EVENT_FW_DOWN_IND
:
1311 set_bit(ATH10K_SNOC_FLAG_RECOVERY
, &ar_snoc
->flags
);
1312 set_bit(ATH10K_FLAG_CRASH_FLUSH
, &ar
->dev_flags
);
1315 ath10k_err(ar
, "invalid fw indication: %llx\n", type
);
1322 static int ath10k_snoc_setup_resource(struct ath10k
*ar
)
1324 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1325 struct ath10k_ce
*ce
= ath10k_ce_priv(ar
);
1326 struct ath10k_snoc_pipe
*pipe
;
1329 timer_setup(&ar_snoc
->rx_post_retry
, ath10k_snoc_rx_replenish_retry
, 0);
1330 spin_lock_init(&ce
->ce_lock
);
1331 for (i
= 0; i
< CE_COUNT
; i
++) {
1332 pipe
= &ar_snoc
->pipe_info
[i
];
1333 pipe
->ce_hdl
= &ce
->ce_states
[i
];
1335 pipe
->hif_ce_state
= ar
;
1337 ret
= ath10k_ce_alloc_pipe(ar
, i
, &host_ce_config_wlan
[i
]);
1339 ath10k_err(ar
, "failed to allocate copy engine pipe %d: %d\n",
1344 pipe
->buf_sz
= host_ce_config_wlan
[i
].src_sz_max
;
1346 ath10k_snoc_init_napi(ar
);
1351 static void ath10k_snoc_release_resource(struct ath10k
*ar
)
1355 netif_napi_del(&ar
->napi
);
1356 for (i
= 0; i
< CE_COUNT
; i
++)
1357 ath10k_ce_free_pipe(ar
, i
);
1360 static int ath10k_hw_power_on(struct ath10k
*ar
)
1362 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1365 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "soc power on\n");
1367 ret
= regulator_bulk_enable(ar_snoc
->num_vregs
, ar_snoc
->vregs
);
1371 ret
= clk_bulk_prepare_enable(ar_snoc
->num_clks
, ar_snoc
->clks
);
1378 regulator_bulk_disable(ar_snoc
->num_vregs
, ar_snoc
->vregs
);
1382 static int ath10k_hw_power_off(struct ath10k
*ar
)
1384 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1386 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "soc power off\n");
1388 clk_bulk_disable_unprepare(ar_snoc
->num_clks
, ar_snoc
->clks
);
1390 return regulator_bulk_disable(ar_snoc
->num_vregs
, ar_snoc
->vregs
);
1393 static void ath10k_msa_dump_memory(struct ath10k
*ar
,
1394 struct ath10k_fw_crash_data
*crash_data
)
1396 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1397 const struct ath10k_hw_mem_layout
*mem_layout
;
1398 const struct ath10k_mem_region
*current_region
;
1399 struct ath10k_dump_ram_data_hdr
*hdr
;
1403 if (!crash_data
|| !crash_data
->ramdump_buf
)
1406 mem_layout
= ath10k_coredump_get_mem_layout(ar
);
1410 current_region
= &mem_layout
->region_table
.regions
[0];
1412 buf
= crash_data
->ramdump_buf
;
1413 buf_len
= crash_data
->ramdump_buf_len
;
1414 memset(buf
, 0, buf_len
);
1416 /* Reserve space for the header. */
1418 buf
+= sizeof(*hdr
);
1419 buf_len
-= sizeof(*hdr
);
1421 hdr
->region_type
= cpu_to_le32(current_region
->type
);
1422 hdr
->start
= cpu_to_le32((unsigned long)ar_snoc
->qmi
->msa_va
);
1423 hdr
->length
= cpu_to_le32(ar_snoc
->qmi
->msa_mem_size
);
1425 if (current_region
->len
< ar_snoc
->qmi
->msa_mem_size
) {
1426 memcpy(buf
, ar_snoc
->qmi
->msa_va
, current_region
->len
);
1427 ath10k_warn(ar
, "msa dump length is less than msa size %x, %x\n",
1428 current_region
->len
, ar_snoc
->qmi
->msa_mem_size
);
1430 memcpy(buf
, ar_snoc
->qmi
->msa_va
, ar_snoc
->qmi
->msa_mem_size
);
1434 void ath10k_snoc_fw_crashed_dump(struct ath10k
*ar
)
1436 struct ath10k_fw_crash_data
*crash_data
;
1437 char guid
[UUID_STRING_LEN
+ 1];
1439 mutex_lock(&ar
->dump_mutex
);
1441 spin_lock_bh(&ar
->data_lock
);
1442 ar
->stats
.fw_crash_counter
++;
1443 spin_unlock_bh(&ar
->data_lock
);
1445 crash_data
= ath10k_coredump_new(ar
);
1448 scnprintf(guid
, sizeof(guid
), "%pUl", &crash_data
->guid
);
1450 scnprintf(guid
, sizeof(guid
), "n/a");
1452 ath10k_err(ar
, "firmware crashed! (guid %s)\n", guid
);
1453 ath10k_print_driver_info(ar
);
1454 ath10k_msa_dump_memory(ar
, crash_data
);
1455 mutex_unlock(&ar
->dump_mutex
);
1458 static const struct of_device_id ath10k_snoc_dt_match
[] = {
1459 { .compatible
= "qcom,wcn3990-wifi",
1464 MODULE_DEVICE_TABLE(of
, ath10k_snoc_dt_match
);
1466 static int ath10k_snoc_probe(struct platform_device
*pdev
)
1468 const struct ath10k_snoc_drv_priv
*drv_data
;
1469 const struct of_device_id
*of_id
;
1470 struct ath10k_snoc
*ar_snoc
;
1477 of_id
= of_match_device(ath10k_snoc_dt_match
, &pdev
->dev
);
1479 dev_err(&pdev
->dev
, "failed to find matching device tree id\n");
1483 drv_data
= of_id
->data
;
1486 ret
= dma_set_mask_and_coherent(dev
, drv_data
->dma_mask
);
1488 dev_err(dev
, "failed to set dma mask: %d", ret
);
1492 ar
= ath10k_core_create(sizeof(*ar_snoc
), dev
, ATH10K_BUS_SNOC
,
1493 drv_data
->hw_rev
, &ath10k_snoc_hif_ops
);
1495 dev_err(dev
, "failed to allocate core\n");
1499 ar_snoc
= ath10k_snoc_priv(ar
);
1500 ar_snoc
->dev
= pdev
;
1501 platform_set_drvdata(pdev
, ar
);
1503 ar_snoc
->ce
.bus_ops
= &ath10k_snoc_bus_ops
;
1504 ar
->ce_priv
= &ar_snoc
->ce
;
1505 msa_size
= drv_data
->msa_size
;
1507 ath10k_snoc_quirks_init(ar
);
1509 ret
= ath10k_snoc_resource_init(ar
);
1511 ath10k_warn(ar
, "failed to initialize resource: %d\n", ret
);
1512 goto err_core_destroy
;
1515 ret
= ath10k_snoc_setup_resource(ar
);
1517 ath10k_warn(ar
, "failed to setup resource: %d\n", ret
);
1518 goto err_core_destroy
;
1520 ret
= ath10k_snoc_request_irq(ar
);
1522 ath10k_warn(ar
, "failed to request irqs: %d\n", ret
);
1523 goto err_release_resource
;
1526 ar_snoc
->num_vregs
= ARRAY_SIZE(ath10k_regulators
);
1527 ar_snoc
->vregs
= devm_kcalloc(&pdev
->dev
, ar_snoc
->num_vregs
,
1528 sizeof(*ar_snoc
->vregs
), GFP_KERNEL
);
1529 if (!ar_snoc
->vregs
) {
1533 for (i
= 0; i
< ar_snoc
->num_vregs
; i
++)
1534 ar_snoc
->vregs
[i
].supply
= ath10k_regulators
[i
];
1536 ret
= devm_regulator_bulk_get(&pdev
->dev
, ar_snoc
->num_vregs
,
1541 ar_snoc
->num_clks
= ARRAY_SIZE(ath10k_clocks
);
1542 ar_snoc
->clks
= devm_kcalloc(&pdev
->dev
, ar_snoc
->num_clks
,
1543 sizeof(*ar_snoc
->clks
), GFP_KERNEL
);
1544 if (!ar_snoc
->clks
) {
1549 for (i
= 0; i
< ar_snoc
->num_clks
; i
++)
1550 ar_snoc
->clks
[i
].id
= ath10k_clocks
[i
];
1552 ret
= devm_clk_bulk_get_optional(&pdev
->dev
, ar_snoc
->num_clks
,
1557 ret
= ath10k_hw_power_on(ar
);
1559 ath10k_err(ar
, "failed to power on device: %d\n", ret
);
1563 ret
= ath10k_qmi_init(ar
, msa_size
);
1565 ath10k_warn(ar
, "failed to register wlfw qmi client: %d\n", ret
);
1566 goto err_core_destroy
;
1569 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc probe\n");
1574 ath10k_snoc_free_irq(ar
);
1576 err_release_resource
:
1577 ath10k_snoc_release_resource(ar
);
1580 ath10k_core_destroy(ar
);
1585 static int ath10k_snoc_remove(struct platform_device
*pdev
)
1587 struct ath10k
*ar
= platform_get_drvdata(pdev
);
1588 struct ath10k_snoc
*ar_snoc
= ath10k_snoc_priv(ar
);
1590 ath10k_dbg(ar
, ATH10K_DBG_SNOC
, "snoc remove\n");
1592 reinit_completion(&ar
->driver_recovery
);
1594 if (test_bit(ATH10K_SNOC_FLAG_RECOVERY
, &ar_snoc
->flags
))
1595 wait_for_completion_timeout(&ar
->driver_recovery
, 3 * HZ
);
1597 set_bit(ATH10K_SNOC_FLAG_UNREGISTERING
, &ar_snoc
->flags
);
1599 ath10k_core_unregister(ar
);
1600 ath10k_hw_power_off(ar
);
1601 ath10k_snoc_free_irq(ar
);
1602 ath10k_snoc_release_resource(ar
);
1603 ath10k_qmi_deinit(ar
);
1604 ath10k_core_destroy(ar
);
1609 static struct platform_driver ath10k_snoc_driver
= {
1610 .probe
= ath10k_snoc_probe
,
1611 .remove
= ath10k_snoc_remove
,
1613 .name
= "ath10k_snoc",
1614 .of_match_table
= ath10k_snoc_dt_match
,
1617 module_platform_driver(ath10k_snoc_driver
);
1619 MODULE_AUTHOR("Qualcomm");
1620 MODULE_LICENSE("Dual BSD/GPL");
1621 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices");