2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/hardirq.h>
49 #include <linux/netdevice.h>
50 #include <linux/cache.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53 #include <linux/slab.h>
54 #include <linux/etherdevice.h>
55 #include <linux/nl80211.h>
57 #include <net/ieee80211_radiotap.h>
59 #include <asm/unaligned.h>
68 #define CREATE_TRACE_POINTS
71 int ath5k_modparam_nohwcrypt
;
72 module_param_named(nohwcrypt
, ath5k_modparam_nohwcrypt
, bool, S_IRUGO
);
73 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
75 static int modparam_all_channels
;
76 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
77 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
79 static int modparam_fastchanswitch
;
80 module_param_named(fastchanswitch
, modparam_fastchanswitch
, bool, S_IRUGO
);
81 MODULE_PARM_DESC(fastchanswitch
, "Enable fast channel switching for AR2413/AR5413 radios.");
85 MODULE_AUTHOR("Jiri Slaby");
86 MODULE_AUTHOR("Nick Kossifidis");
87 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
88 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
89 MODULE_LICENSE("Dual BSD/GPL");
91 static int ath5k_init(struct ieee80211_hw
*hw
);
92 static int ath5k_reset(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
,
96 static const struct ath5k_srev_name srev_names
[] = {
97 #ifdef CONFIG_ATHEROS_AR231X
98 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R2
},
99 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R7
},
100 { "2313", AR5K_VERSION_MAC
, AR5K_SREV_AR2313_R8
},
101 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R6
},
102 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R7
},
103 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R1
},
104 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R2
},
106 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
107 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
108 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
109 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
110 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
111 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
112 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
113 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
114 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
115 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
116 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
117 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
118 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
119 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
120 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
121 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
122 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
123 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
125 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
126 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
127 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
128 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
129 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
130 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
131 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
132 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
133 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
134 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
135 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
136 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
137 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
138 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
139 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
140 #ifdef CONFIG_ATHEROS_AR231X
141 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
142 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
144 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
147 static const struct ieee80211_rate ath5k_rates
[] = {
149 .hw_value
= ATH5K_RATE_CODE_1M
, },
151 .hw_value
= ATH5K_RATE_CODE_2M
,
152 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
153 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
155 .hw_value
= ATH5K_RATE_CODE_5_5M
,
156 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
157 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
159 .hw_value
= ATH5K_RATE_CODE_11M
,
160 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
161 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
163 .hw_value
= ATH5K_RATE_CODE_6M
,
166 .hw_value
= ATH5K_RATE_CODE_9M
,
169 .hw_value
= ATH5K_RATE_CODE_12M
,
172 .hw_value
= ATH5K_RATE_CODE_18M
,
175 .hw_value
= ATH5K_RATE_CODE_24M
,
178 .hw_value
= ATH5K_RATE_CODE_36M
,
181 .hw_value
= ATH5K_RATE_CODE_48M
,
184 .hw_value
= ATH5K_RATE_CODE_54M
,
189 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
191 u64 tsf
= ath5k_hw_get_tsf64(ah
);
193 if ((tsf
& 0x7fff) < rstamp
)
196 return (tsf
& ~0x7fff) | rstamp
;
200 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
202 const char *name
= "xxxxx";
205 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
206 if (srev_names
[i
].sr_type
!= type
)
209 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
210 name
= srev_names
[i
].sr_name
;
212 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
213 name
= srev_names
[i
].sr_name
;
220 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
222 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
223 return ath5k_hw_reg_read(ah
, reg_offset
);
226 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
228 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
229 ath5k_hw_reg_write(ah
, val
, reg_offset
);
232 static const struct ath_ops ath5k_common_ops
= {
233 .read
= ath5k_ioread32
,
234 .write
= ath5k_iowrite32
,
237 /***********************\
238 * Driver Initialization *
239 \***********************/
241 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
243 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
244 struct ath5k_hw
*ah
= hw
->priv
;
245 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
247 return ath_reg_notifier_apply(wiphy
, request
, regulatory
);
250 /********************\
251 * Channel/mode setup *
252 \********************/
255 * Returns true for the channel numbers used without all_channels modparam.
257 static bool ath5k_is_standard_channel(short chan
, enum ieee80211_band band
)
259 if (band
== IEEE80211_BAND_2GHZ
&& chan
<= 14)
262 return /* UNII 1,2 */
263 (((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
265 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
267 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165) ||
268 /* 802.11j 5.030-5.080 GHz (20MHz) */
269 (chan
== 8 || chan
== 12 || chan
== 16) ||
270 /* 802.11j 4.9GHz (20MHz) */
271 (chan
== 184 || chan
== 188 || chan
== 192 || chan
== 196));
275 ath5k_setup_channels(struct ath5k_hw
*ah
, struct ieee80211_channel
*channels
,
276 unsigned int mode
, unsigned int max
)
278 unsigned int count
, size
, freq
, ch
;
279 enum ieee80211_band band
;
283 /* 1..220, but 2GHz frequencies are filtered by check_channel */
285 band
= IEEE80211_BAND_5GHZ
;
290 band
= IEEE80211_BAND_2GHZ
;
293 ATH5K_WARN(ah
, "bad mode, not copying channels\n");
298 for (ch
= 1; ch
<= size
&& count
< max
; ch
++) {
299 freq
= ieee80211_channel_to_frequency(ch
, band
);
301 if (freq
== 0) /* mapping failed - not a standard channel */
304 /* Write channel info, needed for ath5k_channel_ok() */
305 channels
[count
].center_freq
= freq
;
306 channels
[count
].band
= band
;
307 channels
[count
].hw_value
= mode
;
309 /* Check if channel is supported by the chipset */
310 if (!ath5k_channel_ok(ah
, &channels
[count
]))
313 if (!modparam_all_channels
&&
314 !ath5k_is_standard_channel(ch
, band
))
324 ath5k_setup_rate_idx(struct ath5k_hw
*ah
, struct ieee80211_supported_band
*b
)
328 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
329 ah
->rate_idx
[b
->band
][i
] = -1;
331 for (i
= 0; i
< b
->n_bitrates
; i
++) {
332 ah
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
333 if (b
->bitrates
[i
].hw_value_short
)
334 ah
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
339 ath5k_setup_bands(struct ieee80211_hw
*hw
)
341 struct ath5k_hw
*ah
= hw
->priv
;
342 struct ieee80211_supported_band
*sband
;
343 int max_c
, count_c
= 0;
346 BUILD_BUG_ON(ARRAY_SIZE(ah
->sbands
) < IEEE80211_NUM_BANDS
);
347 max_c
= ARRAY_SIZE(ah
->channels
);
350 sband
= &ah
->sbands
[IEEE80211_BAND_2GHZ
];
351 sband
->band
= IEEE80211_BAND_2GHZ
;
352 sband
->bitrates
= &ah
->rates
[IEEE80211_BAND_2GHZ
][0];
354 if (test_bit(AR5K_MODE_11G
, ah
->ah_capabilities
.cap_mode
)) {
356 memcpy(sband
->bitrates
, &ath5k_rates
[0],
357 sizeof(struct ieee80211_rate
) * 12);
358 sband
->n_bitrates
= 12;
360 sband
->channels
= ah
->channels
;
361 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
362 AR5K_MODE_11G
, max_c
);
364 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
365 count_c
= sband
->n_channels
;
367 } else if (test_bit(AR5K_MODE_11B
, ah
->ah_capabilities
.cap_mode
)) {
369 memcpy(sband
->bitrates
, &ath5k_rates
[0],
370 sizeof(struct ieee80211_rate
) * 4);
371 sband
->n_bitrates
= 4;
373 /* 5211 only supports B rates and uses 4bit rate codes
374 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
377 if (ah
->ah_version
== AR5K_AR5211
) {
378 for (i
= 0; i
< 4; i
++) {
379 sband
->bitrates
[i
].hw_value
=
380 sband
->bitrates
[i
].hw_value
& 0xF;
381 sband
->bitrates
[i
].hw_value_short
=
382 sband
->bitrates
[i
].hw_value_short
& 0xF;
386 sband
->channels
= ah
->channels
;
387 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
388 AR5K_MODE_11B
, max_c
);
390 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
391 count_c
= sband
->n_channels
;
394 ath5k_setup_rate_idx(ah
, sband
);
396 /* 5GHz band, A mode */
397 if (test_bit(AR5K_MODE_11A
, ah
->ah_capabilities
.cap_mode
)) {
398 sband
= &ah
->sbands
[IEEE80211_BAND_5GHZ
];
399 sband
->band
= IEEE80211_BAND_5GHZ
;
400 sband
->bitrates
= &ah
->rates
[IEEE80211_BAND_5GHZ
][0];
402 memcpy(sband
->bitrates
, &ath5k_rates
[4],
403 sizeof(struct ieee80211_rate
) * 8);
404 sband
->n_bitrates
= 8;
406 sband
->channels
= &ah
->channels
[count_c
];
407 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
408 AR5K_MODE_11A
, max_c
);
410 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
412 ath5k_setup_rate_idx(ah
, sband
);
414 ath5k_debug_dump_bands(ah
);
420 * Set/change channels. We always reset the chip.
421 * To accomplish this we must first cleanup any pending DMA,
422 * then restart stuff after a la ath5k_init.
424 * Called with ah->lock.
427 ath5k_chan_set(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
)
429 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
430 "channel set, resetting (%u -> %u MHz)\n",
431 ah
->curchan
->center_freq
, chan
->center_freq
);
434 * To switch channels clear any pending DMA operations;
435 * wait long enough for the RX fifo to drain, reset the
436 * hardware at the new frequency, and then re-enable
437 * the relevant bits of the h/w.
439 return ath5k_reset(ah
, chan
, true);
442 void ath5k_vif_iter(void *data
, u8
*mac
, struct ieee80211_vif
*vif
)
444 struct ath5k_vif_iter_data
*iter_data
= data
;
446 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
448 if (iter_data
->hw_macaddr
)
449 for (i
= 0; i
< ETH_ALEN
; i
++)
450 iter_data
->mask
[i
] &=
451 ~(iter_data
->hw_macaddr
[i
] ^ mac
[i
]);
453 if (!iter_data
->found_active
) {
454 iter_data
->found_active
= true;
455 memcpy(iter_data
->active_mac
, mac
, ETH_ALEN
);
458 if (iter_data
->need_set_hw_addr
&& iter_data
->hw_macaddr
)
459 if (compare_ether_addr(iter_data
->hw_macaddr
, mac
) == 0)
460 iter_data
->need_set_hw_addr
= false;
462 if (!iter_data
->any_assoc
) {
464 iter_data
->any_assoc
= true;
467 /* Calculate combined mode - when APs are active, operate in AP mode.
468 * Otherwise use the mode of the new interface. This can currently
469 * only deal with combinations of APs and STAs. Only one ad-hoc
470 * interfaces is allowed.
472 if (avf
->opmode
== NL80211_IFTYPE_AP
)
473 iter_data
->opmode
= NL80211_IFTYPE_AP
;
475 if (avf
->opmode
== NL80211_IFTYPE_STATION
)
477 if (iter_data
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
478 iter_data
->opmode
= avf
->opmode
;
483 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw
*ah
,
484 struct ieee80211_vif
*vif
)
486 struct ath_common
*common
= ath5k_hw_common(ah
);
487 struct ath5k_vif_iter_data iter_data
;
491 * Use the hardware MAC address as reference, the hardware uses it
492 * together with the BSSID mask when matching addresses.
494 iter_data
.hw_macaddr
= common
->macaddr
;
495 memset(&iter_data
.mask
, 0xff, ETH_ALEN
);
496 iter_data
.found_active
= false;
497 iter_data
.need_set_hw_addr
= true;
498 iter_data
.opmode
= NL80211_IFTYPE_UNSPECIFIED
;
499 iter_data
.n_stas
= 0;
502 ath5k_vif_iter(&iter_data
, vif
->addr
, vif
);
504 /* Get list of all active MAC addresses */
505 ieee80211_iterate_active_interfaces_atomic(ah
->hw
, ath5k_vif_iter
,
507 memcpy(ah
->bssidmask
, iter_data
.mask
, ETH_ALEN
);
509 ah
->opmode
= iter_data
.opmode
;
510 if (ah
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
511 /* Nothing active, default to station mode */
512 ah
->opmode
= NL80211_IFTYPE_STATION
;
514 ath5k_hw_set_opmode(ah
, ah
->opmode
);
515 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "mode setup opmode %d (%s)\n",
516 ah
->opmode
, ath_opmode_to_string(ah
->opmode
));
518 if (iter_data
.need_set_hw_addr
&& iter_data
.found_active
)
519 ath5k_hw_set_lladdr(ah
, iter_data
.active_mac
);
521 if (ath5k_hw_hasbssidmask(ah
))
522 ath5k_hw_set_bssid_mask(ah
, ah
->bssidmask
);
524 /* Set up RX Filter */
525 if (iter_data
.n_stas
> 1) {
526 /* If you have multiple STA interfaces connected to
527 * different APs, ARPs are not received (most of the time?)
528 * Enabling PROMISC appears to fix that problem.
530 ah
->filter_flags
|= AR5K_RX_FILTER_PROM
;
533 rfilt
= ah
->filter_flags
;
534 ath5k_hw_set_rx_filter(ah
, rfilt
);
535 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
539 ath5k_hw_to_driver_rix(struct ath5k_hw
*ah
, int hw_rix
)
543 /* return base rate on errors */
544 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
545 "hw_rix out of bounds: %x\n", hw_rix
))
548 rix
= ah
->rate_idx
[ah
->curchan
->band
][hw_rix
];
549 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
560 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_hw
*ah
, dma_addr_t
*skb_addr
)
562 struct ath_common
*common
= ath5k_hw_common(ah
);
566 * Allocate buffer with headroom_needed space for the
567 * fake physical layer header at the start.
569 skb
= ath_rxbuf_alloc(common
,
574 ATH5K_ERR(ah
, "can't alloc skbuff of size %u\n",
579 *skb_addr
= dma_map_single(ah
->dev
,
580 skb
->data
, common
->rx_bufsize
,
583 if (unlikely(dma_mapping_error(ah
->dev
, *skb_addr
))) {
584 ATH5K_ERR(ah
, "%s: DMA mapping failed\n", __func__
);
592 ath5k_rxbuf_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
594 struct sk_buff
*skb
= bf
->skb
;
595 struct ath5k_desc
*ds
;
599 skb
= ath5k_rx_skb_alloc(ah
, &bf
->skbaddr
);
606 * Setup descriptors. For receive we always terminate
607 * the descriptor list with a self-linked entry so we'll
608 * not get overrun under high load (as can happen with a
609 * 5212 when ANI processing enables PHY error frames).
611 * To ensure the last descriptor is self-linked we create
612 * each descriptor as self-linked and add it to the end. As
613 * each additional descriptor is added the previous self-linked
614 * entry is "fixed" naturally. This should be safe even
615 * if DMA is happening. When processing RX interrupts we
616 * never remove/process the last, self-linked, entry on the
617 * descriptor list. This ensures the hardware always has
618 * someplace to write a new frame.
621 ds
->ds_link
= bf
->daddr
; /* link to self */
622 ds
->ds_data
= bf
->skbaddr
;
623 ret
= ath5k_hw_setup_rx_desc(ah
, ds
, ah
->common
.rx_bufsize
, 0);
625 ATH5K_ERR(ah
, "%s: could not setup RX desc\n", __func__
);
629 if (ah
->rxlink
!= NULL
)
630 *ah
->rxlink
= bf
->daddr
;
631 ah
->rxlink
= &ds
->ds_link
;
635 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
637 struct ieee80211_hdr
*hdr
;
638 enum ath5k_pkt_type htype
;
641 hdr
= (struct ieee80211_hdr
*)skb
->data
;
642 fc
= hdr
->frame_control
;
644 if (ieee80211_is_beacon(fc
))
645 htype
= AR5K_PKT_TYPE_BEACON
;
646 else if (ieee80211_is_probe_resp(fc
))
647 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
648 else if (ieee80211_is_atim(fc
))
649 htype
= AR5K_PKT_TYPE_ATIM
;
650 else if (ieee80211_is_pspoll(fc
))
651 htype
= AR5K_PKT_TYPE_PSPOLL
;
653 htype
= AR5K_PKT_TYPE_NORMAL
;
659 ath5k_txbuf_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
,
660 struct ath5k_txq
*txq
, int padsize
)
662 struct ath5k_desc
*ds
= bf
->desc
;
663 struct sk_buff
*skb
= bf
->skb
;
664 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
665 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
666 struct ieee80211_rate
*rate
;
667 unsigned int mrr_rate
[3], mrr_tries
[3];
674 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
677 bf
->skbaddr
= dma_map_single(ah
->dev
, skb
->data
, skb
->len
,
680 rate
= ieee80211_get_tx_rate(ah
->hw
, info
);
686 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
687 flags
|= AR5K_TXDESC_NOACK
;
689 rc_flags
= info
->control
.rates
[0].flags
;
690 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
691 rate
->hw_value_short
: rate
->hw_value
;
695 /* FIXME: If we are in g mode and rate is a CCK rate
696 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
697 * from tx power (value is in dB units already) */
698 if (info
->control
.hw_key
) {
699 keyidx
= info
->control
.hw_key
->hw_key_idx
;
700 pktlen
+= info
->control
.hw_key
->icv_len
;
702 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
703 flags
|= AR5K_TXDESC_RTSENA
;
704 cts_rate
= ieee80211_get_rts_cts_rate(ah
->hw
, info
)->hw_value
;
705 duration
= le16_to_cpu(ieee80211_rts_duration(ah
->hw
,
706 info
->control
.vif
, pktlen
, info
));
708 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
709 flags
|= AR5K_TXDESC_CTSENA
;
710 cts_rate
= ieee80211_get_rts_cts_rate(ah
->hw
, info
)->hw_value
;
711 duration
= le16_to_cpu(ieee80211_ctstoself_duration(ah
->hw
,
712 info
->control
.vif
, pktlen
, info
));
714 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
715 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
716 get_hw_packet_type(skb
),
717 (ah
->power_level
* 2),
719 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
724 memset(mrr_rate
, 0, sizeof(mrr_rate
));
725 memset(mrr_tries
, 0, sizeof(mrr_tries
));
726 for (i
= 0; i
< 3; i
++) {
727 rate
= ieee80211_get_alt_retry_rate(ah
->hw
, info
, i
);
731 mrr_rate
[i
] = rate
->hw_value
;
732 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
735 ath5k_hw_setup_mrr_tx_desc(ah
, ds
,
736 mrr_rate
[0], mrr_tries
[0],
737 mrr_rate
[1], mrr_tries
[1],
738 mrr_rate
[2], mrr_tries
[2]);
741 ds
->ds_data
= bf
->skbaddr
;
743 spin_lock_bh(&txq
->lock
);
744 list_add_tail(&bf
->list
, &txq
->q
);
746 if (txq
->link
== NULL
) /* is this first packet? */
747 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
748 else /* no, so only link it */
749 *txq
->link
= bf
->daddr
;
751 txq
->link
= &ds
->ds_link
;
752 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
754 spin_unlock_bh(&txq
->lock
);
758 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
762 /*******************\
763 * Descriptors setup *
764 \*******************/
767 ath5k_desc_alloc(struct ath5k_hw
*ah
)
769 struct ath5k_desc
*ds
;
770 struct ath5k_buf
*bf
;
775 /* allocate descriptors */
776 ah
->desc_len
= sizeof(struct ath5k_desc
) *
777 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
779 ah
->desc
= dma_alloc_coherent(ah
->dev
, ah
->desc_len
,
780 &ah
->desc_daddr
, GFP_KERNEL
);
781 if (ah
->desc
== NULL
) {
782 ATH5K_ERR(ah
, "can't allocate descriptors\n");
788 ATH5K_DBG(ah
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
789 ds
, ah
->desc_len
, (unsigned long long)ah
->desc_daddr
);
791 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
792 sizeof(struct ath5k_buf
), GFP_KERNEL
);
794 ATH5K_ERR(ah
, "can't allocate bufptr\n");
800 INIT_LIST_HEAD(&ah
->rxbuf
);
801 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
804 list_add_tail(&bf
->list
, &ah
->rxbuf
);
807 INIT_LIST_HEAD(&ah
->txbuf
);
808 ah
->txbuf_len
= ATH_TXBUF
;
809 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
812 list_add_tail(&bf
->list
, &ah
->txbuf
);
816 INIT_LIST_HEAD(&ah
->bcbuf
);
817 for (i
= 0; i
< ATH_BCBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
820 list_add_tail(&bf
->list
, &ah
->bcbuf
);
825 dma_free_coherent(ah
->dev
, ah
->desc_len
, ah
->desc
, ah
->desc_daddr
);
832 ath5k_txbuf_free_skb(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
837 dma_unmap_single(ah
->dev
, bf
->skbaddr
, bf
->skb
->len
,
839 dev_kfree_skb_any(bf
->skb
);
842 bf
->desc
->ds_data
= 0;
846 ath5k_rxbuf_free_skb(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
848 struct ath_common
*common
= ath5k_hw_common(ah
);
853 dma_unmap_single(ah
->dev
, bf
->skbaddr
, common
->rx_bufsize
,
855 dev_kfree_skb_any(bf
->skb
);
858 bf
->desc
->ds_data
= 0;
862 ath5k_desc_free(struct ath5k_hw
*ah
)
864 struct ath5k_buf
*bf
;
866 list_for_each_entry(bf
, &ah
->txbuf
, list
)
867 ath5k_txbuf_free_skb(ah
, bf
);
868 list_for_each_entry(bf
, &ah
->rxbuf
, list
)
869 ath5k_rxbuf_free_skb(ah
, bf
);
870 list_for_each_entry(bf
, &ah
->bcbuf
, list
)
871 ath5k_txbuf_free_skb(ah
, bf
);
873 /* Free memory associated with all descriptors */
874 dma_free_coherent(ah
->dev
, ah
->desc_len
, ah
->desc
, ah
->desc_daddr
);
887 static struct ath5k_txq
*
888 ath5k_txq_setup(struct ath5k_hw
*ah
,
889 int qtype
, int subtype
)
891 struct ath5k_txq
*txq
;
892 struct ath5k_txq_info qi
= {
893 .tqi_subtype
= subtype
,
894 /* XXX: default values not correct for B and XR channels,
896 .tqi_aifs
= AR5K_TUNE_AIFS
,
897 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
898 .tqi_cw_max
= AR5K_TUNE_CWMAX
903 * Enable interrupts only for EOL and DESC conditions.
904 * We mark tx descriptors to receive a DESC interrupt
905 * when a tx queue gets deep; otherwise we wait for the
906 * EOL to reap descriptors. Note that this is done to
907 * reduce interrupt load and this only defers reaping
908 * descriptors, never transmitting frames. Aside from
909 * reducing interrupts this also permits more concurrency.
910 * The only potential downside is if the tx queue backs
911 * up in which case the top half of the kernel may backup
912 * due to a lack of tx descriptors.
914 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
915 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
916 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
919 * NB: don't print a message, this happens
920 * normally on parts with too few tx queues
922 return ERR_PTR(qnum
);
924 if (qnum
>= ARRAY_SIZE(ah
->txqs
)) {
925 ATH5K_ERR(ah
, "hw qnum %u out of range, max %tu!\n",
926 qnum
, ARRAY_SIZE(ah
->txqs
));
927 ath5k_hw_release_tx_queue(ah
, qnum
);
928 return ERR_PTR(-EINVAL
);
930 txq
= &ah
->txqs
[qnum
];
934 INIT_LIST_HEAD(&txq
->q
);
935 spin_lock_init(&txq
->lock
);
938 txq
->txq_max
= ATH5K_TXQ_LEN_MAX
;
939 txq
->txq_poll_mark
= false;
942 return &ah
->txqs
[qnum
];
946 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
948 struct ath5k_txq_info qi
= {
949 /* XXX: default values not correct for B and XR channels,
951 .tqi_aifs
= AR5K_TUNE_AIFS
,
952 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
953 .tqi_cw_max
= AR5K_TUNE_CWMAX
,
954 /* NB: for dynamic turbo, don't enable any other interrupts */
955 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
958 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
962 ath5k_beaconq_config(struct ath5k_hw
*ah
)
964 struct ath5k_txq_info qi
;
967 ret
= ath5k_hw_get_tx_queueprops(ah
, ah
->bhalq
, &qi
);
971 if (ah
->opmode
== NL80211_IFTYPE_AP
||
972 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
974 * Always burst out beacon and CAB traffic
975 * (aifs = cwmin = cwmax = 0)
980 } else if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
982 * Adhoc mode; backoff between 0 and (2 * cw_min).
986 qi
.tqi_cw_max
= 2 * AR5K_TUNE_CWMIN
;
989 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
990 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
991 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
993 ret
= ath5k_hw_set_tx_queueprops(ah
, ah
->bhalq
, &qi
);
995 ATH5K_ERR(ah
, "%s: unable to update parameters for beacon "
996 "hardware queue!\n", __func__
);
999 ret
= ath5k_hw_reset_tx_queue(ah
, ah
->bhalq
); /* push to h/w */
1003 /* reconfigure cabq with ready time to 80% of beacon_interval */
1004 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1008 qi
.tqi_ready_time
= (ah
->bintval
* 80) / 100;
1009 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1013 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1019 * ath5k_drain_tx_buffs - Empty tx buffers
1021 * @ah The &struct ath5k_hw
1023 * Empty tx buffers from all queues in preparation
1024 * of a reset or during shutdown.
1026 * NB: this assumes output has been stopped and
1027 * we do not need to block ath5k_tx_tasklet
1030 ath5k_drain_tx_buffs(struct ath5k_hw
*ah
)
1032 struct ath5k_txq
*txq
;
1033 struct ath5k_buf
*bf
, *bf0
;
1036 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++) {
1037 if (ah
->txqs
[i
].setup
) {
1039 spin_lock_bh(&txq
->lock
);
1040 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1041 ath5k_debug_printtxbuf(ah
, bf
);
1043 ath5k_txbuf_free_skb(ah
, bf
);
1045 spin_lock_bh(&ah
->txbuflock
);
1046 list_move_tail(&bf
->list
, &ah
->txbuf
);
1049 spin_unlock_bh(&ah
->txbuflock
);
1052 txq
->txq_poll_mark
= false;
1053 spin_unlock_bh(&txq
->lock
);
1059 ath5k_txq_release(struct ath5k_hw
*ah
)
1061 struct ath5k_txq
*txq
= ah
->txqs
;
1064 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++, txq
++)
1066 ath5k_hw_release_tx_queue(ah
, txq
->qnum
);
1077 * Enable the receive h/w following a reset.
1080 ath5k_rx_start(struct ath5k_hw
*ah
)
1082 struct ath_common
*common
= ath5k_hw_common(ah
);
1083 struct ath5k_buf
*bf
;
1086 common
->rx_bufsize
= roundup(IEEE80211_MAX_FRAME_LEN
, common
->cachelsz
);
1088 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1089 common
->cachelsz
, common
->rx_bufsize
);
1091 spin_lock_bh(&ah
->rxbuflock
);
1093 list_for_each_entry(bf
, &ah
->rxbuf
, list
) {
1094 ret
= ath5k_rxbuf_setup(ah
, bf
);
1096 spin_unlock_bh(&ah
->rxbuflock
);
1100 bf
= list_first_entry(&ah
->rxbuf
, struct ath5k_buf
, list
);
1101 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1102 spin_unlock_bh(&ah
->rxbuflock
);
1104 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1105 ath5k_update_bssid_mask_and_opmode(ah
, NULL
); /* set filters, etc. */
1106 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1114 * Disable the receive logic on PCU (DRU)
1115 * In preparation for a shutdown.
1117 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1121 ath5k_rx_stop(struct ath5k_hw
*ah
)
1124 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1125 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1127 ath5k_debug_printrxbuffs(ah
);
1131 ath5k_rx_decrypted(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1132 struct ath5k_rx_status
*rs
)
1134 struct ath_common
*common
= ath5k_hw_common(ah
);
1135 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1136 unsigned int keyix
, hlen
;
1138 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1139 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1140 return RX_FLAG_DECRYPTED
;
1142 /* Apparently when a default key is used to decrypt the packet
1143 the hw does not set the index used to decrypt. In such cases
1144 get the index from the packet. */
1145 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1146 if (ieee80211_has_protected(hdr
->frame_control
) &&
1147 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1148 skb
->len
>= hlen
+ 4) {
1149 keyix
= skb
->data
[hlen
+ 3] >> 6;
1151 if (test_bit(keyix
, common
->keymap
))
1152 return RX_FLAG_DECRYPTED
;
1160 ath5k_check_ibss_tsf(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1161 struct ieee80211_rx_status
*rxs
)
1163 struct ath_common
*common
= ath5k_hw_common(ah
);
1166 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1168 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1169 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1170 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) == 0) {
1172 * Received an IBSS beacon with the same BSSID. Hardware *must*
1173 * have updated the local TSF. We have to work around various
1174 * hardware bugs, though...
1176 tsf
= ath5k_hw_get_tsf64(ah
);
1177 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1178 hw_tu
= TSF_TO_TU(tsf
);
1180 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1181 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1182 (unsigned long long)bc_tstamp
,
1183 (unsigned long long)rxs
->mactime
,
1184 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1185 (unsigned long long)tsf
);
1188 * Sometimes the HW will give us a wrong tstamp in the rx
1189 * status, causing the timestamp extension to go wrong.
1190 * (This seems to happen especially with beacon frames bigger
1191 * than 78 byte (incl. FCS))
1192 * But we know that the receive timestamp must be later than the
1193 * timestamp of the beacon since HW must have synced to that.
1195 * NOTE: here we assume mactime to be after the frame was
1196 * received, not like mac80211 which defines it at the start.
1198 if (bc_tstamp
> rxs
->mactime
) {
1199 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1200 "fixing mactime from %llx to %llx\n",
1201 (unsigned long long)rxs
->mactime
,
1202 (unsigned long long)tsf
);
1207 * Local TSF might have moved higher than our beacon timers,
1208 * in that case we have to update them to continue sending
1209 * beacons. This also takes care of synchronizing beacon sending
1210 * times with other stations.
1212 if (hw_tu
>= ah
->nexttbtt
)
1213 ath5k_beacon_update_timers(ah
, bc_tstamp
);
1215 /* Check if the beacon timers are still correct, because a TSF
1216 * update might have created a window between them - for a
1217 * longer description see the comment of this function: */
1218 if (!ath5k_hw_check_beacon_timers(ah
, ah
->bintval
)) {
1219 ath5k_beacon_update_timers(ah
, bc_tstamp
);
1220 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1221 "fixed beacon timers after beacon receive\n");
1227 ath5k_update_beacon_rssi(struct ath5k_hw
*ah
, struct sk_buff
*skb
, int rssi
)
1229 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1230 struct ath_common
*common
= ath5k_hw_common(ah
);
1232 /* only beacons from our BSSID */
1233 if (!ieee80211_is_beacon(mgmt
->frame_control
) ||
1234 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) != 0)
1237 ewma_add(&ah
->ah_beacon_rssi_avg
, rssi
);
1239 /* in IBSS mode we should keep RSSI statistics per neighbour */
1240 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1244 * Compute padding position. skb must contain an IEEE 802.11 frame
1246 static int ath5k_common_padpos(struct sk_buff
*skb
)
1248 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1249 __le16 frame_control
= hdr
->frame_control
;
1252 if (ieee80211_has_a4(frame_control
))
1255 if (ieee80211_is_data_qos(frame_control
))
1256 padpos
+= IEEE80211_QOS_CTL_LEN
;
1262 * This function expects an 802.11 frame and returns the number of
1263 * bytes added, or -1 if we don't have enough header room.
1265 static int ath5k_add_padding(struct sk_buff
*skb
)
1267 int padpos
= ath5k_common_padpos(skb
);
1268 int padsize
= padpos
& 3;
1270 if (padsize
&& skb
->len
> padpos
) {
1272 if (skb_headroom(skb
) < padsize
)
1275 skb_push(skb
, padsize
);
1276 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1284 * The MAC header is padded to have 32-bit boundary if the
1285 * packet payload is non-zero. The general calculation for
1286 * padsize would take into account odd header lengths:
1287 * padsize = 4 - (hdrlen & 3); however, since only
1288 * even-length headers are used, padding can only be 0 or 2
1289 * bytes and we can optimize this a bit. We must not try to
1290 * remove padding from short control frames that do not have a
1293 * This function expects an 802.11 frame and returns the number of
1296 static int ath5k_remove_padding(struct sk_buff
*skb
)
1298 int padpos
= ath5k_common_padpos(skb
);
1299 int padsize
= padpos
& 3;
1301 if (padsize
&& skb
->len
>= padpos
+ padsize
) {
1302 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1303 skb_pull(skb
, padsize
);
1311 ath5k_receive_frame(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1312 struct ath5k_rx_status
*rs
)
1314 struct ieee80211_rx_status
*rxs
;
1316 ath5k_remove_padding(skb
);
1318 rxs
= IEEE80211_SKB_RXCB(skb
);
1321 if (unlikely(rs
->rs_status
& AR5K_RXERR_MIC
))
1322 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
1325 * always extend the mac timestamp, since this information is
1326 * also needed for proper IBSS merging.
1328 * XXX: it might be too late to do it here, since rs_tstamp is
1329 * 15bit only. that means TSF extension has to be done within
1330 * 32768usec (about 32ms). it might be necessary to move this to
1331 * the interrupt handler, like it is done in madwifi.
1333 * Unfortunately we don't know when the hardware takes the rx
1334 * timestamp (beginning of phy frame, data frame, end of rx?).
1335 * The only thing we know is that it is hardware specific...
1336 * On AR5213 it seems the rx timestamp is at the end of the
1337 * frame, but I'm not sure.
1339 * NOTE: mac80211 defines mactime at the beginning of the first
1340 * data symbol. Since we don't have any time references it's
1341 * impossible to comply to that. This affects IBSS merge only
1342 * right now, so it's not too bad...
1344 rxs
->mactime
= ath5k_extend_tsf(ah
, rs
->rs_tstamp
);
1345 rxs
->flag
|= RX_FLAG_MACTIME_MPDU
;
1347 rxs
->freq
= ah
->curchan
->center_freq
;
1348 rxs
->band
= ah
->curchan
->band
;
1350 rxs
->signal
= ah
->ah_noise_floor
+ rs
->rs_rssi
;
1352 rxs
->antenna
= rs
->rs_antenna
;
1354 if (rs
->rs_antenna
> 0 && rs
->rs_antenna
< 5)
1355 ah
->stats
.antenna_rx
[rs
->rs_antenna
]++;
1357 ah
->stats
.antenna_rx
[0]++; /* invalid */
1359 rxs
->rate_idx
= ath5k_hw_to_driver_rix(ah
, rs
->rs_rate
);
1360 rxs
->flag
|= ath5k_rx_decrypted(ah
, skb
, rs
);
1362 if (rxs
->rate_idx
>= 0 && rs
->rs_rate
==
1363 ah
->sbands
[ah
->curchan
->band
].bitrates
[rxs
->rate_idx
].hw_value_short
)
1364 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1366 trace_ath5k_rx(ah
, skb
);
1368 ath5k_update_beacon_rssi(ah
, skb
, rs
->rs_rssi
);
1370 /* check beacons in IBSS mode */
1371 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
)
1372 ath5k_check_ibss_tsf(ah
, skb
, rxs
);
1374 ieee80211_rx(ah
->hw
, skb
);
1377 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1379 * Check if we want to further process this frame or not. Also update
1380 * statistics. Return true if we want this frame, false if not.
1383 ath5k_receive_frame_ok(struct ath5k_hw
*ah
, struct ath5k_rx_status
*rs
)
1385 ah
->stats
.rx_all_count
++;
1386 ah
->stats
.rx_bytes_count
+= rs
->rs_datalen
;
1388 if (unlikely(rs
->rs_status
)) {
1389 if (rs
->rs_status
& AR5K_RXERR_CRC
)
1390 ah
->stats
.rxerr_crc
++;
1391 if (rs
->rs_status
& AR5K_RXERR_FIFO
)
1392 ah
->stats
.rxerr_fifo
++;
1393 if (rs
->rs_status
& AR5K_RXERR_PHY
) {
1394 ah
->stats
.rxerr_phy
++;
1395 if (rs
->rs_phyerr
> 0 && rs
->rs_phyerr
< 32)
1396 ah
->stats
.rxerr_phy_code
[rs
->rs_phyerr
]++;
1399 if (rs
->rs_status
& AR5K_RXERR_DECRYPT
) {
1401 * Decrypt error. If the error occurred
1402 * because there was no hardware key, then
1403 * let the frame through so the upper layers
1404 * can process it. This is necessary for 5210
1405 * parts which have no way to setup a ``clear''
1408 * XXX do key cache faulting
1410 ah
->stats
.rxerr_decrypt
++;
1411 if (rs
->rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1412 !(rs
->rs_status
& AR5K_RXERR_CRC
))
1415 if (rs
->rs_status
& AR5K_RXERR_MIC
) {
1416 ah
->stats
.rxerr_mic
++;
1420 /* reject any frames with non-crypto errors */
1421 if (rs
->rs_status
& ~(AR5K_RXERR_DECRYPT
))
1425 if (unlikely(rs
->rs_more
)) {
1426 ah
->stats
.rxerr_jumbo
++;
1433 ath5k_set_current_imask(struct ath5k_hw
*ah
)
1435 enum ath5k_int imask
;
1436 unsigned long flags
;
1438 spin_lock_irqsave(&ah
->irqlock
, flags
);
1441 imask
&= ~AR5K_INT_RX_ALL
;
1443 imask
&= ~AR5K_INT_TX_ALL
;
1444 ath5k_hw_set_imr(ah
, imask
);
1445 spin_unlock_irqrestore(&ah
->irqlock
, flags
);
1449 ath5k_tasklet_rx(unsigned long data
)
1451 struct ath5k_rx_status rs
= {};
1452 struct sk_buff
*skb
, *next_skb
;
1453 dma_addr_t next_skb_addr
;
1454 struct ath5k_hw
*ah
= (void *)data
;
1455 struct ath_common
*common
= ath5k_hw_common(ah
);
1456 struct ath5k_buf
*bf
;
1457 struct ath5k_desc
*ds
;
1460 spin_lock(&ah
->rxbuflock
);
1461 if (list_empty(&ah
->rxbuf
)) {
1462 ATH5K_WARN(ah
, "empty rx buf pool\n");
1466 bf
= list_first_entry(&ah
->rxbuf
, struct ath5k_buf
, list
);
1467 BUG_ON(bf
->skb
== NULL
);
1471 /* bail if HW is still using self-linked descriptor */
1472 if (ath5k_hw_get_rxdp(ah
) == bf
->daddr
)
1475 ret
= ah
->ah_proc_rx_desc(ah
, ds
, &rs
);
1476 if (unlikely(ret
== -EINPROGRESS
))
1478 else if (unlikely(ret
)) {
1479 ATH5K_ERR(ah
, "error in processing rx descriptor\n");
1480 ah
->stats
.rxerr_proc
++;
1484 if (ath5k_receive_frame_ok(ah
, &rs
)) {
1485 next_skb
= ath5k_rx_skb_alloc(ah
, &next_skb_addr
);
1488 * If we can't replace bf->skb with a new skb under
1489 * memory pressure, just skip this packet
1494 dma_unmap_single(ah
->dev
, bf
->skbaddr
,
1498 skb_put(skb
, rs
.rs_datalen
);
1500 ath5k_receive_frame(ah
, skb
, &rs
);
1503 bf
->skbaddr
= next_skb_addr
;
1506 list_move_tail(&bf
->list
, &ah
->rxbuf
);
1507 } while (ath5k_rxbuf_setup(ah
, bf
) == 0);
1509 spin_unlock(&ah
->rxbuflock
);
1510 ah
->rx_pending
= false;
1511 ath5k_set_current_imask(ah
);
1520 ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1521 struct ath5k_txq
*txq
)
1523 struct ath5k_hw
*ah
= hw
->priv
;
1524 struct ath5k_buf
*bf
;
1525 unsigned long flags
;
1528 trace_ath5k_tx(ah
, skb
, txq
);
1531 * The hardware expects the header padded to 4 byte boundaries.
1532 * If this is not the case, we add the padding after the header.
1534 padsize
= ath5k_add_padding(skb
);
1536 ATH5K_ERR(ah
, "tx hdrlen not %%4: not enough"
1537 " headroom to pad");
1541 if (txq
->txq_len
>= txq
->txq_max
&&
1542 txq
->qnum
<= AR5K_TX_QUEUE_ID_DATA_MAX
)
1543 ieee80211_stop_queue(hw
, txq
->qnum
);
1545 spin_lock_irqsave(&ah
->txbuflock
, flags
);
1546 if (list_empty(&ah
->txbuf
)) {
1547 ATH5K_ERR(ah
, "no further txbuf available, dropping packet\n");
1548 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1549 ieee80211_stop_queues(hw
);
1552 bf
= list_first_entry(&ah
->txbuf
, struct ath5k_buf
, list
);
1553 list_del(&bf
->list
);
1555 if (list_empty(&ah
->txbuf
))
1556 ieee80211_stop_queues(hw
);
1557 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1561 if (ath5k_txbuf_setup(ah
, bf
, txq
, padsize
)) {
1563 spin_lock_irqsave(&ah
->txbuflock
, flags
);
1564 list_add_tail(&bf
->list
, &ah
->txbuf
);
1566 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1572 dev_kfree_skb_any(skb
);
1576 ath5k_tx_frame_completed(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1577 struct ath5k_txq
*txq
, struct ath5k_tx_status
*ts
)
1579 struct ieee80211_tx_info
*info
;
1583 ah
->stats
.tx_all_count
++;
1584 ah
->stats
.tx_bytes_count
+= skb
->len
;
1585 info
= IEEE80211_SKB_CB(skb
);
1587 tries
[0] = info
->status
.rates
[0].count
;
1588 tries
[1] = info
->status
.rates
[1].count
;
1589 tries
[2] = info
->status
.rates
[2].count
;
1591 ieee80211_tx_info_clear_status(info
);
1593 for (i
= 0; i
< ts
->ts_final_idx
; i
++) {
1594 struct ieee80211_tx_rate
*r
=
1595 &info
->status
.rates
[i
];
1597 r
->count
= tries
[i
];
1600 info
->status
.rates
[ts
->ts_final_idx
].count
= ts
->ts_final_retry
;
1601 info
->status
.rates
[ts
->ts_final_idx
+ 1].idx
= -1;
1603 if (unlikely(ts
->ts_status
)) {
1604 ah
->stats
.ack_fail
++;
1605 if (ts
->ts_status
& AR5K_TXERR_FILT
) {
1606 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1607 ah
->stats
.txerr_filt
++;
1609 if (ts
->ts_status
& AR5K_TXERR_XRETRY
)
1610 ah
->stats
.txerr_retry
++;
1611 if (ts
->ts_status
& AR5K_TXERR_FIFO
)
1612 ah
->stats
.txerr_fifo
++;
1614 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1615 info
->status
.ack_signal
= ts
->ts_rssi
;
1617 /* count the successful attempt as well */
1618 info
->status
.rates
[ts
->ts_final_idx
].count
++;
1622 * Remove MAC header padding before giving the frame
1625 ath5k_remove_padding(skb
);
1627 if (ts
->ts_antenna
> 0 && ts
->ts_antenna
< 5)
1628 ah
->stats
.antenna_tx
[ts
->ts_antenna
]++;
1630 ah
->stats
.antenna_tx
[0]++; /* invalid */
1632 trace_ath5k_tx_complete(ah
, skb
, txq
, ts
);
1633 ieee80211_tx_status(ah
->hw
, skb
);
1637 ath5k_tx_processq(struct ath5k_hw
*ah
, struct ath5k_txq
*txq
)
1639 struct ath5k_tx_status ts
= {};
1640 struct ath5k_buf
*bf
, *bf0
;
1641 struct ath5k_desc
*ds
;
1642 struct sk_buff
*skb
;
1645 spin_lock(&txq
->lock
);
1646 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1648 txq
->txq_poll_mark
= false;
1650 /* skb might already have been processed last time. */
1651 if (bf
->skb
!= NULL
) {
1654 ret
= ah
->ah_proc_tx_desc(ah
, ds
, &ts
);
1655 if (unlikely(ret
== -EINPROGRESS
))
1657 else if (unlikely(ret
)) {
1659 "error %d while processing "
1660 "queue %u\n", ret
, txq
->qnum
);
1667 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
,
1669 ath5k_tx_frame_completed(ah
, skb
, txq
, &ts
);
1673 * It's possible that the hardware can say the buffer is
1674 * completed when it hasn't yet loaded the ds_link from
1675 * host memory and moved on.
1676 * Always keep the last descriptor to avoid HW races...
1678 if (ath5k_hw_get_txdp(ah
, txq
->qnum
) != bf
->daddr
) {
1679 spin_lock(&ah
->txbuflock
);
1680 list_move_tail(&bf
->list
, &ah
->txbuf
);
1683 spin_unlock(&ah
->txbuflock
);
1686 spin_unlock(&txq
->lock
);
1687 if (txq
->txq_len
< ATH5K_TXQ_LEN_LOW
&& txq
->qnum
< 4)
1688 ieee80211_wake_queue(ah
->hw
, txq
->qnum
);
1692 ath5k_tasklet_tx(unsigned long data
)
1695 struct ath5k_hw
*ah
= (void *)data
;
1697 for (i
= 0; i
< AR5K_NUM_TX_QUEUES
; i
++)
1698 if (ah
->txqs
[i
].setup
&& (ah
->ah_txq_isr
& BIT(i
)))
1699 ath5k_tx_processq(ah
, &ah
->txqs
[i
]);
1701 ah
->tx_pending
= false;
1702 ath5k_set_current_imask(ah
);
1711 * Setup the beacon frame for transmit.
1714 ath5k_beacon_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
1716 struct sk_buff
*skb
= bf
->skb
;
1717 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1718 struct ath5k_desc
*ds
;
1722 const int padsize
= 0;
1724 bf
->skbaddr
= dma_map_single(ah
->dev
, skb
->data
, skb
->len
,
1726 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1727 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1728 (unsigned long long)bf
->skbaddr
);
1730 if (dma_mapping_error(ah
->dev
, bf
->skbaddr
)) {
1731 ATH5K_ERR(ah
, "beacon DMA mapping failed\n");
1736 antenna
= ah
->ah_tx_ant
;
1738 flags
= AR5K_TXDESC_NOACK
;
1739 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1740 ds
->ds_link
= bf
->daddr
; /* self-linked */
1741 flags
|= AR5K_TXDESC_VEOL
;
1746 * If we use multiple antennas on AP and use
1747 * the Sectored AP scenario, switch antenna every
1748 * 4 beacons to make sure everybody hears our AP.
1749 * When a client tries to associate, hw will keep
1750 * track of the tx antenna to be used for this client
1751 * automatically, based on ACKed packets.
1753 * Note: AP still listens and transmits RTS on the
1754 * default antenna which is supposed to be an omni.
1756 * Note2: On sectored scenarios it's possible to have
1757 * multiple antennas (1 omni -- the default -- and 14
1758 * sectors), so if we choose to actually support this
1759 * mode, we need to allow the user to set how many antennas
1760 * we have and tweak the code below to send beacons
1763 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
1764 antenna
= ah
->bsent
& 4 ? 2 : 1;
1767 /* FIXME: If we are in g mode and rate is a CCK rate
1768 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1769 * from tx power (value is in dB units already) */
1770 ds
->ds_data
= bf
->skbaddr
;
1771 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1772 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
1773 AR5K_PKT_TYPE_BEACON
, (ah
->power_level
* 2),
1774 ieee80211_get_tx_rate(ah
->hw
, info
)->hw_value
,
1775 1, AR5K_TXKEYIX_INVALID
,
1776 antenna
, flags
, 0, 0);
1782 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
1787 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1788 * this is called only once at config_bss time, for AP we do it every
1789 * SWBA interrupt so that the TIM will reflect buffered frames.
1791 * Called with the beacon lock.
1794 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
1797 struct ath5k_hw
*ah
= hw
->priv
;
1798 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
1799 struct sk_buff
*skb
;
1801 if (WARN_ON(!vif
)) {
1806 skb
= ieee80211_beacon_get(hw
, vif
);
1813 ath5k_txbuf_free_skb(ah
, avf
->bbuf
);
1814 avf
->bbuf
->skb
= skb
;
1815 ret
= ath5k_beacon_setup(ah
, avf
->bbuf
);
1817 avf
->bbuf
->skb
= NULL
;
1823 * Transmit a beacon frame at SWBA. Dynamic updates to the
1824 * frame contents are done as needed and the slot time is
1825 * also adjusted based on current state.
1827 * This is called from software irq context (beacontq tasklets)
1828 * or user context from ath5k_beacon_config.
1831 ath5k_beacon_send(struct ath5k_hw
*ah
)
1833 struct ieee80211_vif
*vif
;
1834 struct ath5k_vif
*avf
;
1835 struct ath5k_buf
*bf
;
1836 struct sk_buff
*skb
;
1838 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1841 * Check if the previous beacon has gone out. If
1842 * not, don't don't try to post another: skip this
1843 * period and wait for the next. Missed beacons
1844 * indicate a problem and should not occur. If we
1845 * miss too many consecutive beacons reset the device.
1847 if (unlikely(ath5k_hw_num_tx_pending(ah
, ah
->bhalq
) != 0)) {
1849 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1850 "missed %u consecutive beacons\n", ah
->bmisscount
);
1851 if (ah
->bmisscount
> 10) { /* NB: 10 is a guess */
1852 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1853 "stuck beacon time (%u missed)\n",
1855 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
1856 "stuck beacon, resetting\n");
1857 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
1861 if (unlikely(ah
->bmisscount
!= 0)) {
1862 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1863 "resume beacon xmit after %u misses\n",
1868 if ((ah
->opmode
== NL80211_IFTYPE_AP
&& ah
->num_ap_vifs
> 1) ||
1869 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1870 u64 tsf
= ath5k_hw_get_tsf64(ah
);
1871 u32 tsftu
= TSF_TO_TU(tsf
);
1872 int slot
= ((tsftu
% ah
->bintval
) * ATH_BCBUF
) / ah
->bintval
;
1873 vif
= ah
->bslot
[(slot
+ 1) % ATH_BCBUF
];
1874 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1875 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1876 (unsigned long long)tsf
, tsftu
, ah
->bintval
, slot
, vif
);
1877 } else /* only one interface */
1883 avf
= (void *)vif
->drv_priv
;
1885 if (unlikely(bf
->skb
== NULL
|| ah
->opmode
== NL80211_IFTYPE_STATION
||
1886 ah
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1887 ATH5K_WARN(ah
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1892 * Stop any current dma and put the new frame on the queue.
1893 * This should never fail since we check above that no frames
1894 * are still pending on the queue.
1896 if (unlikely(ath5k_hw_stop_beacon_queue(ah
, ah
->bhalq
))) {
1897 ATH5K_WARN(ah
, "beacon queue %u didn't start/stop ?\n", ah
->bhalq
);
1898 /* NB: hw still stops DMA, so proceed */
1901 /* refresh the beacon for AP or MESH mode */
1902 if (ah
->opmode
== NL80211_IFTYPE_AP
||
1903 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
)
1904 ath5k_beacon_update(ah
->hw
, vif
);
1906 trace_ath5k_tx(ah
, bf
->skb
, &ah
->txqs
[ah
->bhalq
]);
1908 ath5k_hw_set_txdp(ah
, ah
->bhalq
, bf
->daddr
);
1909 ath5k_hw_start_tx_dma(ah
, ah
->bhalq
);
1910 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
1911 ah
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
1913 skb
= ieee80211_get_buffered_bc(ah
->hw
, vif
);
1915 ath5k_tx_queue(ah
->hw
, skb
, ah
->cabq
);
1917 if (ah
->cabq
->txq_len
>= ah
->cabq
->txq_max
)
1920 skb
= ieee80211_get_buffered_bc(ah
->hw
, vif
);
1927 * ath5k_beacon_update_timers - update beacon timers
1929 * @ah: struct ath5k_hw pointer we are operating on
1930 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1931 * beacon timer update based on the current HW TSF.
1933 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1934 * of a received beacon or the current local hardware TSF and write it to the
1935 * beacon timer registers.
1937 * This is called in a variety of situations, e.g. when a beacon is received,
1938 * when a TSF update has been detected, but also when an new IBSS is created or
1939 * when we otherwise know we have to update the timers, but we keep it in this
1940 * function to have it all together in one place.
1943 ath5k_beacon_update_timers(struct ath5k_hw
*ah
, u64 bc_tsf
)
1945 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
1948 intval
= ah
->bintval
& AR5K_BEACON_PERIOD
;
1949 if (ah
->opmode
== NL80211_IFTYPE_AP
&& ah
->num_ap_vifs
> 1) {
1950 intval
/= ATH_BCBUF
; /* staggered multi-bss beacons */
1952 ATH5K_WARN(ah
, "intval %u is too low, min 15\n",
1955 if (WARN_ON(!intval
))
1958 /* beacon TSF converted to TU */
1959 bc_tu
= TSF_TO_TU(bc_tsf
);
1961 /* current TSF converted to TU */
1962 hw_tsf
= ath5k_hw_get_tsf64(ah
);
1963 hw_tu
= TSF_TO_TU(hw_tsf
);
1965 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1966 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1967 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1968 * configuration we need to make sure it is bigger than that. */
1972 * no beacons received, called internally.
1973 * just need to refresh timers based on HW TSF.
1975 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
1976 } else if (bc_tsf
== 0) {
1978 * no beacon received, probably called by ath5k_reset_tsf().
1979 * reset TSF to start with 0.
1982 intval
|= AR5K_BEACON_RESET_TSF
;
1983 } else if (bc_tsf
> hw_tsf
) {
1985 * beacon received, SW merge happened but HW TSF not yet updated.
1986 * not possible to reconfigure timers yet, but next time we
1987 * receive a beacon with the same BSSID, the hardware will
1988 * automatically update the TSF and then we need to reconfigure
1991 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1992 "need to wait for HW TSF sync\n");
1996 * most important case for beacon synchronization between STA.
1998 * beacon received and HW TSF has been already updated by HW.
1999 * update next TBTT based on the TSF of the beacon, but make
2000 * sure it is ahead of our local TSF timer.
2002 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2006 ah
->nexttbtt
= nexttbtt
;
2008 intval
|= AR5K_BEACON_ENA
;
2009 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2012 * debugging output last in order to preserve the time critical aspect
2016 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2017 "reconfigured timers based on HW TSF\n");
2018 else if (bc_tsf
== 0)
2019 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2020 "reset HW TSF and timers\n");
2022 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2023 "updated timers based on beacon TSF\n");
2025 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2026 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2027 (unsigned long long) bc_tsf
,
2028 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2029 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2030 intval
& AR5K_BEACON_PERIOD
,
2031 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2032 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2036 * ath5k_beacon_config - Configure the beacon queues and interrupts
2038 * @ah: struct ath5k_hw pointer we are operating on
2040 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2041 * interrupts to detect TSF updates only.
2044 ath5k_beacon_config(struct ath5k_hw
*ah
)
2046 unsigned long flags
;
2048 spin_lock_irqsave(&ah
->block
, flags
);
2050 ah
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2052 if (ah
->enable_beacon
) {
2054 * In IBSS mode we use a self-linked tx descriptor and let the
2055 * hardware send the beacons automatically. We have to load it
2057 * We use the SWBA interrupt only to keep track of the beacon
2058 * timers in order to detect automatic TSF updates.
2060 ath5k_beaconq_config(ah
);
2062 ah
->imask
|= AR5K_INT_SWBA
;
2064 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
2065 if (ath5k_hw_hasveol(ah
))
2066 ath5k_beacon_send(ah
);
2068 ath5k_beacon_update_timers(ah
, -1);
2070 ath5k_hw_stop_beacon_queue(ah
, ah
->bhalq
);
2073 ath5k_hw_set_imr(ah
, ah
->imask
);
2075 spin_unlock_irqrestore(&ah
->block
, flags
);
2078 static void ath5k_tasklet_beacon(unsigned long data
)
2080 struct ath5k_hw
*ah
= (struct ath5k_hw
*) data
;
2083 * Software beacon alert--time to send a beacon.
2085 * In IBSS mode we use this interrupt just to
2086 * keep track of the next TBTT (target beacon
2087 * transmission time) in order to detect whether
2088 * automatic TSF updates happened.
2090 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
2091 /* XXX: only if VEOL supported */
2092 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2093 ah
->nexttbtt
+= ah
->bintval
;
2094 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
2095 "SWBA nexttbtt: %x hw_tu: %x "
2099 (unsigned long long) tsf
);
2101 spin_lock(&ah
->block
);
2102 ath5k_beacon_send(ah
);
2103 spin_unlock(&ah
->block
);
2108 /********************\
2109 * Interrupt handling *
2110 \********************/
2113 ath5k_intr_calibration_poll(struct ath5k_hw
*ah
)
2115 if (time_is_before_eq_jiffies(ah
->ah_cal_next_ani
) &&
2116 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
)) {
2117 /* run ANI only when full calibration is not active */
2118 ah
->ah_cal_next_ani
= jiffies
+
2119 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2120 tasklet_schedule(&ah
->ani_tasklet
);
2122 } else if (time_is_before_eq_jiffies(ah
->ah_cal_next_full
)) {
2123 ah
->ah_cal_next_full
= jiffies
+
2124 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2125 tasklet_schedule(&ah
->calib
);
2127 /* we could use SWI to generate enough interrupts to meet our
2128 * calibration interval requirements, if necessary:
2129 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2133 ath5k_schedule_rx(struct ath5k_hw
*ah
)
2135 ah
->rx_pending
= true;
2136 tasklet_schedule(&ah
->rxtq
);
2140 ath5k_schedule_tx(struct ath5k_hw
*ah
)
2142 ah
->tx_pending
= true;
2143 tasklet_schedule(&ah
->txtq
);
2147 ath5k_intr(int irq
, void *dev_id
)
2149 struct ath5k_hw
*ah
= dev_id
;
2150 enum ath5k_int status
;
2151 unsigned int counter
= 1000;
2153 if (unlikely(test_bit(ATH_STAT_INVALID
, ah
->status
) ||
2154 ((ath5k_get_bus_type(ah
) != ATH_AHB
) &&
2155 !ath5k_hw_is_intr_pending(ah
))))
2159 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2160 ATH5K_DBG(ah
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2162 if (unlikely(status
& AR5K_INT_FATAL
)) {
2164 * Fatal errors are unrecoverable.
2165 * Typically these are caused by DMA errors.
2167 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2168 "fatal int, resetting\n");
2169 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2170 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2172 * Receive buffers are full. Either the bus is busy or
2173 * the CPU is not fast enough to process all received
2175 * Older chipsets need a reset to come out of this
2176 * condition, but we treat it as RX for newer chips.
2177 * We don't know exactly which versions need a reset -
2178 * this guess is copied from the HAL.
2180 ah
->stats
.rxorn_intr
++;
2181 if (ah
->ah_mac_srev
< AR5K_SREV_AR5212
) {
2182 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2183 "rx overrun, resetting\n");
2184 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2186 ath5k_schedule_rx(ah
);
2188 if (status
& AR5K_INT_SWBA
)
2189 tasklet_hi_schedule(&ah
->beacontq
);
2191 if (status
& AR5K_INT_RXEOL
) {
2193 * NB: the hardware should re-read the link when
2194 * RXE bit is written, but it doesn't work at
2195 * least on older hardware revs.
2197 ah
->stats
.rxeol_intr
++;
2199 if (status
& AR5K_INT_TXURN
) {
2200 /* bump tx trigger level */
2201 ath5k_hw_update_tx_triglevel(ah
, true);
2203 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2204 ath5k_schedule_rx(ah
);
2205 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2206 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2207 ath5k_schedule_tx(ah
);
2208 if (status
& AR5K_INT_BMISS
) {
2211 if (status
& AR5K_INT_MIB
) {
2212 ah
->stats
.mib_intr
++;
2213 ath5k_hw_update_mib_counters(ah
);
2214 ath5k_ani_mib_intr(ah
);
2216 if (status
& AR5K_INT_GPIO
)
2217 tasklet_schedule(&ah
->rf_kill
.toggleq
);
2221 if (ath5k_get_bus_type(ah
) == ATH_AHB
)
2224 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2226 if (ah
->rx_pending
|| ah
->tx_pending
)
2227 ath5k_set_current_imask(ah
);
2229 if (unlikely(!counter
))
2230 ATH5K_WARN(ah
, "too many interrupts, giving up for now\n");
2232 ath5k_intr_calibration_poll(ah
);
2238 * Periodically recalibrate the PHY to account
2239 * for temperature/environment changes.
2242 ath5k_tasklet_calibrate(unsigned long data
)
2244 struct ath5k_hw
*ah
= (void *)data
;
2246 /* Only full calibration for now */
2247 ah
->ah_cal_mask
|= AR5K_CALIBRATION_FULL
;
2249 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2250 ieee80211_frequency_to_channel(ah
->curchan
->center_freq
),
2251 ah
->curchan
->hw_value
);
2253 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2255 * Rfgain is out of bounds, reset the chip
2256 * to load new gain values.
2258 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2259 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2261 if (ath5k_hw_phy_calibrate(ah
, ah
->curchan
))
2262 ATH5K_ERR(ah
, "calibration of channel %u failed\n",
2263 ieee80211_frequency_to_channel(
2264 ah
->curchan
->center_freq
));
2266 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2268 * TODO: We should stop TX here, so that it doesn't interfere.
2269 * Note that stopping the queues is not enough to stop TX! */
2270 if (time_is_before_eq_jiffies(ah
->ah_cal_next_nf
)) {
2271 ah
->ah_cal_next_nf
= jiffies
+
2272 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF
);
2273 ath5k_hw_update_noise_floor(ah
);
2276 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_FULL
;
2281 ath5k_tasklet_ani(unsigned long data
)
2283 struct ath5k_hw
*ah
= (void *)data
;
2285 ah
->ah_cal_mask
|= AR5K_CALIBRATION_ANI
;
2286 ath5k_ani_calibration(ah
);
2287 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_ANI
;
2292 ath5k_tx_complete_poll_work(struct work_struct
*work
)
2294 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2295 tx_complete_work
.work
);
2296 struct ath5k_txq
*txq
;
2298 bool needreset
= false;
2300 mutex_lock(&ah
->lock
);
2302 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++) {
2303 if (ah
->txqs
[i
].setup
) {
2305 spin_lock_bh(&txq
->lock
);
2306 if (txq
->txq_len
> 1) {
2307 if (txq
->txq_poll_mark
) {
2308 ATH5K_DBG(ah
, ATH5K_DEBUG_XMIT
,
2309 "TX queue stuck %d\n",
2313 spin_unlock_bh(&txq
->lock
);
2316 txq
->txq_poll_mark
= true;
2319 spin_unlock_bh(&txq
->lock
);
2324 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2325 "TX queues stuck, resetting\n");
2326 ath5k_reset(ah
, NULL
, true);
2329 mutex_unlock(&ah
->lock
);
2331 ieee80211_queue_delayed_work(ah
->hw
, &ah
->tx_complete_work
,
2332 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2336 /*************************\
2337 * Initialization routines *
2338 \*************************/
2341 ath5k_init_ah(struct ath5k_hw
*ah
, const struct ath_bus_ops
*bus_ops
)
2343 struct ieee80211_hw
*hw
= ah
->hw
;
2344 struct ath_common
*common
;
2348 /* Initialize driver private data */
2349 SET_IEEE80211_DEV(hw
, ah
->dev
);
2350 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
2351 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2352 IEEE80211_HW_SIGNAL_DBM
|
2353 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
2355 hw
->wiphy
->interface_modes
=
2356 BIT(NL80211_IFTYPE_AP
) |
2357 BIT(NL80211_IFTYPE_STATION
) |
2358 BIT(NL80211_IFTYPE_ADHOC
) |
2359 BIT(NL80211_IFTYPE_MESH_POINT
);
2361 /* both antennas can be configured as RX or TX */
2362 hw
->wiphy
->available_antennas_tx
= 0x3;
2363 hw
->wiphy
->available_antennas_rx
= 0x3;
2365 hw
->extra_tx_headroom
= 2;
2366 hw
->channel_change_time
= 5000;
2369 * Mark the device as detached to avoid processing
2370 * interrupts until setup is complete.
2372 __set_bit(ATH_STAT_INVALID
, ah
->status
);
2374 ah
->opmode
= NL80211_IFTYPE_STATION
;
2376 mutex_init(&ah
->lock
);
2377 spin_lock_init(&ah
->rxbuflock
);
2378 spin_lock_init(&ah
->txbuflock
);
2379 spin_lock_init(&ah
->block
);
2380 spin_lock_init(&ah
->irqlock
);
2382 /* Setup interrupt handler */
2383 ret
= request_irq(ah
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", ah
);
2385 ATH5K_ERR(ah
, "request_irq failed\n");
2389 common
= ath5k_hw_common(ah
);
2390 common
->ops
= &ath5k_common_ops
;
2391 common
->bus_ops
= bus_ops
;
2395 common
->clockrate
= 40;
2398 * Cache line size is used to size and align various
2399 * structures used to communicate with the hardware.
2401 ath5k_read_cachesize(common
, &csz
);
2402 common
->cachelsz
= csz
<< 2; /* convert to bytes */
2404 spin_lock_init(&common
->cc_lock
);
2406 /* Initialize device */
2407 ret
= ath5k_hw_init(ah
);
2411 /* set up multi-rate retry capabilities */
2412 if (ah
->ah_version
== AR5K_AR5212
) {
2414 hw
->max_rate_tries
= max(AR5K_INIT_RETRY_SHORT
,
2415 AR5K_INIT_RETRY_LONG
);
2418 hw
->vif_data_size
= sizeof(struct ath5k_vif
);
2420 /* Finish private driver data initialization */
2421 ret
= ath5k_init(hw
);
2425 ATH5K_INFO(ah
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2426 ath5k_chip_name(AR5K_VERSION_MAC
, ah
->ah_mac_srev
),
2428 ah
->ah_phy_revision
);
2430 if (!ah
->ah_single_chip
) {
2431 /* Single chip radio (!RF5111) */
2432 if (ah
->ah_radio_5ghz_revision
&&
2433 !ah
->ah_radio_2ghz_revision
) {
2434 /* No 5GHz support -> report 2GHz radio */
2435 if (!test_bit(AR5K_MODE_11A
,
2436 ah
->ah_capabilities
.cap_mode
)) {
2437 ATH5K_INFO(ah
, "RF%s 2GHz radio found (0x%x)\n",
2438 ath5k_chip_name(AR5K_VERSION_RAD
,
2439 ah
->ah_radio_5ghz_revision
),
2440 ah
->ah_radio_5ghz_revision
);
2441 /* No 2GHz support (5110 and some
2442 * 5GHz only cards) -> report 5GHz radio */
2443 } else if (!test_bit(AR5K_MODE_11B
,
2444 ah
->ah_capabilities
.cap_mode
)) {
2445 ATH5K_INFO(ah
, "RF%s 5GHz radio found (0x%x)\n",
2446 ath5k_chip_name(AR5K_VERSION_RAD
,
2447 ah
->ah_radio_5ghz_revision
),
2448 ah
->ah_radio_5ghz_revision
);
2449 /* Multiband radio */
2451 ATH5K_INFO(ah
, "RF%s multiband radio found"
2453 ath5k_chip_name(AR5K_VERSION_RAD
,
2454 ah
->ah_radio_5ghz_revision
),
2455 ah
->ah_radio_5ghz_revision
);
2458 /* Multi chip radio (RF5111 - RF2111) ->
2459 * report both 2GHz/5GHz radios */
2460 else if (ah
->ah_radio_5ghz_revision
&&
2461 ah
->ah_radio_2ghz_revision
) {
2462 ATH5K_INFO(ah
, "RF%s 5GHz radio found (0x%x)\n",
2463 ath5k_chip_name(AR5K_VERSION_RAD
,
2464 ah
->ah_radio_5ghz_revision
),
2465 ah
->ah_radio_5ghz_revision
);
2466 ATH5K_INFO(ah
, "RF%s 2GHz radio found (0x%x)\n",
2467 ath5k_chip_name(AR5K_VERSION_RAD
,
2468 ah
->ah_radio_2ghz_revision
),
2469 ah
->ah_radio_2ghz_revision
);
2473 ath5k_debug_init_device(ah
);
2475 /* ready to process interrupts */
2476 __clear_bit(ATH_STAT_INVALID
, ah
->status
);
2480 ath5k_hw_deinit(ah
);
2482 free_irq(ah
->irq
, ah
);
2488 ath5k_stop_locked(struct ath5k_hw
*ah
)
2491 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2492 test_bit(ATH_STAT_INVALID
, ah
->status
));
2495 * Shutdown the hardware and driver:
2496 * stop output from above
2497 * disable interrupts
2499 * turn off the radio
2500 * clear transmit machinery
2501 * clear receive machinery
2502 * drain and release tx queues
2503 * reclaim beacon resources
2504 * power down hardware
2506 * Note that some of this work is not possible if the
2507 * hardware is gone (invalid).
2509 ieee80211_stop_queues(ah
->hw
);
2511 if (!test_bit(ATH_STAT_INVALID
, ah
->status
)) {
2513 ath5k_hw_set_imr(ah
, 0);
2514 synchronize_irq(ah
->irq
);
2516 ath5k_hw_dma_stop(ah
);
2517 ath5k_drain_tx_buffs(ah
);
2518 ath5k_hw_phy_disable(ah
);
2524 int ath5k_start(struct ieee80211_hw
*hw
)
2526 struct ath5k_hw
*ah
= hw
->priv
;
2527 struct ath_common
*common
= ath5k_hw_common(ah
);
2530 mutex_lock(&ah
->lock
);
2532 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "mode %d\n", ah
->opmode
);
2535 * Stop anything previously setup. This is safe
2536 * no matter this is the first time through or not.
2538 ath5k_stop_locked(ah
);
2541 * The basic interface to setting the hardware in a good
2542 * state is ``reset''. On return the hardware is known to
2543 * be powered up and with interrupts disabled. This must
2544 * be followed by initialization of the appropriate bits
2545 * and then setup of the interrupt mask.
2547 ah
->curchan
= ah
->hw
->conf
.channel
;
2548 ah
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2549 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2550 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
| AR5K_INT_MIB
;
2552 ret
= ath5k_reset(ah
, NULL
, false);
2556 ath5k_rfkill_hw_start(ah
);
2559 * Reset the key cache since some parts do not reset the
2560 * contents on initial power up or resume from suspend.
2562 for (i
= 0; i
< common
->keymax
; i
++)
2563 ath_hw_keyreset(common
, (u16
) i
);
2565 /* Use higher rates for acks instead of base
2567 ah
->ah_ack_bitrate_high
= true;
2569 for (i
= 0; i
< ARRAY_SIZE(ah
->bslot
); i
++)
2570 ah
->bslot
[i
] = NULL
;
2575 mutex_unlock(&ah
->lock
);
2577 ieee80211_queue_delayed_work(ah
->hw
, &ah
->tx_complete_work
,
2578 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2583 static void ath5k_stop_tasklets(struct ath5k_hw
*ah
)
2585 ah
->rx_pending
= false;
2586 ah
->tx_pending
= false;
2587 tasklet_kill(&ah
->rxtq
);
2588 tasklet_kill(&ah
->txtq
);
2589 tasklet_kill(&ah
->calib
);
2590 tasklet_kill(&ah
->beacontq
);
2591 tasklet_kill(&ah
->ani_tasklet
);
2595 * Stop the device, grabbing the top-level lock to protect
2596 * against concurrent entry through ath5k_init (which can happen
2597 * if another thread does a system call and the thread doing the
2598 * stop is preempted).
2600 void ath5k_stop(struct ieee80211_hw
*hw
)
2602 struct ath5k_hw
*ah
= hw
->priv
;
2605 mutex_lock(&ah
->lock
);
2606 ret
= ath5k_stop_locked(ah
);
2607 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, ah
->status
)) {
2609 * Don't set the card in full sleep mode!
2611 * a) When the device is in this state it must be carefully
2612 * woken up or references to registers in the PCI clock
2613 * domain may freeze the bus (and system). This varies
2614 * by chip and is mostly an issue with newer parts
2615 * (madwifi sources mentioned srev >= 0x78) that go to
2616 * sleep more quickly.
2618 * b) On older chips full sleep results a weird behaviour
2619 * during wakeup. I tested various cards with srev < 0x78
2620 * and they don't wake up after module reload, a second
2621 * module reload is needed to bring the card up again.
2623 * Until we figure out what's going on don't enable
2624 * full chip reset on any chip (this is what Legacy HAL
2625 * and Sam's HAL do anyway). Instead Perform a full reset
2626 * on the device (same as initial state after attach) and
2627 * leave it idle (keep MAC/BB on warm reset) */
2628 ret
= ath5k_hw_on_hold(ah
);
2630 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2631 "putting device to sleep\n");
2635 mutex_unlock(&ah
->lock
);
2637 ath5k_stop_tasklets(ah
);
2639 cancel_delayed_work_sync(&ah
->tx_complete_work
);
2641 ath5k_rfkill_hw_stop(ah
);
2645 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2646 * and change to the given channel.
2648 * This should be called with ah->lock.
2651 ath5k_reset(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
,
2654 struct ath_common
*common
= ath5k_hw_common(ah
);
2658 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "resetting\n");
2660 ath5k_hw_set_imr(ah
, 0);
2661 synchronize_irq(ah
->irq
);
2662 ath5k_stop_tasklets(ah
);
2664 /* Save ani mode and disable ANI during
2665 * reset. If we don't we might get false
2666 * PHY error interrupts. */
2667 ani_mode
= ah
->ani_state
.ani_mode
;
2668 ath5k_ani_init(ah
, ATH5K_ANI_MODE_OFF
);
2670 /* We are going to empty hw queues
2671 * so we should also free any remaining
2673 ath5k_drain_tx_buffs(ah
);
2677 fast
= ((chan
!= NULL
) && modparam_fastchanswitch
) ? 1 : 0;
2679 ret
= ath5k_hw_reset(ah
, ah
->opmode
, ah
->curchan
, fast
, skip_pcu
);
2681 ATH5K_ERR(ah
, "can't reset hardware (%d)\n", ret
);
2685 ret
= ath5k_rx_start(ah
);
2687 ATH5K_ERR(ah
, "can't start recv logic\n");
2691 ath5k_ani_init(ah
, ani_mode
);
2693 ah
->ah_cal_next_full
= jiffies
+ msecs_to_jiffies(100);
2694 ah
->ah_cal_next_ani
= jiffies
;
2695 ah
->ah_cal_next_nf
= jiffies
;
2696 ewma_init(&ah
->ah_beacon_rssi_avg
, 1024, 8);
2698 /* clear survey data and cycle counters */
2699 memset(&ah
->survey
, 0, sizeof(ah
->survey
));
2700 spin_lock_bh(&common
->cc_lock
);
2701 ath_hw_cycle_counters_update(common
);
2702 memset(&common
->cc_survey
, 0, sizeof(common
->cc_survey
));
2703 memset(&common
->cc_ani
, 0, sizeof(common
->cc_ani
));
2704 spin_unlock_bh(&common
->cc_lock
);
2707 * Change channels and update the h/w rate map if we're switching;
2708 * e.g. 11a to 11b/g.
2710 * We may be doing a reset in response to an ioctl that changes the
2711 * channel so update any state that might change as a result.
2715 /* ath5k_chan_change(ah, c); */
2717 ath5k_beacon_config(ah
);
2718 /* intrs are enabled by ath5k_beacon_config */
2720 ieee80211_wake_queues(ah
->hw
);
2727 static void ath5k_reset_work(struct work_struct
*work
)
2729 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2732 mutex_lock(&ah
->lock
);
2733 ath5k_reset(ah
, NULL
, true);
2734 mutex_unlock(&ah
->lock
);
2737 static int __devinit
2738 ath5k_init(struct ieee80211_hw
*hw
)
2741 struct ath5k_hw
*ah
= hw
->priv
;
2742 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2743 struct ath5k_txq
*txq
;
2744 u8 mac
[ETH_ALEN
] = {};
2749 * Check if the MAC has multi-rate retry support.
2750 * We do this by trying to setup a fake extended
2751 * descriptor. MACs that don't have support will
2752 * return false w/o doing anything. MACs that do
2753 * support it will return true w/o doing anything.
2755 ret
= ath5k_hw_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
2760 __set_bit(ATH_STAT_MRRETRY
, ah
->status
);
2763 * Collect the channel list. The 802.11 layer
2764 * is responsible for filtering this list based
2765 * on settings like the phy mode and regulatory
2766 * domain restrictions.
2768 ret
= ath5k_setup_bands(hw
);
2770 ATH5K_ERR(ah
, "can't get channels\n");
2775 * Allocate tx+rx descriptors and populate the lists.
2777 ret
= ath5k_desc_alloc(ah
);
2779 ATH5K_ERR(ah
, "can't allocate descriptors\n");
2784 * Allocate hardware transmit queues: one queue for
2785 * beacon frames and one data queue for each QoS
2786 * priority. Note that hw functions handle resetting
2787 * these queues at the needed time.
2789 ret
= ath5k_beaconq_setup(ah
);
2791 ATH5K_ERR(ah
, "can't setup a beacon xmit queue\n");
2795 ah
->cabq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_CAB
, 0);
2796 if (IS_ERR(ah
->cabq
)) {
2797 ATH5K_ERR(ah
, "can't setup cab queue\n");
2798 ret
= PTR_ERR(ah
->cabq
);
2802 /* 5211 and 5212 usually support 10 queues but we better rely on the
2803 * capability information */
2804 if (ah
->ah_capabilities
.cap_queues
.q_tx_num
>= 6) {
2805 /* This order matches mac80211's queue priority, so we can
2806 * directly use the mac80211 queue number without any mapping */
2807 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VO
);
2809 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2813 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VI
);
2815 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2819 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2821 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2825 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
2827 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2833 /* older hardware (5210) can only support one data queue */
2834 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2836 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2843 tasklet_init(&ah
->rxtq
, ath5k_tasklet_rx
, (unsigned long)ah
);
2844 tasklet_init(&ah
->txtq
, ath5k_tasklet_tx
, (unsigned long)ah
);
2845 tasklet_init(&ah
->calib
, ath5k_tasklet_calibrate
, (unsigned long)ah
);
2846 tasklet_init(&ah
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)ah
);
2847 tasklet_init(&ah
->ani_tasklet
, ath5k_tasklet_ani
, (unsigned long)ah
);
2849 INIT_WORK(&ah
->reset_work
, ath5k_reset_work
);
2850 INIT_DELAYED_WORK(&ah
->tx_complete_work
, ath5k_tx_complete_poll_work
);
2852 ret
= ath5k_hw_common(ah
)->bus_ops
->eeprom_read_mac(ah
, mac
);
2854 ATH5K_ERR(ah
, "unable to read address from EEPROM\n");
2858 SET_IEEE80211_PERM_ADDR(hw
, mac
);
2859 /* All MAC address bits matter for ACKs */
2860 ath5k_update_bssid_mask_and_opmode(ah
, NULL
);
2862 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
2863 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
2865 ATH5K_ERR(ah
, "can't initialize regulatory system\n");
2869 ret
= ieee80211_register_hw(hw
);
2871 ATH5K_ERR(ah
, "can't register ieee80211 hw\n");
2875 if (!ath_is_world_regd(regulatory
))
2876 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
2878 ath5k_init_leds(ah
);
2880 ath5k_sysfs_register(ah
);
2884 ath5k_txq_release(ah
);
2886 ath5k_hw_release_tx_queue(ah
, ah
->bhalq
);
2888 ath5k_desc_free(ah
);
2894 ath5k_deinit_ah(struct ath5k_hw
*ah
)
2896 struct ieee80211_hw
*hw
= ah
->hw
;
2899 * NB: the order of these is important:
2900 * o call the 802.11 layer before detaching ath5k_hw to
2901 * ensure callbacks into the driver to delete global
2902 * key cache entries can be handled
2903 * o reclaim the tx queue data structures after calling
2904 * the 802.11 layer as we'll get called back to reclaim
2905 * node state and potentially want to use them
2906 * o to cleanup the tx queues the hal is called, so detach
2908 * XXX: ??? detach ath5k_hw ???
2909 * Other than that, it's straightforward...
2911 ieee80211_unregister_hw(hw
);
2912 ath5k_desc_free(ah
);
2913 ath5k_txq_release(ah
);
2914 ath5k_hw_release_tx_queue(ah
, ah
->bhalq
);
2915 ath5k_unregister_leds(ah
);
2917 ath5k_sysfs_unregister(ah
);
2919 * NB: can't reclaim these until after ieee80211_ifdetach
2920 * returns because we'll get called back to reclaim node
2921 * state and potentially want to use them.
2923 ath5k_hw_deinit(ah
);
2924 free_irq(ah
->irq
, ah
);
2928 ath5k_any_vif_assoc(struct ath5k_hw
*ah
)
2930 struct ath5k_vif_iter_data iter_data
;
2931 iter_data
.hw_macaddr
= NULL
;
2932 iter_data
.any_assoc
= false;
2933 iter_data
.need_set_hw_addr
= false;
2934 iter_data
.found_active
= true;
2936 ieee80211_iterate_active_interfaces_atomic(ah
->hw
, ath5k_vif_iter
,
2938 return iter_data
.any_assoc
;
2942 ath5k_set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
2944 struct ath5k_hw
*ah
= hw
->priv
;
2946 rfilt
= ath5k_hw_get_rx_filter(ah
);
2948 rfilt
|= AR5K_RX_FILTER_BEACON
;
2950 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
2951 ath5k_hw_set_rx_filter(ah
, rfilt
);
2952 ah
->filter_flags
= rfilt
;