2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #include <linux/module.h>
46 #include <linux/delay.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/hardirq.h>
51 #include <linux/netdevice.h>
52 #include <linux/cache.h>
53 #include <linux/ethtool.h>
54 #include <linux/uaccess.h>
55 #include <linux/slab.h>
56 #include <linux/etherdevice.h>
57 #include <linux/nl80211.h>
59 #include <net/ieee80211_radiotap.h>
61 #include <asm/unaligned.h>
70 #define CREATE_TRACE_POINTS
73 bool ath5k_modparam_nohwcrypt
;
74 module_param_named(nohwcrypt
, ath5k_modparam_nohwcrypt
, bool, S_IRUGO
);
75 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
77 static bool modparam_fastchanswitch
;
78 module_param_named(fastchanswitch
, modparam_fastchanswitch
, bool, S_IRUGO
);
79 MODULE_PARM_DESC(fastchanswitch
, "Enable fast channel switching for AR2413/AR5413 radios.");
81 static bool ath5k_modparam_no_hw_rfkill_switch
;
82 module_param_named(no_hw_rfkill_switch
, ath5k_modparam_no_hw_rfkill_switch
,
84 MODULE_PARM_DESC(no_hw_rfkill_switch
, "Ignore the GPIO RFKill switch state");
88 MODULE_AUTHOR("Jiri Slaby");
89 MODULE_AUTHOR("Nick Kossifidis");
90 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
91 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
92 MODULE_LICENSE("Dual BSD/GPL");
94 static int ath5k_init(struct ieee80211_hw
*hw
);
95 static int ath5k_reset(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
,
99 static const struct ath5k_srev_name srev_names
[] = {
100 #ifdef CONFIG_ATHEROS_AR231X
101 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R2
},
102 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R7
},
103 { "2313", AR5K_VERSION_MAC
, AR5K_SREV_AR2313_R8
},
104 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R6
},
105 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R7
},
106 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R1
},
107 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R2
},
109 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
110 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
111 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
112 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
113 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
114 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
115 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
116 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
117 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
118 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
119 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
120 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
121 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
122 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
123 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
124 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
125 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
126 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
128 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
129 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
130 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
131 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
132 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
133 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
134 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
135 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
136 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
137 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
138 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
139 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
140 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
141 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
142 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
143 #ifdef CONFIG_ATHEROS_AR231X
144 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
145 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
147 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
150 static const struct ieee80211_rate ath5k_rates
[] = {
152 .hw_value
= ATH5K_RATE_CODE_1M
, },
154 .hw_value
= ATH5K_RATE_CODE_2M
,
155 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
156 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
158 .hw_value
= ATH5K_RATE_CODE_5_5M
,
159 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
160 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
162 .hw_value
= ATH5K_RATE_CODE_11M
,
163 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
164 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
166 .hw_value
= ATH5K_RATE_CODE_6M
,
169 .hw_value
= ATH5K_RATE_CODE_9M
,
172 .hw_value
= ATH5K_RATE_CODE_12M
,
175 .hw_value
= ATH5K_RATE_CODE_18M
,
178 .hw_value
= ATH5K_RATE_CODE_24M
,
181 .hw_value
= ATH5K_RATE_CODE_36M
,
184 .hw_value
= ATH5K_RATE_CODE_48M
,
187 .hw_value
= ATH5K_RATE_CODE_54M
,
191 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
193 u64 tsf
= ath5k_hw_get_tsf64(ah
);
195 if ((tsf
& 0x7fff) < rstamp
)
198 return (tsf
& ~0x7fff) | rstamp
;
202 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
204 const char *name
= "xxxxx";
207 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
208 if (srev_names
[i
].sr_type
!= type
)
211 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
212 name
= srev_names
[i
].sr_name
;
214 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
215 name
= srev_names
[i
].sr_name
;
222 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
224 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
225 return ath5k_hw_reg_read(ah
, reg_offset
);
228 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
230 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
231 ath5k_hw_reg_write(ah
, val
, reg_offset
);
234 static const struct ath_ops ath5k_common_ops
= {
235 .read
= ath5k_ioread32
,
236 .write
= ath5k_iowrite32
,
239 /***********************\
240 * Driver Initialization *
241 \***********************/
243 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
245 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
246 struct ath5k_hw
*ah
= hw
->priv
;
247 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
249 return ath_reg_notifier_apply(wiphy
, request
, regulatory
);
252 /********************\
253 * Channel/mode setup *
254 \********************/
257 * Returns true for the channel numbers used.
259 #ifdef CONFIG_ATH5K_TEST_CHANNELS
260 static bool ath5k_is_standard_channel(short chan
, enum ieee80211_band band
)
266 static bool ath5k_is_standard_channel(short chan
, enum ieee80211_band band
)
268 if (band
== IEEE80211_BAND_2GHZ
&& chan
<= 14)
271 return /* UNII 1,2 */
272 (((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
274 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
276 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165) ||
277 /* 802.11j 5.030-5.080 GHz (20MHz) */
278 (chan
== 8 || chan
== 12 || chan
== 16) ||
279 /* 802.11j 4.9GHz (20MHz) */
280 (chan
== 184 || chan
== 188 || chan
== 192 || chan
== 196));
285 ath5k_setup_channels(struct ath5k_hw
*ah
, struct ieee80211_channel
*channels
,
286 unsigned int mode
, unsigned int max
)
288 unsigned int count
, size
, freq
, ch
;
289 enum ieee80211_band band
;
293 /* 1..220, but 2GHz frequencies are filtered by check_channel */
295 band
= IEEE80211_BAND_5GHZ
;
300 band
= IEEE80211_BAND_2GHZ
;
303 ATH5K_WARN(ah
, "bad mode, not copying channels\n");
308 for (ch
= 1; ch
<= size
&& count
< max
; ch
++) {
309 freq
= ieee80211_channel_to_frequency(ch
, band
);
311 if (freq
== 0) /* mapping failed - not a standard channel */
314 /* Write channel info, needed for ath5k_channel_ok() */
315 channels
[count
].center_freq
= freq
;
316 channels
[count
].band
= band
;
317 channels
[count
].hw_value
= mode
;
319 /* Check if channel is supported by the chipset */
320 if (!ath5k_channel_ok(ah
, &channels
[count
]))
323 if (!ath5k_is_standard_channel(ch
, band
))
333 ath5k_setup_rate_idx(struct ath5k_hw
*ah
, struct ieee80211_supported_band
*b
)
337 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
338 ah
->rate_idx
[b
->band
][i
] = -1;
340 for (i
= 0; i
< b
->n_bitrates
; i
++) {
341 ah
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
342 if (b
->bitrates
[i
].hw_value_short
)
343 ah
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
348 ath5k_setup_bands(struct ieee80211_hw
*hw
)
350 struct ath5k_hw
*ah
= hw
->priv
;
351 struct ieee80211_supported_band
*sband
;
352 int max_c
, count_c
= 0;
355 BUILD_BUG_ON(ARRAY_SIZE(ah
->sbands
) < IEEE80211_NUM_BANDS
);
356 max_c
= ARRAY_SIZE(ah
->channels
);
359 sband
= &ah
->sbands
[IEEE80211_BAND_2GHZ
];
360 sband
->band
= IEEE80211_BAND_2GHZ
;
361 sband
->bitrates
= &ah
->rates
[IEEE80211_BAND_2GHZ
][0];
363 if (test_bit(AR5K_MODE_11G
, ah
->ah_capabilities
.cap_mode
)) {
365 memcpy(sband
->bitrates
, &ath5k_rates
[0],
366 sizeof(struct ieee80211_rate
) * 12);
367 sband
->n_bitrates
= 12;
369 sband
->channels
= ah
->channels
;
370 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
371 AR5K_MODE_11G
, max_c
);
373 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
374 count_c
= sband
->n_channels
;
376 } else if (test_bit(AR5K_MODE_11B
, ah
->ah_capabilities
.cap_mode
)) {
378 memcpy(sband
->bitrates
, &ath5k_rates
[0],
379 sizeof(struct ieee80211_rate
) * 4);
380 sband
->n_bitrates
= 4;
382 /* 5211 only supports B rates and uses 4bit rate codes
383 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
386 if (ah
->ah_version
== AR5K_AR5211
) {
387 for (i
= 0; i
< 4; i
++) {
388 sband
->bitrates
[i
].hw_value
=
389 sband
->bitrates
[i
].hw_value
& 0xF;
390 sband
->bitrates
[i
].hw_value_short
=
391 sband
->bitrates
[i
].hw_value_short
& 0xF;
395 sband
->channels
= ah
->channels
;
396 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
397 AR5K_MODE_11B
, max_c
);
399 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
400 count_c
= sband
->n_channels
;
403 ath5k_setup_rate_idx(ah
, sband
);
405 /* 5GHz band, A mode */
406 if (test_bit(AR5K_MODE_11A
, ah
->ah_capabilities
.cap_mode
)) {
407 sband
= &ah
->sbands
[IEEE80211_BAND_5GHZ
];
408 sband
->band
= IEEE80211_BAND_5GHZ
;
409 sband
->bitrates
= &ah
->rates
[IEEE80211_BAND_5GHZ
][0];
411 memcpy(sband
->bitrates
, &ath5k_rates
[4],
412 sizeof(struct ieee80211_rate
) * 8);
413 sband
->n_bitrates
= 8;
415 sband
->channels
= &ah
->channels
[count_c
];
416 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
417 AR5K_MODE_11A
, max_c
);
419 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
421 ath5k_setup_rate_idx(ah
, sband
);
423 ath5k_debug_dump_bands(ah
);
429 * Set/change channels. We always reset the chip.
430 * To accomplish this we must first cleanup any pending DMA,
431 * then restart stuff after a la ath5k_init.
433 * Called with ah->lock.
436 ath5k_chan_set(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
)
438 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
439 "channel set, resetting (%u -> %u MHz)\n",
440 ah
->curchan
->center_freq
, chan
->center_freq
);
443 * To switch channels clear any pending DMA operations;
444 * wait long enough for the RX fifo to drain, reset the
445 * hardware at the new frequency, and then re-enable
446 * the relevant bits of the h/w.
448 return ath5k_reset(ah
, chan
, true);
451 void ath5k_vif_iter(void *data
, u8
*mac
, struct ieee80211_vif
*vif
)
453 struct ath5k_vif_iter_data
*iter_data
= data
;
455 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
457 if (iter_data
->hw_macaddr
)
458 for (i
= 0; i
< ETH_ALEN
; i
++)
459 iter_data
->mask
[i
] &=
460 ~(iter_data
->hw_macaddr
[i
] ^ mac
[i
]);
462 if (!iter_data
->found_active
) {
463 iter_data
->found_active
= true;
464 memcpy(iter_data
->active_mac
, mac
, ETH_ALEN
);
467 if (iter_data
->need_set_hw_addr
&& iter_data
->hw_macaddr
)
468 if (ether_addr_equal(iter_data
->hw_macaddr
, mac
))
469 iter_data
->need_set_hw_addr
= false;
471 if (!iter_data
->any_assoc
) {
473 iter_data
->any_assoc
= true;
476 /* Calculate combined mode - when APs are active, operate in AP mode.
477 * Otherwise use the mode of the new interface. This can currently
478 * only deal with combinations of APs and STAs. Only one ad-hoc
479 * interfaces is allowed.
481 if (avf
->opmode
== NL80211_IFTYPE_AP
)
482 iter_data
->opmode
= NL80211_IFTYPE_AP
;
484 if (avf
->opmode
== NL80211_IFTYPE_STATION
)
486 if (iter_data
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
487 iter_data
->opmode
= avf
->opmode
;
492 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw
*ah
,
493 struct ieee80211_vif
*vif
)
495 struct ath_common
*common
= ath5k_hw_common(ah
);
496 struct ath5k_vif_iter_data iter_data
;
500 * Use the hardware MAC address as reference, the hardware uses it
501 * together with the BSSID mask when matching addresses.
503 iter_data
.hw_macaddr
= common
->macaddr
;
504 memset(&iter_data
.mask
, 0xff, ETH_ALEN
);
505 iter_data
.found_active
= false;
506 iter_data
.need_set_hw_addr
= true;
507 iter_data
.opmode
= NL80211_IFTYPE_UNSPECIFIED
;
508 iter_data
.n_stas
= 0;
511 ath5k_vif_iter(&iter_data
, vif
->addr
, vif
);
513 /* Get list of all active MAC addresses */
514 ieee80211_iterate_active_interfaces_atomic(
515 ah
->hw
, IEEE80211_IFACE_ITER_RESUME_ALL
,
516 ath5k_vif_iter
, &iter_data
);
517 memcpy(ah
->bssidmask
, iter_data
.mask
, ETH_ALEN
);
519 ah
->opmode
= iter_data
.opmode
;
520 if (ah
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
521 /* Nothing active, default to station mode */
522 ah
->opmode
= NL80211_IFTYPE_STATION
;
524 ath5k_hw_set_opmode(ah
, ah
->opmode
);
525 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "mode setup opmode %d (%s)\n",
526 ah
->opmode
, ath_opmode_to_string(ah
->opmode
));
528 if (iter_data
.need_set_hw_addr
&& iter_data
.found_active
)
529 ath5k_hw_set_lladdr(ah
, iter_data
.active_mac
);
531 if (ath5k_hw_hasbssidmask(ah
))
532 ath5k_hw_set_bssid_mask(ah
, ah
->bssidmask
);
534 /* Set up RX Filter */
535 if (iter_data
.n_stas
> 1) {
536 /* If you have multiple STA interfaces connected to
537 * different APs, ARPs are not received (most of the time?)
538 * Enabling PROMISC appears to fix that problem.
540 ah
->filter_flags
|= AR5K_RX_FILTER_PROM
;
543 rfilt
= ah
->filter_flags
;
544 ath5k_hw_set_rx_filter(ah
, rfilt
);
545 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
549 ath5k_hw_to_driver_rix(struct ath5k_hw
*ah
, int hw_rix
)
553 /* return base rate on errors */
554 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
555 "hw_rix out of bounds: %x\n", hw_rix
))
558 rix
= ah
->rate_idx
[ah
->curchan
->band
][hw_rix
];
559 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
570 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_hw
*ah
, dma_addr_t
*skb_addr
)
572 struct ath_common
*common
= ath5k_hw_common(ah
);
576 * Allocate buffer with headroom_needed space for the
577 * fake physical layer header at the start.
579 skb
= ath_rxbuf_alloc(common
,
584 ATH5K_ERR(ah
, "can't alloc skbuff of size %u\n",
589 *skb_addr
= dma_map_single(ah
->dev
,
590 skb
->data
, common
->rx_bufsize
,
593 if (unlikely(dma_mapping_error(ah
->dev
, *skb_addr
))) {
594 ATH5K_ERR(ah
, "%s: DMA mapping failed\n", __func__
);
602 ath5k_rxbuf_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
604 struct sk_buff
*skb
= bf
->skb
;
605 struct ath5k_desc
*ds
;
609 skb
= ath5k_rx_skb_alloc(ah
, &bf
->skbaddr
);
616 * Setup descriptors. For receive we always terminate
617 * the descriptor list with a self-linked entry so we'll
618 * not get overrun under high load (as can happen with a
619 * 5212 when ANI processing enables PHY error frames).
621 * To ensure the last descriptor is self-linked we create
622 * each descriptor as self-linked and add it to the end. As
623 * each additional descriptor is added the previous self-linked
624 * entry is "fixed" naturally. This should be safe even
625 * if DMA is happening. When processing RX interrupts we
626 * never remove/process the last, self-linked, entry on the
627 * descriptor list. This ensures the hardware always has
628 * someplace to write a new frame.
631 ds
->ds_link
= bf
->daddr
; /* link to self */
632 ds
->ds_data
= bf
->skbaddr
;
633 ret
= ath5k_hw_setup_rx_desc(ah
, ds
, ah
->common
.rx_bufsize
, 0);
635 ATH5K_ERR(ah
, "%s: could not setup RX desc\n", __func__
);
639 if (ah
->rxlink
!= NULL
)
640 *ah
->rxlink
= bf
->daddr
;
641 ah
->rxlink
= &ds
->ds_link
;
645 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
647 struct ieee80211_hdr
*hdr
;
648 enum ath5k_pkt_type htype
;
651 hdr
= (struct ieee80211_hdr
*)skb
->data
;
652 fc
= hdr
->frame_control
;
654 if (ieee80211_is_beacon(fc
))
655 htype
= AR5K_PKT_TYPE_BEACON
;
656 else if (ieee80211_is_probe_resp(fc
))
657 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
658 else if (ieee80211_is_atim(fc
))
659 htype
= AR5K_PKT_TYPE_ATIM
;
660 else if (ieee80211_is_pspoll(fc
))
661 htype
= AR5K_PKT_TYPE_PSPOLL
;
663 htype
= AR5K_PKT_TYPE_NORMAL
;
669 ath5k_txbuf_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
,
670 struct ath5k_txq
*txq
, int padsize
)
672 struct ath5k_desc
*ds
= bf
->desc
;
673 struct sk_buff
*skb
= bf
->skb
;
674 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
675 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
676 struct ieee80211_rate
*rate
;
677 unsigned int mrr_rate
[3], mrr_tries
[3];
684 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
687 bf
->skbaddr
= dma_map_single(ah
->dev
, skb
->data
, skb
->len
,
690 rate
= ieee80211_get_tx_rate(ah
->hw
, info
);
696 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
697 flags
|= AR5K_TXDESC_NOACK
;
699 rc_flags
= info
->control
.rates
[0].flags
;
700 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
701 rate
->hw_value_short
: rate
->hw_value
;
705 /* FIXME: If we are in g mode and rate is a CCK rate
706 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
707 * from tx power (value is in dB units already) */
708 if (info
->control
.hw_key
) {
709 keyidx
= info
->control
.hw_key
->hw_key_idx
;
710 pktlen
+= info
->control
.hw_key
->icv_len
;
712 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
713 flags
|= AR5K_TXDESC_RTSENA
;
714 cts_rate
= ieee80211_get_rts_cts_rate(ah
->hw
, info
)->hw_value
;
715 duration
= le16_to_cpu(ieee80211_rts_duration(ah
->hw
,
716 info
->control
.vif
, pktlen
, info
));
718 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
719 flags
|= AR5K_TXDESC_CTSENA
;
720 cts_rate
= ieee80211_get_rts_cts_rate(ah
->hw
, info
)->hw_value
;
721 duration
= le16_to_cpu(ieee80211_ctstoself_duration(ah
->hw
,
722 info
->control
.vif
, pktlen
, info
));
724 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
725 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
726 get_hw_packet_type(skb
),
727 (ah
->ah_txpower
.txp_requested
* 2),
729 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
734 /* Set up MRR descriptor */
735 if (ah
->ah_capabilities
.cap_has_mrr_support
) {
736 memset(mrr_rate
, 0, sizeof(mrr_rate
));
737 memset(mrr_tries
, 0, sizeof(mrr_tries
));
738 for (i
= 0; i
< 3; i
++) {
739 rate
= ieee80211_get_alt_retry_rate(ah
->hw
, info
, i
);
743 mrr_rate
[i
] = rate
->hw_value
;
744 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
747 ath5k_hw_setup_mrr_tx_desc(ah
, ds
,
748 mrr_rate
[0], mrr_tries
[0],
749 mrr_rate
[1], mrr_tries
[1],
750 mrr_rate
[2], mrr_tries
[2]);
754 ds
->ds_data
= bf
->skbaddr
;
756 spin_lock_bh(&txq
->lock
);
757 list_add_tail(&bf
->list
, &txq
->q
);
759 if (txq
->link
== NULL
) /* is this first packet? */
760 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
761 else /* no, so only link it */
762 *txq
->link
= bf
->daddr
;
764 txq
->link
= &ds
->ds_link
;
765 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
767 spin_unlock_bh(&txq
->lock
);
771 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
775 /*******************\
776 * Descriptors setup *
777 \*******************/
780 ath5k_desc_alloc(struct ath5k_hw
*ah
)
782 struct ath5k_desc
*ds
;
783 struct ath5k_buf
*bf
;
788 /* allocate descriptors */
789 ah
->desc_len
= sizeof(struct ath5k_desc
) *
790 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
792 ah
->desc
= dma_alloc_coherent(ah
->dev
, ah
->desc_len
,
793 &ah
->desc_daddr
, GFP_KERNEL
);
794 if (ah
->desc
== NULL
) {
795 ATH5K_ERR(ah
, "can't allocate descriptors\n");
801 ATH5K_DBG(ah
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
802 ds
, ah
->desc_len
, (unsigned long long)ah
->desc_daddr
);
804 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
805 sizeof(struct ath5k_buf
), GFP_KERNEL
);
807 ATH5K_ERR(ah
, "can't allocate bufptr\n");
813 INIT_LIST_HEAD(&ah
->rxbuf
);
814 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
817 list_add_tail(&bf
->list
, &ah
->rxbuf
);
820 INIT_LIST_HEAD(&ah
->txbuf
);
821 ah
->txbuf_len
= ATH_TXBUF
;
822 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
825 list_add_tail(&bf
->list
, &ah
->txbuf
);
829 INIT_LIST_HEAD(&ah
->bcbuf
);
830 for (i
= 0; i
< ATH_BCBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
833 list_add_tail(&bf
->list
, &ah
->bcbuf
);
838 dma_free_coherent(ah
->dev
, ah
->desc_len
, ah
->desc
, ah
->desc_daddr
);
845 ath5k_txbuf_free_skb(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
850 dma_unmap_single(ah
->dev
, bf
->skbaddr
, bf
->skb
->len
,
852 ieee80211_free_txskb(ah
->hw
, bf
->skb
);
855 bf
->desc
->ds_data
= 0;
859 ath5k_rxbuf_free_skb(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
861 struct ath_common
*common
= ath5k_hw_common(ah
);
866 dma_unmap_single(ah
->dev
, bf
->skbaddr
, common
->rx_bufsize
,
868 dev_kfree_skb_any(bf
->skb
);
871 bf
->desc
->ds_data
= 0;
875 ath5k_desc_free(struct ath5k_hw
*ah
)
877 struct ath5k_buf
*bf
;
879 list_for_each_entry(bf
, &ah
->txbuf
, list
)
880 ath5k_txbuf_free_skb(ah
, bf
);
881 list_for_each_entry(bf
, &ah
->rxbuf
, list
)
882 ath5k_rxbuf_free_skb(ah
, bf
);
883 list_for_each_entry(bf
, &ah
->bcbuf
, list
)
884 ath5k_txbuf_free_skb(ah
, bf
);
886 /* Free memory associated with all descriptors */
887 dma_free_coherent(ah
->dev
, ah
->desc_len
, ah
->desc
, ah
->desc_daddr
);
900 static struct ath5k_txq
*
901 ath5k_txq_setup(struct ath5k_hw
*ah
,
902 int qtype
, int subtype
)
904 struct ath5k_txq
*txq
;
905 struct ath5k_txq_info qi
= {
906 .tqi_subtype
= subtype
,
907 /* XXX: default values not correct for B and XR channels,
909 .tqi_aifs
= AR5K_TUNE_AIFS
,
910 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
911 .tqi_cw_max
= AR5K_TUNE_CWMAX
916 * Enable interrupts only for EOL and DESC conditions.
917 * We mark tx descriptors to receive a DESC interrupt
918 * when a tx queue gets deep; otherwise we wait for the
919 * EOL to reap descriptors. Note that this is done to
920 * reduce interrupt load and this only defers reaping
921 * descriptors, never transmitting frames. Aside from
922 * reducing interrupts this also permits more concurrency.
923 * The only potential downside is if the tx queue backs
924 * up in which case the top half of the kernel may backup
925 * due to a lack of tx descriptors.
927 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
928 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
929 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
932 * NB: don't print a message, this happens
933 * normally on parts with too few tx queues
935 return ERR_PTR(qnum
);
937 txq
= &ah
->txqs
[qnum
];
941 INIT_LIST_HEAD(&txq
->q
);
942 spin_lock_init(&txq
->lock
);
945 txq
->txq_max
= ATH5K_TXQ_LEN_MAX
;
946 txq
->txq_poll_mark
= false;
949 return &ah
->txqs
[qnum
];
953 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
955 struct ath5k_txq_info qi
= {
956 /* XXX: default values not correct for B and XR channels,
958 .tqi_aifs
= AR5K_TUNE_AIFS
,
959 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
960 .tqi_cw_max
= AR5K_TUNE_CWMAX
,
961 /* NB: for dynamic turbo, don't enable any other interrupts */
962 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
965 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
969 ath5k_beaconq_config(struct ath5k_hw
*ah
)
971 struct ath5k_txq_info qi
;
974 ret
= ath5k_hw_get_tx_queueprops(ah
, ah
->bhalq
, &qi
);
978 if (ah
->opmode
== NL80211_IFTYPE_AP
||
979 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
981 * Always burst out beacon and CAB traffic
982 * (aifs = cwmin = cwmax = 0)
987 } else if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
989 * Adhoc mode; backoff between 0 and (2 * cw_min).
993 qi
.tqi_cw_max
= 2 * AR5K_TUNE_CWMIN
;
996 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
997 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
998 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1000 ret
= ath5k_hw_set_tx_queueprops(ah
, ah
->bhalq
, &qi
);
1002 ATH5K_ERR(ah
, "%s: unable to update parameters for beacon "
1003 "hardware queue!\n", __func__
);
1006 ret
= ath5k_hw_reset_tx_queue(ah
, ah
->bhalq
); /* push to h/w */
1010 /* reconfigure cabq with ready time to 80% of beacon_interval */
1011 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1015 qi
.tqi_ready_time
= (ah
->bintval
* 80) / 100;
1016 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1020 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1026 * ath5k_drain_tx_buffs - Empty tx buffers
1028 * @ah The &struct ath5k_hw
1030 * Empty tx buffers from all queues in preparation
1031 * of a reset or during shutdown.
1033 * NB: this assumes output has been stopped and
1034 * we do not need to block ath5k_tx_tasklet
1037 ath5k_drain_tx_buffs(struct ath5k_hw
*ah
)
1039 struct ath5k_txq
*txq
;
1040 struct ath5k_buf
*bf
, *bf0
;
1043 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++) {
1044 if (ah
->txqs
[i
].setup
) {
1046 spin_lock_bh(&txq
->lock
);
1047 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1048 ath5k_debug_printtxbuf(ah
, bf
);
1050 ath5k_txbuf_free_skb(ah
, bf
);
1052 spin_lock(&ah
->txbuflock
);
1053 list_move_tail(&bf
->list
, &ah
->txbuf
);
1056 spin_unlock(&ah
->txbuflock
);
1059 txq
->txq_poll_mark
= false;
1060 spin_unlock_bh(&txq
->lock
);
1066 ath5k_txq_release(struct ath5k_hw
*ah
)
1068 struct ath5k_txq
*txq
= ah
->txqs
;
1071 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++, txq
++)
1073 ath5k_hw_release_tx_queue(ah
, txq
->qnum
);
1084 * Enable the receive h/w following a reset.
1087 ath5k_rx_start(struct ath5k_hw
*ah
)
1089 struct ath_common
*common
= ath5k_hw_common(ah
);
1090 struct ath5k_buf
*bf
;
1093 common
->rx_bufsize
= roundup(IEEE80211_MAX_FRAME_LEN
, common
->cachelsz
);
1095 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1096 common
->cachelsz
, common
->rx_bufsize
);
1098 spin_lock_bh(&ah
->rxbuflock
);
1100 list_for_each_entry(bf
, &ah
->rxbuf
, list
) {
1101 ret
= ath5k_rxbuf_setup(ah
, bf
);
1103 spin_unlock_bh(&ah
->rxbuflock
);
1107 bf
= list_first_entry(&ah
->rxbuf
, struct ath5k_buf
, list
);
1108 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1109 spin_unlock_bh(&ah
->rxbuflock
);
1111 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1112 ath5k_update_bssid_mask_and_opmode(ah
, NULL
); /* set filters, etc. */
1113 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1121 * Disable the receive logic on PCU (DRU)
1122 * In preparation for a shutdown.
1124 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1128 ath5k_rx_stop(struct ath5k_hw
*ah
)
1131 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1132 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1134 ath5k_debug_printrxbuffs(ah
);
1138 ath5k_rx_decrypted(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1139 struct ath5k_rx_status
*rs
)
1141 struct ath_common
*common
= ath5k_hw_common(ah
);
1142 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1143 unsigned int keyix
, hlen
;
1145 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1146 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1147 return RX_FLAG_DECRYPTED
;
1149 /* Apparently when a default key is used to decrypt the packet
1150 the hw does not set the index used to decrypt. In such cases
1151 get the index from the packet. */
1152 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1153 if (ieee80211_has_protected(hdr
->frame_control
) &&
1154 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1155 skb
->len
>= hlen
+ 4) {
1156 keyix
= skb
->data
[hlen
+ 3] >> 6;
1158 if (test_bit(keyix
, common
->keymap
))
1159 return RX_FLAG_DECRYPTED
;
1167 ath5k_check_ibss_tsf(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1168 struct ieee80211_rx_status
*rxs
)
1170 struct ath_common
*common
= ath5k_hw_common(ah
);
1173 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1175 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1176 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1177 ether_addr_equal(mgmt
->bssid
, common
->curbssid
)) {
1179 * Received an IBSS beacon with the same BSSID. Hardware *must*
1180 * have updated the local TSF. We have to work around various
1181 * hardware bugs, though...
1183 tsf
= ath5k_hw_get_tsf64(ah
);
1184 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1185 hw_tu
= TSF_TO_TU(tsf
);
1187 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1188 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1189 (unsigned long long)bc_tstamp
,
1190 (unsigned long long)rxs
->mactime
,
1191 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1192 (unsigned long long)tsf
);
1195 * Sometimes the HW will give us a wrong tstamp in the rx
1196 * status, causing the timestamp extension to go wrong.
1197 * (This seems to happen especially with beacon frames bigger
1198 * than 78 byte (incl. FCS))
1199 * But we know that the receive timestamp must be later than the
1200 * timestamp of the beacon since HW must have synced to that.
1202 * NOTE: here we assume mactime to be after the frame was
1203 * received, not like mac80211 which defines it at the start.
1205 if (bc_tstamp
> rxs
->mactime
) {
1206 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1207 "fixing mactime from %llx to %llx\n",
1208 (unsigned long long)rxs
->mactime
,
1209 (unsigned long long)tsf
);
1214 * Local TSF might have moved higher than our beacon timers,
1215 * in that case we have to update them to continue sending
1216 * beacons. This also takes care of synchronizing beacon sending
1217 * times with other stations.
1219 if (hw_tu
>= ah
->nexttbtt
)
1220 ath5k_beacon_update_timers(ah
, bc_tstamp
);
1222 /* Check if the beacon timers are still correct, because a TSF
1223 * update might have created a window between them - for a
1224 * longer description see the comment of this function: */
1225 if (!ath5k_hw_check_beacon_timers(ah
, ah
->bintval
)) {
1226 ath5k_beacon_update_timers(ah
, bc_tstamp
);
1227 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1228 "fixed beacon timers after beacon receive\n");
1234 ath5k_update_beacon_rssi(struct ath5k_hw
*ah
, struct sk_buff
*skb
, int rssi
)
1236 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1237 struct ath_common
*common
= ath5k_hw_common(ah
);
1239 /* only beacons from our BSSID */
1240 if (!ieee80211_is_beacon(mgmt
->frame_control
) ||
1241 !ether_addr_equal(mgmt
->bssid
, common
->curbssid
))
1244 ewma_add(&ah
->ah_beacon_rssi_avg
, rssi
);
1246 /* in IBSS mode we should keep RSSI statistics per neighbour */
1247 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1251 * Compute padding position. skb must contain an IEEE 802.11 frame
1253 static int ath5k_common_padpos(struct sk_buff
*skb
)
1255 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1256 __le16 frame_control
= hdr
->frame_control
;
1259 if (ieee80211_has_a4(frame_control
))
1262 if (ieee80211_is_data_qos(frame_control
))
1263 padpos
+= IEEE80211_QOS_CTL_LEN
;
1269 * This function expects an 802.11 frame and returns the number of
1270 * bytes added, or -1 if we don't have enough header room.
1272 static int ath5k_add_padding(struct sk_buff
*skb
)
1274 int padpos
= ath5k_common_padpos(skb
);
1275 int padsize
= padpos
& 3;
1277 if (padsize
&& skb
->len
> padpos
) {
1279 if (skb_headroom(skb
) < padsize
)
1282 skb_push(skb
, padsize
);
1283 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1291 * The MAC header is padded to have 32-bit boundary if the
1292 * packet payload is non-zero. The general calculation for
1293 * padsize would take into account odd header lengths:
1294 * padsize = 4 - (hdrlen & 3); however, since only
1295 * even-length headers are used, padding can only be 0 or 2
1296 * bytes and we can optimize this a bit. We must not try to
1297 * remove padding from short control frames that do not have a
1300 * This function expects an 802.11 frame and returns the number of
1303 static int ath5k_remove_padding(struct sk_buff
*skb
)
1305 int padpos
= ath5k_common_padpos(skb
);
1306 int padsize
= padpos
& 3;
1308 if (padsize
&& skb
->len
>= padpos
+ padsize
) {
1309 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1310 skb_pull(skb
, padsize
);
1318 ath5k_receive_frame(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1319 struct ath5k_rx_status
*rs
)
1321 struct ieee80211_rx_status
*rxs
;
1323 ath5k_remove_padding(skb
);
1325 rxs
= IEEE80211_SKB_RXCB(skb
);
1328 if (unlikely(rs
->rs_status
& AR5K_RXERR_MIC
))
1329 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
1332 * always extend the mac timestamp, since this information is
1333 * also needed for proper IBSS merging.
1335 * XXX: it might be too late to do it here, since rs_tstamp is
1336 * 15bit only. that means TSF extension has to be done within
1337 * 32768usec (about 32ms). it might be necessary to move this to
1338 * the interrupt handler, like it is done in madwifi.
1340 rxs
->mactime
= ath5k_extend_tsf(ah
, rs
->rs_tstamp
);
1341 rxs
->flag
|= RX_FLAG_MACTIME_END
;
1343 rxs
->freq
= ah
->curchan
->center_freq
;
1344 rxs
->band
= ah
->curchan
->band
;
1346 rxs
->signal
= ah
->ah_noise_floor
+ rs
->rs_rssi
;
1348 rxs
->antenna
= rs
->rs_antenna
;
1350 if (rs
->rs_antenna
> 0 && rs
->rs_antenna
< 5)
1351 ah
->stats
.antenna_rx
[rs
->rs_antenna
]++;
1353 ah
->stats
.antenna_rx
[0]++; /* invalid */
1355 rxs
->rate_idx
= ath5k_hw_to_driver_rix(ah
, rs
->rs_rate
);
1356 rxs
->flag
|= ath5k_rx_decrypted(ah
, skb
, rs
);
1358 if (rxs
->rate_idx
>= 0 && rs
->rs_rate
==
1359 ah
->sbands
[ah
->curchan
->band
].bitrates
[rxs
->rate_idx
].hw_value_short
)
1360 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1362 trace_ath5k_rx(ah
, skb
);
1364 ath5k_update_beacon_rssi(ah
, skb
, rs
->rs_rssi
);
1366 /* check beacons in IBSS mode */
1367 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
)
1368 ath5k_check_ibss_tsf(ah
, skb
, rxs
);
1370 ieee80211_rx(ah
->hw
, skb
);
1373 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1375 * Check if we want to further process this frame or not. Also update
1376 * statistics. Return true if we want this frame, false if not.
1379 ath5k_receive_frame_ok(struct ath5k_hw
*ah
, struct ath5k_rx_status
*rs
)
1381 ah
->stats
.rx_all_count
++;
1382 ah
->stats
.rx_bytes_count
+= rs
->rs_datalen
;
1384 if (unlikely(rs
->rs_status
)) {
1385 if (rs
->rs_status
& AR5K_RXERR_CRC
)
1386 ah
->stats
.rxerr_crc
++;
1387 if (rs
->rs_status
& AR5K_RXERR_FIFO
)
1388 ah
->stats
.rxerr_fifo
++;
1389 if (rs
->rs_status
& AR5K_RXERR_PHY
) {
1390 ah
->stats
.rxerr_phy
++;
1391 if (rs
->rs_phyerr
> 0 && rs
->rs_phyerr
< 32)
1392 ah
->stats
.rxerr_phy_code
[rs
->rs_phyerr
]++;
1395 if (rs
->rs_status
& AR5K_RXERR_DECRYPT
) {
1397 * Decrypt error. If the error occurred
1398 * because there was no hardware key, then
1399 * let the frame through so the upper layers
1400 * can process it. This is necessary for 5210
1401 * parts which have no way to setup a ``clear''
1404 * XXX do key cache faulting
1406 ah
->stats
.rxerr_decrypt
++;
1407 if (rs
->rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1408 !(rs
->rs_status
& AR5K_RXERR_CRC
))
1411 if (rs
->rs_status
& AR5K_RXERR_MIC
) {
1412 ah
->stats
.rxerr_mic
++;
1416 /* reject any frames with non-crypto errors */
1417 if (rs
->rs_status
& ~(AR5K_RXERR_DECRYPT
))
1421 if (unlikely(rs
->rs_more
)) {
1422 ah
->stats
.rxerr_jumbo
++;
1429 ath5k_set_current_imask(struct ath5k_hw
*ah
)
1431 enum ath5k_int imask
;
1432 unsigned long flags
;
1434 spin_lock_irqsave(&ah
->irqlock
, flags
);
1437 imask
&= ~AR5K_INT_RX_ALL
;
1439 imask
&= ~AR5K_INT_TX_ALL
;
1440 ath5k_hw_set_imr(ah
, imask
);
1441 spin_unlock_irqrestore(&ah
->irqlock
, flags
);
1445 ath5k_tasklet_rx(unsigned long data
)
1447 struct ath5k_rx_status rs
= {};
1448 struct sk_buff
*skb
, *next_skb
;
1449 dma_addr_t next_skb_addr
;
1450 struct ath5k_hw
*ah
= (void *)data
;
1451 struct ath_common
*common
= ath5k_hw_common(ah
);
1452 struct ath5k_buf
*bf
;
1453 struct ath5k_desc
*ds
;
1456 spin_lock(&ah
->rxbuflock
);
1457 if (list_empty(&ah
->rxbuf
)) {
1458 ATH5K_WARN(ah
, "empty rx buf pool\n");
1462 bf
= list_first_entry(&ah
->rxbuf
, struct ath5k_buf
, list
);
1463 BUG_ON(bf
->skb
== NULL
);
1467 /* bail if HW is still using self-linked descriptor */
1468 if (ath5k_hw_get_rxdp(ah
) == bf
->daddr
)
1471 ret
= ah
->ah_proc_rx_desc(ah
, ds
, &rs
);
1472 if (unlikely(ret
== -EINPROGRESS
))
1474 else if (unlikely(ret
)) {
1475 ATH5K_ERR(ah
, "error in processing rx descriptor\n");
1476 ah
->stats
.rxerr_proc
++;
1480 if (ath5k_receive_frame_ok(ah
, &rs
)) {
1481 next_skb
= ath5k_rx_skb_alloc(ah
, &next_skb_addr
);
1484 * If we can't replace bf->skb with a new skb under
1485 * memory pressure, just skip this packet
1490 dma_unmap_single(ah
->dev
, bf
->skbaddr
,
1494 skb_put(skb
, rs
.rs_datalen
);
1496 ath5k_receive_frame(ah
, skb
, &rs
);
1499 bf
->skbaddr
= next_skb_addr
;
1502 list_move_tail(&bf
->list
, &ah
->rxbuf
);
1503 } while (ath5k_rxbuf_setup(ah
, bf
) == 0);
1505 spin_unlock(&ah
->rxbuflock
);
1506 ah
->rx_pending
= false;
1507 ath5k_set_current_imask(ah
);
1516 ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1517 struct ath5k_txq
*txq
)
1519 struct ath5k_hw
*ah
= hw
->priv
;
1520 struct ath5k_buf
*bf
;
1521 unsigned long flags
;
1524 trace_ath5k_tx(ah
, skb
, txq
);
1527 * The hardware expects the header padded to 4 byte boundaries.
1528 * If this is not the case, we add the padding after the header.
1530 padsize
= ath5k_add_padding(skb
);
1532 ATH5K_ERR(ah
, "tx hdrlen not %%4: not enough"
1533 " headroom to pad");
1537 if (txq
->txq_len
>= txq
->txq_max
&&
1538 txq
->qnum
<= AR5K_TX_QUEUE_ID_DATA_MAX
)
1539 ieee80211_stop_queue(hw
, txq
->qnum
);
1541 spin_lock_irqsave(&ah
->txbuflock
, flags
);
1542 if (list_empty(&ah
->txbuf
)) {
1543 ATH5K_ERR(ah
, "no further txbuf available, dropping packet\n");
1544 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1545 ieee80211_stop_queues(hw
);
1548 bf
= list_first_entry(&ah
->txbuf
, struct ath5k_buf
, list
);
1549 list_del(&bf
->list
);
1551 if (list_empty(&ah
->txbuf
))
1552 ieee80211_stop_queues(hw
);
1553 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1557 if (ath5k_txbuf_setup(ah
, bf
, txq
, padsize
)) {
1559 spin_lock_irqsave(&ah
->txbuflock
, flags
);
1560 list_add_tail(&bf
->list
, &ah
->txbuf
);
1562 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1568 ieee80211_free_txskb(hw
, skb
);
1572 ath5k_tx_frame_completed(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1573 struct ath5k_txq
*txq
, struct ath5k_tx_status
*ts
)
1575 struct ieee80211_tx_info
*info
;
1579 ah
->stats
.tx_all_count
++;
1580 ah
->stats
.tx_bytes_count
+= skb
->len
;
1581 info
= IEEE80211_SKB_CB(skb
);
1583 tries
[0] = info
->status
.rates
[0].count
;
1584 tries
[1] = info
->status
.rates
[1].count
;
1585 tries
[2] = info
->status
.rates
[2].count
;
1587 ieee80211_tx_info_clear_status(info
);
1589 for (i
= 0; i
< ts
->ts_final_idx
; i
++) {
1590 struct ieee80211_tx_rate
*r
=
1591 &info
->status
.rates
[i
];
1593 r
->count
= tries
[i
];
1596 info
->status
.rates
[ts
->ts_final_idx
].count
= ts
->ts_final_retry
;
1597 info
->status
.rates
[ts
->ts_final_idx
+ 1].idx
= -1;
1599 if (unlikely(ts
->ts_status
)) {
1600 ah
->stats
.ack_fail
++;
1601 if (ts
->ts_status
& AR5K_TXERR_FILT
) {
1602 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1603 ah
->stats
.txerr_filt
++;
1605 if (ts
->ts_status
& AR5K_TXERR_XRETRY
)
1606 ah
->stats
.txerr_retry
++;
1607 if (ts
->ts_status
& AR5K_TXERR_FIFO
)
1608 ah
->stats
.txerr_fifo
++;
1610 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1611 info
->status
.ack_signal
= ts
->ts_rssi
;
1613 /* count the successful attempt as well */
1614 info
->status
.rates
[ts
->ts_final_idx
].count
++;
1618 * Remove MAC header padding before giving the frame
1621 ath5k_remove_padding(skb
);
1623 if (ts
->ts_antenna
> 0 && ts
->ts_antenna
< 5)
1624 ah
->stats
.antenna_tx
[ts
->ts_antenna
]++;
1626 ah
->stats
.antenna_tx
[0]++; /* invalid */
1628 trace_ath5k_tx_complete(ah
, skb
, txq
, ts
);
1629 ieee80211_tx_status(ah
->hw
, skb
);
1633 ath5k_tx_processq(struct ath5k_hw
*ah
, struct ath5k_txq
*txq
)
1635 struct ath5k_tx_status ts
= {};
1636 struct ath5k_buf
*bf
, *bf0
;
1637 struct ath5k_desc
*ds
;
1638 struct sk_buff
*skb
;
1641 spin_lock(&txq
->lock
);
1642 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1644 txq
->txq_poll_mark
= false;
1646 /* skb might already have been processed last time. */
1647 if (bf
->skb
!= NULL
) {
1650 ret
= ah
->ah_proc_tx_desc(ah
, ds
, &ts
);
1651 if (unlikely(ret
== -EINPROGRESS
))
1653 else if (unlikely(ret
)) {
1655 "error %d while processing "
1656 "queue %u\n", ret
, txq
->qnum
);
1663 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
,
1665 ath5k_tx_frame_completed(ah
, skb
, txq
, &ts
);
1669 * It's possible that the hardware can say the buffer is
1670 * completed when it hasn't yet loaded the ds_link from
1671 * host memory and moved on.
1672 * Always keep the last descriptor to avoid HW races...
1674 if (ath5k_hw_get_txdp(ah
, txq
->qnum
) != bf
->daddr
) {
1675 spin_lock(&ah
->txbuflock
);
1676 list_move_tail(&bf
->list
, &ah
->txbuf
);
1679 spin_unlock(&ah
->txbuflock
);
1682 spin_unlock(&txq
->lock
);
1683 if (txq
->txq_len
< ATH5K_TXQ_LEN_LOW
&& txq
->qnum
< 4)
1684 ieee80211_wake_queue(ah
->hw
, txq
->qnum
);
1688 ath5k_tasklet_tx(unsigned long data
)
1691 struct ath5k_hw
*ah
= (void *)data
;
1693 for (i
= 0; i
< AR5K_NUM_TX_QUEUES
; i
++)
1694 if (ah
->txqs
[i
].setup
&& (ah
->ah_txq_isr_txok_all
& BIT(i
)))
1695 ath5k_tx_processq(ah
, &ah
->txqs
[i
]);
1697 ah
->tx_pending
= false;
1698 ath5k_set_current_imask(ah
);
1707 * Setup the beacon frame for transmit.
1710 ath5k_beacon_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
1712 struct sk_buff
*skb
= bf
->skb
;
1713 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1714 struct ath5k_desc
*ds
;
1718 const int padsize
= 0;
1720 bf
->skbaddr
= dma_map_single(ah
->dev
, skb
->data
, skb
->len
,
1722 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1723 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1724 (unsigned long long)bf
->skbaddr
);
1726 if (dma_mapping_error(ah
->dev
, bf
->skbaddr
)) {
1727 ATH5K_ERR(ah
, "beacon DMA mapping failed\n");
1728 dev_kfree_skb_any(skb
);
1734 antenna
= ah
->ah_tx_ant
;
1736 flags
= AR5K_TXDESC_NOACK
;
1737 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1738 ds
->ds_link
= bf
->daddr
; /* self-linked */
1739 flags
|= AR5K_TXDESC_VEOL
;
1744 * If we use multiple antennas on AP and use
1745 * the Sectored AP scenario, switch antenna every
1746 * 4 beacons to make sure everybody hears our AP.
1747 * When a client tries to associate, hw will keep
1748 * track of the tx antenna to be used for this client
1749 * automatically, based on ACKed packets.
1751 * Note: AP still listens and transmits RTS on the
1752 * default antenna which is supposed to be an omni.
1754 * Note2: On sectored scenarios it's possible to have
1755 * multiple antennas (1 omni -- the default -- and 14
1756 * sectors), so if we choose to actually support this
1757 * mode, we need to allow the user to set how many antennas
1758 * we have and tweak the code below to send beacons
1761 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
1762 antenna
= ah
->bsent
& 4 ? 2 : 1;
1765 /* FIXME: If we are in g mode and rate is a CCK rate
1766 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1767 * from tx power (value is in dB units already) */
1768 ds
->ds_data
= bf
->skbaddr
;
1769 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1770 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
1771 AR5K_PKT_TYPE_BEACON
,
1772 (ah
->ah_txpower
.txp_requested
* 2),
1773 ieee80211_get_tx_rate(ah
->hw
, info
)->hw_value
,
1774 1, AR5K_TXKEYIX_INVALID
,
1775 antenna
, flags
, 0, 0);
1781 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
1786 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1787 * this is called only once at config_bss time, for AP we do it every
1788 * SWBA interrupt so that the TIM will reflect buffered frames.
1790 * Called with the beacon lock.
1793 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
1796 struct ath5k_hw
*ah
= hw
->priv
;
1797 struct ath5k_vif
*avf
;
1798 struct sk_buff
*skb
;
1800 if (WARN_ON(!vif
)) {
1805 skb
= ieee80211_beacon_get(hw
, vif
);
1812 avf
= (void *)vif
->drv_priv
;
1813 ath5k_txbuf_free_skb(ah
, avf
->bbuf
);
1814 avf
->bbuf
->skb
= skb
;
1815 ret
= ath5k_beacon_setup(ah
, avf
->bbuf
);
1821 * Transmit a beacon frame at SWBA. Dynamic updates to the
1822 * frame contents are done as needed and the slot time is
1823 * also adjusted based on current state.
1825 * This is called from software irq context (beacontq tasklets)
1826 * or user context from ath5k_beacon_config.
1829 ath5k_beacon_send(struct ath5k_hw
*ah
)
1831 struct ieee80211_vif
*vif
;
1832 struct ath5k_vif
*avf
;
1833 struct ath5k_buf
*bf
;
1834 struct sk_buff
*skb
;
1837 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1840 * Check if the previous beacon has gone out. If
1841 * not, don't don't try to post another: skip this
1842 * period and wait for the next. Missed beacons
1843 * indicate a problem and should not occur. If we
1844 * miss too many consecutive beacons reset the device.
1846 if (unlikely(ath5k_hw_num_tx_pending(ah
, ah
->bhalq
) != 0)) {
1848 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1849 "missed %u consecutive beacons\n", ah
->bmisscount
);
1850 if (ah
->bmisscount
> 10) { /* NB: 10 is a guess */
1851 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1852 "stuck beacon time (%u missed)\n",
1854 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
1855 "stuck beacon, resetting\n");
1856 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
1860 if (unlikely(ah
->bmisscount
!= 0)) {
1861 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1862 "resume beacon xmit after %u misses\n",
1867 if ((ah
->opmode
== NL80211_IFTYPE_AP
&& ah
->num_ap_vifs
+
1868 ah
->num_mesh_vifs
> 1) ||
1869 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1870 u64 tsf
= ath5k_hw_get_tsf64(ah
);
1871 u32 tsftu
= TSF_TO_TU(tsf
);
1872 int slot
= ((tsftu
% ah
->bintval
) * ATH_BCBUF
) / ah
->bintval
;
1873 vif
= ah
->bslot
[(slot
+ 1) % ATH_BCBUF
];
1874 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1875 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1876 (unsigned long long)tsf
, tsftu
, ah
->bintval
, slot
, vif
);
1877 } else /* only one interface */
1883 avf
= (void *)vif
->drv_priv
;
1887 * Stop any current dma and put the new frame on the queue.
1888 * This should never fail since we check above that no frames
1889 * are still pending on the queue.
1891 if (unlikely(ath5k_hw_stop_beacon_queue(ah
, ah
->bhalq
))) {
1892 ATH5K_WARN(ah
, "beacon queue %u didn't start/stop ?\n", ah
->bhalq
);
1893 /* NB: hw still stops DMA, so proceed */
1896 /* refresh the beacon for AP or MESH mode */
1897 if (ah
->opmode
== NL80211_IFTYPE_AP
||
1898 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1899 err
= ath5k_beacon_update(ah
->hw
, vif
);
1904 if (unlikely(bf
->skb
== NULL
|| ah
->opmode
== NL80211_IFTYPE_STATION
||
1905 ah
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1906 ATH5K_WARN(ah
, "bf=%p bf_skb=%p\n", bf
, bf
->skb
);
1910 trace_ath5k_tx(ah
, bf
->skb
, &ah
->txqs
[ah
->bhalq
]);
1912 ath5k_hw_set_txdp(ah
, ah
->bhalq
, bf
->daddr
);
1913 ath5k_hw_start_tx_dma(ah
, ah
->bhalq
);
1914 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
1915 ah
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
1917 skb
= ieee80211_get_buffered_bc(ah
->hw
, vif
);
1919 ath5k_tx_queue(ah
->hw
, skb
, ah
->cabq
);
1921 if (ah
->cabq
->txq_len
>= ah
->cabq
->txq_max
)
1924 skb
= ieee80211_get_buffered_bc(ah
->hw
, vif
);
1931 * ath5k_beacon_update_timers - update beacon timers
1933 * @ah: struct ath5k_hw pointer we are operating on
1934 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1935 * beacon timer update based on the current HW TSF.
1937 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1938 * of a received beacon or the current local hardware TSF and write it to the
1939 * beacon timer registers.
1941 * This is called in a variety of situations, e.g. when a beacon is received,
1942 * when a TSF update has been detected, but also when an new IBSS is created or
1943 * when we otherwise know we have to update the timers, but we keep it in this
1944 * function to have it all together in one place.
1947 ath5k_beacon_update_timers(struct ath5k_hw
*ah
, u64 bc_tsf
)
1949 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
1952 intval
= ah
->bintval
& AR5K_BEACON_PERIOD
;
1953 if (ah
->opmode
== NL80211_IFTYPE_AP
&& ah
->num_ap_vifs
1954 + ah
->num_mesh_vifs
> 1) {
1955 intval
/= ATH_BCBUF
; /* staggered multi-bss beacons */
1957 ATH5K_WARN(ah
, "intval %u is too low, min 15\n",
1960 if (WARN_ON(!intval
))
1963 /* beacon TSF converted to TU */
1964 bc_tu
= TSF_TO_TU(bc_tsf
);
1966 /* current TSF converted to TU */
1967 hw_tsf
= ath5k_hw_get_tsf64(ah
);
1968 hw_tu
= TSF_TO_TU(hw_tsf
);
1970 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1971 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1972 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1973 * configuration we need to make sure it is bigger than that. */
1977 * no beacons received, called internally.
1978 * just need to refresh timers based on HW TSF.
1980 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
1981 } else if (bc_tsf
== 0) {
1983 * no beacon received, probably called by ath5k_reset_tsf().
1984 * reset TSF to start with 0.
1987 intval
|= AR5K_BEACON_RESET_TSF
;
1988 } else if (bc_tsf
> hw_tsf
) {
1990 * beacon received, SW merge happened but HW TSF not yet updated.
1991 * not possible to reconfigure timers yet, but next time we
1992 * receive a beacon with the same BSSID, the hardware will
1993 * automatically update the TSF and then we need to reconfigure
1996 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1997 "need to wait for HW TSF sync\n");
2001 * most important case for beacon synchronization between STA.
2003 * beacon received and HW TSF has been already updated by HW.
2004 * update next TBTT based on the TSF of the beacon, but make
2005 * sure it is ahead of our local TSF timer.
2007 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2011 ah
->nexttbtt
= nexttbtt
;
2013 intval
|= AR5K_BEACON_ENA
;
2014 ath5k_hw_init_beacon_timers(ah
, nexttbtt
, intval
);
2017 * debugging output last in order to preserve the time critical aspect
2021 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2022 "reconfigured timers based on HW TSF\n");
2023 else if (bc_tsf
== 0)
2024 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2025 "reset HW TSF and timers\n");
2027 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2028 "updated timers based on beacon TSF\n");
2030 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2031 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2032 (unsigned long long) bc_tsf
,
2033 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2034 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2035 intval
& AR5K_BEACON_PERIOD
,
2036 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2037 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2041 * ath5k_beacon_config - Configure the beacon queues and interrupts
2043 * @ah: struct ath5k_hw pointer we are operating on
2045 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2046 * interrupts to detect TSF updates only.
2049 ath5k_beacon_config(struct ath5k_hw
*ah
)
2051 spin_lock_bh(&ah
->block
);
2053 ah
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2055 if (ah
->enable_beacon
) {
2057 * In IBSS mode we use a self-linked tx descriptor and let the
2058 * hardware send the beacons automatically. We have to load it
2060 * We use the SWBA interrupt only to keep track of the beacon
2061 * timers in order to detect automatic TSF updates.
2063 ath5k_beaconq_config(ah
);
2065 ah
->imask
|= AR5K_INT_SWBA
;
2067 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
2068 if (ath5k_hw_hasveol(ah
))
2069 ath5k_beacon_send(ah
);
2071 ath5k_beacon_update_timers(ah
, -1);
2073 ath5k_hw_stop_beacon_queue(ah
, ah
->bhalq
);
2076 ath5k_hw_set_imr(ah
, ah
->imask
);
2078 spin_unlock_bh(&ah
->block
);
2081 static void ath5k_tasklet_beacon(unsigned long data
)
2083 struct ath5k_hw
*ah
= (struct ath5k_hw
*) data
;
2086 * Software beacon alert--time to send a beacon.
2088 * In IBSS mode we use this interrupt just to
2089 * keep track of the next TBTT (target beacon
2090 * transmission time) in order to detect whether
2091 * automatic TSF updates happened.
2093 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
2094 /* XXX: only if VEOL supported */
2095 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2096 ah
->nexttbtt
+= ah
->bintval
;
2097 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
2098 "SWBA nexttbtt: %x hw_tu: %x "
2102 (unsigned long long) tsf
);
2104 spin_lock(&ah
->block
);
2105 ath5k_beacon_send(ah
);
2106 spin_unlock(&ah
->block
);
2111 /********************\
2112 * Interrupt handling *
2113 \********************/
2116 ath5k_intr_calibration_poll(struct ath5k_hw
*ah
)
2118 if (time_is_before_eq_jiffies(ah
->ah_cal_next_ani
) &&
2119 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
) &&
2120 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)) {
2122 /* Run ANI only when calibration is not active */
2124 ah
->ah_cal_next_ani
= jiffies
+
2125 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2126 tasklet_schedule(&ah
->ani_tasklet
);
2128 } else if (time_is_before_eq_jiffies(ah
->ah_cal_next_short
) &&
2129 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
) &&
2130 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)) {
2132 /* Run calibration only when another calibration
2135 * Note: This is for both full/short calibration,
2136 * if it's time for a full one, ath5k_calibrate_work will deal
2139 ah
->ah_cal_next_short
= jiffies
+
2140 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT
);
2141 ieee80211_queue_work(ah
->hw
, &ah
->calib_work
);
2143 /* we could use SWI to generate enough interrupts to meet our
2144 * calibration interval requirements, if necessary:
2145 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2149 ath5k_schedule_rx(struct ath5k_hw
*ah
)
2151 ah
->rx_pending
= true;
2152 tasklet_schedule(&ah
->rxtq
);
2156 ath5k_schedule_tx(struct ath5k_hw
*ah
)
2158 ah
->tx_pending
= true;
2159 tasklet_schedule(&ah
->txtq
);
2163 ath5k_intr(int irq
, void *dev_id
)
2165 struct ath5k_hw
*ah
= dev_id
;
2166 enum ath5k_int status
;
2167 unsigned int counter
= 1000;
2171 * If hw is not ready (or detached) and we get an
2172 * interrupt, or if we have no interrupts pending
2173 * (that means it's not for us) skip it.
2175 * NOTE: Group 0/1 PCI interface registers are not
2176 * supported on WiSOCs, so we can't check for pending
2177 * interrupts (ISR belongs to another register group
2180 if (unlikely(test_bit(ATH_STAT_INVALID
, ah
->status
) ||
2181 ((ath5k_get_bus_type(ah
) != ATH_AHB
) &&
2182 !ath5k_hw_is_intr_pending(ah
))))
2187 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2189 ATH5K_DBG(ah
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2193 * Fatal hw error -> Log and reset
2195 * Fatal errors are unrecoverable so we have to
2196 * reset the card. These errors include bus and
2199 if (unlikely(status
& AR5K_INT_FATAL
)) {
2201 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2202 "fatal int, resetting\n");
2203 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2206 * RX Overrun -> Count and reset if needed
2208 * Receive buffers are full. Either the bus is busy or
2209 * the CPU is not fast enough to process all received
2212 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2215 * Older chipsets need a reset to come out of this
2216 * condition, but we treat it as RX for newer chips.
2217 * We don't know exactly which versions need a reset
2218 * this guess is copied from the HAL.
2220 ah
->stats
.rxorn_intr
++;
2222 if (ah
->ah_mac_srev
< AR5K_SREV_AR5212
) {
2223 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2224 "rx overrun, resetting\n");
2225 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2227 ath5k_schedule_rx(ah
);
2231 /* Software Beacon Alert -> Schedule beacon tasklet */
2232 if (status
& AR5K_INT_SWBA
)
2233 tasklet_hi_schedule(&ah
->beacontq
);
2236 * No more RX descriptors -> Just count
2238 * NB: the hardware should re-read the link when
2239 * RXE bit is written, but it doesn't work at
2240 * least on older hardware revs.
2242 if (status
& AR5K_INT_RXEOL
)
2243 ah
->stats
.rxeol_intr
++;
2246 /* TX Underrun -> Bump tx trigger level */
2247 if (status
& AR5K_INT_TXURN
)
2248 ath5k_hw_update_tx_triglevel(ah
, true);
2250 /* RX -> Schedule rx tasklet */
2251 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2252 ath5k_schedule_rx(ah
);
2254 /* TX -> Schedule tx tasklet */
2255 if (status
& (AR5K_INT_TXOK
2259 ath5k_schedule_tx(ah
);
2261 /* Missed beacon -> TODO
2262 if (status & AR5K_INT_BMISS)
2265 /* MIB event -> Update counters and notify ANI */
2266 if (status
& AR5K_INT_MIB
) {
2267 ah
->stats
.mib_intr
++;
2268 ath5k_hw_update_mib_counters(ah
);
2269 ath5k_ani_mib_intr(ah
);
2272 /* GPIO -> Notify RFKill layer */
2273 if (status
& AR5K_INT_GPIO
)
2274 tasklet_schedule(&ah
->rf_kill
.toggleq
);
2278 if (ath5k_get_bus_type(ah
) == ATH_AHB
)
2281 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2284 * Until we handle rx/tx interrupts mask them on IMR
2286 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2287 * and unset after we 've handled the interrupts.
2289 if (ah
->rx_pending
|| ah
->tx_pending
)
2290 ath5k_set_current_imask(ah
);
2292 if (unlikely(!counter
))
2293 ATH5K_WARN(ah
, "too many interrupts, giving up for now\n");
2295 /* Fire up calibration poll */
2296 ath5k_intr_calibration_poll(ah
);
2302 * Periodically recalibrate the PHY to account
2303 * for temperature/environment changes.
2306 ath5k_calibrate_work(struct work_struct
*work
)
2308 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2311 /* Should we run a full calibration ? */
2312 if (time_is_before_eq_jiffies(ah
->ah_cal_next_full
)) {
2314 ah
->ah_cal_next_full
= jiffies
+
2315 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2316 ah
->ah_cal_mask
|= AR5K_CALIBRATION_FULL
;
2318 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
,
2319 "running full calibration\n");
2321 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2323 * Rfgain is out of bounds, reset the chip
2324 * to load new gain values.
2326 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2327 "got new rfgain, resetting\n");
2328 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2331 ah
->ah_cal_mask
|= AR5K_CALIBRATION_SHORT
;
2334 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2335 ieee80211_frequency_to_channel(ah
->curchan
->center_freq
),
2336 ah
->curchan
->hw_value
);
2338 if (ath5k_hw_phy_calibrate(ah
, ah
->curchan
))
2339 ATH5K_ERR(ah
, "calibration of channel %u failed\n",
2340 ieee80211_frequency_to_channel(
2341 ah
->curchan
->center_freq
));
2343 /* Clear calibration flags */
2344 if (ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
)
2345 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_FULL
;
2346 else if (ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)
2347 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_SHORT
;
2352 ath5k_tasklet_ani(unsigned long data
)
2354 struct ath5k_hw
*ah
= (void *)data
;
2356 ah
->ah_cal_mask
|= AR5K_CALIBRATION_ANI
;
2357 ath5k_ani_calibration(ah
);
2358 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_ANI
;
2363 ath5k_tx_complete_poll_work(struct work_struct
*work
)
2365 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2366 tx_complete_work
.work
);
2367 struct ath5k_txq
*txq
;
2369 bool needreset
= false;
2371 mutex_lock(&ah
->lock
);
2373 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++) {
2374 if (ah
->txqs
[i
].setup
) {
2376 spin_lock_bh(&txq
->lock
);
2377 if (txq
->txq_len
> 1) {
2378 if (txq
->txq_poll_mark
) {
2379 ATH5K_DBG(ah
, ATH5K_DEBUG_XMIT
,
2380 "TX queue stuck %d\n",
2384 spin_unlock_bh(&txq
->lock
);
2387 txq
->txq_poll_mark
= true;
2390 spin_unlock_bh(&txq
->lock
);
2395 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2396 "TX queues stuck, resetting\n");
2397 ath5k_reset(ah
, NULL
, true);
2400 mutex_unlock(&ah
->lock
);
2402 ieee80211_queue_delayed_work(ah
->hw
, &ah
->tx_complete_work
,
2403 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2407 /*************************\
2408 * Initialization routines *
2409 \*************************/
2411 static const struct ieee80211_iface_limit if_limits
[] = {
2412 { .max
= 2048, .types
= BIT(NL80211_IFTYPE_STATION
) },
2413 { .max
= 4, .types
=
2414 #ifdef CONFIG_MAC80211_MESH
2415 BIT(NL80211_IFTYPE_MESH_POINT
) |
2417 BIT(NL80211_IFTYPE_AP
) },
2420 static const struct ieee80211_iface_combination if_comb
= {
2421 .limits
= if_limits
,
2422 .n_limits
= ARRAY_SIZE(if_limits
),
2423 .max_interfaces
= 2048,
2424 .num_different_channels
= 1,
2428 ath5k_init_ah(struct ath5k_hw
*ah
, const struct ath_bus_ops
*bus_ops
)
2430 struct ieee80211_hw
*hw
= ah
->hw
;
2431 struct ath_common
*common
;
2435 /* Initialize driver private data */
2436 SET_IEEE80211_DEV(hw
, ah
->dev
);
2437 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
2438 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2439 IEEE80211_HW_SIGNAL_DBM
|
2440 IEEE80211_HW_MFP_CAPABLE
|
2441 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
2443 hw
->wiphy
->interface_modes
=
2444 BIT(NL80211_IFTYPE_AP
) |
2445 BIT(NL80211_IFTYPE_STATION
) |
2446 BIT(NL80211_IFTYPE_ADHOC
) |
2447 BIT(NL80211_IFTYPE_MESH_POINT
);
2449 hw
->wiphy
->iface_combinations
= &if_comb
;
2450 hw
->wiphy
->n_iface_combinations
= 1;
2452 /* SW support for IBSS_RSN is provided by mac80211 */
2453 hw
->wiphy
->flags
|= WIPHY_FLAG_IBSS_RSN
;
2455 /* both antennas can be configured as RX or TX */
2456 hw
->wiphy
->available_antennas_tx
= 0x3;
2457 hw
->wiphy
->available_antennas_rx
= 0x3;
2459 hw
->extra_tx_headroom
= 2;
2460 hw
->channel_change_time
= 5000;
2463 * Mark the device as detached to avoid processing
2464 * interrupts until setup is complete.
2466 __set_bit(ATH_STAT_INVALID
, ah
->status
);
2468 ah
->opmode
= NL80211_IFTYPE_STATION
;
2470 mutex_init(&ah
->lock
);
2471 spin_lock_init(&ah
->rxbuflock
);
2472 spin_lock_init(&ah
->txbuflock
);
2473 spin_lock_init(&ah
->block
);
2474 spin_lock_init(&ah
->irqlock
);
2476 /* Setup interrupt handler */
2477 ret
= request_irq(ah
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", ah
);
2479 ATH5K_ERR(ah
, "request_irq failed\n");
2483 common
= ath5k_hw_common(ah
);
2484 common
->ops
= &ath5k_common_ops
;
2485 common
->bus_ops
= bus_ops
;
2489 common
->clockrate
= 40;
2492 * Cache line size is used to size and align various
2493 * structures used to communicate with the hardware.
2495 ath5k_read_cachesize(common
, &csz
);
2496 common
->cachelsz
= csz
<< 2; /* convert to bytes */
2498 spin_lock_init(&common
->cc_lock
);
2500 /* Initialize device */
2501 ret
= ath5k_hw_init(ah
);
2505 /* Set up multi-rate retry capabilities */
2506 if (ah
->ah_capabilities
.cap_has_mrr_support
) {
2508 hw
->max_rate_tries
= max(AR5K_INIT_RETRY_SHORT
,
2509 AR5K_INIT_RETRY_LONG
);
2512 hw
->vif_data_size
= sizeof(struct ath5k_vif
);
2514 /* Finish private driver data initialization */
2515 ret
= ath5k_init(hw
);
2519 ATH5K_INFO(ah
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2520 ath5k_chip_name(AR5K_VERSION_MAC
, ah
->ah_mac_srev
),
2522 ah
->ah_phy_revision
);
2524 if (!ah
->ah_single_chip
) {
2525 /* Single chip radio (!RF5111) */
2526 if (ah
->ah_radio_5ghz_revision
&&
2527 !ah
->ah_radio_2ghz_revision
) {
2528 /* No 5GHz support -> report 2GHz radio */
2529 if (!test_bit(AR5K_MODE_11A
,
2530 ah
->ah_capabilities
.cap_mode
)) {
2531 ATH5K_INFO(ah
, "RF%s 2GHz radio found (0x%x)\n",
2532 ath5k_chip_name(AR5K_VERSION_RAD
,
2533 ah
->ah_radio_5ghz_revision
),
2534 ah
->ah_radio_5ghz_revision
);
2535 /* No 2GHz support (5110 and some
2536 * 5GHz only cards) -> report 5GHz radio */
2537 } else if (!test_bit(AR5K_MODE_11B
,
2538 ah
->ah_capabilities
.cap_mode
)) {
2539 ATH5K_INFO(ah
, "RF%s 5GHz radio found (0x%x)\n",
2540 ath5k_chip_name(AR5K_VERSION_RAD
,
2541 ah
->ah_radio_5ghz_revision
),
2542 ah
->ah_radio_5ghz_revision
);
2543 /* Multiband radio */
2545 ATH5K_INFO(ah
, "RF%s multiband radio found"
2547 ath5k_chip_name(AR5K_VERSION_RAD
,
2548 ah
->ah_radio_5ghz_revision
),
2549 ah
->ah_radio_5ghz_revision
);
2552 /* Multi chip radio (RF5111 - RF2111) ->
2553 * report both 2GHz/5GHz radios */
2554 else if (ah
->ah_radio_5ghz_revision
&&
2555 ah
->ah_radio_2ghz_revision
) {
2556 ATH5K_INFO(ah
, "RF%s 5GHz radio found (0x%x)\n",
2557 ath5k_chip_name(AR5K_VERSION_RAD
,
2558 ah
->ah_radio_5ghz_revision
),
2559 ah
->ah_radio_5ghz_revision
);
2560 ATH5K_INFO(ah
, "RF%s 2GHz radio found (0x%x)\n",
2561 ath5k_chip_name(AR5K_VERSION_RAD
,
2562 ah
->ah_radio_2ghz_revision
),
2563 ah
->ah_radio_2ghz_revision
);
2567 ath5k_debug_init_device(ah
);
2569 /* ready to process interrupts */
2570 __clear_bit(ATH_STAT_INVALID
, ah
->status
);
2574 ath5k_hw_deinit(ah
);
2576 free_irq(ah
->irq
, ah
);
2582 ath5k_stop_locked(struct ath5k_hw
*ah
)
2585 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2586 test_bit(ATH_STAT_INVALID
, ah
->status
));
2589 * Shutdown the hardware and driver:
2590 * stop output from above
2591 * disable interrupts
2593 * turn off the radio
2594 * clear transmit machinery
2595 * clear receive machinery
2596 * drain and release tx queues
2597 * reclaim beacon resources
2598 * power down hardware
2600 * Note that some of this work is not possible if the
2601 * hardware is gone (invalid).
2603 ieee80211_stop_queues(ah
->hw
);
2605 if (!test_bit(ATH_STAT_INVALID
, ah
->status
)) {
2607 ath5k_hw_set_imr(ah
, 0);
2608 synchronize_irq(ah
->irq
);
2610 ath5k_hw_dma_stop(ah
);
2611 ath5k_drain_tx_buffs(ah
);
2612 ath5k_hw_phy_disable(ah
);
2618 int ath5k_start(struct ieee80211_hw
*hw
)
2620 struct ath5k_hw
*ah
= hw
->priv
;
2621 struct ath_common
*common
= ath5k_hw_common(ah
);
2624 mutex_lock(&ah
->lock
);
2626 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "mode %d\n", ah
->opmode
);
2629 * Stop anything previously setup. This is safe
2630 * no matter this is the first time through or not.
2632 ath5k_stop_locked(ah
);
2635 * The basic interface to setting the hardware in a good
2636 * state is ``reset''. On return the hardware is known to
2637 * be powered up and with interrupts disabled. This must
2638 * be followed by initialization of the appropriate bits
2639 * and then setup of the interrupt mask.
2641 ah
->curchan
= ah
->hw
->conf
.channel
;
2642 ah
->imask
= AR5K_INT_RXOK
2652 ret
= ath5k_reset(ah
, NULL
, false);
2656 if (!ath5k_modparam_no_hw_rfkill_switch
)
2657 ath5k_rfkill_hw_start(ah
);
2660 * Reset the key cache since some parts do not reset the
2661 * contents on initial power up or resume from suspend.
2663 for (i
= 0; i
< common
->keymax
; i
++)
2664 ath_hw_keyreset(common
, (u16
) i
);
2666 /* Use higher rates for acks instead of base
2668 ah
->ah_ack_bitrate_high
= true;
2670 for (i
= 0; i
< ARRAY_SIZE(ah
->bslot
); i
++)
2671 ah
->bslot
[i
] = NULL
;
2676 mutex_unlock(&ah
->lock
);
2678 ieee80211_queue_delayed_work(ah
->hw
, &ah
->tx_complete_work
,
2679 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2684 static void ath5k_stop_tasklets(struct ath5k_hw
*ah
)
2686 ah
->rx_pending
= false;
2687 ah
->tx_pending
= false;
2688 tasklet_kill(&ah
->rxtq
);
2689 tasklet_kill(&ah
->txtq
);
2690 tasklet_kill(&ah
->beacontq
);
2691 tasklet_kill(&ah
->ani_tasklet
);
2695 * Stop the device, grabbing the top-level lock to protect
2696 * against concurrent entry through ath5k_init (which can happen
2697 * if another thread does a system call and the thread doing the
2698 * stop is preempted).
2700 void ath5k_stop(struct ieee80211_hw
*hw
)
2702 struct ath5k_hw
*ah
= hw
->priv
;
2705 mutex_lock(&ah
->lock
);
2706 ret
= ath5k_stop_locked(ah
);
2707 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, ah
->status
)) {
2709 * Don't set the card in full sleep mode!
2711 * a) When the device is in this state it must be carefully
2712 * woken up or references to registers in the PCI clock
2713 * domain may freeze the bus (and system). This varies
2714 * by chip and is mostly an issue with newer parts
2715 * (madwifi sources mentioned srev >= 0x78) that go to
2716 * sleep more quickly.
2718 * b) On older chips full sleep results a weird behaviour
2719 * during wakeup. I tested various cards with srev < 0x78
2720 * and they don't wake up after module reload, a second
2721 * module reload is needed to bring the card up again.
2723 * Until we figure out what's going on don't enable
2724 * full chip reset on any chip (this is what Legacy HAL
2725 * and Sam's HAL do anyway). Instead Perform a full reset
2726 * on the device (same as initial state after attach) and
2727 * leave it idle (keep MAC/BB on warm reset) */
2728 ret
= ath5k_hw_on_hold(ah
);
2730 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2731 "putting device to sleep\n");
2735 mutex_unlock(&ah
->lock
);
2737 ath5k_stop_tasklets(ah
);
2739 cancel_delayed_work_sync(&ah
->tx_complete_work
);
2741 if (!ath5k_modparam_no_hw_rfkill_switch
)
2742 ath5k_rfkill_hw_stop(ah
);
2746 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2747 * and change to the given channel.
2749 * This should be called with ah->lock.
2752 ath5k_reset(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
,
2755 struct ath_common
*common
= ath5k_hw_common(ah
);
2759 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "resetting\n");
2761 ath5k_hw_set_imr(ah
, 0);
2762 synchronize_irq(ah
->irq
);
2763 ath5k_stop_tasklets(ah
);
2765 /* Save ani mode and disable ANI during
2766 * reset. If we don't we might get false
2767 * PHY error interrupts. */
2768 ani_mode
= ah
->ani_state
.ani_mode
;
2769 ath5k_ani_init(ah
, ATH5K_ANI_MODE_OFF
);
2771 /* We are going to empty hw queues
2772 * so we should also free any remaining
2774 ath5k_drain_tx_buffs(ah
);
2778 fast
= ((chan
!= NULL
) && modparam_fastchanswitch
) ? 1 : 0;
2780 ret
= ath5k_hw_reset(ah
, ah
->opmode
, ah
->curchan
, fast
, skip_pcu
);
2782 ATH5K_ERR(ah
, "can't reset hardware (%d)\n", ret
);
2786 ret
= ath5k_rx_start(ah
);
2788 ATH5K_ERR(ah
, "can't start recv logic\n");
2792 ath5k_ani_init(ah
, ani_mode
);
2795 * Set calibration intervals
2797 * Note: We don't need to run calibration imediately
2798 * since some initial calibration is done on reset
2799 * even for fast channel switching. Also on scanning
2800 * this will get set again and again and it won't get
2801 * executed unless we connect somewhere and spend some
2802 * time on the channel (that's what calibration needs
2803 * anyway to be accurate).
2805 ah
->ah_cal_next_full
= jiffies
+
2806 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2807 ah
->ah_cal_next_ani
= jiffies
+
2808 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2809 ah
->ah_cal_next_short
= jiffies
+
2810 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT
);
2812 ewma_init(&ah
->ah_beacon_rssi_avg
, 1024, 8);
2814 /* clear survey data and cycle counters */
2815 memset(&ah
->survey
, 0, sizeof(ah
->survey
));
2816 spin_lock_bh(&common
->cc_lock
);
2817 ath_hw_cycle_counters_update(common
);
2818 memset(&common
->cc_survey
, 0, sizeof(common
->cc_survey
));
2819 memset(&common
->cc_ani
, 0, sizeof(common
->cc_ani
));
2820 spin_unlock_bh(&common
->cc_lock
);
2823 * Change channels and update the h/w rate map if we're switching;
2824 * e.g. 11a to 11b/g.
2826 * We may be doing a reset in response to an ioctl that changes the
2827 * channel so update any state that might change as a result.
2831 /* ath5k_chan_change(ah, c); */
2833 ath5k_beacon_config(ah
);
2834 /* intrs are enabled by ath5k_beacon_config */
2836 ieee80211_wake_queues(ah
->hw
);
2843 static void ath5k_reset_work(struct work_struct
*work
)
2845 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2848 mutex_lock(&ah
->lock
);
2849 ath5k_reset(ah
, NULL
, true);
2850 mutex_unlock(&ah
->lock
);
2854 ath5k_init(struct ieee80211_hw
*hw
)
2857 struct ath5k_hw
*ah
= hw
->priv
;
2858 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2859 struct ath5k_txq
*txq
;
2860 u8 mac
[ETH_ALEN
] = {};
2865 * Collect the channel list. The 802.11 layer
2866 * is responsible for filtering this list based
2867 * on settings like the phy mode and regulatory
2868 * domain restrictions.
2870 ret
= ath5k_setup_bands(hw
);
2872 ATH5K_ERR(ah
, "can't get channels\n");
2877 * Allocate tx+rx descriptors and populate the lists.
2879 ret
= ath5k_desc_alloc(ah
);
2881 ATH5K_ERR(ah
, "can't allocate descriptors\n");
2886 * Allocate hardware transmit queues: one queue for
2887 * beacon frames and one data queue for each QoS
2888 * priority. Note that hw functions handle resetting
2889 * these queues at the needed time.
2891 ret
= ath5k_beaconq_setup(ah
);
2893 ATH5K_ERR(ah
, "can't setup a beacon xmit queue\n");
2897 ah
->cabq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_CAB
, 0);
2898 if (IS_ERR(ah
->cabq
)) {
2899 ATH5K_ERR(ah
, "can't setup cab queue\n");
2900 ret
= PTR_ERR(ah
->cabq
);
2904 /* 5211 and 5212 usually support 10 queues but we better rely on the
2905 * capability information */
2906 if (ah
->ah_capabilities
.cap_queues
.q_tx_num
>= 6) {
2907 /* This order matches mac80211's queue priority, so we can
2908 * directly use the mac80211 queue number without any mapping */
2909 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VO
);
2911 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2915 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VI
);
2917 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2921 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2923 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2927 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
2929 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2935 /* older hardware (5210) can only support one data queue */
2936 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2938 ATH5K_ERR(ah
, "can't setup xmit queue\n");
2945 tasklet_init(&ah
->rxtq
, ath5k_tasklet_rx
, (unsigned long)ah
);
2946 tasklet_init(&ah
->txtq
, ath5k_tasklet_tx
, (unsigned long)ah
);
2947 tasklet_init(&ah
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)ah
);
2948 tasklet_init(&ah
->ani_tasklet
, ath5k_tasklet_ani
, (unsigned long)ah
);
2950 INIT_WORK(&ah
->reset_work
, ath5k_reset_work
);
2951 INIT_WORK(&ah
->calib_work
, ath5k_calibrate_work
);
2952 INIT_DELAYED_WORK(&ah
->tx_complete_work
, ath5k_tx_complete_poll_work
);
2954 ret
= ath5k_hw_common(ah
)->bus_ops
->eeprom_read_mac(ah
, mac
);
2956 ATH5K_ERR(ah
, "unable to read address from EEPROM\n");
2960 SET_IEEE80211_PERM_ADDR(hw
, mac
);
2961 /* All MAC address bits matter for ACKs */
2962 ath5k_update_bssid_mask_and_opmode(ah
, NULL
);
2964 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
2965 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
2967 ATH5K_ERR(ah
, "can't initialize regulatory system\n");
2971 ret
= ieee80211_register_hw(hw
);
2973 ATH5K_ERR(ah
, "can't register ieee80211 hw\n");
2977 if (!ath_is_world_regd(regulatory
))
2978 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
2980 ath5k_init_leds(ah
);
2982 ath5k_sysfs_register(ah
);
2986 ath5k_txq_release(ah
);
2988 ath5k_hw_release_tx_queue(ah
, ah
->bhalq
);
2990 ath5k_desc_free(ah
);
2996 ath5k_deinit_ah(struct ath5k_hw
*ah
)
2998 struct ieee80211_hw
*hw
= ah
->hw
;
3001 * NB: the order of these is important:
3002 * o call the 802.11 layer before detaching ath5k_hw to
3003 * ensure callbacks into the driver to delete global
3004 * key cache entries can be handled
3005 * o reclaim the tx queue data structures after calling
3006 * the 802.11 layer as we'll get called back to reclaim
3007 * node state and potentially want to use them
3008 * o to cleanup the tx queues the hal is called, so detach
3010 * XXX: ??? detach ath5k_hw ???
3011 * Other than that, it's straightforward...
3013 ieee80211_unregister_hw(hw
);
3014 ath5k_desc_free(ah
);
3015 ath5k_txq_release(ah
);
3016 ath5k_hw_release_tx_queue(ah
, ah
->bhalq
);
3017 ath5k_unregister_leds(ah
);
3019 ath5k_sysfs_unregister(ah
);
3021 * NB: can't reclaim these until after ieee80211_ifdetach
3022 * returns because we'll get called back to reclaim node
3023 * state and potentially want to use them.
3025 ath5k_hw_deinit(ah
);
3026 free_irq(ah
->irq
, ah
);
3030 ath5k_any_vif_assoc(struct ath5k_hw
*ah
)
3032 struct ath5k_vif_iter_data iter_data
;
3033 iter_data
.hw_macaddr
= NULL
;
3034 iter_data
.any_assoc
= false;
3035 iter_data
.need_set_hw_addr
= false;
3036 iter_data
.found_active
= true;
3038 ieee80211_iterate_active_interfaces_atomic(
3039 ah
->hw
, IEEE80211_IFACE_ITER_RESUME_ALL
,
3040 ath5k_vif_iter
, &iter_data
);
3041 return iter_data
.any_assoc
;
3045 ath5k_set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3047 struct ath5k_hw
*ah
= hw
->priv
;
3049 rfilt
= ath5k_hw_get_rx_filter(ah
);
3051 rfilt
|= AR5K_RX_FILTER_BEACON
;
3053 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3054 ath5k_hw_set_rx_filter(ah
, rfilt
);
3055 ah
->filter_flags
= rfilt
;
3058 void _ath5k_printk(const struct ath5k_hw
*ah
, const char *level
,
3059 const char *fmt
, ...)
3061 struct va_format vaf
;
3064 va_start(args
, fmt
);
3070 printk("%s" pr_fmt("%s: %pV"),
3071 level
, wiphy_name(ah
->hw
->wiphy
), &vaf
);
3073 printk("%s" pr_fmt("%pV"), level
, &vaf
);