2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static u8 ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt
;
64 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
65 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
67 static int modparam_all_channels
;
68 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
69 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table
[] = {
87 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
89 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
91 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
92 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
93 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS
, 0x001d), .driver_data
= AR5K_AR5212
}, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
110 static const struct ath5k_srev_name srev_names
[] = {
111 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
112 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
113 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
114 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
115 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
116 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
117 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
118 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
119 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
120 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
121 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
122 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
123 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
124 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
125 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
126 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
127 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
128 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
129 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
130 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
131 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
132 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
133 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
134 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
135 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
136 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
137 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
138 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
139 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
140 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
141 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
142 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
143 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
144 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
145 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
146 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
149 static const struct ieee80211_rate ath5k_rates
[] = {
151 .hw_value
= ATH5K_RATE_CODE_1M
, },
153 .hw_value
= ATH5K_RATE_CODE_2M
,
154 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
155 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
157 .hw_value
= ATH5K_RATE_CODE_5_5M
,
158 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
159 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
161 .hw_value
= ATH5K_RATE_CODE_11M
,
162 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
163 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
165 .hw_value
= ATH5K_RATE_CODE_6M
,
168 .hw_value
= ATH5K_RATE_CODE_9M
,
171 .hw_value
= ATH5K_RATE_CODE_12M
,
174 .hw_value
= ATH5K_RATE_CODE_18M
,
177 .hw_value
= ATH5K_RATE_CODE_24M
,
180 .hw_value
= ATH5K_RATE_CODE_36M
,
183 .hw_value
= ATH5K_RATE_CODE_48M
,
186 .hw_value
= ATH5K_RATE_CODE_54M
,
192 * Prototypes - PCI stack related functions
194 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
195 const struct pci_device_id
*id
);
196 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
198 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
200 static int ath5k_pci_resume(struct pci_dev
*pdev
);
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
206 static struct pci_driver ath5k_pci_driver
= {
207 .name
= KBUILD_MODNAME
,
208 .id_table
= ath5k_pci_id_table
,
209 .probe
= ath5k_pci_probe
,
210 .remove
= __devexit_p(ath5k_pci_remove
),
211 .suspend
= ath5k_pci_suspend
,
212 .resume
= ath5k_pci_resume
,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
221 static int ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
222 struct ath5k_txq
*txq
);
223 static int ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
);
224 static int ath5k_reset_wake(struct ath5k_softc
*sc
);
225 static int ath5k_start(struct ieee80211_hw
*hw
);
226 static void ath5k_stop(struct ieee80211_hw
*hw
);
227 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
228 struct ieee80211_if_init_conf
*conf
);
229 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
230 struct ieee80211_if_init_conf
*conf
);
231 static int ath5k_config(struct ieee80211_hw
*hw
, u32 changed
);
232 static u64
ath5k_prepare_multicast(struct ieee80211_hw
*hw
,
233 int mc_count
, struct dev_addr_list
*mc_list
);
234 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
235 unsigned int changed_flags
,
236 unsigned int *new_flags
,
238 static int ath5k_set_key(struct ieee80211_hw
*hw
,
239 enum set_key_cmd cmd
,
240 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
241 struct ieee80211_key_conf
*key
);
242 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
243 struct ieee80211_low_level_stats
*stats
);
244 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
245 struct ieee80211_tx_queue_stats
*stats
);
246 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
247 static void ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
);
248 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
249 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
250 struct ieee80211_vif
*vif
);
251 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
252 struct ieee80211_vif
*vif
,
253 struct ieee80211_bss_conf
*bss_conf
,
255 static void ath5k_sw_scan_start(struct ieee80211_hw
*hw
);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw
*hw
);
258 static const struct ieee80211_ops ath5k_hw_ops
= {
260 .start
= ath5k_start
,
262 .add_interface
= ath5k_add_interface
,
263 .remove_interface
= ath5k_remove_interface
,
264 .config
= ath5k_config
,
265 .prepare_multicast
= ath5k_prepare_multicast
,
266 .configure_filter
= ath5k_configure_filter
,
267 .set_key
= ath5k_set_key
,
268 .get_stats
= ath5k_get_stats
,
270 .get_tx_stats
= ath5k_get_tx_stats
,
271 .get_tsf
= ath5k_get_tsf
,
272 .set_tsf
= ath5k_set_tsf
,
273 .reset_tsf
= ath5k_reset_tsf
,
274 .bss_info_changed
= ath5k_bss_info_changed
,
275 .sw_scan_start
= ath5k_sw_scan_start
,
276 .sw_scan_complete
= ath5k_sw_scan_complete
,
280 * Prototypes - Internal functions
283 static int ath5k_attach(struct pci_dev
*pdev
,
284 struct ieee80211_hw
*hw
);
285 static void ath5k_detach(struct pci_dev
*pdev
,
286 struct ieee80211_hw
*hw
);
287 /* Channel/mode setup */
288 static inline short ath5k_ieee2mhz(short chan
);
289 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
290 struct ieee80211_channel
*channels
,
293 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
294 static int ath5k_chan_set(struct ath5k_softc
*sc
,
295 struct ieee80211_channel
*chan
);
296 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
298 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
300 /* Descriptor setup */
301 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
302 struct pci_dev
*pdev
);
303 static void ath5k_desc_free(struct ath5k_softc
*sc
,
304 struct pci_dev
*pdev
);
306 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
307 struct ath5k_buf
*bf
);
308 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
309 struct ath5k_buf
*bf
,
310 struct ath5k_txq
*txq
);
311 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
312 struct ath5k_buf
*bf
)
317 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
319 dev_kfree_skb_any(bf
->skb
);
323 static inline void ath5k_rxbuf_free(struct ath5k_softc
*sc
,
324 struct ath5k_buf
*bf
)
329 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
331 dev_kfree_skb_any(bf
->skb
);
337 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
338 int qtype
, int subtype
);
339 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
340 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
341 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
342 struct ath5k_txq
*txq
);
343 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
344 static void ath5k_txq_release(struct ath5k_softc
*sc
);
346 static int ath5k_rx_start(struct ath5k_softc
*sc
);
347 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
348 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
349 struct ath5k_desc
*ds
,
351 struct ath5k_rx_status
*rs
);
352 static void ath5k_tasklet_rx(unsigned long data
);
354 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
355 struct ath5k_txq
*txq
);
356 static void ath5k_tasklet_tx(unsigned long data
);
357 /* Beacon handling */
358 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
359 struct ath5k_buf
*bf
);
360 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
361 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
362 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
363 static void ath5k_tasklet_beacon(unsigned long data
);
365 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
367 u64 tsf
= ath5k_hw_get_tsf64(ah
);
369 if ((tsf
& 0x7fff) < rstamp
)
372 return (tsf
& ~0x7fff) | rstamp
;
375 /* Interrupt handling */
376 static int ath5k_init(struct ath5k_softc
*sc
);
377 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
378 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
379 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
380 static void ath5k_tasklet_reset(unsigned long data
);
382 static void ath5k_tasklet_calibrate(unsigned long data
);
385 * Module init/exit functions
394 ret
= pci_register_driver(&ath5k_pci_driver
);
396 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
406 pci_unregister_driver(&ath5k_pci_driver
);
408 ath5k_debug_finish();
411 module_init(init_ath5k_pci
);
412 module_exit(exit_ath5k_pci
);
415 /********************\
416 * PCI Initialization *
417 \********************/
420 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
422 const char *name
= "xxxxx";
425 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
426 if (srev_names
[i
].sr_type
!= type
)
429 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
430 name
= srev_names
[i
].sr_name
;
432 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
433 name
= srev_names
[i
].sr_name
;
442 ath5k_pci_probe(struct pci_dev
*pdev
,
443 const struct pci_device_id
*id
)
446 struct ath5k_softc
*sc
;
447 struct ieee80211_hw
*hw
;
451 ret
= pci_enable_device(pdev
);
453 dev_err(&pdev
->dev
, "can't enable device\n");
457 /* XXX 32-bit addressing only */
458 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
460 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
465 * Cache line size is used to size and align various
466 * structures used to communicate with the hardware.
468 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
471 * Linux 2.4.18 (at least) writes the cache line size
472 * register as a 16-bit wide register which is wrong.
473 * We must have this setup properly for rx buffer
474 * DMA to work so force a reasonable value here if it
477 csz
= L1_CACHE_BYTES
>> 2;
478 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
481 * The default setting of latency timer yields poor results,
482 * set it to the value used by other systems. It may be worth
483 * tweaking this setting more.
485 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
487 /* Enable bus mastering */
488 pci_set_master(pdev
);
491 * Disable the RETRY_TIMEOUT register (0x41) to keep
492 * PCI Tx retries from interfering with C3 CPU state.
494 pci_write_config_byte(pdev
, 0x41, 0);
496 ret
= pci_request_region(pdev
, 0, "ath5k");
498 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
502 mem
= pci_iomap(pdev
, 0, 0);
504 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
510 * Allocate hw (mac80211 main struct)
511 * and hw->priv (driver private data)
513 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
515 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
520 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
522 /* Initialize driver private data */
523 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
524 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
525 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
526 IEEE80211_HW_SIGNAL_DBM
|
527 IEEE80211_HW_NOISE_DBM
;
529 hw
->wiphy
->interface_modes
=
530 BIT(NL80211_IFTYPE_AP
) |
531 BIT(NL80211_IFTYPE_STATION
) |
532 BIT(NL80211_IFTYPE_ADHOC
) |
533 BIT(NL80211_IFTYPE_MESH_POINT
);
535 hw
->extra_tx_headroom
= 2;
536 hw
->channel_change_time
= 5000;
541 ath5k_debug_init_device(sc
);
544 * Mark the device as detached to avoid processing
545 * interrupts until setup is complete.
547 __set_bit(ATH_STAT_INVALID
, sc
->status
);
549 sc
->iobase
= mem
; /* So we can unmap it on detach */
550 sc
->common
.cachelsz
= csz
<< 2; /* convert to bytes */
551 sc
->opmode
= NL80211_IFTYPE_STATION
;
553 mutex_init(&sc
->lock
);
554 spin_lock_init(&sc
->rxbuflock
);
555 spin_lock_init(&sc
->txbuflock
);
556 spin_lock_init(&sc
->block
);
558 /* Set private data */
559 pci_set_drvdata(pdev
, hw
);
561 /* Setup interrupt handler */
562 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
564 ATH5K_ERR(sc
, "request_irq failed\n");
568 /* Initialize device */
569 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
570 if (IS_ERR(sc
->ah
)) {
571 ret
= PTR_ERR(sc
->ah
);
575 /* set up multi-rate retry capabilities */
576 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
578 hw
->max_rate_tries
= 11;
581 /* Finish private driver data initialization */
582 ret
= ath5k_attach(pdev
, hw
);
586 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
587 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
589 sc
->ah
->ah_phy_revision
);
591 if (!sc
->ah
->ah_single_chip
) {
592 /* Single chip radio (!RF5111) */
593 if (sc
->ah
->ah_radio_5ghz_revision
&&
594 !sc
->ah
->ah_radio_2ghz_revision
) {
595 /* No 5GHz support -> report 2GHz radio */
596 if (!test_bit(AR5K_MODE_11A
,
597 sc
->ah
->ah_capabilities
.cap_mode
)) {
598 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
599 ath5k_chip_name(AR5K_VERSION_RAD
,
600 sc
->ah
->ah_radio_5ghz_revision
),
601 sc
->ah
->ah_radio_5ghz_revision
);
602 /* No 2GHz support (5110 and some
603 * 5Ghz only cards) -> report 5Ghz radio */
604 } else if (!test_bit(AR5K_MODE_11B
,
605 sc
->ah
->ah_capabilities
.cap_mode
)) {
606 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
607 ath5k_chip_name(AR5K_VERSION_RAD
,
608 sc
->ah
->ah_radio_5ghz_revision
),
609 sc
->ah
->ah_radio_5ghz_revision
);
610 /* Multiband radio */
612 ATH5K_INFO(sc
, "RF%s multiband radio found"
614 ath5k_chip_name(AR5K_VERSION_RAD
,
615 sc
->ah
->ah_radio_5ghz_revision
),
616 sc
->ah
->ah_radio_5ghz_revision
);
619 /* Multi chip radio (RF5111 - RF2111) ->
620 * report both 2GHz/5GHz radios */
621 else if (sc
->ah
->ah_radio_5ghz_revision
&&
622 sc
->ah
->ah_radio_2ghz_revision
){
623 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
624 ath5k_chip_name(AR5K_VERSION_RAD
,
625 sc
->ah
->ah_radio_5ghz_revision
),
626 sc
->ah
->ah_radio_5ghz_revision
);
627 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
628 ath5k_chip_name(AR5K_VERSION_RAD
,
629 sc
->ah
->ah_radio_2ghz_revision
),
630 sc
->ah
->ah_radio_2ghz_revision
);
635 /* ready to process interrupts */
636 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
640 ath5k_hw_detach(sc
->ah
);
642 free_irq(pdev
->irq
, sc
);
644 ieee80211_free_hw(hw
);
646 pci_iounmap(pdev
, mem
);
648 pci_release_region(pdev
, 0);
650 pci_disable_device(pdev
);
655 static void __devexit
656 ath5k_pci_remove(struct pci_dev
*pdev
)
658 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
659 struct ath5k_softc
*sc
= hw
->priv
;
661 ath5k_debug_finish_device(sc
);
662 ath5k_detach(pdev
, hw
);
663 ath5k_hw_detach(sc
->ah
);
664 free_irq(pdev
->irq
, sc
);
665 pci_iounmap(pdev
, sc
->iobase
);
666 pci_release_region(pdev
, 0);
667 pci_disable_device(pdev
);
668 ieee80211_free_hw(hw
);
673 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
675 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
676 struct ath5k_softc
*sc
= hw
->priv
;
680 pci_save_state(pdev
);
681 pci_disable_device(pdev
);
682 pci_set_power_state(pdev
, PCI_D3hot
);
688 ath5k_pci_resume(struct pci_dev
*pdev
)
690 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
691 struct ath5k_softc
*sc
= hw
->priv
;
694 pci_restore_state(pdev
);
696 err
= pci_enable_device(pdev
);
701 * Suspend/Resume resets the PCI configuration space, so we have to
702 * re-disable the RETRY_TIMEOUT register (0x41) to keep
703 * PCI Tx retries from interfering with C3 CPU state
705 pci_write_config_byte(pdev
, 0x41, 0);
707 ath5k_led_enable(sc
);
710 #endif /* CONFIG_PM */
713 /***********************\
714 * Driver Initialization *
715 \***********************/
717 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
719 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
720 struct ath5k_softc
*sc
= hw
->priv
;
721 struct ath_regulatory
*reg
= &sc
->ah
->ah_regulatory
;
723 return ath_reg_notifier_apply(wiphy
, request
, reg
);
727 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
729 struct ath5k_softc
*sc
= hw
->priv
;
730 struct ath5k_hw
*ah
= sc
->ah
;
731 u8 mac
[ETH_ALEN
] = {};
734 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
737 * Check if the MAC has multi-rate retry support.
738 * We do this by trying to setup a fake extended
739 * descriptor. MAC's that don't have support will
740 * return false w/o doing anything. MAC's that do
741 * support it will return true w/o doing anything.
743 ret
= ah
->ah_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
747 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
750 * Collect the channel list. The 802.11 layer
751 * is resposible for filtering this list based
752 * on settings like the phy mode and regulatory
753 * domain restrictions.
755 ret
= ath5k_setup_bands(hw
);
757 ATH5K_ERR(sc
, "can't get channels\n");
761 /* NB: setup here so ath5k_rate_update is happy */
762 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
763 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
765 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
768 * Allocate tx+rx descriptors and populate the lists.
770 ret
= ath5k_desc_alloc(sc
, pdev
);
772 ATH5K_ERR(sc
, "can't allocate descriptors\n");
777 * Allocate hardware transmit queues: one queue for
778 * beacon frames and one data queue for each QoS
779 * priority. Note that hw functions handle reseting
780 * these queues at the needed time.
782 ret
= ath5k_beaconq_setup(ah
);
784 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
788 sc
->cabq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_CAB
, 0);
789 if (IS_ERR(sc
->cabq
)) {
790 ATH5K_ERR(sc
, "can't setup cab queue\n");
791 ret
= PTR_ERR(sc
->cabq
);
795 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
796 if (IS_ERR(sc
->txq
)) {
797 ATH5K_ERR(sc
, "can't setup xmit queue\n");
798 ret
= PTR_ERR(sc
->txq
);
802 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
803 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
804 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
805 tasklet_init(&sc
->calib
, ath5k_tasklet_calibrate
, (unsigned long)sc
);
806 tasklet_init(&sc
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)sc
);
808 ret
= ath5k_eeprom_read_mac(ah
, mac
);
810 ATH5K_ERR(sc
, "unable to read address from EEPROM: 0x%04x\n",
815 SET_IEEE80211_PERM_ADDR(hw
, mac
);
816 /* All MAC address bits matter for ACKs */
817 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
818 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
820 ah
->ah_regulatory
.current_rd
=
821 ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
822 ret
= ath_regd_init(&ah
->ah_regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
824 ATH5K_ERR(sc
, "can't initialize regulatory system\n");
828 ret
= ieee80211_register_hw(hw
);
830 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
834 if (!ath_is_world_regd(&sc
->ah
->ah_regulatory
))
835 regulatory_hint(hw
->wiphy
, sc
->ah
->ah_regulatory
.alpha2
);
841 ath5k_txq_release(sc
);
843 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
845 ath5k_desc_free(sc
, pdev
);
851 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
853 struct ath5k_softc
*sc
= hw
->priv
;
856 * NB: the order of these is important:
857 * o call the 802.11 layer before detaching ath5k_hw to
858 * insure callbacks into the driver to delete global
859 * key cache entries can be handled
860 * o reclaim the tx queue data structures after calling
861 * the 802.11 layer as we'll get called back to reclaim
862 * node state and potentially want to use them
863 * o to cleanup the tx queues the hal is called, so detach
865 * XXX: ??? detach ath5k_hw ???
866 * Other than that, it's straightforward...
868 ieee80211_unregister_hw(hw
);
869 ath5k_desc_free(sc
, pdev
);
870 ath5k_txq_release(sc
);
871 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
872 ath5k_unregister_leds(sc
);
875 * NB: can't reclaim these until after ieee80211_ifdetach
876 * returns because we'll get called back to reclaim node
877 * state and potentially want to use them.
884 /********************\
885 * Channel/mode setup *
886 \********************/
889 * Convert IEEE channel number to MHz frequency.
892 ath5k_ieee2mhz(short chan
)
894 if (chan
<= 14 || chan
>= 27)
895 return ieee80211chan2mhz(chan
);
897 return 2212 + chan
* 20;
901 * Returns true for the channel numbers used without all_channels modparam.
903 static bool ath5k_is_standard_channel(short chan
)
905 return ((chan
<= 14) ||
907 ((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
909 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
911 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165));
915 ath5k_copy_channels(struct ath5k_hw
*ah
,
916 struct ieee80211_channel
*channels
,
920 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
922 if (!test_bit(mode
, ah
->ah_modes
))
927 case AR5K_MODE_11A_TURBO
:
928 /* 1..220, but 2GHz frequencies are filtered by check_channel */
930 chfreq
= CHANNEL_5GHZ
;
934 case AR5K_MODE_11G_TURBO
:
936 chfreq
= CHANNEL_2GHZ
;
939 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
943 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
945 freq
= ath5k_ieee2mhz(ch
);
947 /* Check if channel is supported by the chipset */
948 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
951 if (!modparam_all_channels
&& !ath5k_is_standard_channel(ch
))
954 /* Write channel info and increment counter */
955 channels
[count
].center_freq
= freq
;
956 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
957 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
961 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
963 case AR5K_MODE_11A_TURBO
:
964 case AR5K_MODE_11G_TURBO
:
965 channels
[count
].hw_value
= chfreq
|
966 CHANNEL_OFDM
| CHANNEL_TURBO
;
969 channels
[count
].hw_value
= CHANNEL_B
;
980 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
984 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
985 sc
->rate_idx
[b
->band
][i
] = -1;
987 for (i
= 0; i
< b
->n_bitrates
; i
++) {
988 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
989 if (b
->bitrates
[i
].hw_value_short
)
990 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
995 ath5k_setup_bands(struct ieee80211_hw
*hw
)
997 struct ath5k_softc
*sc
= hw
->priv
;
998 struct ath5k_hw
*ah
= sc
->ah
;
999 struct ieee80211_supported_band
*sband
;
1000 int max_c
, count_c
= 0;
1003 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
1004 max_c
= ARRAY_SIZE(sc
->channels
);
1007 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1008 sband
->band
= IEEE80211_BAND_2GHZ
;
1009 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
1011 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1013 memcpy(sband
->bitrates
, &ath5k_rates
[0],
1014 sizeof(struct ieee80211_rate
) * 12);
1015 sband
->n_bitrates
= 12;
1017 sband
->channels
= sc
->channels
;
1018 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1019 AR5K_MODE_11G
, max_c
);
1021 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
1022 count_c
= sband
->n_channels
;
1024 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1026 memcpy(sband
->bitrates
, &ath5k_rates
[0],
1027 sizeof(struct ieee80211_rate
) * 4);
1028 sband
->n_bitrates
= 4;
1030 /* 5211 only supports B rates and uses 4bit rate codes
1031 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1034 if (ah
->ah_version
== AR5K_AR5211
) {
1035 for (i
= 0; i
< 4; i
++) {
1036 sband
->bitrates
[i
].hw_value
=
1037 sband
->bitrates
[i
].hw_value
& 0xF;
1038 sband
->bitrates
[i
].hw_value_short
=
1039 sband
->bitrates
[i
].hw_value_short
& 0xF;
1043 sband
->channels
= sc
->channels
;
1044 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1045 AR5K_MODE_11B
, max_c
);
1047 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
1048 count_c
= sband
->n_channels
;
1051 ath5k_setup_rate_idx(sc
, sband
);
1053 /* 5GHz band, A mode */
1054 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1055 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1056 sband
->band
= IEEE80211_BAND_5GHZ
;
1057 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
1059 memcpy(sband
->bitrates
, &ath5k_rates
[4],
1060 sizeof(struct ieee80211_rate
) * 8);
1061 sband
->n_bitrates
= 8;
1063 sband
->channels
= &sc
->channels
[count_c
];
1064 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1065 AR5K_MODE_11A
, max_c
);
1067 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1069 ath5k_setup_rate_idx(sc
, sband
);
1071 ath5k_debug_dump_bands(sc
);
1077 * Set/change channels. We always reset the chip.
1078 * To accomplish this we must first cleanup any pending DMA,
1079 * then restart stuff after a la ath5k_init.
1081 * Called with sc->lock.
1084 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1086 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1087 sc
->curchan
->center_freq
, chan
->center_freq
);
1090 * To switch channels clear any pending DMA operations;
1091 * wait long enough for the RX fifo to drain, reset the
1092 * hardware at the new frequency, and then re-enable
1093 * the relevant bits of the h/w.
1095 return ath5k_reset(sc
, chan
);
1099 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1103 if (mode
== AR5K_MODE_11A
) {
1104 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1106 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1111 ath5k_mode_setup(struct ath5k_softc
*sc
)
1113 struct ath5k_hw
*ah
= sc
->ah
;
1116 ah
->ah_op_mode
= sc
->opmode
;
1118 /* configure rx filter */
1119 rfilt
= sc
->filter_flags
;
1120 ath5k_hw_set_rx_filter(ah
, rfilt
);
1122 if (ath5k_hw_hasbssidmask(ah
))
1123 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1125 /* configure operational mode */
1126 ath5k_hw_set_opmode(ah
);
1128 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1129 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1133 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1137 /* return base rate on errors */
1138 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
1139 "hw_rix out of bounds: %x\n", hw_rix
))
1142 rix
= sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1143 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
1154 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_softc
*sc
, dma_addr_t
*skb_addr
)
1156 struct sk_buff
*skb
;
1159 * Allocate buffer with headroom_needed space for the
1160 * fake physical layer header at the start.
1162 skb
= ath_rxbuf_alloc(&sc
->common
,
1163 sc
->rxbufsize
+ sc
->common
.cachelsz
- 1,
1167 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1168 sc
->rxbufsize
+ sc
->common
.cachelsz
- 1);
1172 *skb_addr
= pci_map_single(sc
->pdev
,
1173 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1174 if (unlikely(pci_dma_mapping_error(sc
->pdev
, *skb_addr
))) {
1175 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1183 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1185 struct ath5k_hw
*ah
= sc
->ah
;
1186 struct sk_buff
*skb
= bf
->skb
;
1187 struct ath5k_desc
*ds
;
1190 skb
= ath5k_rx_skb_alloc(sc
, &bf
->skbaddr
);
1197 * Setup descriptors. For receive we always terminate
1198 * the descriptor list with a self-linked entry so we'll
1199 * not get overrun under high load (as can happen with a
1200 * 5212 when ANI processing enables PHY error frames).
1202 * To insure the last descriptor is self-linked we create
1203 * each descriptor as self-linked and add it to the end. As
1204 * each additional descriptor is added the previous self-linked
1205 * entry is ``fixed'' naturally. This should be safe even
1206 * if DMA is happening. When processing RX interrupts we
1207 * never remove/process the last, self-linked, entry on the
1208 * descriptor list. This insures the hardware always has
1209 * someplace to write a new frame.
1212 ds
->ds_link
= bf
->daddr
; /* link to self */
1213 ds
->ds_data
= bf
->skbaddr
;
1214 ah
->ah_setup_rx_desc(ah
, ds
,
1215 skb_tailroom(skb
), /* buffer size */
1218 if (sc
->rxlink
!= NULL
)
1219 *sc
->rxlink
= bf
->daddr
;
1220 sc
->rxlink
= &ds
->ds_link
;
1225 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
1226 struct ath5k_txq
*txq
)
1228 struct ath5k_hw
*ah
= sc
->ah
;
1229 struct ath5k_desc
*ds
= bf
->desc
;
1230 struct sk_buff
*skb
= bf
->skb
;
1231 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1232 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1233 struct ieee80211_rate
*rate
;
1234 unsigned int mrr_rate
[3], mrr_tries
[3];
1241 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1243 /* XXX endianness */
1244 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1247 rate
= ieee80211_get_tx_rate(sc
->hw
, info
);
1249 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1250 flags
|= AR5K_TXDESC_NOACK
;
1252 rc_flags
= info
->control
.rates
[0].flags
;
1253 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
1254 rate
->hw_value_short
: rate
->hw_value
;
1258 /* FIXME: If we are in g mode and rate is a CCK rate
1259 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1260 * from tx power (value is in dB units already) */
1261 if (info
->control
.hw_key
) {
1262 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1263 pktlen
+= info
->control
.hw_key
->icv_len
;
1265 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1266 flags
|= AR5K_TXDESC_RTSENA
;
1267 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1268 duration
= le16_to_cpu(ieee80211_rts_duration(sc
->hw
,
1269 sc
->vif
, pktlen
, info
));
1271 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1272 flags
|= AR5K_TXDESC_CTSENA
;
1273 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1274 duration
= le16_to_cpu(ieee80211_ctstoself_duration(sc
->hw
,
1275 sc
->vif
, pktlen
, info
));
1277 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1278 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1279 (sc
->power_level
* 2),
1281 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
1282 cts_rate
, duration
);
1286 memset(mrr_rate
, 0, sizeof(mrr_rate
));
1287 memset(mrr_tries
, 0, sizeof(mrr_tries
));
1288 for (i
= 0; i
< 3; i
++) {
1289 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
1293 mrr_rate
[i
] = rate
->hw_value
;
1294 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
1297 ah
->ah_setup_mrr_tx_desc(ah
, ds
,
1298 mrr_rate
[0], mrr_tries
[0],
1299 mrr_rate
[1], mrr_tries
[1],
1300 mrr_rate
[2], mrr_tries
[2]);
1303 ds
->ds_data
= bf
->skbaddr
;
1305 spin_lock_bh(&txq
->lock
);
1306 list_add_tail(&bf
->list
, &txq
->q
);
1307 sc
->tx_stats
[txq
->qnum
].len
++;
1308 if (txq
->link
== NULL
) /* is this first packet? */
1309 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1310 else /* no, so only link it */
1311 *txq
->link
= bf
->daddr
;
1313 txq
->link
= &ds
->ds_link
;
1314 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1316 spin_unlock_bh(&txq
->lock
);
1320 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1324 /*******************\
1325 * Descriptors setup *
1326 \*******************/
1329 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1331 struct ath5k_desc
*ds
;
1332 struct ath5k_buf
*bf
;
1337 /* allocate descriptors */
1338 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1339 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1340 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1341 if (sc
->desc
== NULL
) {
1342 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1347 da
= sc
->desc_daddr
;
1348 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1349 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1351 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1352 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1354 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1360 INIT_LIST_HEAD(&sc
->rxbuf
);
1361 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1364 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1367 INIT_LIST_HEAD(&sc
->txbuf
);
1368 sc
->txbuf_len
= ATH_TXBUF
;
1369 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1370 da
+= sizeof(*ds
)) {
1373 list_add_tail(&bf
->list
, &sc
->txbuf
);
1383 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1390 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1392 struct ath5k_buf
*bf
;
1394 ath5k_txbuf_free(sc
, sc
->bbuf
);
1395 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1396 ath5k_txbuf_free(sc
, bf
);
1397 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1398 ath5k_rxbuf_free(sc
, bf
);
1400 /* Free memory associated with all descriptors */
1401 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1415 static struct ath5k_txq
*
1416 ath5k_txq_setup(struct ath5k_softc
*sc
,
1417 int qtype
, int subtype
)
1419 struct ath5k_hw
*ah
= sc
->ah
;
1420 struct ath5k_txq
*txq
;
1421 struct ath5k_txq_info qi
= {
1422 .tqi_subtype
= subtype
,
1423 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1424 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1425 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1430 * Enable interrupts only for EOL and DESC conditions.
1431 * We mark tx descriptors to receive a DESC interrupt
1432 * when a tx queue gets deep; otherwise waiting for the
1433 * EOL to reap descriptors. Note that this is done to
1434 * reduce interrupt load and this only defers reaping
1435 * descriptors, never transmitting frames. Aside from
1436 * reducing interrupts this also permits more concurrency.
1437 * The only potential downside is if the tx queue backs
1438 * up in which case the top half of the kernel may backup
1439 * due to a lack of tx descriptors.
1441 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1442 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1443 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1446 * NB: don't print a message, this happens
1447 * normally on parts with too few tx queues
1449 return ERR_PTR(qnum
);
1451 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1452 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1453 qnum
, ARRAY_SIZE(sc
->txqs
));
1454 ath5k_hw_release_tx_queue(ah
, qnum
);
1455 return ERR_PTR(-EINVAL
);
1457 txq
= &sc
->txqs
[qnum
];
1461 INIT_LIST_HEAD(&txq
->q
);
1462 spin_lock_init(&txq
->lock
);
1465 return &sc
->txqs
[qnum
];
1469 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1471 struct ath5k_txq_info qi
= {
1472 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1473 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1474 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1475 /* NB: for dynamic turbo, don't enable any other interrupts */
1476 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1479 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1483 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1485 struct ath5k_hw
*ah
= sc
->ah
;
1486 struct ath5k_txq_info qi
;
1489 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1492 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1493 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1495 * Always burst out beacon and CAB traffic
1496 * (aifs = cwmin = cwmax = 0)
1501 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1503 * Adhoc mode; backoff between 0 and (2 * cw_min).
1507 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1510 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1511 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1512 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1514 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1516 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1517 "hardware queue!\n", __func__
);
1521 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1525 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1527 struct ath5k_buf
*bf
, *bf0
;
1530 * NB: this assumes output has been stopped and
1531 * we do not need to block ath5k_tx_tasklet
1533 spin_lock_bh(&txq
->lock
);
1534 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1535 ath5k_debug_printtxbuf(sc
, bf
);
1537 ath5k_txbuf_free(sc
, bf
);
1539 spin_lock_bh(&sc
->txbuflock
);
1540 sc
->tx_stats
[txq
->qnum
].len
--;
1541 list_move_tail(&bf
->list
, &sc
->txbuf
);
1543 spin_unlock_bh(&sc
->txbuflock
);
1546 spin_unlock_bh(&txq
->lock
);
1550 * Drain the transmit queues and reclaim resources.
1553 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1555 struct ath5k_hw
*ah
= sc
->ah
;
1558 /* XXX return value */
1559 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1560 /* don't touch the hardware if marked invalid */
1561 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1562 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1563 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1564 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1565 if (sc
->txqs
[i
].setup
) {
1566 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1567 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1570 ath5k_hw_get_txdp(ah
,
1575 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1577 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1578 if (sc
->txqs
[i
].setup
)
1579 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1583 ath5k_txq_release(struct ath5k_softc
*sc
)
1585 struct ath5k_txq
*txq
= sc
->txqs
;
1588 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1590 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1603 * Enable the receive h/w following a reset.
1606 ath5k_rx_start(struct ath5k_softc
*sc
)
1608 struct ath5k_hw
*ah
= sc
->ah
;
1609 struct ath5k_buf
*bf
;
1612 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->common
.cachelsz
);
1614 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1615 sc
->common
.cachelsz
, sc
->rxbufsize
);
1617 spin_lock_bh(&sc
->rxbuflock
);
1619 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1620 ret
= ath5k_rxbuf_setup(sc
, bf
);
1622 spin_unlock_bh(&sc
->rxbuflock
);
1626 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1627 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1628 spin_unlock_bh(&sc
->rxbuflock
);
1630 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1631 ath5k_mode_setup(sc
); /* set filters, etc. */
1632 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1640 * Disable the receive h/w in preparation for a reset.
1643 ath5k_rx_stop(struct ath5k_softc
*sc
)
1645 struct ath5k_hw
*ah
= sc
->ah
;
1647 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1648 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1649 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1651 ath5k_debug_printrxbuffs(sc
, ah
);
1653 sc
->rxlink
= NULL
; /* just in case */
1657 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1658 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1660 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1661 unsigned int keyix
, hlen
;
1663 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1664 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1665 return RX_FLAG_DECRYPTED
;
1667 /* Apparently when a default key is used to decrypt the packet
1668 the hw does not set the index used to decrypt. In such cases
1669 get the index from the packet. */
1670 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1671 if (ieee80211_has_protected(hdr
->frame_control
) &&
1672 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1673 skb
->len
>= hlen
+ 4) {
1674 keyix
= skb
->data
[hlen
+ 3] >> 6;
1676 if (test_bit(keyix
, sc
->keymap
))
1677 return RX_FLAG_DECRYPTED
;
1685 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1686 struct ieee80211_rx_status
*rxs
)
1690 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1692 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1693 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1694 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1696 * Received an IBSS beacon with the same BSSID. Hardware *must*
1697 * have updated the local TSF. We have to work around various
1698 * hardware bugs, though...
1700 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1701 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1702 hw_tu
= TSF_TO_TU(tsf
);
1704 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1705 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1706 (unsigned long long)bc_tstamp
,
1707 (unsigned long long)rxs
->mactime
,
1708 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1709 (unsigned long long)tsf
);
1712 * Sometimes the HW will give us a wrong tstamp in the rx
1713 * status, causing the timestamp extension to go wrong.
1714 * (This seems to happen especially with beacon frames bigger
1715 * than 78 byte (incl. FCS))
1716 * But we know that the receive timestamp must be later than the
1717 * timestamp of the beacon since HW must have synced to that.
1719 * NOTE: here we assume mactime to be after the frame was
1720 * received, not like mac80211 which defines it at the start.
1722 if (bc_tstamp
> rxs
->mactime
) {
1723 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1724 "fixing mactime from %llx to %llx\n",
1725 (unsigned long long)rxs
->mactime
,
1726 (unsigned long long)tsf
);
1731 * Local TSF might have moved higher than our beacon timers,
1732 * in that case we have to update them to continue sending
1733 * beacons. This also takes care of synchronizing beacon sending
1734 * times with other stations.
1736 if (hw_tu
>= sc
->nexttbtt
)
1737 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1742 ath5k_tasklet_rx(unsigned long data
)
1744 struct ieee80211_rx_status rxs
= {};
1745 struct ath5k_rx_status rs
= {};
1746 struct sk_buff
*skb
, *next_skb
;
1747 dma_addr_t next_skb_addr
;
1748 struct ath5k_softc
*sc
= (void *)data
;
1749 struct ath5k_buf
*bf
;
1750 struct ath5k_desc
*ds
;
1755 spin_lock(&sc
->rxbuflock
);
1756 if (list_empty(&sc
->rxbuf
)) {
1757 ATH5K_WARN(sc
, "empty rx buf pool\n");
1763 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1764 BUG_ON(bf
->skb
== NULL
);
1768 /* bail if HW is still using self-linked descriptor */
1769 if (ath5k_hw_get_rxdp(sc
->ah
) == bf
->daddr
)
1772 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1773 if (unlikely(ret
== -EINPROGRESS
))
1775 else if (unlikely(ret
)) {
1776 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1777 spin_unlock(&sc
->rxbuflock
);
1781 if (unlikely(rs
.rs_more
)) {
1782 ATH5K_WARN(sc
, "unsupported jumbo\n");
1786 if (unlikely(rs
.rs_status
)) {
1787 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1789 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1791 * Decrypt error. If the error occurred
1792 * because there was no hardware key, then
1793 * let the frame through so the upper layers
1794 * can process it. This is necessary for 5210
1795 * parts which have no way to setup a ``clear''
1798 * XXX do key cache faulting
1800 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1801 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1804 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1805 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1809 /* let crypto-error packets fall through in MNTR */
1811 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1812 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
1816 next_skb
= ath5k_rx_skb_alloc(sc
, &next_skb_addr
);
1819 * If we can't replace bf->skb with a new skb under memory
1820 * pressure, just skip this packet
1825 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1826 PCI_DMA_FROMDEVICE
);
1827 skb_put(skb
, rs
.rs_datalen
);
1829 /* The MAC header is padded to have 32-bit boundary if the
1830 * packet payload is non-zero. The general calculation for
1831 * padsize would take into account odd header lengths:
1832 * padsize = (4 - hdrlen % 4) % 4; However, since only
1833 * even-length headers are used, padding can only be 0 or 2
1834 * bytes and we can optimize this a bit. In addition, we must
1835 * not try to remove padding from short control frames that do
1836 * not have payload. */
1837 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1838 padsize
= ath5k_pad_size(hdrlen
);
1840 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
1841 skb_pull(skb
, padsize
);
1845 * always extend the mac timestamp, since this information is
1846 * also needed for proper IBSS merging.
1848 * XXX: it might be too late to do it here, since rs_tstamp is
1849 * 15bit only. that means TSF extension has to be done within
1850 * 32768usec (about 32ms). it might be necessary to move this to
1851 * the interrupt handler, like it is done in madwifi.
1853 * Unfortunately we don't know when the hardware takes the rx
1854 * timestamp (beginning of phy frame, data frame, end of rx?).
1855 * The only thing we know is that it is hardware specific...
1856 * On AR5213 it seems the rx timestamp is at the end of the
1857 * frame, but i'm not sure.
1859 * NOTE: mac80211 defines mactime at the beginning of the first
1860 * data symbol. Since we don't have any time references it's
1861 * impossible to comply to that. This affects IBSS merge only
1862 * right now, so it's not too bad...
1864 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1865 rxs
.flag
|= RX_FLAG_TSFT
;
1867 rxs
.freq
= sc
->curchan
->center_freq
;
1868 rxs
.band
= sc
->curband
->band
;
1870 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1871 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1873 /* An rssi of 35 indicates you should be able use
1874 * 54 Mbps reliably. A more elaborate scheme can be used
1875 * here but it requires a map of SNR/throughput for each
1876 * possible mode used */
1877 rxs
.qual
= rs
.rs_rssi
* 100 / 35;
1879 /* rssi can be more than 35 though, anything above that
1880 * should be considered at 100% */
1884 rxs
.antenna
= rs
.rs_antenna
;
1885 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1886 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1888 if (rxs
.rate_idx
>= 0 && rs
.rs_rate
==
1889 sc
->curband
->bitrates
[rxs
.rate_idx
].hw_value_short
)
1890 rxs
.flag
|= RX_FLAG_SHORTPRE
;
1892 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1894 /* check beacons in IBSS mode */
1895 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1896 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1898 memcpy(IEEE80211_SKB_RXCB(skb
), &rxs
, sizeof(rxs
));
1899 ieee80211_rx(sc
->hw
, skb
);
1902 bf
->skbaddr
= next_skb_addr
;
1904 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1905 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1907 spin_unlock(&sc
->rxbuflock
);
1918 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1920 struct ath5k_tx_status ts
= {};
1921 struct ath5k_buf
*bf
, *bf0
;
1922 struct ath5k_desc
*ds
;
1923 struct sk_buff
*skb
;
1924 struct ieee80211_tx_info
*info
;
1927 spin_lock(&txq
->lock
);
1928 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1931 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1932 if (unlikely(ret
== -EINPROGRESS
))
1934 else if (unlikely(ret
)) {
1935 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1941 info
= IEEE80211_SKB_CB(skb
);
1944 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1947 ieee80211_tx_info_clear_status(info
);
1948 for (i
= 0; i
< 4; i
++) {
1949 struct ieee80211_tx_rate
*r
=
1950 &info
->status
.rates
[i
];
1952 if (ts
.ts_rate
[i
]) {
1953 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
.ts_rate
[i
]);
1954 r
->count
= ts
.ts_retry
[i
];
1961 /* count the successful attempt as well */
1962 info
->status
.rates
[ts
.ts_final_idx
].count
++;
1964 if (unlikely(ts
.ts_status
)) {
1965 sc
->ll_stats
.dot11ACKFailureCount
++;
1966 if (ts
.ts_status
& AR5K_TXERR_FILT
)
1967 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1969 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1970 info
->status
.ack_signal
= ts
.ts_rssi
;
1973 ieee80211_tx_status(sc
->hw
, skb
);
1974 sc
->tx_stats
[txq
->qnum
].count
++;
1976 spin_lock(&sc
->txbuflock
);
1977 sc
->tx_stats
[txq
->qnum
].len
--;
1978 list_move_tail(&bf
->list
, &sc
->txbuf
);
1980 spin_unlock(&sc
->txbuflock
);
1982 if (likely(list_empty(&txq
->q
)))
1984 spin_unlock(&txq
->lock
);
1985 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1986 ieee80211_wake_queues(sc
->hw
);
1990 ath5k_tasklet_tx(unsigned long data
)
1993 struct ath5k_softc
*sc
= (void *)data
;
1995 for (i
=0; i
< AR5K_NUM_TX_QUEUES
; i
++)
1996 if (sc
->txqs
[i
].setup
&& (sc
->ah
->ah_txq_isr
& BIT(i
)))
1997 ath5k_tx_processq(sc
, &sc
->txqs
[i
]);
2006 * Setup the beacon frame for transmit.
2009 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
2011 struct sk_buff
*skb
= bf
->skb
;
2012 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2013 struct ath5k_hw
*ah
= sc
->ah
;
2014 struct ath5k_desc
*ds
;
2019 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
2021 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
2022 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
2023 (unsigned long long)bf
->skbaddr
);
2024 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
2025 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
2030 antenna
= ah
->ah_tx_ant
;
2032 flags
= AR5K_TXDESC_NOACK
;
2033 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
2034 ds
->ds_link
= bf
->daddr
; /* self-linked */
2035 flags
|= AR5K_TXDESC_VEOL
;
2040 * If we use multiple antennas on AP and use
2041 * the Sectored AP scenario, switch antenna every
2042 * 4 beacons to make sure everybody hears our AP.
2043 * When a client tries to associate, hw will keep
2044 * track of the tx antenna to be used for this client
2045 * automaticaly, based on ACKed packets.
2047 * Note: AP still listens and transmits RTS on the
2048 * default antenna which is supposed to be an omni.
2050 * Note2: On sectored scenarios it's possible to have
2051 * multiple antennas (1omni -the default- and 14 sectors)
2052 * so if we choose to actually support this mode we need
2053 * to allow user to set how many antennas we have and tweak
2054 * the code below to send beacons on all of them.
2056 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
2057 antenna
= sc
->bsent
& 4 ? 2 : 1;
2060 /* FIXME: If we are in g mode and rate is a CCK rate
2061 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2062 * from tx power (value is in dB units already) */
2063 ds
->ds_data
= bf
->skbaddr
;
2064 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
2065 ieee80211_get_hdrlen_from_skb(skb
),
2066 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
2067 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
2068 1, AR5K_TXKEYIX_INVALID
,
2069 antenna
, flags
, 0, 0);
2075 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
2080 * Transmit a beacon frame at SWBA. Dynamic updates to the
2081 * frame contents are done as needed and the slot time is
2082 * also adjusted based on current state.
2084 * This is called from software irq context (beacontq or restq
2085 * tasklets) or user context from ath5k_beacon_config.
2088 ath5k_beacon_send(struct ath5k_softc
*sc
)
2090 struct ath5k_buf
*bf
= sc
->bbuf
;
2091 struct ath5k_hw
*ah
= sc
->ah
;
2092 struct sk_buff
*skb
;
2094 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
2096 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
2097 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
2098 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
2102 * Check if the previous beacon has gone out. If
2103 * not don't don't try to post another, skip this
2104 * period and wait for the next. Missed beacons
2105 * indicate a problem and should not occur. If we
2106 * miss too many consecutive beacons reset the device.
2108 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
2110 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2111 "missed %u consecutive beacons\n", sc
->bmisscount
);
2112 if (sc
->bmisscount
> 10) { /* NB: 10 is a guess */
2113 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2114 "stuck beacon time (%u missed)\n",
2116 tasklet_schedule(&sc
->restq
);
2120 if (unlikely(sc
->bmisscount
!= 0)) {
2121 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2122 "resume beacon xmit after %u misses\n",
2128 * Stop any current dma and put the new frame on the queue.
2129 * This should never fail since we check above that no frames
2130 * are still pending on the queue.
2132 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2133 ATH5K_WARN(sc
, "beacon queue %u didn't start/stop ?\n", sc
->bhalq
);
2134 /* NB: hw still stops DMA, so proceed */
2137 /* refresh the beacon for AP mode */
2138 if (sc
->opmode
== NL80211_IFTYPE_AP
)
2139 ath5k_beacon_update(sc
->hw
, sc
->vif
);
2141 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
2142 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
2143 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2144 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2146 skb
= ieee80211_get_buffered_bc(sc
->hw
, sc
->vif
);
2148 ath5k_tx_queue(sc
->hw
, skb
, sc
->cabq
);
2149 skb
= ieee80211_get_buffered_bc(sc
->hw
, sc
->vif
);
2157 * ath5k_beacon_update_timers - update beacon timers
2159 * @sc: struct ath5k_softc pointer we are operating on
2160 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2161 * beacon timer update based on the current HW TSF.
2163 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2164 * of a received beacon or the current local hardware TSF and write it to the
2165 * beacon timer registers.
2167 * This is called in a variety of situations, e.g. when a beacon is received,
2168 * when a TSF update has been detected, but also when an new IBSS is created or
2169 * when we otherwise know we have to update the timers, but we keep it in this
2170 * function to have it all together in one place.
2173 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2175 struct ath5k_hw
*ah
= sc
->ah
;
2176 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2179 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2180 if (WARN_ON(!intval
))
2183 /* beacon TSF converted to TU */
2184 bc_tu
= TSF_TO_TU(bc_tsf
);
2186 /* current TSF converted to TU */
2187 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2188 hw_tu
= TSF_TO_TU(hw_tsf
);
2191 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2194 * no beacons received, called internally.
2195 * just need to refresh timers based on HW TSF.
2197 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2198 } else if (bc_tsf
== 0) {
2200 * no beacon received, probably called by ath5k_reset_tsf().
2201 * reset TSF to start with 0.
2204 intval
|= AR5K_BEACON_RESET_TSF
;
2205 } else if (bc_tsf
> hw_tsf
) {
2207 * beacon received, SW merge happend but HW TSF not yet updated.
2208 * not possible to reconfigure timers yet, but next time we
2209 * receive a beacon with the same BSSID, the hardware will
2210 * automatically update the TSF and then we need to reconfigure
2213 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2214 "need to wait for HW TSF sync\n");
2218 * most important case for beacon synchronization between STA.
2220 * beacon received and HW TSF has been already updated by HW.
2221 * update next TBTT based on the TSF of the beacon, but make
2222 * sure it is ahead of our local TSF timer.
2224 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2228 sc
->nexttbtt
= nexttbtt
;
2230 intval
|= AR5K_BEACON_ENA
;
2231 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2234 * debugging output last in order to preserve the time critical aspect
2238 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2239 "reconfigured timers based on HW TSF\n");
2240 else if (bc_tsf
== 0)
2241 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2242 "reset HW TSF and timers\n");
2244 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2245 "updated timers based on beacon TSF\n");
2247 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2248 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2249 (unsigned long long) bc_tsf
,
2250 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2251 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2252 intval
& AR5K_BEACON_PERIOD
,
2253 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2254 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2259 * ath5k_beacon_config - Configure the beacon queues and interrupts
2261 * @sc: struct ath5k_softc pointer we are operating on
2263 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2264 * interrupts to detect TSF updates only.
2267 ath5k_beacon_config(struct ath5k_softc
*sc
)
2269 struct ath5k_hw
*ah
= sc
->ah
;
2270 unsigned long flags
;
2272 spin_lock_irqsave(&sc
->block
, flags
);
2274 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2276 if (sc
->enable_beacon
) {
2278 * In IBSS mode we use a self-linked tx descriptor and let the
2279 * hardware send the beacons automatically. We have to load it
2281 * We use the SWBA interrupt only to keep track of the beacon
2282 * timers in order to detect automatic TSF updates.
2284 ath5k_beaconq_config(sc
);
2286 sc
->imask
|= AR5K_INT_SWBA
;
2288 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2289 if (ath5k_hw_hasveol(ah
))
2290 ath5k_beacon_send(sc
);
2292 ath5k_beacon_update_timers(sc
, -1);
2294 ath5k_hw_stop_tx_dma(sc
->ah
, sc
->bhalq
);
2297 ath5k_hw_set_imr(ah
, sc
->imask
);
2299 spin_unlock_irqrestore(&sc
->block
, flags
);
2302 static void ath5k_tasklet_beacon(unsigned long data
)
2304 struct ath5k_softc
*sc
= (struct ath5k_softc
*) data
;
2307 * Software beacon alert--time to send a beacon.
2309 * In IBSS mode we use this interrupt just to
2310 * keep track of the next TBTT (target beacon
2311 * transmission time) in order to detect wether
2312 * automatic TSF updates happened.
2314 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2315 /* XXX: only if VEOL suppported */
2316 u64 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
2317 sc
->nexttbtt
+= sc
->bintval
;
2318 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2319 "SWBA nexttbtt: %x hw_tu: %x "
2323 (unsigned long long) tsf
);
2325 spin_lock(&sc
->block
);
2326 ath5k_beacon_send(sc
);
2327 spin_unlock(&sc
->block
);
2332 /********************\
2333 * Interrupt handling *
2334 \********************/
2337 ath5k_init(struct ath5k_softc
*sc
)
2339 struct ath5k_hw
*ah
= sc
->ah
;
2342 mutex_lock(&sc
->lock
);
2344 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2347 * Stop anything previously setup. This is safe
2348 * no matter this is the first time through or not.
2350 ath5k_stop_locked(sc
);
2353 * The basic interface to setting the hardware in a good
2354 * state is ``reset''. On return the hardware is known to
2355 * be powered up and with interrupts disabled. This must
2356 * be followed by initialization of the appropriate bits
2357 * and then setup of the interrupt mask.
2359 sc
->curchan
= sc
->hw
->conf
.channel
;
2360 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2361 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2362 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2363 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
| AR5K_INT_SWI
;
2364 ret
= ath5k_reset(sc
, NULL
);
2368 ath5k_rfkill_hw_start(ah
);
2371 * Reset the key cache since some parts do not reset the
2372 * contents on initial power up or resume from suspend.
2374 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
2375 ath5k_hw_reset_key(ah
, i
);
2377 /* Set ack to be sent at low bit-rates */
2378 ath5k_hw_set_ack_bitrate_high(ah
, false);
2380 /* Set PHY calibration inteval */
2381 ah
->ah_cal_intval
= ath5k_calinterval
;
2386 mutex_unlock(&sc
->lock
);
2391 ath5k_stop_locked(struct ath5k_softc
*sc
)
2393 struct ath5k_hw
*ah
= sc
->ah
;
2395 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2396 test_bit(ATH_STAT_INVALID
, sc
->status
));
2399 * Shutdown the hardware and driver:
2400 * stop output from above
2401 * disable interrupts
2403 * turn off the radio
2404 * clear transmit machinery
2405 * clear receive machinery
2406 * drain and release tx queues
2407 * reclaim beacon resources
2408 * power down hardware
2410 * Note that some of this work is not possible if the
2411 * hardware is gone (invalid).
2413 ieee80211_stop_queues(sc
->hw
);
2415 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2417 ath5k_hw_set_imr(ah
, 0);
2418 synchronize_irq(sc
->pdev
->irq
);
2420 ath5k_txq_cleanup(sc
);
2421 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2423 ath5k_hw_phy_disable(ah
);
2431 * Stop the device, grabbing the top-level lock to protect
2432 * against concurrent entry through ath5k_init (which can happen
2433 * if another thread does a system call and the thread doing the
2434 * stop is preempted).
2437 ath5k_stop_hw(struct ath5k_softc
*sc
)
2441 mutex_lock(&sc
->lock
);
2442 ret
= ath5k_stop_locked(sc
);
2443 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2445 * Don't set the card in full sleep mode!
2447 * a) When the device is in this state it must be carefully
2448 * woken up or references to registers in the PCI clock
2449 * domain may freeze the bus (and system). This varies
2450 * by chip and is mostly an issue with newer parts
2451 * (madwifi sources mentioned srev >= 0x78) that go to
2452 * sleep more quickly.
2454 * b) On older chips full sleep results a weird behaviour
2455 * during wakeup. I tested various cards with srev < 0x78
2456 * and they don't wake up after module reload, a second
2457 * module reload is needed to bring the card up again.
2459 * Until we figure out what's going on don't enable
2460 * full chip reset on any chip (this is what Legacy HAL
2461 * and Sam's HAL do anyway). Instead Perform a full reset
2462 * on the device (same as initial state after attach) and
2463 * leave it idle (keep MAC/BB on warm reset) */
2464 ret
= ath5k_hw_on_hold(sc
->ah
);
2466 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2467 "putting device to sleep\n");
2469 ath5k_txbuf_free(sc
, sc
->bbuf
);
2472 mutex_unlock(&sc
->lock
);
2474 tasklet_kill(&sc
->rxtq
);
2475 tasklet_kill(&sc
->txtq
);
2476 tasklet_kill(&sc
->restq
);
2477 tasklet_kill(&sc
->calib
);
2478 tasklet_kill(&sc
->beacontq
);
2480 ath5k_rfkill_hw_stop(sc
->ah
);
2486 ath5k_intr(int irq
, void *dev_id
)
2488 struct ath5k_softc
*sc
= dev_id
;
2489 struct ath5k_hw
*ah
= sc
->ah
;
2490 enum ath5k_int status
;
2491 unsigned int counter
= 1000;
2493 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2494 !ath5k_hw_is_intr_pending(ah
)))
2498 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2499 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2501 if (unlikely(status
& AR5K_INT_FATAL
)) {
2503 * Fatal errors are unrecoverable.
2504 * Typically these are caused by DMA errors.
2506 tasklet_schedule(&sc
->restq
);
2507 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2508 tasklet_schedule(&sc
->restq
);
2510 if (status
& AR5K_INT_SWBA
) {
2511 tasklet_hi_schedule(&sc
->beacontq
);
2513 if (status
& AR5K_INT_RXEOL
) {
2515 * NB: the hardware should re-read the link when
2516 * RXE bit is written, but it doesn't work at
2517 * least on older hardware revs.
2521 if (status
& AR5K_INT_TXURN
) {
2522 /* bump tx trigger level */
2523 ath5k_hw_update_tx_triglevel(ah
, true);
2525 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2526 tasklet_schedule(&sc
->rxtq
);
2527 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2528 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2529 tasklet_schedule(&sc
->txtq
);
2530 if (status
& AR5K_INT_BMISS
) {
2533 if (status
& AR5K_INT_SWI
) {
2534 tasklet_schedule(&sc
->calib
);
2536 if (status
& AR5K_INT_MIB
) {
2538 * These stats are also used for ANI i think
2539 * so how about updating them more often ?
2541 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2543 if (status
& AR5K_INT_GPIO
)
2544 tasklet_schedule(&sc
->rf_kill
.toggleq
);
2547 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2549 if (unlikely(!counter
))
2550 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2552 ath5k_hw_calibration_poll(ah
);
2558 ath5k_tasklet_reset(unsigned long data
)
2560 struct ath5k_softc
*sc
= (void *)data
;
2562 ath5k_reset_wake(sc
);
2566 * Periodically recalibrate the PHY to account
2567 * for temperature/environment changes.
2570 ath5k_tasklet_calibrate(unsigned long data
)
2572 struct ath5k_softc
*sc
= (void *)data
;
2573 struct ath5k_hw
*ah
= sc
->ah
;
2575 /* Only full calibration for now */
2576 if (ah
->ah_swi_mask
!= AR5K_SWI_FULL_CALIBRATION
)
2579 /* Stop queues so that calibration
2580 * doesn't interfere with tx */
2581 ieee80211_stop_queues(sc
->hw
);
2583 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2584 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2585 sc
->curchan
->hw_value
);
2587 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2589 * Rfgain is out of bounds, reset the chip
2590 * to load new gain values.
2592 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2593 ath5k_reset_wake(sc
);
2595 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2596 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2597 ieee80211_frequency_to_channel(
2598 sc
->curchan
->center_freq
));
2600 ah
->ah_swi_mask
= 0;
2603 ieee80211_wake_queues(sc
->hw
);
2608 /********************\
2609 * Mac80211 functions *
2610 \********************/
2613 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2615 struct ath5k_softc
*sc
= hw
->priv
;
2617 return ath5k_tx_queue(hw
, skb
, sc
->txq
);
2620 static int ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2621 struct ath5k_txq
*txq
)
2623 struct ath5k_softc
*sc
= hw
->priv
;
2624 struct ath5k_buf
*bf
;
2625 unsigned long flags
;
2629 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2631 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2632 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2635 * the hardware expects the header padded to 4 byte boundaries
2636 * if this is not the case we add the padding after the header
2638 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2639 padsize
= ath5k_pad_size(hdrlen
);
2642 if (skb_headroom(skb
) < padsize
) {
2643 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2644 " headroom to pad %d\n", hdrlen
, padsize
);
2647 skb_push(skb
, padsize
);
2648 memmove(skb
->data
, skb
->data
+padsize
, hdrlen
);
2651 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2652 if (list_empty(&sc
->txbuf
)) {
2653 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2654 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2655 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2658 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2659 list_del(&bf
->list
);
2661 if (list_empty(&sc
->txbuf
))
2662 ieee80211_stop_queues(hw
);
2663 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2667 if (ath5k_txbuf_setup(sc
, bf
, txq
)) {
2669 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2670 list_add_tail(&bf
->list
, &sc
->txbuf
);
2672 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2675 return NETDEV_TX_OK
;
2678 dev_kfree_skb_any(skb
);
2679 return NETDEV_TX_OK
;
2683 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2684 * and change to the given channel.
2687 ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
2689 struct ath5k_hw
*ah
= sc
->ah
;
2692 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2695 ath5k_hw_set_imr(ah
, 0);
2696 ath5k_txq_cleanup(sc
);
2700 sc
->curband
= &sc
->sbands
[chan
->band
];
2702 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, chan
!= NULL
);
2704 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2708 ret
= ath5k_rx_start(sc
);
2710 ATH5K_ERR(sc
, "can't start recv logic\n");
2715 * Change channels and update the h/w rate map if we're switching;
2716 * e.g. 11a to 11b/g.
2718 * We may be doing a reset in response to an ioctl that changes the
2719 * channel so update any state that might change as a result.
2723 /* ath5k_chan_change(sc, c); */
2725 ath5k_beacon_config(sc
);
2726 /* intrs are enabled by ath5k_beacon_config */
2734 ath5k_reset_wake(struct ath5k_softc
*sc
)
2738 ret
= ath5k_reset(sc
, sc
->curchan
);
2740 ieee80211_wake_queues(sc
->hw
);
2745 static int ath5k_start(struct ieee80211_hw
*hw
)
2747 return ath5k_init(hw
->priv
);
2750 static void ath5k_stop(struct ieee80211_hw
*hw
)
2752 ath5k_stop_hw(hw
->priv
);
2755 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2756 struct ieee80211_if_init_conf
*conf
)
2758 struct ath5k_softc
*sc
= hw
->priv
;
2761 mutex_lock(&sc
->lock
);
2767 sc
->vif
= conf
->vif
;
2769 switch (conf
->type
) {
2770 case NL80211_IFTYPE_AP
:
2771 case NL80211_IFTYPE_STATION
:
2772 case NL80211_IFTYPE_ADHOC
:
2773 case NL80211_IFTYPE_MESH_POINT
:
2774 case NL80211_IFTYPE_MONITOR
:
2775 sc
->opmode
= conf
->type
;
2782 ath5k_hw_set_lladdr(sc
->ah
, conf
->mac_addr
);
2783 ath5k_mode_setup(sc
);
2787 mutex_unlock(&sc
->lock
);
2792 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2793 struct ieee80211_if_init_conf
*conf
)
2795 struct ath5k_softc
*sc
= hw
->priv
;
2796 u8 mac
[ETH_ALEN
] = {};
2798 mutex_lock(&sc
->lock
);
2799 if (sc
->vif
!= conf
->vif
)
2802 ath5k_hw_set_lladdr(sc
->ah
, mac
);
2805 mutex_unlock(&sc
->lock
);
2809 * TODO: Phy disable/diversity etc
2812 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
2814 struct ath5k_softc
*sc
= hw
->priv
;
2815 struct ath5k_hw
*ah
= sc
->ah
;
2816 struct ieee80211_conf
*conf
= &hw
->conf
;
2819 mutex_lock(&sc
->lock
);
2821 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2822 ret
= ath5k_chan_set(sc
, conf
->channel
);
2827 if ((changed
& IEEE80211_CONF_CHANGE_POWER
) &&
2828 (sc
->power_level
!= conf
->power_level
)) {
2829 sc
->power_level
= conf
->power_level
;
2832 ath5k_hw_set_txpower_limit(ah
, (conf
->power_level
* 2));
2836 * 1) Move this on config_interface and handle each case
2837 * separately eg. when we have only one STA vif, use
2838 * AR5K_ANTMODE_SINGLE_AP
2840 * 2) Allow the user to change antenna mode eg. when only
2841 * one antenna is present
2843 * 3) Allow the user to set default/tx antenna when possible
2845 * 4) Default mode should handle 90% of the cases, together
2846 * with fixed a/b and single AP modes we should be able to
2847 * handle 99%. Sectored modes are extreme cases and i still
2848 * haven't found a usage for them. If we decide to support them,
2849 * then we must allow the user to set how many tx antennas we
2852 ath5k_hw_set_antenna_mode(ah
, AR5K_ANTMODE_DEFAULT
);
2855 mutex_unlock(&sc
->lock
);
2859 static u64
ath5k_prepare_multicast(struct ieee80211_hw
*hw
,
2860 int mc_count
, struct dev_addr_list
*mclist
)
2869 for (i
= 0; i
< mc_count
; i
++) {
2872 /* calculate XOR of eight 6-bit values */
2873 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2874 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2875 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2876 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2878 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2879 /* XXX: we might be able to just do this instead,
2880 * but not sure, needs testing, if we do use this we'd
2881 * neet to inform below to not reset the mcast */
2882 /* ath5k_hw_set_mcast_filterindex(ah,
2883 * mclist->dmi_addr[5]); */
2884 mclist
= mclist
->next
;
2887 return ((u64
)(mfilt
[1]) << 32) | mfilt
[0];
2890 #define SUPPORTED_FIF_FLAGS \
2891 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2892 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2893 FIF_BCN_PRBRESP_PROMISC
2895 * o always accept unicast, broadcast, and multicast traffic
2896 * o multicast traffic for all BSSIDs will be enabled if mac80211
2898 * o maintain current state of phy ofdm or phy cck error reception.
2899 * If the hardware detects any of these type of errors then
2900 * ath5k_hw_get_rx_filter() will pass to us the respective
2901 * hardware filters to be able to receive these type of frames.
2902 * o probe request frames are accepted only when operating in
2903 * hostap, adhoc, or monitor modes
2904 * o enable promiscuous mode according to the interface state
2906 * - when operating in adhoc mode so the 802.11 layer creates
2907 * node table entries for peers,
2908 * - when operating in station mode for collecting rssi data when
2909 * the station is otherwise quiet, or
2912 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2913 unsigned int changed_flags
,
2914 unsigned int *new_flags
,
2917 struct ath5k_softc
*sc
= hw
->priv
;
2918 struct ath5k_hw
*ah
= sc
->ah
;
2919 u32 mfilt
[2], rfilt
;
2921 mfilt
[0] = multicast
;
2922 mfilt
[1] = multicast
>> 32;
2924 /* Only deal with supported flags */
2925 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2926 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2928 /* If HW detects any phy or radar errors, leave those filters on.
2929 * Also, always enable Unicast, Broadcasts and Multicast
2930 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2931 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2932 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2933 AR5K_RX_FILTER_MCAST
);
2935 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2936 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2937 rfilt
|= AR5K_RX_FILTER_PROM
;
2938 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2940 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2944 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2945 if (*new_flags
& FIF_ALLMULTI
) {
2950 /* This is the best we can do */
2951 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2952 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2954 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2955 * and probes for any BSSID, this needs testing */
2956 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2957 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2959 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2960 * set we should only pass on control frames for this
2961 * station. This needs testing. I believe right now this
2962 * enables *all* control frames, which is OK.. but
2963 * but we should see if we can improve on granularity */
2964 if (*new_flags
& FIF_CONTROL
)
2965 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2967 /* Additional settings per mode -- this is per ath5k */
2969 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2971 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2972 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2973 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2974 if (sc
->opmode
!= NL80211_IFTYPE_STATION
)
2975 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2976 if (sc
->opmode
!= NL80211_IFTYPE_AP
&&
2977 sc
->opmode
!= NL80211_IFTYPE_MESH_POINT
&&
2978 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2979 rfilt
|= AR5K_RX_FILTER_PROM
;
2980 if ((sc
->opmode
== NL80211_IFTYPE_STATION
&& sc
->assoc
) ||
2981 sc
->opmode
== NL80211_IFTYPE_ADHOC
||
2982 sc
->opmode
== NL80211_IFTYPE_AP
)
2983 rfilt
|= AR5K_RX_FILTER_BEACON
;
2984 if (sc
->opmode
== NL80211_IFTYPE_MESH_POINT
)
2985 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2986 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2989 ath5k_hw_set_rx_filter(ah
, rfilt
);
2991 /* Set multicast bits */
2992 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2993 /* Set the cached hw filter flags, this will alter actually
2995 sc
->filter_flags
= rfilt
;
2999 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3000 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3001 struct ieee80211_key_conf
*key
)
3003 struct ath5k_softc
*sc
= hw
->priv
;
3006 if (modparam_nohwcrypt
)
3009 if (sc
->opmode
== NL80211_IFTYPE_AP
)
3023 mutex_lock(&sc
->lock
);
3027 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
,
3028 sta
? sta
->addr
: NULL
);
3030 ATH5K_ERR(sc
, "can't set the key\n");
3033 __set_bit(key
->keyidx
, sc
->keymap
);
3034 key
->hw_key_idx
= key
->keyidx
;
3035 key
->flags
|= (IEEE80211_KEY_FLAG_GENERATE_IV
|
3036 IEEE80211_KEY_FLAG_GENERATE_MMIC
);
3039 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
3040 __clear_bit(key
->keyidx
, sc
->keymap
);
3049 mutex_unlock(&sc
->lock
);
3054 ath5k_get_stats(struct ieee80211_hw
*hw
,
3055 struct ieee80211_low_level_stats
*stats
)
3057 struct ath5k_softc
*sc
= hw
->priv
;
3058 struct ath5k_hw
*ah
= sc
->ah
;
3061 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3063 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3069 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3070 struct ieee80211_tx_queue_stats
*stats
)
3072 struct ath5k_softc
*sc
= hw
->priv
;
3074 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3080 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3082 struct ath5k_softc
*sc
= hw
->priv
;
3084 return ath5k_hw_get_tsf64(sc
->ah
);
3088 ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3090 struct ath5k_softc
*sc
= hw
->priv
;
3092 ath5k_hw_set_tsf64(sc
->ah
, tsf
);
3096 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3098 struct ath5k_softc
*sc
= hw
->priv
;
3101 * in IBSS mode we need to update the beacon timers too.
3102 * this will also reset the TSF if we call it with 0
3104 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3105 ath5k_beacon_update_timers(sc
, 0);
3107 ath5k_hw_reset_tsf(sc
->ah
);
3111 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3112 * this is called only once at config_bss time, for AP we do it every
3113 * SWBA interrupt so that the TIM will reflect buffered frames.
3115 * Called with the beacon lock.
3118 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
3121 struct ath5k_softc
*sc
= hw
->priv
;
3122 struct sk_buff
*skb
;
3124 if (WARN_ON(!vif
)) {
3129 skb
= ieee80211_beacon_get(hw
, vif
);
3136 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3138 ath5k_txbuf_free(sc
, sc
->bbuf
);
3139 sc
->bbuf
->skb
= skb
;
3140 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3142 sc
->bbuf
->skb
= NULL
;
3148 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3150 struct ath5k_softc
*sc
= hw
->priv
;
3151 struct ath5k_hw
*ah
= sc
->ah
;
3153 rfilt
= ath5k_hw_get_rx_filter(ah
);
3155 rfilt
|= AR5K_RX_FILTER_BEACON
;
3157 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3158 ath5k_hw_set_rx_filter(ah
, rfilt
);
3159 sc
->filter_flags
= rfilt
;
3162 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
3163 struct ieee80211_vif
*vif
,
3164 struct ieee80211_bss_conf
*bss_conf
,
3167 struct ath5k_softc
*sc
= hw
->priv
;
3168 struct ath5k_hw
*ah
= sc
->ah
;
3169 unsigned long flags
;
3171 mutex_lock(&sc
->lock
);
3172 if (WARN_ON(sc
->vif
!= vif
))
3175 if (changes
& BSS_CHANGED_BSSID
) {
3176 /* Cache for later use during resets */
3177 memcpy(ah
->ah_bssid
, bss_conf
->bssid
, ETH_ALEN
);
3178 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3179 * a clean way of letting us retrieve this yet. */
3180 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
3184 if (changes
& BSS_CHANGED_BEACON_INT
)
3185 sc
->bintval
= bss_conf
->beacon_int
;
3187 if (changes
& BSS_CHANGED_ASSOC
) {
3188 sc
->assoc
= bss_conf
->assoc
;
3189 if (sc
->opmode
== NL80211_IFTYPE_STATION
)
3190 set_beacon_filter(hw
, sc
->assoc
);
3191 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3192 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3195 if (changes
& BSS_CHANGED_BEACON
) {
3196 spin_lock_irqsave(&sc
->block
, flags
);
3197 ath5k_beacon_update(hw
, vif
);
3198 spin_unlock_irqrestore(&sc
->block
, flags
);
3201 if (changes
& BSS_CHANGED_BEACON_ENABLED
)
3202 sc
->enable_beacon
= bss_conf
->enable_beacon
;
3204 if (changes
& (BSS_CHANGED_BEACON
| BSS_CHANGED_BEACON_ENABLED
|
3205 BSS_CHANGED_BEACON_INT
))
3206 ath5k_beacon_config(sc
);
3209 mutex_unlock(&sc
->lock
);
3212 static void ath5k_sw_scan_start(struct ieee80211_hw
*hw
)
3214 struct ath5k_softc
*sc
= hw
->priv
;
3216 ath5k_hw_set_ledstate(sc
->ah
, AR5K_LED_SCAN
);
3219 static void ath5k_sw_scan_complete(struct ieee80211_hw
*hw
)
3221 struct ath5k_softc
*sc
= hw
->priv
;
3222 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3223 AR5K_LED_ASSOC
: AR5K_LED_INIT
);