2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53 #include <linux/slab.h>
55 #include <net/ieee80211_radiotap.h>
57 #include <asm/unaligned.h>
63 static u8 ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
64 static int modparam_nohwcrypt
;
65 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
66 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
68 static int modparam_all_channels
;
69 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
70 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
87 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table
) = {
88 { PCI_VDEVICE(ATHEROS
, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS
, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS
, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS
, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS
, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2
, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM
, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS
, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS
, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS
, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS
, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS
, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS
, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS
, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS
, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS
, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS
, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS
, 0x001d) }, /* 2417 Nala */
108 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
111 static const struct ath5k_srev_name srev_names
[] = {
112 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
113 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
114 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
115 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
116 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
117 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
118 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
119 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
120 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
121 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
122 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
123 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
124 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
125 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
126 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
127 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
128 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
129 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
130 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
131 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
132 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
133 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
134 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
135 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
136 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
137 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
138 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
139 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
140 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
141 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
142 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
143 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
144 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
145 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
146 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
147 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
150 static const struct ieee80211_rate ath5k_rates
[] = {
152 .hw_value
= ATH5K_RATE_CODE_1M
, },
154 .hw_value
= ATH5K_RATE_CODE_2M
,
155 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
156 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
158 .hw_value
= ATH5K_RATE_CODE_5_5M
,
159 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
160 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
162 .hw_value
= ATH5K_RATE_CODE_11M
,
163 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
164 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
166 .hw_value
= ATH5K_RATE_CODE_6M
,
169 .hw_value
= ATH5K_RATE_CODE_9M
,
172 .hw_value
= ATH5K_RATE_CODE_12M
,
175 .hw_value
= ATH5K_RATE_CODE_18M
,
178 .hw_value
= ATH5K_RATE_CODE_24M
,
181 .hw_value
= ATH5K_RATE_CODE_36M
,
184 .hw_value
= ATH5K_RATE_CODE_48M
,
187 .hw_value
= ATH5K_RATE_CODE_54M
,
193 * Prototypes - PCI stack related functions
195 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
196 const struct pci_device_id
*id
);
197 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
199 static int ath5k_pci_suspend(struct device
*dev
);
200 static int ath5k_pci_resume(struct device
*dev
);
202 SIMPLE_DEV_PM_OPS(ath5k_pm_ops
, ath5k_pci_suspend
, ath5k_pci_resume
);
203 #define ATH5K_PM_OPS (&ath5k_pm_ops)
205 #define ATH5K_PM_OPS NULL
206 #endif /* CONFIG_PM */
208 static struct pci_driver ath5k_pci_driver
= {
209 .name
= KBUILD_MODNAME
,
210 .id_table
= ath5k_pci_id_table
,
211 .probe
= ath5k_pci_probe
,
212 .remove
= __devexit_p(ath5k_pci_remove
),
213 .driver
.pm
= ATH5K_PM_OPS
,
219 * Prototypes - MAC 802.11 stack related functions
221 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
222 static int ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
223 struct ath5k_txq
*txq
);
224 static int ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
);
225 static int ath5k_reset_wake(struct ath5k_softc
*sc
);
226 static int ath5k_start(struct ieee80211_hw
*hw
);
227 static void ath5k_stop(struct ieee80211_hw
*hw
);
228 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
229 struct ieee80211_vif
*vif
);
230 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
231 struct ieee80211_vif
*vif
);
232 static int ath5k_config(struct ieee80211_hw
*hw
, u32 changed
);
233 static u64
ath5k_prepare_multicast(struct ieee80211_hw
*hw
,
234 int mc_count
, struct dev_addr_list
*mc_list
);
235 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
236 unsigned int changed_flags
,
237 unsigned int *new_flags
,
239 static int ath5k_set_key(struct ieee80211_hw
*hw
,
240 enum set_key_cmd cmd
,
241 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
242 struct ieee80211_key_conf
*key
);
243 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
244 struct ieee80211_low_level_stats
*stats
);
245 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
246 static void ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
);
247 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
248 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
249 struct ieee80211_vif
*vif
);
250 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
251 struct ieee80211_vif
*vif
,
252 struct ieee80211_bss_conf
*bss_conf
,
254 static void ath5k_sw_scan_start(struct ieee80211_hw
*hw
);
255 static void ath5k_sw_scan_complete(struct ieee80211_hw
*hw
);
256 static void ath5k_set_coverage_class(struct ieee80211_hw
*hw
,
259 static const struct ieee80211_ops ath5k_hw_ops
= {
261 .start
= ath5k_start
,
263 .add_interface
= ath5k_add_interface
,
264 .remove_interface
= ath5k_remove_interface
,
265 .config
= ath5k_config
,
266 .prepare_multicast
= ath5k_prepare_multicast
,
267 .configure_filter
= ath5k_configure_filter
,
268 .set_key
= ath5k_set_key
,
269 .get_stats
= ath5k_get_stats
,
271 .get_tsf
= ath5k_get_tsf
,
272 .set_tsf
= ath5k_set_tsf
,
273 .reset_tsf
= ath5k_reset_tsf
,
274 .bss_info_changed
= ath5k_bss_info_changed
,
275 .sw_scan_start
= ath5k_sw_scan_start
,
276 .sw_scan_complete
= ath5k_sw_scan_complete
,
277 .set_coverage_class
= ath5k_set_coverage_class
,
281 * Prototypes - Internal functions
284 static int ath5k_attach(struct pci_dev
*pdev
,
285 struct ieee80211_hw
*hw
);
286 static void ath5k_detach(struct pci_dev
*pdev
,
287 struct ieee80211_hw
*hw
);
288 /* Channel/mode setup */
289 static inline short ath5k_ieee2mhz(short chan
);
290 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
291 struct ieee80211_channel
*channels
,
294 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
295 static int ath5k_chan_set(struct ath5k_softc
*sc
,
296 struct ieee80211_channel
*chan
);
297 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
299 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
301 /* Descriptor setup */
302 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
303 struct pci_dev
*pdev
);
304 static void ath5k_desc_free(struct ath5k_softc
*sc
,
305 struct pci_dev
*pdev
);
307 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
308 struct ath5k_buf
*bf
);
309 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
310 struct ath5k_buf
*bf
,
311 struct ath5k_txq
*txq
);
312 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
313 struct ath5k_buf
*bf
)
318 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
320 dev_kfree_skb_any(bf
->skb
);
324 static inline void ath5k_rxbuf_free(struct ath5k_softc
*sc
,
325 struct ath5k_buf
*bf
)
327 struct ath5k_hw
*ah
= sc
->ah
;
328 struct ath_common
*common
= ath5k_hw_common(ah
);
333 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, common
->rx_bufsize
,
335 dev_kfree_skb_any(bf
->skb
);
341 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
342 int qtype
, int subtype
);
343 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
344 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
345 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
346 struct ath5k_txq
*txq
);
347 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
348 static void ath5k_txq_release(struct ath5k_softc
*sc
);
350 static int ath5k_rx_start(struct ath5k_softc
*sc
);
351 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
352 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
353 struct ath5k_desc
*ds
,
355 struct ath5k_rx_status
*rs
);
356 static void ath5k_tasklet_rx(unsigned long data
);
358 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
359 struct ath5k_txq
*txq
);
360 static void ath5k_tasklet_tx(unsigned long data
);
361 /* Beacon handling */
362 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
363 struct ath5k_buf
*bf
);
364 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
365 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
366 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
367 static void ath5k_tasklet_beacon(unsigned long data
);
369 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
371 u64 tsf
= ath5k_hw_get_tsf64(ah
);
373 if ((tsf
& 0x7fff) < rstamp
)
376 return (tsf
& ~0x7fff) | rstamp
;
379 /* Interrupt handling */
380 static int ath5k_init(struct ath5k_softc
*sc
);
381 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
382 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
383 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
384 static void ath5k_tasklet_reset(unsigned long data
);
386 static void ath5k_tasklet_calibrate(unsigned long data
);
389 * Module init/exit functions
398 ret
= pci_register_driver(&ath5k_pci_driver
);
400 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
410 pci_unregister_driver(&ath5k_pci_driver
);
412 ath5k_debug_finish();
415 module_init(init_ath5k_pci
);
416 module_exit(exit_ath5k_pci
);
419 /********************\
420 * PCI Initialization *
421 \********************/
424 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
426 const char *name
= "xxxxx";
429 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
430 if (srev_names
[i
].sr_type
!= type
)
433 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
434 name
= srev_names
[i
].sr_name
;
436 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
437 name
= srev_names
[i
].sr_name
;
444 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
446 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
447 return ath5k_hw_reg_read(ah
, reg_offset
);
450 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
452 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
453 ath5k_hw_reg_write(ah
, val
, reg_offset
);
456 static const struct ath_ops ath5k_common_ops
= {
457 .read
= ath5k_ioread32
,
458 .write
= ath5k_iowrite32
,
462 ath5k_pci_probe(struct pci_dev
*pdev
,
463 const struct pci_device_id
*id
)
466 struct ath5k_softc
*sc
;
467 struct ath_common
*common
;
468 struct ieee80211_hw
*hw
;
472 ret
= pci_enable_device(pdev
);
474 dev_err(&pdev
->dev
, "can't enable device\n");
478 /* XXX 32-bit addressing only */
479 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
481 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
486 * Cache line size is used to size and align various
487 * structures used to communicate with the hardware.
489 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
492 * Linux 2.4.18 (at least) writes the cache line size
493 * register as a 16-bit wide register which is wrong.
494 * We must have this setup properly for rx buffer
495 * DMA to work so force a reasonable value here if it
498 csz
= L1_CACHE_BYTES
>> 2;
499 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
502 * The default setting of latency timer yields poor results,
503 * set it to the value used by other systems. It may be worth
504 * tweaking this setting more.
506 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
508 /* Enable bus mastering */
509 pci_set_master(pdev
);
512 * Disable the RETRY_TIMEOUT register (0x41) to keep
513 * PCI Tx retries from interfering with C3 CPU state.
515 pci_write_config_byte(pdev
, 0x41, 0);
517 ret
= pci_request_region(pdev
, 0, "ath5k");
519 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
523 mem
= pci_iomap(pdev
, 0, 0);
525 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
531 * Allocate hw (mac80211 main struct)
532 * and hw->priv (driver private data)
534 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
536 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
541 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
543 /* Initialize driver private data */
544 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
545 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
546 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
547 IEEE80211_HW_SIGNAL_DBM
|
548 IEEE80211_HW_NOISE_DBM
;
550 hw
->wiphy
->interface_modes
=
551 BIT(NL80211_IFTYPE_AP
) |
552 BIT(NL80211_IFTYPE_STATION
) |
553 BIT(NL80211_IFTYPE_ADHOC
) |
554 BIT(NL80211_IFTYPE_MESH_POINT
);
556 hw
->extra_tx_headroom
= 2;
557 hw
->channel_change_time
= 5000;
562 ath5k_debug_init_device(sc
);
565 * Mark the device as detached to avoid processing
566 * interrupts until setup is complete.
568 __set_bit(ATH_STAT_INVALID
, sc
->status
);
570 sc
->iobase
= mem
; /* So we can unmap it on detach */
571 sc
->opmode
= NL80211_IFTYPE_STATION
;
573 mutex_init(&sc
->lock
);
574 spin_lock_init(&sc
->rxbuflock
);
575 spin_lock_init(&sc
->txbuflock
);
576 spin_lock_init(&sc
->block
);
578 /* Set private data */
579 pci_set_drvdata(pdev
, hw
);
581 /* Setup interrupt handler */
582 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
584 ATH5K_ERR(sc
, "request_irq failed\n");
588 /*If we passed the test malloc a ath5k_hw struct*/
589 sc
->ah
= kzalloc(sizeof(struct ath5k_hw
), GFP_KERNEL
);
592 ATH5K_ERR(sc
, "out of memory\n");
597 sc
->ah
->ah_iobase
= sc
->iobase
;
598 common
= ath5k_hw_common(sc
->ah
);
599 common
->ops
= &ath5k_common_ops
;
602 common
->cachelsz
= csz
<< 2; /* convert to bytes */
604 /* Initialize device */
605 ret
= ath5k_hw_attach(sc
);
610 /* set up multi-rate retry capabilities */
611 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
613 hw
->max_rate_tries
= 11;
616 /* Finish private driver data initialization */
617 ret
= ath5k_attach(pdev
, hw
);
621 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
622 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
624 sc
->ah
->ah_phy_revision
);
626 if (!sc
->ah
->ah_single_chip
) {
627 /* Single chip radio (!RF5111) */
628 if (sc
->ah
->ah_radio_5ghz_revision
&&
629 !sc
->ah
->ah_radio_2ghz_revision
) {
630 /* No 5GHz support -> report 2GHz radio */
631 if (!test_bit(AR5K_MODE_11A
,
632 sc
->ah
->ah_capabilities
.cap_mode
)) {
633 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
634 ath5k_chip_name(AR5K_VERSION_RAD
,
635 sc
->ah
->ah_radio_5ghz_revision
),
636 sc
->ah
->ah_radio_5ghz_revision
);
637 /* No 2GHz support (5110 and some
638 * 5Ghz only cards) -> report 5Ghz radio */
639 } else if (!test_bit(AR5K_MODE_11B
,
640 sc
->ah
->ah_capabilities
.cap_mode
)) {
641 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
642 ath5k_chip_name(AR5K_VERSION_RAD
,
643 sc
->ah
->ah_radio_5ghz_revision
),
644 sc
->ah
->ah_radio_5ghz_revision
);
645 /* Multiband radio */
647 ATH5K_INFO(sc
, "RF%s multiband radio found"
649 ath5k_chip_name(AR5K_VERSION_RAD
,
650 sc
->ah
->ah_radio_5ghz_revision
),
651 sc
->ah
->ah_radio_5ghz_revision
);
654 /* Multi chip radio (RF5111 - RF2111) ->
655 * report both 2GHz/5GHz radios */
656 else if (sc
->ah
->ah_radio_5ghz_revision
&&
657 sc
->ah
->ah_radio_2ghz_revision
){
658 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
659 ath5k_chip_name(AR5K_VERSION_RAD
,
660 sc
->ah
->ah_radio_5ghz_revision
),
661 sc
->ah
->ah_radio_5ghz_revision
);
662 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
663 ath5k_chip_name(AR5K_VERSION_RAD
,
664 sc
->ah
->ah_radio_2ghz_revision
),
665 sc
->ah
->ah_radio_2ghz_revision
);
670 /* ready to process interrupts */
671 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
675 ath5k_hw_detach(sc
->ah
);
677 free_irq(pdev
->irq
, sc
);
681 ieee80211_free_hw(hw
);
683 pci_iounmap(pdev
, mem
);
685 pci_release_region(pdev
, 0);
687 pci_disable_device(pdev
);
692 static void __devexit
693 ath5k_pci_remove(struct pci_dev
*pdev
)
695 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
696 struct ath5k_softc
*sc
= hw
->priv
;
698 ath5k_debug_finish_device(sc
);
699 ath5k_detach(pdev
, hw
);
700 ath5k_hw_detach(sc
->ah
);
702 free_irq(pdev
->irq
, sc
);
703 pci_iounmap(pdev
, sc
->iobase
);
704 pci_release_region(pdev
, 0);
705 pci_disable_device(pdev
);
706 ieee80211_free_hw(hw
);
710 static int ath5k_pci_suspend(struct device
*dev
)
712 struct ieee80211_hw
*hw
= pci_get_drvdata(to_pci_dev(dev
));
713 struct ath5k_softc
*sc
= hw
->priv
;
719 static int ath5k_pci_resume(struct device
*dev
)
721 struct pci_dev
*pdev
= to_pci_dev(dev
);
722 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
723 struct ath5k_softc
*sc
= hw
->priv
;
726 * Suspend/Resume resets the PCI configuration space, so we have to
727 * re-disable the RETRY_TIMEOUT register (0x41) to keep
728 * PCI Tx retries from interfering with C3 CPU state
730 pci_write_config_byte(pdev
, 0x41, 0);
732 ath5k_led_enable(sc
);
735 #endif /* CONFIG_PM */
738 /***********************\
739 * Driver Initialization *
740 \***********************/
742 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
744 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
745 struct ath5k_softc
*sc
= hw
->priv
;
746 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(sc
->ah
);
748 return ath_reg_notifier_apply(wiphy
, request
, regulatory
);
752 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
754 struct ath5k_softc
*sc
= hw
->priv
;
755 struct ath5k_hw
*ah
= sc
->ah
;
756 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
757 u8 mac
[ETH_ALEN
] = {};
760 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
763 * Check if the MAC has multi-rate retry support.
764 * We do this by trying to setup a fake extended
765 * descriptor. MAC's that don't have support will
766 * return false w/o doing anything. MAC's that do
767 * support it will return true w/o doing anything.
769 ret
= ah
->ah_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
773 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
776 * Collect the channel list. The 802.11 layer
777 * is resposible for filtering this list based
778 * on settings like the phy mode and regulatory
779 * domain restrictions.
781 ret
= ath5k_setup_bands(hw
);
783 ATH5K_ERR(sc
, "can't get channels\n");
787 /* NB: setup here so ath5k_rate_update is happy */
788 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
789 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
791 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
794 * Allocate tx+rx descriptors and populate the lists.
796 ret
= ath5k_desc_alloc(sc
, pdev
);
798 ATH5K_ERR(sc
, "can't allocate descriptors\n");
803 * Allocate hardware transmit queues: one queue for
804 * beacon frames and one data queue for each QoS
805 * priority. Note that hw functions handle reseting
806 * these queues at the needed time.
808 ret
= ath5k_beaconq_setup(ah
);
810 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
814 sc
->cabq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_CAB
, 0);
815 if (IS_ERR(sc
->cabq
)) {
816 ATH5K_ERR(sc
, "can't setup cab queue\n");
817 ret
= PTR_ERR(sc
->cabq
);
821 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
822 if (IS_ERR(sc
->txq
)) {
823 ATH5K_ERR(sc
, "can't setup xmit queue\n");
824 ret
= PTR_ERR(sc
->txq
);
828 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
829 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
830 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
831 tasklet_init(&sc
->calib
, ath5k_tasklet_calibrate
, (unsigned long)sc
);
832 tasklet_init(&sc
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)sc
);
834 ret
= ath5k_eeprom_read_mac(ah
, mac
);
836 ATH5K_ERR(sc
, "unable to read address from EEPROM: 0x%04x\n",
841 SET_IEEE80211_PERM_ADDR(hw
, mac
);
842 /* All MAC address bits matter for ACKs */
843 memcpy(sc
->bssidmask
, ath_bcast_mac
, ETH_ALEN
);
844 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
846 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
847 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
849 ATH5K_ERR(sc
, "can't initialize regulatory system\n");
853 ret
= ieee80211_register_hw(hw
);
855 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
859 if (!ath_is_world_regd(regulatory
))
860 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
866 ath5k_txq_release(sc
);
868 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
870 ath5k_desc_free(sc
, pdev
);
876 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
878 struct ath5k_softc
*sc
= hw
->priv
;
881 * NB: the order of these is important:
882 * o call the 802.11 layer before detaching ath5k_hw to
883 * insure callbacks into the driver to delete global
884 * key cache entries can be handled
885 * o reclaim the tx queue data structures after calling
886 * the 802.11 layer as we'll get called back to reclaim
887 * node state and potentially want to use them
888 * o to cleanup the tx queues the hal is called, so detach
890 * XXX: ??? detach ath5k_hw ???
891 * Other than that, it's straightforward...
893 ieee80211_unregister_hw(hw
);
894 ath5k_desc_free(sc
, pdev
);
895 ath5k_txq_release(sc
);
896 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
897 ath5k_unregister_leds(sc
);
900 * NB: can't reclaim these until after ieee80211_ifdetach
901 * returns because we'll get called back to reclaim node
902 * state and potentially want to use them.
909 /********************\
910 * Channel/mode setup *
911 \********************/
914 * Convert IEEE channel number to MHz frequency.
917 ath5k_ieee2mhz(short chan
)
919 if (chan
<= 14 || chan
>= 27)
920 return ieee80211chan2mhz(chan
);
922 return 2212 + chan
* 20;
926 * Returns true for the channel numbers used without all_channels modparam.
928 static bool ath5k_is_standard_channel(short chan
)
930 return ((chan
<= 14) ||
932 ((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
934 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
936 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165));
940 ath5k_copy_channels(struct ath5k_hw
*ah
,
941 struct ieee80211_channel
*channels
,
945 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
947 if (!test_bit(mode
, ah
->ah_modes
))
952 case AR5K_MODE_11A_TURBO
:
953 /* 1..220, but 2GHz frequencies are filtered by check_channel */
955 chfreq
= CHANNEL_5GHZ
;
959 case AR5K_MODE_11G_TURBO
:
961 chfreq
= CHANNEL_2GHZ
;
964 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
968 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
970 freq
= ath5k_ieee2mhz(ch
);
972 /* Check if channel is supported by the chipset */
973 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
976 if (!modparam_all_channels
&& !ath5k_is_standard_channel(ch
))
979 /* Write channel info and increment counter */
980 channels
[count
].center_freq
= freq
;
981 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
982 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
986 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
988 case AR5K_MODE_11A_TURBO
:
989 case AR5K_MODE_11G_TURBO
:
990 channels
[count
].hw_value
= chfreq
|
991 CHANNEL_OFDM
| CHANNEL_TURBO
;
994 channels
[count
].hw_value
= CHANNEL_B
;
1005 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
1009 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
1010 sc
->rate_idx
[b
->band
][i
] = -1;
1012 for (i
= 0; i
< b
->n_bitrates
; i
++) {
1013 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
1014 if (b
->bitrates
[i
].hw_value_short
)
1015 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
1020 ath5k_setup_bands(struct ieee80211_hw
*hw
)
1022 struct ath5k_softc
*sc
= hw
->priv
;
1023 struct ath5k_hw
*ah
= sc
->ah
;
1024 struct ieee80211_supported_band
*sband
;
1025 int max_c
, count_c
= 0;
1028 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
1029 max_c
= ARRAY_SIZE(sc
->channels
);
1032 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1033 sband
->band
= IEEE80211_BAND_2GHZ
;
1034 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
1036 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1038 memcpy(sband
->bitrates
, &ath5k_rates
[0],
1039 sizeof(struct ieee80211_rate
) * 12);
1040 sband
->n_bitrates
= 12;
1042 sband
->channels
= sc
->channels
;
1043 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1044 AR5K_MODE_11G
, max_c
);
1046 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
1047 count_c
= sband
->n_channels
;
1049 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1051 memcpy(sband
->bitrates
, &ath5k_rates
[0],
1052 sizeof(struct ieee80211_rate
) * 4);
1053 sband
->n_bitrates
= 4;
1055 /* 5211 only supports B rates and uses 4bit rate codes
1056 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1059 if (ah
->ah_version
== AR5K_AR5211
) {
1060 for (i
= 0; i
< 4; i
++) {
1061 sband
->bitrates
[i
].hw_value
=
1062 sband
->bitrates
[i
].hw_value
& 0xF;
1063 sband
->bitrates
[i
].hw_value_short
=
1064 sband
->bitrates
[i
].hw_value_short
& 0xF;
1068 sband
->channels
= sc
->channels
;
1069 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1070 AR5K_MODE_11B
, max_c
);
1072 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
1073 count_c
= sband
->n_channels
;
1076 ath5k_setup_rate_idx(sc
, sband
);
1078 /* 5GHz band, A mode */
1079 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1080 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1081 sband
->band
= IEEE80211_BAND_5GHZ
;
1082 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
1084 memcpy(sband
->bitrates
, &ath5k_rates
[4],
1085 sizeof(struct ieee80211_rate
) * 8);
1086 sband
->n_bitrates
= 8;
1088 sband
->channels
= &sc
->channels
[count_c
];
1089 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1090 AR5K_MODE_11A
, max_c
);
1092 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1094 ath5k_setup_rate_idx(sc
, sband
);
1096 ath5k_debug_dump_bands(sc
);
1102 * Set/change channels. We always reset the chip.
1103 * To accomplish this we must first cleanup any pending DMA,
1104 * then restart stuff after a la ath5k_init.
1106 * Called with sc->lock.
1109 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1111 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1112 sc
->curchan
->center_freq
, chan
->center_freq
);
1115 * To switch channels clear any pending DMA operations;
1116 * wait long enough for the RX fifo to drain, reset the
1117 * hardware at the new frequency, and then re-enable
1118 * the relevant bits of the h/w.
1120 return ath5k_reset(sc
, chan
);
1124 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1128 if (mode
== AR5K_MODE_11A
) {
1129 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1131 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1136 ath5k_mode_setup(struct ath5k_softc
*sc
)
1138 struct ath5k_hw
*ah
= sc
->ah
;
1141 ah
->ah_op_mode
= sc
->opmode
;
1143 /* configure rx filter */
1144 rfilt
= sc
->filter_flags
;
1145 ath5k_hw_set_rx_filter(ah
, rfilt
);
1147 if (ath5k_hw_hasbssidmask(ah
))
1148 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1150 /* configure operational mode */
1151 ath5k_hw_set_opmode(ah
);
1153 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1157 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1161 /* return base rate on errors */
1162 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
1163 "hw_rix out of bounds: %x\n", hw_rix
))
1166 rix
= sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1167 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
1178 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_softc
*sc
, dma_addr_t
*skb_addr
)
1180 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
1181 struct sk_buff
*skb
;
1184 * Allocate buffer with headroom_needed space for the
1185 * fake physical layer header at the start.
1187 skb
= ath_rxbuf_alloc(common
,
1192 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1193 common
->rx_bufsize
);
1197 *skb_addr
= pci_map_single(sc
->pdev
,
1198 skb
->data
, common
->rx_bufsize
,
1199 PCI_DMA_FROMDEVICE
);
1200 if (unlikely(pci_dma_mapping_error(sc
->pdev
, *skb_addr
))) {
1201 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1209 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1211 struct ath5k_hw
*ah
= sc
->ah
;
1212 struct sk_buff
*skb
= bf
->skb
;
1213 struct ath5k_desc
*ds
;
1216 skb
= ath5k_rx_skb_alloc(sc
, &bf
->skbaddr
);
1223 * Setup descriptors. For receive we always terminate
1224 * the descriptor list with a self-linked entry so we'll
1225 * not get overrun under high load (as can happen with a
1226 * 5212 when ANI processing enables PHY error frames).
1228 * To insure the last descriptor is self-linked we create
1229 * each descriptor as self-linked and add it to the end. As
1230 * each additional descriptor is added the previous self-linked
1231 * entry is ``fixed'' naturally. This should be safe even
1232 * if DMA is happening. When processing RX interrupts we
1233 * never remove/process the last, self-linked, entry on the
1234 * descriptor list. This insures the hardware always has
1235 * someplace to write a new frame.
1238 ds
->ds_link
= bf
->daddr
; /* link to self */
1239 ds
->ds_data
= bf
->skbaddr
;
1240 ah
->ah_setup_rx_desc(ah
, ds
,
1241 skb_tailroom(skb
), /* buffer size */
1244 if (sc
->rxlink
!= NULL
)
1245 *sc
->rxlink
= bf
->daddr
;
1246 sc
->rxlink
= &ds
->ds_link
;
1250 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1252 struct ieee80211_hdr
*hdr
;
1253 enum ath5k_pkt_type htype
;
1256 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1257 fc
= hdr
->frame_control
;
1259 if (ieee80211_is_beacon(fc
))
1260 htype
= AR5K_PKT_TYPE_BEACON
;
1261 else if (ieee80211_is_probe_resp(fc
))
1262 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
1263 else if (ieee80211_is_atim(fc
))
1264 htype
= AR5K_PKT_TYPE_ATIM
;
1265 else if (ieee80211_is_pspoll(fc
))
1266 htype
= AR5K_PKT_TYPE_PSPOLL
;
1268 htype
= AR5K_PKT_TYPE_NORMAL
;
1274 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
1275 struct ath5k_txq
*txq
)
1277 struct ath5k_hw
*ah
= sc
->ah
;
1278 struct ath5k_desc
*ds
= bf
->desc
;
1279 struct sk_buff
*skb
= bf
->skb
;
1280 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1281 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1282 struct ieee80211_rate
*rate
;
1283 unsigned int mrr_rate
[3], mrr_tries
[3];
1290 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1292 /* XXX endianness */
1293 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1296 rate
= ieee80211_get_tx_rate(sc
->hw
, info
);
1298 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1299 flags
|= AR5K_TXDESC_NOACK
;
1301 rc_flags
= info
->control
.rates
[0].flags
;
1302 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
1303 rate
->hw_value_short
: rate
->hw_value
;
1307 /* FIXME: If we are in g mode and rate is a CCK rate
1308 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1309 * from tx power (value is in dB units already) */
1310 if (info
->control
.hw_key
) {
1311 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1312 pktlen
+= info
->control
.hw_key
->icv_len
;
1314 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1315 flags
|= AR5K_TXDESC_RTSENA
;
1316 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1317 duration
= le16_to_cpu(ieee80211_rts_duration(sc
->hw
,
1318 sc
->vif
, pktlen
, info
));
1320 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1321 flags
|= AR5K_TXDESC_CTSENA
;
1322 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1323 duration
= le16_to_cpu(ieee80211_ctstoself_duration(sc
->hw
,
1324 sc
->vif
, pktlen
, info
));
1326 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1327 ieee80211_get_hdrlen_from_skb(skb
),
1328 get_hw_packet_type(skb
),
1329 (sc
->power_level
* 2),
1331 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
1332 cts_rate
, duration
);
1336 memset(mrr_rate
, 0, sizeof(mrr_rate
));
1337 memset(mrr_tries
, 0, sizeof(mrr_tries
));
1338 for (i
= 0; i
< 3; i
++) {
1339 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
1343 mrr_rate
[i
] = rate
->hw_value
;
1344 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
1347 ah
->ah_setup_mrr_tx_desc(ah
, ds
,
1348 mrr_rate
[0], mrr_tries
[0],
1349 mrr_rate
[1], mrr_tries
[1],
1350 mrr_rate
[2], mrr_tries
[2]);
1353 ds
->ds_data
= bf
->skbaddr
;
1355 spin_lock_bh(&txq
->lock
);
1356 list_add_tail(&bf
->list
, &txq
->q
);
1357 if (txq
->link
== NULL
) /* is this first packet? */
1358 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1359 else /* no, so only link it */
1360 *txq
->link
= bf
->daddr
;
1362 txq
->link
= &ds
->ds_link
;
1363 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1365 spin_unlock_bh(&txq
->lock
);
1369 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1373 /*******************\
1374 * Descriptors setup *
1375 \*******************/
1378 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1380 struct ath5k_desc
*ds
;
1381 struct ath5k_buf
*bf
;
1386 /* allocate descriptors */
1387 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1388 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1389 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1390 if (sc
->desc
== NULL
) {
1391 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1396 da
= sc
->desc_daddr
;
1397 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1398 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1400 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1401 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1403 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1409 INIT_LIST_HEAD(&sc
->rxbuf
);
1410 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1413 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1416 INIT_LIST_HEAD(&sc
->txbuf
);
1417 sc
->txbuf_len
= ATH_TXBUF
;
1418 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1419 da
+= sizeof(*ds
)) {
1422 list_add_tail(&bf
->list
, &sc
->txbuf
);
1432 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1439 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1441 struct ath5k_buf
*bf
;
1443 ath5k_txbuf_free(sc
, sc
->bbuf
);
1444 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1445 ath5k_txbuf_free(sc
, bf
);
1446 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1447 ath5k_rxbuf_free(sc
, bf
);
1449 /* Free memory associated with all descriptors */
1450 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1464 static struct ath5k_txq
*
1465 ath5k_txq_setup(struct ath5k_softc
*sc
,
1466 int qtype
, int subtype
)
1468 struct ath5k_hw
*ah
= sc
->ah
;
1469 struct ath5k_txq
*txq
;
1470 struct ath5k_txq_info qi
= {
1471 .tqi_subtype
= subtype
,
1472 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1473 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1474 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1479 * Enable interrupts only for EOL and DESC conditions.
1480 * We mark tx descriptors to receive a DESC interrupt
1481 * when a tx queue gets deep; otherwise waiting for the
1482 * EOL to reap descriptors. Note that this is done to
1483 * reduce interrupt load and this only defers reaping
1484 * descriptors, never transmitting frames. Aside from
1485 * reducing interrupts this also permits more concurrency.
1486 * The only potential downside is if the tx queue backs
1487 * up in which case the top half of the kernel may backup
1488 * due to a lack of tx descriptors.
1490 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1491 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1492 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1495 * NB: don't print a message, this happens
1496 * normally on parts with too few tx queues
1498 return ERR_PTR(qnum
);
1500 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1501 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1502 qnum
, ARRAY_SIZE(sc
->txqs
));
1503 ath5k_hw_release_tx_queue(ah
, qnum
);
1504 return ERR_PTR(-EINVAL
);
1506 txq
= &sc
->txqs
[qnum
];
1510 INIT_LIST_HEAD(&txq
->q
);
1511 spin_lock_init(&txq
->lock
);
1514 return &sc
->txqs
[qnum
];
1518 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1520 struct ath5k_txq_info qi
= {
1521 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1522 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1523 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1524 /* NB: for dynamic turbo, don't enable any other interrupts */
1525 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1528 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1532 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1534 struct ath5k_hw
*ah
= sc
->ah
;
1535 struct ath5k_txq_info qi
;
1538 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1542 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1543 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1545 * Always burst out beacon and CAB traffic
1546 * (aifs = cwmin = cwmax = 0)
1551 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1553 * Adhoc mode; backoff between 0 and (2 * cw_min).
1557 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1560 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1561 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1562 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1564 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1566 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1567 "hardware queue!\n", __func__
);
1570 ret
= ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */
1574 /* reconfigure cabq with ready time to 80% of beacon_interval */
1575 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1579 qi
.tqi_ready_time
= (sc
->bintval
* 80) / 100;
1580 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1584 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1590 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1592 struct ath5k_buf
*bf
, *bf0
;
1595 * NB: this assumes output has been stopped and
1596 * we do not need to block ath5k_tx_tasklet
1598 spin_lock_bh(&txq
->lock
);
1599 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1600 ath5k_debug_printtxbuf(sc
, bf
);
1602 ath5k_txbuf_free(sc
, bf
);
1604 spin_lock_bh(&sc
->txbuflock
);
1605 list_move_tail(&bf
->list
, &sc
->txbuf
);
1607 spin_unlock_bh(&sc
->txbuflock
);
1610 spin_unlock_bh(&txq
->lock
);
1614 * Drain the transmit queues and reclaim resources.
1617 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1619 struct ath5k_hw
*ah
= sc
->ah
;
1622 /* XXX return value */
1623 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1624 /* don't touch the hardware if marked invalid */
1625 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1626 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1627 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1628 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1629 if (sc
->txqs
[i
].setup
) {
1630 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1631 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1634 ath5k_hw_get_txdp(ah
,
1639 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1641 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1642 if (sc
->txqs
[i
].setup
)
1643 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1647 ath5k_txq_release(struct ath5k_softc
*sc
)
1649 struct ath5k_txq
*txq
= sc
->txqs
;
1652 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1654 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1667 * Enable the receive h/w following a reset.
1670 ath5k_rx_start(struct ath5k_softc
*sc
)
1672 struct ath5k_hw
*ah
= sc
->ah
;
1673 struct ath_common
*common
= ath5k_hw_common(ah
);
1674 struct ath5k_buf
*bf
;
1677 common
->rx_bufsize
= roundup(IEEE80211_MAX_LEN
, common
->cachelsz
);
1679 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1680 common
->cachelsz
, common
->rx_bufsize
);
1682 spin_lock_bh(&sc
->rxbuflock
);
1684 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1685 ret
= ath5k_rxbuf_setup(sc
, bf
);
1687 spin_unlock_bh(&sc
->rxbuflock
);
1691 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1692 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1693 spin_unlock_bh(&sc
->rxbuflock
);
1695 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1696 ath5k_mode_setup(sc
); /* set filters, etc. */
1697 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1705 * Disable the receive h/w in preparation for a reset.
1708 ath5k_rx_stop(struct ath5k_softc
*sc
)
1710 struct ath5k_hw
*ah
= sc
->ah
;
1712 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1713 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1714 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1716 ath5k_debug_printrxbuffs(sc
, ah
);
1718 sc
->rxlink
= NULL
; /* just in case */
1722 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1723 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1725 struct ath5k_hw
*ah
= sc
->ah
;
1726 struct ath_common
*common
= ath5k_hw_common(ah
);
1727 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1728 unsigned int keyix
, hlen
;
1730 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1731 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1732 return RX_FLAG_DECRYPTED
;
1734 /* Apparently when a default key is used to decrypt the packet
1735 the hw does not set the index used to decrypt. In such cases
1736 get the index from the packet. */
1737 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1738 if (ieee80211_has_protected(hdr
->frame_control
) &&
1739 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1740 skb
->len
>= hlen
+ 4) {
1741 keyix
= skb
->data
[hlen
+ 3] >> 6;
1743 if (test_bit(keyix
, common
->keymap
))
1744 return RX_FLAG_DECRYPTED
;
1752 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1753 struct ieee80211_rx_status
*rxs
)
1755 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
1758 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1760 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1761 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1762 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) == 0) {
1764 * Received an IBSS beacon with the same BSSID. Hardware *must*
1765 * have updated the local TSF. We have to work around various
1766 * hardware bugs, though...
1768 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1769 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1770 hw_tu
= TSF_TO_TU(tsf
);
1772 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1773 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1774 (unsigned long long)bc_tstamp
,
1775 (unsigned long long)rxs
->mactime
,
1776 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1777 (unsigned long long)tsf
);
1780 * Sometimes the HW will give us a wrong tstamp in the rx
1781 * status, causing the timestamp extension to go wrong.
1782 * (This seems to happen especially with beacon frames bigger
1783 * than 78 byte (incl. FCS))
1784 * But we know that the receive timestamp must be later than the
1785 * timestamp of the beacon since HW must have synced to that.
1787 * NOTE: here we assume mactime to be after the frame was
1788 * received, not like mac80211 which defines it at the start.
1790 if (bc_tstamp
> rxs
->mactime
) {
1791 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1792 "fixing mactime from %llx to %llx\n",
1793 (unsigned long long)rxs
->mactime
,
1794 (unsigned long long)tsf
);
1799 * Local TSF might have moved higher than our beacon timers,
1800 * in that case we have to update them to continue sending
1801 * beacons. This also takes care of synchronizing beacon sending
1802 * times with other stations.
1804 if (hw_tu
>= sc
->nexttbtt
)
1805 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1810 ath5k_tasklet_rx(unsigned long data
)
1812 struct ieee80211_rx_status
*rxs
;
1813 struct ath5k_rx_status rs
= {};
1814 struct sk_buff
*skb
, *next_skb
;
1815 dma_addr_t next_skb_addr
;
1816 struct ath5k_softc
*sc
= (void *)data
;
1817 struct ath5k_hw
*ah
= sc
->ah
;
1818 struct ath_common
*common
= ath5k_hw_common(ah
);
1819 struct ath5k_buf
*bf
;
1820 struct ath5k_desc
*ds
;
1826 spin_lock(&sc
->rxbuflock
);
1827 if (list_empty(&sc
->rxbuf
)) {
1828 ATH5K_WARN(sc
, "empty rx buf pool\n");
1834 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1835 BUG_ON(bf
->skb
== NULL
);
1839 /* bail if HW is still using self-linked descriptor */
1840 if (ath5k_hw_get_rxdp(sc
->ah
) == bf
->daddr
)
1843 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1844 if (unlikely(ret
== -EINPROGRESS
))
1846 else if (unlikely(ret
)) {
1847 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1848 spin_unlock(&sc
->rxbuflock
);
1852 if (unlikely(rs
.rs_more
)) {
1853 ATH5K_WARN(sc
, "unsupported jumbo\n");
1857 if (unlikely(rs
.rs_status
)) {
1858 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1860 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1862 * Decrypt error. If the error occurred
1863 * because there was no hardware key, then
1864 * let the frame through so the upper layers
1865 * can process it. This is necessary for 5210
1866 * parts which have no way to setup a ``clear''
1869 * XXX do key cache faulting
1871 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1872 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1875 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1876 rx_flag
|= RX_FLAG_MMIC_ERROR
;
1880 /* let crypto-error packets fall through in MNTR */
1882 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1883 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
1887 next_skb
= ath5k_rx_skb_alloc(sc
, &next_skb_addr
);
1890 * If we can't replace bf->skb with a new skb under memory
1891 * pressure, just skip this packet
1896 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, common
->rx_bufsize
,
1897 PCI_DMA_FROMDEVICE
);
1898 skb_put(skb
, rs
.rs_datalen
);
1900 /* The MAC header is padded to have 32-bit boundary if the
1901 * packet payload is non-zero. The general calculation for
1902 * padsize would take into account odd header lengths:
1903 * padsize = (4 - hdrlen % 4) % 4; However, since only
1904 * even-length headers are used, padding can only be 0 or 2
1905 * bytes and we can optimize this a bit. In addition, we must
1906 * not try to remove padding from short control frames that do
1907 * not have payload. */
1908 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1909 padsize
= ath5k_pad_size(hdrlen
);
1911 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
1912 skb_pull(skb
, padsize
);
1914 rxs
= IEEE80211_SKB_RXCB(skb
);
1917 * always extend the mac timestamp, since this information is
1918 * also needed for proper IBSS merging.
1920 * XXX: it might be too late to do it here, since rs_tstamp is
1921 * 15bit only. that means TSF extension has to be done within
1922 * 32768usec (about 32ms). it might be necessary to move this to
1923 * the interrupt handler, like it is done in madwifi.
1925 * Unfortunately we don't know when the hardware takes the rx
1926 * timestamp (beginning of phy frame, data frame, end of rx?).
1927 * The only thing we know is that it is hardware specific...
1928 * On AR5213 it seems the rx timestamp is at the end of the
1929 * frame, but i'm not sure.
1931 * NOTE: mac80211 defines mactime at the beginning of the first
1932 * data symbol. Since we don't have any time references it's
1933 * impossible to comply to that. This affects IBSS merge only
1934 * right now, so it's not too bad...
1936 rxs
->mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1937 rxs
->flag
= rx_flag
| RX_FLAG_TSFT
;
1939 rxs
->freq
= sc
->curchan
->center_freq
;
1940 rxs
->band
= sc
->curband
->band
;
1942 rxs
->noise
= sc
->ah
->ah_noise_floor
;
1943 rxs
->signal
= rxs
->noise
+ rs
.rs_rssi
;
1945 rxs
->antenna
= rs
.rs_antenna
;
1946 rxs
->rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1947 rxs
->flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1949 if (rxs
->rate_idx
>= 0 && rs
.rs_rate
==
1950 sc
->curband
->bitrates
[rxs
->rate_idx
].hw_value_short
)
1951 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1953 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1955 /* check beacons in IBSS mode */
1956 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1957 ath5k_check_ibss_tsf(sc
, skb
, rxs
);
1959 ieee80211_rx(sc
->hw
, skb
);
1962 bf
->skbaddr
= next_skb_addr
;
1964 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1965 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1967 spin_unlock(&sc
->rxbuflock
);
1978 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1980 struct ath5k_tx_status ts
= {};
1981 struct ath5k_buf
*bf
, *bf0
;
1982 struct ath5k_desc
*ds
;
1983 struct sk_buff
*skb
;
1984 struct ieee80211_tx_info
*info
;
1987 spin_lock(&txq
->lock
);
1988 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1991 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1992 if (unlikely(ret
== -EINPROGRESS
))
1994 else if (unlikely(ret
)) {
1995 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
2001 info
= IEEE80211_SKB_CB(skb
);
2004 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
2007 ieee80211_tx_info_clear_status(info
);
2008 for (i
= 0; i
< 4; i
++) {
2009 struct ieee80211_tx_rate
*r
=
2010 &info
->status
.rates
[i
];
2012 if (ts
.ts_rate
[i
]) {
2013 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
.ts_rate
[i
]);
2014 r
->count
= ts
.ts_retry
[i
];
2021 /* count the successful attempt as well */
2022 info
->status
.rates
[ts
.ts_final_idx
].count
++;
2024 if (unlikely(ts
.ts_status
)) {
2025 sc
->ll_stats
.dot11ACKFailureCount
++;
2026 if (ts
.ts_status
& AR5K_TXERR_FILT
)
2027 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2029 info
->flags
|= IEEE80211_TX_STAT_ACK
;
2030 info
->status
.ack_signal
= ts
.ts_rssi
;
2033 ieee80211_tx_status(sc
->hw
, skb
);
2035 spin_lock(&sc
->txbuflock
);
2036 list_move_tail(&bf
->list
, &sc
->txbuf
);
2038 spin_unlock(&sc
->txbuflock
);
2040 if (likely(list_empty(&txq
->q
)))
2042 spin_unlock(&txq
->lock
);
2043 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
2044 ieee80211_wake_queues(sc
->hw
);
2048 ath5k_tasklet_tx(unsigned long data
)
2051 struct ath5k_softc
*sc
= (void *)data
;
2053 for (i
=0; i
< AR5K_NUM_TX_QUEUES
; i
++)
2054 if (sc
->txqs
[i
].setup
&& (sc
->ah
->ah_txq_isr
& BIT(i
)))
2055 ath5k_tx_processq(sc
, &sc
->txqs
[i
]);
2064 * Setup the beacon frame for transmit.
2067 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
2069 struct sk_buff
*skb
= bf
->skb
;
2070 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2071 struct ath5k_hw
*ah
= sc
->ah
;
2072 struct ath5k_desc
*ds
;
2077 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
2079 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
2080 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
2081 (unsigned long long)bf
->skbaddr
);
2082 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
2083 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
2088 antenna
= ah
->ah_tx_ant
;
2090 flags
= AR5K_TXDESC_NOACK
;
2091 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
2092 ds
->ds_link
= bf
->daddr
; /* self-linked */
2093 flags
|= AR5K_TXDESC_VEOL
;
2098 * If we use multiple antennas on AP and use
2099 * the Sectored AP scenario, switch antenna every
2100 * 4 beacons to make sure everybody hears our AP.
2101 * When a client tries to associate, hw will keep
2102 * track of the tx antenna to be used for this client
2103 * automaticaly, based on ACKed packets.
2105 * Note: AP still listens and transmits RTS on the
2106 * default antenna which is supposed to be an omni.
2108 * Note2: On sectored scenarios it's possible to have
2109 * multiple antennas (1omni -the default- and 14 sectors)
2110 * so if we choose to actually support this mode we need
2111 * to allow user to set how many antennas we have and tweak
2112 * the code below to send beacons on all of them.
2114 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
2115 antenna
= sc
->bsent
& 4 ? 2 : 1;
2118 /* FIXME: If we are in g mode and rate is a CCK rate
2119 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2120 * from tx power (value is in dB units already) */
2121 ds
->ds_data
= bf
->skbaddr
;
2122 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
2123 ieee80211_get_hdrlen_from_skb(skb
),
2124 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
2125 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
2126 1, AR5K_TXKEYIX_INVALID
,
2127 antenna
, flags
, 0, 0);
2133 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
2138 * Transmit a beacon frame at SWBA. Dynamic updates to the
2139 * frame contents are done as needed and the slot time is
2140 * also adjusted based on current state.
2142 * This is called from software irq context (beacontq or restq
2143 * tasklets) or user context from ath5k_beacon_config.
2146 ath5k_beacon_send(struct ath5k_softc
*sc
)
2148 struct ath5k_buf
*bf
= sc
->bbuf
;
2149 struct ath5k_hw
*ah
= sc
->ah
;
2150 struct sk_buff
*skb
;
2152 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
2154 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
2155 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
2156 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
2160 * Check if the previous beacon has gone out. If
2161 * not don't don't try to post another, skip this
2162 * period and wait for the next. Missed beacons
2163 * indicate a problem and should not occur. If we
2164 * miss too many consecutive beacons reset the device.
2166 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
2168 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2169 "missed %u consecutive beacons\n", sc
->bmisscount
);
2170 if (sc
->bmisscount
> 10) { /* NB: 10 is a guess */
2171 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2172 "stuck beacon time (%u missed)\n",
2174 tasklet_schedule(&sc
->restq
);
2178 if (unlikely(sc
->bmisscount
!= 0)) {
2179 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2180 "resume beacon xmit after %u misses\n",
2186 * Stop any current dma and put the new frame on the queue.
2187 * This should never fail since we check above that no frames
2188 * are still pending on the queue.
2190 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2191 ATH5K_WARN(sc
, "beacon queue %u didn't start/stop ?\n", sc
->bhalq
);
2192 /* NB: hw still stops DMA, so proceed */
2195 /* refresh the beacon for AP mode */
2196 if (sc
->opmode
== NL80211_IFTYPE_AP
)
2197 ath5k_beacon_update(sc
->hw
, sc
->vif
);
2199 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
2200 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
2201 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2202 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2204 skb
= ieee80211_get_buffered_bc(sc
->hw
, sc
->vif
);
2206 ath5k_tx_queue(sc
->hw
, skb
, sc
->cabq
);
2207 skb
= ieee80211_get_buffered_bc(sc
->hw
, sc
->vif
);
2215 * ath5k_beacon_update_timers - update beacon timers
2217 * @sc: struct ath5k_softc pointer we are operating on
2218 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2219 * beacon timer update based on the current HW TSF.
2221 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2222 * of a received beacon or the current local hardware TSF and write it to the
2223 * beacon timer registers.
2225 * This is called in a variety of situations, e.g. when a beacon is received,
2226 * when a TSF update has been detected, but also when an new IBSS is created or
2227 * when we otherwise know we have to update the timers, but we keep it in this
2228 * function to have it all together in one place.
2231 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2233 struct ath5k_hw
*ah
= sc
->ah
;
2234 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2237 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2238 if (WARN_ON(!intval
))
2241 /* beacon TSF converted to TU */
2242 bc_tu
= TSF_TO_TU(bc_tsf
);
2244 /* current TSF converted to TU */
2245 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2246 hw_tu
= TSF_TO_TU(hw_tsf
);
2249 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2252 * no beacons received, called internally.
2253 * just need to refresh timers based on HW TSF.
2255 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2256 } else if (bc_tsf
== 0) {
2258 * no beacon received, probably called by ath5k_reset_tsf().
2259 * reset TSF to start with 0.
2262 intval
|= AR5K_BEACON_RESET_TSF
;
2263 } else if (bc_tsf
> hw_tsf
) {
2265 * beacon received, SW merge happend but HW TSF not yet updated.
2266 * not possible to reconfigure timers yet, but next time we
2267 * receive a beacon with the same BSSID, the hardware will
2268 * automatically update the TSF and then we need to reconfigure
2271 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2272 "need to wait for HW TSF sync\n");
2276 * most important case for beacon synchronization between STA.
2278 * beacon received and HW TSF has been already updated by HW.
2279 * update next TBTT based on the TSF of the beacon, but make
2280 * sure it is ahead of our local TSF timer.
2282 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2286 sc
->nexttbtt
= nexttbtt
;
2288 intval
|= AR5K_BEACON_ENA
;
2289 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2292 * debugging output last in order to preserve the time critical aspect
2296 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2297 "reconfigured timers based on HW TSF\n");
2298 else if (bc_tsf
== 0)
2299 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2300 "reset HW TSF and timers\n");
2302 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2303 "updated timers based on beacon TSF\n");
2305 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2306 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2307 (unsigned long long) bc_tsf
,
2308 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2309 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2310 intval
& AR5K_BEACON_PERIOD
,
2311 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2312 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2317 * ath5k_beacon_config - Configure the beacon queues and interrupts
2319 * @sc: struct ath5k_softc pointer we are operating on
2321 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2322 * interrupts to detect TSF updates only.
2325 ath5k_beacon_config(struct ath5k_softc
*sc
)
2327 struct ath5k_hw
*ah
= sc
->ah
;
2328 unsigned long flags
;
2330 spin_lock_irqsave(&sc
->block
, flags
);
2332 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2334 if (sc
->enable_beacon
) {
2336 * In IBSS mode we use a self-linked tx descriptor and let the
2337 * hardware send the beacons automatically. We have to load it
2339 * We use the SWBA interrupt only to keep track of the beacon
2340 * timers in order to detect automatic TSF updates.
2342 ath5k_beaconq_config(sc
);
2344 sc
->imask
|= AR5K_INT_SWBA
;
2346 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2347 if (ath5k_hw_hasveol(ah
))
2348 ath5k_beacon_send(sc
);
2350 ath5k_beacon_update_timers(sc
, -1);
2352 ath5k_hw_stop_tx_dma(sc
->ah
, sc
->bhalq
);
2355 ath5k_hw_set_imr(ah
, sc
->imask
);
2357 spin_unlock_irqrestore(&sc
->block
, flags
);
2360 static void ath5k_tasklet_beacon(unsigned long data
)
2362 struct ath5k_softc
*sc
= (struct ath5k_softc
*) data
;
2365 * Software beacon alert--time to send a beacon.
2367 * In IBSS mode we use this interrupt just to
2368 * keep track of the next TBTT (target beacon
2369 * transmission time) in order to detect wether
2370 * automatic TSF updates happened.
2372 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2373 /* XXX: only if VEOL suppported */
2374 u64 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
2375 sc
->nexttbtt
+= sc
->bintval
;
2376 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2377 "SWBA nexttbtt: %x hw_tu: %x "
2381 (unsigned long long) tsf
);
2383 spin_lock(&sc
->block
);
2384 ath5k_beacon_send(sc
);
2385 spin_unlock(&sc
->block
);
2390 /********************\
2391 * Interrupt handling *
2392 \********************/
2395 ath5k_init(struct ath5k_softc
*sc
)
2397 struct ath5k_hw
*ah
= sc
->ah
;
2400 mutex_lock(&sc
->lock
);
2402 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2405 * Stop anything previously setup. This is safe
2406 * no matter this is the first time through or not.
2408 ath5k_stop_locked(sc
);
2410 /* Set PHY calibration interval */
2411 ah
->ah_cal_intval
= ath5k_calinterval
;
2414 * The basic interface to setting the hardware in a good
2415 * state is ``reset''. On return the hardware is known to
2416 * be powered up and with interrupts disabled. This must
2417 * be followed by initialization of the appropriate bits
2418 * and then setup of the interrupt mask.
2420 sc
->curchan
= sc
->hw
->conf
.channel
;
2421 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2422 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2423 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2424 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
| AR5K_INT_SWI
;
2425 ret
= ath5k_reset(sc
, NULL
);
2429 ath5k_rfkill_hw_start(ah
);
2432 * Reset the key cache since some parts do not reset the
2433 * contents on initial power up or resume from suspend.
2435 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
2436 ath5k_hw_reset_key(ah
, i
);
2438 /* Set ack to be sent at low bit-rates */
2439 ath5k_hw_set_ack_bitrate_high(ah
, false);
2443 mutex_unlock(&sc
->lock
);
2448 ath5k_stop_locked(struct ath5k_softc
*sc
)
2450 struct ath5k_hw
*ah
= sc
->ah
;
2452 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2453 test_bit(ATH_STAT_INVALID
, sc
->status
));
2456 * Shutdown the hardware and driver:
2457 * stop output from above
2458 * disable interrupts
2460 * turn off the radio
2461 * clear transmit machinery
2462 * clear receive machinery
2463 * drain and release tx queues
2464 * reclaim beacon resources
2465 * power down hardware
2467 * Note that some of this work is not possible if the
2468 * hardware is gone (invalid).
2470 ieee80211_stop_queues(sc
->hw
);
2472 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2474 ath5k_hw_set_imr(ah
, 0);
2475 synchronize_irq(sc
->pdev
->irq
);
2477 ath5k_txq_cleanup(sc
);
2478 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2480 ath5k_hw_phy_disable(ah
);
2488 * Stop the device, grabbing the top-level lock to protect
2489 * against concurrent entry through ath5k_init (which can happen
2490 * if another thread does a system call and the thread doing the
2491 * stop is preempted).
2494 ath5k_stop_hw(struct ath5k_softc
*sc
)
2498 mutex_lock(&sc
->lock
);
2499 ret
= ath5k_stop_locked(sc
);
2500 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2502 * Don't set the card in full sleep mode!
2504 * a) When the device is in this state it must be carefully
2505 * woken up or references to registers in the PCI clock
2506 * domain may freeze the bus (and system). This varies
2507 * by chip and is mostly an issue with newer parts
2508 * (madwifi sources mentioned srev >= 0x78) that go to
2509 * sleep more quickly.
2511 * b) On older chips full sleep results a weird behaviour
2512 * during wakeup. I tested various cards with srev < 0x78
2513 * and they don't wake up after module reload, a second
2514 * module reload is needed to bring the card up again.
2516 * Until we figure out what's going on don't enable
2517 * full chip reset on any chip (this is what Legacy HAL
2518 * and Sam's HAL do anyway). Instead Perform a full reset
2519 * on the device (same as initial state after attach) and
2520 * leave it idle (keep MAC/BB on warm reset) */
2521 ret
= ath5k_hw_on_hold(sc
->ah
);
2523 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2524 "putting device to sleep\n");
2526 ath5k_txbuf_free(sc
, sc
->bbuf
);
2529 mutex_unlock(&sc
->lock
);
2531 tasklet_kill(&sc
->rxtq
);
2532 tasklet_kill(&sc
->txtq
);
2533 tasklet_kill(&sc
->restq
);
2534 tasklet_kill(&sc
->calib
);
2535 tasklet_kill(&sc
->beacontq
);
2537 ath5k_rfkill_hw_stop(sc
->ah
);
2543 ath5k_intr(int irq
, void *dev_id
)
2545 struct ath5k_softc
*sc
= dev_id
;
2546 struct ath5k_hw
*ah
= sc
->ah
;
2547 enum ath5k_int status
;
2548 unsigned int counter
= 1000;
2550 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2551 !ath5k_hw_is_intr_pending(ah
)))
2555 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2556 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2558 if (unlikely(status
& AR5K_INT_FATAL
)) {
2560 * Fatal errors are unrecoverable.
2561 * Typically these are caused by DMA errors.
2563 tasklet_schedule(&sc
->restq
);
2564 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2565 tasklet_schedule(&sc
->restq
);
2567 if (status
& AR5K_INT_SWBA
) {
2568 tasklet_hi_schedule(&sc
->beacontq
);
2570 if (status
& AR5K_INT_RXEOL
) {
2572 * NB: the hardware should re-read the link when
2573 * RXE bit is written, but it doesn't work at
2574 * least on older hardware revs.
2578 if (status
& AR5K_INT_TXURN
) {
2579 /* bump tx trigger level */
2580 ath5k_hw_update_tx_triglevel(ah
, true);
2582 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2583 tasklet_schedule(&sc
->rxtq
);
2584 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2585 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2586 tasklet_schedule(&sc
->txtq
);
2587 if (status
& AR5K_INT_BMISS
) {
2590 if (status
& AR5K_INT_SWI
) {
2591 tasklet_schedule(&sc
->calib
);
2593 if (status
& AR5K_INT_MIB
) {
2595 * These stats are also used for ANI i think
2596 * so how about updating them more often ?
2598 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2600 if (status
& AR5K_INT_GPIO
)
2601 tasklet_schedule(&sc
->rf_kill
.toggleq
);
2604 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2606 if (unlikely(!counter
))
2607 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2609 ath5k_hw_calibration_poll(ah
);
2615 ath5k_tasklet_reset(unsigned long data
)
2617 struct ath5k_softc
*sc
= (void *)data
;
2619 ath5k_reset_wake(sc
);
2623 * Periodically recalibrate the PHY to account
2624 * for temperature/environment changes.
2627 ath5k_tasklet_calibrate(unsigned long data
)
2629 struct ath5k_softc
*sc
= (void *)data
;
2630 struct ath5k_hw
*ah
= sc
->ah
;
2632 /* Only full calibration for now */
2633 if (ah
->ah_swi_mask
!= AR5K_SWI_FULL_CALIBRATION
)
2636 /* Stop queues so that calibration
2637 * doesn't interfere with tx */
2638 ieee80211_stop_queues(sc
->hw
);
2640 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2641 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2642 sc
->curchan
->hw_value
);
2644 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2646 * Rfgain is out of bounds, reset the chip
2647 * to load new gain values.
2649 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2650 ath5k_reset_wake(sc
);
2652 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2653 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2654 ieee80211_frequency_to_channel(
2655 sc
->curchan
->center_freq
));
2657 ah
->ah_swi_mask
= 0;
2660 ieee80211_wake_queues(sc
->hw
);
2665 /********************\
2666 * Mac80211 functions *
2667 \********************/
2670 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2672 struct ath5k_softc
*sc
= hw
->priv
;
2674 return ath5k_tx_queue(hw
, skb
, sc
->txq
);
2677 static int ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2678 struct ath5k_txq
*txq
)
2680 struct ath5k_softc
*sc
= hw
->priv
;
2681 struct ath5k_buf
*bf
;
2682 unsigned long flags
;
2686 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2688 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2689 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2692 * the hardware expects the header padded to 4 byte boundaries
2693 * if this is not the case we add the padding after the header
2695 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2696 padsize
= ath5k_pad_size(hdrlen
);
2699 if (skb_headroom(skb
) < padsize
) {
2700 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2701 " headroom to pad %d\n", hdrlen
, padsize
);
2704 skb_push(skb
, padsize
);
2705 memmove(skb
->data
, skb
->data
+padsize
, hdrlen
);
2708 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2709 if (list_empty(&sc
->txbuf
)) {
2710 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2711 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2712 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2715 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2716 list_del(&bf
->list
);
2718 if (list_empty(&sc
->txbuf
))
2719 ieee80211_stop_queues(hw
);
2720 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2724 if (ath5k_txbuf_setup(sc
, bf
, txq
)) {
2726 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2727 list_add_tail(&bf
->list
, &sc
->txbuf
);
2729 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2732 return NETDEV_TX_OK
;
2735 dev_kfree_skb_any(skb
);
2736 return NETDEV_TX_OK
;
2740 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2741 * and change to the given channel.
2744 ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
2746 struct ath5k_hw
*ah
= sc
->ah
;
2749 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2752 ath5k_hw_set_imr(ah
, 0);
2753 ath5k_txq_cleanup(sc
);
2757 sc
->curband
= &sc
->sbands
[chan
->band
];
2759 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, chan
!= NULL
);
2761 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2765 ret
= ath5k_rx_start(sc
);
2767 ATH5K_ERR(sc
, "can't start recv logic\n");
2772 * Change channels and update the h/w rate map if we're switching;
2773 * e.g. 11a to 11b/g.
2775 * We may be doing a reset in response to an ioctl that changes the
2776 * channel so update any state that might change as a result.
2780 /* ath5k_chan_change(sc, c); */
2782 ath5k_beacon_config(sc
);
2783 /* intrs are enabled by ath5k_beacon_config */
2791 ath5k_reset_wake(struct ath5k_softc
*sc
)
2795 ret
= ath5k_reset(sc
, sc
->curchan
);
2797 ieee80211_wake_queues(sc
->hw
);
2802 static int ath5k_start(struct ieee80211_hw
*hw
)
2804 return ath5k_init(hw
->priv
);
2807 static void ath5k_stop(struct ieee80211_hw
*hw
)
2809 ath5k_stop_hw(hw
->priv
);
2812 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2813 struct ieee80211_vif
*vif
)
2815 struct ath5k_softc
*sc
= hw
->priv
;
2818 mutex_lock(&sc
->lock
);
2826 switch (vif
->type
) {
2827 case NL80211_IFTYPE_AP
:
2828 case NL80211_IFTYPE_STATION
:
2829 case NL80211_IFTYPE_ADHOC
:
2830 case NL80211_IFTYPE_MESH_POINT
:
2831 case NL80211_IFTYPE_MONITOR
:
2832 sc
->opmode
= vif
->type
;
2839 ath5k_hw_set_lladdr(sc
->ah
, vif
->addr
);
2840 ath5k_mode_setup(sc
);
2844 mutex_unlock(&sc
->lock
);
2849 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2850 struct ieee80211_vif
*vif
)
2852 struct ath5k_softc
*sc
= hw
->priv
;
2853 u8 mac
[ETH_ALEN
] = {};
2855 mutex_lock(&sc
->lock
);
2859 ath5k_hw_set_lladdr(sc
->ah
, mac
);
2862 mutex_unlock(&sc
->lock
);
2866 * TODO: Phy disable/diversity etc
2869 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
2871 struct ath5k_softc
*sc
= hw
->priv
;
2872 struct ath5k_hw
*ah
= sc
->ah
;
2873 struct ieee80211_conf
*conf
= &hw
->conf
;
2876 mutex_lock(&sc
->lock
);
2878 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2879 ret
= ath5k_chan_set(sc
, conf
->channel
);
2884 if ((changed
& IEEE80211_CONF_CHANGE_POWER
) &&
2885 (sc
->power_level
!= conf
->power_level
)) {
2886 sc
->power_level
= conf
->power_level
;
2889 ath5k_hw_set_txpower_limit(ah
, (conf
->power_level
* 2));
2893 * 1) Move this on config_interface and handle each case
2894 * separately eg. when we have only one STA vif, use
2895 * AR5K_ANTMODE_SINGLE_AP
2897 * 2) Allow the user to change antenna mode eg. when only
2898 * one antenna is present
2900 * 3) Allow the user to set default/tx antenna when possible
2902 * 4) Default mode should handle 90% of the cases, together
2903 * with fixed a/b and single AP modes we should be able to
2904 * handle 99%. Sectored modes are extreme cases and i still
2905 * haven't found a usage for them. If we decide to support them,
2906 * then we must allow the user to set how many tx antennas we
2909 ath5k_hw_set_antenna_mode(ah
, AR5K_ANTMODE_DEFAULT
);
2912 mutex_unlock(&sc
->lock
);
2916 static u64
ath5k_prepare_multicast(struct ieee80211_hw
*hw
,
2917 int mc_count
, struct dev_addr_list
*mclist
)
2926 for (i
= 0; i
< mc_count
; i
++) {
2929 /* calculate XOR of eight 6-bit values */
2930 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2931 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2932 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2933 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2935 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2936 /* XXX: we might be able to just do this instead,
2937 * but not sure, needs testing, if we do use this we'd
2938 * neet to inform below to not reset the mcast */
2939 /* ath5k_hw_set_mcast_filterindex(ah,
2940 * mclist->dmi_addr[5]); */
2941 mclist
= mclist
->next
;
2944 return ((u64
)(mfilt
[1]) << 32) | mfilt
[0];
2947 #define SUPPORTED_FIF_FLAGS \
2948 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2949 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2950 FIF_BCN_PRBRESP_PROMISC
2952 * o always accept unicast, broadcast, and multicast traffic
2953 * o multicast traffic for all BSSIDs will be enabled if mac80211
2955 * o maintain current state of phy ofdm or phy cck error reception.
2956 * If the hardware detects any of these type of errors then
2957 * ath5k_hw_get_rx_filter() will pass to us the respective
2958 * hardware filters to be able to receive these type of frames.
2959 * o probe request frames are accepted only when operating in
2960 * hostap, adhoc, or monitor modes
2961 * o enable promiscuous mode according to the interface state
2963 * - when operating in adhoc mode so the 802.11 layer creates
2964 * node table entries for peers,
2965 * - when operating in station mode for collecting rssi data when
2966 * the station is otherwise quiet, or
2969 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2970 unsigned int changed_flags
,
2971 unsigned int *new_flags
,
2974 struct ath5k_softc
*sc
= hw
->priv
;
2975 struct ath5k_hw
*ah
= sc
->ah
;
2976 u32 mfilt
[2], rfilt
;
2978 mutex_lock(&sc
->lock
);
2980 mfilt
[0] = multicast
;
2981 mfilt
[1] = multicast
>> 32;
2983 /* Only deal with supported flags */
2984 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2985 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2987 /* If HW detects any phy or radar errors, leave those filters on.
2988 * Also, always enable Unicast, Broadcasts and Multicast
2989 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2990 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2991 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2992 AR5K_RX_FILTER_MCAST
);
2994 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2995 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2996 rfilt
|= AR5K_RX_FILTER_PROM
;
2997 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2999 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
3003 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3004 if (*new_flags
& FIF_ALLMULTI
) {
3009 /* This is the best we can do */
3010 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
3011 rfilt
|= AR5K_RX_FILTER_PHYERR
;
3013 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3014 * and probes for any BSSID, this needs testing */
3015 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
3016 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
3018 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3019 * set we should only pass on control frames for this
3020 * station. This needs testing. I believe right now this
3021 * enables *all* control frames, which is OK.. but
3022 * but we should see if we can improve on granularity */
3023 if (*new_flags
& FIF_CONTROL
)
3024 rfilt
|= AR5K_RX_FILTER_CONTROL
;
3026 /* Additional settings per mode -- this is per ath5k */
3028 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3030 switch (sc
->opmode
) {
3031 case NL80211_IFTYPE_MESH_POINT
:
3032 case NL80211_IFTYPE_MONITOR
:
3033 rfilt
|= AR5K_RX_FILTER_CONTROL
|
3034 AR5K_RX_FILTER_BEACON
|
3035 AR5K_RX_FILTER_PROBEREQ
|
3036 AR5K_RX_FILTER_PROM
;
3038 case NL80211_IFTYPE_AP
:
3039 case NL80211_IFTYPE_ADHOC
:
3040 rfilt
|= AR5K_RX_FILTER_PROBEREQ
|
3041 AR5K_RX_FILTER_BEACON
;
3043 case NL80211_IFTYPE_STATION
:
3045 rfilt
|= AR5K_RX_FILTER_BEACON
;
3051 ath5k_hw_set_rx_filter(ah
, rfilt
);
3053 /* Set multicast bits */
3054 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
3055 /* Set the cached hw filter flags, this will alter actually
3057 sc
->filter_flags
= rfilt
;
3059 mutex_unlock(&sc
->lock
);
3063 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3064 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3065 struct ieee80211_key_conf
*key
)
3067 struct ath5k_softc
*sc
= hw
->priv
;
3068 struct ath5k_hw
*ah
= sc
->ah
;
3069 struct ath_common
*common
= ath5k_hw_common(ah
);
3072 if (modparam_nohwcrypt
)
3075 if (sc
->opmode
== NL80211_IFTYPE_AP
)
3083 if (sc
->ah
->ah_aes_support
)
3092 mutex_lock(&sc
->lock
);
3096 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
,
3097 sta
? sta
->addr
: NULL
);
3099 ATH5K_ERR(sc
, "can't set the key\n");
3102 __set_bit(key
->keyidx
, common
->keymap
);
3103 key
->hw_key_idx
= key
->keyidx
;
3104 key
->flags
|= (IEEE80211_KEY_FLAG_GENERATE_IV
|
3105 IEEE80211_KEY_FLAG_GENERATE_MMIC
);
3108 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
3109 __clear_bit(key
->keyidx
, common
->keymap
);
3118 mutex_unlock(&sc
->lock
);
3123 ath5k_get_stats(struct ieee80211_hw
*hw
,
3124 struct ieee80211_low_level_stats
*stats
)
3126 struct ath5k_softc
*sc
= hw
->priv
;
3127 struct ath5k_hw
*ah
= sc
->ah
;
3130 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3132 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3138 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3140 struct ath5k_softc
*sc
= hw
->priv
;
3142 return ath5k_hw_get_tsf64(sc
->ah
);
3146 ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3148 struct ath5k_softc
*sc
= hw
->priv
;
3150 ath5k_hw_set_tsf64(sc
->ah
, tsf
);
3154 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3156 struct ath5k_softc
*sc
= hw
->priv
;
3159 * in IBSS mode we need to update the beacon timers too.
3160 * this will also reset the TSF if we call it with 0
3162 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3163 ath5k_beacon_update_timers(sc
, 0);
3165 ath5k_hw_reset_tsf(sc
->ah
);
3169 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3170 * this is called only once at config_bss time, for AP we do it every
3171 * SWBA interrupt so that the TIM will reflect buffered frames.
3173 * Called with the beacon lock.
3176 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
3179 struct ath5k_softc
*sc
= hw
->priv
;
3180 struct sk_buff
*skb
;
3182 if (WARN_ON(!vif
)) {
3187 skb
= ieee80211_beacon_get(hw
, vif
);
3194 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3196 ath5k_txbuf_free(sc
, sc
->bbuf
);
3197 sc
->bbuf
->skb
= skb
;
3198 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3200 sc
->bbuf
->skb
= NULL
;
3206 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3208 struct ath5k_softc
*sc
= hw
->priv
;
3209 struct ath5k_hw
*ah
= sc
->ah
;
3211 rfilt
= ath5k_hw_get_rx_filter(ah
);
3213 rfilt
|= AR5K_RX_FILTER_BEACON
;
3215 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3216 ath5k_hw_set_rx_filter(ah
, rfilt
);
3217 sc
->filter_flags
= rfilt
;
3220 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
3221 struct ieee80211_vif
*vif
,
3222 struct ieee80211_bss_conf
*bss_conf
,
3225 struct ath5k_softc
*sc
= hw
->priv
;
3226 struct ath5k_hw
*ah
= sc
->ah
;
3227 struct ath_common
*common
= ath5k_hw_common(ah
);
3228 unsigned long flags
;
3230 mutex_lock(&sc
->lock
);
3231 if (WARN_ON(sc
->vif
!= vif
))
3234 if (changes
& BSS_CHANGED_BSSID
) {
3235 /* Cache for later use during resets */
3236 memcpy(common
->curbssid
, bss_conf
->bssid
, ETH_ALEN
);
3238 ath5k_hw_set_associd(ah
);
3242 if (changes
& BSS_CHANGED_BEACON_INT
)
3243 sc
->bintval
= bss_conf
->beacon_int
;
3245 if (changes
& BSS_CHANGED_ASSOC
) {
3246 sc
->assoc
= bss_conf
->assoc
;
3247 if (sc
->opmode
== NL80211_IFTYPE_STATION
)
3248 set_beacon_filter(hw
, sc
->assoc
);
3249 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3250 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3251 if (bss_conf
->assoc
) {
3252 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
,
3253 "Bss Info ASSOC %d, bssid: %pM\n",
3254 bss_conf
->aid
, common
->curbssid
);
3255 common
->curaid
= bss_conf
->aid
;
3256 ath5k_hw_set_associd(ah
);
3257 /* Once ANI is available you would start it here */
3261 if (changes
& BSS_CHANGED_BEACON
) {
3262 spin_lock_irqsave(&sc
->block
, flags
);
3263 ath5k_beacon_update(hw
, vif
);
3264 spin_unlock_irqrestore(&sc
->block
, flags
);
3267 if (changes
& BSS_CHANGED_BEACON_ENABLED
)
3268 sc
->enable_beacon
= bss_conf
->enable_beacon
;
3270 if (changes
& (BSS_CHANGED_BEACON
| BSS_CHANGED_BEACON_ENABLED
|
3271 BSS_CHANGED_BEACON_INT
))
3272 ath5k_beacon_config(sc
);
3275 mutex_unlock(&sc
->lock
);
3278 static void ath5k_sw_scan_start(struct ieee80211_hw
*hw
)
3280 struct ath5k_softc
*sc
= hw
->priv
;
3282 ath5k_hw_set_ledstate(sc
->ah
, AR5K_LED_SCAN
);
3285 static void ath5k_sw_scan_complete(struct ieee80211_hw
*hw
)
3287 struct ath5k_softc
*sc
= hw
->priv
;
3288 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3289 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3293 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3295 * @hw: struct ieee80211_hw pointer
3296 * @coverage_class: IEEE 802.11 coverage class number
3298 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3299 * coverage class. The values are persistent, they are restored after device
3302 static void ath5k_set_coverage_class(struct ieee80211_hw
*hw
, u8 coverage_class
)
3304 struct ath5k_softc
*sc
= hw
->priv
;
3306 mutex_lock(&sc
->lock
);
3307 ath5k_hw_set_coverage_class(sc
->ah
, coverage_class
);
3308 mutex_unlock(&sc
->lock
);