2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45 #include <linux/module.h>
46 #include <linux/delay.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/hardirq.h>
51 #include <linux/netdevice.h>
52 #include <linux/cache.h>
53 #include <linux/ethtool.h>
54 #include <linux/uaccess.h>
55 #include <linux/slab.h>
56 #include <linux/etherdevice.h>
57 #include <linux/nl80211.h>
59 #include <net/cfg80211.h>
60 #include <net/ieee80211_radiotap.h>
62 #include <asm/unaligned.h>
64 #include <net/mac80211.h>
72 #define CREATE_TRACE_POINTS
75 bool ath5k_modparam_nohwcrypt
;
76 module_param_named(nohwcrypt
, ath5k_modparam_nohwcrypt
, bool, S_IRUGO
);
77 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
79 static bool modparam_fastchanswitch
;
80 module_param_named(fastchanswitch
, modparam_fastchanswitch
, bool, S_IRUGO
);
81 MODULE_PARM_DESC(fastchanswitch
, "Enable fast channel switching for AR2413/AR5413 radios.");
83 static bool ath5k_modparam_no_hw_rfkill_switch
;
84 module_param_named(no_hw_rfkill_switch
, ath5k_modparam_no_hw_rfkill_switch
,
86 MODULE_PARM_DESC(no_hw_rfkill_switch
, "Ignore the GPIO RFKill switch state");
90 MODULE_AUTHOR("Jiri Slaby");
91 MODULE_AUTHOR("Nick Kossifidis");
92 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
93 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
94 MODULE_LICENSE("Dual BSD/GPL");
96 static int ath5k_init(struct ieee80211_hw
*hw
);
97 static int ath5k_reset(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
,
101 static const struct ath5k_srev_name srev_names
[] = {
102 #ifdef CONFIG_ATH5K_AHB
103 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R2
},
104 { "5312", AR5K_VERSION_MAC
, AR5K_SREV_AR5312_R7
},
105 { "2313", AR5K_VERSION_MAC
, AR5K_SREV_AR2313_R8
},
106 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R6
},
107 { "2315", AR5K_VERSION_MAC
, AR5K_SREV_AR2315_R7
},
108 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R1
},
109 { "2317", AR5K_VERSION_MAC
, AR5K_SREV_AR2317_R2
},
111 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
112 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
113 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
114 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
115 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
116 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
117 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
118 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
119 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
120 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
121 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
122 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
123 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
124 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
125 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
126 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
127 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
128 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
130 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
131 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
132 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
133 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
134 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
135 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
136 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
137 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
138 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
139 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
140 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
141 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
142 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
143 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
144 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
145 #ifdef CONFIG_ATH5K_AHB
146 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
147 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
149 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
152 static const struct ieee80211_rate ath5k_rates
[] = {
154 .hw_value
= ATH5K_RATE_CODE_1M
, },
156 .hw_value
= ATH5K_RATE_CODE_2M
,
157 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
158 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
160 .hw_value
= ATH5K_RATE_CODE_5_5M
,
161 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
162 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
164 .hw_value
= ATH5K_RATE_CODE_11M
,
165 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
166 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
168 .hw_value
= ATH5K_RATE_CODE_6M
,
169 .flags
= IEEE80211_RATE_SUPPORTS_5MHZ
|
170 IEEE80211_RATE_SUPPORTS_10MHZ
},
172 .hw_value
= ATH5K_RATE_CODE_9M
,
173 .flags
= IEEE80211_RATE_SUPPORTS_5MHZ
|
174 IEEE80211_RATE_SUPPORTS_10MHZ
},
176 .hw_value
= ATH5K_RATE_CODE_12M
,
177 .flags
= IEEE80211_RATE_SUPPORTS_5MHZ
|
178 IEEE80211_RATE_SUPPORTS_10MHZ
},
180 .hw_value
= ATH5K_RATE_CODE_18M
,
181 .flags
= IEEE80211_RATE_SUPPORTS_5MHZ
|
182 IEEE80211_RATE_SUPPORTS_10MHZ
},
184 .hw_value
= ATH5K_RATE_CODE_24M
,
185 .flags
= IEEE80211_RATE_SUPPORTS_5MHZ
|
186 IEEE80211_RATE_SUPPORTS_10MHZ
},
188 .hw_value
= ATH5K_RATE_CODE_36M
,
189 .flags
= IEEE80211_RATE_SUPPORTS_5MHZ
|
190 IEEE80211_RATE_SUPPORTS_10MHZ
},
192 .hw_value
= ATH5K_RATE_CODE_48M
,
193 .flags
= IEEE80211_RATE_SUPPORTS_5MHZ
|
194 IEEE80211_RATE_SUPPORTS_10MHZ
},
196 .hw_value
= ATH5K_RATE_CODE_54M
,
197 .flags
= IEEE80211_RATE_SUPPORTS_5MHZ
|
198 IEEE80211_RATE_SUPPORTS_10MHZ
},
201 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
203 u64 tsf
= ath5k_hw_get_tsf64(ah
);
205 if ((tsf
& 0x7fff) < rstamp
)
208 return (tsf
& ~0x7fff) | rstamp
;
212 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
214 const char *name
= "xxxxx";
217 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
218 if (srev_names
[i
].sr_type
!= type
)
221 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
222 name
= srev_names
[i
].sr_name
;
224 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
225 name
= srev_names
[i
].sr_name
;
232 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
234 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
235 return ath5k_hw_reg_read(ah
, reg_offset
);
238 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
240 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
241 ath5k_hw_reg_write(ah
, val
, reg_offset
);
244 static const struct ath_ops ath5k_common_ops
= {
245 .read
= ath5k_ioread32
,
246 .write
= ath5k_iowrite32
,
249 /***********************\
250 * Driver Initialization *
251 \***********************/
253 static void ath5k_reg_notifier(struct wiphy
*wiphy
,
254 struct regulatory_request
*request
)
256 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
257 struct ath5k_hw
*ah
= hw
->priv
;
258 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
260 ath_reg_notifier_apply(wiphy
, request
, regulatory
);
263 /********************\
264 * Channel/mode setup *
265 \********************/
268 * Returns true for the channel numbers used.
270 #ifdef CONFIG_ATH5K_TEST_CHANNELS
271 static bool ath5k_is_standard_channel(short chan
, enum ieee80211_band band
)
277 static bool ath5k_is_standard_channel(short chan
, enum ieee80211_band band
)
279 if (band
== IEEE80211_BAND_2GHZ
&& chan
<= 14)
282 return /* UNII 1,2 */
283 (((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
285 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
287 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165) ||
288 /* 802.11j 5.030-5.080 GHz (20MHz) */
289 (chan
== 8 || chan
== 12 || chan
== 16) ||
290 /* 802.11j 4.9GHz (20MHz) */
291 (chan
== 184 || chan
== 188 || chan
== 192 || chan
== 196));
296 ath5k_setup_channels(struct ath5k_hw
*ah
, struct ieee80211_channel
*channels
,
297 unsigned int mode
, unsigned int max
)
299 unsigned int count
, size
, freq
, ch
;
300 enum ieee80211_band band
;
304 /* 1..220, but 2GHz frequencies are filtered by check_channel */
306 band
= IEEE80211_BAND_5GHZ
;
311 band
= IEEE80211_BAND_2GHZ
;
314 ATH5K_WARN(ah
, "bad mode, not copying channels\n");
319 for (ch
= 1; ch
<= size
&& count
< max
; ch
++) {
320 freq
= ieee80211_channel_to_frequency(ch
, band
);
322 if (freq
== 0) /* mapping failed - not a standard channel */
325 /* Write channel info, needed for ath5k_channel_ok() */
326 channels
[count
].center_freq
= freq
;
327 channels
[count
].band
= band
;
328 channels
[count
].hw_value
= mode
;
330 /* Check if channel is supported by the chipset */
331 if (!ath5k_channel_ok(ah
, &channels
[count
]))
334 if (!ath5k_is_standard_channel(ch
, band
))
344 ath5k_setup_rate_idx(struct ath5k_hw
*ah
, struct ieee80211_supported_band
*b
)
348 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
349 ah
->rate_idx
[b
->band
][i
] = -1;
351 for (i
= 0; i
< b
->n_bitrates
; i
++) {
352 ah
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
353 if (b
->bitrates
[i
].hw_value_short
)
354 ah
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
359 ath5k_setup_bands(struct ieee80211_hw
*hw
)
361 struct ath5k_hw
*ah
= hw
->priv
;
362 struct ieee80211_supported_band
*sband
;
363 int max_c
, count_c
= 0;
366 BUILD_BUG_ON(ARRAY_SIZE(ah
->sbands
) < IEEE80211_NUM_BANDS
);
367 max_c
= ARRAY_SIZE(ah
->channels
);
370 sband
= &ah
->sbands
[IEEE80211_BAND_2GHZ
];
371 sband
->band
= IEEE80211_BAND_2GHZ
;
372 sband
->bitrates
= &ah
->rates
[IEEE80211_BAND_2GHZ
][0];
374 if (test_bit(AR5K_MODE_11G
, ah
->ah_capabilities
.cap_mode
)) {
376 memcpy(sband
->bitrates
, &ath5k_rates
[0],
377 sizeof(struct ieee80211_rate
) * 12);
378 sband
->n_bitrates
= 12;
380 sband
->channels
= ah
->channels
;
381 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
382 AR5K_MODE_11G
, max_c
);
384 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
385 count_c
= sband
->n_channels
;
387 } else if (test_bit(AR5K_MODE_11B
, ah
->ah_capabilities
.cap_mode
)) {
389 memcpy(sband
->bitrates
, &ath5k_rates
[0],
390 sizeof(struct ieee80211_rate
) * 4);
391 sband
->n_bitrates
= 4;
393 /* 5211 only supports B rates and uses 4bit rate codes
394 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
397 if (ah
->ah_version
== AR5K_AR5211
) {
398 for (i
= 0; i
< 4; i
++) {
399 sband
->bitrates
[i
].hw_value
=
400 sband
->bitrates
[i
].hw_value
& 0xF;
401 sband
->bitrates
[i
].hw_value_short
=
402 sband
->bitrates
[i
].hw_value_short
& 0xF;
406 sband
->channels
= ah
->channels
;
407 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
408 AR5K_MODE_11B
, max_c
);
410 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
411 count_c
= sband
->n_channels
;
414 ath5k_setup_rate_idx(ah
, sband
);
416 /* 5GHz band, A mode */
417 if (test_bit(AR5K_MODE_11A
, ah
->ah_capabilities
.cap_mode
)) {
418 sband
= &ah
->sbands
[IEEE80211_BAND_5GHZ
];
419 sband
->band
= IEEE80211_BAND_5GHZ
;
420 sband
->bitrates
= &ah
->rates
[IEEE80211_BAND_5GHZ
][0];
422 memcpy(sband
->bitrates
, &ath5k_rates
[4],
423 sizeof(struct ieee80211_rate
) * 8);
424 sband
->n_bitrates
= 8;
426 sband
->channels
= &ah
->channels
[count_c
];
427 sband
->n_channels
= ath5k_setup_channels(ah
, sband
->channels
,
428 AR5K_MODE_11A
, max_c
);
430 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
432 ath5k_setup_rate_idx(ah
, sband
);
434 ath5k_debug_dump_bands(ah
);
440 * Set/change channels. We always reset the chip.
441 * To accomplish this we must first cleanup any pending DMA,
442 * then restart stuff after a la ath5k_init.
444 * Called with ah->lock.
447 ath5k_chan_set(struct ath5k_hw
*ah
, struct cfg80211_chan_def
*chandef
)
449 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
450 "channel set, resetting (%u -> %u MHz)\n",
451 ah
->curchan
->center_freq
, chandef
->chan
->center_freq
);
453 switch (chandef
->width
) {
454 case NL80211_CHAN_WIDTH_20
:
455 case NL80211_CHAN_WIDTH_20_NOHT
:
456 ah
->ah_bwmode
= AR5K_BWMODE_DEFAULT
;
458 case NL80211_CHAN_WIDTH_5
:
459 ah
->ah_bwmode
= AR5K_BWMODE_5MHZ
;
461 case NL80211_CHAN_WIDTH_10
:
462 ah
->ah_bwmode
= AR5K_BWMODE_10MHZ
;
470 * To switch channels clear any pending DMA operations;
471 * wait long enough for the RX fifo to drain, reset the
472 * hardware at the new frequency, and then re-enable
473 * the relevant bits of the h/w.
475 return ath5k_reset(ah
, chandef
->chan
, true);
478 void ath5k_vif_iter(void *data
, u8
*mac
, struct ieee80211_vif
*vif
)
480 struct ath5k_vif_iter_data
*iter_data
= data
;
482 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
484 if (iter_data
->hw_macaddr
)
485 for (i
= 0; i
< ETH_ALEN
; i
++)
486 iter_data
->mask
[i
] &=
487 ~(iter_data
->hw_macaddr
[i
] ^ mac
[i
]);
489 if (!iter_data
->found_active
) {
490 iter_data
->found_active
= true;
491 memcpy(iter_data
->active_mac
, mac
, ETH_ALEN
);
494 if (iter_data
->need_set_hw_addr
&& iter_data
->hw_macaddr
)
495 if (ether_addr_equal(iter_data
->hw_macaddr
, mac
))
496 iter_data
->need_set_hw_addr
= false;
498 if (!iter_data
->any_assoc
) {
500 iter_data
->any_assoc
= true;
503 /* Calculate combined mode - when APs are active, operate in AP mode.
504 * Otherwise use the mode of the new interface. This can currently
505 * only deal with combinations of APs and STAs. Only one ad-hoc
506 * interfaces is allowed.
508 if (avf
->opmode
== NL80211_IFTYPE_AP
)
509 iter_data
->opmode
= NL80211_IFTYPE_AP
;
511 if (avf
->opmode
== NL80211_IFTYPE_STATION
)
513 if (iter_data
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
514 iter_data
->opmode
= avf
->opmode
;
519 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw
*ah
,
520 struct ieee80211_vif
*vif
)
522 struct ath_common
*common
= ath5k_hw_common(ah
);
523 struct ath5k_vif_iter_data iter_data
;
527 * Use the hardware MAC address as reference, the hardware uses it
528 * together with the BSSID mask when matching addresses.
530 iter_data
.hw_macaddr
= common
->macaddr
;
531 eth_broadcast_addr(iter_data
.mask
);
532 iter_data
.found_active
= false;
533 iter_data
.need_set_hw_addr
= true;
534 iter_data
.opmode
= NL80211_IFTYPE_UNSPECIFIED
;
535 iter_data
.n_stas
= 0;
538 ath5k_vif_iter(&iter_data
, vif
->addr
, vif
);
540 /* Get list of all active MAC addresses */
541 ieee80211_iterate_active_interfaces_atomic(
542 ah
->hw
, IEEE80211_IFACE_ITER_RESUME_ALL
,
543 ath5k_vif_iter
, &iter_data
);
544 memcpy(ah
->bssidmask
, iter_data
.mask
, ETH_ALEN
);
546 ah
->opmode
= iter_data
.opmode
;
547 if (ah
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
548 /* Nothing active, default to station mode */
549 ah
->opmode
= NL80211_IFTYPE_STATION
;
551 ath5k_hw_set_opmode(ah
, ah
->opmode
);
552 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "mode setup opmode %d (%s)\n",
553 ah
->opmode
, ath_opmode_to_string(ah
->opmode
));
555 if (iter_data
.need_set_hw_addr
&& iter_data
.found_active
)
556 ath5k_hw_set_lladdr(ah
, iter_data
.active_mac
);
558 if (ath5k_hw_hasbssidmask(ah
))
559 ath5k_hw_set_bssid_mask(ah
, ah
->bssidmask
);
561 /* Set up RX Filter */
562 if (iter_data
.n_stas
> 1) {
563 /* If you have multiple STA interfaces connected to
564 * different APs, ARPs are not received (most of the time?)
565 * Enabling PROMISC appears to fix that problem.
567 ah
->filter_flags
|= AR5K_RX_FILTER_PROM
;
570 rfilt
= ah
->filter_flags
;
571 ath5k_hw_set_rx_filter(ah
, rfilt
);
572 ATH5K_DBG(ah
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
576 ath5k_hw_to_driver_rix(struct ath5k_hw
*ah
, int hw_rix
)
580 /* return base rate on errors */
581 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
582 "hw_rix out of bounds: %x\n", hw_rix
))
585 rix
= ah
->rate_idx
[ah
->curchan
->band
][hw_rix
];
586 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
597 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_hw
*ah
, dma_addr_t
*skb_addr
)
599 struct ath_common
*common
= ath5k_hw_common(ah
);
603 * Allocate buffer with headroom_needed space for the
604 * fake physical layer header at the start.
606 skb
= ath_rxbuf_alloc(common
,
611 ATH5K_ERR(ah
, "can't alloc skbuff of size %u\n",
616 *skb_addr
= dma_map_single(ah
->dev
,
617 skb
->data
, common
->rx_bufsize
,
620 if (unlikely(dma_mapping_error(ah
->dev
, *skb_addr
))) {
621 ATH5K_ERR(ah
, "%s: DMA mapping failed\n", __func__
);
629 ath5k_rxbuf_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
631 struct sk_buff
*skb
= bf
->skb
;
632 struct ath5k_desc
*ds
;
636 skb
= ath5k_rx_skb_alloc(ah
, &bf
->skbaddr
);
643 * Setup descriptors. For receive we always terminate
644 * the descriptor list with a self-linked entry so we'll
645 * not get overrun under high load (as can happen with a
646 * 5212 when ANI processing enables PHY error frames).
648 * To ensure the last descriptor is self-linked we create
649 * each descriptor as self-linked and add it to the end. As
650 * each additional descriptor is added the previous self-linked
651 * entry is "fixed" naturally. This should be safe even
652 * if DMA is happening. When processing RX interrupts we
653 * never remove/process the last, self-linked, entry on the
654 * descriptor list. This ensures the hardware always has
655 * someplace to write a new frame.
658 ds
->ds_link
= bf
->daddr
; /* link to self */
659 ds
->ds_data
= bf
->skbaddr
;
660 ret
= ath5k_hw_setup_rx_desc(ah
, ds
, ah
->common
.rx_bufsize
, 0);
662 ATH5K_ERR(ah
, "%s: could not setup RX desc\n", __func__
);
666 if (ah
->rxlink
!= NULL
)
667 *ah
->rxlink
= bf
->daddr
;
668 ah
->rxlink
= &ds
->ds_link
;
672 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
674 struct ieee80211_hdr
*hdr
;
675 enum ath5k_pkt_type htype
;
678 hdr
= (struct ieee80211_hdr
*)skb
->data
;
679 fc
= hdr
->frame_control
;
681 if (ieee80211_is_beacon(fc
))
682 htype
= AR5K_PKT_TYPE_BEACON
;
683 else if (ieee80211_is_probe_resp(fc
))
684 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
685 else if (ieee80211_is_atim(fc
))
686 htype
= AR5K_PKT_TYPE_ATIM
;
687 else if (ieee80211_is_pspoll(fc
))
688 htype
= AR5K_PKT_TYPE_PSPOLL
;
690 htype
= AR5K_PKT_TYPE_NORMAL
;
695 static struct ieee80211_rate
*
696 ath5k_get_rate(const struct ieee80211_hw
*hw
,
697 const struct ieee80211_tx_info
*info
,
698 struct ath5k_buf
*bf
, int idx
)
701 * convert a ieee80211_tx_rate RC-table entry to
702 * the respective ieee80211_rate struct
704 if (bf
->rates
[idx
].idx
< 0) {
708 return &hw
->wiphy
->bands
[info
->band
]->bitrates
[ bf
->rates
[idx
].idx
];
712 ath5k_get_rate_hw_value(const struct ieee80211_hw
*hw
,
713 const struct ieee80211_tx_info
*info
,
714 struct ath5k_buf
*bf
, int idx
)
716 struct ieee80211_rate
*rate
;
720 rate
= ath5k_get_rate(hw
, info
, bf
, idx
);
724 rc_flags
= bf
->rates
[idx
].flags
;
725 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
726 rate
->hw_value_short
: rate
->hw_value
;
732 ath5k_txbuf_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
,
733 struct ath5k_txq
*txq
, int padsize
,
734 struct ieee80211_tx_control
*control
)
736 struct ath5k_desc
*ds
= bf
->desc
;
737 struct sk_buff
*skb
= bf
->skb
;
738 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
739 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
740 struct ieee80211_rate
*rate
;
741 unsigned int mrr_rate
[3], mrr_tries
[3];
748 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
751 bf
->skbaddr
= dma_map_single(ah
->dev
, skb
->data
, skb
->len
,
754 if (dma_mapping_error(ah
->dev
, bf
->skbaddr
))
757 ieee80211_get_tx_rates(info
->control
.vif
, (control
) ? control
->sta
: NULL
, skb
, bf
->rates
,
758 ARRAY_SIZE(bf
->rates
));
760 rate
= ath5k_get_rate(ah
->hw
, info
, bf
, 0);
767 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
768 flags
|= AR5K_TXDESC_NOACK
;
770 rc_flags
= info
->control
.rates
[0].flags
;
772 hw_rate
= ath5k_get_rate_hw_value(ah
->hw
, info
, bf
, 0);
776 /* FIXME: If we are in g mode and rate is a CCK rate
777 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
778 * from tx power (value is in dB units already) */
779 if (info
->control
.hw_key
) {
780 keyidx
= info
->control
.hw_key
->hw_key_idx
;
781 pktlen
+= info
->control
.hw_key
->icv_len
;
783 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
784 flags
|= AR5K_TXDESC_RTSENA
;
785 cts_rate
= ieee80211_get_rts_cts_rate(ah
->hw
, info
)->hw_value
;
786 duration
= le16_to_cpu(ieee80211_rts_duration(ah
->hw
,
787 info
->control
.vif
, pktlen
, info
));
789 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
790 flags
|= AR5K_TXDESC_CTSENA
;
791 cts_rate
= ieee80211_get_rts_cts_rate(ah
->hw
, info
)->hw_value
;
792 duration
= le16_to_cpu(ieee80211_ctstoself_duration(ah
->hw
,
793 info
->control
.vif
, pktlen
, info
));
796 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
797 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
798 get_hw_packet_type(skb
),
799 (ah
->ah_txpower
.txp_requested
* 2),
801 bf
->rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
806 /* Set up MRR descriptor */
807 if (ah
->ah_capabilities
.cap_has_mrr_support
) {
808 memset(mrr_rate
, 0, sizeof(mrr_rate
));
809 memset(mrr_tries
, 0, sizeof(mrr_tries
));
811 for (i
= 0; i
< 3; i
++) {
813 rate
= ath5k_get_rate(ah
->hw
, info
, bf
, i
);
817 mrr_rate
[i
] = ath5k_get_rate_hw_value(ah
->hw
, info
, bf
, i
);
818 mrr_tries
[i
] = bf
->rates
[i
].count
;
821 ath5k_hw_setup_mrr_tx_desc(ah
, ds
,
822 mrr_rate
[0], mrr_tries
[0],
823 mrr_rate
[1], mrr_tries
[1],
824 mrr_rate
[2], mrr_tries
[2]);
828 ds
->ds_data
= bf
->skbaddr
;
830 spin_lock_bh(&txq
->lock
);
831 list_add_tail(&bf
->list
, &txq
->q
);
833 if (txq
->link
== NULL
) /* is this first packet? */
834 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
835 else /* no, so only link it */
836 *txq
->link
= bf
->daddr
;
838 txq
->link
= &ds
->ds_link
;
839 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
841 spin_unlock_bh(&txq
->lock
);
845 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
849 /*******************\
850 * Descriptors setup *
851 \*******************/
854 ath5k_desc_alloc(struct ath5k_hw
*ah
)
856 struct ath5k_desc
*ds
;
857 struct ath5k_buf
*bf
;
862 /* allocate descriptors */
863 ah
->desc_len
= sizeof(struct ath5k_desc
) *
864 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
866 ah
->desc
= dma_alloc_coherent(ah
->dev
, ah
->desc_len
,
867 &ah
->desc_daddr
, GFP_KERNEL
);
868 if (ah
->desc
== NULL
) {
869 ATH5K_ERR(ah
, "can't allocate descriptors\n");
875 ATH5K_DBG(ah
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
876 ds
, ah
->desc_len
, (unsigned long long)ah
->desc_daddr
);
878 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
879 sizeof(struct ath5k_buf
), GFP_KERNEL
);
881 ATH5K_ERR(ah
, "can't allocate bufptr\n");
887 INIT_LIST_HEAD(&ah
->rxbuf
);
888 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
891 list_add_tail(&bf
->list
, &ah
->rxbuf
);
894 INIT_LIST_HEAD(&ah
->txbuf
);
895 ah
->txbuf_len
= ATH_TXBUF
;
896 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
899 list_add_tail(&bf
->list
, &ah
->txbuf
);
903 INIT_LIST_HEAD(&ah
->bcbuf
);
904 for (i
= 0; i
< ATH_BCBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
907 list_add_tail(&bf
->list
, &ah
->bcbuf
);
912 dma_free_coherent(ah
->dev
, ah
->desc_len
, ah
->desc
, ah
->desc_daddr
);
919 ath5k_txbuf_free_skb(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
924 dma_unmap_single(ah
->dev
, bf
->skbaddr
, bf
->skb
->len
,
926 ieee80211_free_txskb(ah
->hw
, bf
->skb
);
929 bf
->desc
->ds_data
= 0;
933 ath5k_rxbuf_free_skb(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
935 struct ath_common
*common
= ath5k_hw_common(ah
);
940 dma_unmap_single(ah
->dev
, bf
->skbaddr
, common
->rx_bufsize
,
942 dev_kfree_skb_any(bf
->skb
);
945 bf
->desc
->ds_data
= 0;
949 ath5k_desc_free(struct ath5k_hw
*ah
)
951 struct ath5k_buf
*bf
;
953 list_for_each_entry(bf
, &ah
->txbuf
, list
)
954 ath5k_txbuf_free_skb(ah
, bf
);
955 list_for_each_entry(bf
, &ah
->rxbuf
, list
)
956 ath5k_rxbuf_free_skb(ah
, bf
);
957 list_for_each_entry(bf
, &ah
->bcbuf
, list
)
958 ath5k_txbuf_free_skb(ah
, bf
);
960 /* Free memory associated with all descriptors */
961 dma_free_coherent(ah
->dev
, ah
->desc_len
, ah
->desc
, ah
->desc_daddr
);
974 static struct ath5k_txq
*
975 ath5k_txq_setup(struct ath5k_hw
*ah
,
976 int qtype
, int subtype
)
978 struct ath5k_txq
*txq
;
979 struct ath5k_txq_info qi
= {
980 .tqi_subtype
= subtype
,
981 /* XXX: default values not correct for B and XR channels,
983 .tqi_aifs
= AR5K_TUNE_AIFS
,
984 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
985 .tqi_cw_max
= AR5K_TUNE_CWMAX
990 * Enable interrupts only for EOL and DESC conditions.
991 * We mark tx descriptors to receive a DESC interrupt
992 * when a tx queue gets deep; otherwise we wait for the
993 * EOL to reap descriptors. Note that this is done to
994 * reduce interrupt load and this only defers reaping
995 * descriptors, never transmitting frames. Aside from
996 * reducing interrupts this also permits more concurrency.
997 * The only potential downside is if the tx queue backs
998 * up in which case the top half of the kernel may backup
999 * due to a lack of tx descriptors.
1001 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1002 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1003 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1006 * NB: don't print a message, this happens
1007 * normally on parts with too few tx queues
1009 return ERR_PTR(qnum
);
1011 txq
= &ah
->txqs
[qnum
];
1015 INIT_LIST_HEAD(&txq
->q
);
1016 spin_lock_init(&txq
->lock
);
1019 txq
->txq_max
= ATH5K_TXQ_LEN_MAX
;
1020 txq
->txq_poll_mark
= false;
1023 return &ah
->txqs
[qnum
];
1027 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1029 struct ath5k_txq_info qi
= {
1030 /* XXX: default values not correct for B and XR channels,
1032 .tqi_aifs
= AR5K_TUNE_AIFS
,
1033 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
1034 .tqi_cw_max
= AR5K_TUNE_CWMAX
,
1035 /* NB: for dynamic turbo, don't enable any other interrupts */
1036 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1039 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1043 ath5k_beaconq_config(struct ath5k_hw
*ah
)
1045 struct ath5k_txq_info qi
;
1048 ret
= ath5k_hw_get_tx_queueprops(ah
, ah
->bhalq
, &qi
);
1052 if (ah
->opmode
== NL80211_IFTYPE_AP
||
1053 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1055 * Always burst out beacon and CAB traffic
1056 * (aifs = cwmin = cwmax = 0)
1061 } else if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
1063 * Adhoc mode; backoff between 0 and (2 * cw_min).
1067 qi
.tqi_cw_max
= 2 * AR5K_TUNE_CWMIN
;
1070 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1071 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1072 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1074 ret
= ath5k_hw_set_tx_queueprops(ah
, ah
->bhalq
, &qi
);
1076 ATH5K_ERR(ah
, "%s: unable to update parameters for beacon "
1077 "hardware queue!\n", __func__
);
1080 ret
= ath5k_hw_reset_tx_queue(ah
, ah
->bhalq
); /* push to h/w */
1084 /* reconfigure cabq with ready time to 80% of beacon_interval */
1085 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1089 qi
.tqi_ready_time
= (ah
->bintval
* 80) / 100;
1090 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1094 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1100 * ath5k_drain_tx_buffs - Empty tx buffers
1102 * @ah The &struct ath5k_hw
1104 * Empty tx buffers from all queues in preparation
1105 * of a reset or during shutdown.
1107 * NB: this assumes output has been stopped and
1108 * we do not need to block ath5k_tx_tasklet
1111 ath5k_drain_tx_buffs(struct ath5k_hw
*ah
)
1113 struct ath5k_txq
*txq
;
1114 struct ath5k_buf
*bf
, *bf0
;
1117 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++) {
1118 if (ah
->txqs
[i
].setup
) {
1120 spin_lock_bh(&txq
->lock
);
1121 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1122 ath5k_debug_printtxbuf(ah
, bf
);
1124 ath5k_txbuf_free_skb(ah
, bf
);
1126 spin_lock(&ah
->txbuflock
);
1127 list_move_tail(&bf
->list
, &ah
->txbuf
);
1130 spin_unlock(&ah
->txbuflock
);
1133 txq
->txq_poll_mark
= false;
1134 spin_unlock_bh(&txq
->lock
);
1140 ath5k_txq_release(struct ath5k_hw
*ah
)
1142 struct ath5k_txq
*txq
= ah
->txqs
;
1145 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++, txq
++)
1147 ath5k_hw_release_tx_queue(ah
, txq
->qnum
);
1158 * Enable the receive h/w following a reset.
1161 ath5k_rx_start(struct ath5k_hw
*ah
)
1163 struct ath_common
*common
= ath5k_hw_common(ah
);
1164 struct ath5k_buf
*bf
;
1167 common
->rx_bufsize
= roundup(IEEE80211_MAX_FRAME_LEN
, common
->cachelsz
);
1169 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1170 common
->cachelsz
, common
->rx_bufsize
);
1172 spin_lock_bh(&ah
->rxbuflock
);
1174 list_for_each_entry(bf
, &ah
->rxbuf
, list
) {
1175 ret
= ath5k_rxbuf_setup(ah
, bf
);
1177 spin_unlock_bh(&ah
->rxbuflock
);
1181 bf
= list_first_entry(&ah
->rxbuf
, struct ath5k_buf
, list
);
1182 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1183 spin_unlock_bh(&ah
->rxbuflock
);
1185 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1186 ath5k_update_bssid_mask_and_opmode(ah
, NULL
); /* set filters, etc. */
1187 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1195 * Disable the receive logic on PCU (DRU)
1196 * In preparation for a shutdown.
1198 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1202 ath5k_rx_stop(struct ath5k_hw
*ah
)
1205 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1206 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1208 ath5k_debug_printrxbuffs(ah
);
1212 ath5k_rx_decrypted(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1213 struct ath5k_rx_status
*rs
)
1215 struct ath_common
*common
= ath5k_hw_common(ah
);
1216 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1217 unsigned int keyix
, hlen
;
1219 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1220 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1221 return RX_FLAG_DECRYPTED
;
1223 /* Apparently when a default key is used to decrypt the packet
1224 the hw does not set the index used to decrypt. In such cases
1225 get the index from the packet. */
1226 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1227 if (ieee80211_has_protected(hdr
->frame_control
) &&
1228 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1229 skb
->len
>= hlen
+ 4) {
1230 keyix
= skb
->data
[hlen
+ 3] >> 6;
1232 if (test_bit(keyix
, common
->keymap
))
1233 return RX_FLAG_DECRYPTED
;
1241 ath5k_check_ibss_tsf(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1242 struct ieee80211_rx_status
*rxs
)
1246 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1248 if (le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
) {
1250 * Received an IBSS beacon with the same BSSID. Hardware *must*
1251 * have updated the local TSF. We have to work around various
1252 * hardware bugs, though...
1254 tsf
= ath5k_hw_get_tsf64(ah
);
1255 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1256 hw_tu
= TSF_TO_TU(tsf
);
1258 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1259 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1260 (unsigned long long)bc_tstamp
,
1261 (unsigned long long)rxs
->mactime
,
1262 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1263 (unsigned long long)tsf
);
1266 * Sometimes the HW will give us a wrong tstamp in the rx
1267 * status, causing the timestamp extension to go wrong.
1268 * (This seems to happen especially with beacon frames bigger
1269 * than 78 byte (incl. FCS))
1270 * But we know that the receive timestamp must be later than the
1271 * timestamp of the beacon since HW must have synced to that.
1273 * NOTE: here we assume mactime to be after the frame was
1274 * received, not like mac80211 which defines it at the start.
1276 if (bc_tstamp
> rxs
->mactime
) {
1277 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1278 "fixing mactime from %llx to %llx\n",
1279 (unsigned long long)rxs
->mactime
,
1280 (unsigned long long)tsf
);
1285 * Local TSF might have moved higher than our beacon timers,
1286 * in that case we have to update them to continue sending
1287 * beacons. This also takes care of synchronizing beacon sending
1288 * times with other stations.
1290 if (hw_tu
>= ah
->nexttbtt
)
1291 ath5k_beacon_update_timers(ah
, bc_tstamp
);
1293 /* Check if the beacon timers are still correct, because a TSF
1294 * update might have created a window between them - for a
1295 * longer description see the comment of this function: */
1296 if (!ath5k_hw_check_beacon_timers(ah
, ah
->bintval
)) {
1297 ath5k_beacon_update_timers(ah
, bc_tstamp
);
1298 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
1299 "fixed beacon timers after beacon receive\n");
1305 * Compute padding position. skb must contain an IEEE 802.11 frame
1307 static int ath5k_common_padpos(struct sk_buff
*skb
)
1309 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1310 __le16 frame_control
= hdr
->frame_control
;
1313 if (ieee80211_has_a4(frame_control
))
1316 if (ieee80211_is_data_qos(frame_control
))
1317 padpos
+= IEEE80211_QOS_CTL_LEN
;
1323 * This function expects an 802.11 frame and returns the number of
1324 * bytes added, or -1 if we don't have enough header room.
1326 static int ath5k_add_padding(struct sk_buff
*skb
)
1328 int padpos
= ath5k_common_padpos(skb
);
1329 int padsize
= padpos
& 3;
1331 if (padsize
&& skb
->len
> padpos
) {
1333 if (skb_headroom(skb
) < padsize
)
1336 skb_push(skb
, padsize
);
1337 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1345 * The MAC header is padded to have 32-bit boundary if the
1346 * packet payload is non-zero. The general calculation for
1347 * padsize would take into account odd header lengths:
1348 * padsize = 4 - (hdrlen & 3); however, since only
1349 * even-length headers are used, padding can only be 0 or 2
1350 * bytes and we can optimize this a bit. We must not try to
1351 * remove padding from short control frames that do not have a
1354 * This function expects an 802.11 frame and returns the number of
1357 static int ath5k_remove_padding(struct sk_buff
*skb
)
1359 int padpos
= ath5k_common_padpos(skb
);
1360 int padsize
= padpos
& 3;
1362 if (padsize
&& skb
->len
>= padpos
+ padsize
) {
1363 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1364 skb_pull(skb
, padsize
);
1372 ath5k_receive_frame(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1373 struct ath5k_rx_status
*rs
)
1375 struct ieee80211_rx_status
*rxs
;
1376 struct ath_common
*common
= ath5k_hw_common(ah
);
1378 ath5k_remove_padding(skb
);
1380 rxs
= IEEE80211_SKB_RXCB(skb
);
1383 if (unlikely(rs
->rs_status
& AR5K_RXERR_MIC
))
1384 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
1385 if (unlikely(rs
->rs_status
& AR5K_RXERR_CRC
))
1386 rxs
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
1390 * always extend the mac timestamp, since this information is
1391 * also needed for proper IBSS merging.
1393 * XXX: it might be too late to do it here, since rs_tstamp is
1394 * 15bit only. that means TSF extension has to be done within
1395 * 32768usec (about 32ms). it might be necessary to move this to
1396 * the interrupt handler, like it is done in madwifi.
1398 rxs
->mactime
= ath5k_extend_tsf(ah
, rs
->rs_tstamp
);
1399 rxs
->flag
|= RX_FLAG_MACTIME_END
;
1401 rxs
->freq
= ah
->curchan
->center_freq
;
1402 rxs
->band
= ah
->curchan
->band
;
1404 rxs
->signal
= ah
->ah_noise_floor
+ rs
->rs_rssi
;
1406 rxs
->antenna
= rs
->rs_antenna
;
1408 if (rs
->rs_antenna
> 0 && rs
->rs_antenna
< 5)
1409 ah
->stats
.antenna_rx
[rs
->rs_antenna
]++;
1411 ah
->stats
.antenna_rx
[0]++; /* invalid */
1413 rxs
->rate_idx
= ath5k_hw_to_driver_rix(ah
, rs
->rs_rate
);
1414 rxs
->flag
|= ath5k_rx_decrypted(ah
, skb
, rs
);
1415 switch (ah
->ah_bwmode
) {
1416 case AR5K_BWMODE_5MHZ
:
1417 rxs
->flag
|= RX_FLAG_5MHZ
;
1419 case AR5K_BWMODE_10MHZ
:
1420 rxs
->flag
|= RX_FLAG_10MHZ
;
1427 ah
->sbands
[ah
->curchan
->band
].bitrates
[rxs
->rate_idx
].hw_value_short
)
1428 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1430 trace_ath5k_rx(ah
, skb
);
1432 if (ath_is_mybeacon(common
, (struct ieee80211_hdr
*)skb
->data
)) {
1433 ewma_add(&ah
->ah_beacon_rssi_avg
, rs
->rs_rssi
);
1435 /* check beacons in IBSS mode */
1436 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
)
1437 ath5k_check_ibss_tsf(ah
, skb
, rxs
);
1440 ieee80211_rx(ah
->hw
, skb
);
1443 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1445 * Check if we want to further process this frame or not. Also update
1446 * statistics. Return true if we want this frame, false if not.
1449 ath5k_receive_frame_ok(struct ath5k_hw
*ah
, struct ath5k_rx_status
*rs
)
1451 ah
->stats
.rx_all_count
++;
1452 ah
->stats
.rx_bytes_count
+= rs
->rs_datalen
;
1454 if (unlikely(rs
->rs_status
)) {
1455 unsigned int filters
;
1457 if (rs
->rs_status
& AR5K_RXERR_CRC
)
1458 ah
->stats
.rxerr_crc
++;
1459 if (rs
->rs_status
& AR5K_RXERR_FIFO
)
1460 ah
->stats
.rxerr_fifo
++;
1461 if (rs
->rs_status
& AR5K_RXERR_PHY
) {
1462 ah
->stats
.rxerr_phy
++;
1463 if (rs
->rs_phyerr
> 0 && rs
->rs_phyerr
< 32)
1464 ah
->stats
.rxerr_phy_code
[rs
->rs_phyerr
]++;
1467 * Treat packets that underwent a CCK or OFDM reset as having a bad CRC.
1468 * These restarts happen when the radio resynchronizes to a stronger frame
1469 * while receiving a weaker frame. Here we receive the prefix of the weak
1470 * frame. Since these are incomplete packets, mark their CRC as invalid.
1472 if (rs
->rs_phyerr
== AR5K_RX_PHY_ERROR_OFDM_RESTART
||
1473 rs
->rs_phyerr
== AR5K_RX_PHY_ERROR_CCK_RESTART
) {
1474 rs
->rs_status
|= AR5K_RXERR_CRC
;
1475 rs
->rs_status
&= ~AR5K_RXERR_PHY
;
1480 if (rs
->rs_status
& AR5K_RXERR_DECRYPT
) {
1482 * Decrypt error. If the error occurred
1483 * because there was no hardware key, then
1484 * let the frame through so the upper layers
1485 * can process it. This is necessary for 5210
1486 * parts which have no way to setup a ``clear''
1489 * XXX do key cache faulting
1491 ah
->stats
.rxerr_decrypt
++;
1492 if (rs
->rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1493 !(rs
->rs_status
& AR5K_RXERR_CRC
))
1496 if (rs
->rs_status
& AR5K_RXERR_MIC
) {
1497 ah
->stats
.rxerr_mic
++;
1502 * Reject any frames with non-crypto errors, and take into account the
1503 * current FIF_* filters.
1505 filters
= AR5K_RXERR_DECRYPT
;
1506 if (ah
->fif_filter_flags
& FIF_FCSFAIL
)
1507 filters
|= AR5K_RXERR_CRC
;
1509 if (rs
->rs_status
& ~filters
)
1513 if (unlikely(rs
->rs_more
)) {
1514 ah
->stats
.rxerr_jumbo
++;
1521 ath5k_set_current_imask(struct ath5k_hw
*ah
)
1523 enum ath5k_int imask
;
1524 unsigned long flags
;
1526 spin_lock_irqsave(&ah
->irqlock
, flags
);
1529 imask
&= ~AR5K_INT_RX_ALL
;
1531 imask
&= ~AR5K_INT_TX_ALL
;
1532 ath5k_hw_set_imr(ah
, imask
);
1533 spin_unlock_irqrestore(&ah
->irqlock
, flags
);
1537 ath5k_tasklet_rx(unsigned long data
)
1539 struct ath5k_rx_status rs
= {};
1540 struct sk_buff
*skb
, *next_skb
;
1541 dma_addr_t next_skb_addr
;
1542 struct ath5k_hw
*ah
= (void *)data
;
1543 struct ath_common
*common
= ath5k_hw_common(ah
);
1544 struct ath5k_buf
*bf
;
1545 struct ath5k_desc
*ds
;
1548 spin_lock(&ah
->rxbuflock
);
1549 if (list_empty(&ah
->rxbuf
)) {
1550 ATH5K_WARN(ah
, "empty rx buf pool\n");
1554 bf
= list_first_entry(&ah
->rxbuf
, struct ath5k_buf
, list
);
1555 BUG_ON(bf
->skb
== NULL
);
1559 /* bail if HW is still using self-linked descriptor */
1560 if (ath5k_hw_get_rxdp(ah
) == bf
->daddr
)
1563 ret
= ah
->ah_proc_rx_desc(ah
, ds
, &rs
);
1564 if (unlikely(ret
== -EINPROGRESS
))
1566 else if (unlikely(ret
)) {
1567 ATH5K_ERR(ah
, "error in processing rx descriptor\n");
1568 ah
->stats
.rxerr_proc
++;
1572 if (ath5k_receive_frame_ok(ah
, &rs
)) {
1573 next_skb
= ath5k_rx_skb_alloc(ah
, &next_skb_addr
);
1576 * If we can't replace bf->skb with a new skb under
1577 * memory pressure, just skip this packet
1582 dma_unmap_single(ah
->dev
, bf
->skbaddr
,
1586 skb_put(skb
, rs
.rs_datalen
);
1588 ath5k_receive_frame(ah
, skb
, &rs
);
1591 bf
->skbaddr
= next_skb_addr
;
1594 list_move_tail(&bf
->list
, &ah
->rxbuf
);
1595 } while (ath5k_rxbuf_setup(ah
, bf
) == 0);
1597 spin_unlock(&ah
->rxbuflock
);
1598 ah
->rx_pending
= false;
1599 ath5k_set_current_imask(ah
);
1608 ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1609 struct ath5k_txq
*txq
, struct ieee80211_tx_control
*control
)
1611 struct ath5k_hw
*ah
= hw
->priv
;
1612 struct ath5k_buf
*bf
;
1613 unsigned long flags
;
1616 trace_ath5k_tx(ah
, skb
, txq
);
1619 * The hardware expects the header padded to 4 byte boundaries.
1620 * If this is not the case, we add the padding after the header.
1622 padsize
= ath5k_add_padding(skb
);
1624 ATH5K_ERR(ah
, "tx hdrlen not %%4: not enough"
1625 " headroom to pad");
1629 if (txq
->txq_len
>= txq
->txq_max
&&
1630 txq
->qnum
<= AR5K_TX_QUEUE_ID_DATA_MAX
)
1631 ieee80211_stop_queue(hw
, txq
->qnum
);
1633 spin_lock_irqsave(&ah
->txbuflock
, flags
);
1634 if (list_empty(&ah
->txbuf
)) {
1635 ATH5K_ERR(ah
, "no further txbuf available, dropping packet\n");
1636 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1637 ieee80211_stop_queues(hw
);
1640 bf
= list_first_entry(&ah
->txbuf
, struct ath5k_buf
, list
);
1641 list_del(&bf
->list
);
1643 if (list_empty(&ah
->txbuf
))
1644 ieee80211_stop_queues(hw
);
1645 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1649 if (ath5k_txbuf_setup(ah
, bf
, txq
, padsize
, control
)) {
1651 spin_lock_irqsave(&ah
->txbuflock
, flags
);
1652 list_add_tail(&bf
->list
, &ah
->txbuf
);
1654 spin_unlock_irqrestore(&ah
->txbuflock
, flags
);
1660 ieee80211_free_txskb(hw
, skb
);
1664 ath5k_tx_frame_completed(struct ath5k_hw
*ah
, struct sk_buff
*skb
,
1665 struct ath5k_txq
*txq
, struct ath5k_tx_status
*ts
,
1666 struct ath5k_buf
*bf
)
1668 struct ieee80211_tx_info
*info
;
1673 ah
->stats
.tx_all_count
++;
1674 ah
->stats
.tx_bytes_count
+= skb
->len
;
1675 info
= IEEE80211_SKB_CB(skb
);
1677 size
= min_t(int, sizeof(info
->status
.rates
), sizeof(bf
->rates
));
1678 memcpy(info
->status
.rates
, bf
->rates
, size
);
1680 tries
[0] = info
->status
.rates
[0].count
;
1681 tries
[1] = info
->status
.rates
[1].count
;
1682 tries
[2] = info
->status
.rates
[2].count
;
1684 ieee80211_tx_info_clear_status(info
);
1686 for (i
= 0; i
< ts
->ts_final_idx
; i
++) {
1687 struct ieee80211_tx_rate
*r
=
1688 &info
->status
.rates
[i
];
1690 r
->count
= tries
[i
];
1693 info
->status
.rates
[ts
->ts_final_idx
].count
= ts
->ts_final_retry
;
1694 info
->status
.rates
[ts
->ts_final_idx
+ 1].idx
= -1;
1696 if (unlikely(ts
->ts_status
)) {
1697 ah
->stats
.ack_fail
++;
1698 if (ts
->ts_status
& AR5K_TXERR_FILT
) {
1699 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1700 ah
->stats
.txerr_filt
++;
1702 if (ts
->ts_status
& AR5K_TXERR_XRETRY
)
1703 ah
->stats
.txerr_retry
++;
1704 if (ts
->ts_status
& AR5K_TXERR_FIFO
)
1705 ah
->stats
.txerr_fifo
++;
1707 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1708 info
->status
.ack_signal
= ts
->ts_rssi
;
1710 /* count the successful attempt as well */
1711 info
->status
.rates
[ts
->ts_final_idx
].count
++;
1715 * Remove MAC header padding before giving the frame
1718 ath5k_remove_padding(skb
);
1720 if (ts
->ts_antenna
> 0 && ts
->ts_antenna
< 5)
1721 ah
->stats
.antenna_tx
[ts
->ts_antenna
]++;
1723 ah
->stats
.antenna_tx
[0]++; /* invalid */
1725 trace_ath5k_tx_complete(ah
, skb
, txq
, ts
);
1726 ieee80211_tx_status(ah
->hw
, skb
);
1730 ath5k_tx_processq(struct ath5k_hw
*ah
, struct ath5k_txq
*txq
)
1732 struct ath5k_tx_status ts
= {};
1733 struct ath5k_buf
*bf
, *bf0
;
1734 struct ath5k_desc
*ds
;
1735 struct sk_buff
*skb
;
1738 spin_lock(&txq
->lock
);
1739 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1741 txq
->txq_poll_mark
= false;
1743 /* skb might already have been processed last time. */
1744 if (bf
->skb
!= NULL
) {
1747 ret
= ah
->ah_proc_tx_desc(ah
, ds
, &ts
);
1748 if (unlikely(ret
== -EINPROGRESS
))
1750 else if (unlikely(ret
)) {
1752 "error %d while processing "
1753 "queue %u\n", ret
, txq
->qnum
);
1760 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
,
1762 ath5k_tx_frame_completed(ah
, skb
, txq
, &ts
, bf
);
1766 * It's possible that the hardware can say the buffer is
1767 * completed when it hasn't yet loaded the ds_link from
1768 * host memory and moved on.
1769 * Always keep the last descriptor to avoid HW races...
1771 if (ath5k_hw_get_txdp(ah
, txq
->qnum
) != bf
->daddr
) {
1772 spin_lock(&ah
->txbuflock
);
1773 list_move_tail(&bf
->list
, &ah
->txbuf
);
1776 spin_unlock(&ah
->txbuflock
);
1779 spin_unlock(&txq
->lock
);
1780 if (txq
->txq_len
< ATH5K_TXQ_LEN_LOW
&& txq
->qnum
< 4)
1781 ieee80211_wake_queue(ah
->hw
, txq
->qnum
);
1785 ath5k_tasklet_tx(unsigned long data
)
1788 struct ath5k_hw
*ah
= (void *)data
;
1790 for (i
= 0; i
< AR5K_NUM_TX_QUEUES
; i
++)
1791 if (ah
->txqs
[i
].setup
&& (ah
->ah_txq_isr_txok_all
& BIT(i
)))
1792 ath5k_tx_processq(ah
, &ah
->txqs
[i
]);
1794 ah
->tx_pending
= false;
1795 ath5k_set_current_imask(ah
);
1804 * Setup the beacon frame for transmit.
1807 ath5k_beacon_setup(struct ath5k_hw
*ah
, struct ath5k_buf
*bf
)
1809 struct sk_buff
*skb
= bf
->skb
;
1810 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1811 struct ath5k_desc
*ds
;
1815 const int padsize
= 0;
1817 bf
->skbaddr
= dma_map_single(ah
->dev
, skb
->data
, skb
->len
,
1819 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1820 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1821 (unsigned long long)bf
->skbaddr
);
1823 if (dma_mapping_error(ah
->dev
, bf
->skbaddr
)) {
1824 ATH5K_ERR(ah
, "beacon DMA mapping failed\n");
1825 dev_kfree_skb_any(skb
);
1831 antenna
= ah
->ah_tx_ant
;
1833 flags
= AR5K_TXDESC_NOACK
;
1834 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1835 ds
->ds_link
= bf
->daddr
; /* self-linked */
1836 flags
|= AR5K_TXDESC_VEOL
;
1841 * If we use multiple antennas on AP and use
1842 * the Sectored AP scenario, switch antenna every
1843 * 4 beacons to make sure everybody hears our AP.
1844 * When a client tries to associate, hw will keep
1845 * track of the tx antenna to be used for this client
1846 * automatically, based on ACKed packets.
1848 * Note: AP still listens and transmits RTS on the
1849 * default antenna which is supposed to be an omni.
1851 * Note2: On sectored scenarios it's possible to have
1852 * multiple antennas (1 omni -- the default -- and 14
1853 * sectors), so if we choose to actually support this
1854 * mode, we need to allow the user to set how many antennas
1855 * we have and tweak the code below to send beacons
1858 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
1859 antenna
= ah
->bsent
& 4 ? 2 : 1;
1862 /* FIXME: If we are in g mode and rate is a CCK rate
1863 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1864 * from tx power (value is in dB units already) */
1865 ds
->ds_data
= bf
->skbaddr
;
1866 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1867 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
1868 AR5K_PKT_TYPE_BEACON
,
1869 (ah
->ah_txpower
.txp_requested
* 2),
1870 ieee80211_get_tx_rate(ah
->hw
, info
)->hw_value
,
1871 1, AR5K_TXKEYIX_INVALID
,
1872 antenna
, flags
, 0, 0);
1878 dma_unmap_single(ah
->dev
, bf
->skbaddr
, skb
->len
, DMA_TO_DEVICE
);
1883 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1884 * this is called only once at config_bss time, for AP we do it every
1885 * SWBA interrupt so that the TIM will reflect buffered frames.
1887 * Called with the beacon lock.
1890 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
1893 struct ath5k_hw
*ah
= hw
->priv
;
1894 struct ath5k_vif
*avf
;
1895 struct sk_buff
*skb
;
1897 if (WARN_ON(!vif
)) {
1902 skb
= ieee80211_beacon_get(hw
, vif
);
1909 avf
= (void *)vif
->drv_priv
;
1910 ath5k_txbuf_free_skb(ah
, avf
->bbuf
);
1911 avf
->bbuf
->skb
= skb
;
1912 ret
= ath5k_beacon_setup(ah
, avf
->bbuf
);
1918 * Transmit a beacon frame at SWBA. Dynamic updates to the
1919 * frame contents are done as needed and the slot time is
1920 * also adjusted based on current state.
1922 * This is called from software irq context (beacontq tasklets)
1923 * or user context from ath5k_beacon_config.
1926 ath5k_beacon_send(struct ath5k_hw
*ah
)
1928 struct ieee80211_vif
*vif
;
1929 struct ath5k_vif
*avf
;
1930 struct ath5k_buf
*bf
;
1931 struct sk_buff
*skb
;
1934 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1937 * Check if the previous beacon has gone out. If
1938 * not, don't don't try to post another: skip this
1939 * period and wait for the next. Missed beacons
1940 * indicate a problem and should not occur. If we
1941 * miss too many consecutive beacons reset the device.
1943 if (unlikely(ath5k_hw_num_tx_pending(ah
, ah
->bhalq
) != 0)) {
1945 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1946 "missed %u consecutive beacons\n", ah
->bmisscount
);
1947 if (ah
->bmisscount
> 10) { /* NB: 10 is a guess */
1948 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1949 "stuck beacon time (%u missed)\n",
1951 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
1952 "stuck beacon, resetting\n");
1953 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
1957 if (unlikely(ah
->bmisscount
!= 0)) {
1958 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1959 "resume beacon xmit after %u misses\n",
1964 if ((ah
->opmode
== NL80211_IFTYPE_AP
&& ah
->num_ap_vifs
+
1965 ah
->num_mesh_vifs
> 1) ||
1966 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1967 u64 tsf
= ath5k_hw_get_tsf64(ah
);
1968 u32 tsftu
= TSF_TO_TU(tsf
);
1969 int slot
= ((tsftu
% ah
->bintval
) * ATH_BCBUF
) / ah
->bintval
;
1970 vif
= ah
->bslot
[(slot
+ 1) % ATH_BCBUF
];
1971 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
1972 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1973 (unsigned long long)tsf
, tsftu
, ah
->bintval
, slot
, vif
);
1974 } else /* only one interface */
1980 avf
= (void *)vif
->drv_priv
;
1984 * Stop any current dma and put the new frame on the queue.
1985 * This should never fail since we check above that no frames
1986 * are still pending on the queue.
1988 if (unlikely(ath5k_hw_stop_beacon_queue(ah
, ah
->bhalq
))) {
1989 ATH5K_WARN(ah
, "beacon queue %u didn't start/stop ?\n", ah
->bhalq
);
1990 /* NB: hw still stops DMA, so proceed */
1993 /* refresh the beacon for AP or MESH mode */
1994 if (ah
->opmode
== NL80211_IFTYPE_AP
||
1995 ah
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1996 err
= ath5k_beacon_update(ah
->hw
, vif
);
2001 if (unlikely(bf
->skb
== NULL
|| ah
->opmode
== NL80211_IFTYPE_STATION
||
2002 ah
->opmode
== NL80211_IFTYPE_MONITOR
)) {
2003 ATH5K_WARN(ah
, "bf=%p bf_skb=%p\n", bf
, bf
->skb
);
2007 trace_ath5k_tx(ah
, bf
->skb
, &ah
->txqs
[ah
->bhalq
]);
2009 ath5k_hw_set_txdp(ah
, ah
->bhalq
, bf
->daddr
);
2010 ath5k_hw_start_tx_dma(ah
, ah
->bhalq
);
2011 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2012 ah
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2014 skb
= ieee80211_get_buffered_bc(ah
->hw
, vif
);
2016 ath5k_tx_queue(ah
->hw
, skb
, ah
->cabq
, NULL
);
2018 if (ah
->cabq
->txq_len
>= ah
->cabq
->txq_max
)
2021 skb
= ieee80211_get_buffered_bc(ah
->hw
, vif
);
2028 * ath5k_beacon_update_timers - update beacon timers
2030 * @ah: struct ath5k_hw pointer we are operating on
2031 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2032 * beacon timer update based on the current HW TSF.
2034 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2035 * of a received beacon or the current local hardware TSF and write it to the
2036 * beacon timer registers.
2038 * This is called in a variety of situations, e.g. when a beacon is received,
2039 * when a TSF update has been detected, but also when an new IBSS is created or
2040 * when we otherwise know we have to update the timers, but we keep it in this
2041 * function to have it all together in one place.
2044 ath5k_beacon_update_timers(struct ath5k_hw
*ah
, u64 bc_tsf
)
2046 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2049 intval
= ah
->bintval
& AR5K_BEACON_PERIOD
;
2050 if (ah
->opmode
== NL80211_IFTYPE_AP
&& ah
->num_ap_vifs
2051 + ah
->num_mesh_vifs
> 1) {
2052 intval
/= ATH_BCBUF
; /* staggered multi-bss beacons */
2054 ATH5K_WARN(ah
, "intval %u is too low, min 15\n",
2057 if (WARN_ON(!intval
))
2060 /* beacon TSF converted to TU */
2061 bc_tu
= TSF_TO_TU(bc_tsf
);
2063 /* current TSF converted to TU */
2064 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2065 hw_tu
= TSF_TO_TU(hw_tsf
);
2067 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
2068 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
2069 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
2070 * configuration we need to make sure it is bigger than that. */
2074 * no beacons received, called internally.
2075 * just need to refresh timers based on HW TSF.
2077 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2078 } else if (bc_tsf
== 0) {
2080 * no beacon received, probably called by ath5k_reset_tsf().
2081 * reset TSF to start with 0.
2084 intval
|= AR5K_BEACON_RESET_TSF
;
2085 } else if (bc_tsf
> hw_tsf
) {
2087 * beacon received, SW merge happened but HW TSF not yet updated.
2088 * not possible to reconfigure timers yet, but next time we
2089 * receive a beacon with the same BSSID, the hardware will
2090 * automatically update the TSF and then we need to reconfigure
2093 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2094 "need to wait for HW TSF sync\n");
2098 * most important case for beacon synchronization between STA.
2100 * beacon received and HW TSF has been already updated by HW.
2101 * update next TBTT based on the TSF of the beacon, but make
2102 * sure it is ahead of our local TSF timer.
2104 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2108 ah
->nexttbtt
= nexttbtt
;
2110 intval
|= AR5K_BEACON_ENA
;
2111 ath5k_hw_init_beacon_timers(ah
, nexttbtt
, intval
);
2114 * debugging output last in order to preserve the time critical aspect
2118 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2119 "reconfigured timers based on HW TSF\n");
2120 else if (bc_tsf
== 0)
2121 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2122 "reset HW TSF and timers\n");
2124 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2125 "updated timers based on beacon TSF\n");
2127 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
,
2128 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2129 (unsigned long long) bc_tsf
,
2130 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2131 ATH5K_DBG_UNLIMIT(ah
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2132 intval
& AR5K_BEACON_PERIOD
,
2133 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2134 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2138 * ath5k_beacon_config - Configure the beacon queues and interrupts
2140 * @ah: struct ath5k_hw pointer we are operating on
2142 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2143 * interrupts to detect TSF updates only.
2146 ath5k_beacon_config(struct ath5k_hw
*ah
)
2148 spin_lock_bh(&ah
->block
);
2150 ah
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2152 if (ah
->enable_beacon
) {
2154 * In IBSS mode we use a self-linked tx descriptor and let the
2155 * hardware send the beacons automatically. We have to load it
2157 * We use the SWBA interrupt only to keep track of the beacon
2158 * timers in order to detect automatic TSF updates.
2160 ath5k_beaconq_config(ah
);
2162 ah
->imask
|= AR5K_INT_SWBA
;
2164 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
2165 if (ath5k_hw_hasveol(ah
))
2166 ath5k_beacon_send(ah
);
2168 ath5k_beacon_update_timers(ah
, -1);
2170 ath5k_hw_stop_beacon_queue(ah
, ah
->bhalq
);
2173 ath5k_hw_set_imr(ah
, ah
->imask
);
2175 spin_unlock_bh(&ah
->block
);
2178 static void ath5k_tasklet_beacon(unsigned long data
)
2180 struct ath5k_hw
*ah
= (struct ath5k_hw
*) data
;
2183 * Software beacon alert--time to send a beacon.
2185 * In IBSS mode we use this interrupt just to
2186 * keep track of the next TBTT (target beacon
2187 * transmission time) in order to detect whether
2188 * automatic TSF updates happened.
2190 if (ah
->opmode
== NL80211_IFTYPE_ADHOC
) {
2191 /* XXX: only if VEOL supported */
2192 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2193 ah
->nexttbtt
+= ah
->bintval
;
2194 ATH5K_DBG(ah
, ATH5K_DEBUG_BEACON
,
2195 "SWBA nexttbtt: %x hw_tu: %x "
2199 (unsigned long long) tsf
);
2201 spin_lock(&ah
->block
);
2202 ath5k_beacon_send(ah
);
2203 spin_unlock(&ah
->block
);
2208 /********************\
2209 * Interrupt handling *
2210 \********************/
2213 ath5k_intr_calibration_poll(struct ath5k_hw
*ah
)
2215 if (time_is_before_eq_jiffies(ah
->ah_cal_next_ani
) &&
2216 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
) &&
2217 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)) {
2219 /* Run ANI only when calibration is not active */
2221 ah
->ah_cal_next_ani
= jiffies
+
2222 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2223 tasklet_schedule(&ah
->ani_tasklet
);
2225 } else if (time_is_before_eq_jiffies(ah
->ah_cal_next_short
) &&
2226 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
) &&
2227 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)) {
2229 /* Run calibration only when another calibration
2232 * Note: This is for both full/short calibration,
2233 * if it's time for a full one, ath5k_calibrate_work will deal
2236 ah
->ah_cal_next_short
= jiffies
+
2237 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT
);
2238 ieee80211_queue_work(ah
->hw
, &ah
->calib_work
);
2240 /* we could use SWI to generate enough interrupts to meet our
2241 * calibration interval requirements, if necessary:
2242 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2246 ath5k_schedule_rx(struct ath5k_hw
*ah
)
2248 ah
->rx_pending
= true;
2249 tasklet_schedule(&ah
->rxtq
);
2253 ath5k_schedule_tx(struct ath5k_hw
*ah
)
2255 ah
->tx_pending
= true;
2256 tasklet_schedule(&ah
->txtq
);
2260 ath5k_intr(int irq
, void *dev_id
)
2262 struct ath5k_hw
*ah
= dev_id
;
2263 enum ath5k_int status
;
2264 unsigned int counter
= 1000;
2268 * If hw is not ready (or detached) and we get an
2269 * interrupt, or if we have no interrupts pending
2270 * (that means it's not for us) skip it.
2272 * NOTE: Group 0/1 PCI interface registers are not
2273 * supported on WiSOCs, so we can't check for pending
2274 * interrupts (ISR belongs to another register group
2277 if (unlikely(test_bit(ATH_STAT_INVALID
, ah
->status
) ||
2278 ((ath5k_get_bus_type(ah
) != ATH_AHB
) &&
2279 !ath5k_hw_is_intr_pending(ah
))))
2284 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2286 ATH5K_DBG(ah
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2290 * Fatal hw error -> Log and reset
2292 * Fatal errors are unrecoverable so we have to
2293 * reset the card. These errors include bus and
2296 if (unlikely(status
& AR5K_INT_FATAL
)) {
2298 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2299 "fatal int, resetting\n");
2300 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2303 * RX Overrun -> Count and reset if needed
2305 * Receive buffers are full. Either the bus is busy or
2306 * the CPU is not fast enough to process all received
2309 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2312 * Older chipsets need a reset to come out of this
2313 * condition, but we treat it as RX for newer chips.
2314 * We don't know exactly which versions need a reset
2315 * this guess is copied from the HAL.
2317 ah
->stats
.rxorn_intr
++;
2319 if (ah
->ah_mac_srev
< AR5K_SREV_AR5212
) {
2320 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2321 "rx overrun, resetting\n");
2322 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2324 ath5k_schedule_rx(ah
);
2328 /* Software Beacon Alert -> Schedule beacon tasklet */
2329 if (status
& AR5K_INT_SWBA
)
2330 tasklet_hi_schedule(&ah
->beacontq
);
2333 * No more RX descriptors -> Just count
2335 * NB: the hardware should re-read the link when
2336 * RXE bit is written, but it doesn't work at
2337 * least on older hardware revs.
2339 if (status
& AR5K_INT_RXEOL
)
2340 ah
->stats
.rxeol_intr
++;
2343 /* TX Underrun -> Bump tx trigger level */
2344 if (status
& AR5K_INT_TXURN
)
2345 ath5k_hw_update_tx_triglevel(ah
, true);
2347 /* RX -> Schedule rx tasklet */
2348 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2349 ath5k_schedule_rx(ah
);
2351 /* TX -> Schedule tx tasklet */
2352 if (status
& (AR5K_INT_TXOK
2356 ath5k_schedule_tx(ah
);
2358 /* Missed beacon -> TODO
2359 if (status & AR5K_INT_BMISS)
2362 /* MIB event -> Update counters and notify ANI */
2363 if (status
& AR5K_INT_MIB
) {
2364 ah
->stats
.mib_intr
++;
2365 ath5k_hw_update_mib_counters(ah
);
2366 ath5k_ani_mib_intr(ah
);
2369 /* GPIO -> Notify RFKill layer */
2370 if (status
& AR5K_INT_GPIO
)
2371 tasklet_schedule(&ah
->rf_kill
.toggleq
);
2375 if (ath5k_get_bus_type(ah
) == ATH_AHB
)
2378 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2381 * Until we handle rx/tx interrupts mask them on IMR
2383 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2384 * and unset after we 've handled the interrupts.
2386 if (ah
->rx_pending
|| ah
->tx_pending
)
2387 ath5k_set_current_imask(ah
);
2389 if (unlikely(!counter
))
2390 ATH5K_WARN(ah
, "too many interrupts, giving up for now\n");
2392 /* Fire up calibration poll */
2393 ath5k_intr_calibration_poll(ah
);
2399 * Periodically recalibrate the PHY to account
2400 * for temperature/environment changes.
2403 ath5k_calibrate_work(struct work_struct
*work
)
2405 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2408 /* Should we run a full calibration ? */
2409 if (time_is_before_eq_jiffies(ah
->ah_cal_next_full
)) {
2411 ah
->ah_cal_next_full
= jiffies
+
2412 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2413 ah
->ah_cal_mask
|= AR5K_CALIBRATION_FULL
;
2415 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
,
2416 "running full calibration\n");
2418 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2420 * Rfgain is out of bounds, reset the chip
2421 * to load new gain values.
2423 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2424 "got new rfgain, resetting\n");
2425 ieee80211_queue_work(ah
->hw
, &ah
->reset_work
);
2428 ah
->ah_cal_mask
|= AR5K_CALIBRATION_SHORT
;
2431 ATH5K_DBG(ah
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2432 ieee80211_frequency_to_channel(ah
->curchan
->center_freq
),
2433 ah
->curchan
->hw_value
);
2435 if (ath5k_hw_phy_calibrate(ah
, ah
->curchan
))
2436 ATH5K_ERR(ah
, "calibration of channel %u failed\n",
2437 ieee80211_frequency_to_channel(
2438 ah
->curchan
->center_freq
));
2440 /* Clear calibration flags */
2441 if (ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
)
2442 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_FULL
;
2443 else if (ah
->ah_cal_mask
& AR5K_CALIBRATION_SHORT
)
2444 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_SHORT
;
2449 ath5k_tasklet_ani(unsigned long data
)
2451 struct ath5k_hw
*ah
= (void *)data
;
2453 ah
->ah_cal_mask
|= AR5K_CALIBRATION_ANI
;
2454 ath5k_ani_calibration(ah
);
2455 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_ANI
;
2460 ath5k_tx_complete_poll_work(struct work_struct
*work
)
2462 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2463 tx_complete_work
.work
);
2464 struct ath5k_txq
*txq
;
2466 bool needreset
= false;
2468 if (!test_bit(ATH_STAT_STARTED
, ah
->status
))
2471 mutex_lock(&ah
->lock
);
2473 for (i
= 0; i
< ARRAY_SIZE(ah
->txqs
); i
++) {
2474 if (ah
->txqs
[i
].setup
) {
2476 spin_lock_bh(&txq
->lock
);
2477 if (txq
->txq_len
> 1) {
2478 if (txq
->txq_poll_mark
) {
2479 ATH5K_DBG(ah
, ATH5K_DEBUG_XMIT
,
2480 "TX queue stuck %d\n",
2484 spin_unlock_bh(&txq
->lock
);
2487 txq
->txq_poll_mark
= true;
2490 spin_unlock_bh(&txq
->lock
);
2495 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2496 "TX queues stuck, resetting\n");
2497 ath5k_reset(ah
, NULL
, true);
2500 mutex_unlock(&ah
->lock
);
2502 ieee80211_queue_delayed_work(ah
->hw
, &ah
->tx_complete_work
,
2503 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2507 /*************************\
2508 * Initialization routines *
2509 \*************************/
2511 static const struct ieee80211_iface_limit if_limits
[] = {
2512 { .max
= 2048, .types
= BIT(NL80211_IFTYPE_STATION
) },
2513 { .max
= 4, .types
=
2514 #ifdef CONFIG_MAC80211_MESH
2515 BIT(NL80211_IFTYPE_MESH_POINT
) |
2517 BIT(NL80211_IFTYPE_AP
) },
2520 static const struct ieee80211_iface_combination if_comb
= {
2521 .limits
= if_limits
,
2522 .n_limits
= ARRAY_SIZE(if_limits
),
2523 .max_interfaces
= 2048,
2524 .num_different_channels
= 1,
2528 ath5k_init_ah(struct ath5k_hw
*ah
, const struct ath_bus_ops
*bus_ops
)
2530 struct ieee80211_hw
*hw
= ah
->hw
;
2531 struct ath_common
*common
;
2535 /* Initialize driver private data */
2536 SET_IEEE80211_DEV(hw
, ah
->dev
);
2537 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
2538 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2539 IEEE80211_HW_SIGNAL_DBM
|
2540 IEEE80211_HW_MFP_CAPABLE
|
2541 IEEE80211_HW_REPORTS_TX_ACK_STATUS
|
2542 IEEE80211_HW_SUPPORTS_RC_TABLE
;
2544 hw
->wiphy
->interface_modes
=
2545 BIT(NL80211_IFTYPE_AP
) |
2546 BIT(NL80211_IFTYPE_STATION
) |
2547 BIT(NL80211_IFTYPE_ADHOC
) |
2548 BIT(NL80211_IFTYPE_MESH_POINT
);
2550 hw
->wiphy
->iface_combinations
= &if_comb
;
2551 hw
->wiphy
->n_iface_combinations
= 1;
2553 /* SW support for IBSS_RSN is provided by mac80211 */
2554 hw
->wiphy
->flags
|= WIPHY_FLAG_IBSS_RSN
;
2556 hw
->wiphy
->flags
|= WIPHY_FLAG_SUPPORTS_5_10_MHZ
;
2558 /* both antennas can be configured as RX or TX */
2559 hw
->wiphy
->available_antennas_tx
= 0x3;
2560 hw
->wiphy
->available_antennas_rx
= 0x3;
2562 hw
->extra_tx_headroom
= 2;
2565 * Mark the device as detached to avoid processing
2566 * interrupts until setup is complete.
2568 __set_bit(ATH_STAT_INVALID
, ah
->status
);
2570 ah
->opmode
= NL80211_IFTYPE_STATION
;
2572 mutex_init(&ah
->lock
);
2573 spin_lock_init(&ah
->rxbuflock
);
2574 spin_lock_init(&ah
->txbuflock
);
2575 spin_lock_init(&ah
->block
);
2576 spin_lock_init(&ah
->irqlock
);
2578 /* Setup interrupt handler */
2579 ret
= request_irq(ah
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", ah
);
2581 ATH5K_ERR(ah
, "request_irq failed\n");
2585 common
= ath5k_hw_common(ah
);
2586 common
->ops
= &ath5k_common_ops
;
2587 common
->bus_ops
= bus_ops
;
2591 common
->clockrate
= 40;
2594 * Cache line size is used to size and align various
2595 * structures used to communicate with the hardware.
2597 ath5k_read_cachesize(common
, &csz
);
2598 common
->cachelsz
= csz
<< 2; /* convert to bytes */
2600 spin_lock_init(&common
->cc_lock
);
2602 /* Initialize device */
2603 ret
= ath5k_hw_init(ah
);
2607 /* Set up multi-rate retry capabilities */
2608 if (ah
->ah_capabilities
.cap_has_mrr_support
) {
2610 hw
->max_rate_tries
= max(AR5K_INIT_RETRY_SHORT
,
2611 AR5K_INIT_RETRY_LONG
);
2614 hw
->vif_data_size
= sizeof(struct ath5k_vif
);
2616 /* Finish private driver data initialization */
2617 ret
= ath5k_init(hw
);
2621 ATH5K_INFO(ah
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2622 ath5k_chip_name(AR5K_VERSION_MAC
, ah
->ah_mac_srev
),
2624 ah
->ah_phy_revision
);
2626 if (!ah
->ah_single_chip
) {
2627 /* Single chip radio (!RF5111) */
2628 if (ah
->ah_radio_5ghz_revision
&&
2629 !ah
->ah_radio_2ghz_revision
) {
2630 /* No 5GHz support -> report 2GHz radio */
2631 if (!test_bit(AR5K_MODE_11A
,
2632 ah
->ah_capabilities
.cap_mode
)) {
2633 ATH5K_INFO(ah
, "RF%s 2GHz radio found (0x%x)\n",
2634 ath5k_chip_name(AR5K_VERSION_RAD
,
2635 ah
->ah_radio_5ghz_revision
),
2636 ah
->ah_radio_5ghz_revision
);
2637 /* No 2GHz support (5110 and some
2638 * 5GHz only cards) -> report 5GHz radio */
2639 } else if (!test_bit(AR5K_MODE_11B
,
2640 ah
->ah_capabilities
.cap_mode
)) {
2641 ATH5K_INFO(ah
, "RF%s 5GHz radio found (0x%x)\n",
2642 ath5k_chip_name(AR5K_VERSION_RAD
,
2643 ah
->ah_radio_5ghz_revision
),
2644 ah
->ah_radio_5ghz_revision
);
2645 /* Multiband radio */
2647 ATH5K_INFO(ah
, "RF%s multiband radio found"
2649 ath5k_chip_name(AR5K_VERSION_RAD
,
2650 ah
->ah_radio_5ghz_revision
),
2651 ah
->ah_radio_5ghz_revision
);
2654 /* Multi chip radio (RF5111 - RF2111) ->
2655 * report both 2GHz/5GHz radios */
2656 else if (ah
->ah_radio_5ghz_revision
&&
2657 ah
->ah_radio_2ghz_revision
) {
2658 ATH5K_INFO(ah
, "RF%s 5GHz radio found (0x%x)\n",
2659 ath5k_chip_name(AR5K_VERSION_RAD
,
2660 ah
->ah_radio_5ghz_revision
),
2661 ah
->ah_radio_5ghz_revision
);
2662 ATH5K_INFO(ah
, "RF%s 2GHz radio found (0x%x)\n",
2663 ath5k_chip_name(AR5K_VERSION_RAD
,
2664 ah
->ah_radio_2ghz_revision
),
2665 ah
->ah_radio_2ghz_revision
);
2669 ath5k_debug_init_device(ah
);
2671 /* ready to process interrupts */
2672 __clear_bit(ATH_STAT_INVALID
, ah
->status
);
2676 ath5k_hw_deinit(ah
);
2678 free_irq(ah
->irq
, ah
);
2684 ath5k_stop_locked(struct ath5k_hw
*ah
)
2687 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2688 test_bit(ATH_STAT_INVALID
, ah
->status
));
2691 * Shutdown the hardware and driver:
2692 * stop output from above
2693 * disable interrupts
2695 * turn off the radio
2696 * clear transmit machinery
2697 * clear receive machinery
2698 * drain and release tx queues
2699 * reclaim beacon resources
2700 * power down hardware
2702 * Note that some of this work is not possible if the
2703 * hardware is gone (invalid).
2705 ieee80211_stop_queues(ah
->hw
);
2707 if (!test_bit(ATH_STAT_INVALID
, ah
->status
)) {
2709 ath5k_hw_set_imr(ah
, 0);
2710 synchronize_irq(ah
->irq
);
2712 ath5k_hw_dma_stop(ah
);
2713 ath5k_drain_tx_buffs(ah
);
2714 ath5k_hw_phy_disable(ah
);
2720 int ath5k_start(struct ieee80211_hw
*hw
)
2722 struct ath5k_hw
*ah
= hw
->priv
;
2723 struct ath_common
*common
= ath5k_hw_common(ah
);
2726 mutex_lock(&ah
->lock
);
2728 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "mode %d\n", ah
->opmode
);
2731 * Stop anything previously setup. This is safe
2732 * no matter this is the first time through or not.
2734 ath5k_stop_locked(ah
);
2737 * The basic interface to setting the hardware in a good
2738 * state is ``reset''. On return the hardware is known to
2739 * be powered up and with interrupts disabled. This must
2740 * be followed by initialization of the appropriate bits
2741 * and then setup of the interrupt mask.
2743 ah
->curchan
= ah
->hw
->conf
.chandef
.chan
;
2744 ah
->imask
= AR5K_INT_RXOK
2754 ret
= ath5k_reset(ah
, NULL
, false);
2758 if (!ath5k_modparam_no_hw_rfkill_switch
)
2759 ath5k_rfkill_hw_start(ah
);
2762 * Reset the key cache since some parts do not reset the
2763 * contents on initial power up or resume from suspend.
2765 for (i
= 0; i
< common
->keymax
; i
++)
2766 ath_hw_keyreset(common
, (u16
) i
);
2768 /* Use higher rates for acks instead of base
2770 ah
->ah_ack_bitrate_high
= true;
2772 for (i
= 0; i
< ARRAY_SIZE(ah
->bslot
); i
++)
2773 ah
->bslot
[i
] = NULL
;
2778 mutex_unlock(&ah
->lock
);
2780 set_bit(ATH_STAT_STARTED
, ah
->status
);
2781 ieee80211_queue_delayed_work(ah
->hw
, &ah
->tx_complete_work
,
2782 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2787 static void ath5k_stop_tasklets(struct ath5k_hw
*ah
)
2789 ah
->rx_pending
= false;
2790 ah
->tx_pending
= false;
2791 tasklet_kill(&ah
->rxtq
);
2792 tasklet_kill(&ah
->txtq
);
2793 tasklet_kill(&ah
->beacontq
);
2794 tasklet_kill(&ah
->ani_tasklet
);
2798 * Stop the device, grabbing the top-level lock to protect
2799 * against concurrent entry through ath5k_init (which can happen
2800 * if another thread does a system call and the thread doing the
2801 * stop is preempted).
2803 void ath5k_stop(struct ieee80211_hw
*hw
)
2805 struct ath5k_hw
*ah
= hw
->priv
;
2808 mutex_lock(&ah
->lock
);
2809 ret
= ath5k_stop_locked(ah
);
2810 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, ah
->status
)) {
2812 * Don't set the card in full sleep mode!
2814 * a) When the device is in this state it must be carefully
2815 * woken up or references to registers in the PCI clock
2816 * domain may freeze the bus (and system). This varies
2817 * by chip and is mostly an issue with newer parts
2818 * (madwifi sources mentioned srev >= 0x78) that go to
2819 * sleep more quickly.
2821 * b) On older chips full sleep results a weird behaviour
2822 * during wakeup. I tested various cards with srev < 0x78
2823 * and they don't wake up after module reload, a second
2824 * module reload is needed to bring the card up again.
2826 * Until we figure out what's going on don't enable
2827 * full chip reset on any chip (this is what Legacy HAL
2828 * and Sam's HAL do anyway). Instead Perform a full reset
2829 * on the device (same as initial state after attach) and
2830 * leave it idle (keep MAC/BB on warm reset) */
2831 ret
= ath5k_hw_on_hold(ah
);
2833 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2834 "putting device to sleep\n");
2838 mutex_unlock(&ah
->lock
);
2840 ath5k_stop_tasklets(ah
);
2842 clear_bit(ATH_STAT_STARTED
, ah
->status
);
2843 cancel_delayed_work_sync(&ah
->tx_complete_work
);
2845 if (!ath5k_modparam_no_hw_rfkill_switch
)
2846 ath5k_rfkill_hw_stop(ah
);
2850 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2851 * and change to the given channel.
2853 * This should be called with ah->lock.
2856 ath5k_reset(struct ath5k_hw
*ah
, struct ieee80211_channel
*chan
,
2859 struct ath_common
*common
= ath5k_hw_common(ah
);
2861 bool fast
= chan
&& modparam_fastchanswitch
? 1 : 0;
2863 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
, "resetting\n");
2865 ath5k_hw_set_imr(ah
, 0);
2866 synchronize_irq(ah
->irq
);
2867 ath5k_stop_tasklets(ah
);
2869 /* Save ani mode and disable ANI during
2870 * reset. If we don't we might get false
2871 * PHY error interrupts. */
2872 ani_mode
= ah
->ani_state
.ani_mode
;
2873 ath5k_ani_init(ah
, ATH5K_ANI_MODE_OFF
);
2875 /* We are going to empty hw queues
2876 * so we should also free any remaining
2878 ath5k_drain_tx_buffs(ah
);
2881 ath5k_hw_stop_rx_pcu(ah
);
2885 * Note: If DMA didn't stop continue
2886 * since only a reset will fix it.
2888 ret
= ath5k_hw_dma_stop(ah
);
2890 /* RF Bus grant won't work if we have pending
2894 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
2895 "DMA didn't stop, falling back to normal reset\n");
2902 ret
= ath5k_hw_reset(ah
, ah
->opmode
, ah
->curchan
, fast
, skip_pcu
);
2904 ATH5K_ERR(ah
, "can't reset hardware (%d)\n", ret
);
2908 ret
= ath5k_rx_start(ah
);
2910 ATH5K_ERR(ah
, "can't start recv logic\n");
2914 ath5k_ani_init(ah
, ani_mode
);
2917 * Set calibration intervals
2919 * Note: We don't need to run calibration imediately
2920 * since some initial calibration is done on reset
2921 * even for fast channel switching. Also on scanning
2922 * this will get set again and again and it won't get
2923 * executed unless we connect somewhere and spend some
2924 * time on the channel (that's what calibration needs
2925 * anyway to be accurate).
2927 ah
->ah_cal_next_full
= jiffies
+
2928 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2929 ah
->ah_cal_next_ani
= jiffies
+
2930 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2931 ah
->ah_cal_next_short
= jiffies
+
2932 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT
);
2934 ewma_init(&ah
->ah_beacon_rssi_avg
, 1024, 8);
2936 /* clear survey data and cycle counters */
2937 memset(&ah
->survey
, 0, sizeof(ah
->survey
));
2938 spin_lock_bh(&common
->cc_lock
);
2939 ath_hw_cycle_counters_update(common
);
2940 memset(&common
->cc_survey
, 0, sizeof(common
->cc_survey
));
2941 memset(&common
->cc_ani
, 0, sizeof(common
->cc_ani
));
2942 spin_unlock_bh(&common
->cc_lock
);
2945 * Change channels and update the h/w rate map if we're switching;
2946 * e.g. 11a to 11b/g.
2948 * We may be doing a reset in response to an ioctl that changes the
2949 * channel so update any state that might change as a result.
2953 /* ath5k_chan_change(ah, c); */
2955 ath5k_beacon_config(ah
);
2956 /* intrs are enabled by ath5k_beacon_config */
2958 ieee80211_wake_queues(ah
->hw
);
2965 static void ath5k_reset_work(struct work_struct
*work
)
2967 struct ath5k_hw
*ah
= container_of(work
, struct ath5k_hw
,
2970 mutex_lock(&ah
->lock
);
2971 ath5k_reset(ah
, NULL
, true);
2972 mutex_unlock(&ah
->lock
);
2976 ath5k_init(struct ieee80211_hw
*hw
)
2979 struct ath5k_hw
*ah
= hw
->priv
;
2980 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2981 struct ath5k_txq
*txq
;
2982 u8 mac
[ETH_ALEN
] = {};
2987 * Collect the channel list. The 802.11 layer
2988 * is responsible for filtering this list based
2989 * on settings like the phy mode and regulatory
2990 * domain restrictions.
2992 ret
= ath5k_setup_bands(hw
);
2994 ATH5K_ERR(ah
, "can't get channels\n");
2999 * Allocate tx+rx descriptors and populate the lists.
3001 ret
= ath5k_desc_alloc(ah
);
3003 ATH5K_ERR(ah
, "can't allocate descriptors\n");
3008 * Allocate hardware transmit queues: one queue for
3009 * beacon frames and one data queue for each QoS
3010 * priority. Note that hw functions handle resetting
3011 * these queues at the needed time.
3013 ret
= ath5k_beaconq_setup(ah
);
3015 ATH5K_ERR(ah
, "can't setup a beacon xmit queue\n");
3019 ah
->cabq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_CAB
, 0);
3020 if (IS_ERR(ah
->cabq
)) {
3021 ATH5K_ERR(ah
, "can't setup cab queue\n");
3022 ret
= PTR_ERR(ah
->cabq
);
3026 /* 5211 and 5212 usually support 10 queues but we better rely on the
3027 * capability information */
3028 if (ah
->ah_capabilities
.cap_queues
.q_tx_num
>= 6) {
3029 /* This order matches mac80211's queue priority, so we can
3030 * directly use the mac80211 queue number without any mapping */
3031 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VO
);
3033 ATH5K_ERR(ah
, "can't setup xmit queue\n");
3037 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VI
);
3039 ATH5K_ERR(ah
, "can't setup xmit queue\n");
3043 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
3045 ATH5K_ERR(ah
, "can't setup xmit queue\n");
3049 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
3051 ATH5K_ERR(ah
, "can't setup xmit queue\n");
3057 /* older hardware (5210) can only support one data queue */
3058 txq
= ath5k_txq_setup(ah
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
3060 ATH5K_ERR(ah
, "can't setup xmit queue\n");
3067 tasklet_init(&ah
->rxtq
, ath5k_tasklet_rx
, (unsigned long)ah
);
3068 tasklet_init(&ah
->txtq
, ath5k_tasklet_tx
, (unsigned long)ah
);
3069 tasklet_init(&ah
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)ah
);
3070 tasklet_init(&ah
->ani_tasklet
, ath5k_tasklet_ani
, (unsigned long)ah
);
3072 INIT_WORK(&ah
->reset_work
, ath5k_reset_work
);
3073 INIT_WORK(&ah
->calib_work
, ath5k_calibrate_work
);
3074 INIT_DELAYED_WORK(&ah
->tx_complete_work
, ath5k_tx_complete_poll_work
);
3076 ret
= ath5k_hw_common(ah
)->bus_ops
->eeprom_read_mac(ah
, mac
);
3078 ATH5K_ERR(ah
, "unable to read address from EEPROM\n");
3082 SET_IEEE80211_PERM_ADDR(hw
, mac
);
3083 /* All MAC address bits matter for ACKs */
3084 ath5k_update_bssid_mask_and_opmode(ah
, NULL
);
3086 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
3087 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
3089 ATH5K_ERR(ah
, "can't initialize regulatory system\n");
3093 ret
= ieee80211_register_hw(hw
);
3095 ATH5K_ERR(ah
, "can't register ieee80211 hw\n");
3099 if (!ath_is_world_regd(regulatory
))
3100 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
3102 ath5k_init_leds(ah
);
3104 ath5k_sysfs_register(ah
);
3108 ath5k_txq_release(ah
);
3110 ath5k_hw_release_tx_queue(ah
, ah
->bhalq
);
3112 ath5k_desc_free(ah
);
3118 ath5k_deinit_ah(struct ath5k_hw
*ah
)
3120 struct ieee80211_hw
*hw
= ah
->hw
;
3123 * NB: the order of these is important:
3124 * o call the 802.11 layer before detaching ath5k_hw to
3125 * ensure callbacks into the driver to delete global
3126 * key cache entries can be handled
3127 * o reclaim the tx queue data structures after calling
3128 * the 802.11 layer as we'll get called back to reclaim
3129 * node state and potentially want to use them
3130 * o to cleanup the tx queues the hal is called, so detach
3132 * XXX: ??? detach ath5k_hw ???
3133 * Other than that, it's straightforward...
3135 ieee80211_unregister_hw(hw
);
3136 ath5k_desc_free(ah
);
3137 ath5k_txq_release(ah
);
3138 ath5k_hw_release_tx_queue(ah
, ah
->bhalq
);
3139 ath5k_unregister_leds(ah
);
3141 ath5k_sysfs_unregister(ah
);
3143 * NB: can't reclaim these until after ieee80211_ifdetach
3144 * returns because we'll get called back to reclaim node
3145 * state and potentially want to use them.
3147 ath5k_hw_deinit(ah
);
3148 free_irq(ah
->irq
, ah
);
3152 ath5k_any_vif_assoc(struct ath5k_hw
*ah
)
3154 struct ath5k_vif_iter_data iter_data
;
3155 iter_data
.hw_macaddr
= NULL
;
3156 iter_data
.any_assoc
= false;
3157 iter_data
.need_set_hw_addr
= false;
3158 iter_data
.found_active
= true;
3160 ieee80211_iterate_active_interfaces_atomic(
3161 ah
->hw
, IEEE80211_IFACE_ITER_RESUME_ALL
,
3162 ath5k_vif_iter
, &iter_data
);
3163 return iter_data
.any_assoc
;
3167 ath5k_set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3169 struct ath5k_hw
*ah
= hw
->priv
;
3171 rfilt
= ath5k_hw_get_rx_filter(ah
);
3173 rfilt
|= AR5K_RX_FILTER_BEACON
;
3175 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3176 ath5k_hw_set_rx_filter(ah
, rfilt
);
3177 ah
->filter_flags
= rfilt
;
3180 void _ath5k_printk(const struct ath5k_hw
*ah
, const char *level
,
3181 const char *fmt
, ...)
3183 struct va_format vaf
;
3186 va_start(args
, fmt
);
3192 printk("%s" pr_fmt("%s: %pV"),
3193 level
, wiphy_name(ah
->hw
->wiphy
), &vaf
);
3195 printk("%s" pr_fmt("%pV"), level
, &vaf
);