drivers/net/wireless/ath/ath5k/base.h

   1 /*-
   2  * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  * 3. Neither the names of the above-listed copyright holders nor the names
  16  *    of any contributors may be used to endorse or promote products derived
  17  *    from this software without specific prior written permission.
  18  *
  19  * Alternatively, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") version 2 as published by the Free
  21  * Software Foundation.
  22  *
  23  * NO WARRANTY
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  27  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  28  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  29  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  32  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  34  * THE POSSIBILITY OF SUCH DAMAGES.
  35  *
  36  */
  37
  38 /*
  39  * Defintions for the Atheros Wireless LAN controller driver.
  40  */
  41 #ifndef _DEV_ATH_ATHVAR_H
  42 #define _DEV_ATH_ATHVAR_H
  43
  44 #include <linux/interrupt.h>
  45 #include <linux/list.h>
  46 #include <linux/wireless.h>
  47 #include <linux/if_ether.h>
  48 #include <linux/leds.h>
  49 #include <linux/rfkill.h>
  50
  51 #include "ath5k.h"
  52 #include "debug.h"
  53
  54 #include "../regd.h"
  55 #include "../ath.h"
  56
  57 #define ATH_RXBUF       40              /* number of RX buffers */
  58 #define ATH_TXBUF       200             /* number of TX buffers */
  59 #define ATH_BCBUF       1               /* number of beacon buffers */
  60
  61 struct ath5k_buf {
  62         struct list_head        list;
  63         struct ath5k_desc       *desc;  /* virtual addr of desc */
  64         dma_addr_t              daddr;  /* physical addr of desc */
  65         struct sk_buff          *skb;   /* skbuff for buf */
  66         dma_addr_t              skbaddr;/* physical addr of skb data */
  67 };
  68
  69 /*
  70  * Data transmit queue state.  One of these exists for each
  71  * hardware transmit queue.  Packets sent to us from above
  72  * are assigned to queues based on their priority.  Not all
  73  * devices support a complete set of hardware transmit queues.
  74  * For those devices the array sc_ac2q will map multiple
  75  * priorities to fewer hardware queues (typically all to one
  76  * hardware queue).
  77  */
  78 struct ath5k_txq {
  79         unsigned int            qnum;   /* hardware q number */
  80         u32                     *link;  /* link ptr in last TX desc */
  81         struct list_head        q;      /* transmit queue */
  82         spinlock_t              lock;   /* lock on q and link */
  83         bool                    setup;
  84 };
  85
  86 #define ATH5K_LED_MAX_NAME_LEN 31
  87
  88 /*
  89  * State for LED triggers
  90  */
  91 struct ath5k_led
  92 {
  93         char name[ATH5K_LED_MAX_NAME_LEN + 1];  /* name of the LED in sysfs */
  94         struct ath5k_softc *sc;                 /* driver state */
  95         struct led_classdev led_dev;            /* led classdev */
  96 };
  97
  98 /* Rfkill */
  99 struct ath5k_rfkill {
 100         /* GPIO PIN for rfkill */
 101         u16 gpio;
 102         /* polarity of rfkill GPIO PIN */
 103         bool polarity;
 104         /* RFKILL toggle tasklet */
 105         struct tasklet_struct toggleq;
 106 };
 107
 108 #if CHAN_DEBUG
 109 #define ATH_CHAN_MAX    (26+26+26+200+200)
 110 #else
 111 #define ATH_CHAN_MAX    (14+14+14+252+20)
 112 #endif
 113
 114 /* Software Carrier, keeps track of the driver state
 115  * associated with an instance of a device */
 116 struct ath5k_softc {
 117         struct pci_dev          *pdev;          /* for dma mapping */
 118         struct ath_common       common;
 119         void __iomem            *iobase;        /* address of the device */
 120         struct mutex            lock;           /* dev-level lock */
 121         struct ieee80211_tx_queue_stats tx_stats[AR5K_NUM_TX_QUEUES];
 122         struct ieee80211_low_level_stats ll_stats;
 123         struct ieee80211_hw     *hw;            /* IEEE 802.11 common */
 124         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 125         struct ieee80211_channel channels[ATH_CHAN_MAX];
 126         struct ieee80211_rate   rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
 127         s8                      rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
 128         enum nl80211_iftype     opmode;
 129         struct ath5k_hw         *ah;            /* Atheros HW */
 130
 131         struct ieee80211_supported_band         *curband;
 132
 133 #ifdef CONFIG_ATH5K_DEBUG
 134         struct ath5k_dbg_info   debug;          /* debug info */
 135 #endif /* CONFIG_ATH5K_DEBUG */
 136
 137         struct ath5k_buf        *bufptr;        /* allocated buffer ptr */
 138         struct ath5k_desc       *desc;          /* TX/RX descriptors */
 139         dma_addr_t              desc_daddr;     /* DMA (physical) address */
 140         size_t                  desc_len;       /* size of TX/RX descriptors */
 141
 142         DECLARE_BITMAP(status, 5);
 143 #define ATH_STAT_INVALID        0               /* disable hardware accesses */
 144 #define ATH_STAT_MRRETRY        1               /* multi-rate retry support */
 145 #define ATH_STAT_PROMISC        2
 146 #define ATH_STAT_LEDSOFT        3               /* enable LED gpio status */
 147 #define ATH_STAT_STARTED        4               /* opened & irqs enabled */
 148
 149         unsigned int            filter_flags;   /* HW flags, AR5K_RX_FILTER_* */
 150         unsigned int            curmode;        /* current phy mode */
 151         struct ieee80211_channel *curchan;      /* current h/w channel */
 152
 153         struct ieee80211_vif *vif;
 154
 155         enum ath5k_int          imask;          /* interrupt mask copy */
 156
 157         DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */
 158
 159         u8                      bssidmask[ETH_ALEN];
 160
 161         unsigned int            led_pin,        /* GPIO pin for driving LED */
 162                                 led_on;         /* pin setting for LED on */
 163
 164         struct tasklet_struct   restq;          /* reset tasklet */
 165
 166         unsigned int            rxbufsize;      /* rx size based on mtu */
 167         struct list_head        rxbuf;          /* receive buffer */
 168         spinlock_t              rxbuflock;
 169         u32                     *rxlink;        /* link ptr in last RX desc */
 170         struct tasklet_struct   rxtq;           /* rx intr tasklet */
 171         struct ath5k_led        rx_led;         /* rx led */
 172
 173         struct list_head        txbuf;          /* transmit buffer */
 174         spinlock_t              txbuflock;
 175         unsigned int            txbuf_len;      /* buf count in txbuf list */
 176         struct ath5k_txq        txqs[AR5K_NUM_TX_QUEUES];       /* tx queues */
 177         struct ath5k_txq        *txq;           /* main tx queue */
 178         struct tasklet_struct   txtq;           /* tx intr tasklet */
 179         struct ath5k_led        tx_led;         /* tx led */
 180
 181         struct ath5k_rfkill     rf_kill;
 182
 183         struct tasklet_struct   calib;          /* calibration tasklet */
 184
 185         spinlock_t              block;          /* protects beacon */
 186         struct tasklet_struct   beacontq;       /* beacon intr tasklet */
 187         struct ath5k_buf        *bbuf;          /* beacon buffer */
 188         unsigned int            bhalq,          /* SW q for outgoing beacons */
 189                                 bmisscount,     /* missed beacon transmits */
 190                                 bintval,        /* beacon interval in TU */
 191                                 bsent;
 192         unsigned int            nexttbtt;       /* next beacon time in TU */
 193         struct ath5k_txq        *cabq;          /* content after beacon */
 194
 195         int                     power_level;    /* Requested tx power in dbm */
 196         bool                    assoc;          /* associate state */
 197         bool                    enable_beacon;  /* true if beacons are on */
 198 };
 199
 200 #define ath5k_hw_hasbssidmask(_ah) \
 201         (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
 202 #define ath5k_hw_hasveol(_ah) \
 203         (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
 204
 205 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
 206 {
 207         return &ah->ah_sc->common;
 208 }
 209
 210 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
 211 {
 212         return &(ath5k_hw_common(ah)->regulatory);
 213
 214 }
 215
 216 #endif