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ath5k: Add new field on ath5k_hw to track bandwidth modes
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath5k / phy.c
1 /*
2 * PHY functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25
26 #include "ath5k.h"
27 #include "reg.h"
28 #include "base.h"
29 #include "rfbuffer.h"
30 #include "rfgain.h"
31
32
33 /******************\
34 * Helper functions *
35 \******************/
36
37 /*
38 * Get the PHY Chip revision
39 */
40 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
41 {
42 unsigned int i;
43 u32 srev;
44 u16 ret;
45
46 /*
47 * Set the radio chip access register
48 */
49 switch (chan) {
50 case CHANNEL_2GHZ:
51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
52 break;
53 case CHANNEL_5GHZ:
54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
55 break;
56 default:
57 return 0;
58 }
59
60 mdelay(2);
61
62 /* ...wait until PHY is ready and read the selected radio revision */
63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
64
65 for (i = 0; i < 8; i++)
66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
67
68 if (ah->ah_version == AR5K_AR5210) {
69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
71 } else {
72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
74 ((srev & 0x0f) << 4), 8);
75 }
76
77 /* Reset to the 5GHz mode */
78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
79
80 return ret;
81 }
82
83 /*
84 * Check if a channel is supported
85 */
86 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
87 {
88 /* Check if the channel is in our supported range */
89 if (flags & CHANNEL_2GHZ) {
90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
92 return true;
93 } else if (flags & CHANNEL_5GHZ)
94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
96 return true;
97
98 return false;
99 }
100
101 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
102 struct ieee80211_channel *channel)
103 {
104 u8 refclk_freq;
105
106 if ((ah->ah_radio == AR5K_RF5112) ||
107 (ah->ah_radio == AR5K_RF5413) ||
108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
109 refclk_freq = 40;
110 else
111 refclk_freq = 32;
112
113 if ((channel->center_freq % refclk_freq != 0) &&
114 ((channel->center_freq % refclk_freq < 10) ||
115 (channel->center_freq % refclk_freq > 22)))
116 return true;
117 else
118 return false;
119 }
120
121 /*
122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
123 */
124 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
125 const struct ath5k_rf_reg *rf_regs,
126 u32 val, u8 reg_id, bool set)
127 {
128 const struct ath5k_rf_reg *rfreg = NULL;
129 u8 offset, bank, num_bits, col, position;
130 u16 entry;
131 u32 mask, data, last_bit, bits_shifted, first_bit;
132 u32 *rfb;
133 s32 bits_left;
134 int i;
135
136 data = 0;
137 rfb = ah->ah_rf_banks;
138
139 for (i = 0; i < ah->ah_rf_regs_count; i++) {
140 if (rf_regs[i].index == reg_id) {
141 rfreg = &rf_regs[i];
142 break;
143 }
144 }
145
146 if (rfb == NULL || rfreg == NULL) {
147 ATH5K_PRINTF("Rf register not found!\n");
148 /* should not happen */
149 return 0;
150 }
151
152 bank = rfreg->bank;
153 num_bits = rfreg->field.len;
154 first_bit = rfreg->field.pos;
155 col = rfreg->field.col;
156
157 /* first_bit is an offset from bank's
158 * start. Since we have all banks on
159 * the same array, we use this offset
160 * to mark each bank's start */
161 offset = ah->ah_offset[bank];
162
163 /* Boundary check */
164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
165 ATH5K_PRINTF("invalid values at offset %u\n", offset);
166 return 0;
167 }
168
169 entry = ((first_bit - 1) / 8) + offset;
170 position = (first_bit - 1) % 8;
171
172 if (set)
173 data = ath5k_hw_bitswap(val, num_bits);
174
175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
176 position = 0, entry++) {
177
178 last_bit = (position + bits_left > 8) ? 8 :
179 position + bits_left;
180
181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
182 (col * 8);
183
184 if (set) {
185 rfb[entry] &= ~mask;
186 rfb[entry] |= ((data << position) << (col * 8)) & mask;
187 data >>= (8 - position);
188 } else {
189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
190 << bits_shifted;
191 bits_shifted += last_bit - position;
192 }
193
194 bits_left -= 8 - position;
195 }
196
197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
198
199 return data;
200 }
201
202 /**
203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
204 *
205 * @ah: the &struct ath5k_hw
206 * @channel: the currently set channel upon reset
207 *
208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
210 *
211 * Since delta slope is floating point we split it on its exponent and
212 * mantissa and provide these values on hw.
213 *
214 * For more infos i think this patent is related
215 * http://www.freepatentsonline.com/7184495.html
216 */
217 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
218 struct ieee80211_channel *channel)
219 {
220 /* Get exponent and mantissa and set it */
221 u32 coef_scaled, coef_exp, coef_man,
222 ds_coef_exp, ds_coef_man, clock;
223
224 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
225 !(channel->hw_value & CHANNEL_OFDM));
226
227 /* Get coefficient
228 * ALGO: coef = (5 * clock / carrier_freq) / 2
229 * we scale coef by shifting clock value by 24 for
230 * better precision since we use integers */
231 /* TODO: Half/quarter rate */
232 clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40;
233 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
234
235 /* Get exponent
236 * ALGO: coef_exp = 14 - highest set bit position */
237 coef_exp = ilog2(coef_scaled);
238
239 /* Doesn't make sense if it's zero*/
240 if (!coef_scaled || !coef_exp)
241 return -EINVAL;
242
243 /* Note: we've shifted coef_scaled by 24 */
244 coef_exp = 14 - (coef_exp - 24);
245
246
247 /* Get mantissa (significant digits)
248 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
249 coef_man = coef_scaled +
250 (1 << (24 - coef_exp - 1));
251
252 /* Calculate delta slope coefficient exponent
253 * and mantissa (remove scaling) and set them on hw */
254 ds_coef_man = coef_man >> (24 - coef_exp);
255 ds_coef_exp = coef_exp - 16;
256
257 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
258 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
259 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
260 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
261
262 return 0;
263 }
264
265 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
266 {
267 /*Just a try M.F.*/
268 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
269
270 return 0;
271 }
272
273
274 /**********************\
275 * RF Gain optimization *
276 \**********************/
277
278 /*
279 * This code is used to optimize RF gain on different environments
280 * (temperature mostly) based on feedback from a power detector.
281 *
282 * It's only used on RF5111 and RF5112, later RF chips seem to have
283 * auto adjustment on hw -notice they have a much smaller BANK 7 and
284 * no gain optimization ladder-.
285 *
286 * For more infos check out this patent doc
287 * http://www.freepatentsonline.com/7400691.html
288 *
289 * This paper describes power drops as seen on the receiver due to
290 * probe packets
291 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
292 * %20of%20Power%20Control.pdf
293 *
294 * And this is the MadWiFi bug entry related to the above
295 * http://madwifi-project.org/ticket/1659
296 * with various measurements and diagrams
297 *
298 * TODO: Deal with power drops due to probes by setting an apropriate
299 * tx power on the probe packets ! Make this part of the calibration process.
300 */
301
302 /* Initialize ah_gain durring attach */
303 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
304 {
305 /* Initialize the gain optimization values */
306 switch (ah->ah_radio) {
307 case AR5K_RF5111:
308 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
309 ah->ah_gain.g_low = 20;
310 ah->ah_gain.g_high = 35;
311 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
312 break;
313 case AR5K_RF5112:
314 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
315 ah->ah_gain.g_low = 20;
316 ah->ah_gain.g_high = 85;
317 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
318 break;
319 default:
320 return -EINVAL;
321 }
322
323 return 0;
324 }
325
326 /* Schedule a gain probe check on the next transmited packet.
327 * That means our next packet is going to be sent with lower
328 * tx power and a Peak to Average Power Detector (PAPD) will try
329 * to measure the gain.
330 *
331 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
332 * just after we enable the probe so that we don't mess with
333 * standard traffic ? Maybe it's time to use sw interrupts and
334 * a probe tasklet !!!
335 */
336 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
337 {
338
339 /* Skip if gain calibration is inactive or
340 * we already handle a probe request */
341 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
342 return;
343
344 /* Send the packet with 2dB below max power as
345 * patent doc suggest */
346 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
347 AR5K_PHY_PAPD_PROBE_TXPOWER) |
348 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
349
350 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
351
352 }
353
354 /* Calculate gain_F measurement correction
355 * based on the current step for RF5112 rev. 2 */
356 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
357 {
358 u32 mix, step;
359 u32 *rf;
360 const struct ath5k_gain_opt *go;
361 const struct ath5k_gain_opt_step *g_step;
362 const struct ath5k_rf_reg *rf_regs;
363
364 /* Only RF5112 Rev. 2 supports it */
365 if ((ah->ah_radio != AR5K_RF5112) ||
366 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
367 return 0;
368
369 go = &rfgain_opt_5112;
370 rf_regs = rf_regs_5112a;
371 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
372
373 g_step = &go->go_step[ah->ah_gain.g_step_idx];
374
375 if (ah->ah_rf_banks == NULL)
376 return 0;
377
378 rf = ah->ah_rf_banks;
379 ah->ah_gain.g_f_corr = 0;
380
381 /* No VGA (Variable Gain Amplifier) override, skip */
382 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
383 return 0;
384
385 /* Mix gain stepping */
386 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
387
388 /* Mix gain override */
389 mix = g_step->gos_param[0];
390
391 switch (mix) {
392 case 3:
393 ah->ah_gain.g_f_corr = step * 2;
394 break;
395 case 2:
396 ah->ah_gain.g_f_corr = (step - 5) * 2;
397 break;
398 case 1:
399 ah->ah_gain.g_f_corr = step;
400 break;
401 default:
402 ah->ah_gain.g_f_corr = 0;
403 break;
404 }
405
406 return ah->ah_gain.g_f_corr;
407 }
408
409 /* Check if current gain_F measurement is in the range of our
410 * power detector windows. If we get a measurement outside range
411 * we know it's not accurate (detectors can't measure anything outside
412 * their detection window) so we must ignore it */
413 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
414 {
415 const struct ath5k_rf_reg *rf_regs;
416 u32 step, mix_ovr, level[4];
417 u32 *rf;
418
419 if (ah->ah_rf_banks == NULL)
420 return false;
421
422 rf = ah->ah_rf_banks;
423
424 if (ah->ah_radio == AR5K_RF5111) {
425
426 rf_regs = rf_regs_5111;
427 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
428
429 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
430 false);
431
432 level[0] = 0;
433 level[1] = (step == 63) ? 50 : step + 4;
434 level[2] = (step != 63) ? 64 : level[0];
435 level[3] = level[2] + 50 ;
436
437 ah->ah_gain.g_high = level[3] -
438 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
439 ah->ah_gain.g_low = level[0] +
440 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
441 } else {
442
443 rf_regs = rf_regs_5112;
444 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
445
446 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
447 false);
448
449 level[0] = level[2] = 0;
450
451 if (mix_ovr == 1) {
452 level[1] = level[3] = 83;
453 } else {
454 level[1] = level[3] = 107;
455 ah->ah_gain.g_high = 55;
456 }
457 }
458
459 return (ah->ah_gain.g_current >= level[0] &&
460 ah->ah_gain.g_current <= level[1]) ||
461 (ah->ah_gain.g_current >= level[2] &&
462 ah->ah_gain.g_current <= level[3]);
463 }
464
465 /* Perform gain_F adjustment by choosing the right set
466 * of parameters from RF gain optimization ladder */
467 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
468 {
469 const struct ath5k_gain_opt *go;
470 const struct ath5k_gain_opt_step *g_step;
471 int ret = 0;
472
473 switch (ah->ah_radio) {
474 case AR5K_RF5111:
475 go = &rfgain_opt_5111;
476 break;
477 case AR5K_RF5112:
478 go = &rfgain_opt_5112;
479 break;
480 default:
481 return 0;
482 }
483
484 g_step = &go->go_step[ah->ah_gain.g_step_idx];
485
486 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
487
488 /* Reached maximum */
489 if (ah->ah_gain.g_step_idx == 0)
490 return -1;
491
492 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
493 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
494 ah->ah_gain.g_step_idx > 0;
495 g_step = &go->go_step[ah->ah_gain.g_step_idx])
496 ah->ah_gain.g_target -= 2 *
497 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
498 g_step->gos_gain);
499
500 ret = 1;
501 goto done;
502 }
503
504 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
505
506 /* Reached minimum */
507 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
508 return -2;
509
510 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
511 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
512 ah->ah_gain.g_step_idx < go->go_steps_count-1;
513 g_step = &go->go_step[ah->ah_gain.g_step_idx])
514 ah->ah_gain.g_target -= 2 *
515 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
516 g_step->gos_gain);
517
518 ret = 2;
519 goto done;
520 }
521
522 done:
523 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
524 "ret %d, gain step %u, current gain %u, target gain %u\n",
525 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
526 ah->ah_gain.g_target);
527
528 return ret;
529 }
530
531 /* Main callback for thermal RF gain calibration engine
532 * Check for a new gain reading and schedule an adjustment
533 * if needed.
534 *
535 * TODO: Use sw interrupt to schedule reset if gain_F needs
536 * adjustment */
537 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
538 {
539 u32 data, type;
540 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
541
542 if (ah->ah_rf_banks == NULL ||
543 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
544 return AR5K_RFGAIN_INACTIVE;
545
546 /* No check requested, either engine is inactive
547 * or an adjustment is already requested */
548 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
549 goto done;
550
551 /* Read the PAPD (Peak to Average Power Detector)
552 * register */
553 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
554
555 /* No probe is scheduled, read gain_F measurement */
556 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
557 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
558 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
559
560 /* If tx packet is CCK correct the gain_F measurement
561 * by cck ofdm gain delta */
562 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
563 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
564 ah->ah_gain.g_current +=
565 ee->ee_cck_ofdm_gain_delta;
566 else
567 ah->ah_gain.g_current +=
568 AR5K_GAIN_CCK_PROBE_CORR;
569 }
570
571 /* Further correct gain_F measurement for
572 * RF5112A radios */
573 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
574 ath5k_hw_rf_gainf_corr(ah);
575 ah->ah_gain.g_current =
576 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
577 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
578 0;
579 }
580
581 /* Check if measurement is ok and if we need
582 * to adjust gain, schedule a gain adjustment,
583 * else switch back to the acive state */
584 if (ath5k_hw_rf_check_gainf_readback(ah) &&
585 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
586 ath5k_hw_rf_gainf_adjust(ah)) {
587 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
588 } else {
589 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
590 }
591 }
592
593 done:
594 return ah->ah_gain.g_state;
595 }
596
597 /* Write initial RF gain table to set the RF sensitivity
598 * this one works on all RF chips and has nothing to do
599 * with gain_F calibration */
600 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
601 {
602 const struct ath5k_ini_rfgain *ath5k_rfg;
603 unsigned int i, size;
604
605 switch (ah->ah_radio) {
606 case AR5K_RF5111:
607 ath5k_rfg = rfgain_5111;
608 size = ARRAY_SIZE(rfgain_5111);
609 break;
610 case AR5K_RF5112:
611 ath5k_rfg = rfgain_5112;
612 size = ARRAY_SIZE(rfgain_5112);
613 break;
614 case AR5K_RF2413:
615 ath5k_rfg = rfgain_2413;
616 size = ARRAY_SIZE(rfgain_2413);
617 break;
618 case AR5K_RF2316:
619 ath5k_rfg = rfgain_2316;
620 size = ARRAY_SIZE(rfgain_2316);
621 break;
622 case AR5K_RF5413:
623 ath5k_rfg = rfgain_5413;
624 size = ARRAY_SIZE(rfgain_5413);
625 break;
626 case AR5K_RF2317:
627 case AR5K_RF2425:
628 ath5k_rfg = rfgain_2425;
629 size = ARRAY_SIZE(rfgain_2425);
630 break;
631 default:
632 return -EINVAL;
633 }
634
635 switch (freq) {
636 case AR5K_INI_RFGAIN_2GHZ:
637 case AR5K_INI_RFGAIN_5GHZ:
638 break;
639 default:
640 return -EINVAL;
641 }
642
643 for (i = 0; i < size; i++) {
644 AR5K_REG_WAIT(i);
645 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
646 (u32)ath5k_rfg[i].rfg_register);
647 }
648
649 return 0;
650 }
651
652
653
654 /********************\
655 * RF Registers setup *
656 \********************/
657
658 /*
659 * Setup RF registers by writing RF buffer on hw
660 */
661 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
662 struct ieee80211_channel *channel, unsigned int mode)
663 {
664 const struct ath5k_rf_reg *rf_regs;
665 const struct ath5k_ini_rfbuffer *ini_rfb;
666 const struct ath5k_gain_opt *go = NULL;
667 const struct ath5k_gain_opt_step *g_step;
668 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
669 u8 ee_mode = 0;
670 u32 *rfb;
671 int i, obdb = -1, bank = -1;
672
673 switch (ah->ah_radio) {
674 case AR5K_RF5111:
675 rf_regs = rf_regs_5111;
676 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
677 ini_rfb = rfb_5111;
678 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
679 go = &rfgain_opt_5111;
680 break;
681 case AR5K_RF5112:
682 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
683 rf_regs = rf_regs_5112a;
684 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
685 ini_rfb = rfb_5112a;
686 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
687 } else {
688 rf_regs = rf_regs_5112;
689 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
690 ini_rfb = rfb_5112;
691 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
692 }
693 go = &rfgain_opt_5112;
694 break;
695 case AR5K_RF2413:
696 rf_regs = rf_regs_2413;
697 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
698 ini_rfb = rfb_2413;
699 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
700 break;
701 case AR5K_RF2316:
702 rf_regs = rf_regs_2316;
703 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
704 ini_rfb = rfb_2316;
705 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
706 break;
707 case AR5K_RF5413:
708 rf_regs = rf_regs_5413;
709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
710 ini_rfb = rfb_5413;
711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
712 break;
713 case AR5K_RF2317:
714 rf_regs = rf_regs_2425;
715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
716 ini_rfb = rfb_2317;
717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
718 break;
719 case AR5K_RF2425:
720 rf_regs = rf_regs_2425;
721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
722 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
723 ini_rfb = rfb_2425;
724 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
725 } else {
726 ini_rfb = rfb_2417;
727 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
728 }
729 break;
730 default:
731 return -EINVAL;
732 }
733
734 /* If it's the first time we set RF buffer, allocate
735 * ah->ah_rf_banks based on ah->ah_rf_banks_size
736 * we set above */
737 if (ah->ah_rf_banks == NULL) {
738 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
739 GFP_KERNEL);
740 if (ah->ah_rf_banks == NULL) {
741 ATH5K_ERR(ah->ah_sc, "out of memory\n");
742 return -ENOMEM;
743 }
744 }
745
746 /* Copy values to modify them */
747 rfb = ah->ah_rf_banks;
748
749 for (i = 0; i < ah->ah_rf_banks_size; i++) {
750 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
751 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
752 return -EINVAL;
753 }
754
755 /* Bank changed, write down the offset */
756 if (bank != ini_rfb[i].rfb_bank) {
757 bank = ini_rfb[i].rfb_bank;
758 ah->ah_offset[bank] = i;
759 }
760
761 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
762 }
763
764 /* Set Output and Driver bias current (OB/DB) */
765 if (channel->hw_value & CHANNEL_2GHZ) {
766
767 if (channel->hw_value & CHANNEL_CCK)
768 ee_mode = AR5K_EEPROM_MODE_11B;
769 else
770 ee_mode = AR5K_EEPROM_MODE_11G;
771
772 /* For RF511X/RF211X combination we
773 * use b_OB and b_DB parameters stored
774 * in eeprom on ee->ee_ob[ee_mode][0]
775 *
776 * For all other chips we use OB/DB for 2Ghz
777 * stored in the b/g modal section just like
778 * 802.11a on ee->ee_ob[ee_mode][1] */
779 if ((ah->ah_radio == AR5K_RF5111) ||
780 (ah->ah_radio == AR5K_RF5112))
781 obdb = 0;
782 else
783 obdb = 1;
784
785 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
786 AR5K_RF_OB_2GHZ, true);
787
788 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
789 AR5K_RF_DB_2GHZ, true);
790
791 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
792 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
793 (ah->ah_radio == AR5K_RF5111)) {
794
795 /* For 11a, Turbo and XR we need to choose
796 * OB/DB based on frequency range */
797 ee_mode = AR5K_EEPROM_MODE_11A;
798 obdb = channel->center_freq >= 5725 ? 3 :
799 (channel->center_freq >= 5500 ? 2 :
800 (channel->center_freq >= 5260 ? 1 :
801 (channel->center_freq > 4000 ? 0 : -1)));
802
803 if (obdb < 0)
804 return -EINVAL;
805
806 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
807 AR5K_RF_OB_5GHZ, true);
808
809 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
810 AR5K_RF_DB_5GHZ, true);
811 }
812
813 g_step = &go->go_step[ah->ah_gain.g_step_idx];
814
815 /* Bank Modifications (chip-specific) */
816 if (ah->ah_radio == AR5K_RF5111) {
817
818 /* Set gain_F settings according to current step */
819 if (channel->hw_value & CHANNEL_OFDM) {
820
821 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
822 AR5K_PHY_FRAME_CTL_TX_CLIP,
823 g_step->gos_param[0]);
824
825 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
826 AR5K_RF_PWD_90, true);
827
828 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
829 AR5K_RF_PWD_84, true);
830
831 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
832 AR5K_RF_RFGAIN_SEL, true);
833
834 /* We programmed gain_F parameters, switch back
835 * to active state */
836 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
837
838 }
839
840 /* Bank 6/7 setup */
841
842 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
843 AR5K_RF_PWD_XPD, true);
844
845 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
846 AR5K_RF_XPD_GAIN, true);
847
848 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
849 AR5K_RF_GAIN_I, true);
850
851 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
852 AR5K_RF_PLO_SEL, true);
853
854 /* TODO: Half/quarter channel support */
855 }
856
857 if (ah->ah_radio == AR5K_RF5112) {
858
859 /* Set gain_F settings according to current step */
860 if (channel->hw_value & CHANNEL_OFDM) {
861
862 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
863 AR5K_RF_MIXGAIN_OVR, true);
864
865 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
866 AR5K_RF_PWD_138, true);
867
868 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
869 AR5K_RF_PWD_137, true);
870
871 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
872 AR5K_RF_PWD_136, true);
873
874 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
875 AR5K_RF_PWD_132, true);
876
877 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
878 AR5K_RF_PWD_131, true);
879
880 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
881 AR5K_RF_PWD_130, true);
882
883 /* We programmed gain_F parameters, switch back
884 * to active state */
885 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
886 }
887
888 /* Bank 6/7 setup */
889
890 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
891 AR5K_RF_XPD_SEL, true);
892
893 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
894 /* Rev. 1 supports only one xpd */
895 ath5k_hw_rfb_op(ah, rf_regs,
896 ee->ee_x_gain[ee_mode],
897 AR5K_RF_XPD_GAIN, true);
898
899 } else {
900 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
901 if (ee->ee_pd_gains[ee_mode] > 1) {
902 ath5k_hw_rfb_op(ah, rf_regs,
903 pdg_curve_to_idx[0],
904 AR5K_RF_PD_GAIN_LO, true);
905 ath5k_hw_rfb_op(ah, rf_regs,
906 pdg_curve_to_idx[1],
907 AR5K_RF_PD_GAIN_HI, true);
908 } else {
909 ath5k_hw_rfb_op(ah, rf_regs,
910 pdg_curve_to_idx[0],
911 AR5K_RF_PD_GAIN_LO, true);
912 ath5k_hw_rfb_op(ah, rf_regs,
913 pdg_curve_to_idx[0],
914 AR5K_RF_PD_GAIN_HI, true);
915 }
916
917 /* Lower synth voltage on Rev 2 */
918 ath5k_hw_rfb_op(ah, rf_regs, 2,
919 AR5K_RF_HIGH_VC_CP, true);
920
921 ath5k_hw_rfb_op(ah, rf_regs, 2,
922 AR5K_RF_MID_VC_CP, true);
923
924 ath5k_hw_rfb_op(ah, rf_regs, 2,
925 AR5K_RF_LOW_VC_CP, true);
926
927 ath5k_hw_rfb_op(ah, rf_regs, 2,
928 AR5K_RF_PUSH_UP, true);
929
930 /* Decrease power consumption on 5213+ BaseBand */
931 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
932 ath5k_hw_rfb_op(ah, rf_regs, 1,
933 AR5K_RF_PAD2GND, true);
934
935 ath5k_hw_rfb_op(ah, rf_regs, 1,
936 AR5K_RF_XB2_LVL, true);
937
938 ath5k_hw_rfb_op(ah, rf_regs, 1,
939 AR5K_RF_XB5_LVL, true);
940
941 ath5k_hw_rfb_op(ah, rf_regs, 1,
942 AR5K_RF_PWD_167, true);
943
944 ath5k_hw_rfb_op(ah, rf_regs, 1,
945 AR5K_RF_PWD_166, true);
946 }
947 }
948
949 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
950 AR5K_RF_GAIN_I, true);
951
952 /* TODO: Half/quarter channel support */
953
954 }
955
956 if (ah->ah_radio == AR5K_RF5413 &&
957 channel->hw_value & CHANNEL_2GHZ) {
958
959 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
960 true);
961
962 /* Set optimum value for early revisions (on pci-e chips) */
963 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
964 ah->ah_mac_srev < AR5K_SREV_AR5413)
965 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
966 AR5K_RF_PWD_ICLOBUF_2G, true);
967
968 }
969
970 /* Write RF banks on hw */
971 for (i = 0; i < ah->ah_rf_banks_size; i++) {
972 AR5K_REG_WAIT(i);
973 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
974 }
975
976 return 0;
977 }
978
979
980 /**************************\
981 PHY/RF channel functions
982 \**************************/
983
984 /*
985 * Convertion needed for RF5110
986 */
987 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
988 {
989 u32 athchan;
990
991 /*
992 * Convert IEEE channel/MHz to an internal channel value used
993 * by the AR5210 chipset. This has not been verified with
994 * newer chipsets like the AR5212A who have a completely
995 * different RF/PHY part.
996 */
997 athchan = (ath5k_hw_bitswap(
998 (ieee80211_frequency_to_channel(
999 channel->center_freq) - 24) / 2, 5)
1000 << 1) | (1 << 6) | 0x1;
1001 return athchan;
1002 }
1003
1004 /*
1005 * Set channel on RF5110
1006 */
1007 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1008 struct ieee80211_channel *channel)
1009 {
1010 u32 data;
1011
1012 /*
1013 * Set the channel and wait
1014 */
1015 data = ath5k_hw_rf5110_chan2athchan(channel);
1016 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1017 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1018 mdelay(1);
1019
1020 return 0;
1021 }
1022
1023 /*
1024 * Convertion needed for 5111
1025 */
1026 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1027 struct ath5k_athchan_2ghz *athchan)
1028 {
1029 int channel;
1030
1031 /* Cast this value to catch negative channel numbers (>= -19) */
1032 channel = (int)ieee;
1033
1034 /*
1035 * Map 2GHz IEEE channel to 5GHz Atheros channel
1036 */
1037 if (channel <= 13) {
1038 athchan->a2_athchan = 115 + channel;
1039 athchan->a2_flags = 0x46;
1040 } else if (channel == 14) {
1041 athchan->a2_athchan = 124;
1042 athchan->a2_flags = 0x44;
1043 } else if (channel >= 15 && channel <= 26) {
1044 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1045 athchan->a2_flags = 0x46;
1046 } else
1047 return -EINVAL;
1048
1049 return 0;
1050 }
1051
1052 /*
1053 * Set channel on 5111
1054 */
1055 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1056 struct ieee80211_channel *channel)
1057 {
1058 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1059 unsigned int ath5k_channel =
1060 ieee80211_frequency_to_channel(channel->center_freq);
1061 u32 data0, data1, clock;
1062 int ret;
1063
1064 /*
1065 * Set the channel on the RF5111 radio
1066 */
1067 data0 = data1 = 0;
1068
1069 if (channel->hw_value & CHANNEL_2GHZ) {
1070 /* Map 2GHz channel to 5GHz Atheros channel ID */
1071 ret = ath5k_hw_rf5111_chan2athchan(
1072 ieee80211_frequency_to_channel(channel->center_freq),
1073 &ath5k_channel_2ghz);
1074 if (ret)
1075 return ret;
1076
1077 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1078 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1079 << 5) | (1 << 4);
1080 }
1081
1082 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1083 clock = 1;
1084 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1085 (clock << 1) | (1 << 10) | 1;
1086 } else {
1087 clock = 0;
1088 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1089 << 2) | (clock << 1) | (1 << 10) | 1;
1090 }
1091
1092 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1093 AR5K_RF_BUFFER);
1094 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1095 AR5K_RF_BUFFER_CONTROL_3);
1096
1097 return 0;
1098 }
1099
1100 /*
1101 * Set channel on 5112 and newer
1102 */
1103 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1104 struct ieee80211_channel *channel)
1105 {
1106 u32 data, data0, data1, data2;
1107 u16 c;
1108
1109 data = data0 = data1 = data2 = 0;
1110 c = channel->center_freq;
1111
1112 if (c < 4800) {
1113 if (!((c - 2224) % 5)) {
1114 data0 = ((2 * (c - 704)) - 3040) / 10;
1115 data1 = 1;
1116 } else if (!((c - 2192) % 5)) {
1117 data0 = ((2 * (c - 672)) - 3040) / 10;
1118 data1 = 0;
1119 } else
1120 return -EINVAL;
1121
1122 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1123 } else if ((c % 5) != 2 || c > 5435) {
1124 if (!(c % 20) && c >= 5120) {
1125 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1126 data2 = ath5k_hw_bitswap(3, 2);
1127 } else if (!(c % 10)) {
1128 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1129 data2 = ath5k_hw_bitswap(2, 2);
1130 } else if (!(c % 5)) {
1131 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1132 data2 = ath5k_hw_bitswap(1, 2);
1133 } else
1134 return -EINVAL;
1135 } else {
1136 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1137 data2 = ath5k_hw_bitswap(0, 2);
1138 }
1139
1140 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1141
1142 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1143 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1144
1145 return 0;
1146 }
1147
1148 /*
1149 * Set the channel on the RF2425
1150 */
1151 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1152 struct ieee80211_channel *channel)
1153 {
1154 u32 data, data0, data2;
1155 u16 c;
1156
1157 data = data0 = data2 = 0;
1158 c = channel->center_freq;
1159
1160 if (c < 4800) {
1161 data0 = ath5k_hw_bitswap((c - 2272), 8);
1162 data2 = 0;
1163 /* ? 5GHz ? */
1164 } else if ((c % 5) != 2 || c > 5435) {
1165 if (!(c % 20) && c < 5120)
1166 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1167 else if (!(c % 10))
1168 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1169 else if (!(c % 5))
1170 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1171 else
1172 return -EINVAL;
1173 data2 = ath5k_hw_bitswap(1, 2);
1174 } else {
1175 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1176 data2 = ath5k_hw_bitswap(0, 2);
1177 }
1178
1179 data = (data0 << 4) | data2 << 2 | 0x1001;
1180
1181 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1182 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1183
1184 return 0;
1185 }
1186
1187 /*
1188 * Set a channel on the radio chip
1189 */
1190 static int ath5k_hw_channel(struct ath5k_hw *ah,
1191 struct ieee80211_channel *channel)
1192 {
1193 int ret;
1194 /*
1195 * Check bounds supported by the PHY (we don't care about regultory
1196 * restrictions at this point). Note: hw_value already has the band
1197 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1198 * of the band by that */
1199 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1200 ATH5K_ERR(ah->ah_sc,
1201 "channel frequency (%u MHz) out of supported "
1202 "band range\n",
1203 channel->center_freq);
1204 return -EINVAL;
1205 }
1206
1207 /*
1208 * Set the channel and wait
1209 */
1210 switch (ah->ah_radio) {
1211 case AR5K_RF5110:
1212 ret = ath5k_hw_rf5110_channel(ah, channel);
1213 break;
1214 case AR5K_RF5111:
1215 ret = ath5k_hw_rf5111_channel(ah, channel);
1216 break;
1217 case AR5K_RF2425:
1218 ret = ath5k_hw_rf2425_channel(ah, channel);
1219 break;
1220 default:
1221 ret = ath5k_hw_rf5112_channel(ah, channel);
1222 break;
1223 }
1224
1225 if (ret)
1226 return ret;
1227
1228 /* Set JAPAN setting for channel 14 */
1229 if (channel->center_freq == 2484) {
1230 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1231 AR5K_PHY_CCKTXCTL_JAPAN);
1232 } else {
1233 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1234 AR5K_PHY_CCKTXCTL_WORLD);
1235 }
1236
1237 ah->ah_current_channel = channel;
1238 ath5k_hw_set_clockrate(ah);
1239
1240 return 0;
1241 }
1242
1243 /*****************\
1244 PHY calibration
1245 \*****************/
1246
1247 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1248 {
1249 s32 val;
1250
1251 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1252 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1253 }
1254
1255 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1256 {
1257 int i;
1258
1259 ah->ah_nfcal_hist.index = 0;
1260 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1261 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1262 }
1263
1264 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1265 {
1266 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1267 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1268 hist->nfval[hist->index] = noise_floor;
1269 }
1270
1271 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1272 {
1273 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1274 s16 tmp;
1275 int i, j;
1276
1277 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1278 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1279 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1280 if (sort[j] > sort[j-1]) {
1281 tmp = sort[j];
1282 sort[j] = sort[j-1];
1283 sort[j-1] = tmp;
1284 }
1285 }
1286 }
1287 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1288 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1289 "cal %d:%d\n", i, sort[i]);
1290 }
1291 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1292 }
1293
1294 /*
1295 * When we tell the hardware to perform a noise floor calibration
1296 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1297 * sample-and-hold the minimum noise level seen at the antennas.
1298 * This value is then stored in a ring buffer of recently measured
1299 * noise floor values so we have a moving window of the last few
1300 * samples.
1301 *
1302 * The median of the values in the history is then loaded into the
1303 * hardware for its own use for RSSI and CCA measurements.
1304 */
1305 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1306 {
1307 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1308 u32 val;
1309 s16 nf, threshold;
1310 u8 ee_mode;
1311
1312 /* keep last value if calibration hasn't completed */
1313 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1314 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1315 "NF did not complete in calibration window\n");
1316
1317 return;
1318 }
1319
1320 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1321 case CHANNEL_A:
1322 case CHANNEL_T:
1323 case CHANNEL_XR:
1324 ee_mode = AR5K_EEPROM_MODE_11A;
1325 break;
1326 case CHANNEL_G:
1327 case CHANNEL_TG:
1328 ee_mode = AR5K_EEPROM_MODE_11G;
1329 break;
1330 default:
1331 case CHANNEL_B:
1332 ee_mode = AR5K_EEPROM_MODE_11B;
1333 break;
1334 }
1335
1336
1337 /* completed NF calibration, test threshold */
1338 nf = ath5k_hw_read_measured_noise_floor(ah);
1339 threshold = ee->ee_noise_floor_thr[ee_mode];
1340
1341 if (nf > threshold) {
1342 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1343 "noise floor failure detected; "
1344 "read %d, threshold %d\n",
1345 nf, threshold);
1346
1347 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1348 }
1349
1350 ath5k_hw_update_nfcal_hist(ah, nf);
1351 nf = ath5k_hw_get_median_noise_floor(ah);
1352
1353 /* load noise floor (in .5 dBm) so the hardware will use it */
1354 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1355 val |= (nf * 2) & AR5K_PHY_NF_M;
1356 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1357
1358 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1359 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1360
1361 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1362 0, false);
1363
1364 /*
1365 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1366 * so that we're not capped by the median we just loaded.
1367 * This will be used as the initial value for the next noise
1368 * floor calibration.
1369 */
1370 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1371 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1372 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1373 AR5K_PHY_AGCCTL_NF_EN |
1374 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1375 AR5K_PHY_AGCCTL_NF);
1376
1377 ah->ah_noise_floor = nf;
1378
1379 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1380 "noise floor calibrated: %d\n", nf);
1381 }
1382
1383 /*
1384 * Perform a PHY calibration on RF5110
1385 * -Fix BPSK/QAM Constellation (I/Q correction)
1386 */
1387 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1388 struct ieee80211_channel *channel)
1389 {
1390 u32 phy_sig, phy_agc, phy_sat, beacon;
1391 int ret;
1392
1393 /*
1394 * Disable beacons and RX/TX queues, wait
1395 */
1396 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1397 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1398 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1399 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1400
1401 mdelay(2);
1402
1403 /*
1404 * Set the channel (with AGC turned off)
1405 */
1406 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1407 udelay(10);
1408 ret = ath5k_hw_channel(ah, channel);
1409
1410 /*
1411 * Activate PHY and wait
1412 */
1413 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1414 mdelay(1);
1415
1416 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1417
1418 if (ret)
1419 return ret;
1420
1421 /*
1422 * Calibrate the radio chip
1423 */
1424
1425 /* Remember normal state */
1426 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1427 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1428 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1429
1430 /* Update radio registers */
1431 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1432 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1433
1434 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1435 AR5K_PHY_AGCCOARSE_LO)) |
1436 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1437 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1438
1439 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1440 AR5K_PHY_ADCSAT_THR)) |
1441 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1442 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1443
1444 udelay(20);
1445
1446 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1447 udelay(10);
1448 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1449 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1450
1451 mdelay(1);
1452
1453 /*
1454 * Enable calibration and wait until completion
1455 */
1456 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1457
1458 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1459 AR5K_PHY_AGCCTL_CAL, 0, false);
1460
1461 /* Reset to normal state */
1462 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1463 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1464 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1465
1466 if (ret) {
1467 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1468 channel->center_freq);
1469 return ret;
1470 }
1471
1472 /*
1473 * Re-enable RX/TX and beacons
1474 */
1475 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1476 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1477 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1478
1479 return 0;
1480 }
1481
1482 /*
1483 * Perform I/Q calibration on RF5111/5112 and newer chips
1484 */
1485 static int
1486 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1487 {
1488 u32 i_pwr, q_pwr;
1489 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1490 int i;
1491
1492 if (!ah->ah_calibration ||
1493 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1494 return 0;
1495
1496 /* Calibration has finished, get the results and re-run */
1497 /* work around empty results which can apparently happen on 5212 */
1498 for (i = 0; i <= 10; i++) {
1499 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1500 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1501 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1502 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1503 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1504 if (i_pwr && q_pwr)
1505 break;
1506 }
1507
1508 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1509
1510 if (ah->ah_version == AR5K_AR5211)
1511 q_coffd = q_pwr >> 6;
1512 else
1513 q_coffd = q_pwr >> 7;
1514
1515 /* protect against divide by 0 and loss of sign bits */
1516 if (i_coffd == 0 || q_coffd < 2)
1517 return 0;
1518
1519 i_coff = (-iq_corr) / i_coffd;
1520 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1521
1522 if (ah->ah_version == AR5K_AR5211)
1523 q_coff = (i_pwr / q_coffd) - 64;
1524 else
1525 q_coff = (i_pwr / q_coffd) - 128;
1526 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1527
1528 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1529 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1530 i_coff, q_coff, i_coffd, q_coffd);
1531
1532 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1533 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1534 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1535 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1536
1537 /* Re-enable calibration -if we don't we'll commit
1538 * the same values again and again */
1539 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1540 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1541 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1542
1543 return 0;
1544 }
1545
1546 /*
1547 * Perform a PHY calibration
1548 */
1549 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1550 struct ieee80211_channel *channel)
1551 {
1552 int ret;
1553
1554 if (ah->ah_radio == AR5K_RF5110)
1555 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1556 else {
1557 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1558 ath5k_hw_request_rfgain_probe(ah);
1559 }
1560
1561 return ret;
1562 }
1563
1564
1565 /***************************\
1566 * Spur mitigation functions *
1567 \***************************/
1568
1569 static void
1570 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1571 struct ieee80211_channel *channel)
1572 {
1573 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1574 u32 mag_mask[4] = {0, 0, 0, 0};
1575 u32 pilot_mask[2] = {0, 0};
1576 /* Note: fbin values are scaled up by 2 */
1577 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1578 s32 spur_delta_phase, spur_freq_sigma_delta;
1579 s32 spur_offset, num_symbols_x16;
1580 u8 num_symbol_offsets, i, freq_band;
1581
1582 /* Convert current frequency to fbin value (the same way channels
1583 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1584 * up by 2 so we can compare it later */
1585 if (channel->hw_value & CHANNEL_2GHZ) {
1586 chan_fbin = (channel->center_freq - 2300) * 10;
1587 freq_band = AR5K_EEPROM_BAND_2GHZ;
1588 } else {
1589 chan_fbin = (channel->center_freq - 4900) * 10;
1590 freq_band = AR5K_EEPROM_BAND_5GHZ;
1591 }
1592
1593 /* Check if any spur_chan_fbin from EEPROM is
1594 * within our current channel's spur detection range */
1595 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1596 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1597 /* XXX: Half/Quarter channels ?*/
1598 if (channel->hw_value & CHANNEL_TURBO)
1599 spur_detection_window *= 2;
1600
1601 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1602 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1603
1604 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1605 * so it's zero if we got nothing from EEPROM */
1606 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1607 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1608 break;
1609 }
1610
1611 if ((chan_fbin - spur_detection_window <=
1612 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1613 (chan_fbin + spur_detection_window >=
1614 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1615 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1616 break;
1617 }
1618 }
1619
1620 /* We need to enable spur filter for this channel */
1621 if (spur_chan_fbin) {
1622 spur_offset = spur_chan_fbin - chan_fbin;
1623 /*
1624 * Calculate deltas:
1625 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1626 * spur_delta_phase -> spur_offset / chip_freq << 11
1627 * Note: Both values have 100KHz resolution
1628 */
1629 /* XXX: Half/Quarter rate channels ? */
1630 switch (channel->hw_value) {
1631 case CHANNEL_A:
1632 /* Both sample_freq and chip_freq are 40MHz */
1633 spur_delta_phase = (spur_offset << 17) / 25;
1634 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1635 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1636 break;
1637 case CHANNEL_G:
1638 /* sample_freq -> 40MHz chip_freq -> 44MHz
1639 * (for b compatibility) */
1640 spur_freq_sigma_delta = (spur_offset << 8) / 55;
1641 spur_delta_phase = (spur_offset << 17) / 25;
1642 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1643 break;
1644 case CHANNEL_T:
1645 case CHANNEL_TG:
1646 /* Both sample_freq and chip_freq are 80MHz */
1647 spur_delta_phase = (spur_offset << 16) / 25;
1648 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1649 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1650 break;
1651 default:
1652 return;
1653 }
1654
1655 /* Calculate pilot and magnitude masks */
1656
1657 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1658 * and divide by symbol_width to find how many symbols we have
1659 * Note: number of symbols is scaled up by 16 */
1660 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1661
1662 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1663 if (!(num_symbols_x16 & 0xF))
1664 /* _X_ */
1665 num_symbol_offsets = 3;
1666 else
1667 /* _xx_ */
1668 num_symbol_offsets = 4;
1669
1670 for (i = 0; i < num_symbol_offsets; i++) {
1671
1672 /* Calculate pilot mask */
1673 s32 curr_sym_off =
1674 (num_symbols_x16 / 16) + i + 25;
1675
1676 /* Pilot magnitude mask seems to be a way to
1677 * declare the boundaries for our detection
1678 * window or something, it's 2 for the middle
1679 * value(s) where the symbol is expected to be
1680 * and 1 on the boundary values */
1681 u8 plt_mag_map =
1682 (i == 0 || i == (num_symbol_offsets - 1))
1683 ? 1 : 2;
1684
1685 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1686 if (curr_sym_off <= 25)
1687 pilot_mask[0] |= 1 << curr_sym_off;
1688 else if (curr_sym_off >= 27)
1689 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1690 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1691 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1692
1693 /* Calculate magnitude mask (for viterbi decoder) */
1694 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1695 mag_mask[0] |=
1696 plt_mag_map << (curr_sym_off + 1) * 2;
1697 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1698 mag_mask[1] |=
1699 plt_mag_map << (curr_sym_off - 15) * 2;
1700 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1701 mag_mask[2] |=
1702 plt_mag_map << (curr_sym_off - 31) * 2;
1703 else if (curr_sym_off >= 47 && curr_sym_off <= 53)
1704 mag_mask[3] |=
1705 plt_mag_map << (curr_sym_off - 47) * 2;
1706
1707 }
1708
1709 /* Write settings on hw to enable spur filter */
1710 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1711 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1712 /* XXX: Self correlator also ? */
1713 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1714 AR5K_PHY_IQ_PILOT_MASK_EN |
1715 AR5K_PHY_IQ_CHAN_MASK_EN |
1716 AR5K_PHY_IQ_SPUR_FILT_EN);
1717
1718 /* Set delta phase and freq sigma delta */
1719 ath5k_hw_reg_write(ah,
1720 AR5K_REG_SM(spur_delta_phase,
1721 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1722 AR5K_REG_SM(spur_freq_sigma_delta,
1723 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1724 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1725 AR5K_PHY_TIMING_11);
1726
1727 /* Write pilot masks */
1728 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1729 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1730 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1731 pilot_mask[1]);
1732
1733 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1734 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1735 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1736 pilot_mask[1]);
1737
1738 /* Write magnitude masks */
1739 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1740 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1741 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1742 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1743 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1744 mag_mask[3]);
1745
1746 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1747 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1748 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1749 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1750 AR5K_PHY_BIN_MASK2_4_MASK_4,
1751 mag_mask[3]);
1752
1753 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1754 AR5K_PHY_IQ_SPUR_FILT_EN) {
1755 /* Clean up spur mitigation settings and disable fliter */
1756 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1757 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1758 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1759 AR5K_PHY_IQ_PILOT_MASK_EN |
1760 AR5K_PHY_IQ_CHAN_MASK_EN |
1761 AR5K_PHY_IQ_SPUR_FILT_EN);
1762 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1763
1764 /* Clear pilot masks */
1765 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1766 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1767 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1768 0);
1769
1770 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1771 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1772 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1773 0);
1774
1775 /* Clear magnitude masks */
1776 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1777 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1778 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1779 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1780 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1781 0);
1782
1783 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1784 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1785 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1786 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1787 AR5K_PHY_BIN_MASK2_4_MASK_4,
1788 0);
1789 }
1790 }
1791
1792
1793 /*****************\
1794 * Antenna control *
1795 \*****************/
1796
1797 static void /*TODO:Boundary check*/
1798 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1799 {
1800 if (ah->ah_version != AR5K_AR5210)
1801 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1802 }
1803
1804 /*
1805 * Enable/disable fast rx antenna diversity
1806 */
1807 static void
1808 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1809 {
1810 switch (ee_mode) {
1811 case AR5K_EEPROM_MODE_11G:
1812 /* XXX: This is set to
1813 * disabled on initvals !!! */
1814 case AR5K_EEPROM_MODE_11A:
1815 if (enable)
1816 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1817 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1818 else
1819 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1820 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1821 break;
1822 case AR5K_EEPROM_MODE_11B:
1823 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1824 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1825 break;
1826 default:
1827 return;
1828 }
1829
1830 if (enable) {
1831 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1832 AR5K_PHY_RESTART_DIV_GC, 4);
1833
1834 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1835 AR5K_PHY_FAST_ANT_DIV_EN);
1836 } else {
1837 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1838 AR5K_PHY_RESTART_DIV_GC, 0);
1839
1840 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1841 AR5K_PHY_FAST_ANT_DIV_EN);
1842 }
1843 }
1844
1845 void
1846 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1847 {
1848 u8 ant0, ant1;
1849
1850 /*
1851 * In case a fixed antenna was set as default
1852 * use the same switch table twice.
1853 */
1854 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1855 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1856 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1857 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1858 else {
1859 ant0 = AR5K_ANT_SWTABLE_A;
1860 ant1 = AR5K_ANT_SWTABLE_B;
1861 }
1862
1863 /* Set antenna idle switch table */
1864 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1865 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1866 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1867 AR5K_PHY_ANT_CTL_TXRX_EN));
1868
1869 /* Set antenna switch tables */
1870 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1871 AR5K_PHY_ANT_SWITCH_TABLE_0);
1872 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1873 AR5K_PHY_ANT_SWITCH_TABLE_1);
1874 }
1875
1876 /*
1877 * Set antenna operating mode
1878 */
1879 void
1880 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1881 {
1882 struct ieee80211_channel *channel = ah->ah_current_channel;
1883 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1884 bool use_def_for_sg;
1885 u8 def_ant, tx_ant, ee_mode;
1886 u32 sta_id1 = 0;
1887
1888 /* if channel is not initialized yet we can't set the antennas
1889 * so just store the mode. it will be set on the next reset */
1890 if (channel == NULL) {
1891 ah->ah_ant_mode = ant_mode;
1892 return;
1893 }
1894
1895 def_ant = ah->ah_def_ant;
1896
1897 switch (channel->hw_value & CHANNEL_MODES) {
1898 case CHANNEL_A:
1899 case CHANNEL_T:
1900 case CHANNEL_XR:
1901 ee_mode = AR5K_EEPROM_MODE_11A;
1902 break;
1903 case CHANNEL_G:
1904 case CHANNEL_TG:
1905 ee_mode = AR5K_EEPROM_MODE_11G;
1906 break;
1907 case CHANNEL_B:
1908 ee_mode = AR5K_EEPROM_MODE_11B;
1909 break;
1910 default:
1911 ATH5K_ERR(ah->ah_sc,
1912 "invalid channel: %d\n", channel->center_freq);
1913 return;
1914 }
1915
1916 switch (ant_mode) {
1917 case AR5K_ANTMODE_DEFAULT:
1918 tx_ant = 0;
1919 use_def_for_tx = false;
1920 update_def_on_tx = false;
1921 use_def_for_rts = false;
1922 use_def_for_sg = false;
1923 fast_div = true;
1924 break;
1925 case AR5K_ANTMODE_FIXED_A:
1926 def_ant = 1;
1927 tx_ant = 1;
1928 use_def_for_tx = true;
1929 update_def_on_tx = false;
1930 use_def_for_rts = true;
1931 use_def_for_sg = true;
1932 fast_div = false;
1933 break;
1934 case AR5K_ANTMODE_FIXED_B:
1935 def_ant = 2;
1936 tx_ant = 2;
1937 use_def_for_tx = true;
1938 update_def_on_tx = false;
1939 use_def_for_rts = true;
1940 use_def_for_sg = true;
1941 fast_div = false;
1942 break;
1943 case AR5K_ANTMODE_SINGLE_AP:
1944 def_ant = 1; /* updated on tx */
1945 tx_ant = 0;
1946 use_def_for_tx = true;
1947 update_def_on_tx = true;
1948 use_def_for_rts = true;
1949 use_def_for_sg = true;
1950 fast_div = true;
1951 break;
1952 case AR5K_ANTMODE_SECTOR_AP:
1953 tx_ant = 1; /* variable */
1954 use_def_for_tx = false;
1955 update_def_on_tx = false;
1956 use_def_for_rts = true;
1957 use_def_for_sg = false;
1958 fast_div = false;
1959 break;
1960 case AR5K_ANTMODE_SECTOR_STA:
1961 tx_ant = 1; /* variable */
1962 use_def_for_tx = true;
1963 update_def_on_tx = false;
1964 use_def_for_rts = true;
1965 use_def_for_sg = false;
1966 fast_div = true;
1967 break;
1968 case AR5K_ANTMODE_DEBUG:
1969 def_ant = 1;
1970 tx_ant = 2;
1971 use_def_for_tx = false;
1972 update_def_on_tx = false;
1973 use_def_for_rts = false;
1974 use_def_for_sg = false;
1975 fast_div = false;
1976 break;
1977 default:
1978 return;
1979 }
1980
1981 ah->ah_tx_ant = tx_ant;
1982 ah->ah_ant_mode = ant_mode;
1983 ah->ah_def_ant = def_ant;
1984
1985 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1986 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1987 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1988 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1989
1990 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1991
1992 if (sta_id1)
1993 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1994
1995 ath5k_hw_set_antenna_switch(ah, ee_mode);
1996 /* Note: set diversity before default antenna
1997 * because it won't work correctly */
1998 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1999 ath5k_hw_set_def_antenna(ah, def_ant);
2000 }
2001
2002
2003 /****************\
2004 * TX power setup *
2005 \****************/
2006
2007 /*
2008 * Helper functions
2009 */
2010
2011 /*
2012 * Do linear interpolation between two given (x, y) points
2013 */
2014 static s16
2015 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2016 s16 y_left, s16 y_right)
2017 {
2018 s16 ratio, result;
2019
2020 /* Avoid divide by zero and skip interpolation
2021 * if we have the same point */
2022 if ((x_left == x_right) || (y_left == y_right))
2023 return y_left;
2024
2025 /*
2026 * Since we use ints and not fps, we need to scale up in
2027 * order to get a sane ratio value (or else we 'll eg. get
2028 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2029 * to have some accuracy both for 0.5 and 0.25 steps.
2030 */
2031 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
2032
2033 /* Now scale down to be in range */
2034 result = y_left + (ratio * (target - x_left) / 100);
2035
2036 return result;
2037 }
2038
2039 /*
2040 * Find vertical boundary (min pwr) for the linear PCDAC curve.
2041 *
2042 * Since we have the top of the curve and we draw the line below
2043 * until we reach 1 (1 pcdac step) we need to know which point
2044 * (x value) that is so that we don't go below y axis and have negative
2045 * pcdac values when creating the curve, or fill the table with zeroes.
2046 */
2047 static s16
2048 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2049 const s16 *pwrL, const s16 *pwrR)
2050 {
2051 s8 tmp;
2052 s16 min_pwrL, min_pwrR;
2053 s16 pwr_i;
2054
2055 /* Some vendors write the same pcdac value twice !!! */
2056 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2057 return max(pwrL[0], pwrR[0]);
2058
2059 if (pwrL[0] == pwrL[1])
2060 min_pwrL = pwrL[0];
2061 else {
2062 pwr_i = pwrL[0];
2063 do {
2064 pwr_i--;
2065 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2066 pwrL[0], pwrL[1],
2067 stepL[0], stepL[1]);
2068 } while (tmp > 1);
2069
2070 min_pwrL = pwr_i;
2071 }
2072
2073 if (pwrR[0] == pwrR[1])
2074 min_pwrR = pwrR[0];
2075 else {
2076 pwr_i = pwrR[0];
2077 do {
2078 pwr_i--;
2079 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2080 pwrR[0], pwrR[1],
2081 stepR[0], stepR[1]);
2082 } while (tmp > 1);
2083
2084 min_pwrR = pwr_i;
2085 }
2086
2087 /* Keep the right boundary so that it works for both curves */
2088 return max(min_pwrL, min_pwrR);
2089 }
2090
2091 /*
2092 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2093 * Power to PCDAC curve.
2094 *
2095 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2096 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2097 * PCDAC/PDADC step for each curve is 64 but we can write more than
2098 * one curves on hw so we can go up to 128 (which is the max step we
2099 * can write on the final table).
2100 *
2101 * We write y values (PCDAC/PDADC steps) on hw.
2102 */
2103 static void
2104 ath5k_create_power_curve(s16 pmin, s16 pmax,
2105 const s16 *pwr, const u8 *vpd,
2106 u8 num_points,
2107 u8 *vpd_table, u8 type)
2108 {
2109 u8 idx[2] = { 0, 1 };
2110 s16 pwr_i = 2*pmin;
2111 int i;
2112
2113 if (num_points < 2)
2114 return;
2115
2116 /* We want the whole line, so adjust boundaries
2117 * to cover the entire power range. Note that
2118 * power values are already 0.25dB so no need
2119 * to multiply pwr_i by 2 */
2120 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2121 pwr_i = pmin;
2122 pmin = 0;
2123 pmax = 63;
2124 }
2125
2126 /* Find surrounding turning points (TPs)
2127 * and interpolate between them */
2128 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2129 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2130
2131 /* We passed the right TP, move to the next set of TPs
2132 * if we pass the last TP, extrapolate above using the last
2133 * two TPs for ratio */
2134 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2135 idx[0]++;
2136 idx[1]++;
2137 }
2138
2139 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2140 pwr[idx[0]], pwr[idx[1]],
2141 vpd[idx[0]], vpd[idx[1]]);
2142
2143 /* Increase by 0.5dB
2144 * (0.25 dB units) */
2145 pwr_i += 2;
2146 }
2147 }
2148
2149 /*
2150 * Get the surrounding per-channel power calibration piers
2151 * for a given frequency so that we can interpolate between
2152 * them and come up with an apropriate dataset for our current
2153 * channel.
2154 */
2155 static void
2156 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2157 struct ieee80211_channel *channel,
2158 struct ath5k_chan_pcal_info **pcinfo_l,
2159 struct ath5k_chan_pcal_info **pcinfo_r)
2160 {
2161 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2162 struct ath5k_chan_pcal_info *pcinfo;
2163 u8 idx_l, idx_r;
2164 u8 mode, max, i;
2165 u32 target = channel->center_freq;
2166
2167 idx_l = 0;
2168 idx_r = 0;
2169
2170 if (!(channel->hw_value & CHANNEL_OFDM)) {
2171 pcinfo = ee->ee_pwr_cal_b;
2172 mode = AR5K_EEPROM_MODE_11B;
2173 } else if (channel->hw_value & CHANNEL_2GHZ) {
2174 pcinfo = ee->ee_pwr_cal_g;
2175 mode = AR5K_EEPROM_MODE_11G;
2176 } else {
2177 pcinfo = ee->ee_pwr_cal_a;
2178 mode = AR5K_EEPROM_MODE_11A;
2179 }
2180 max = ee->ee_n_piers[mode] - 1;
2181
2182 /* Frequency is below our calibrated
2183 * range. Use the lowest power curve
2184 * we have */
2185 if (target < pcinfo[0].freq) {
2186 idx_l = idx_r = 0;
2187 goto done;
2188 }
2189
2190 /* Frequency is above our calibrated
2191 * range. Use the highest power curve
2192 * we have */
2193 if (target > pcinfo[max].freq) {
2194 idx_l = idx_r = max;
2195 goto done;
2196 }
2197
2198 /* Frequency is inside our calibrated
2199 * channel range. Pick the surrounding
2200 * calibration piers so that we can
2201 * interpolate */
2202 for (i = 0; i <= max; i++) {
2203
2204 /* Frequency matches one of our calibration
2205 * piers, no need to interpolate, just use
2206 * that calibration pier */
2207 if (pcinfo[i].freq == target) {
2208 idx_l = idx_r = i;
2209 goto done;
2210 }
2211
2212 /* We found a calibration pier that's above
2213 * frequency, use this pier and the previous
2214 * one to interpolate */
2215 if (target < pcinfo[i].freq) {
2216 idx_r = i;
2217 idx_l = idx_r - 1;
2218 goto done;
2219 }
2220 }
2221
2222 done:
2223 *pcinfo_l = &pcinfo[idx_l];
2224 *pcinfo_r = &pcinfo[idx_r];
2225 }
2226
2227 /*
2228 * Get the surrounding per-rate power calibration data
2229 * for a given frequency and interpolate between power
2230 * values to set max target power supported by hw for
2231 * each rate.
2232 */
2233 static void
2234 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2235 struct ieee80211_channel *channel,
2236 struct ath5k_rate_pcal_info *rates)
2237 {
2238 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2239 struct ath5k_rate_pcal_info *rpinfo;
2240 u8 idx_l, idx_r;
2241 u8 mode, max, i;
2242 u32 target = channel->center_freq;
2243
2244 idx_l = 0;
2245 idx_r = 0;
2246
2247 if (!(channel->hw_value & CHANNEL_OFDM)) {
2248 rpinfo = ee->ee_rate_tpwr_b;
2249 mode = AR5K_EEPROM_MODE_11B;
2250 } else if (channel->hw_value & CHANNEL_2GHZ) {
2251 rpinfo = ee->ee_rate_tpwr_g;
2252 mode = AR5K_EEPROM_MODE_11G;
2253 } else {
2254 rpinfo = ee->ee_rate_tpwr_a;
2255 mode = AR5K_EEPROM_MODE_11A;
2256 }
2257 max = ee->ee_rate_target_pwr_num[mode] - 1;
2258
2259 /* Get the surrounding calibration
2260 * piers - same as above */
2261 if (target < rpinfo[0].freq) {
2262 idx_l = idx_r = 0;
2263 goto done;
2264 }
2265
2266 if (target > rpinfo[max].freq) {
2267 idx_l = idx_r = max;
2268 goto done;
2269 }
2270
2271 for (i = 0; i <= max; i++) {
2272
2273 if (rpinfo[i].freq == target) {
2274 idx_l = idx_r = i;
2275 goto done;
2276 }
2277
2278 if (target < rpinfo[i].freq) {
2279 idx_r = i;
2280 idx_l = idx_r - 1;
2281 goto done;
2282 }
2283 }
2284
2285 done:
2286 /* Now interpolate power value, based on the frequency */
2287 rates->freq = target;
2288
2289 rates->target_power_6to24 =
2290 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2291 rpinfo[idx_r].freq,
2292 rpinfo[idx_l].target_power_6to24,
2293 rpinfo[idx_r].target_power_6to24);
2294
2295 rates->target_power_36 =
2296 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2297 rpinfo[idx_r].freq,
2298 rpinfo[idx_l].target_power_36,
2299 rpinfo[idx_r].target_power_36);
2300
2301 rates->target_power_48 =
2302 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2303 rpinfo[idx_r].freq,
2304 rpinfo[idx_l].target_power_48,
2305 rpinfo[idx_r].target_power_48);
2306
2307 rates->target_power_54 =
2308 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2309 rpinfo[idx_r].freq,
2310 rpinfo[idx_l].target_power_54,
2311 rpinfo[idx_r].target_power_54);
2312 }
2313
2314 /*
2315 * Get the max edge power for this channel if
2316 * we have such data from EEPROM's Conformance Test
2317 * Limits (CTL), and limit max power if needed.
2318 */
2319 static void
2320 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2321 struct ieee80211_channel *channel)
2322 {
2323 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2324 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2325 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2326 u8 *ctl_val = ee->ee_ctl;
2327 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2328 s16 edge_pwr = 0;
2329 u8 rep_idx;
2330 u8 i, ctl_mode;
2331 u8 ctl_idx = 0xFF;
2332 u32 target = channel->center_freq;
2333
2334 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2335
2336 switch (channel->hw_value & CHANNEL_MODES) {
2337 case CHANNEL_A:
2338 ctl_mode |= AR5K_CTL_11A;
2339 break;
2340 case CHANNEL_G:
2341 ctl_mode |= AR5K_CTL_11G;
2342 break;
2343 case CHANNEL_B:
2344 ctl_mode |= AR5K_CTL_11B;
2345 break;
2346 case CHANNEL_T:
2347 ctl_mode |= AR5K_CTL_TURBO;
2348 break;
2349 case CHANNEL_TG:
2350 ctl_mode |= AR5K_CTL_TURBOG;
2351 break;
2352 case CHANNEL_XR:
2353 /* Fall through */
2354 default:
2355 return;
2356 }
2357
2358 for (i = 0; i < ee->ee_ctls; i++) {
2359 if (ctl_val[i] == ctl_mode) {
2360 ctl_idx = i;
2361 break;
2362 }
2363 }
2364
2365 /* If we have a CTL dataset available grab it and find the
2366 * edge power for our frequency */
2367 if (ctl_idx == 0xFF)
2368 return;
2369
2370 /* Edge powers are sorted by frequency from lower
2371 * to higher. Each CTL corresponds to 8 edge power
2372 * measurements. */
2373 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2374
2375 /* Don't do boundaries check because we
2376 * might have more that one bands defined
2377 * for this mode */
2378
2379 /* Get the edge power that's closer to our
2380 * frequency */
2381 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2382 rep_idx += i;
2383 if (target <= rep[rep_idx].freq)
2384 edge_pwr = (s16) rep[rep_idx].edge;
2385 }
2386
2387 if (edge_pwr)
2388 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2389 }
2390
2391
2392 /*
2393 * Power to PCDAC table functions
2394 */
2395
2396 /*
2397 * Fill Power to PCDAC table on RF5111
2398 *
2399 * No further processing is needed for RF5111, the only thing we have to
2400 * do is fill the values below and above calibration range since eeprom data
2401 * may not cover the entire PCDAC table.
2402 */
2403 static void
2404 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2405 s16 *table_max)
2406 {
2407 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2408 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2409 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2410 s16 min_pwr, max_pwr;
2411
2412 /* Get table boundaries */
2413 min_pwr = table_min[0];
2414 pcdac_0 = pcdac_tmp[0];
2415
2416 max_pwr = table_max[0];
2417 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2418
2419 /* Extrapolate below minimum using pcdac_0 */
2420 pcdac_i = 0;
2421 for (i = 0; i < min_pwr; i++)
2422 pcdac_out[pcdac_i++] = pcdac_0;
2423
2424 /* Copy values from pcdac_tmp */
2425 pwr_idx = min_pwr;
2426 for (i = 0 ; pwr_idx <= max_pwr &&
2427 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2428 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2429 pwr_idx++;
2430 }
2431
2432 /* Extrapolate above maximum */
2433 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2434 pcdac_out[pcdac_i++] = pcdac_n;
2435
2436 }
2437
2438 /*
2439 * Combine available XPD Curves and fill Linear Power to PCDAC table
2440 * on RF5112
2441 *
2442 * RFX112 can have up to 2 curves (one for low txpower range and one for
2443 * higher txpower range). We need to put them both on pcdac_out and place
2444 * them in the correct location. In case we only have one curve available
2445 * just fit it on pcdac_out (it's supposed to cover the entire range of
2446 * available pwr levels since it's always the higher power curve). Extrapolate
2447 * below and above final table if needed.
2448 */
2449 static void
2450 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2451 s16 *table_max, u8 pdcurves)
2452 {
2453 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2454 u8 *pcdac_low_pwr;
2455 u8 *pcdac_high_pwr;
2456 u8 *pcdac_tmp;
2457 u8 pwr;
2458 s16 max_pwr_idx;
2459 s16 min_pwr_idx;
2460 s16 mid_pwr_idx = 0;
2461 /* Edge flag turs on the 7nth bit on the PCDAC
2462 * to delcare the higher power curve (force values
2463 * to be greater than 64). If we only have one curve
2464 * we don't need to set this, if we have 2 curves and
2465 * fill the table backwards this can also be used to
2466 * switch from higher power curve to lower power curve */
2467 u8 edge_flag;
2468 int i;
2469
2470 /* When we have only one curve available
2471 * that's the higher power curve. If we have
2472 * two curves the first is the high power curve
2473 * and the next is the low power curve. */
2474 if (pdcurves > 1) {
2475 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2476 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2477 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2478 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2479
2480 /* If table size goes beyond 31.5dB, keep the
2481 * upper 31.5dB range when setting tx power.
2482 * Note: 126 = 31.5 dB in quarter dB steps */
2483 if (table_max[0] - table_min[1] > 126)
2484 min_pwr_idx = table_max[0] - 126;
2485 else
2486 min_pwr_idx = table_min[1];
2487
2488 /* Since we fill table backwards
2489 * start from high power curve */
2490 pcdac_tmp = pcdac_high_pwr;
2491
2492 edge_flag = 0x40;
2493 } else {
2494 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2495 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2496 min_pwr_idx = table_min[0];
2497 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2498 pcdac_tmp = pcdac_high_pwr;
2499 edge_flag = 0;
2500 }
2501
2502 /* This is used when setting tx power*/
2503 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2504
2505 /* Fill Power to PCDAC table backwards */
2506 pwr = max_pwr_idx;
2507 for (i = 63; i >= 0; i--) {
2508 /* Entering lower power range, reset
2509 * edge flag and set pcdac_tmp to lower
2510 * power curve.*/
2511 if (edge_flag == 0x40 &&
2512 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2513 edge_flag = 0x00;
2514 pcdac_tmp = pcdac_low_pwr;
2515 pwr = mid_pwr_idx/2;
2516 }
2517
2518 /* Don't go below 1, extrapolate below if we have
2519 * already swithced to the lower power curve -or
2520 * we only have one curve and edge_flag is zero
2521 * anyway */
2522 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2523 while (i >= 0) {
2524 pcdac_out[i] = pcdac_out[i + 1];
2525 i--;
2526 }
2527 break;
2528 }
2529
2530 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2531
2532 /* Extrapolate above if pcdac is greater than
2533 * 126 -this can happen because we OR pcdac_out
2534 * value with edge_flag on high power curve */
2535 if (pcdac_out[i] > 126)
2536 pcdac_out[i] = 126;
2537
2538 /* Decrease by a 0.5dB step */
2539 pwr--;
2540 }
2541 }
2542
2543 /* Write PCDAC values on hw */
2544 static void
2545 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2546 {
2547 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2548 int i;
2549
2550 /*
2551 * Write TX power values
2552 */
2553 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2554 ath5k_hw_reg_write(ah,
2555 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2556 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2557 AR5K_PHY_PCDAC_TXPOWER(i));
2558 }
2559 }
2560
2561
2562 /*
2563 * Power to PDADC table functions
2564 */
2565
2566 /*
2567 * Set the gain boundaries and create final Power to PDADC table
2568 *
2569 * We can have up to 4 pd curves, we need to do a simmilar process
2570 * as we do for RF5112. This time we don't have an edge_flag but we
2571 * set the gain boundaries on a separate register.
2572 */
2573 static void
2574 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2575 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2576 {
2577 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2578 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2579 u8 *pdadc_tmp;
2580 s16 pdadc_0;
2581 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2582 u8 pd_gain_overlap;
2583
2584 /* Note: Register value is initialized on initvals
2585 * there is no feedback from hw.
2586 * XXX: What about pd_gain_overlap from EEPROM ? */
2587 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2588 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2589
2590 /* Create final PDADC table */
2591 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2592 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2593
2594 if (pdg == pdcurves - 1)
2595 /* 2 dB boundary stretch for last
2596 * (higher power) curve */
2597 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2598 else
2599 /* Set gain boundary in the middle
2600 * between this curve and the next one */
2601 gain_boundaries[pdg] =
2602 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2603
2604 /* Sanity check in case our 2 db stretch got out of
2605 * range. */
2606 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2607 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2608
2609 /* For the first curve (lower power)
2610 * start from 0 dB */
2611 if (pdg == 0)
2612 pdadc_0 = 0;
2613 else
2614 /* For the other curves use the gain overlap */
2615 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2616 pd_gain_overlap;
2617
2618 /* Force each power step to be at least 0.5 dB */
2619 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2620 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2621 else
2622 pwr_step = 1;
2623
2624 /* If pdadc_0 is negative, we need to extrapolate
2625 * below this pdgain by a number of pwr_steps */
2626 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2627 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2628 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2629 pdadc_0++;
2630 }
2631
2632 /* Set last pwr level, using gain boundaries */
2633 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2634 /* Limit it to be inside pwr range */
2635 table_size = pwr_max[pdg] - pwr_min[pdg];
2636 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2637
2638 /* Fill pdadc_out table */
2639 while (pdadc_0 < max_idx && pdadc_i < 128)
2640 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2641
2642 /* Need to extrapolate above this pdgain? */
2643 if (pdadc_n <= max_idx)
2644 continue;
2645
2646 /* Force each power step to be at least 0.5 dB */
2647 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2648 pwr_step = pdadc_tmp[table_size - 1] -
2649 pdadc_tmp[table_size - 2];
2650 else
2651 pwr_step = 1;
2652
2653 /* Extrapolate above */
2654 while ((pdadc_0 < (s16) pdadc_n) &&
2655 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2656 s16 tmp = pdadc_tmp[table_size - 1] +
2657 (pdadc_0 - max_idx) * pwr_step;
2658 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2659 pdadc_0++;
2660 }
2661 }
2662
2663 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2664 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2665 pdg++;
2666 }
2667
2668 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2669 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2670 pdadc_i++;
2671 }
2672
2673 /* Set gain boundaries */
2674 ath5k_hw_reg_write(ah,
2675 AR5K_REG_SM(pd_gain_overlap,
2676 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2677 AR5K_REG_SM(gain_boundaries[0],
2678 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2679 AR5K_REG_SM(gain_boundaries[1],
2680 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2681 AR5K_REG_SM(gain_boundaries[2],
2682 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2683 AR5K_REG_SM(gain_boundaries[3],
2684 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2685 AR5K_PHY_TPC_RG5);
2686
2687 /* Used for setting rate power table */
2688 ah->ah_txpower.txp_min_idx = pwr_min[0];
2689
2690 }
2691
2692 /* Write PDADC values on hw */
2693 static void
2694 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2695 u8 pdcurves, u8 *pdg_to_idx)
2696 {
2697 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2698 u32 reg;
2699 u8 i;
2700
2701 /* Select the right pdgain curves */
2702
2703 /* Clear current settings */
2704 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2705 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2706 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2707 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2708 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2709
2710 /*
2711 * Use pd_gains curve from eeprom
2712 *
2713 * This overrides the default setting from initvals
2714 * in case some vendors (e.g. Zcomax) don't use the default
2715 * curves. If we don't honor their settings we 'll get a
2716 * 5dB (1 * gain overlap ?) drop.
2717 */
2718 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2719
2720 switch (pdcurves) {
2721 case 3:
2722 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2723 /* Fall through */
2724 case 2:
2725 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2726 /* Fall through */
2727 case 1:
2728 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2729 break;
2730 }
2731 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2732
2733 /*
2734 * Write TX power values
2735 */
2736 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2737 ath5k_hw_reg_write(ah,
2738 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2739 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2740 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2741 ((pdadc_out[4*i + 3] & 0xff) << 24),
2742 AR5K_PHY_PDADC_TXPOWER(i));
2743 }
2744 }
2745
2746
2747 /*
2748 * Common code for PCDAC/PDADC tables
2749 */
2750
2751 /*
2752 * This is the main function that uses all of the above
2753 * to set PCDAC/PDADC table on hw for the current channel.
2754 * This table is used for tx power calibration on the basband,
2755 * without it we get weird tx power levels and in some cases
2756 * distorted spectral mask
2757 */
2758 static int
2759 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2760 struct ieee80211_channel *channel,
2761 u8 ee_mode, u8 type)
2762 {
2763 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2764 struct ath5k_chan_pcal_info *pcinfo_L;
2765 struct ath5k_chan_pcal_info *pcinfo_R;
2766 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2767 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2768 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2769 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2770 u8 *tmpL;
2771 u8 *tmpR;
2772 u32 target = channel->center_freq;
2773 int pdg, i;
2774
2775 /* Get surounding freq piers for this channel */
2776 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2777 &pcinfo_L,
2778 &pcinfo_R);
2779
2780 /* Loop over pd gain curves on
2781 * surounding freq piers by index */
2782 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2783
2784 /* Fill curves in reverse order
2785 * from lower power (max gain)
2786 * to higher power. Use curve -> idx
2787 * backmapping we did on eeprom init */
2788 u8 idx = pdg_curve_to_idx[pdg];
2789
2790 /* Grab the needed curves by index */
2791 pdg_L = &pcinfo_L->pd_curves[idx];
2792 pdg_R = &pcinfo_R->pd_curves[idx];
2793
2794 /* Initialize the temp tables */
2795 tmpL = ah->ah_txpower.tmpL[pdg];
2796 tmpR = ah->ah_txpower.tmpR[pdg];
2797
2798 /* Set curve's x boundaries and create
2799 * curves so that they cover the same
2800 * range (if we don't do that one table
2801 * will have values on some range and the
2802 * other one won't have any so interpolation
2803 * will fail) */
2804 table_min[pdg] = min(pdg_L->pd_pwr[0],
2805 pdg_R->pd_pwr[0]) / 2;
2806
2807 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2808 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2809
2810 /* Now create the curves on surrounding channels
2811 * and interpolate if needed to get the final
2812 * curve for this gain on this channel */
2813 switch (type) {
2814 case AR5K_PWRTABLE_LINEAR_PCDAC:
2815 /* Override min/max so that we don't loose
2816 * accuracy (don't divide by 2) */
2817 table_min[pdg] = min(pdg_L->pd_pwr[0],
2818 pdg_R->pd_pwr[0]);
2819
2820 table_max[pdg] =
2821 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2822 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2823
2824 /* Override minimum so that we don't get
2825 * out of bounds while extrapolating
2826 * below. Don't do this when we have 2
2827 * curves and we are on the high power curve
2828 * because table_min is ok in this case */
2829 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2830
2831 table_min[pdg] =
2832 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2833 pdg_R->pd_step,
2834 pdg_L->pd_pwr,
2835 pdg_R->pd_pwr);
2836
2837 /* Don't go too low because we will
2838 * miss the upper part of the curve.
2839 * Note: 126 = 31.5dB (max power supported)
2840 * in 0.25dB units */
2841 if (table_max[pdg] - table_min[pdg] > 126)
2842 table_min[pdg] = table_max[pdg] - 126;
2843 }
2844
2845 /* Fall through */
2846 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2847 case AR5K_PWRTABLE_PWR_TO_PDADC:
2848
2849 ath5k_create_power_curve(table_min[pdg],
2850 table_max[pdg],
2851 pdg_L->pd_pwr,
2852 pdg_L->pd_step,
2853 pdg_L->pd_points, tmpL, type);
2854
2855 /* We are in a calibration
2856 * pier, no need to interpolate
2857 * between freq piers */
2858 if (pcinfo_L == pcinfo_R)
2859 continue;
2860
2861 ath5k_create_power_curve(table_min[pdg],
2862 table_max[pdg],
2863 pdg_R->pd_pwr,
2864 pdg_R->pd_step,
2865 pdg_R->pd_points, tmpR, type);
2866 break;
2867 default:
2868 return -EINVAL;
2869 }
2870
2871 /* Interpolate between curves
2872 * of surounding freq piers to
2873 * get the final curve for this
2874 * pd gain. Re-use tmpL for interpolation
2875 * output */
2876 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2877 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2878 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2879 (s16) pcinfo_L->freq,
2880 (s16) pcinfo_R->freq,
2881 (s16) tmpL[i],
2882 (s16) tmpR[i]);
2883 }
2884 }
2885
2886 /* Now we have a set of curves for this
2887 * channel on tmpL (x range is table_max - table_min
2888 * and y values are tmpL[pdg][]) sorted in the same
2889 * order as EEPROM (because we've used the backmapping).
2890 * So for RF5112 it's from higher power to lower power
2891 * and for RF2413 it's from lower power to higher power.
2892 * For RF5111 we only have one curve. */
2893
2894 /* Fill min and max power levels for this
2895 * channel by interpolating the values on
2896 * surounding channels to complete the dataset */
2897 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2898 (s16) pcinfo_L->freq,
2899 (s16) pcinfo_R->freq,
2900 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2901
2902 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2903 (s16) pcinfo_L->freq,
2904 (s16) pcinfo_R->freq,
2905 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2906
2907 /* We are ready to go, fill PCDAC/PDADC
2908 * table and write settings on hardware */
2909 switch (type) {
2910 case AR5K_PWRTABLE_LINEAR_PCDAC:
2911 /* For RF5112 we can have one or two curves
2912 * and each curve covers a certain power lvl
2913 * range so we need to do some more processing */
2914 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2915 ee->ee_pd_gains[ee_mode]);
2916
2917 /* Set txp.offset so that we can
2918 * match max power value with max
2919 * table index */
2920 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2921
2922 /* Write settings on hw */
2923 ath5k_setup_pcdac_table(ah);
2924 break;
2925 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2926 /* We are done for RF5111 since it has only
2927 * one curve, just fit the curve on the table */
2928 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2929
2930 /* No rate powertable adjustment for RF5111 */
2931 ah->ah_txpower.txp_min_idx = 0;
2932 ah->ah_txpower.txp_offset = 0;
2933
2934 /* Write settings on hw */
2935 ath5k_setup_pcdac_table(ah);
2936 break;
2937 case AR5K_PWRTABLE_PWR_TO_PDADC:
2938 /* Set PDADC boundaries and fill
2939 * final PDADC table */
2940 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2941 ee->ee_pd_gains[ee_mode]);
2942
2943 /* Write settings on hw */
2944 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2945
2946 /* Set txp.offset, note that table_min
2947 * can be negative */
2948 ah->ah_txpower.txp_offset = table_min[0];
2949 break;
2950 default:
2951 return -EINVAL;
2952 }
2953
2954 return 0;
2955 }
2956
2957
2958 /*
2959 * Per-rate tx power setting
2960 *
2961 * This is the code that sets the desired tx power (below
2962 * maximum) on hw for each rate (we also have TPC that sets
2963 * power per packet). We do that by providing an index on the
2964 * PCDAC/PDADC table we set up.
2965 */
2966
2967 /*
2968 * Set rate power table
2969 *
2970 * For now we only limit txpower based on maximum tx power
2971 * supported by hw (what's inside rate_info). We need to limit
2972 * this even more, based on regulatory domain etc.
2973 *
2974 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2975 * and is indexed as follows:
2976 * rates[0] - rates[7] -> OFDM rates
2977 * rates[8] - rates[14] -> CCK rates
2978 * rates[15] -> XR rates (they all have the same power)
2979 */
2980 static void
2981 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2982 struct ath5k_rate_pcal_info *rate_info,
2983 u8 ee_mode)
2984 {
2985 unsigned int i;
2986 u16 *rates;
2987
2988 /* max_pwr is power level we got from driver/user in 0.5dB
2989 * units, switch to 0.25dB units so we can compare */
2990 max_pwr *= 2;
2991 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2992
2993 /* apply rate limits */
2994 rates = ah->ah_txpower.txp_rates_power_table;
2995
2996 /* OFDM rates 6 to 24Mb/s */
2997 for (i = 0; i < 5; i++)
2998 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2999
3000 /* Rest OFDM rates */
3001 rates[5] = min(rates[0], rate_info->target_power_36);
3002 rates[6] = min(rates[0], rate_info->target_power_48);
3003 rates[7] = min(rates[0], rate_info->target_power_54);
3004
3005 /* CCK rates */
3006 /* 1L */
3007 rates[8] = min(rates[0], rate_info->target_power_6to24);
3008 /* 2L */
3009 rates[9] = min(rates[0], rate_info->target_power_36);
3010 /* 2S */
3011 rates[10] = min(rates[0], rate_info->target_power_36);
3012 /* 5L */
3013 rates[11] = min(rates[0], rate_info->target_power_48);
3014 /* 5S */
3015 rates[12] = min(rates[0], rate_info->target_power_48);
3016 /* 11L */
3017 rates[13] = min(rates[0], rate_info->target_power_54);
3018 /* 11S */
3019 rates[14] = min(rates[0], rate_info->target_power_54);
3020
3021 /* XR rates */
3022 rates[15] = min(rates[0], rate_info->target_power_6to24);
3023
3024 /* CCK rates have different peak to average ratio
3025 * so we have to tweak their power so that gainf
3026 * correction works ok. For this we use OFDM to
3027 * CCK delta from eeprom */
3028 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
3029 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
3030 for (i = 8; i <= 15; i++)
3031 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
3032
3033 /* Now that we have all rates setup use table offset to
3034 * match the power range set by user with the power indices
3035 * on PCDAC/PDADC table */
3036 for (i = 0; i < 16; i++) {
3037 rates[i] += ah->ah_txpower.txp_offset;
3038 /* Don't get out of bounds */
3039 if (rates[i] > 63)
3040 rates[i] = 63;
3041 }
3042
3043 /* Min/max in 0.25dB units */
3044 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
3045 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
3046 ah->ah_txpower.txp_ofdm = rates[7];
3047 }
3048
3049
3050 /*
3051 * Set transmission power
3052 */
3053 static int
3054 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3055 u8 ee_mode, u8 txpower)
3056 {
3057 struct ath5k_rate_pcal_info rate_info;
3058 u8 type;
3059 int ret;
3060
3061 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3062 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3063 return -EINVAL;
3064 }
3065
3066 /* Reset TX power values */
3067 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3068 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3069 ah->ah_txpower.txp_min_pwr = 0;
3070 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3071
3072 /* Initialize TX power table */
3073 switch (ah->ah_radio) {
3074 case AR5K_RF5111:
3075 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3076 break;
3077 case AR5K_RF5112:
3078 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3079 break;
3080 case AR5K_RF2413:
3081 case AR5K_RF5413:
3082 case AR5K_RF2316:
3083 case AR5K_RF2317:
3084 case AR5K_RF2425:
3085 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3086 break;
3087 default:
3088 return -EINVAL;
3089 }
3090
3091 /* FIXME: Only on channel/mode change */
3092 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3093 if (ret)
3094 return ret;
3095
3096 /* Limit max power if we have a CTL available */
3097 ath5k_get_max_ctl_power(ah, channel);
3098
3099 /* FIXME: Antenna reduction stuff */
3100
3101 /* FIXME: Limit power on turbo modes */
3102
3103 /* FIXME: TPC scale reduction */
3104
3105 /* Get surounding channels for per-rate power table
3106 * calibration */
3107 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3108
3109 /* Setup rate power table */
3110 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3111
3112 /* Write rate power table on hw */
3113 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3114 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3115 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3116
3117 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3118 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3119 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3120
3121 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3122 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3123 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3124
3125 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3126 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3127 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3128
3129 /* FIXME: TPC support */
3130 if (ah->ah_txpower.txp_tpc) {
3131 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3132 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3133
3134 ath5k_hw_reg_write(ah,
3135 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3136 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3137 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3138 AR5K_TPC);
3139 } else {
3140 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3141 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3142 }
3143
3144 return 0;
3145 }
3146
3147 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3148 {
3149 /*Just a try M.F.*/
3150 struct ieee80211_channel *channel = ah->ah_current_channel;
3151 u8 ee_mode;
3152
3153 switch (channel->hw_value & CHANNEL_MODES) {
3154 case CHANNEL_A:
3155 case CHANNEL_T:
3156 case CHANNEL_XR:
3157 ee_mode = AR5K_EEPROM_MODE_11A;
3158 break;
3159 case CHANNEL_G:
3160 case CHANNEL_TG:
3161 ee_mode = AR5K_EEPROM_MODE_11G;
3162 break;
3163 case CHANNEL_B:
3164 ee_mode = AR5K_EEPROM_MODE_11B;
3165 break;
3166 default:
3167 ATH5K_ERR(ah->ah_sc,
3168 "invalid channel: %d\n", channel->center_freq);
3169 return -EINVAL;
3170 }
3171
3172 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3173 "changing txpower to %d\n", txpower);
3174
3175 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
3176 }
3177
3178 /*************\
3179 Init function
3180 \*************/
3181
3182 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3183 u8 mode, u8 ee_mode, u8 freq)
3184 {
3185 int ret, i;
3186 u32 phy_tst1;
3187
3188 ret = 0;
3189
3190 /*
3191 * 5211/5212 Specific
3192 */
3193 if (ah->ah_version != AR5K_AR5210) {
3194
3195 /*
3196 * Write initial RF gain settings
3197 * This should work for both 5111/5112
3198 */
3199 ret = ath5k_hw_rfgain_init(ah, freq);
3200 if (ret)
3201 return ret;
3202
3203 mdelay(1);
3204
3205 /*
3206 * Set TX power
3207 */
3208 ret = ath5k_hw_txpower(ah, channel, ee_mode,
3209 ah->ah_txpower.txp_max_pwr / 2);
3210 if (ret)
3211 return ret;
3212
3213 /*
3214 * Write RF buffer
3215 */
3216 ret = ath5k_hw_rfregs_init(ah, channel, mode);
3217 if (ret)
3218 return ret;
3219
3220
3221 /* Write OFDM timings on 5212*/
3222 if (ah->ah_version == AR5K_AR5212 &&
3223 channel->hw_value & CHANNEL_OFDM) {
3224
3225 ret = ath5k_hw_write_ofdm_timings(ah, channel);
3226 if (ret)
3227 return ret;
3228
3229 /* Spur info is available only from EEPROM versions
3230 * greater than 5.3, but the EEPROM routines will use
3231 * static values for older versions */
3232 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
3233 ath5k_hw_set_spur_mitigation_filter(ah,
3234 channel);
3235 }
3236
3237 /*Enable/disable 802.11b mode on 5111
3238 (enable 2111 frequency converter + CCK)*/
3239 if (ah->ah_radio == AR5K_RF5111) {
3240 if (mode == AR5K_MODE_11B)
3241 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
3242 AR5K_TXCFG_B_MODE);
3243 else
3244 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
3245 AR5K_TXCFG_B_MODE);
3246 }
3247
3248 } else {
3249 /*
3250 * For 5210 we do all initialization using
3251 * initvals, so we don't have to modify
3252 * any settings (5210 also only supports
3253 * a/aturbo modes)
3254 */
3255 mdelay(1);
3256 /* Disable phy and wait */
3257 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3258 mdelay(1);
3259 }
3260
3261 /* Set channel on PHY */
3262 ret = ath5k_hw_channel(ah, channel);
3263 if (ret)
3264 return ret;
3265
3266 /*
3267 * Enable the PHY and wait until completion
3268 * This includes BaseBand and Synthesizer
3269 * activation.
3270 */
3271 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
3272
3273 /*
3274 * On 5211+ read activation -> rx delay
3275 * and use it.
3276 *
3277 * TODO: Half/quarter rate support
3278 */
3279 if (ah->ah_version != AR5K_AR5210) {
3280 u32 delay;
3281 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
3282 AR5K_PHY_RX_DELAY_M;
3283 delay = (channel->hw_value & CHANNEL_CCK) ?
3284 ((delay << 2) / 22) : (delay / 10);
3285
3286 udelay(100 + (2 * delay));
3287 } else {
3288 mdelay(1);
3289 }
3290
3291 /*
3292 * Perform ADC test to see if baseband is ready
3293 * Set TX hold and check ADC test register
3294 */
3295 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
3296 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
3297 for (i = 0; i <= 20; i++) {
3298 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
3299 break;
3300 udelay(200);
3301 }
3302 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
3303
3304 /*
3305 * Start automatic gain control calibration
3306 *
3307 * During AGC calibration RX path is re-routed to
3308 * a power detector so we don't receive anything.
3309 *
3310 * This method is used to calibrate some static offsets
3311 * used together with on-the fly I/Q calibration (the
3312 * one performed via ath5k_hw_phy_calibrate), which doesn't
3313 * interrupt rx path.
3314 *
3315 * While rx path is re-routed to the power detector we also
3316 * start a noise floor calibration to measure the
3317 * card's noise floor (the noise we measure when we are not
3318 * transmitting or receiving anything).
3319 *
3320 * If we are in a noisy environment, AGC calibration may time
3321 * out and/or noise floor calibration might timeout.
3322 */
3323 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3324 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
3325
3326 /* At the same time start I/Q calibration for QAM constellation
3327 * -no need for CCK- */
3328 ah->ah_calibration = false;
3329 if (!(mode == AR5K_MODE_11B)) {
3330 ah->ah_calibration = true;
3331 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
3332 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
3333 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
3334 AR5K_PHY_IQ_RUN);
3335 }
3336
3337 /* Wait for gain calibration to finish (we check for I/Q calibration
3338 * during ath5k_phy_calibrate) */
3339 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3340 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3341 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
3342 channel->center_freq);
3343 }
3344
3345 /* Restore antenna mode */
3346 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3347
3348 return ret;
3349 }
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