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Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-kernels.git] / drivers / net / wireless / ath / ath5k / phy.c
1 /*
2 * PHY functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25
26 #include "ath5k.h"
27 #include "reg.h"
28 #include "base.h"
29 #include "rfbuffer.h"
30 #include "rfgain.h"
31
32 /*
33 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
34 */
35 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
36 const struct ath5k_rf_reg *rf_regs,
37 u32 val, u8 reg_id, bool set)
38 {
39 const struct ath5k_rf_reg *rfreg = NULL;
40 u8 offset, bank, num_bits, col, position;
41 u16 entry;
42 u32 mask, data, last_bit, bits_shifted, first_bit;
43 u32 *rfb;
44 s32 bits_left;
45 int i;
46
47 data = 0;
48 rfb = ah->ah_rf_banks;
49
50 for (i = 0; i < ah->ah_rf_regs_count; i++) {
51 if (rf_regs[i].index == reg_id) {
52 rfreg = &rf_regs[i];
53 break;
54 }
55 }
56
57 if (rfb == NULL || rfreg == NULL) {
58 ATH5K_PRINTF("Rf register not found!\n");
59 /* should not happen */
60 return 0;
61 }
62
63 bank = rfreg->bank;
64 num_bits = rfreg->field.len;
65 first_bit = rfreg->field.pos;
66 col = rfreg->field.col;
67
68 /* first_bit is an offset from bank's
69 * start. Since we have all banks on
70 * the same array, we use this offset
71 * to mark each bank's start */
72 offset = ah->ah_offset[bank];
73
74 /* Boundary check */
75 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
76 ATH5K_PRINTF("invalid values at offset %u\n", offset);
77 return 0;
78 }
79
80 entry = ((first_bit - 1) / 8) + offset;
81 position = (first_bit - 1) % 8;
82
83 if (set)
84 data = ath5k_hw_bitswap(val, num_bits);
85
86 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
87 position = 0, entry++) {
88
89 last_bit = (position + bits_left > 8) ? 8 :
90 position + bits_left;
91
92 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
93 (col * 8);
94
95 if (set) {
96 rfb[entry] &= ~mask;
97 rfb[entry] |= ((data << position) << (col * 8)) & mask;
98 data >>= (8 - position);
99 } else {
100 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
101 << bits_shifted;
102 bits_shifted += last_bit - position;
103 }
104
105 bits_left -= 8 - position;
106 }
107
108 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
109
110 return data;
111 }
112
113 /**********************\
114 * RF Gain optimization *
115 \**********************/
116
117 /*
118 * This code is used to optimize rf gain on different environments
119 * (temperature mostly) based on feedback from a power detector.
120 *
121 * It's only used on RF5111 and RF5112, later RF chips seem to have
122 * auto adjustment on hw -notice they have a much smaller BANK 7 and
123 * no gain optimization ladder-.
124 *
125 * For more infos check out this patent doc
126 * http://www.freepatentsonline.com/7400691.html
127 *
128 * This paper describes power drops as seen on the receiver due to
129 * probe packets
130 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
131 * %20of%20Power%20Control.pdf
132 *
133 * And this is the MadWiFi bug entry related to the above
134 * http://madwifi-project.org/ticket/1659
135 * with various measurements and diagrams
136 *
137 * TODO: Deal with power drops due to probes by setting an apropriate
138 * tx power on the probe packets ! Make this part of the calibration process.
139 */
140
141 /* Initialize ah_gain durring attach */
142 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
143 {
144 /* Initialize the gain optimization values */
145 switch (ah->ah_radio) {
146 case AR5K_RF5111:
147 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
148 ah->ah_gain.g_low = 20;
149 ah->ah_gain.g_high = 35;
150 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
151 break;
152 case AR5K_RF5112:
153 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
154 ah->ah_gain.g_low = 20;
155 ah->ah_gain.g_high = 85;
156 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
157 break;
158 default:
159 return -EINVAL;
160 }
161
162 return 0;
163 }
164
165 /* Schedule a gain probe check on the next transmited packet.
166 * That means our next packet is going to be sent with lower
167 * tx power and a Peak to Average Power Detector (PAPD) will try
168 * to measure the gain.
169 *
170 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
171 * just after we enable the probe so that we don't mess with
172 * standard traffic ? Maybe it's time to use sw interrupts and
173 * a probe tasklet !!!
174 */
175 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
176 {
177
178 /* Skip if gain calibration is inactive or
179 * we already handle a probe request */
180 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
181 return;
182
183 /* Send the packet with 2dB below max power as
184 * patent doc suggest */
185 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
186 AR5K_PHY_PAPD_PROBE_TXPOWER) |
187 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
188
189 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
190
191 }
192
193 /* Calculate gain_F measurement correction
194 * based on the current step for RF5112 rev. 2 */
195 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
196 {
197 u32 mix, step;
198 u32 *rf;
199 const struct ath5k_gain_opt *go;
200 const struct ath5k_gain_opt_step *g_step;
201 const struct ath5k_rf_reg *rf_regs;
202
203 /* Only RF5112 Rev. 2 supports it */
204 if ((ah->ah_radio != AR5K_RF5112) ||
205 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
206 return 0;
207
208 go = &rfgain_opt_5112;
209 rf_regs = rf_regs_5112a;
210 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
211
212 g_step = &go->go_step[ah->ah_gain.g_step_idx];
213
214 if (ah->ah_rf_banks == NULL)
215 return 0;
216
217 rf = ah->ah_rf_banks;
218 ah->ah_gain.g_f_corr = 0;
219
220 /* No VGA (Variable Gain Amplifier) override, skip */
221 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
222 return 0;
223
224 /* Mix gain stepping */
225 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
226
227 /* Mix gain override */
228 mix = g_step->gos_param[0];
229
230 switch (mix) {
231 case 3:
232 ah->ah_gain.g_f_corr = step * 2;
233 break;
234 case 2:
235 ah->ah_gain.g_f_corr = (step - 5) * 2;
236 break;
237 case 1:
238 ah->ah_gain.g_f_corr = step;
239 break;
240 default:
241 ah->ah_gain.g_f_corr = 0;
242 break;
243 }
244
245 return ah->ah_gain.g_f_corr;
246 }
247
248 /* Check if current gain_F measurement is in the range of our
249 * power detector windows. If we get a measurement outside range
250 * we know it's not accurate (detectors can't measure anything outside
251 * their detection window) so we must ignore it */
252 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
253 {
254 const struct ath5k_rf_reg *rf_regs;
255 u32 step, mix_ovr, level[4];
256 u32 *rf;
257
258 if (ah->ah_rf_banks == NULL)
259 return false;
260
261 rf = ah->ah_rf_banks;
262
263 if (ah->ah_radio == AR5K_RF5111) {
264
265 rf_regs = rf_regs_5111;
266 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
267
268 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
269 false);
270
271 level[0] = 0;
272 level[1] = (step == 63) ? 50 : step + 4;
273 level[2] = (step != 63) ? 64 : level[0];
274 level[3] = level[2] + 50 ;
275
276 ah->ah_gain.g_high = level[3] -
277 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
278 ah->ah_gain.g_low = level[0] +
279 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
280 } else {
281
282 rf_regs = rf_regs_5112;
283 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
284
285 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
286 false);
287
288 level[0] = level[2] = 0;
289
290 if (mix_ovr == 1) {
291 level[1] = level[3] = 83;
292 } else {
293 level[1] = level[3] = 107;
294 ah->ah_gain.g_high = 55;
295 }
296 }
297
298 return (ah->ah_gain.g_current >= level[0] &&
299 ah->ah_gain.g_current <= level[1]) ||
300 (ah->ah_gain.g_current >= level[2] &&
301 ah->ah_gain.g_current <= level[3]);
302 }
303
304 /* Perform gain_F adjustment by choosing the right set
305 * of parameters from rf gain optimization ladder */
306 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
307 {
308 const struct ath5k_gain_opt *go;
309 const struct ath5k_gain_opt_step *g_step;
310 int ret = 0;
311
312 switch (ah->ah_radio) {
313 case AR5K_RF5111:
314 go = &rfgain_opt_5111;
315 break;
316 case AR5K_RF5112:
317 go = &rfgain_opt_5112;
318 break;
319 default:
320 return 0;
321 }
322
323 g_step = &go->go_step[ah->ah_gain.g_step_idx];
324
325 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
326
327 /* Reached maximum */
328 if (ah->ah_gain.g_step_idx == 0)
329 return -1;
330
331 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
332 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
333 ah->ah_gain.g_step_idx > 0;
334 g_step = &go->go_step[ah->ah_gain.g_step_idx])
335 ah->ah_gain.g_target -= 2 *
336 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
337 g_step->gos_gain);
338
339 ret = 1;
340 goto done;
341 }
342
343 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
344
345 /* Reached minimum */
346 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
347 return -2;
348
349 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
350 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
351 ah->ah_gain.g_step_idx < go->go_steps_count-1;
352 g_step = &go->go_step[ah->ah_gain.g_step_idx])
353 ah->ah_gain.g_target -= 2 *
354 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
355 g_step->gos_gain);
356
357 ret = 2;
358 goto done;
359 }
360
361 done:
362 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
363 "ret %d, gain step %u, current gain %u, target gain %u\n",
364 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
365 ah->ah_gain.g_target);
366
367 return ret;
368 }
369
370 /* Main callback for thermal rf gain calibration engine
371 * Check for a new gain reading and schedule an adjustment
372 * if needed.
373 *
374 * TODO: Use sw interrupt to schedule reset if gain_F needs
375 * adjustment */
376 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
377 {
378 u32 data, type;
379 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
380
381 if (ah->ah_rf_banks == NULL ||
382 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
383 return AR5K_RFGAIN_INACTIVE;
384
385 /* No check requested, either engine is inactive
386 * or an adjustment is already requested */
387 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
388 goto done;
389
390 /* Read the PAPD (Peak to Average Power Detector)
391 * register */
392 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
393
394 /* No probe is scheduled, read gain_F measurement */
395 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
396 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
397 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
398
399 /* If tx packet is CCK correct the gain_F measurement
400 * by cck ofdm gain delta */
401 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
402 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
403 ah->ah_gain.g_current +=
404 ee->ee_cck_ofdm_gain_delta;
405 else
406 ah->ah_gain.g_current +=
407 AR5K_GAIN_CCK_PROBE_CORR;
408 }
409
410 /* Further correct gain_F measurement for
411 * RF5112A radios */
412 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
413 ath5k_hw_rf_gainf_corr(ah);
414 ah->ah_gain.g_current =
415 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
416 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
417 0;
418 }
419
420 /* Check if measurement is ok and if we need
421 * to adjust gain, schedule a gain adjustment,
422 * else switch back to the acive state */
423 if (ath5k_hw_rf_check_gainf_readback(ah) &&
424 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
425 ath5k_hw_rf_gainf_adjust(ah)) {
426 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
427 } else {
428 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
429 }
430 }
431
432 done:
433 return ah->ah_gain.g_state;
434 }
435
436 /* Write initial rf gain table to set the RF sensitivity
437 * this one works on all RF chips and has nothing to do
438 * with gain_F calibration */
439 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
440 {
441 const struct ath5k_ini_rfgain *ath5k_rfg;
442 unsigned int i, size;
443
444 switch (ah->ah_radio) {
445 case AR5K_RF5111:
446 ath5k_rfg = rfgain_5111;
447 size = ARRAY_SIZE(rfgain_5111);
448 break;
449 case AR5K_RF5112:
450 ath5k_rfg = rfgain_5112;
451 size = ARRAY_SIZE(rfgain_5112);
452 break;
453 case AR5K_RF2413:
454 ath5k_rfg = rfgain_2413;
455 size = ARRAY_SIZE(rfgain_2413);
456 break;
457 case AR5K_RF2316:
458 ath5k_rfg = rfgain_2316;
459 size = ARRAY_SIZE(rfgain_2316);
460 break;
461 case AR5K_RF5413:
462 ath5k_rfg = rfgain_5413;
463 size = ARRAY_SIZE(rfgain_5413);
464 break;
465 case AR5K_RF2317:
466 case AR5K_RF2425:
467 ath5k_rfg = rfgain_2425;
468 size = ARRAY_SIZE(rfgain_2425);
469 break;
470 default:
471 return -EINVAL;
472 }
473
474 switch (freq) {
475 case AR5K_INI_RFGAIN_2GHZ:
476 case AR5K_INI_RFGAIN_5GHZ:
477 break;
478 default:
479 return -EINVAL;
480 }
481
482 for (i = 0; i < size; i++) {
483 AR5K_REG_WAIT(i);
484 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
485 (u32)ath5k_rfg[i].rfg_register);
486 }
487
488 return 0;
489 }
490
491
492
493 /********************\
494 * RF Registers setup *
495 \********************/
496
497
498 /*
499 * Setup RF registers by writing rf buffer on hw
500 */
501 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
502 unsigned int mode)
503 {
504 const struct ath5k_rf_reg *rf_regs;
505 const struct ath5k_ini_rfbuffer *ini_rfb;
506 const struct ath5k_gain_opt *go = NULL;
507 const struct ath5k_gain_opt_step *g_step;
508 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
509 u8 ee_mode = 0;
510 u32 *rfb;
511 int i, obdb = -1, bank = -1;
512
513 switch (ah->ah_radio) {
514 case AR5K_RF5111:
515 rf_regs = rf_regs_5111;
516 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
517 ini_rfb = rfb_5111;
518 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
519 go = &rfgain_opt_5111;
520 break;
521 case AR5K_RF5112:
522 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
523 rf_regs = rf_regs_5112a;
524 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
525 ini_rfb = rfb_5112a;
526 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
527 } else {
528 rf_regs = rf_regs_5112;
529 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
530 ini_rfb = rfb_5112;
531 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
532 }
533 go = &rfgain_opt_5112;
534 break;
535 case AR5K_RF2413:
536 rf_regs = rf_regs_2413;
537 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
538 ini_rfb = rfb_2413;
539 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
540 break;
541 case AR5K_RF2316:
542 rf_regs = rf_regs_2316;
543 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
544 ini_rfb = rfb_2316;
545 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
546 break;
547 case AR5K_RF5413:
548 rf_regs = rf_regs_5413;
549 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
550 ini_rfb = rfb_5413;
551 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
552 break;
553 case AR5K_RF2317:
554 rf_regs = rf_regs_2425;
555 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
556 ini_rfb = rfb_2317;
557 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
558 break;
559 case AR5K_RF2425:
560 rf_regs = rf_regs_2425;
561 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
562 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
563 ini_rfb = rfb_2425;
564 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
565 } else {
566 ini_rfb = rfb_2417;
567 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
568 }
569 break;
570 default:
571 return -EINVAL;
572 }
573
574 /* If it's the first time we set rf buffer, allocate
575 * ah->ah_rf_banks based on ah->ah_rf_banks_size
576 * we set above */
577 if (ah->ah_rf_banks == NULL) {
578 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
579 GFP_KERNEL);
580 if (ah->ah_rf_banks == NULL) {
581 ATH5K_ERR(ah->ah_sc, "out of memory\n");
582 return -ENOMEM;
583 }
584 }
585
586 /* Copy values to modify them */
587 rfb = ah->ah_rf_banks;
588
589 for (i = 0; i < ah->ah_rf_banks_size; i++) {
590 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
591 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
592 return -EINVAL;
593 }
594
595 /* Bank changed, write down the offset */
596 if (bank != ini_rfb[i].rfb_bank) {
597 bank = ini_rfb[i].rfb_bank;
598 ah->ah_offset[bank] = i;
599 }
600
601 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
602 }
603
604 /* Set Output and Driver bias current (OB/DB) */
605 if (channel->hw_value & CHANNEL_2GHZ) {
606
607 if (channel->hw_value & CHANNEL_CCK)
608 ee_mode = AR5K_EEPROM_MODE_11B;
609 else
610 ee_mode = AR5K_EEPROM_MODE_11G;
611
612 /* For RF511X/RF211X combination we
613 * use b_OB and b_DB parameters stored
614 * in eeprom on ee->ee_ob[ee_mode][0]
615 *
616 * For all other chips we use OB/DB for 2Ghz
617 * stored in the b/g modal section just like
618 * 802.11a on ee->ee_ob[ee_mode][1] */
619 if ((ah->ah_radio == AR5K_RF5111) ||
620 (ah->ah_radio == AR5K_RF5112))
621 obdb = 0;
622 else
623 obdb = 1;
624
625 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
626 AR5K_RF_OB_2GHZ, true);
627
628 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
629 AR5K_RF_DB_2GHZ, true);
630
631 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
632 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
633 (ah->ah_radio == AR5K_RF5111)) {
634
635 /* For 11a, Turbo and XR we need to choose
636 * OB/DB based on frequency range */
637 ee_mode = AR5K_EEPROM_MODE_11A;
638 obdb = channel->center_freq >= 5725 ? 3 :
639 (channel->center_freq >= 5500 ? 2 :
640 (channel->center_freq >= 5260 ? 1 :
641 (channel->center_freq > 4000 ? 0 : -1)));
642
643 if (obdb < 0)
644 return -EINVAL;
645
646 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
647 AR5K_RF_OB_5GHZ, true);
648
649 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
650 AR5K_RF_DB_5GHZ, true);
651 }
652
653 g_step = &go->go_step[ah->ah_gain.g_step_idx];
654
655 /* Bank Modifications (chip-specific) */
656 if (ah->ah_radio == AR5K_RF5111) {
657
658 /* Set gain_F settings according to current step */
659 if (channel->hw_value & CHANNEL_OFDM) {
660
661 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
662 AR5K_PHY_FRAME_CTL_TX_CLIP,
663 g_step->gos_param[0]);
664
665 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
666 AR5K_RF_PWD_90, true);
667
668 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
669 AR5K_RF_PWD_84, true);
670
671 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
672 AR5K_RF_RFGAIN_SEL, true);
673
674 /* We programmed gain_F parameters, switch back
675 * to active state */
676 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
677
678 }
679
680 /* Bank 6/7 setup */
681
682 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
683 AR5K_RF_PWD_XPD, true);
684
685 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
686 AR5K_RF_XPD_GAIN, true);
687
688 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
689 AR5K_RF_GAIN_I, true);
690
691 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
692 AR5K_RF_PLO_SEL, true);
693
694 /* TODO: Half/quarter channel support */
695 }
696
697 if (ah->ah_radio == AR5K_RF5112) {
698
699 /* Set gain_F settings according to current step */
700 if (channel->hw_value & CHANNEL_OFDM) {
701
702 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
703 AR5K_RF_MIXGAIN_OVR, true);
704
705 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
706 AR5K_RF_PWD_138, true);
707
708 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
709 AR5K_RF_PWD_137, true);
710
711 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
712 AR5K_RF_PWD_136, true);
713
714 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
715 AR5K_RF_PWD_132, true);
716
717 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
718 AR5K_RF_PWD_131, true);
719
720 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
721 AR5K_RF_PWD_130, true);
722
723 /* We programmed gain_F parameters, switch back
724 * to active state */
725 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
726 }
727
728 /* Bank 6/7 setup */
729
730 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
731 AR5K_RF_XPD_SEL, true);
732
733 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
734 /* Rev. 1 supports only one xpd */
735 ath5k_hw_rfb_op(ah, rf_regs,
736 ee->ee_x_gain[ee_mode],
737 AR5K_RF_XPD_GAIN, true);
738
739 } else {
740 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
741 if (ee->ee_pd_gains[ee_mode] > 1) {
742 ath5k_hw_rfb_op(ah, rf_regs,
743 pdg_curve_to_idx[0],
744 AR5K_RF_PD_GAIN_LO, true);
745 ath5k_hw_rfb_op(ah, rf_regs,
746 pdg_curve_to_idx[1],
747 AR5K_RF_PD_GAIN_HI, true);
748 } else {
749 ath5k_hw_rfb_op(ah, rf_regs,
750 pdg_curve_to_idx[0],
751 AR5K_RF_PD_GAIN_LO, true);
752 ath5k_hw_rfb_op(ah, rf_regs,
753 pdg_curve_to_idx[0],
754 AR5K_RF_PD_GAIN_HI, true);
755 }
756
757 /* Lower synth voltage on Rev 2 */
758 ath5k_hw_rfb_op(ah, rf_regs, 2,
759 AR5K_RF_HIGH_VC_CP, true);
760
761 ath5k_hw_rfb_op(ah, rf_regs, 2,
762 AR5K_RF_MID_VC_CP, true);
763
764 ath5k_hw_rfb_op(ah, rf_regs, 2,
765 AR5K_RF_LOW_VC_CP, true);
766
767 ath5k_hw_rfb_op(ah, rf_regs, 2,
768 AR5K_RF_PUSH_UP, true);
769
770 /* Decrease power consumption on 5213+ BaseBand */
771 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
772 ath5k_hw_rfb_op(ah, rf_regs, 1,
773 AR5K_RF_PAD2GND, true);
774
775 ath5k_hw_rfb_op(ah, rf_regs, 1,
776 AR5K_RF_XB2_LVL, true);
777
778 ath5k_hw_rfb_op(ah, rf_regs, 1,
779 AR5K_RF_XB5_LVL, true);
780
781 ath5k_hw_rfb_op(ah, rf_regs, 1,
782 AR5K_RF_PWD_167, true);
783
784 ath5k_hw_rfb_op(ah, rf_regs, 1,
785 AR5K_RF_PWD_166, true);
786 }
787 }
788
789 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
790 AR5K_RF_GAIN_I, true);
791
792 /* TODO: Half/quarter channel support */
793
794 }
795
796 if (ah->ah_radio == AR5K_RF5413 &&
797 channel->hw_value & CHANNEL_2GHZ) {
798
799 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
800 true);
801
802 /* Set optimum value for early revisions (on pci-e chips) */
803 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
804 ah->ah_mac_srev < AR5K_SREV_AR5413)
805 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
806 AR5K_RF_PWD_ICLOBUF_2G, true);
807
808 }
809
810 /* Write RF banks on hw */
811 for (i = 0; i < ah->ah_rf_banks_size; i++) {
812 AR5K_REG_WAIT(i);
813 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
814 }
815
816 return 0;
817 }
818
819
820 /**************************\
821 PHY/RF channel functions
822 \**************************/
823
824 /*
825 * Check if a channel is supported
826 */
827 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
828 {
829 /* Check if the channel is in our supported range */
830 if (flags & CHANNEL_2GHZ) {
831 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
832 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
833 return true;
834 } else if (flags & CHANNEL_5GHZ)
835 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
836 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
837 return true;
838
839 return false;
840 }
841
842 /*
843 * Convertion needed for RF5110
844 */
845 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
846 {
847 u32 athchan;
848
849 /*
850 * Convert IEEE channel/MHz to an internal channel value used
851 * by the AR5210 chipset. This has not been verified with
852 * newer chipsets like the AR5212A who have a completely
853 * different RF/PHY part.
854 */
855 athchan = (ath5k_hw_bitswap(
856 (ieee80211_frequency_to_channel(
857 channel->center_freq) - 24) / 2, 5)
858 << 1) | (1 << 6) | 0x1;
859 return athchan;
860 }
861
862 /*
863 * Set channel on RF5110
864 */
865 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
866 struct ieee80211_channel *channel)
867 {
868 u32 data;
869
870 /*
871 * Set the channel and wait
872 */
873 data = ath5k_hw_rf5110_chan2athchan(channel);
874 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
875 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
876 mdelay(1);
877
878 return 0;
879 }
880
881 /*
882 * Convertion needed for 5111
883 */
884 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
885 struct ath5k_athchan_2ghz *athchan)
886 {
887 int channel;
888
889 /* Cast this value to catch negative channel numbers (>= -19) */
890 channel = (int)ieee;
891
892 /*
893 * Map 2GHz IEEE channel to 5GHz Atheros channel
894 */
895 if (channel <= 13) {
896 athchan->a2_athchan = 115 + channel;
897 athchan->a2_flags = 0x46;
898 } else if (channel == 14) {
899 athchan->a2_athchan = 124;
900 athchan->a2_flags = 0x44;
901 } else if (channel >= 15 && channel <= 26) {
902 athchan->a2_athchan = ((channel - 14) * 4) + 132;
903 athchan->a2_flags = 0x46;
904 } else
905 return -EINVAL;
906
907 return 0;
908 }
909
910 /*
911 * Set channel on 5111
912 */
913 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
914 struct ieee80211_channel *channel)
915 {
916 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
917 unsigned int ath5k_channel =
918 ieee80211_frequency_to_channel(channel->center_freq);
919 u32 data0, data1, clock;
920 int ret;
921
922 /*
923 * Set the channel on the RF5111 radio
924 */
925 data0 = data1 = 0;
926
927 if (channel->hw_value & CHANNEL_2GHZ) {
928 /* Map 2GHz channel to 5GHz Atheros channel ID */
929 ret = ath5k_hw_rf5111_chan2athchan(
930 ieee80211_frequency_to_channel(channel->center_freq),
931 &ath5k_channel_2ghz);
932 if (ret)
933 return ret;
934
935 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
936 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
937 << 5) | (1 << 4);
938 }
939
940 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
941 clock = 1;
942 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
943 (clock << 1) | (1 << 10) | 1;
944 } else {
945 clock = 0;
946 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
947 << 2) | (clock << 1) | (1 << 10) | 1;
948 }
949
950 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
951 AR5K_RF_BUFFER);
952 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
953 AR5K_RF_BUFFER_CONTROL_3);
954
955 return 0;
956 }
957
958 /*
959 * Set channel on 5112 and newer
960 */
961 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
962 struct ieee80211_channel *channel)
963 {
964 u32 data, data0, data1, data2;
965 u16 c;
966
967 data = data0 = data1 = data2 = 0;
968 c = channel->center_freq;
969
970 if (c < 4800) {
971 if (!((c - 2224) % 5)) {
972 data0 = ((2 * (c - 704)) - 3040) / 10;
973 data1 = 1;
974 } else if (!((c - 2192) % 5)) {
975 data0 = ((2 * (c - 672)) - 3040) / 10;
976 data1 = 0;
977 } else
978 return -EINVAL;
979
980 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
981 } else if ((c % 5) != 2 || c > 5435) {
982 if (!(c % 20) && c >= 5120) {
983 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
984 data2 = ath5k_hw_bitswap(3, 2);
985 } else if (!(c % 10)) {
986 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
987 data2 = ath5k_hw_bitswap(2, 2);
988 } else if (!(c % 5)) {
989 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
990 data2 = ath5k_hw_bitswap(1, 2);
991 } else
992 return -EINVAL;
993 } else {
994 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
995 data2 = ath5k_hw_bitswap(0, 2);
996 }
997
998 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
999
1000 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1001 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1002
1003 return 0;
1004 }
1005
1006 /*
1007 * Set the channel on the RF2425
1008 */
1009 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1010 struct ieee80211_channel *channel)
1011 {
1012 u32 data, data0, data2;
1013 u16 c;
1014
1015 data = data0 = data2 = 0;
1016 c = channel->center_freq;
1017
1018 if (c < 4800) {
1019 data0 = ath5k_hw_bitswap((c - 2272), 8);
1020 data2 = 0;
1021 /* ? 5GHz ? */
1022 } else if ((c % 5) != 2 || c > 5435) {
1023 if (!(c % 20) && c < 5120)
1024 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1025 else if (!(c % 10))
1026 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1027 else if (!(c % 5))
1028 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1029 else
1030 return -EINVAL;
1031 data2 = ath5k_hw_bitswap(1, 2);
1032 } else {
1033 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1034 data2 = ath5k_hw_bitswap(0, 2);
1035 }
1036
1037 data = (data0 << 4) | data2 << 2 | 0x1001;
1038
1039 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1040 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1041
1042 return 0;
1043 }
1044
1045 /*
1046 * Set a channel on the radio chip
1047 */
1048 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1049 {
1050 int ret;
1051 /*
1052 * Check bounds supported by the PHY (we don't care about regultory
1053 * restrictions at this point). Note: hw_value already has the band
1054 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1055 * of the band by that */
1056 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1057 ATH5K_ERR(ah->ah_sc,
1058 "channel frequency (%u MHz) out of supported "
1059 "band range\n",
1060 channel->center_freq);
1061 return -EINVAL;
1062 }
1063
1064 /*
1065 * Set the channel and wait
1066 */
1067 switch (ah->ah_radio) {
1068 case AR5K_RF5110:
1069 ret = ath5k_hw_rf5110_channel(ah, channel);
1070 break;
1071 case AR5K_RF5111:
1072 ret = ath5k_hw_rf5111_channel(ah, channel);
1073 break;
1074 case AR5K_RF2425:
1075 ret = ath5k_hw_rf2425_channel(ah, channel);
1076 break;
1077 default:
1078 ret = ath5k_hw_rf5112_channel(ah, channel);
1079 break;
1080 }
1081
1082 if (ret)
1083 return ret;
1084
1085 /* Set JAPAN setting for channel 14 */
1086 if (channel->center_freq == 2484) {
1087 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1088 AR5K_PHY_CCKTXCTL_JAPAN);
1089 } else {
1090 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1091 AR5K_PHY_CCKTXCTL_WORLD);
1092 }
1093
1094 ah->ah_current_channel = channel;
1095 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1096
1097 return 0;
1098 }
1099
1100 /*****************\
1101 PHY calibration
1102 \*****************/
1103
1104 static int sign_extend(int val, const int nbits)
1105 {
1106 int order = BIT(nbits-1);
1107 return (val ^ order) - order;
1108 }
1109
1110 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1111 {
1112 s32 val;
1113
1114 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1115 return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
1116 }
1117
1118 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1119 {
1120 int i;
1121
1122 ah->ah_nfcal_hist.index = 0;
1123 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1124 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1125 }
1126
1127 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1128 {
1129 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1130 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1131 hist->nfval[hist->index] = noise_floor;
1132 }
1133
1134 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1135 {
1136 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1137 s16 tmp;
1138 int i, j;
1139
1140 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1141 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1142 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1143 if (sort[j] > sort[j-1]) {
1144 tmp = sort[j];
1145 sort[j] = sort[j-1];
1146 sort[j-1] = tmp;
1147 }
1148 }
1149 }
1150 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1151 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1152 "cal %d:%d\n", i, sort[i]);
1153 }
1154 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1155 }
1156
1157 /*
1158 * When we tell the hardware to perform a noise floor calibration
1159 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1160 * sample-and-hold the minimum noise level seen at the antennas.
1161 * This value is then stored in a ring buffer of recently measured
1162 * noise floor values so we have a moving window of the last few
1163 * samples.
1164 *
1165 * The median of the values in the history is then loaded into the
1166 * hardware for its own use for RSSI and CCA measurements.
1167 */
1168 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1169 {
1170 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1171 u32 val;
1172 s16 nf, threshold;
1173 u8 ee_mode;
1174
1175 /* keep last value if calibration hasn't completed */
1176 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1177 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1178 "NF did not complete in calibration window\n");
1179
1180 return;
1181 }
1182
1183 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1184 case CHANNEL_A:
1185 case CHANNEL_T:
1186 case CHANNEL_XR:
1187 ee_mode = AR5K_EEPROM_MODE_11A;
1188 break;
1189 case CHANNEL_G:
1190 case CHANNEL_TG:
1191 ee_mode = AR5K_EEPROM_MODE_11G;
1192 break;
1193 default:
1194 case CHANNEL_B:
1195 ee_mode = AR5K_EEPROM_MODE_11B;
1196 break;
1197 }
1198
1199
1200 /* completed NF calibration, test threshold */
1201 nf = ath5k_hw_read_measured_noise_floor(ah);
1202 threshold = ee->ee_noise_floor_thr[ee_mode];
1203
1204 if (nf > threshold) {
1205 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1206 "noise floor failure detected; "
1207 "read %d, threshold %d\n",
1208 nf, threshold);
1209
1210 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1211 }
1212
1213 ath5k_hw_update_nfcal_hist(ah, nf);
1214 nf = ath5k_hw_get_median_noise_floor(ah);
1215
1216 /* load noise floor (in .5 dBm) so the hardware will use it */
1217 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1218 val |= (nf * 2) & AR5K_PHY_NF_M;
1219 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1220
1221 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1222 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1223
1224 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1225 0, false);
1226
1227 /*
1228 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1229 * so that we're not capped by the median we just loaded.
1230 * This will be used as the initial value for the next noise
1231 * floor calibration.
1232 */
1233 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1234 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1235 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1236 AR5K_PHY_AGCCTL_NF_EN |
1237 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1238 AR5K_PHY_AGCCTL_NF);
1239
1240 ah->ah_noise_floor = nf;
1241
1242 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1243 "noise floor calibrated: %d\n", nf);
1244 }
1245
1246 /*
1247 * Perform a PHY calibration on RF5110
1248 * -Fix BPSK/QAM Constellation (I/Q correction)
1249 */
1250 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1251 struct ieee80211_channel *channel)
1252 {
1253 u32 phy_sig, phy_agc, phy_sat, beacon;
1254 int ret;
1255
1256 /*
1257 * Disable beacons and RX/TX queues, wait
1258 */
1259 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1260 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1261 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1262 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1263
1264 mdelay(2);
1265
1266 /*
1267 * Set the channel (with AGC turned off)
1268 */
1269 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1270 udelay(10);
1271 ret = ath5k_hw_channel(ah, channel);
1272
1273 /*
1274 * Activate PHY and wait
1275 */
1276 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1277 mdelay(1);
1278
1279 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1280
1281 if (ret)
1282 return ret;
1283
1284 /*
1285 * Calibrate the radio chip
1286 */
1287
1288 /* Remember normal state */
1289 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1290 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1291 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1292
1293 /* Update radio registers */
1294 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1295 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1296
1297 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1298 AR5K_PHY_AGCCOARSE_LO)) |
1299 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1300 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1301
1302 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1303 AR5K_PHY_ADCSAT_THR)) |
1304 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1305 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1306
1307 udelay(20);
1308
1309 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1310 udelay(10);
1311 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1312 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1313
1314 mdelay(1);
1315
1316 /*
1317 * Enable calibration and wait until completion
1318 */
1319 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1320
1321 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1322 AR5K_PHY_AGCCTL_CAL, 0, false);
1323
1324 /* Reset to normal state */
1325 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1326 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1327 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1328
1329 if (ret) {
1330 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1331 channel->center_freq);
1332 return ret;
1333 }
1334
1335 /*
1336 * Re-enable RX/TX and beacons
1337 */
1338 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1339 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1340 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1341
1342 return 0;
1343 }
1344
1345 /*
1346 * Perform I/Q calibration on RF5111/5112 and newer chips
1347 */
1348 static int
1349 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1350 {
1351 u32 i_pwr, q_pwr;
1352 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1353 int i;
1354
1355 if (!ah->ah_calibration ||
1356 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1357 return 0;
1358
1359 /* Calibration has finished, get the results and re-run */
1360 /* work around empty results which can apparently happen on 5212 */
1361 for (i = 0; i <= 10; i++) {
1362 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1363 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1364 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1365 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1366 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1367 if (i_pwr && q_pwr)
1368 break;
1369 }
1370
1371 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1372
1373 if (ah->ah_version == AR5K_AR5211)
1374 q_coffd = q_pwr >> 6;
1375 else
1376 q_coffd = q_pwr >> 7;
1377
1378 /* protect against divide by 0 and loss of sign bits */
1379 if (i_coffd == 0 || q_coffd < 2)
1380 return -1;
1381
1382 i_coff = (-iq_corr) / i_coffd;
1383 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1384
1385 if (ah->ah_version == AR5K_AR5211)
1386 q_coff = (i_pwr / q_coffd) - 64;
1387 else
1388 q_coff = (i_pwr / q_coffd) - 128;
1389 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1390
1391 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1392 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1393 i_coff, q_coff, i_coffd, q_coffd);
1394
1395 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1396 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1397 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1398 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1399
1400 /* Re-enable calibration -if we don't we'll commit
1401 * the same values again and again */
1402 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1403 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1404 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1405
1406 return 0;
1407 }
1408
1409 /*
1410 * Perform a PHY calibration
1411 */
1412 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1413 struct ieee80211_channel *channel)
1414 {
1415 int ret;
1416
1417 if (ah->ah_radio == AR5K_RF5110)
1418 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1419 else {
1420 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1421 ath5k_hw_request_rfgain_probe(ah);
1422 }
1423
1424 return ret;
1425 }
1426
1427 /***************************\
1428 * Spur mitigation functions *
1429 \***************************/
1430
1431 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1432 struct ieee80211_channel *channel)
1433 {
1434 u8 refclk_freq;
1435
1436 if ((ah->ah_radio == AR5K_RF5112) ||
1437 (ah->ah_radio == AR5K_RF5413) ||
1438 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1439 refclk_freq = 40;
1440 else
1441 refclk_freq = 32;
1442
1443 if ((channel->center_freq % refclk_freq != 0) &&
1444 ((channel->center_freq % refclk_freq < 10) ||
1445 (channel->center_freq % refclk_freq > 22)))
1446 return true;
1447 else
1448 return false;
1449 }
1450
1451 void
1452 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1453 struct ieee80211_channel *channel)
1454 {
1455 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1456 u32 mag_mask[4] = {0, 0, 0, 0};
1457 u32 pilot_mask[2] = {0, 0};
1458 /* Note: fbin values are scaled up by 2 */
1459 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1460 s32 spur_delta_phase, spur_freq_sigma_delta;
1461 s32 spur_offset, num_symbols_x16;
1462 u8 num_symbol_offsets, i, freq_band;
1463
1464 /* Convert current frequency to fbin value (the same way channels
1465 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1466 * up by 2 so we can compare it later */
1467 if (channel->hw_value & CHANNEL_2GHZ) {
1468 chan_fbin = (channel->center_freq - 2300) * 10;
1469 freq_band = AR5K_EEPROM_BAND_2GHZ;
1470 } else {
1471 chan_fbin = (channel->center_freq - 4900) * 10;
1472 freq_band = AR5K_EEPROM_BAND_5GHZ;
1473 }
1474
1475 /* Check if any spur_chan_fbin from EEPROM is
1476 * within our current channel's spur detection range */
1477 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1478 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1479 /* XXX: Half/Quarter channels ?*/
1480 if (channel->hw_value & CHANNEL_TURBO)
1481 spur_detection_window *= 2;
1482
1483 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1484 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1485
1486 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1487 * so it's zero if we got nothing from EEPROM */
1488 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1489 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1490 break;
1491 }
1492
1493 if ((chan_fbin - spur_detection_window <=
1494 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1495 (chan_fbin + spur_detection_window >=
1496 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1497 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1498 break;
1499 }
1500 }
1501
1502 /* We need to enable spur filter for this channel */
1503 if (spur_chan_fbin) {
1504 spur_offset = spur_chan_fbin - chan_fbin;
1505 /*
1506 * Calculate deltas:
1507 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1508 * spur_delta_phase -> spur_offset / chip_freq << 11
1509 * Note: Both values have 100KHz resolution
1510 */
1511 /* XXX: Half/Quarter rate channels ? */
1512 switch (channel->hw_value) {
1513 case CHANNEL_A:
1514 /* Both sample_freq and chip_freq are 40MHz */
1515 spur_delta_phase = (spur_offset << 17) / 25;
1516 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1517 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1518 break;
1519 case CHANNEL_G:
1520 /* sample_freq -> 40MHz chip_freq -> 44MHz
1521 * (for b compatibility) */
1522 spur_freq_sigma_delta = (spur_offset << 8) / 55;
1523 spur_delta_phase = (spur_offset << 17) / 25;
1524 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1525 break;
1526 case CHANNEL_T:
1527 case CHANNEL_TG:
1528 /* Both sample_freq and chip_freq are 80MHz */
1529 spur_delta_phase = (spur_offset << 16) / 25;
1530 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1531 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1532 break;
1533 default:
1534 return;
1535 }
1536
1537 /* Calculate pilot and magnitude masks */
1538
1539 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1540 * and divide by symbol_width to find how many symbols we have
1541 * Note: number of symbols is scaled up by 16 */
1542 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1543
1544 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1545 if (!(num_symbols_x16 & 0xF))
1546 /* _X_ */
1547 num_symbol_offsets = 3;
1548 else
1549 /* _xx_ */
1550 num_symbol_offsets = 4;
1551
1552 for (i = 0; i < num_symbol_offsets; i++) {
1553
1554 /* Calculate pilot mask */
1555 s32 curr_sym_off =
1556 (num_symbols_x16 / 16) + i + 25;
1557
1558 /* Pilot magnitude mask seems to be a way to
1559 * declare the boundaries for our detection
1560 * window or something, it's 2 for the middle
1561 * value(s) where the symbol is expected to be
1562 * and 1 on the boundary values */
1563 u8 plt_mag_map =
1564 (i == 0 || i == (num_symbol_offsets - 1))
1565 ? 1 : 2;
1566
1567 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1568 if (curr_sym_off <= 25)
1569 pilot_mask[0] |= 1 << curr_sym_off;
1570 else if (curr_sym_off >= 27)
1571 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1572 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1573 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1574
1575 /* Calculate magnitude mask (for viterbi decoder) */
1576 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1577 mag_mask[0] |=
1578 plt_mag_map << (curr_sym_off + 1) * 2;
1579 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1580 mag_mask[1] |=
1581 plt_mag_map << (curr_sym_off - 15) * 2;
1582 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1583 mag_mask[2] |=
1584 plt_mag_map << (curr_sym_off - 31) * 2;
1585 else if (curr_sym_off >= 46 && curr_sym_off <= 53)
1586 mag_mask[3] |=
1587 plt_mag_map << (curr_sym_off - 47) * 2;
1588
1589 }
1590
1591 /* Write settings on hw to enable spur filter */
1592 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1593 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1594 /* XXX: Self correlator also ? */
1595 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1596 AR5K_PHY_IQ_PILOT_MASK_EN |
1597 AR5K_PHY_IQ_CHAN_MASK_EN |
1598 AR5K_PHY_IQ_SPUR_FILT_EN);
1599
1600 /* Set delta phase and freq sigma delta */
1601 ath5k_hw_reg_write(ah,
1602 AR5K_REG_SM(spur_delta_phase,
1603 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1604 AR5K_REG_SM(spur_freq_sigma_delta,
1605 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1606 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1607 AR5K_PHY_TIMING_11);
1608
1609 /* Write pilot masks */
1610 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1611 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1612 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1613 pilot_mask[1]);
1614
1615 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1616 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1617 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1618 pilot_mask[1]);
1619
1620 /* Write magnitude masks */
1621 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1622 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1623 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1624 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1625 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1626 mag_mask[3]);
1627
1628 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1629 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1630 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1631 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1632 AR5K_PHY_BIN_MASK2_4_MASK_4,
1633 mag_mask[3]);
1634
1635 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1636 AR5K_PHY_IQ_SPUR_FILT_EN) {
1637 /* Clean up spur mitigation settings and disable fliter */
1638 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1639 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1640 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1641 AR5K_PHY_IQ_PILOT_MASK_EN |
1642 AR5K_PHY_IQ_CHAN_MASK_EN |
1643 AR5K_PHY_IQ_SPUR_FILT_EN);
1644 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1645
1646 /* Clear pilot masks */
1647 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1648 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1649 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1650 0);
1651
1652 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1653 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1654 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1655 0);
1656
1657 /* Clear magnitude masks */
1658 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1659 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1660 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1661 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1662 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1663 0);
1664
1665 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1666 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1667 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1668 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1669 AR5K_PHY_BIN_MASK2_4_MASK_4,
1670 0);
1671 }
1672 }
1673
1674 /********************\
1675 Misc PHY functions
1676 \********************/
1677
1678 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1679 {
1680 /*Just a try M.F.*/
1681 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1682
1683 return 0;
1684 }
1685
1686 /*
1687 * Get the PHY Chip revision
1688 */
1689 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1690 {
1691 unsigned int i;
1692 u32 srev;
1693 u16 ret;
1694
1695 /*
1696 * Set the radio chip access register
1697 */
1698 switch (chan) {
1699 case CHANNEL_2GHZ:
1700 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1701 break;
1702 case CHANNEL_5GHZ:
1703 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1704 break;
1705 default:
1706 return 0;
1707 }
1708
1709 mdelay(2);
1710
1711 /* ...wait until PHY is ready and read the selected radio revision */
1712 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1713
1714 for (i = 0; i < 8; i++)
1715 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1716
1717 if (ah->ah_version == AR5K_AR5210) {
1718 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1719 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1720 } else {
1721 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1722 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1723 ((srev & 0x0f) << 4), 8);
1724 }
1725
1726 /* Reset to the 5GHz mode */
1727 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1728
1729 return ret;
1730 }
1731
1732 /*****************\
1733 * Antenna control *
1734 \*****************/
1735
1736 static void /*TODO:Boundary check*/
1737 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1738 {
1739 if (ah->ah_version != AR5K_AR5210)
1740 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1741 }
1742
1743 /*
1744 * Enable/disable fast rx antenna diversity
1745 */
1746 static void
1747 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1748 {
1749 switch (ee_mode) {
1750 case AR5K_EEPROM_MODE_11G:
1751 /* XXX: This is set to
1752 * disabled on initvals !!! */
1753 case AR5K_EEPROM_MODE_11A:
1754 if (enable)
1755 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1756 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1757 else
1758 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1759 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1760 break;
1761 case AR5K_EEPROM_MODE_11B:
1762 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1763 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1764 break;
1765 default:
1766 return;
1767 }
1768
1769 if (enable) {
1770 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1771 AR5K_PHY_RESTART_DIV_GC, 4);
1772
1773 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1774 AR5K_PHY_FAST_ANT_DIV_EN);
1775 } else {
1776 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1777 AR5K_PHY_RESTART_DIV_GC, 0);
1778
1779 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1780 AR5K_PHY_FAST_ANT_DIV_EN);
1781 }
1782 }
1783
1784 void
1785 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1786 {
1787 u8 ant0, ant1;
1788
1789 /*
1790 * In case a fixed antenna was set as default
1791 * use the same switch table twice.
1792 */
1793 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1794 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1795 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1796 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1797 else {
1798 ant0 = AR5K_ANT_SWTABLE_A;
1799 ant1 = AR5K_ANT_SWTABLE_B;
1800 }
1801
1802 /* Set antenna idle switch table */
1803 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1804 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1805 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1806 AR5K_PHY_ANT_CTL_TXRX_EN));
1807
1808 /* Set antenna switch tables */
1809 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1810 AR5K_PHY_ANT_SWITCH_TABLE_0);
1811 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1812 AR5K_PHY_ANT_SWITCH_TABLE_1);
1813 }
1814
1815 /*
1816 * Set antenna operating mode
1817 */
1818 void
1819 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1820 {
1821 struct ieee80211_channel *channel = ah->ah_current_channel;
1822 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1823 bool use_def_for_sg;
1824 u8 def_ant, tx_ant, ee_mode;
1825 u32 sta_id1 = 0;
1826
1827 /* if channel is not initialized yet we can't set the antennas
1828 * so just store the mode. it will be set on the next reset */
1829 if (channel == NULL) {
1830 ah->ah_ant_mode = ant_mode;
1831 return;
1832 }
1833
1834 def_ant = ah->ah_def_ant;
1835
1836 switch (channel->hw_value & CHANNEL_MODES) {
1837 case CHANNEL_A:
1838 case CHANNEL_T:
1839 case CHANNEL_XR:
1840 ee_mode = AR5K_EEPROM_MODE_11A;
1841 break;
1842 case CHANNEL_G:
1843 case CHANNEL_TG:
1844 ee_mode = AR5K_EEPROM_MODE_11G;
1845 break;
1846 case CHANNEL_B:
1847 ee_mode = AR5K_EEPROM_MODE_11B;
1848 break;
1849 default:
1850 ATH5K_ERR(ah->ah_sc,
1851 "invalid channel: %d\n", channel->center_freq);
1852 return;
1853 }
1854
1855 switch (ant_mode) {
1856 case AR5K_ANTMODE_DEFAULT:
1857 tx_ant = 0;
1858 use_def_for_tx = false;
1859 update_def_on_tx = false;
1860 use_def_for_rts = false;
1861 use_def_for_sg = false;
1862 fast_div = true;
1863 break;
1864 case AR5K_ANTMODE_FIXED_A:
1865 def_ant = 1;
1866 tx_ant = 1;
1867 use_def_for_tx = true;
1868 update_def_on_tx = false;
1869 use_def_for_rts = true;
1870 use_def_for_sg = true;
1871 fast_div = false;
1872 break;
1873 case AR5K_ANTMODE_FIXED_B:
1874 def_ant = 2;
1875 tx_ant = 2;
1876 use_def_for_tx = true;
1877 update_def_on_tx = false;
1878 use_def_for_rts = true;
1879 use_def_for_sg = true;
1880 fast_div = false;
1881 break;
1882 case AR5K_ANTMODE_SINGLE_AP:
1883 def_ant = 1; /* updated on tx */
1884 tx_ant = 0;
1885 use_def_for_tx = true;
1886 update_def_on_tx = true;
1887 use_def_for_rts = true;
1888 use_def_for_sg = true;
1889 fast_div = true;
1890 break;
1891 case AR5K_ANTMODE_SECTOR_AP:
1892 tx_ant = 1; /* variable */
1893 use_def_for_tx = false;
1894 update_def_on_tx = false;
1895 use_def_for_rts = true;
1896 use_def_for_sg = false;
1897 fast_div = false;
1898 break;
1899 case AR5K_ANTMODE_SECTOR_STA:
1900 tx_ant = 1; /* variable */
1901 use_def_for_tx = true;
1902 update_def_on_tx = false;
1903 use_def_for_rts = true;
1904 use_def_for_sg = false;
1905 fast_div = true;
1906 break;
1907 case AR5K_ANTMODE_DEBUG:
1908 def_ant = 1;
1909 tx_ant = 2;
1910 use_def_for_tx = false;
1911 update_def_on_tx = false;
1912 use_def_for_rts = false;
1913 use_def_for_sg = false;
1914 fast_div = false;
1915 break;
1916 default:
1917 return;
1918 }
1919
1920 ah->ah_tx_ant = tx_ant;
1921 ah->ah_ant_mode = ant_mode;
1922 ah->ah_def_ant = def_ant;
1923
1924 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1925 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1926 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1927 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1928
1929 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1930
1931 if (sta_id1)
1932 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1933
1934 ath5k_hw_set_antenna_switch(ah, ee_mode);
1935 /* Note: set diversity before default antenna
1936 * because it won't work correctly */
1937 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1938 ath5k_hw_set_def_antenna(ah, def_ant);
1939 }
1940
1941
1942 /****************\
1943 * TX power setup *
1944 \****************/
1945
1946 /*
1947 * Helper functions
1948 */
1949
1950 /*
1951 * Do linear interpolation between two given (x, y) points
1952 */
1953 static s16
1954 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1955 s16 y_left, s16 y_right)
1956 {
1957 s16 ratio, result;
1958
1959 /* Avoid divide by zero and skip interpolation
1960 * if we have the same point */
1961 if ((x_left == x_right) || (y_left == y_right))
1962 return y_left;
1963
1964 /*
1965 * Since we use ints and not fps, we need to scale up in
1966 * order to get a sane ratio value (or else we 'll eg. get
1967 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1968 * to have some accuracy both for 0.5 and 0.25 steps.
1969 */
1970 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1971
1972 /* Now scale down to be in range */
1973 result = y_left + (ratio * (target - x_left) / 100);
1974
1975 return result;
1976 }
1977
1978 /*
1979 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1980 *
1981 * Since we have the top of the curve and we draw the line below
1982 * until we reach 1 (1 pcdac step) we need to know which point
1983 * (x value) that is so that we don't go below y axis and have negative
1984 * pcdac values when creating the curve, or fill the table with zeroes.
1985 */
1986 static s16
1987 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1988 const s16 *pwrL, const s16 *pwrR)
1989 {
1990 s8 tmp;
1991 s16 min_pwrL, min_pwrR;
1992 s16 pwr_i;
1993
1994 /* Some vendors write the same pcdac value twice !!! */
1995 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
1996 return max(pwrL[0], pwrR[0]);
1997
1998 if (pwrL[0] == pwrL[1])
1999 min_pwrL = pwrL[0];
2000 else {
2001 pwr_i = pwrL[0];
2002 do {
2003 pwr_i--;
2004 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2005 pwrL[0], pwrL[1],
2006 stepL[0], stepL[1]);
2007 } while (tmp > 1);
2008
2009 min_pwrL = pwr_i;
2010 }
2011
2012 if (pwrR[0] == pwrR[1])
2013 min_pwrR = pwrR[0];
2014 else {
2015 pwr_i = pwrR[0];
2016 do {
2017 pwr_i--;
2018 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2019 pwrR[0], pwrR[1],
2020 stepR[0], stepR[1]);
2021 } while (tmp > 1);
2022
2023 min_pwrR = pwr_i;
2024 }
2025
2026 /* Keep the right boundary so that it works for both curves */
2027 return max(min_pwrL, min_pwrR);
2028 }
2029
2030 /*
2031 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2032 * Power to PCDAC curve.
2033 *
2034 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2035 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2036 * PCDAC/PDADC step for each curve is 64 but we can write more than
2037 * one curves on hw so we can go up to 128 (which is the max step we
2038 * can write on the final table).
2039 *
2040 * We write y values (PCDAC/PDADC steps) on hw.
2041 */
2042 static void
2043 ath5k_create_power_curve(s16 pmin, s16 pmax,
2044 const s16 *pwr, const u8 *vpd,
2045 u8 num_points,
2046 u8 *vpd_table, u8 type)
2047 {
2048 u8 idx[2] = { 0, 1 };
2049 s16 pwr_i = 2*pmin;
2050 int i;
2051
2052 if (num_points < 2)
2053 return;
2054
2055 /* We want the whole line, so adjust boundaries
2056 * to cover the entire power range. Note that
2057 * power values are already 0.25dB so no need
2058 * to multiply pwr_i by 2 */
2059 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2060 pwr_i = pmin;
2061 pmin = 0;
2062 pmax = 63;
2063 }
2064
2065 /* Find surrounding turning points (TPs)
2066 * and interpolate between them */
2067 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2068 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2069
2070 /* We passed the right TP, move to the next set of TPs
2071 * if we pass the last TP, extrapolate above using the last
2072 * two TPs for ratio */
2073 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2074 idx[0]++;
2075 idx[1]++;
2076 }
2077
2078 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2079 pwr[idx[0]], pwr[idx[1]],
2080 vpd[idx[0]], vpd[idx[1]]);
2081
2082 /* Increase by 0.5dB
2083 * (0.25 dB units) */
2084 pwr_i += 2;
2085 }
2086 }
2087
2088 /*
2089 * Get the surrounding per-channel power calibration piers
2090 * for a given frequency so that we can interpolate between
2091 * them and come up with an apropriate dataset for our current
2092 * channel.
2093 */
2094 static void
2095 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2096 struct ieee80211_channel *channel,
2097 struct ath5k_chan_pcal_info **pcinfo_l,
2098 struct ath5k_chan_pcal_info **pcinfo_r)
2099 {
2100 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2101 struct ath5k_chan_pcal_info *pcinfo;
2102 u8 idx_l, idx_r;
2103 u8 mode, max, i;
2104 u32 target = channel->center_freq;
2105
2106 idx_l = 0;
2107 idx_r = 0;
2108
2109 if (!(channel->hw_value & CHANNEL_OFDM)) {
2110 pcinfo = ee->ee_pwr_cal_b;
2111 mode = AR5K_EEPROM_MODE_11B;
2112 } else if (channel->hw_value & CHANNEL_2GHZ) {
2113 pcinfo = ee->ee_pwr_cal_g;
2114 mode = AR5K_EEPROM_MODE_11G;
2115 } else {
2116 pcinfo = ee->ee_pwr_cal_a;
2117 mode = AR5K_EEPROM_MODE_11A;
2118 }
2119 max = ee->ee_n_piers[mode] - 1;
2120
2121 /* Frequency is below our calibrated
2122 * range. Use the lowest power curve
2123 * we have */
2124 if (target < pcinfo[0].freq) {
2125 idx_l = idx_r = 0;
2126 goto done;
2127 }
2128
2129 /* Frequency is above our calibrated
2130 * range. Use the highest power curve
2131 * we have */
2132 if (target > pcinfo[max].freq) {
2133 idx_l = idx_r = max;
2134 goto done;
2135 }
2136
2137 /* Frequency is inside our calibrated
2138 * channel range. Pick the surrounding
2139 * calibration piers so that we can
2140 * interpolate */
2141 for (i = 0; i <= max; i++) {
2142
2143 /* Frequency matches one of our calibration
2144 * piers, no need to interpolate, just use
2145 * that calibration pier */
2146 if (pcinfo[i].freq == target) {
2147 idx_l = idx_r = i;
2148 goto done;
2149 }
2150
2151 /* We found a calibration pier that's above
2152 * frequency, use this pier and the previous
2153 * one to interpolate */
2154 if (target < pcinfo[i].freq) {
2155 idx_r = i;
2156 idx_l = idx_r - 1;
2157 goto done;
2158 }
2159 }
2160
2161 done:
2162 *pcinfo_l = &pcinfo[idx_l];
2163 *pcinfo_r = &pcinfo[idx_r];
2164 }
2165
2166 /*
2167 * Get the surrounding per-rate power calibration data
2168 * for a given frequency and interpolate between power
2169 * values to set max target power supported by hw for
2170 * each rate.
2171 */
2172 static void
2173 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2174 struct ieee80211_channel *channel,
2175 struct ath5k_rate_pcal_info *rates)
2176 {
2177 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2178 struct ath5k_rate_pcal_info *rpinfo;
2179 u8 idx_l, idx_r;
2180 u8 mode, max, i;
2181 u32 target = channel->center_freq;
2182
2183 idx_l = 0;
2184 idx_r = 0;
2185
2186 if (!(channel->hw_value & CHANNEL_OFDM)) {
2187 rpinfo = ee->ee_rate_tpwr_b;
2188 mode = AR5K_EEPROM_MODE_11B;
2189 } else if (channel->hw_value & CHANNEL_2GHZ) {
2190 rpinfo = ee->ee_rate_tpwr_g;
2191 mode = AR5K_EEPROM_MODE_11G;
2192 } else {
2193 rpinfo = ee->ee_rate_tpwr_a;
2194 mode = AR5K_EEPROM_MODE_11A;
2195 }
2196 max = ee->ee_rate_target_pwr_num[mode] - 1;
2197
2198 /* Get the surrounding calibration
2199 * piers - same as above */
2200 if (target < rpinfo[0].freq) {
2201 idx_l = idx_r = 0;
2202 goto done;
2203 }
2204
2205 if (target > rpinfo[max].freq) {
2206 idx_l = idx_r = max;
2207 goto done;
2208 }
2209
2210 for (i = 0; i <= max; i++) {
2211
2212 if (rpinfo[i].freq == target) {
2213 idx_l = idx_r = i;
2214 goto done;
2215 }
2216
2217 if (target < rpinfo[i].freq) {
2218 idx_r = i;
2219 idx_l = idx_r - 1;
2220 goto done;
2221 }
2222 }
2223
2224 done:
2225 /* Now interpolate power value, based on the frequency */
2226 rates->freq = target;
2227
2228 rates->target_power_6to24 =
2229 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2230 rpinfo[idx_r].freq,
2231 rpinfo[idx_l].target_power_6to24,
2232 rpinfo[idx_r].target_power_6to24);
2233
2234 rates->target_power_36 =
2235 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2236 rpinfo[idx_r].freq,
2237 rpinfo[idx_l].target_power_36,
2238 rpinfo[idx_r].target_power_36);
2239
2240 rates->target_power_48 =
2241 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2242 rpinfo[idx_r].freq,
2243 rpinfo[idx_l].target_power_48,
2244 rpinfo[idx_r].target_power_48);
2245
2246 rates->target_power_54 =
2247 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2248 rpinfo[idx_r].freq,
2249 rpinfo[idx_l].target_power_54,
2250 rpinfo[idx_r].target_power_54);
2251 }
2252
2253 /*
2254 * Get the max edge power for this channel if
2255 * we have such data from EEPROM's Conformance Test
2256 * Limits (CTL), and limit max power if needed.
2257 */
2258 static void
2259 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2260 struct ieee80211_channel *channel)
2261 {
2262 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2263 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2264 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2265 u8 *ctl_val = ee->ee_ctl;
2266 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2267 s16 edge_pwr = 0;
2268 u8 rep_idx;
2269 u8 i, ctl_mode;
2270 u8 ctl_idx = 0xFF;
2271 u32 target = channel->center_freq;
2272
2273 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2274
2275 switch (channel->hw_value & CHANNEL_MODES) {
2276 case CHANNEL_A:
2277 ctl_mode |= AR5K_CTL_11A;
2278 break;
2279 case CHANNEL_G:
2280 ctl_mode |= AR5K_CTL_11G;
2281 break;
2282 case CHANNEL_B:
2283 ctl_mode |= AR5K_CTL_11B;
2284 break;
2285 case CHANNEL_T:
2286 ctl_mode |= AR5K_CTL_TURBO;
2287 break;
2288 case CHANNEL_TG:
2289 ctl_mode |= AR5K_CTL_TURBOG;
2290 break;
2291 case CHANNEL_XR:
2292 /* Fall through */
2293 default:
2294 return;
2295 }
2296
2297 for (i = 0; i < ee->ee_ctls; i++) {
2298 if (ctl_val[i] == ctl_mode) {
2299 ctl_idx = i;
2300 break;
2301 }
2302 }
2303
2304 /* If we have a CTL dataset available grab it and find the
2305 * edge power for our frequency */
2306 if (ctl_idx == 0xFF)
2307 return;
2308
2309 /* Edge powers are sorted by frequency from lower
2310 * to higher. Each CTL corresponds to 8 edge power
2311 * measurements. */
2312 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2313
2314 /* Don't do boundaries check because we
2315 * might have more that one bands defined
2316 * for this mode */
2317
2318 /* Get the edge power that's closer to our
2319 * frequency */
2320 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2321 rep_idx += i;
2322 if (target <= rep[rep_idx].freq)
2323 edge_pwr = (s16) rep[rep_idx].edge;
2324 }
2325
2326 if (edge_pwr)
2327 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2328 }
2329
2330
2331 /*
2332 * Power to PCDAC table functions
2333 */
2334
2335 /*
2336 * Fill Power to PCDAC table on RF5111
2337 *
2338 * No further processing is needed for RF5111, the only thing we have to
2339 * do is fill the values below and above calibration range since eeprom data
2340 * may not cover the entire PCDAC table.
2341 */
2342 static void
2343 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2344 s16 *table_max)
2345 {
2346 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2347 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2348 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2349 s16 min_pwr, max_pwr;
2350
2351 /* Get table boundaries */
2352 min_pwr = table_min[0];
2353 pcdac_0 = pcdac_tmp[0];
2354
2355 max_pwr = table_max[0];
2356 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2357
2358 /* Extrapolate below minimum using pcdac_0 */
2359 pcdac_i = 0;
2360 for (i = 0; i < min_pwr; i++)
2361 pcdac_out[pcdac_i++] = pcdac_0;
2362
2363 /* Copy values from pcdac_tmp */
2364 pwr_idx = min_pwr;
2365 for (i = 0 ; pwr_idx <= max_pwr &&
2366 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2367 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2368 pwr_idx++;
2369 }
2370
2371 /* Extrapolate above maximum */
2372 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2373 pcdac_out[pcdac_i++] = pcdac_n;
2374
2375 }
2376
2377 /*
2378 * Combine available XPD Curves and fill Linear Power to PCDAC table
2379 * on RF5112
2380 *
2381 * RFX112 can have up to 2 curves (one for low txpower range and one for
2382 * higher txpower range). We need to put them both on pcdac_out and place
2383 * them in the correct location. In case we only have one curve available
2384 * just fit it on pcdac_out (it's supposed to cover the entire range of
2385 * available pwr levels since it's always the higher power curve). Extrapolate
2386 * below and above final table if needed.
2387 */
2388 static void
2389 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2390 s16 *table_max, u8 pdcurves)
2391 {
2392 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2393 u8 *pcdac_low_pwr;
2394 u8 *pcdac_high_pwr;
2395 u8 *pcdac_tmp;
2396 u8 pwr;
2397 s16 max_pwr_idx;
2398 s16 min_pwr_idx;
2399 s16 mid_pwr_idx = 0;
2400 /* Edge flag turs on the 7nth bit on the PCDAC
2401 * to delcare the higher power curve (force values
2402 * to be greater than 64). If we only have one curve
2403 * we don't need to set this, if we have 2 curves and
2404 * fill the table backwards this can also be used to
2405 * switch from higher power curve to lower power curve */
2406 u8 edge_flag;
2407 int i;
2408
2409 /* When we have only one curve available
2410 * that's the higher power curve. If we have
2411 * two curves the first is the high power curve
2412 * and the next is the low power curve. */
2413 if (pdcurves > 1) {
2414 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2415 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2416 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2417 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2418
2419 /* If table size goes beyond 31.5dB, keep the
2420 * upper 31.5dB range when setting tx power.
2421 * Note: 126 = 31.5 dB in quarter dB steps */
2422 if (table_max[0] - table_min[1] > 126)
2423 min_pwr_idx = table_max[0] - 126;
2424 else
2425 min_pwr_idx = table_min[1];
2426
2427 /* Since we fill table backwards
2428 * start from high power curve */
2429 pcdac_tmp = pcdac_high_pwr;
2430
2431 edge_flag = 0x40;
2432 } else {
2433 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2434 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2435 min_pwr_idx = table_min[0];
2436 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2437 pcdac_tmp = pcdac_high_pwr;
2438 edge_flag = 0;
2439 }
2440
2441 /* This is used when setting tx power*/
2442 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2443
2444 /* Fill Power to PCDAC table backwards */
2445 pwr = max_pwr_idx;
2446 for (i = 63; i >= 0; i--) {
2447 /* Entering lower power range, reset
2448 * edge flag and set pcdac_tmp to lower
2449 * power curve.*/
2450 if (edge_flag == 0x40 &&
2451 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2452 edge_flag = 0x00;
2453 pcdac_tmp = pcdac_low_pwr;
2454 pwr = mid_pwr_idx/2;
2455 }
2456
2457 /* Don't go below 1, extrapolate below if we have
2458 * already swithced to the lower power curve -or
2459 * we only have one curve and edge_flag is zero
2460 * anyway */
2461 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2462 while (i >= 0) {
2463 pcdac_out[i] = pcdac_out[i + 1];
2464 i--;
2465 }
2466 break;
2467 }
2468
2469 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2470
2471 /* Extrapolate above if pcdac is greater than
2472 * 126 -this can happen because we OR pcdac_out
2473 * value with edge_flag on high power curve */
2474 if (pcdac_out[i] > 126)
2475 pcdac_out[i] = 126;
2476
2477 /* Decrease by a 0.5dB step */
2478 pwr--;
2479 }
2480 }
2481
2482 /* Write PCDAC values on hw */
2483 static void
2484 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2485 {
2486 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2487 int i;
2488
2489 /*
2490 * Write TX power values
2491 */
2492 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2493 ath5k_hw_reg_write(ah,
2494 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2495 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2496 AR5K_PHY_PCDAC_TXPOWER(i));
2497 }
2498 }
2499
2500
2501 /*
2502 * Power to PDADC table functions
2503 */
2504
2505 /*
2506 * Set the gain boundaries and create final Power to PDADC table
2507 *
2508 * We can have up to 4 pd curves, we need to do a simmilar process
2509 * as we do for RF5112. This time we don't have an edge_flag but we
2510 * set the gain boundaries on a separate register.
2511 */
2512 static void
2513 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2514 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2515 {
2516 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2517 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2518 u8 *pdadc_tmp;
2519 s16 pdadc_0;
2520 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2521 u8 pd_gain_overlap;
2522
2523 /* Note: Register value is initialized on initvals
2524 * there is no feedback from hw.
2525 * XXX: What about pd_gain_overlap from EEPROM ? */
2526 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2527 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2528
2529 /* Create final PDADC table */
2530 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2531 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2532
2533 if (pdg == pdcurves - 1)
2534 /* 2 dB boundary stretch for last
2535 * (higher power) curve */
2536 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2537 else
2538 /* Set gain boundary in the middle
2539 * between this curve and the next one */
2540 gain_boundaries[pdg] =
2541 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2542
2543 /* Sanity check in case our 2 db stretch got out of
2544 * range. */
2545 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2546 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2547
2548 /* For the first curve (lower power)
2549 * start from 0 dB */
2550 if (pdg == 0)
2551 pdadc_0 = 0;
2552 else
2553 /* For the other curves use the gain overlap */
2554 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2555 pd_gain_overlap;
2556
2557 /* Force each power step to be at least 0.5 dB */
2558 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2559 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2560 else
2561 pwr_step = 1;
2562
2563 /* If pdadc_0 is negative, we need to extrapolate
2564 * below this pdgain by a number of pwr_steps */
2565 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2566 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2567 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2568 pdadc_0++;
2569 }
2570
2571 /* Set last pwr level, using gain boundaries */
2572 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2573 /* Limit it to be inside pwr range */
2574 table_size = pwr_max[pdg] - pwr_min[pdg];
2575 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2576
2577 /* Fill pdadc_out table */
2578 while (pdadc_0 < max_idx && pdadc_i < 128)
2579 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2580
2581 /* Need to extrapolate above this pdgain? */
2582 if (pdadc_n <= max_idx)
2583 continue;
2584
2585 /* Force each power step to be at least 0.5 dB */
2586 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2587 pwr_step = pdadc_tmp[table_size - 1] -
2588 pdadc_tmp[table_size - 2];
2589 else
2590 pwr_step = 1;
2591
2592 /* Extrapolate above */
2593 while ((pdadc_0 < (s16) pdadc_n) &&
2594 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2595 s16 tmp = pdadc_tmp[table_size - 1] +
2596 (pdadc_0 - max_idx) * pwr_step;
2597 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2598 pdadc_0++;
2599 }
2600 }
2601
2602 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2603 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2604 pdg++;
2605 }
2606
2607 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2608 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2609 pdadc_i++;
2610 }
2611
2612 /* Set gain boundaries */
2613 ath5k_hw_reg_write(ah,
2614 AR5K_REG_SM(pd_gain_overlap,
2615 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2616 AR5K_REG_SM(gain_boundaries[0],
2617 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2618 AR5K_REG_SM(gain_boundaries[1],
2619 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2620 AR5K_REG_SM(gain_boundaries[2],
2621 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2622 AR5K_REG_SM(gain_boundaries[3],
2623 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2624 AR5K_PHY_TPC_RG5);
2625
2626 /* Used for setting rate power table */
2627 ah->ah_txpower.txp_min_idx = pwr_min[0];
2628
2629 }
2630
2631 /* Write PDADC values on hw */
2632 static void
2633 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2634 u8 pdcurves, u8 *pdg_to_idx)
2635 {
2636 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2637 u32 reg;
2638 u8 i;
2639
2640 /* Select the right pdgain curves */
2641
2642 /* Clear current settings */
2643 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2644 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2645 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2646 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2647 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2648
2649 /*
2650 * Use pd_gains curve from eeprom
2651 *
2652 * This overrides the default setting from initvals
2653 * in case some vendors (e.g. Zcomax) don't use the default
2654 * curves. If we don't honor their settings we 'll get a
2655 * 5dB (1 * gain overlap ?) drop.
2656 */
2657 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2658
2659 switch (pdcurves) {
2660 case 3:
2661 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2662 /* Fall through */
2663 case 2:
2664 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2665 /* Fall through */
2666 case 1:
2667 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2668 break;
2669 }
2670 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2671
2672 /*
2673 * Write TX power values
2674 */
2675 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2676 ath5k_hw_reg_write(ah,
2677 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2678 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2679 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2680 ((pdadc_out[4*i + 3] & 0xff) << 24),
2681 AR5K_PHY_PDADC_TXPOWER(i));
2682 }
2683 }
2684
2685
2686 /*
2687 * Common code for PCDAC/PDADC tables
2688 */
2689
2690 /*
2691 * This is the main function that uses all of the above
2692 * to set PCDAC/PDADC table on hw for the current channel.
2693 * This table is used for tx power calibration on the basband,
2694 * without it we get weird tx power levels and in some cases
2695 * distorted spectral mask
2696 */
2697 static int
2698 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2699 struct ieee80211_channel *channel,
2700 u8 ee_mode, u8 type)
2701 {
2702 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2703 struct ath5k_chan_pcal_info *pcinfo_L;
2704 struct ath5k_chan_pcal_info *pcinfo_R;
2705 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2706 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2707 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2708 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2709 u8 *tmpL;
2710 u8 *tmpR;
2711 u32 target = channel->center_freq;
2712 int pdg, i;
2713
2714 /* Get surounding freq piers for this channel */
2715 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2716 &pcinfo_L,
2717 &pcinfo_R);
2718
2719 /* Loop over pd gain curves on
2720 * surounding freq piers by index */
2721 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2722
2723 /* Fill curves in reverse order
2724 * from lower power (max gain)
2725 * to higher power. Use curve -> idx
2726 * backmapping we did on eeprom init */
2727 u8 idx = pdg_curve_to_idx[pdg];
2728
2729 /* Grab the needed curves by index */
2730 pdg_L = &pcinfo_L->pd_curves[idx];
2731 pdg_R = &pcinfo_R->pd_curves[idx];
2732
2733 /* Initialize the temp tables */
2734 tmpL = ah->ah_txpower.tmpL[pdg];
2735 tmpR = ah->ah_txpower.tmpR[pdg];
2736
2737 /* Set curve's x boundaries and create
2738 * curves so that they cover the same
2739 * range (if we don't do that one table
2740 * will have values on some range and the
2741 * other one won't have any so interpolation
2742 * will fail) */
2743 table_min[pdg] = min(pdg_L->pd_pwr[0],
2744 pdg_R->pd_pwr[0]) / 2;
2745
2746 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2747 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2748
2749 /* Now create the curves on surrounding channels
2750 * and interpolate if needed to get the final
2751 * curve for this gain on this channel */
2752 switch (type) {
2753 case AR5K_PWRTABLE_LINEAR_PCDAC:
2754 /* Override min/max so that we don't loose
2755 * accuracy (don't divide by 2) */
2756 table_min[pdg] = min(pdg_L->pd_pwr[0],
2757 pdg_R->pd_pwr[0]);
2758
2759 table_max[pdg] =
2760 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2761 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2762
2763 /* Override minimum so that we don't get
2764 * out of bounds while extrapolating
2765 * below. Don't do this when we have 2
2766 * curves and we are on the high power curve
2767 * because table_min is ok in this case */
2768 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2769
2770 table_min[pdg] =
2771 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2772 pdg_R->pd_step,
2773 pdg_L->pd_pwr,
2774 pdg_R->pd_pwr);
2775
2776 /* Don't go too low because we will
2777 * miss the upper part of the curve.
2778 * Note: 126 = 31.5dB (max power supported)
2779 * in 0.25dB units */
2780 if (table_max[pdg] - table_min[pdg] > 126)
2781 table_min[pdg] = table_max[pdg] - 126;
2782 }
2783
2784 /* Fall through */
2785 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2786 case AR5K_PWRTABLE_PWR_TO_PDADC:
2787
2788 ath5k_create_power_curve(table_min[pdg],
2789 table_max[pdg],
2790 pdg_L->pd_pwr,
2791 pdg_L->pd_step,
2792 pdg_L->pd_points, tmpL, type);
2793
2794 /* We are in a calibration
2795 * pier, no need to interpolate
2796 * between freq piers */
2797 if (pcinfo_L == pcinfo_R)
2798 continue;
2799
2800 ath5k_create_power_curve(table_min[pdg],
2801 table_max[pdg],
2802 pdg_R->pd_pwr,
2803 pdg_R->pd_step,
2804 pdg_R->pd_points, tmpR, type);
2805 break;
2806 default:
2807 return -EINVAL;
2808 }
2809
2810 /* Interpolate between curves
2811 * of surounding freq piers to
2812 * get the final curve for this
2813 * pd gain. Re-use tmpL for interpolation
2814 * output */
2815 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2816 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2817 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2818 (s16) pcinfo_L->freq,
2819 (s16) pcinfo_R->freq,
2820 (s16) tmpL[i],
2821 (s16) tmpR[i]);
2822 }
2823 }
2824
2825 /* Now we have a set of curves for this
2826 * channel on tmpL (x range is table_max - table_min
2827 * and y values are tmpL[pdg][]) sorted in the same
2828 * order as EEPROM (because we've used the backmapping).
2829 * So for RF5112 it's from higher power to lower power
2830 * and for RF2413 it's from lower power to higher power.
2831 * For RF5111 we only have one curve. */
2832
2833 /* Fill min and max power levels for this
2834 * channel by interpolating the values on
2835 * surounding channels to complete the dataset */
2836 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2837 (s16) pcinfo_L->freq,
2838 (s16) pcinfo_R->freq,
2839 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2840
2841 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2842 (s16) pcinfo_L->freq,
2843 (s16) pcinfo_R->freq,
2844 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2845
2846 /* We are ready to go, fill PCDAC/PDADC
2847 * table and write settings on hardware */
2848 switch (type) {
2849 case AR5K_PWRTABLE_LINEAR_PCDAC:
2850 /* For RF5112 we can have one or two curves
2851 * and each curve covers a certain power lvl
2852 * range so we need to do some more processing */
2853 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2854 ee->ee_pd_gains[ee_mode]);
2855
2856 /* Set txp.offset so that we can
2857 * match max power value with max
2858 * table index */
2859 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2860
2861 /* Write settings on hw */
2862 ath5k_setup_pcdac_table(ah);
2863 break;
2864 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2865 /* We are done for RF5111 since it has only
2866 * one curve, just fit the curve on the table */
2867 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2868
2869 /* No rate powertable adjustment for RF5111 */
2870 ah->ah_txpower.txp_min_idx = 0;
2871 ah->ah_txpower.txp_offset = 0;
2872
2873 /* Write settings on hw */
2874 ath5k_setup_pcdac_table(ah);
2875 break;
2876 case AR5K_PWRTABLE_PWR_TO_PDADC:
2877 /* Set PDADC boundaries and fill
2878 * final PDADC table */
2879 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2880 ee->ee_pd_gains[ee_mode]);
2881
2882 /* Write settings on hw */
2883 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2884
2885 /* Set txp.offset, note that table_min
2886 * can be negative */
2887 ah->ah_txpower.txp_offset = table_min[0];
2888 break;
2889 default:
2890 return -EINVAL;
2891 }
2892
2893 return 0;
2894 }
2895
2896
2897 /*
2898 * Per-rate tx power setting
2899 *
2900 * This is the code that sets the desired tx power (below
2901 * maximum) on hw for each rate (we also have TPC that sets
2902 * power per packet). We do that by providing an index on the
2903 * PCDAC/PDADC table we set up.
2904 */
2905
2906 /*
2907 * Set rate power table
2908 *
2909 * For now we only limit txpower based on maximum tx power
2910 * supported by hw (what's inside rate_info). We need to limit
2911 * this even more, based on regulatory domain etc.
2912 *
2913 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2914 * and is indexed as follows:
2915 * rates[0] - rates[7] -> OFDM rates
2916 * rates[8] - rates[14] -> CCK rates
2917 * rates[15] -> XR rates (they all have the same power)
2918 */
2919 static void
2920 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2921 struct ath5k_rate_pcal_info *rate_info,
2922 u8 ee_mode)
2923 {
2924 unsigned int i;
2925 u16 *rates;
2926
2927 /* max_pwr is power level we got from driver/user in 0.5dB
2928 * units, switch to 0.25dB units so we can compare */
2929 max_pwr *= 2;
2930 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2931
2932 /* apply rate limits */
2933 rates = ah->ah_txpower.txp_rates_power_table;
2934
2935 /* OFDM rates 6 to 24Mb/s */
2936 for (i = 0; i < 5; i++)
2937 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2938
2939 /* Rest OFDM rates */
2940 rates[5] = min(rates[0], rate_info->target_power_36);
2941 rates[6] = min(rates[0], rate_info->target_power_48);
2942 rates[7] = min(rates[0], rate_info->target_power_54);
2943
2944 /* CCK rates */
2945 /* 1L */
2946 rates[8] = min(rates[0], rate_info->target_power_6to24);
2947 /* 2L */
2948 rates[9] = min(rates[0], rate_info->target_power_36);
2949 /* 2S */
2950 rates[10] = min(rates[0], rate_info->target_power_36);
2951 /* 5L */
2952 rates[11] = min(rates[0], rate_info->target_power_48);
2953 /* 5S */
2954 rates[12] = min(rates[0], rate_info->target_power_48);
2955 /* 11L */
2956 rates[13] = min(rates[0], rate_info->target_power_54);
2957 /* 11S */
2958 rates[14] = min(rates[0], rate_info->target_power_54);
2959
2960 /* XR rates */
2961 rates[15] = min(rates[0], rate_info->target_power_6to24);
2962
2963 /* CCK rates have different peak to average ratio
2964 * so we have to tweak their power so that gainf
2965 * correction works ok. For this we use OFDM to
2966 * CCK delta from eeprom */
2967 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2968 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2969 for (i = 8; i <= 15; i++)
2970 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2971
2972 /* Now that we have all rates setup use table offset to
2973 * match the power range set by user with the power indices
2974 * on PCDAC/PDADC table */
2975 for (i = 0; i < 16; i++) {
2976 rates[i] += ah->ah_txpower.txp_offset;
2977 /* Don't get out of bounds */
2978 if (rates[i] > 63)
2979 rates[i] = 63;
2980 }
2981
2982 /* Min/max in 0.25dB units */
2983 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2984 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
2985 ah->ah_txpower.txp_ofdm = rates[7];
2986 }
2987
2988
2989 /*
2990 * Set transmition power
2991 */
2992 int
2993 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2994 u8 ee_mode, u8 txpower)
2995 {
2996 struct ath5k_rate_pcal_info rate_info;
2997 u8 type;
2998 int ret;
2999
3000 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3001 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3002 return -EINVAL;
3003 }
3004
3005 /* Reset TX power values */
3006 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3007 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3008 ah->ah_txpower.txp_min_pwr = 0;
3009 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3010
3011 /* Initialize TX power table */
3012 switch (ah->ah_radio) {
3013 case AR5K_RF5111:
3014 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3015 break;
3016 case AR5K_RF5112:
3017 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3018 break;
3019 case AR5K_RF2413:
3020 case AR5K_RF5413:
3021 case AR5K_RF2316:
3022 case AR5K_RF2317:
3023 case AR5K_RF2425:
3024 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3025 break;
3026 default:
3027 return -EINVAL;
3028 }
3029
3030 /* FIXME: Only on channel/mode change */
3031 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3032 if (ret)
3033 return ret;
3034
3035 /* Limit max power if we have a CTL available */
3036 ath5k_get_max_ctl_power(ah, channel);
3037
3038 /* FIXME: Tx power limit for this regdomain
3039 * XXX: Mac80211/CRDA will do that anyway ? */
3040
3041 /* FIXME: Antenna reduction stuff */
3042
3043 /* FIXME: Limit power on turbo modes */
3044
3045 /* FIXME: TPC scale reduction */
3046
3047 /* Get surounding channels for per-rate power table
3048 * calibration */
3049 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3050
3051 /* Setup rate power table */
3052 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3053
3054 /* Write rate power table on hw */
3055 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3056 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3057 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3058
3059 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3060 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3061 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3062
3063 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3064 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3065 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3066
3067 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3068 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3069 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3070
3071 /* FIXME: TPC support */
3072 if (ah->ah_txpower.txp_tpc) {
3073 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3074 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3075
3076 ath5k_hw_reg_write(ah,
3077 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3078 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3079 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3080 AR5K_TPC);
3081 } else {
3082 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3083 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3084 }
3085
3086 return 0;
3087 }
3088
3089 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3090 {
3091 /*Just a try M.F.*/
3092 struct ieee80211_channel *channel = ah->ah_current_channel;
3093 u8 ee_mode;
3094
3095 switch (channel->hw_value & CHANNEL_MODES) {
3096 case CHANNEL_A:
3097 case CHANNEL_T:
3098 case CHANNEL_XR:
3099 ee_mode = AR5K_EEPROM_MODE_11A;
3100 break;
3101 case CHANNEL_G:
3102 case CHANNEL_TG:
3103 ee_mode = AR5K_EEPROM_MODE_11G;
3104 break;
3105 case CHANNEL_B:
3106 ee_mode = AR5K_EEPROM_MODE_11B;
3107 break;
3108 default:
3109 ATH5K_ERR(ah->ah_sc,
3110 "invalid channel: %d\n", channel->center_freq);
3111 return -EINVAL;
3112 }
3113
3114 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3115 "changing txpower to %d\n", txpower);
3116
3117 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
3118 }
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