4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/delay.h>
24 #include <linux/slab.h>
33 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
35 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw
*ah
,
36 const struct ath5k_rf_reg
*rf_regs
,
37 u32 val
, u8 reg_id
, bool set
)
39 const struct ath5k_rf_reg
*rfreg
= NULL
;
40 u8 offset
, bank
, num_bits
, col
, position
;
42 u32 mask
, data
, last_bit
, bits_shifted
, first_bit
;
48 rfb
= ah
->ah_rf_banks
;
50 for (i
= 0; i
< ah
->ah_rf_regs_count
; i
++) {
51 if (rf_regs
[i
].index
== reg_id
) {
57 if (rfb
== NULL
|| rfreg
== NULL
) {
58 ATH5K_PRINTF("Rf register not found!\n");
59 /* should not happen */
64 num_bits
= rfreg
->field
.len
;
65 first_bit
= rfreg
->field
.pos
;
66 col
= rfreg
->field
.col
;
68 /* first_bit is an offset from bank's
69 * start. Since we have all banks on
70 * the same array, we use this offset
71 * to mark each bank's start */
72 offset
= ah
->ah_offset
[bank
];
75 if (!(col
<= 3 && num_bits
<= 32 && first_bit
+ num_bits
<= 319)) {
76 ATH5K_PRINTF("invalid values at offset %u\n", offset
);
80 entry
= ((first_bit
- 1) / 8) + offset
;
81 position
= (first_bit
- 1) % 8;
84 data
= ath5k_hw_bitswap(val
, num_bits
);
86 for (bits_shifted
= 0, bits_left
= num_bits
; bits_left
> 0;
87 position
= 0, entry
++) {
89 last_bit
= (position
+ bits_left
> 8) ? 8 :
92 mask
= (((1 << last_bit
) - 1) ^ ((1 << position
) - 1)) <<
97 rfb
[entry
] |= ((data
<< position
) << (col
* 8)) & mask
;
98 data
>>= (8 - position
);
100 data
|= (((rfb
[entry
] & mask
) >> (col
* 8)) >> position
)
102 bits_shifted
+= last_bit
- position
;
105 bits_left
-= 8 - position
;
108 data
= set
? 1 : ath5k_hw_bitswap(data
, num_bits
);
113 /**********************\
114 * RF Gain optimization *
115 \**********************/
118 * This code is used to optimize RF gain on different environments
119 * (temperature mostly) based on feedback from a power detector.
121 * It's only used on RF5111 and RF5112, later RF chips seem to have
122 * auto adjustment on hw -notice they have a much smaller BANK 7 and
123 * no gain optimization ladder-.
125 * For more infos check out this patent doc
126 * http://www.freepatentsonline.com/7400691.html
128 * This paper describes power drops as seen on the receiver due to
130 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
131 * %20of%20Power%20Control.pdf
133 * And this is the MadWiFi bug entry related to the above
134 * http://madwifi-project.org/ticket/1659
135 * with various measurements and diagrams
137 * TODO: Deal with power drops due to probes by setting an apropriate
138 * tx power on the probe packets ! Make this part of the calibration process.
141 /* Initialize ah_gain durring attach */
142 int ath5k_hw_rfgain_opt_init(struct ath5k_hw
*ah
)
144 /* Initialize the gain optimization values */
145 switch (ah
->ah_radio
) {
147 ah
->ah_gain
.g_step_idx
= rfgain_opt_5111
.go_default
;
148 ah
->ah_gain
.g_low
= 20;
149 ah
->ah_gain
.g_high
= 35;
150 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
153 ah
->ah_gain
.g_step_idx
= rfgain_opt_5112
.go_default
;
154 ah
->ah_gain
.g_low
= 20;
155 ah
->ah_gain
.g_high
= 85;
156 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
165 /* Schedule a gain probe check on the next transmited packet.
166 * That means our next packet is going to be sent with lower
167 * tx power and a Peak to Average Power Detector (PAPD) will try
168 * to measure the gain.
170 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
171 * just after we enable the probe so that we don't mess with
172 * standard traffic ? Maybe it's time to use sw interrupts and
173 * a probe tasklet !!!
175 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw
*ah
)
178 /* Skip if gain calibration is inactive or
179 * we already handle a probe request */
180 if (ah
->ah_gain
.g_state
!= AR5K_RFGAIN_ACTIVE
)
183 /* Send the packet with 2dB below max power as
184 * patent doc suggest */
185 ath5k_hw_reg_write(ah
, AR5K_REG_SM(ah
->ah_txpower
.txp_ofdm
- 4,
186 AR5K_PHY_PAPD_PROBE_TXPOWER
) |
187 AR5K_PHY_PAPD_PROBE_TX_NEXT
, AR5K_PHY_PAPD_PROBE
);
189 ah
->ah_gain
.g_state
= AR5K_RFGAIN_READ_REQUESTED
;
193 /* Calculate gain_F measurement correction
194 * based on the current step for RF5112 rev. 2 */
195 static u32
ath5k_hw_rf_gainf_corr(struct ath5k_hw
*ah
)
199 const struct ath5k_gain_opt
*go
;
200 const struct ath5k_gain_opt_step
*g_step
;
201 const struct ath5k_rf_reg
*rf_regs
;
203 /* Only RF5112 Rev. 2 supports it */
204 if ((ah
->ah_radio
!= AR5K_RF5112
) ||
205 (ah
->ah_radio_5ghz_revision
<= AR5K_SREV_RAD_5112A
))
208 go
= &rfgain_opt_5112
;
209 rf_regs
= rf_regs_5112a
;
210 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112a
);
212 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
214 if (ah
->ah_rf_banks
== NULL
)
217 rf
= ah
->ah_rf_banks
;
218 ah
->ah_gain
.g_f_corr
= 0;
220 /* No VGA (Variable Gain Amplifier) override, skip */
221 if (ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXVGA_OVR
, false) != 1)
224 /* Mix gain stepping */
225 step
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXGAIN_STEP
, false);
227 /* Mix gain override */
228 mix
= g_step
->gos_param
[0];
232 ah
->ah_gain
.g_f_corr
= step
* 2;
235 ah
->ah_gain
.g_f_corr
= (step
- 5) * 2;
238 ah
->ah_gain
.g_f_corr
= step
;
241 ah
->ah_gain
.g_f_corr
= 0;
245 return ah
->ah_gain
.g_f_corr
;
248 /* Check if current gain_F measurement is in the range of our
249 * power detector windows. If we get a measurement outside range
250 * we know it's not accurate (detectors can't measure anything outside
251 * their detection window) so we must ignore it */
252 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw
*ah
)
254 const struct ath5k_rf_reg
*rf_regs
;
255 u32 step
, mix_ovr
, level
[4];
258 if (ah
->ah_rf_banks
== NULL
)
261 rf
= ah
->ah_rf_banks
;
263 if (ah
->ah_radio
== AR5K_RF5111
) {
265 rf_regs
= rf_regs_5111
;
266 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5111
);
268 step
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_RFGAIN_STEP
,
272 level
[1] = (step
== 63) ? 50 : step
+ 4;
273 level
[2] = (step
!= 63) ? 64 : level
[0];
274 level
[3] = level
[2] + 50 ;
276 ah
->ah_gain
.g_high
= level
[3] -
277 (step
== 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN
: -5);
278 ah
->ah_gain
.g_low
= level
[0] +
279 (step
== 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN
: 0);
282 rf_regs
= rf_regs_5112
;
283 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112
);
285 mix_ovr
= ath5k_hw_rfb_op(ah
, rf_regs
, 0, AR5K_RF_MIXVGA_OVR
,
288 level
[0] = level
[2] = 0;
291 level
[1] = level
[3] = 83;
293 level
[1] = level
[3] = 107;
294 ah
->ah_gain
.g_high
= 55;
298 return (ah
->ah_gain
.g_current
>= level
[0] &&
299 ah
->ah_gain
.g_current
<= level
[1]) ||
300 (ah
->ah_gain
.g_current
>= level
[2] &&
301 ah
->ah_gain
.g_current
<= level
[3]);
304 /* Perform gain_F adjustment by choosing the right set
305 * of parameters from RF gain optimization ladder */
306 static s8
ath5k_hw_rf_gainf_adjust(struct ath5k_hw
*ah
)
308 const struct ath5k_gain_opt
*go
;
309 const struct ath5k_gain_opt_step
*g_step
;
312 switch (ah
->ah_radio
) {
314 go
= &rfgain_opt_5111
;
317 go
= &rfgain_opt_5112
;
323 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
325 if (ah
->ah_gain
.g_current
>= ah
->ah_gain
.g_high
) {
327 /* Reached maximum */
328 if (ah
->ah_gain
.g_step_idx
== 0)
331 for (ah
->ah_gain
.g_target
= ah
->ah_gain
.g_current
;
332 ah
->ah_gain
.g_target
>= ah
->ah_gain
.g_high
&&
333 ah
->ah_gain
.g_step_idx
> 0;
334 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
])
335 ah
->ah_gain
.g_target
-= 2 *
336 (go
->go_step
[--(ah
->ah_gain
.g_step_idx
)].gos_gain
-
343 if (ah
->ah_gain
.g_current
<= ah
->ah_gain
.g_low
) {
345 /* Reached minimum */
346 if (ah
->ah_gain
.g_step_idx
== (go
->go_steps_count
- 1))
349 for (ah
->ah_gain
.g_target
= ah
->ah_gain
.g_current
;
350 ah
->ah_gain
.g_target
<= ah
->ah_gain
.g_low
&&
351 ah
->ah_gain
.g_step_idx
< go
->go_steps_count
-1;
352 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
])
353 ah
->ah_gain
.g_target
-= 2 *
354 (go
->go_step
[++ah
->ah_gain
.g_step_idx
].gos_gain
-
362 ATH5K_DBG(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
363 "ret %d, gain step %u, current gain %u, target gain %u\n",
364 ret
, ah
->ah_gain
.g_step_idx
, ah
->ah_gain
.g_current
,
365 ah
->ah_gain
.g_target
);
370 /* Main callback for thermal RF gain calibration engine
371 * Check for a new gain reading and schedule an adjustment
374 * TODO: Use sw interrupt to schedule reset if gain_F needs
376 enum ath5k_rfgain
ath5k_hw_gainf_calibrate(struct ath5k_hw
*ah
)
379 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
381 if (ah
->ah_rf_banks
== NULL
||
382 ah
->ah_gain
.g_state
== AR5K_RFGAIN_INACTIVE
)
383 return AR5K_RFGAIN_INACTIVE
;
385 /* No check requested, either engine is inactive
386 * or an adjustment is already requested */
387 if (ah
->ah_gain
.g_state
!= AR5K_RFGAIN_READ_REQUESTED
)
390 /* Read the PAPD (Peak to Average Power Detector)
392 data
= ath5k_hw_reg_read(ah
, AR5K_PHY_PAPD_PROBE
);
394 /* No probe is scheduled, read gain_F measurement */
395 if (!(data
& AR5K_PHY_PAPD_PROBE_TX_NEXT
)) {
396 ah
->ah_gain
.g_current
= data
>> AR5K_PHY_PAPD_PROBE_GAINF_S
;
397 type
= AR5K_REG_MS(data
, AR5K_PHY_PAPD_PROBE_TYPE
);
399 /* If tx packet is CCK correct the gain_F measurement
400 * by cck ofdm gain delta */
401 if (type
== AR5K_PHY_PAPD_PROBE_TYPE_CCK
) {
402 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
)
403 ah
->ah_gain
.g_current
+=
404 ee
->ee_cck_ofdm_gain_delta
;
406 ah
->ah_gain
.g_current
+=
407 AR5K_GAIN_CCK_PROBE_CORR
;
410 /* Further correct gain_F measurement for
412 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
) {
413 ath5k_hw_rf_gainf_corr(ah
);
414 ah
->ah_gain
.g_current
=
415 ah
->ah_gain
.g_current
>= ah
->ah_gain
.g_f_corr
?
416 (ah
->ah_gain
.g_current
-ah
->ah_gain
.g_f_corr
) :
420 /* Check if measurement is ok and if we need
421 * to adjust gain, schedule a gain adjustment,
422 * else switch back to the acive state */
423 if (ath5k_hw_rf_check_gainf_readback(ah
) &&
424 AR5K_GAIN_CHECK_ADJUST(&ah
->ah_gain
) &&
425 ath5k_hw_rf_gainf_adjust(ah
)) {
426 ah
->ah_gain
.g_state
= AR5K_RFGAIN_NEED_CHANGE
;
428 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
433 return ah
->ah_gain
.g_state
;
436 /* Write initial RF gain table to set the RF sensitivity
437 * this one works on all RF chips and has nothing to do
438 * with gain_F calibration */
439 int ath5k_hw_rfgain_init(struct ath5k_hw
*ah
, unsigned int freq
)
441 const struct ath5k_ini_rfgain
*ath5k_rfg
;
442 unsigned int i
, size
;
444 switch (ah
->ah_radio
) {
446 ath5k_rfg
= rfgain_5111
;
447 size
= ARRAY_SIZE(rfgain_5111
);
450 ath5k_rfg
= rfgain_5112
;
451 size
= ARRAY_SIZE(rfgain_5112
);
454 ath5k_rfg
= rfgain_2413
;
455 size
= ARRAY_SIZE(rfgain_2413
);
458 ath5k_rfg
= rfgain_2316
;
459 size
= ARRAY_SIZE(rfgain_2316
);
462 ath5k_rfg
= rfgain_5413
;
463 size
= ARRAY_SIZE(rfgain_5413
);
467 ath5k_rfg
= rfgain_2425
;
468 size
= ARRAY_SIZE(rfgain_2425
);
475 case AR5K_INI_RFGAIN_2GHZ
:
476 case AR5K_INI_RFGAIN_5GHZ
:
482 for (i
= 0; i
< size
; i
++) {
484 ath5k_hw_reg_write(ah
, ath5k_rfg
[i
].rfg_value
[freq
],
485 (u32
)ath5k_rfg
[i
].rfg_register
);
493 /********************\
494 * RF Registers setup *
495 \********************/
499 * Setup RF registers by writing RF buffer on hw
501 int ath5k_hw_rfregs_init(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
,
504 const struct ath5k_rf_reg
*rf_regs
;
505 const struct ath5k_ini_rfbuffer
*ini_rfb
;
506 const struct ath5k_gain_opt
*go
= NULL
;
507 const struct ath5k_gain_opt_step
*g_step
;
508 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
511 int i
, obdb
= -1, bank
= -1;
513 switch (ah
->ah_radio
) {
515 rf_regs
= rf_regs_5111
;
516 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5111
);
518 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5111
);
519 go
= &rfgain_opt_5111
;
522 if (ah
->ah_radio_5ghz_revision
>= AR5K_SREV_RAD_5112A
) {
523 rf_regs
= rf_regs_5112a
;
524 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112a
);
526 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5112a
);
528 rf_regs
= rf_regs_5112
;
529 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5112
);
531 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5112
);
533 go
= &rfgain_opt_5112
;
536 rf_regs
= rf_regs_2413
;
537 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2413
);
539 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2413
);
542 rf_regs
= rf_regs_2316
;
543 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2316
);
545 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2316
);
548 rf_regs
= rf_regs_5413
;
549 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_5413
);
551 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_5413
);
554 rf_regs
= rf_regs_2425
;
555 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2425
);
557 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2317
);
560 rf_regs
= rf_regs_2425
;
561 ah
->ah_rf_regs_count
= ARRAY_SIZE(rf_regs_2425
);
562 if (ah
->ah_mac_srev
< AR5K_SREV_AR2417
) {
564 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2425
);
567 ah
->ah_rf_banks_size
= ARRAY_SIZE(rfb_2417
);
574 /* If it's the first time we set RF buffer, allocate
575 * ah->ah_rf_banks based on ah->ah_rf_banks_size
577 if (ah
->ah_rf_banks
== NULL
) {
578 ah
->ah_rf_banks
= kmalloc(sizeof(u32
) * ah
->ah_rf_banks_size
,
580 if (ah
->ah_rf_banks
== NULL
) {
581 ATH5K_ERR(ah
->ah_sc
, "out of memory\n");
586 /* Copy values to modify them */
587 rfb
= ah
->ah_rf_banks
;
589 for (i
= 0; i
< ah
->ah_rf_banks_size
; i
++) {
590 if (ini_rfb
[i
].rfb_bank
>= AR5K_MAX_RF_BANKS
) {
591 ATH5K_ERR(ah
->ah_sc
, "invalid bank\n");
595 /* Bank changed, write down the offset */
596 if (bank
!= ini_rfb
[i
].rfb_bank
) {
597 bank
= ini_rfb
[i
].rfb_bank
;
598 ah
->ah_offset
[bank
] = i
;
601 rfb
[i
] = ini_rfb
[i
].rfb_mode_data
[mode
];
604 /* Set Output and Driver bias current (OB/DB) */
605 if (channel
->hw_value
& CHANNEL_2GHZ
) {
607 if (channel
->hw_value
& CHANNEL_CCK
)
608 ee_mode
= AR5K_EEPROM_MODE_11B
;
610 ee_mode
= AR5K_EEPROM_MODE_11G
;
612 /* For RF511X/RF211X combination we
613 * use b_OB and b_DB parameters stored
614 * in eeprom on ee->ee_ob[ee_mode][0]
616 * For all other chips we use OB/DB for 2Ghz
617 * stored in the b/g modal section just like
618 * 802.11a on ee->ee_ob[ee_mode][1] */
619 if ((ah
->ah_radio
== AR5K_RF5111
) ||
620 (ah
->ah_radio
== AR5K_RF5112
))
625 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_ob
[ee_mode
][obdb
],
626 AR5K_RF_OB_2GHZ
, true);
628 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_db
[ee_mode
][obdb
],
629 AR5K_RF_DB_2GHZ
, true);
631 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
632 } else if ((channel
->hw_value
& CHANNEL_5GHZ
) ||
633 (ah
->ah_radio
== AR5K_RF5111
)) {
635 /* For 11a, Turbo and XR we need to choose
636 * OB/DB based on frequency range */
637 ee_mode
= AR5K_EEPROM_MODE_11A
;
638 obdb
= channel
->center_freq
>= 5725 ? 3 :
639 (channel
->center_freq
>= 5500 ? 2 :
640 (channel
->center_freq
>= 5260 ? 1 :
641 (channel
->center_freq
> 4000 ? 0 : -1)));
646 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_ob
[ee_mode
][obdb
],
647 AR5K_RF_OB_5GHZ
, true);
649 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_db
[ee_mode
][obdb
],
650 AR5K_RF_DB_5GHZ
, true);
653 g_step
= &go
->go_step
[ah
->ah_gain
.g_step_idx
];
655 /* Bank Modifications (chip-specific) */
656 if (ah
->ah_radio
== AR5K_RF5111
) {
658 /* Set gain_F settings according to current step */
659 if (channel
->hw_value
& CHANNEL_OFDM
) {
661 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_FRAME_CTL
,
662 AR5K_PHY_FRAME_CTL_TX_CLIP
,
663 g_step
->gos_param
[0]);
665 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[1],
666 AR5K_RF_PWD_90
, true);
668 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[2],
669 AR5K_RF_PWD_84
, true);
671 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[3],
672 AR5K_RF_RFGAIN_SEL
, true);
674 /* We programmed gain_F parameters, switch back
676 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
682 ath5k_hw_rfb_op(ah
, rf_regs
, !ee
->ee_xpd
[ee_mode
],
683 AR5K_RF_PWD_XPD
, true);
685 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_x_gain
[ee_mode
],
686 AR5K_RF_XPD_GAIN
, true);
688 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_i_gain
[ee_mode
],
689 AR5K_RF_GAIN_I
, true);
691 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_xpd
[ee_mode
],
692 AR5K_RF_PLO_SEL
, true);
694 /* TODO: Half/quarter channel support */
697 if (ah
->ah_radio
== AR5K_RF5112
) {
699 /* Set gain_F settings according to current step */
700 if (channel
->hw_value
& CHANNEL_OFDM
) {
702 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[0],
703 AR5K_RF_MIXGAIN_OVR
, true);
705 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[1],
706 AR5K_RF_PWD_138
, true);
708 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[2],
709 AR5K_RF_PWD_137
, true);
711 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[3],
712 AR5K_RF_PWD_136
, true);
714 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[4],
715 AR5K_RF_PWD_132
, true);
717 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[5],
718 AR5K_RF_PWD_131
, true);
720 ath5k_hw_rfb_op(ah
, rf_regs
, g_step
->gos_param
[6],
721 AR5K_RF_PWD_130
, true);
723 /* We programmed gain_F parameters, switch back
725 ah
->ah_gain
.g_state
= AR5K_RFGAIN_ACTIVE
;
730 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_xpd
[ee_mode
],
731 AR5K_RF_XPD_SEL
, true);
733 if (ah
->ah_radio_5ghz_revision
< AR5K_SREV_RAD_5112A
) {
734 /* Rev. 1 supports only one xpd */
735 ath5k_hw_rfb_op(ah
, rf_regs
,
736 ee
->ee_x_gain
[ee_mode
],
737 AR5K_RF_XPD_GAIN
, true);
740 u8
*pdg_curve_to_idx
= ee
->ee_pdc_to_idx
[ee_mode
];
741 if (ee
->ee_pd_gains
[ee_mode
] > 1) {
742 ath5k_hw_rfb_op(ah
, rf_regs
,
744 AR5K_RF_PD_GAIN_LO
, true);
745 ath5k_hw_rfb_op(ah
, rf_regs
,
747 AR5K_RF_PD_GAIN_HI
, true);
749 ath5k_hw_rfb_op(ah
, rf_regs
,
751 AR5K_RF_PD_GAIN_LO
, true);
752 ath5k_hw_rfb_op(ah
, rf_regs
,
754 AR5K_RF_PD_GAIN_HI
, true);
757 /* Lower synth voltage on Rev 2 */
758 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
759 AR5K_RF_HIGH_VC_CP
, true);
761 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
762 AR5K_RF_MID_VC_CP
, true);
764 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
765 AR5K_RF_LOW_VC_CP
, true);
767 ath5k_hw_rfb_op(ah
, rf_regs
, 2,
768 AR5K_RF_PUSH_UP
, true);
770 /* Decrease power consumption on 5213+ BaseBand */
771 if (ah
->ah_phy_revision
>= AR5K_SREV_PHY_5212A
) {
772 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
773 AR5K_RF_PAD2GND
, true);
775 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
776 AR5K_RF_XB2_LVL
, true);
778 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
779 AR5K_RF_XB5_LVL
, true);
781 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
782 AR5K_RF_PWD_167
, true);
784 ath5k_hw_rfb_op(ah
, rf_regs
, 1,
785 AR5K_RF_PWD_166
, true);
789 ath5k_hw_rfb_op(ah
, rf_regs
, ee
->ee_i_gain
[ee_mode
],
790 AR5K_RF_GAIN_I
, true);
792 /* TODO: Half/quarter channel support */
796 if (ah
->ah_radio
== AR5K_RF5413
&&
797 channel
->hw_value
& CHANNEL_2GHZ
) {
799 ath5k_hw_rfb_op(ah
, rf_regs
, 1, AR5K_RF_DERBY_CHAN_SEL_MODE
,
802 /* Set optimum value for early revisions (on pci-e chips) */
803 if (ah
->ah_mac_srev
>= AR5K_SREV_AR5424
&&
804 ah
->ah_mac_srev
< AR5K_SREV_AR5413
)
805 ath5k_hw_rfb_op(ah
, rf_regs
, ath5k_hw_bitswap(6, 3),
806 AR5K_RF_PWD_ICLOBUF_2G
, true);
810 /* Write RF banks on hw */
811 for (i
= 0; i
< ah
->ah_rf_banks_size
; i
++) {
813 ath5k_hw_reg_write(ah
, rfb
[i
], ini_rfb
[i
].rfb_ctrl_register
);
820 /**************************\
821 PHY/RF channel functions
822 \**************************/
825 * Check if a channel is supported
827 bool ath5k_channel_ok(struct ath5k_hw
*ah
, u16 freq
, unsigned int flags
)
829 /* Check if the channel is in our supported range */
830 if (flags
& CHANNEL_2GHZ
) {
831 if ((freq
>= ah
->ah_capabilities
.cap_range
.range_2ghz_min
) &&
832 (freq
<= ah
->ah_capabilities
.cap_range
.range_2ghz_max
))
834 } else if (flags
& CHANNEL_5GHZ
)
835 if ((freq
>= ah
->ah_capabilities
.cap_range
.range_5ghz_min
) &&
836 (freq
<= ah
->ah_capabilities
.cap_range
.range_5ghz_max
))
843 * Convertion needed for RF5110
845 static u32
ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel
*channel
)
850 * Convert IEEE channel/MHz to an internal channel value used
851 * by the AR5210 chipset. This has not been verified with
852 * newer chipsets like the AR5212A who have a completely
853 * different RF/PHY part.
855 athchan
= (ath5k_hw_bitswap(
856 (ieee80211_frequency_to_channel(
857 channel
->center_freq
) - 24) / 2, 5)
858 << 1) | (1 << 6) | 0x1;
863 * Set channel on RF5110
865 static int ath5k_hw_rf5110_channel(struct ath5k_hw
*ah
,
866 struct ieee80211_channel
*channel
)
871 * Set the channel and wait
873 data
= ath5k_hw_rf5110_chan2athchan(channel
);
874 ath5k_hw_reg_write(ah
, data
, AR5K_RF_BUFFER
);
875 ath5k_hw_reg_write(ah
, 0, AR5K_RF_BUFFER_CONTROL_0
);
882 * Convertion needed for 5111
884 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee
,
885 struct ath5k_athchan_2ghz
*athchan
)
889 /* Cast this value to catch negative channel numbers (>= -19) */
893 * Map 2GHz IEEE channel to 5GHz Atheros channel
896 athchan
->a2_athchan
= 115 + channel
;
897 athchan
->a2_flags
= 0x46;
898 } else if (channel
== 14) {
899 athchan
->a2_athchan
= 124;
900 athchan
->a2_flags
= 0x44;
901 } else if (channel
>= 15 && channel
<= 26) {
902 athchan
->a2_athchan
= ((channel
- 14) * 4) + 132;
903 athchan
->a2_flags
= 0x46;
911 * Set channel on 5111
913 static int ath5k_hw_rf5111_channel(struct ath5k_hw
*ah
,
914 struct ieee80211_channel
*channel
)
916 struct ath5k_athchan_2ghz ath5k_channel_2ghz
;
917 unsigned int ath5k_channel
=
918 ieee80211_frequency_to_channel(channel
->center_freq
);
919 u32 data0
, data1
, clock
;
923 * Set the channel on the RF5111 radio
927 if (channel
->hw_value
& CHANNEL_2GHZ
) {
928 /* Map 2GHz channel to 5GHz Atheros channel ID */
929 ret
= ath5k_hw_rf5111_chan2athchan(
930 ieee80211_frequency_to_channel(channel
->center_freq
),
931 &ath5k_channel_2ghz
);
935 ath5k_channel
= ath5k_channel_2ghz
.a2_athchan
;
936 data0
= ((ath5k_hw_bitswap(ath5k_channel_2ghz
.a2_flags
, 8) & 0xff)
940 if (ath5k_channel
< 145 || !(ath5k_channel
& 1)) {
942 data1
= ((ath5k_hw_bitswap(ath5k_channel
- 24, 8) & 0xff) << 2) |
943 (clock
<< 1) | (1 << 10) | 1;
946 data1
= ((ath5k_hw_bitswap((ath5k_channel
- 24) / 2, 8) & 0xff)
947 << 2) | (clock
<< 1) | (1 << 10) | 1;
950 ath5k_hw_reg_write(ah
, (data1
& 0xff) | ((data0
& 0xff) << 8),
952 ath5k_hw_reg_write(ah
, ((data1
>> 8) & 0xff) | (data0
& 0xff00),
953 AR5K_RF_BUFFER_CONTROL_3
);
959 * Set channel on 5112 and newer
961 static int ath5k_hw_rf5112_channel(struct ath5k_hw
*ah
,
962 struct ieee80211_channel
*channel
)
964 u32 data
, data0
, data1
, data2
;
967 data
= data0
= data1
= data2
= 0;
968 c
= channel
->center_freq
;
971 if (!((c
- 2224) % 5)) {
972 data0
= ((2 * (c
- 704)) - 3040) / 10;
974 } else if (!((c
- 2192) % 5)) {
975 data0
= ((2 * (c
- 672)) - 3040) / 10;
980 data0
= ath5k_hw_bitswap((data0
<< 2) & 0xff, 8);
981 } else if ((c
% 5) != 2 || c
> 5435) {
982 if (!(c
% 20) && c
>= 5120) {
983 data0
= ath5k_hw_bitswap(((c
- 4800) / 20 << 2), 8);
984 data2
= ath5k_hw_bitswap(3, 2);
985 } else if (!(c
% 10)) {
986 data0
= ath5k_hw_bitswap(((c
- 4800) / 10 << 1), 8);
987 data2
= ath5k_hw_bitswap(2, 2);
988 } else if (!(c
% 5)) {
989 data0
= ath5k_hw_bitswap((c
- 4800) / 5, 8);
990 data2
= ath5k_hw_bitswap(1, 2);
994 data0
= ath5k_hw_bitswap((10 * (c
- 2 - 4800)) / 25 + 1, 8);
995 data2
= ath5k_hw_bitswap(0, 2);
998 data
= (data0
<< 4) | (data1
<< 1) | (data2
<< 2) | 0x1001;
1000 ath5k_hw_reg_write(ah
, data
& 0xff, AR5K_RF_BUFFER
);
1001 ath5k_hw_reg_write(ah
, (data
>> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5
);
1007 * Set the channel on the RF2425
1009 static int ath5k_hw_rf2425_channel(struct ath5k_hw
*ah
,
1010 struct ieee80211_channel
*channel
)
1012 u32 data
, data0
, data2
;
1015 data
= data0
= data2
= 0;
1016 c
= channel
->center_freq
;
1019 data0
= ath5k_hw_bitswap((c
- 2272), 8);
1022 } else if ((c
% 5) != 2 || c
> 5435) {
1023 if (!(c
% 20) && c
< 5120)
1024 data0
= ath5k_hw_bitswap(((c
- 4800) / 20 << 2), 8);
1026 data0
= ath5k_hw_bitswap(((c
- 4800) / 10 << 1), 8);
1028 data0
= ath5k_hw_bitswap((c
- 4800) / 5, 8);
1031 data2
= ath5k_hw_bitswap(1, 2);
1033 data0
= ath5k_hw_bitswap((10 * (c
- 2 - 4800)) / 25 + 1, 8);
1034 data2
= ath5k_hw_bitswap(0, 2);
1037 data
= (data0
<< 4) | data2
<< 2 | 0x1001;
1039 ath5k_hw_reg_write(ah
, data
& 0xff, AR5K_RF_BUFFER
);
1040 ath5k_hw_reg_write(ah
, (data
>> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5
);
1046 * Set a channel on the radio chip
1048 int ath5k_hw_channel(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
)
1052 * Check bounds supported by the PHY (we don't care about regultory
1053 * restrictions at this point). Note: hw_value already has the band
1054 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1055 * of the band by that */
1056 if (!ath5k_channel_ok(ah
, channel
->center_freq
, channel
->hw_value
)) {
1057 ATH5K_ERR(ah
->ah_sc
,
1058 "channel frequency (%u MHz) out of supported "
1060 channel
->center_freq
);
1065 * Set the channel and wait
1067 switch (ah
->ah_radio
) {
1069 ret
= ath5k_hw_rf5110_channel(ah
, channel
);
1072 ret
= ath5k_hw_rf5111_channel(ah
, channel
);
1075 ret
= ath5k_hw_rf2425_channel(ah
, channel
);
1078 ret
= ath5k_hw_rf5112_channel(ah
, channel
);
1085 /* Set JAPAN setting for channel 14 */
1086 if (channel
->center_freq
== 2484) {
1087 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_CCKTXCTL
,
1088 AR5K_PHY_CCKTXCTL_JAPAN
);
1090 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_CCKTXCTL
,
1091 AR5K_PHY_CCKTXCTL_WORLD
);
1094 ah
->ah_current_channel
= channel
;
1095 ah
->ah_turbo
= channel
->hw_value
== CHANNEL_T
? true : false;
1104 static int sign_extend(int val
, const int nbits
)
1106 int order
= BIT(nbits
-1);
1107 return (val
^ order
) - order
;
1110 static s32
ath5k_hw_read_measured_noise_floor(struct ath5k_hw
*ah
)
1114 val
= ath5k_hw_reg_read(ah
, AR5K_PHY_NF
);
1115 return sign_extend(AR5K_REG_MS(val
, AR5K_PHY_NF_MINCCA_PWR
), 9);
1118 void ath5k_hw_init_nfcal_hist(struct ath5k_hw
*ah
)
1122 ah
->ah_nfcal_hist
.index
= 0;
1123 for (i
= 0; i
< ATH5K_NF_CAL_HIST_MAX
; i
++)
1124 ah
->ah_nfcal_hist
.nfval
[i
] = AR5K_TUNE_CCA_MAX_GOOD_VALUE
;
1127 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw
*ah
, s16 noise_floor
)
1129 struct ath5k_nfcal_hist
*hist
= &ah
->ah_nfcal_hist
;
1130 hist
->index
= (hist
->index
+ 1) & (ATH5K_NF_CAL_HIST_MAX
-1);
1131 hist
->nfval
[hist
->index
] = noise_floor
;
1134 static s16
ath5k_hw_get_median_noise_floor(struct ath5k_hw
*ah
)
1136 s16 sort
[ATH5K_NF_CAL_HIST_MAX
];
1140 memcpy(sort
, ah
->ah_nfcal_hist
.nfval
, sizeof(sort
));
1141 for (i
= 0; i
< ATH5K_NF_CAL_HIST_MAX
- 1; i
++) {
1142 for (j
= 1; j
< ATH5K_NF_CAL_HIST_MAX
- i
; j
++) {
1143 if (sort
[j
] > sort
[j
-1]) {
1145 sort
[j
] = sort
[j
-1];
1150 for (i
= 0; i
< ATH5K_NF_CAL_HIST_MAX
; i
++) {
1151 ATH5K_DBG(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
1152 "cal %d:%d\n", i
, sort
[i
]);
1154 return sort
[(ATH5K_NF_CAL_HIST_MAX
-1) / 2];
1158 * When we tell the hardware to perform a noise floor calibration
1159 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1160 * sample-and-hold the minimum noise level seen at the antennas.
1161 * This value is then stored in a ring buffer of recently measured
1162 * noise floor values so we have a moving window of the last few
1165 * The median of the values in the history is then loaded into the
1166 * hardware for its own use for RSSI and CCA measurements.
1168 void ath5k_hw_update_noise_floor(struct ath5k_hw
*ah
)
1170 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
1175 /* keep last value if calibration hasn't completed */
1176 if (ath5k_hw_reg_read(ah
, AR5K_PHY_AGCCTL
) & AR5K_PHY_AGCCTL_NF
) {
1177 ATH5K_DBG(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
1178 "NF did not complete in calibration window\n");
1183 switch (ah
->ah_current_channel
->hw_value
& CHANNEL_MODES
) {
1187 ee_mode
= AR5K_EEPROM_MODE_11A
;
1191 ee_mode
= AR5K_EEPROM_MODE_11G
;
1195 ee_mode
= AR5K_EEPROM_MODE_11B
;
1200 /* completed NF calibration, test threshold */
1201 nf
= ath5k_hw_read_measured_noise_floor(ah
);
1202 threshold
= ee
->ee_noise_floor_thr
[ee_mode
];
1204 if (nf
> threshold
) {
1205 ATH5K_DBG(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
1206 "noise floor failure detected; "
1207 "read %d, threshold %d\n",
1210 nf
= AR5K_TUNE_CCA_MAX_GOOD_VALUE
;
1213 ath5k_hw_update_nfcal_hist(ah
, nf
);
1214 nf
= ath5k_hw_get_median_noise_floor(ah
);
1216 /* load noise floor (in .5 dBm) so the hardware will use it */
1217 val
= ath5k_hw_reg_read(ah
, AR5K_PHY_NF
) & ~AR5K_PHY_NF_M
;
1218 val
|= (nf
* 2) & AR5K_PHY_NF_M
;
1219 ath5k_hw_reg_write(ah
, val
, AR5K_PHY_NF
);
1221 AR5K_REG_MASKED_BITS(ah
, AR5K_PHY_AGCCTL
, AR5K_PHY_AGCCTL_NF
,
1222 ~(AR5K_PHY_AGCCTL_NF_EN
| AR5K_PHY_AGCCTL_NF_NOUPDATE
));
1224 ath5k_hw_register_timeout(ah
, AR5K_PHY_AGCCTL
, AR5K_PHY_AGCCTL_NF
,
1228 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1229 * so that we're not capped by the median we just loaded.
1230 * This will be used as the initial value for the next noise
1231 * floor calibration.
1233 val
= (val
& ~AR5K_PHY_NF_M
) | ((-50 * 2) & AR5K_PHY_NF_M
);
1234 ath5k_hw_reg_write(ah
, val
, AR5K_PHY_NF
);
1235 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
1236 AR5K_PHY_AGCCTL_NF_EN
|
1237 AR5K_PHY_AGCCTL_NF_NOUPDATE
|
1238 AR5K_PHY_AGCCTL_NF
);
1240 ah
->ah_noise_floor
= nf
;
1242 ATH5K_DBG(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
1243 "noise floor calibrated: %d\n", nf
);
1247 * Perform a PHY calibration on RF5110
1248 * -Fix BPSK/QAM Constellation (I/Q correction)
1250 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw
*ah
,
1251 struct ieee80211_channel
*channel
)
1253 u32 phy_sig
, phy_agc
, phy_sat
, beacon
;
1257 * Disable beacons and RX/TX queues, wait
1259 AR5K_REG_ENABLE_BITS(ah
, AR5K_DIAG_SW_5210
,
1260 AR5K_DIAG_SW_DIS_TX
| AR5K_DIAG_SW_DIS_RX_5210
);
1261 beacon
= ath5k_hw_reg_read(ah
, AR5K_BEACON_5210
);
1262 ath5k_hw_reg_write(ah
, beacon
& ~AR5K_BEACON_ENABLE
, AR5K_BEACON_5210
);
1267 * Set the channel (with AGC turned off)
1269 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1271 ret
= ath5k_hw_channel(ah
, channel
);
1274 * Activate PHY and wait
1276 ath5k_hw_reg_write(ah
, AR5K_PHY_ACT_ENABLE
, AR5K_PHY_ACT
);
1279 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1285 * Calibrate the radio chip
1288 /* Remember normal state */
1289 phy_sig
= ath5k_hw_reg_read(ah
, AR5K_PHY_SIG
);
1290 phy_agc
= ath5k_hw_reg_read(ah
, AR5K_PHY_AGCCOARSE
);
1291 phy_sat
= ath5k_hw_reg_read(ah
, AR5K_PHY_ADCSAT
);
1293 /* Update radio registers */
1294 ath5k_hw_reg_write(ah
, (phy_sig
& ~(AR5K_PHY_SIG_FIRPWR
)) |
1295 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR
), AR5K_PHY_SIG
);
1297 ath5k_hw_reg_write(ah
, (phy_agc
& ~(AR5K_PHY_AGCCOARSE_HI
|
1298 AR5K_PHY_AGCCOARSE_LO
)) |
1299 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI
) |
1300 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO
), AR5K_PHY_AGCCOARSE
);
1302 ath5k_hw_reg_write(ah
, (phy_sat
& ~(AR5K_PHY_ADCSAT_ICNT
|
1303 AR5K_PHY_ADCSAT_THR
)) |
1304 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT
) |
1305 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR
), AR5K_PHY_ADCSAT
);
1309 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1311 ath5k_hw_reg_write(ah
, AR5K_PHY_RFSTG_DISABLE
, AR5K_PHY_RFSTG
);
1312 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_AGC
, AR5K_PHY_AGC_DISABLE
);
1317 * Enable calibration and wait until completion
1319 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
, AR5K_PHY_AGCCTL_CAL
);
1321 ret
= ath5k_hw_register_timeout(ah
, AR5K_PHY_AGCCTL
,
1322 AR5K_PHY_AGCCTL_CAL
, 0, false);
1324 /* Reset to normal state */
1325 ath5k_hw_reg_write(ah
, phy_sig
, AR5K_PHY_SIG
);
1326 ath5k_hw_reg_write(ah
, phy_agc
, AR5K_PHY_AGCCOARSE
);
1327 ath5k_hw_reg_write(ah
, phy_sat
, AR5K_PHY_ADCSAT
);
1330 ATH5K_ERR(ah
->ah_sc
, "calibration timeout (%uMHz)\n",
1331 channel
->center_freq
);
1336 * Re-enable RX/TX and beacons
1338 AR5K_REG_DISABLE_BITS(ah
, AR5K_DIAG_SW_5210
,
1339 AR5K_DIAG_SW_DIS_TX
| AR5K_DIAG_SW_DIS_RX_5210
);
1340 ath5k_hw_reg_write(ah
, beacon
, AR5K_BEACON_5210
);
1346 * Perform I/Q calibration on RF5111/5112 and newer chips
1349 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw
*ah
)
1352 s32 iq_corr
, i_coff
, i_coffd
, q_coff
, q_coffd
;
1355 if (!ah
->ah_calibration
||
1356 ath5k_hw_reg_read(ah
, AR5K_PHY_IQ
) & AR5K_PHY_IQ_RUN
)
1359 /* Calibration has finished, get the results and re-run */
1360 /* work around empty results which can apparently happen on 5212 */
1361 for (i
= 0; i
<= 10; i
++) {
1362 iq_corr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_CORR
);
1363 i_pwr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_PWR_I
);
1364 q_pwr
= ath5k_hw_reg_read(ah
, AR5K_PHY_IQRES_CAL_PWR_Q
);
1365 ATH5K_DBG_UNLIMIT(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
1366 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr
, i_pwr
, q_pwr
);
1371 i_coffd
= ((i_pwr
>> 1) + (q_pwr
>> 1)) >> 7;
1373 if (ah
->ah_version
== AR5K_AR5211
)
1374 q_coffd
= q_pwr
>> 6;
1376 q_coffd
= q_pwr
>> 7;
1378 /* protect against divide by 0 and loss of sign bits */
1379 if (i_coffd
== 0 || q_coffd
< 2)
1382 i_coff
= (-iq_corr
) / i_coffd
;
1383 i_coff
= clamp(i_coff
, -32, 31); /* signed 6 bit */
1385 if (ah
->ah_version
== AR5K_AR5211
)
1386 q_coff
= (i_pwr
/ q_coffd
) - 64;
1388 q_coff
= (i_pwr
/ q_coffd
) - 128;
1389 q_coff
= clamp(q_coff
, -16, 15); /* signed 5 bit */
1391 ATH5K_DBG_UNLIMIT(ah
->ah_sc
, ATH5K_DEBUG_CALIBRATE
,
1392 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1393 i_coff
, q_coff
, i_coffd
, q_coffd
);
1395 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1396 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_Q_I_COFF
, i_coff
);
1397 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_Q_Q_COFF
, q_coff
);
1398 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_ENABLE
);
1400 /* Re-enable calibration -if we don't we'll commit
1401 * the same values again and again */
1402 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
,
1403 AR5K_PHY_IQ_CAL_NUM_LOG_MAX
, 15);
1404 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_RUN
);
1410 * Perform a PHY calibration
1412 int ath5k_hw_phy_calibrate(struct ath5k_hw
*ah
,
1413 struct ieee80211_channel
*channel
)
1417 if (ah
->ah_radio
== AR5K_RF5110
)
1418 ret
= ath5k_hw_rf5110_calibrate(ah
, channel
);
1420 ret
= ath5k_hw_rf511x_iq_calibrate(ah
);
1421 ath5k_hw_request_rfgain_probe(ah
);
1427 /***************************\
1428 * Spur mitigation functions *
1429 \***************************/
1431 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw
*ah
,
1432 struct ieee80211_channel
*channel
)
1436 if ((ah
->ah_radio
== AR5K_RF5112
) ||
1437 (ah
->ah_radio
== AR5K_RF5413
) ||
1438 (ah
->ah_mac_version
== (AR5K_SREV_AR2417
>> 4)))
1443 if ((channel
->center_freq
% refclk_freq
!= 0) &&
1444 ((channel
->center_freq
% refclk_freq
< 10) ||
1445 (channel
->center_freq
% refclk_freq
> 22)))
1452 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw
*ah
,
1453 struct ieee80211_channel
*channel
)
1455 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
1456 u32 mag_mask
[4] = {0, 0, 0, 0};
1457 u32 pilot_mask
[2] = {0, 0};
1458 /* Note: fbin values are scaled up by 2 */
1459 u16 spur_chan_fbin
, chan_fbin
, symbol_width
, spur_detection_window
;
1460 s32 spur_delta_phase
, spur_freq_sigma_delta
;
1461 s32 spur_offset
, num_symbols_x16
;
1462 u8 num_symbol_offsets
, i
, freq_band
;
1464 /* Convert current frequency to fbin value (the same way channels
1465 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1466 * up by 2 so we can compare it later */
1467 if (channel
->hw_value
& CHANNEL_2GHZ
) {
1468 chan_fbin
= (channel
->center_freq
- 2300) * 10;
1469 freq_band
= AR5K_EEPROM_BAND_2GHZ
;
1471 chan_fbin
= (channel
->center_freq
- 4900) * 10;
1472 freq_band
= AR5K_EEPROM_BAND_5GHZ
;
1475 /* Check if any spur_chan_fbin from EEPROM is
1476 * within our current channel's spur detection range */
1477 spur_chan_fbin
= AR5K_EEPROM_NO_SPUR
;
1478 spur_detection_window
= AR5K_SPUR_CHAN_WIDTH
;
1479 /* XXX: Half/Quarter channels ?*/
1480 if (channel
->hw_value
& CHANNEL_TURBO
)
1481 spur_detection_window
*= 2;
1483 for (i
= 0; i
< AR5K_EEPROM_N_SPUR_CHANS
; i
++) {
1484 spur_chan_fbin
= ee
->ee_spur_chans
[i
][freq_band
];
1486 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1487 * so it's zero if we got nothing from EEPROM */
1488 if (spur_chan_fbin
== AR5K_EEPROM_NO_SPUR
) {
1489 spur_chan_fbin
&= AR5K_EEPROM_SPUR_CHAN_MASK
;
1493 if ((chan_fbin
- spur_detection_window
<=
1494 (spur_chan_fbin
& AR5K_EEPROM_SPUR_CHAN_MASK
)) &&
1495 (chan_fbin
+ spur_detection_window
>=
1496 (spur_chan_fbin
& AR5K_EEPROM_SPUR_CHAN_MASK
))) {
1497 spur_chan_fbin
&= AR5K_EEPROM_SPUR_CHAN_MASK
;
1502 /* We need to enable spur filter for this channel */
1503 if (spur_chan_fbin
) {
1504 spur_offset
= spur_chan_fbin
- chan_fbin
;
1507 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1508 * spur_delta_phase -> spur_offset / chip_freq << 11
1509 * Note: Both values have 100KHz resolution
1511 /* XXX: Half/Quarter rate channels ? */
1512 switch (channel
->hw_value
) {
1514 /* Both sample_freq and chip_freq are 40MHz */
1515 spur_delta_phase
= (spur_offset
<< 17) / 25;
1516 spur_freq_sigma_delta
= (spur_delta_phase
>> 10);
1517 symbol_width
= AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz
;
1520 /* sample_freq -> 40MHz chip_freq -> 44MHz
1521 * (for b compatibility) */
1522 spur_freq_sigma_delta
= (spur_offset
<< 8) / 55;
1523 spur_delta_phase
= (spur_offset
<< 17) / 25;
1524 symbol_width
= AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz
;
1528 /* Both sample_freq and chip_freq are 80MHz */
1529 spur_delta_phase
= (spur_offset
<< 16) / 25;
1530 spur_freq_sigma_delta
= (spur_delta_phase
>> 10);
1531 symbol_width
= AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz
;
1537 /* Calculate pilot and magnitude masks */
1539 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1540 * and divide by symbol_width to find how many symbols we have
1541 * Note: number of symbols is scaled up by 16 */
1542 num_symbols_x16
= ((spur_offset
* 1000) << 4) / symbol_width
;
1544 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1545 if (!(num_symbols_x16
& 0xF))
1547 num_symbol_offsets
= 3;
1550 num_symbol_offsets
= 4;
1552 for (i
= 0; i
< num_symbol_offsets
; i
++) {
1554 /* Calculate pilot mask */
1556 (num_symbols_x16
/ 16) + i
+ 25;
1558 /* Pilot magnitude mask seems to be a way to
1559 * declare the boundaries for our detection
1560 * window or something, it's 2 for the middle
1561 * value(s) where the symbol is expected to be
1562 * and 1 on the boundary values */
1564 (i
== 0 || i
== (num_symbol_offsets
- 1))
1567 if (curr_sym_off
>= 0 && curr_sym_off
<= 32) {
1568 if (curr_sym_off
<= 25)
1569 pilot_mask
[0] |= 1 << curr_sym_off
;
1570 else if (curr_sym_off
>= 27)
1571 pilot_mask
[0] |= 1 << (curr_sym_off
- 1);
1572 } else if (curr_sym_off
>= 33 && curr_sym_off
<= 52)
1573 pilot_mask
[1] |= 1 << (curr_sym_off
- 33);
1575 /* Calculate magnitude mask (for viterbi decoder) */
1576 if (curr_sym_off
>= -1 && curr_sym_off
<= 14)
1578 plt_mag_map
<< (curr_sym_off
+ 1) * 2;
1579 else if (curr_sym_off
>= 15 && curr_sym_off
<= 30)
1581 plt_mag_map
<< (curr_sym_off
- 15) * 2;
1582 else if (curr_sym_off
>= 31 && curr_sym_off
<= 46)
1584 plt_mag_map
<< (curr_sym_off
- 31) * 2;
1585 else if (curr_sym_off
>= 47 && curr_sym_off
<= 53)
1587 plt_mag_map
<< (curr_sym_off
- 47) * 2;
1591 /* Write settings on hw to enable spur filter */
1592 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK_CTL
,
1593 AR5K_PHY_BIN_MASK_CTL_RATE
, 0xff);
1594 /* XXX: Self correlator also ? */
1595 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
,
1596 AR5K_PHY_IQ_PILOT_MASK_EN
|
1597 AR5K_PHY_IQ_CHAN_MASK_EN
|
1598 AR5K_PHY_IQ_SPUR_FILT_EN
);
1600 /* Set delta phase and freq sigma delta */
1601 ath5k_hw_reg_write(ah
,
1602 AR5K_REG_SM(spur_delta_phase
,
1603 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE
) |
1604 AR5K_REG_SM(spur_freq_sigma_delta
,
1605 AR5K_PHY_TIMING_11_SPUR_FREQ_SD
) |
1606 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC
,
1607 AR5K_PHY_TIMING_11
);
1609 /* Write pilot masks */
1610 ath5k_hw_reg_write(ah
, pilot_mask
[0], AR5K_PHY_TIMING_7
);
1611 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_8
,
1612 AR5K_PHY_TIMING_8_PILOT_MASK_2
,
1615 ath5k_hw_reg_write(ah
, pilot_mask
[0], AR5K_PHY_TIMING_9
);
1616 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_10
,
1617 AR5K_PHY_TIMING_10_PILOT_MASK_2
,
1620 /* Write magnitude masks */
1621 ath5k_hw_reg_write(ah
, mag_mask
[0], AR5K_PHY_BIN_MASK_1
);
1622 ath5k_hw_reg_write(ah
, mag_mask
[1], AR5K_PHY_BIN_MASK_2
);
1623 ath5k_hw_reg_write(ah
, mag_mask
[2], AR5K_PHY_BIN_MASK_3
);
1624 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK_CTL
,
1625 AR5K_PHY_BIN_MASK_CTL_MASK_4
,
1628 ath5k_hw_reg_write(ah
, mag_mask
[0], AR5K_PHY_BIN_MASK2_1
);
1629 ath5k_hw_reg_write(ah
, mag_mask
[1], AR5K_PHY_BIN_MASK2_2
);
1630 ath5k_hw_reg_write(ah
, mag_mask
[2], AR5K_PHY_BIN_MASK2_3
);
1631 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK2_4
,
1632 AR5K_PHY_BIN_MASK2_4_MASK_4
,
1635 } else if (ath5k_hw_reg_read(ah
, AR5K_PHY_IQ
) &
1636 AR5K_PHY_IQ_SPUR_FILT_EN
) {
1637 /* Clean up spur mitigation settings and disable fliter */
1638 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK_CTL
,
1639 AR5K_PHY_BIN_MASK_CTL_RATE
, 0);
1640 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_IQ
,
1641 AR5K_PHY_IQ_PILOT_MASK_EN
|
1642 AR5K_PHY_IQ_CHAN_MASK_EN
|
1643 AR5K_PHY_IQ_SPUR_FILT_EN
);
1644 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_TIMING_11
);
1646 /* Clear pilot masks */
1647 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_TIMING_7
);
1648 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_8
,
1649 AR5K_PHY_TIMING_8_PILOT_MASK_2
,
1652 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_TIMING_9
);
1653 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_TIMING_10
,
1654 AR5K_PHY_TIMING_10_PILOT_MASK_2
,
1657 /* Clear magnitude masks */
1658 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK_1
);
1659 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK_2
);
1660 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK_3
);
1661 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK_CTL
,
1662 AR5K_PHY_BIN_MASK_CTL_MASK_4
,
1665 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK2_1
);
1666 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK2_2
);
1667 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BIN_MASK2_3
);
1668 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_BIN_MASK2_4
,
1669 AR5K_PHY_BIN_MASK2_4_MASK_4
,
1674 /********************\
1676 \********************/
1678 int ath5k_hw_phy_disable(struct ath5k_hw
*ah
)
1681 ath5k_hw_reg_write(ah
, AR5K_PHY_ACT_DISABLE
, AR5K_PHY_ACT
);
1687 * Get the PHY Chip revision
1689 u16
ath5k_hw_radio_revision(struct ath5k_hw
*ah
, unsigned int chan
)
1696 * Set the radio chip access register
1700 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_2GHZ
, AR5K_PHY(0));
1703 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_5GHZ
, AR5K_PHY(0));
1711 /* ...wait until PHY is ready and read the selected radio revision */
1712 ath5k_hw_reg_write(ah
, 0x00001c16, AR5K_PHY(0x34));
1714 for (i
= 0; i
< 8; i
++)
1715 ath5k_hw_reg_write(ah
, 0x00010000, AR5K_PHY(0x20));
1717 if (ah
->ah_version
== AR5K_AR5210
) {
1718 srev
= ath5k_hw_reg_read(ah
, AR5K_PHY(256) >> 28) & 0xf;
1719 ret
= (u16
)ath5k_hw_bitswap(srev
, 4) + 1;
1721 srev
= (ath5k_hw_reg_read(ah
, AR5K_PHY(0x100)) >> 24) & 0xff;
1722 ret
= (u16
)ath5k_hw_bitswap(((srev
& 0xf0) >> 4) |
1723 ((srev
& 0x0f) << 4), 8);
1726 /* Reset to the 5GHz mode */
1727 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_5GHZ
, AR5K_PHY(0));
1736 static void /*TODO:Boundary check*/
1737 ath5k_hw_set_def_antenna(struct ath5k_hw
*ah
, u8 ant
)
1739 if (ah
->ah_version
!= AR5K_AR5210
)
1740 ath5k_hw_reg_write(ah
, ant
& 0x7, AR5K_DEFAULT_ANTENNA
);
1744 * Enable/disable fast rx antenna diversity
1747 ath5k_hw_set_fast_div(struct ath5k_hw
*ah
, u8 ee_mode
, bool enable
)
1750 case AR5K_EEPROM_MODE_11G
:
1751 /* XXX: This is set to
1752 * disabled on initvals !!! */
1753 case AR5K_EEPROM_MODE_11A
:
1755 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
1756 AR5K_PHY_AGCCTL_OFDM_DIV_DIS
);
1758 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
1759 AR5K_PHY_AGCCTL_OFDM_DIV_DIS
);
1761 case AR5K_EEPROM_MODE_11B
:
1762 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_AGCCTL
,
1763 AR5K_PHY_AGCCTL_OFDM_DIV_DIS
);
1770 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_RESTART
,
1771 AR5K_PHY_RESTART_DIV_GC
, 4);
1773 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_FAST_ANT_DIV
,
1774 AR5K_PHY_FAST_ANT_DIV_EN
);
1776 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_RESTART
,
1777 AR5K_PHY_RESTART_DIV_GC
, 0);
1779 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_FAST_ANT_DIV
,
1780 AR5K_PHY_FAST_ANT_DIV_EN
);
1785 ath5k_hw_set_antenna_switch(struct ath5k_hw
*ah
, u8 ee_mode
)
1790 * In case a fixed antenna was set as default
1791 * use the same switch table twice.
1793 if (ah
->ah_ant_mode
== AR5K_ANTMODE_FIXED_A
)
1794 ant0
= ant1
= AR5K_ANT_SWTABLE_A
;
1795 else if (ah
->ah_ant_mode
== AR5K_ANTMODE_FIXED_B
)
1796 ant0
= ant1
= AR5K_ANT_SWTABLE_B
;
1798 ant0
= AR5K_ANT_SWTABLE_A
;
1799 ant1
= AR5K_ANT_SWTABLE_B
;
1802 /* Set antenna idle switch table */
1803 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_ANT_CTL
,
1804 AR5K_PHY_ANT_CTL_SWTABLE_IDLE
,
1805 (ah
->ah_ant_ctl
[ee_mode
][AR5K_ANT_CTL
] |
1806 AR5K_PHY_ANT_CTL_TXRX_EN
));
1808 /* Set antenna switch tables */
1809 ath5k_hw_reg_write(ah
, ah
->ah_ant_ctl
[ee_mode
][ant0
],
1810 AR5K_PHY_ANT_SWITCH_TABLE_0
);
1811 ath5k_hw_reg_write(ah
, ah
->ah_ant_ctl
[ee_mode
][ant1
],
1812 AR5K_PHY_ANT_SWITCH_TABLE_1
);
1816 * Set antenna operating mode
1819 ath5k_hw_set_antenna_mode(struct ath5k_hw
*ah
, u8 ant_mode
)
1821 struct ieee80211_channel
*channel
= ah
->ah_current_channel
;
1822 bool use_def_for_tx
, update_def_on_tx
, use_def_for_rts
, fast_div
;
1823 bool use_def_for_sg
;
1824 u8 def_ant
, tx_ant
, ee_mode
;
1827 /* if channel is not initialized yet we can't set the antennas
1828 * so just store the mode. it will be set on the next reset */
1829 if (channel
== NULL
) {
1830 ah
->ah_ant_mode
= ant_mode
;
1834 def_ant
= ah
->ah_def_ant
;
1836 switch (channel
->hw_value
& CHANNEL_MODES
) {
1840 ee_mode
= AR5K_EEPROM_MODE_11A
;
1844 ee_mode
= AR5K_EEPROM_MODE_11G
;
1847 ee_mode
= AR5K_EEPROM_MODE_11B
;
1850 ATH5K_ERR(ah
->ah_sc
,
1851 "invalid channel: %d\n", channel
->center_freq
);
1856 case AR5K_ANTMODE_DEFAULT
:
1858 use_def_for_tx
= false;
1859 update_def_on_tx
= false;
1860 use_def_for_rts
= false;
1861 use_def_for_sg
= false;
1864 case AR5K_ANTMODE_FIXED_A
:
1867 use_def_for_tx
= true;
1868 update_def_on_tx
= false;
1869 use_def_for_rts
= true;
1870 use_def_for_sg
= true;
1873 case AR5K_ANTMODE_FIXED_B
:
1876 use_def_for_tx
= true;
1877 update_def_on_tx
= false;
1878 use_def_for_rts
= true;
1879 use_def_for_sg
= true;
1882 case AR5K_ANTMODE_SINGLE_AP
:
1883 def_ant
= 1; /* updated on tx */
1885 use_def_for_tx
= true;
1886 update_def_on_tx
= true;
1887 use_def_for_rts
= true;
1888 use_def_for_sg
= true;
1891 case AR5K_ANTMODE_SECTOR_AP
:
1892 tx_ant
= 1; /* variable */
1893 use_def_for_tx
= false;
1894 update_def_on_tx
= false;
1895 use_def_for_rts
= true;
1896 use_def_for_sg
= false;
1899 case AR5K_ANTMODE_SECTOR_STA
:
1900 tx_ant
= 1; /* variable */
1901 use_def_for_tx
= true;
1902 update_def_on_tx
= false;
1903 use_def_for_rts
= true;
1904 use_def_for_sg
= false;
1907 case AR5K_ANTMODE_DEBUG
:
1910 use_def_for_tx
= false;
1911 update_def_on_tx
= false;
1912 use_def_for_rts
= false;
1913 use_def_for_sg
= false;
1920 ah
->ah_tx_ant
= tx_ant
;
1921 ah
->ah_ant_mode
= ant_mode
;
1922 ah
->ah_def_ant
= def_ant
;
1924 sta_id1
|= use_def_for_tx
? AR5K_STA_ID1_DEFAULT_ANTENNA
: 0;
1925 sta_id1
|= update_def_on_tx
? AR5K_STA_ID1_DESC_ANTENNA
: 0;
1926 sta_id1
|= use_def_for_rts
? AR5K_STA_ID1_RTS_DEF_ANTENNA
: 0;
1927 sta_id1
|= use_def_for_sg
? AR5K_STA_ID1_SELFGEN_DEF_ANT
: 0;
1929 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
, AR5K_STA_ID1_ANTENNA_SETTINGS
);
1932 AR5K_REG_ENABLE_BITS(ah
, AR5K_STA_ID1
, sta_id1
);
1934 ath5k_hw_set_antenna_switch(ah
, ee_mode
);
1935 /* Note: set diversity before default antenna
1936 * because it won't work correctly */
1937 ath5k_hw_set_fast_div(ah
, ee_mode
, fast_div
);
1938 ath5k_hw_set_def_antenna(ah
, def_ant
);
1951 * Do linear interpolation between two given (x, y) points
1954 ath5k_get_interpolated_value(s16 target
, s16 x_left
, s16 x_right
,
1955 s16 y_left
, s16 y_right
)
1959 /* Avoid divide by zero and skip interpolation
1960 * if we have the same point */
1961 if ((x_left
== x_right
) || (y_left
== y_right
))
1965 * Since we use ints and not fps, we need to scale up in
1966 * order to get a sane ratio value (or else we 'll eg. get
1967 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1968 * to have some accuracy both for 0.5 and 0.25 steps.
1970 ratio
= ((100 * y_right
- 100 * y_left
)/(x_right
- x_left
));
1972 /* Now scale down to be in range */
1973 result
= y_left
+ (ratio
* (target
- x_left
) / 100);
1979 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1981 * Since we have the top of the curve and we draw the line below
1982 * until we reach 1 (1 pcdac step) we need to know which point
1983 * (x value) that is so that we don't go below y axis and have negative
1984 * pcdac values when creating the curve, or fill the table with zeroes.
1987 ath5k_get_linear_pcdac_min(const u8
*stepL
, const u8
*stepR
,
1988 const s16
*pwrL
, const s16
*pwrR
)
1991 s16 min_pwrL
, min_pwrR
;
1994 /* Some vendors write the same pcdac value twice !!! */
1995 if (stepL
[0] == stepL
[1] || stepR
[0] == stepR
[1])
1996 return max(pwrL
[0], pwrR
[0]);
1998 if (pwrL
[0] == pwrL
[1])
2004 tmp
= (s8
) ath5k_get_interpolated_value(pwr_i
,
2006 stepL
[0], stepL
[1]);
2012 if (pwrR
[0] == pwrR
[1])
2018 tmp
= (s8
) ath5k_get_interpolated_value(pwr_i
,
2020 stepR
[0], stepR
[1]);
2026 /* Keep the right boundary so that it works for both curves */
2027 return max(min_pwrL
, min_pwrR
);
2031 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2032 * Power to PCDAC curve.
2034 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2035 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2036 * PCDAC/PDADC step for each curve is 64 but we can write more than
2037 * one curves on hw so we can go up to 128 (which is the max step we
2038 * can write on the final table).
2040 * We write y values (PCDAC/PDADC steps) on hw.
2043 ath5k_create_power_curve(s16 pmin
, s16 pmax
,
2044 const s16
*pwr
, const u8
*vpd
,
2046 u8
*vpd_table
, u8 type
)
2048 u8 idx
[2] = { 0, 1 };
2055 /* We want the whole line, so adjust boundaries
2056 * to cover the entire power range. Note that
2057 * power values are already 0.25dB so no need
2058 * to multiply pwr_i by 2 */
2059 if (type
== AR5K_PWRTABLE_LINEAR_PCDAC
) {
2065 /* Find surrounding turning points (TPs)
2066 * and interpolate between them */
2067 for (i
= 0; (i
<= (u16
) (pmax
- pmin
)) &&
2068 (i
< AR5K_EEPROM_POWER_TABLE_SIZE
); i
++) {
2070 /* We passed the right TP, move to the next set of TPs
2071 * if we pass the last TP, extrapolate above using the last
2072 * two TPs for ratio */
2073 if ((pwr_i
> pwr
[idx
[1]]) && (idx
[1] < num_points
- 1)) {
2078 vpd_table
[i
] = (u8
) ath5k_get_interpolated_value(pwr_i
,
2079 pwr
[idx
[0]], pwr
[idx
[1]],
2080 vpd
[idx
[0]], vpd
[idx
[1]]);
2082 /* Increase by 0.5dB
2083 * (0.25 dB units) */
2089 * Get the surrounding per-channel power calibration piers
2090 * for a given frequency so that we can interpolate between
2091 * them and come up with an apropriate dataset for our current
2095 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw
*ah
,
2096 struct ieee80211_channel
*channel
,
2097 struct ath5k_chan_pcal_info
**pcinfo_l
,
2098 struct ath5k_chan_pcal_info
**pcinfo_r
)
2100 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
2101 struct ath5k_chan_pcal_info
*pcinfo
;
2104 u32 target
= channel
->center_freq
;
2109 if (!(channel
->hw_value
& CHANNEL_OFDM
)) {
2110 pcinfo
= ee
->ee_pwr_cal_b
;
2111 mode
= AR5K_EEPROM_MODE_11B
;
2112 } else if (channel
->hw_value
& CHANNEL_2GHZ
) {
2113 pcinfo
= ee
->ee_pwr_cal_g
;
2114 mode
= AR5K_EEPROM_MODE_11G
;
2116 pcinfo
= ee
->ee_pwr_cal_a
;
2117 mode
= AR5K_EEPROM_MODE_11A
;
2119 max
= ee
->ee_n_piers
[mode
] - 1;
2121 /* Frequency is below our calibrated
2122 * range. Use the lowest power curve
2124 if (target
< pcinfo
[0].freq
) {
2129 /* Frequency is above our calibrated
2130 * range. Use the highest power curve
2132 if (target
> pcinfo
[max
].freq
) {
2133 idx_l
= idx_r
= max
;
2137 /* Frequency is inside our calibrated
2138 * channel range. Pick the surrounding
2139 * calibration piers so that we can
2141 for (i
= 0; i
<= max
; i
++) {
2143 /* Frequency matches one of our calibration
2144 * piers, no need to interpolate, just use
2145 * that calibration pier */
2146 if (pcinfo
[i
].freq
== target
) {
2151 /* We found a calibration pier that's above
2152 * frequency, use this pier and the previous
2153 * one to interpolate */
2154 if (target
< pcinfo
[i
].freq
) {
2162 *pcinfo_l
= &pcinfo
[idx_l
];
2163 *pcinfo_r
= &pcinfo
[idx_r
];
2167 * Get the surrounding per-rate power calibration data
2168 * for a given frequency and interpolate between power
2169 * values to set max target power supported by hw for
2173 ath5k_get_rate_pcal_data(struct ath5k_hw
*ah
,
2174 struct ieee80211_channel
*channel
,
2175 struct ath5k_rate_pcal_info
*rates
)
2177 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
2178 struct ath5k_rate_pcal_info
*rpinfo
;
2181 u32 target
= channel
->center_freq
;
2186 if (!(channel
->hw_value
& CHANNEL_OFDM
)) {
2187 rpinfo
= ee
->ee_rate_tpwr_b
;
2188 mode
= AR5K_EEPROM_MODE_11B
;
2189 } else if (channel
->hw_value
& CHANNEL_2GHZ
) {
2190 rpinfo
= ee
->ee_rate_tpwr_g
;
2191 mode
= AR5K_EEPROM_MODE_11G
;
2193 rpinfo
= ee
->ee_rate_tpwr_a
;
2194 mode
= AR5K_EEPROM_MODE_11A
;
2196 max
= ee
->ee_rate_target_pwr_num
[mode
] - 1;
2198 /* Get the surrounding calibration
2199 * piers - same as above */
2200 if (target
< rpinfo
[0].freq
) {
2205 if (target
> rpinfo
[max
].freq
) {
2206 idx_l
= idx_r
= max
;
2210 for (i
= 0; i
<= max
; i
++) {
2212 if (rpinfo
[i
].freq
== target
) {
2217 if (target
< rpinfo
[i
].freq
) {
2225 /* Now interpolate power value, based on the frequency */
2226 rates
->freq
= target
;
2228 rates
->target_power_6to24
=
2229 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
2231 rpinfo
[idx_l
].target_power_6to24
,
2232 rpinfo
[idx_r
].target_power_6to24
);
2234 rates
->target_power_36
=
2235 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
2237 rpinfo
[idx_l
].target_power_36
,
2238 rpinfo
[idx_r
].target_power_36
);
2240 rates
->target_power_48
=
2241 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
2243 rpinfo
[idx_l
].target_power_48
,
2244 rpinfo
[idx_r
].target_power_48
);
2246 rates
->target_power_54
=
2247 ath5k_get_interpolated_value(target
, rpinfo
[idx_l
].freq
,
2249 rpinfo
[idx_l
].target_power_54
,
2250 rpinfo
[idx_r
].target_power_54
);
2254 * Get the max edge power for this channel if
2255 * we have such data from EEPROM's Conformance Test
2256 * Limits (CTL), and limit max power if needed.
2259 ath5k_get_max_ctl_power(struct ath5k_hw
*ah
,
2260 struct ieee80211_channel
*channel
)
2262 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2263 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
2264 struct ath5k_edge_power
*rep
= ee
->ee_ctl_pwr
;
2265 u8
*ctl_val
= ee
->ee_ctl
;
2266 s16 max_chan_pwr
= ah
->ah_txpower
.txp_max_pwr
/ 4;
2271 u32 target
= channel
->center_freq
;
2273 ctl_mode
= ath_regd_get_band_ctl(regulatory
, channel
->band
);
2275 switch (channel
->hw_value
& CHANNEL_MODES
) {
2277 ctl_mode
|= AR5K_CTL_11A
;
2280 ctl_mode
|= AR5K_CTL_11G
;
2283 ctl_mode
|= AR5K_CTL_11B
;
2286 ctl_mode
|= AR5K_CTL_TURBO
;
2289 ctl_mode
|= AR5K_CTL_TURBOG
;
2297 for (i
= 0; i
< ee
->ee_ctls
; i
++) {
2298 if (ctl_val
[i
] == ctl_mode
) {
2304 /* If we have a CTL dataset available grab it and find the
2305 * edge power for our frequency */
2306 if (ctl_idx
== 0xFF)
2309 /* Edge powers are sorted by frequency from lower
2310 * to higher. Each CTL corresponds to 8 edge power
2312 rep_idx
= ctl_idx
* AR5K_EEPROM_N_EDGES
;
2314 /* Don't do boundaries check because we
2315 * might have more that one bands defined
2318 /* Get the edge power that's closer to our
2320 for (i
= 0; i
< AR5K_EEPROM_N_EDGES
; i
++) {
2322 if (target
<= rep
[rep_idx
].freq
)
2323 edge_pwr
= (s16
) rep
[rep_idx
].edge
;
2327 ah
->ah_txpower
.txp_max_pwr
= 4*min(edge_pwr
, max_chan_pwr
);
2332 * Power to PCDAC table functions
2336 * Fill Power to PCDAC table on RF5111
2338 * No further processing is needed for RF5111, the only thing we have to
2339 * do is fill the values below and above calibration range since eeprom data
2340 * may not cover the entire PCDAC table.
2343 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw
*ah
, s16
* table_min
,
2346 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
2347 u8
*pcdac_tmp
= ah
->ah_txpower
.tmpL
[0];
2348 u8 pcdac_0
, pcdac_n
, pcdac_i
, pwr_idx
, i
;
2349 s16 min_pwr
, max_pwr
;
2351 /* Get table boundaries */
2352 min_pwr
= table_min
[0];
2353 pcdac_0
= pcdac_tmp
[0];
2355 max_pwr
= table_max
[0];
2356 pcdac_n
= pcdac_tmp
[table_max
[0] - table_min
[0]];
2358 /* Extrapolate below minimum using pcdac_0 */
2360 for (i
= 0; i
< min_pwr
; i
++)
2361 pcdac_out
[pcdac_i
++] = pcdac_0
;
2363 /* Copy values from pcdac_tmp */
2365 for (i
= 0 ; pwr_idx
<= max_pwr
&&
2366 pcdac_i
< AR5K_EEPROM_POWER_TABLE_SIZE
; i
++) {
2367 pcdac_out
[pcdac_i
++] = pcdac_tmp
[i
];
2371 /* Extrapolate above maximum */
2372 while (pcdac_i
< AR5K_EEPROM_POWER_TABLE_SIZE
)
2373 pcdac_out
[pcdac_i
++] = pcdac_n
;
2378 * Combine available XPD Curves and fill Linear Power to PCDAC table
2381 * RFX112 can have up to 2 curves (one for low txpower range and one for
2382 * higher txpower range). We need to put them both on pcdac_out and place
2383 * them in the correct location. In case we only have one curve available
2384 * just fit it on pcdac_out (it's supposed to cover the entire range of
2385 * available pwr levels since it's always the higher power curve). Extrapolate
2386 * below and above final table if needed.
2389 ath5k_combine_linear_pcdac_curves(struct ath5k_hw
*ah
, s16
* table_min
,
2390 s16
*table_max
, u8 pdcurves
)
2392 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
2399 s16 mid_pwr_idx
= 0;
2400 /* Edge flag turs on the 7nth bit on the PCDAC
2401 * to delcare the higher power curve (force values
2402 * to be greater than 64). If we only have one curve
2403 * we don't need to set this, if we have 2 curves and
2404 * fill the table backwards this can also be used to
2405 * switch from higher power curve to lower power curve */
2409 /* When we have only one curve available
2410 * that's the higher power curve. If we have
2411 * two curves the first is the high power curve
2412 * and the next is the low power curve. */
2414 pcdac_low_pwr
= ah
->ah_txpower
.tmpL
[1];
2415 pcdac_high_pwr
= ah
->ah_txpower
.tmpL
[0];
2416 mid_pwr_idx
= table_max
[1] - table_min
[1] - 1;
2417 max_pwr_idx
= (table_max
[0] - table_min
[0]) / 2;
2419 /* If table size goes beyond 31.5dB, keep the
2420 * upper 31.5dB range when setting tx power.
2421 * Note: 126 = 31.5 dB in quarter dB steps */
2422 if (table_max
[0] - table_min
[1] > 126)
2423 min_pwr_idx
= table_max
[0] - 126;
2425 min_pwr_idx
= table_min
[1];
2427 /* Since we fill table backwards
2428 * start from high power curve */
2429 pcdac_tmp
= pcdac_high_pwr
;
2433 pcdac_low_pwr
= ah
->ah_txpower
.tmpL
[1]; /* Zeroed */
2434 pcdac_high_pwr
= ah
->ah_txpower
.tmpL
[0];
2435 min_pwr_idx
= table_min
[0];
2436 max_pwr_idx
= (table_max
[0] - table_min
[0]) / 2;
2437 pcdac_tmp
= pcdac_high_pwr
;
2441 /* This is used when setting tx power*/
2442 ah
->ah_txpower
.txp_min_idx
= min_pwr_idx
/2;
2444 /* Fill Power to PCDAC table backwards */
2446 for (i
= 63; i
>= 0; i
--) {
2447 /* Entering lower power range, reset
2448 * edge flag and set pcdac_tmp to lower
2450 if (edge_flag
== 0x40 &&
2451 (2*pwr
<= (table_max
[1] - table_min
[0]) || pwr
== 0)) {
2453 pcdac_tmp
= pcdac_low_pwr
;
2454 pwr
= mid_pwr_idx
/2;
2457 /* Don't go below 1, extrapolate below if we have
2458 * already swithced to the lower power curve -or
2459 * we only have one curve and edge_flag is zero
2461 if (pcdac_tmp
[pwr
] < 1 && (edge_flag
== 0x00)) {
2463 pcdac_out
[i
] = pcdac_out
[i
+ 1];
2469 pcdac_out
[i
] = pcdac_tmp
[pwr
] | edge_flag
;
2471 /* Extrapolate above if pcdac is greater than
2472 * 126 -this can happen because we OR pcdac_out
2473 * value with edge_flag on high power curve */
2474 if (pcdac_out
[i
] > 126)
2477 /* Decrease by a 0.5dB step */
2482 /* Write PCDAC values on hw */
2484 ath5k_setup_pcdac_table(struct ath5k_hw
*ah
)
2486 u8
*pcdac_out
= ah
->ah_txpower
.txp_pd_table
;
2490 * Write TX power values
2492 for (i
= 0; i
< (AR5K_EEPROM_POWER_TABLE_SIZE
/ 2); i
++) {
2493 ath5k_hw_reg_write(ah
,
2494 (((pcdac_out
[2*i
+ 0] << 8 | 0xff) & 0xffff) << 0) |
2495 (((pcdac_out
[2*i
+ 1] << 8 | 0xff) & 0xffff) << 16),
2496 AR5K_PHY_PCDAC_TXPOWER(i
));
2502 * Power to PDADC table functions
2506 * Set the gain boundaries and create final Power to PDADC table
2508 * We can have up to 4 pd curves, we need to do a simmilar process
2509 * as we do for RF5112. This time we don't have an edge_flag but we
2510 * set the gain boundaries on a separate register.
2513 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw
*ah
,
2514 s16
*pwr_min
, s16
*pwr_max
, u8 pdcurves
)
2516 u8 gain_boundaries
[AR5K_EEPROM_N_PD_GAINS
];
2517 u8
*pdadc_out
= ah
->ah_txpower
.txp_pd_table
;
2520 u8 pdadc_i
, pdadc_n
, pwr_step
, pdg
, max_idx
, table_size
;
2523 /* Note: Register value is initialized on initvals
2524 * there is no feedback from hw.
2525 * XXX: What about pd_gain_overlap from EEPROM ? */
2526 pd_gain_overlap
= (u8
) ath5k_hw_reg_read(ah
, AR5K_PHY_TPC_RG5
) &
2527 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP
;
2529 /* Create final PDADC table */
2530 for (pdg
= 0, pdadc_i
= 0; pdg
< pdcurves
; pdg
++) {
2531 pdadc_tmp
= ah
->ah_txpower
.tmpL
[pdg
];
2533 if (pdg
== pdcurves
- 1)
2534 /* 2 dB boundary stretch for last
2535 * (higher power) curve */
2536 gain_boundaries
[pdg
] = pwr_max
[pdg
] + 4;
2538 /* Set gain boundary in the middle
2539 * between this curve and the next one */
2540 gain_boundaries
[pdg
] =
2541 (pwr_max
[pdg
] + pwr_min
[pdg
+ 1]) / 2;
2543 /* Sanity check in case our 2 db stretch got out of
2545 if (gain_boundaries
[pdg
] > AR5K_TUNE_MAX_TXPOWER
)
2546 gain_boundaries
[pdg
] = AR5K_TUNE_MAX_TXPOWER
;
2548 /* For the first curve (lower power)
2549 * start from 0 dB */
2553 /* For the other curves use the gain overlap */
2554 pdadc_0
= (gain_boundaries
[pdg
- 1] - pwr_min
[pdg
]) -
2557 /* Force each power step to be at least 0.5 dB */
2558 if ((pdadc_tmp
[1] - pdadc_tmp
[0]) > 1)
2559 pwr_step
= pdadc_tmp
[1] - pdadc_tmp
[0];
2563 /* If pdadc_0 is negative, we need to extrapolate
2564 * below this pdgain by a number of pwr_steps */
2565 while ((pdadc_0
< 0) && (pdadc_i
< 128)) {
2566 s16 tmp
= pdadc_tmp
[0] + pdadc_0
* pwr_step
;
2567 pdadc_out
[pdadc_i
++] = (tmp
< 0) ? 0 : (u8
) tmp
;
2571 /* Set last pwr level, using gain boundaries */
2572 pdadc_n
= gain_boundaries
[pdg
] + pd_gain_overlap
- pwr_min
[pdg
];
2573 /* Limit it to be inside pwr range */
2574 table_size
= pwr_max
[pdg
] - pwr_min
[pdg
];
2575 max_idx
= (pdadc_n
< table_size
) ? pdadc_n
: table_size
;
2577 /* Fill pdadc_out table */
2578 while (pdadc_0
< max_idx
&& pdadc_i
< 128)
2579 pdadc_out
[pdadc_i
++] = pdadc_tmp
[pdadc_0
++];
2581 /* Need to extrapolate above this pdgain? */
2582 if (pdadc_n
<= max_idx
)
2585 /* Force each power step to be at least 0.5 dB */
2586 if ((pdadc_tmp
[table_size
- 1] - pdadc_tmp
[table_size
- 2]) > 1)
2587 pwr_step
= pdadc_tmp
[table_size
- 1] -
2588 pdadc_tmp
[table_size
- 2];
2592 /* Extrapolate above */
2593 while ((pdadc_0
< (s16
) pdadc_n
) &&
2594 (pdadc_i
< AR5K_EEPROM_POWER_TABLE_SIZE
* 2)) {
2595 s16 tmp
= pdadc_tmp
[table_size
- 1] +
2596 (pdadc_0
- max_idx
) * pwr_step
;
2597 pdadc_out
[pdadc_i
++] = (tmp
> 127) ? 127 : (u8
) tmp
;
2602 while (pdg
< AR5K_EEPROM_N_PD_GAINS
) {
2603 gain_boundaries
[pdg
] = gain_boundaries
[pdg
- 1];
2607 while (pdadc_i
< AR5K_EEPROM_POWER_TABLE_SIZE
* 2) {
2608 pdadc_out
[pdadc_i
] = pdadc_out
[pdadc_i
- 1];
2612 /* Set gain boundaries */
2613 ath5k_hw_reg_write(ah
,
2614 AR5K_REG_SM(pd_gain_overlap
,
2615 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP
) |
2616 AR5K_REG_SM(gain_boundaries
[0],
2617 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1
) |
2618 AR5K_REG_SM(gain_boundaries
[1],
2619 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2
) |
2620 AR5K_REG_SM(gain_boundaries
[2],
2621 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3
) |
2622 AR5K_REG_SM(gain_boundaries
[3],
2623 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4
),
2626 /* Used for setting rate power table */
2627 ah
->ah_txpower
.txp_min_idx
= pwr_min
[0];
2631 /* Write PDADC values on hw */
2633 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw
*ah
,
2634 u8 pdcurves
, u8
*pdg_to_idx
)
2636 u8
*pdadc_out
= ah
->ah_txpower
.txp_pd_table
;
2640 /* Select the right pdgain curves */
2642 /* Clear current settings */
2643 reg
= ath5k_hw_reg_read(ah
, AR5K_PHY_TPC_RG1
);
2644 reg
&= ~(AR5K_PHY_TPC_RG1_PDGAIN_1
|
2645 AR5K_PHY_TPC_RG1_PDGAIN_2
|
2646 AR5K_PHY_TPC_RG1_PDGAIN_3
|
2647 AR5K_PHY_TPC_RG1_NUM_PD_GAIN
);
2650 * Use pd_gains curve from eeprom
2652 * This overrides the default setting from initvals
2653 * in case some vendors (e.g. Zcomax) don't use the default
2654 * curves. If we don't honor their settings we 'll get a
2655 * 5dB (1 * gain overlap ?) drop.
2657 reg
|= AR5K_REG_SM(pdcurves
, AR5K_PHY_TPC_RG1_NUM_PD_GAIN
);
2661 reg
|= AR5K_REG_SM(pdg_to_idx
[2], AR5K_PHY_TPC_RG1_PDGAIN_3
);
2664 reg
|= AR5K_REG_SM(pdg_to_idx
[1], AR5K_PHY_TPC_RG1_PDGAIN_2
);
2667 reg
|= AR5K_REG_SM(pdg_to_idx
[0], AR5K_PHY_TPC_RG1_PDGAIN_1
);
2670 ath5k_hw_reg_write(ah
, reg
, AR5K_PHY_TPC_RG1
);
2673 * Write TX power values
2675 for (i
= 0; i
< (AR5K_EEPROM_POWER_TABLE_SIZE
/ 2); i
++) {
2676 ath5k_hw_reg_write(ah
,
2677 ((pdadc_out
[4*i
+ 0] & 0xff) << 0) |
2678 ((pdadc_out
[4*i
+ 1] & 0xff) << 8) |
2679 ((pdadc_out
[4*i
+ 2] & 0xff) << 16) |
2680 ((pdadc_out
[4*i
+ 3] & 0xff) << 24),
2681 AR5K_PHY_PDADC_TXPOWER(i
));
2687 * Common code for PCDAC/PDADC tables
2691 * This is the main function that uses all of the above
2692 * to set PCDAC/PDADC table on hw for the current channel.
2693 * This table is used for tx power calibration on the basband,
2694 * without it we get weird tx power levels and in some cases
2695 * distorted spectral mask
2698 ath5k_setup_channel_powertable(struct ath5k_hw
*ah
,
2699 struct ieee80211_channel
*channel
,
2700 u8 ee_mode
, u8 type
)
2702 struct ath5k_pdgain_info
*pdg_L
, *pdg_R
;
2703 struct ath5k_chan_pcal_info
*pcinfo_L
;
2704 struct ath5k_chan_pcal_info
*pcinfo_R
;
2705 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
2706 u8
*pdg_curve_to_idx
= ee
->ee_pdc_to_idx
[ee_mode
];
2707 s16 table_min
[AR5K_EEPROM_N_PD_GAINS
];
2708 s16 table_max
[AR5K_EEPROM_N_PD_GAINS
];
2711 u32 target
= channel
->center_freq
;
2714 /* Get surounding freq piers for this channel */
2715 ath5k_get_chan_pcal_surrounding_piers(ah
, channel
,
2719 /* Loop over pd gain curves on
2720 * surounding freq piers by index */
2721 for (pdg
= 0; pdg
< ee
->ee_pd_gains
[ee_mode
]; pdg
++) {
2723 /* Fill curves in reverse order
2724 * from lower power (max gain)
2725 * to higher power. Use curve -> idx
2726 * backmapping we did on eeprom init */
2727 u8 idx
= pdg_curve_to_idx
[pdg
];
2729 /* Grab the needed curves by index */
2730 pdg_L
= &pcinfo_L
->pd_curves
[idx
];
2731 pdg_R
= &pcinfo_R
->pd_curves
[idx
];
2733 /* Initialize the temp tables */
2734 tmpL
= ah
->ah_txpower
.tmpL
[pdg
];
2735 tmpR
= ah
->ah_txpower
.tmpR
[pdg
];
2737 /* Set curve's x boundaries and create
2738 * curves so that they cover the same
2739 * range (if we don't do that one table
2740 * will have values on some range and the
2741 * other one won't have any so interpolation
2743 table_min
[pdg
] = min(pdg_L
->pd_pwr
[0],
2744 pdg_R
->pd_pwr
[0]) / 2;
2746 table_max
[pdg
] = max(pdg_L
->pd_pwr
[pdg_L
->pd_points
- 1],
2747 pdg_R
->pd_pwr
[pdg_R
->pd_points
- 1]) / 2;
2749 /* Now create the curves on surrounding channels
2750 * and interpolate if needed to get the final
2751 * curve for this gain on this channel */
2753 case AR5K_PWRTABLE_LINEAR_PCDAC
:
2754 /* Override min/max so that we don't loose
2755 * accuracy (don't divide by 2) */
2756 table_min
[pdg
] = min(pdg_L
->pd_pwr
[0],
2760 max(pdg_L
->pd_pwr
[pdg_L
->pd_points
- 1],
2761 pdg_R
->pd_pwr
[pdg_R
->pd_points
- 1]);
2763 /* Override minimum so that we don't get
2764 * out of bounds while extrapolating
2765 * below. Don't do this when we have 2
2766 * curves and we are on the high power curve
2767 * because table_min is ok in this case */
2768 if (!(ee
->ee_pd_gains
[ee_mode
] > 1 && pdg
== 0)) {
2771 ath5k_get_linear_pcdac_min(pdg_L
->pd_step
,
2776 /* Don't go too low because we will
2777 * miss the upper part of the curve.
2778 * Note: 126 = 31.5dB (max power supported)
2779 * in 0.25dB units */
2780 if (table_max
[pdg
] - table_min
[pdg
] > 126)
2781 table_min
[pdg
] = table_max
[pdg
] - 126;
2785 case AR5K_PWRTABLE_PWR_TO_PCDAC
:
2786 case AR5K_PWRTABLE_PWR_TO_PDADC
:
2788 ath5k_create_power_curve(table_min
[pdg
],
2792 pdg_L
->pd_points
, tmpL
, type
);
2794 /* We are in a calibration
2795 * pier, no need to interpolate
2796 * between freq piers */
2797 if (pcinfo_L
== pcinfo_R
)
2800 ath5k_create_power_curve(table_min
[pdg
],
2804 pdg_R
->pd_points
, tmpR
, type
);
2810 /* Interpolate between curves
2811 * of surounding freq piers to
2812 * get the final curve for this
2813 * pd gain. Re-use tmpL for interpolation
2815 for (i
= 0; (i
< (u16
) (table_max
[pdg
] - table_min
[pdg
])) &&
2816 (i
< AR5K_EEPROM_POWER_TABLE_SIZE
); i
++) {
2817 tmpL
[i
] = (u8
) ath5k_get_interpolated_value(target
,
2818 (s16
) pcinfo_L
->freq
,
2819 (s16
) pcinfo_R
->freq
,
2825 /* Now we have a set of curves for this
2826 * channel on tmpL (x range is table_max - table_min
2827 * and y values are tmpL[pdg][]) sorted in the same
2828 * order as EEPROM (because we've used the backmapping).
2829 * So for RF5112 it's from higher power to lower power
2830 * and for RF2413 it's from lower power to higher power.
2831 * For RF5111 we only have one curve. */
2833 /* Fill min and max power levels for this
2834 * channel by interpolating the values on
2835 * surounding channels to complete the dataset */
2836 ah
->ah_txpower
.txp_min_pwr
= ath5k_get_interpolated_value(target
,
2837 (s16
) pcinfo_L
->freq
,
2838 (s16
) pcinfo_R
->freq
,
2839 pcinfo_L
->min_pwr
, pcinfo_R
->min_pwr
);
2841 ah
->ah_txpower
.txp_max_pwr
= ath5k_get_interpolated_value(target
,
2842 (s16
) pcinfo_L
->freq
,
2843 (s16
) pcinfo_R
->freq
,
2844 pcinfo_L
->max_pwr
, pcinfo_R
->max_pwr
);
2846 /* We are ready to go, fill PCDAC/PDADC
2847 * table and write settings on hardware */
2849 case AR5K_PWRTABLE_LINEAR_PCDAC
:
2850 /* For RF5112 we can have one or two curves
2851 * and each curve covers a certain power lvl
2852 * range so we need to do some more processing */
2853 ath5k_combine_linear_pcdac_curves(ah
, table_min
, table_max
,
2854 ee
->ee_pd_gains
[ee_mode
]);
2856 /* Set txp.offset so that we can
2857 * match max power value with max
2859 ah
->ah_txpower
.txp_offset
= 64 - (table_max
[0] / 2);
2861 /* Write settings on hw */
2862 ath5k_setup_pcdac_table(ah
);
2864 case AR5K_PWRTABLE_PWR_TO_PCDAC
:
2865 /* We are done for RF5111 since it has only
2866 * one curve, just fit the curve on the table */
2867 ath5k_fill_pwr_to_pcdac_table(ah
, table_min
, table_max
);
2869 /* No rate powertable adjustment for RF5111 */
2870 ah
->ah_txpower
.txp_min_idx
= 0;
2871 ah
->ah_txpower
.txp_offset
= 0;
2873 /* Write settings on hw */
2874 ath5k_setup_pcdac_table(ah
);
2876 case AR5K_PWRTABLE_PWR_TO_PDADC
:
2877 /* Set PDADC boundaries and fill
2878 * final PDADC table */
2879 ath5k_combine_pwr_to_pdadc_curves(ah
, table_min
, table_max
,
2880 ee
->ee_pd_gains
[ee_mode
]);
2882 /* Write settings on hw */
2883 ath5k_setup_pwr_to_pdadc_table(ah
, pdg
, pdg_curve_to_idx
);
2885 /* Set txp.offset, note that table_min
2886 * can be negative */
2887 ah
->ah_txpower
.txp_offset
= table_min
[0];
2898 * Per-rate tx power setting
2900 * This is the code that sets the desired tx power (below
2901 * maximum) on hw for each rate (we also have TPC that sets
2902 * power per packet). We do that by providing an index on the
2903 * PCDAC/PDADC table we set up.
2907 * Set rate power table
2909 * For now we only limit txpower based on maximum tx power
2910 * supported by hw (what's inside rate_info). We need to limit
2911 * this even more, based on regulatory domain etc.
2913 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2914 * and is indexed as follows:
2915 * rates[0] - rates[7] -> OFDM rates
2916 * rates[8] - rates[14] -> CCK rates
2917 * rates[15] -> XR rates (they all have the same power)
2920 ath5k_setup_rate_powertable(struct ath5k_hw
*ah
, u16 max_pwr
,
2921 struct ath5k_rate_pcal_info
*rate_info
,
2927 /* max_pwr is power level we got from driver/user in 0.5dB
2928 * units, switch to 0.25dB units so we can compare */
2930 max_pwr
= min(max_pwr
, (u16
) ah
->ah_txpower
.txp_max_pwr
) / 2;
2932 /* apply rate limits */
2933 rates
= ah
->ah_txpower
.txp_rates_power_table
;
2935 /* OFDM rates 6 to 24Mb/s */
2936 for (i
= 0; i
< 5; i
++)
2937 rates
[i
] = min(max_pwr
, rate_info
->target_power_6to24
);
2939 /* Rest OFDM rates */
2940 rates
[5] = min(rates
[0], rate_info
->target_power_36
);
2941 rates
[6] = min(rates
[0], rate_info
->target_power_48
);
2942 rates
[7] = min(rates
[0], rate_info
->target_power_54
);
2946 rates
[8] = min(rates
[0], rate_info
->target_power_6to24
);
2948 rates
[9] = min(rates
[0], rate_info
->target_power_36
);
2950 rates
[10] = min(rates
[0], rate_info
->target_power_36
);
2952 rates
[11] = min(rates
[0], rate_info
->target_power_48
);
2954 rates
[12] = min(rates
[0], rate_info
->target_power_48
);
2956 rates
[13] = min(rates
[0], rate_info
->target_power_54
);
2958 rates
[14] = min(rates
[0], rate_info
->target_power_54
);
2961 rates
[15] = min(rates
[0], rate_info
->target_power_6to24
);
2963 /* CCK rates have different peak to average ratio
2964 * so we have to tweak their power so that gainf
2965 * correction works ok. For this we use OFDM to
2966 * CCK delta from eeprom */
2967 if ((ee_mode
== AR5K_EEPROM_MODE_11G
) &&
2968 (ah
->ah_phy_revision
< AR5K_SREV_PHY_5212A
))
2969 for (i
= 8; i
<= 15; i
++)
2970 rates
[i
] -= ah
->ah_txpower
.txp_cck_ofdm_gainf_delta
;
2972 /* Now that we have all rates setup use table offset to
2973 * match the power range set by user with the power indices
2974 * on PCDAC/PDADC table */
2975 for (i
= 0; i
< 16; i
++) {
2976 rates
[i
] += ah
->ah_txpower
.txp_offset
;
2977 /* Don't get out of bounds */
2982 /* Min/max in 0.25dB units */
2983 ah
->ah_txpower
.txp_min_pwr
= 2 * rates
[7];
2984 ah
->ah_txpower
.txp_max_pwr
= 2 * rates
[0];
2985 ah
->ah_txpower
.txp_ofdm
= rates
[7];
2990 * Set transmission power
2993 ath5k_hw_txpower(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
,
2994 u8 ee_mode
, u8 txpower
)
2996 struct ath5k_rate_pcal_info rate_info
;
3000 if (txpower
> AR5K_TUNE_MAX_TXPOWER
) {
3001 ATH5K_ERR(ah
->ah_sc
, "invalid tx power: %u\n", txpower
);
3005 /* Reset TX power values */
3006 memset(&ah
->ah_txpower
, 0, sizeof(ah
->ah_txpower
));
3007 ah
->ah_txpower
.txp_tpc
= AR5K_TUNE_TPC_TXPOWER
;
3008 ah
->ah_txpower
.txp_min_pwr
= 0;
3009 ah
->ah_txpower
.txp_max_pwr
= AR5K_TUNE_MAX_TXPOWER
;
3011 /* Initialize TX power table */
3012 switch (ah
->ah_radio
) {
3014 type
= AR5K_PWRTABLE_PWR_TO_PCDAC
;
3017 type
= AR5K_PWRTABLE_LINEAR_PCDAC
;
3024 type
= AR5K_PWRTABLE_PWR_TO_PDADC
;
3030 /* FIXME: Only on channel/mode change */
3031 ret
= ath5k_setup_channel_powertable(ah
, channel
, ee_mode
, type
);
3035 /* Limit max power if we have a CTL available */
3036 ath5k_get_max_ctl_power(ah
, channel
);
3038 /* FIXME: Antenna reduction stuff */
3040 /* FIXME: Limit power on turbo modes */
3042 /* FIXME: TPC scale reduction */
3044 /* Get surounding channels for per-rate power table
3046 ath5k_get_rate_pcal_data(ah
, channel
, &rate_info
);
3048 /* Setup rate power table */
3049 ath5k_setup_rate_powertable(ah
, txpower
, &rate_info
, ee_mode
);
3051 /* Write rate power table on hw */
3052 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_OFDM(3, 24) |
3053 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3054 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1
);
3056 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_OFDM(7, 24) |
3057 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3058 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2
);
3060 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_CCK(10, 24) |
3061 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3062 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3
);
3064 ath5k_hw_reg_write(ah
, AR5K_TXPOWER_CCK(14, 24) |
3065 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3066 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4
);
3068 /* FIXME: TPC support */
3069 if (ah
->ah_txpower
.txp_tpc
) {
3070 ath5k_hw_reg_write(ah
, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE
|
3071 AR5K_TUNE_MAX_TXPOWER
, AR5K_PHY_TXPOWER_RATE_MAX
);
3073 ath5k_hw_reg_write(ah
,
3074 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_ACK
) |
3075 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_CTS
) |
3076 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER
, AR5K_TPC_CHIRP
),
3079 ath5k_hw_reg_write(ah
, AR5K_PHY_TXPOWER_RATE_MAX
|
3080 AR5K_TUNE_MAX_TXPOWER
, AR5K_PHY_TXPOWER_RATE_MAX
);
3086 int ath5k_hw_set_txpower_limit(struct ath5k_hw
*ah
, u8 txpower
)
3089 struct ieee80211_channel
*channel
= ah
->ah_current_channel
;
3092 switch (channel
->hw_value
& CHANNEL_MODES
) {
3096 ee_mode
= AR5K_EEPROM_MODE_11A
;
3100 ee_mode
= AR5K_EEPROM_MODE_11G
;
3103 ee_mode
= AR5K_EEPROM_MODE_11B
;
3106 ATH5K_ERR(ah
->ah_sc
,
3107 "invalid channel: %d\n", channel
->center_freq
);
3111 ATH5K_DBG(ah
->ah_sc
, ATH5K_DEBUG_TXPOWER
,
3112 "changing txpower to %d\n", txpower
);
3114 return ath5k_hw_txpower(ah
, channel
, ee_mode
, txpower
);