2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 /****************************\
23 Reset function and helpers
24 \****************************/
26 #include <asm/unaligned.h>
28 #include <linux/pci.h> /* To determine if a card is pci-e */
29 #include <linux/log2.h>
30 #include <linux/platform_device.h>
37 * DOC: Reset function and helpers
39 * Here we implement the main reset routine, used to bring the card
40 * to a working state and ready to receive. We also handle routines
41 * that don't fit on other places such as clock, sleep and power control
50 * ath5k_hw_register_timeout() - Poll a register for a flag/field change
51 * @ah: The &struct ath5k_hw
52 * @reg: The register to read
53 * @flag: The flag/field to check on the register
54 * @val: The field value we expect (if we check a field)
55 * @is_set: Instead of checking if the flag got cleared, check if it got set
57 * Some registers contain flags that indicate that an operation is
58 * running. We use this function to poll these registers and check
59 * if these flags get cleared. We also use it to poll a register
60 * field (containing multiple flags) until it gets a specific value.
62 * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
65 ath5k_hw_register_timeout(struct ath5k_hw
*ah
, u32 reg
, u32 flag
, u32 val
,
71 for (i
= AR5K_TUNE_REGISTER_TIMEOUT
; i
> 0; i
--) {
72 data
= ath5k_hw_reg_read(ah
, reg
);
73 if (is_set
&& (data
& flag
))
75 else if ((data
& flag
) == val
)
80 return (i
<= 0) ? -EAGAIN
: 0;
84 /*************************\
85 * Clock related functions *
86 \*************************/
89 * ath5k_hw_htoclock() - Translate usec to hw clock units
90 * @ah: The &struct ath5k_hw
91 * @usec: value in microseconds
93 * Translate usecs to hw clock units based on the current
96 * Returns number of clock units
99 ath5k_hw_htoclock(struct ath5k_hw
*ah
, unsigned int usec
)
101 struct ath_common
*common
= ath5k_hw_common(ah
);
102 return usec
* common
->clockrate
;
106 * ath5k_hw_clocktoh() - Translate hw clock units to usec
107 * @ah: The &struct ath5k_hw
108 * @clock: value in hw clock units
110 * Translate hw clock units to usecs based on the current
113 * Returns number of usecs
116 ath5k_hw_clocktoh(struct ath5k_hw
*ah
, unsigned int clock
)
118 struct ath_common
*common
= ath5k_hw_common(ah
);
119 return clock
/ common
->clockrate
;
123 * ath5k_hw_init_core_clock() - Initialize core clock
124 * @ah: The &struct ath5k_hw
126 * Initialize core clock parameters (usec, usec32, latencies etc),
127 * based on current bwmode and chipset properties.
130 ath5k_hw_init_core_clock(struct ath5k_hw
*ah
)
132 struct ieee80211_channel
*channel
= ah
->ah_current_channel
;
133 struct ath_common
*common
= ath5k_hw_common(ah
);
134 u32 usec_reg
, txlat
, rxlat
, usec
, clock
, sclock
, txf2txs
;
137 * Set core clock frequency
139 switch (channel
->hw_value
) {
152 /* Use clock multiplier for non-default
154 switch (ah
->ah_bwmode
) {
155 case AR5K_BWMODE_40MHZ
:
158 case AR5K_BWMODE_10MHZ
:
161 case AR5K_BWMODE_5MHZ
:
168 common
->clockrate
= clock
;
171 * Set USEC parameters
173 /* Set USEC counter on PCU*/
175 usec
= AR5K_REG_SM(usec
, AR5K_USEC_1
);
177 /* Set usec duration on DCU */
178 if (ah
->ah_version
!= AR5K_AR5210
)
179 AR5K_REG_WRITE_BITS(ah
, AR5K_DCU_GBL_IFS_MISC
,
180 AR5K_DCU_GBL_IFS_MISC_USEC_DUR
,
183 /* Set 32MHz USEC counter */
184 if ((ah
->ah_radio
== AR5K_RF5112
) ||
185 (ah
->ah_radio
== AR5K_RF2413
) ||
186 (ah
->ah_radio
== AR5K_RF5413
) ||
187 (ah
->ah_radio
== AR5K_RF2316
) ||
188 (ah
->ah_radio
== AR5K_RF2317
))
189 /* Remain on 40MHz clock ? */
193 sclock
= AR5K_REG_SM(sclock
, AR5K_USEC_32
);
196 * Set tx/rx latencies
198 usec_reg
= ath5k_hw_reg_read(ah
, AR5K_USEC_5211
);
199 txlat
= AR5K_REG_MS(usec_reg
, AR5K_USEC_TX_LATENCY_5211
);
200 rxlat
= AR5K_REG_MS(usec_reg
, AR5K_USEC_RX_LATENCY_5211
);
203 * Set default Tx frame to Tx data start delay
205 txf2txs
= AR5K_INIT_TXF2TXD_START_DEFAULT
;
208 * 5210 initvals don't include usec settings
209 * so we need to use magic values here for
212 if (ah
->ah_version
== AR5K_AR5210
) {
214 txlat
= AR5K_INIT_TX_LATENCY_5210
;
215 rxlat
= AR5K_INIT_RX_LATENCY_5210
;
218 if (ah
->ah_mac_srev
< AR5K_SREV_AR5211
) {
219 /* 5311 has different tx/rx latency masks
220 * from 5211, since we deal 5311 the same
221 * as 5211 when setting initvals, shift
222 * values here to their proper locations
224 * Note: Initvals indicate tx/rx/ latencies
225 * are the same for turbo mode */
226 txlat
= AR5K_REG_SM(txlat
, AR5K_USEC_TX_LATENCY_5210
);
227 rxlat
= AR5K_REG_SM(rxlat
, AR5K_USEC_RX_LATENCY_5210
);
229 switch (ah
->ah_bwmode
) {
230 case AR5K_BWMODE_10MHZ
:
231 txlat
= AR5K_REG_SM(txlat
* 2,
232 AR5K_USEC_TX_LATENCY_5211
);
233 rxlat
= AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX
,
234 AR5K_USEC_RX_LATENCY_5211
);
235 txf2txs
= AR5K_INIT_TXF2TXD_START_DELAY_10MHZ
;
237 case AR5K_BWMODE_5MHZ
:
238 txlat
= AR5K_REG_SM(txlat
* 4,
239 AR5K_USEC_TX_LATENCY_5211
);
240 rxlat
= AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX
,
241 AR5K_USEC_RX_LATENCY_5211
);
242 txf2txs
= AR5K_INIT_TXF2TXD_START_DELAY_5MHZ
;
244 case AR5K_BWMODE_40MHZ
:
245 txlat
= AR5K_INIT_TX_LAT_MIN
;
246 rxlat
= AR5K_REG_SM(rxlat
/ 2,
247 AR5K_USEC_RX_LATENCY_5211
);
248 txf2txs
= AR5K_INIT_TXF2TXD_START_DEFAULT
;
254 usec_reg
= (usec
| sclock
| txlat
| rxlat
);
255 ath5k_hw_reg_write(ah
, usec_reg
, AR5K_USEC
);
257 /* On 5112 set tx frame to tx data start delay */
258 if (ah
->ah_radio
== AR5K_RF5112
) {
259 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_RF_CTL2
,
260 AR5K_PHY_RF_CTL2_TXF2TXD_START
,
266 * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
267 * @ah: The &struct ath5k_hw
268 * @enable: Enable sleep clock operation (false to disable)
270 * If there is an external 32KHz crystal available, use it
271 * as ref. clock instead of 32/40MHz clock and baseband clocks
272 * to save power during sleep or restore normal 32/40MHz
275 * NOTE: When operating on 32KHz certain PHY registers (27 - 31,
276 * 123 - 127) require delay on access.
279 ath5k_hw_set_sleep_clock(struct ath5k_hw
*ah
, bool enable
)
281 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
282 u32 scal
, spending
, sclock
;
284 /* Only set 32KHz settings if we have an external
285 * 32KHz crystal present */
286 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee
->ee_misc1
) ||
287 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee
->ee_misc1
)) &&
291 AR5K_REG_WRITE_BITS(ah
, AR5K_USEC_5211
, AR5K_USEC_32
, 1);
292 /* Set up tsf increment on each cycle */
293 AR5K_REG_WRITE_BITS(ah
, AR5K_TSF_PARM
, AR5K_TSF_PARM_INC
, 61);
295 /* Set baseband sleep control registers
296 * and sleep control rate */
297 ath5k_hw_reg_write(ah
, 0x1f, AR5K_PHY_SCR
);
299 if ((ah
->ah_radio
== AR5K_RF5112
) ||
300 (ah
->ah_radio
== AR5K_RF5413
) ||
301 (ah
->ah_radio
== AR5K_RF2316
) ||
302 (ah
->ah_mac_version
== (AR5K_SREV_AR2417
>> 4)))
306 ath5k_hw_reg_write(ah
, spending
, AR5K_PHY_SPENDING
);
308 if ((ah
->ah_radio
== AR5K_RF5112
) ||
309 (ah
->ah_radio
== AR5K_RF5413
) ||
310 (ah
->ah_mac_version
== (AR5K_SREV_AR2417
>> 4))) {
311 ath5k_hw_reg_write(ah
, 0x26, AR5K_PHY_SLMT
);
312 ath5k_hw_reg_write(ah
, 0x0d, AR5K_PHY_SCAL
);
313 ath5k_hw_reg_write(ah
, 0x07, AR5K_PHY_SCLOCK
);
314 ath5k_hw_reg_write(ah
, 0x3f, AR5K_PHY_SDELAY
);
315 AR5K_REG_WRITE_BITS(ah
, AR5K_PCICFG
,
316 AR5K_PCICFG_SLEEP_CLOCK_RATE
, 0x02);
318 ath5k_hw_reg_write(ah
, 0x0a, AR5K_PHY_SLMT
);
319 ath5k_hw_reg_write(ah
, 0x0c, AR5K_PHY_SCAL
);
320 ath5k_hw_reg_write(ah
, 0x03, AR5K_PHY_SCLOCK
);
321 ath5k_hw_reg_write(ah
, 0x20, AR5K_PHY_SDELAY
);
322 AR5K_REG_WRITE_BITS(ah
, AR5K_PCICFG
,
323 AR5K_PCICFG_SLEEP_CLOCK_RATE
, 0x03);
326 /* Enable sleep clock operation */
327 AR5K_REG_ENABLE_BITS(ah
, AR5K_PCICFG
,
328 AR5K_PCICFG_SLEEP_CLOCK_EN
);
332 /* Disable sleep clock operation and
333 * restore default parameters */
334 AR5K_REG_DISABLE_BITS(ah
, AR5K_PCICFG
,
335 AR5K_PCICFG_SLEEP_CLOCK_EN
);
337 AR5K_REG_WRITE_BITS(ah
, AR5K_PCICFG
,
338 AR5K_PCICFG_SLEEP_CLOCK_RATE
, 0);
340 /* Set DAC/ADC delays */
341 ath5k_hw_reg_write(ah
, 0x1f, AR5K_PHY_SCR
);
342 ath5k_hw_reg_write(ah
, AR5K_PHY_SLMT_32MHZ
, AR5K_PHY_SLMT
);
344 if (ah
->ah_mac_version
== (AR5K_SREV_AR2417
>> 4))
345 scal
= AR5K_PHY_SCAL_32MHZ_2417
;
346 else if (ee
->ee_is_hb63
)
347 scal
= AR5K_PHY_SCAL_32MHZ_HB63
;
349 scal
= AR5K_PHY_SCAL_32MHZ
;
350 ath5k_hw_reg_write(ah
, scal
, AR5K_PHY_SCAL
);
352 ath5k_hw_reg_write(ah
, AR5K_PHY_SCLOCK_32MHZ
, AR5K_PHY_SCLOCK
);
353 ath5k_hw_reg_write(ah
, AR5K_PHY_SDELAY_32MHZ
, AR5K_PHY_SDELAY
);
355 if ((ah
->ah_radio
== AR5K_RF5112
) ||
356 (ah
->ah_radio
== AR5K_RF5413
) ||
357 (ah
->ah_radio
== AR5K_RF2316
) ||
358 (ah
->ah_mac_version
== (AR5K_SREV_AR2417
>> 4)))
362 ath5k_hw_reg_write(ah
, spending
, AR5K_PHY_SPENDING
);
364 /* Set up tsf increment on each cycle */
365 AR5K_REG_WRITE_BITS(ah
, AR5K_TSF_PARM
, AR5K_TSF_PARM_INC
, 1);
367 if ((ah
->ah_radio
== AR5K_RF5112
) ||
368 (ah
->ah_radio
== AR5K_RF5413
) ||
369 (ah
->ah_radio
== AR5K_RF2316
) ||
370 (ah
->ah_radio
== AR5K_RF2317
))
374 AR5K_REG_WRITE_BITS(ah
, AR5K_USEC_5211
, AR5K_USEC_32
, sclock
);
379 /*********************\
380 * Reset/Sleep control *
381 \*********************/
384 * ath5k_hw_nic_reset() - Reset the various chipset units
385 * @ah: The &struct ath5k_hw
386 * @val: Mask to indicate what units to reset
388 * To reset the various chipset units we need to write
389 * the mask to AR5K_RESET_CTL and poll the register until
390 * all flags are cleared.
392 * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
395 ath5k_hw_nic_reset(struct ath5k_hw
*ah
, u32 val
)
398 u32 mask
= val
? val
: ~0U;
400 /* Read-and-clear RX Descriptor Pointer*/
401 ath5k_hw_reg_read(ah
, AR5K_RXDP
);
404 * Reset the device and wait until success
406 ath5k_hw_reg_write(ah
, val
, AR5K_RESET_CTL
);
408 /* Wait at least 128 PCI clocks */
409 usleep_range(15, 20);
411 if (ah
->ah_version
== AR5K_AR5210
) {
412 val
&= AR5K_RESET_CTL_PCU
| AR5K_RESET_CTL_DMA
413 | AR5K_RESET_CTL_MAC
| AR5K_RESET_CTL_PHY
;
414 mask
&= AR5K_RESET_CTL_PCU
| AR5K_RESET_CTL_DMA
415 | AR5K_RESET_CTL_MAC
| AR5K_RESET_CTL_PHY
;
417 val
&= AR5K_RESET_CTL_PCU
| AR5K_RESET_CTL_BASEBAND
;
418 mask
&= AR5K_RESET_CTL_PCU
| AR5K_RESET_CTL_BASEBAND
;
421 ret
= ath5k_hw_register_timeout(ah
, AR5K_RESET_CTL
, mask
, val
, false);
424 * Reset configuration register (for hw byte-swap). Note that this
425 * is only set for big endian. We do the necessary magic in
428 if ((val
& AR5K_RESET_CTL_PCU
) == 0)
429 ath5k_hw_reg_write(ah
, AR5K_INIT_CFG
, AR5K_CFG
);
435 * ath5k_hw_wisoc_reset() - Reset AHB chipset
436 * @ah: The &struct ath5k_hw
437 * @flags: Mask to indicate what units to reset
439 * Same as ath5k_hw_nic_reset but for AHB based devices
441 * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
444 ath5k_hw_wisoc_reset(struct ath5k_hw
*ah
, u32 flags
)
446 u32 mask
= flags
? flags
: ~0U;
451 /* ah->ah_mac_srev is not available at this point yet */
452 if (ah
->devid
>= AR5K_SREV_AR2315_R6
) {
453 reg
= (u32 __iomem
*) AR5K_AR2315_RESET
;
454 if (mask
& AR5K_RESET_CTL_PCU
)
455 val
|= AR5K_AR2315_RESET_WMAC
;
456 if (mask
& AR5K_RESET_CTL_BASEBAND
)
457 val
|= AR5K_AR2315_RESET_BB_WARM
;
459 reg
= (u32 __iomem
*) AR5K_AR5312_RESET
;
460 if (to_platform_device(ah
->dev
)->id
== 0) {
461 if (mask
& AR5K_RESET_CTL_PCU
)
462 val
|= AR5K_AR5312_RESET_WMAC0
;
463 if (mask
& AR5K_RESET_CTL_BASEBAND
)
464 val
|= AR5K_AR5312_RESET_BB0_COLD
|
465 AR5K_AR5312_RESET_BB0_WARM
;
467 if (mask
& AR5K_RESET_CTL_PCU
)
468 val
|= AR5K_AR5312_RESET_WMAC1
;
469 if (mask
& AR5K_RESET_CTL_BASEBAND
)
470 val
|= AR5K_AR5312_RESET_BB1_COLD
|
471 AR5K_AR5312_RESET_BB1_WARM
;
475 /* Put BB/MAC into reset */
476 regval
= ioread32(reg
);
477 iowrite32(regval
| val
, reg
);
478 regval
= ioread32(reg
);
479 usleep_range(100, 150);
481 /* Bring BB/MAC out of reset */
482 iowrite32(regval
& ~val
, reg
);
483 regval
= ioread32(reg
);
486 * Reset configuration register (for hw byte-swap). Note that this
487 * is only set for big endian. We do the necessary magic in
490 if ((flags
& AR5K_RESET_CTL_PCU
) == 0)
491 ath5k_hw_reg_write(ah
, AR5K_INIT_CFG
, AR5K_CFG
);
497 * ath5k_hw_set_power_mode() - Set power mode
498 * @ah: The &struct ath5k_hw
499 * @mode: One of enum ath5k_power_mode
500 * @set_chip: Set to true to write sleep control register
501 * @sleep_duration: How much time the device is allowed to sleep
502 * when sleep logic is enabled (in 128 microsecond increments).
504 * This function is used to configure sleep policy and allowed
505 * sleep modes. For more information check out the sleep control
506 * register on reg.h and STA_ID1.
508 * Returns 0 on success, -EIO if chip didn't wake up or -EINVAL if an invalid
512 ath5k_hw_set_power_mode(struct ath5k_hw
*ah
, enum ath5k_power_mode mode
,
513 bool set_chip
, u16 sleep_duration
)
518 staid
= ath5k_hw_reg_read(ah
, AR5K_STA_ID1
);
522 staid
&= ~AR5K_STA_ID1_DEFAULT_ANTENNA
;
524 case AR5K_PM_NETWORK_SLEEP
:
526 ath5k_hw_reg_write(ah
,
527 AR5K_SLEEP_CTL_SLE_ALLOW
|
531 staid
|= AR5K_STA_ID1_PWR_SV
;
534 case AR5K_PM_FULL_SLEEP
:
536 ath5k_hw_reg_write(ah
, AR5K_SLEEP_CTL_SLE_SLP
,
539 staid
|= AR5K_STA_ID1_PWR_SV
;
544 staid
&= ~AR5K_STA_ID1_PWR_SV
;
549 data
= ath5k_hw_reg_read(ah
, AR5K_SLEEP_CTL
);
551 /* If card is down we 'll get 0xffff... so we
552 * need to clean this up before we write the register
554 if (data
& 0xffc00000)
557 /* Preserve sleep duration etc */
558 data
= data
& ~AR5K_SLEEP_CTL_SLE
;
560 ath5k_hw_reg_write(ah
, data
| AR5K_SLEEP_CTL_SLE_WAKE
,
562 usleep_range(15, 20);
564 for (i
= 200; i
> 0; i
--) {
565 /* Check if the chip did wake up */
566 if ((ath5k_hw_reg_read(ah
, AR5K_PCICFG
) &
567 AR5K_PCICFG_SPWR_DN
) == 0)
570 /* Wait a bit and retry */
571 usleep_range(50, 75);
572 ath5k_hw_reg_write(ah
, data
| AR5K_SLEEP_CTL_SLE_WAKE
,
576 /* Fail if the chip didn't wake up */
587 ath5k_hw_reg_write(ah
, staid
, AR5K_STA_ID1
);
593 * ath5k_hw_on_hold() - Put device on hold
594 * @ah: The &struct ath5k_hw
596 * Put MAC and Baseband on warm reset and keep that state
597 * (don't clean sleep control register). After this MAC
598 * and Baseband are disabled and a full reset is needed
599 * to come back. This way we save as much power as possible
600 * without putting the card on full sleep.
602 * Returns 0 on success or -EIO on error
605 ath5k_hw_on_hold(struct ath5k_hw
*ah
)
607 struct pci_dev
*pdev
= ah
->pdev
;
611 if (ath5k_get_bus_type(ah
) == ATH_AHB
)
614 /* Make sure device is awake */
615 ret
= ath5k_hw_set_power_mode(ah
, AR5K_PM_AWAKE
, true, 0);
617 ATH5K_ERR(ah
, "failed to wakeup the MAC Chip\n");
622 * Put chipset on warm reset...
624 * Note: putting PCI core on warm reset on PCI-E cards
625 * results card to hang and always return 0xffff... so
626 * we ignore that flag for PCI-E cards. On PCI cards
627 * this flag gets cleared after 64 PCI clocks.
629 bus_flags
= (pdev
&& pci_is_pcie(pdev
)) ? 0 : AR5K_RESET_CTL_PCI
;
631 if (ah
->ah_version
== AR5K_AR5210
) {
632 ret
= ath5k_hw_nic_reset(ah
, AR5K_RESET_CTL_PCU
|
633 AR5K_RESET_CTL_MAC
| AR5K_RESET_CTL_DMA
|
634 AR5K_RESET_CTL_PHY
| AR5K_RESET_CTL_PCI
);
635 usleep_range(2000, 2500);
637 ret
= ath5k_hw_nic_reset(ah
, AR5K_RESET_CTL_PCU
|
638 AR5K_RESET_CTL_BASEBAND
| bus_flags
);
642 ATH5K_ERR(ah
, "failed to put device on warm reset\n");
646 /* ...wakeup again!*/
647 ret
= ath5k_hw_set_power_mode(ah
, AR5K_PM_AWAKE
, true, 0);
649 ATH5K_ERR(ah
, "failed to put device on hold\n");
657 * ath5k_hw_nic_wakeup() - Force card out of sleep
658 * @ah: The &struct ath5k_hw
659 * @channel: The &struct ieee80211_channel
661 * Bring up MAC + PHY Chips and program PLL
662 * NOTE: Channel is NULL for the initial wakeup.
664 * Returns 0 on success, -EIO on hw failure or -EINVAL for false channel infos
667 ath5k_hw_nic_wakeup(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
)
669 struct pci_dev
*pdev
= ah
->pdev
;
670 u32 turbo
, mode
, clock
, bus_flags
;
677 if ((ath5k_get_bus_type(ah
) != ATH_AHB
) || channel
) {
678 /* Wakeup the device */
679 ret
= ath5k_hw_set_power_mode(ah
, AR5K_PM_AWAKE
, true, 0);
681 ATH5K_ERR(ah
, "failed to wakeup the MAC Chip\n");
687 * Put chipset on warm reset...
689 * Note: putting PCI core on warm reset on PCI-E cards
690 * results card to hang and always return 0xffff... so
691 * we ignore that flag for PCI-E cards. On PCI cards
692 * this flag gets cleared after 64 PCI clocks.
694 bus_flags
= (pdev
&& pci_is_pcie(pdev
)) ? 0 : AR5K_RESET_CTL_PCI
;
696 if (ah
->ah_version
== AR5K_AR5210
) {
697 ret
= ath5k_hw_nic_reset(ah
, AR5K_RESET_CTL_PCU
|
698 AR5K_RESET_CTL_MAC
| AR5K_RESET_CTL_DMA
|
699 AR5K_RESET_CTL_PHY
| AR5K_RESET_CTL_PCI
);
700 usleep_range(2000, 2500);
702 if (ath5k_get_bus_type(ah
) == ATH_AHB
)
703 ret
= ath5k_hw_wisoc_reset(ah
, AR5K_RESET_CTL_PCU
|
704 AR5K_RESET_CTL_BASEBAND
);
706 ret
= ath5k_hw_nic_reset(ah
, AR5K_RESET_CTL_PCU
|
707 AR5K_RESET_CTL_BASEBAND
| bus_flags
);
711 ATH5K_ERR(ah
, "failed to reset the MAC Chip\n");
715 /* ...wakeup again!...*/
716 ret
= ath5k_hw_set_power_mode(ah
, AR5K_PM_AWAKE
, true, 0);
718 ATH5K_ERR(ah
, "failed to resume the MAC Chip\n");
722 /* ...reset configuration register on Wisoc ...
723 * ...clear reset control register and pull device out of
724 * warm reset on others */
725 if (ath5k_get_bus_type(ah
) == ATH_AHB
)
726 ret
= ath5k_hw_wisoc_reset(ah
, 0);
728 ret
= ath5k_hw_nic_reset(ah
, 0);
731 ATH5K_ERR(ah
, "failed to warm reset the MAC Chip\n");
735 /* On initialization skip PLL programming since we don't have
736 * a channel / mode set yet */
740 if (ah
->ah_version
!= AR5K_AR5210
) {
742 * Get channel mode flags
745 if (ah
->ah_radio
>= AR5K_RF5112
) {
746 mode
= AR5K_PHY_MODE_RAD_RF5112
;
747 clock
= AR5K_PHY_PLL_RF5112
;
749 mode
= AR5K_PHY_MODE_RAD_RF5111
; /*Zero*/
750 clock
= AR5K_PHY_PLL_RF5111
; /*Zero*/
753 if (channel
->band
== IEEE80211_BAND_2GHZ
) {
754 mode
|= AR5K_PHY_MODE_FREQ_2GHZ
;
755 clock
|= AR5K_PHY_PLL_44MHZ
;
757 if (channel
->hw_value
== AR5K_MODE_11B
) {
758 mode
|= AR5K_PHY_MODE_MOD_CCK
;
760 /* XXX Dynamic OFDM/CCK is not supported by the
761 * AR5211 so we set MOD_OFDM for plain g (no
762 * CCK headers) operation. We need to test
763 * this, 5211 might support ofdm-only g after
764 * all, there are also initial register values
765 * in the code for g mode (see initvals.c).
767 if (ah
->ah_version
== AR5K_AR5211
)
768 mode
|= AR5K_PHY_MODE_MOD_OFDM
;
770 mode
|= AR5K_PHY_MODE_MOD_DYN
;
772 } else if (channel
->band
== IEEE80211_BAND_5GHZ
) {
773 mode
|= (AR5K_PHY_MODE_FREQ_5GHZ
|
774 AR5K_PHY_MODE_MOD_OFDM
);
776 /* Different PLL setting for 5413 */
777 if (ah
->ah_radio
== AR5K_RF5413
)
778 clock
= AR5K_PHY_PLL_40MHZ_5413
;
780 clock
|= AR5K_PHY_PLL_40MHZ
;
782 ATH5K_ERR(ah
, "invalid radio frequency mode\n");
786 /*XXX: Can bwmode be used with dynamic mode ?
787 * (I don't think it supports 44MHz) */
788 /* On 2425 initvals TURBO_SHORT is not present */
789 if (ah
->ah_bwmode
== AR5K_BWMODE_40MHZ
) {
790 turbo
= AR5K_PHY_TURBO_MODE
|
791 (ah
->ah_radio
== AR5K_RF2425
) ? 0 :
792 AR5K_PHY_TURBO_SHORT
;
793 } else if (ah
->ah_bwmode
!= AR5K_BWMODE_DEFAULT
) {
794 if (ah
->ah_radio
== AR5K_RF5413
) {
795 mode
|= (ah
->ah_bwmode
== AR5K_BWMODE_10MHZ
) ?
796 AR5K_PHY_MODE_HALF_RATE
:
797 AR5K_PHY_MODE_QUARTER_RATE
;
798 } else if (ah
->ah_version
== AR5K_AR5212
) {
799 clock
|= (ah
->ah_bwmode
== AR5K_BWMODE_10MHZ
) ?
800 AR5K_PHY_PLL_HALF_RATE
:
801 AR5K_PHY_PLL_QUARTER_RATE
;
805 } else { /* Reset the device */
807 /* ...enable Atheros turbo mode if requested */
808 if (ah
->ah_bwmode
== AR5K_BWMODE_40MHZ
)
809 ath5k_hw_reg_write(ah
, AR5K_PHY_TURBO_MODE
,
813 if (ah
->ah_version
!= AR5K_AR5210
) {
815 /* ...update PLL if needed */
816 if (ath5k_hw_reg_read(ah
, AR5K_PHY_PLL
) != clock
) {
817 ath5k_hw_reg_write(ah
, clock
, AR5K_PHY_PLL
);
818 usleep_range(300, 350);
821 /* ...set the PHY operating mode */
822 ath5k_hw_reg_write(ah
, mode
, AR5K_PHY_MODE
);
823 ath5k_hw_reg_write(ah
, turbo
, AR5K_PHY_TURBO
);
830 /**************************************\
831 * Post-initvals register modifications *
832 \**************************************/
835 * ath5k_hw_tweak_initval_settings() - Tweak initial settings
836 * @ah: The &struct ath5k_hw
837 * @channel: The &struct ieee80211_channel
839 * Some settings are not handled on initvals, e.g. bwmode
840 * settings, some phy settings, workarounds etc that in general
841 * don't fit anywhere else or are too small to introduce a separate
842 * function for each one. So we have this function to handle
843 * them all during reset and complete card's initialization.
846 ath5k_hw_tweak_initval_settings(struct ath5k_hw
*ah
,
847 struct ieee80211_channel
*channel
)
849 if (ah
->ah_version
== AR5K_AR5212
&&
850 ah
->ah_phy_revision
>= AR5K_SREV_PHY_5212A
) {
852 /* Setup ADC control */
853 ath5k_hw_reg_write(ah
,
855 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF
) |
857 AR5K_PHY_ADC_CTL_INBUFGAIN_ON
) |
858 AR5K_PHY_ADC_CTL_PWD_DAC_OFF
|
859 AR5K_PHY_ADC_CTL_PWD_ADC_OFF
),
864 /* Disable barker RSSI threshold */
865 AR5K_REG_DISABLE_BITS(ah
, AR5K_PHY_DAG_CCK_CTL
,
866 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR
);
868 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_DAG_CCK_CTL
,
869 AR5K_PHY_DAG_CCK_CTL_RSSI_THR
, 2);
871 /* Set the mute mask */
872 ath5k_hw_reg_write(ah
, 0x0000000f, AR5K_SEQ_MASK
);
875 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
876 if (ah
->ah_phy_revision
>= AR5K_SREV_PHY_5212B
)
877 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_BLUETOOTH
);
879 /* Enable DCU double buffering */
880 if (ah
->ah_phy_revision
> AR5K_SREV_PHY_5212B
)
881 AR5K_REG_DISABLE_BITS(ah
, AR5K_TXCFG
,
882 AR5K_TXCFG_DCU_DBL_BUF_DIS
);
885 if ((ah
->ah_radio
== AR5K_RF5413
) ||
886 (ah
->ah_radio
== AR5K_RF2317
) ||
887 (ah
->ah_mac_version
== (AR5K_SREV_AR2417
>> 4))) {
890 if (channel
->center_freq
== 2462 ||
891 channel
->center_freq
== 2467)
894 /* Only update if needed */
895 if (ath5k_hw_reg_read(ah
, AR5K_PHY_FAST_ADC
) != fast_adc
)
896 ath5k_hw_reg_write(ah
, fast_adc
,
900 /* Fix for first revision of the RF5112 RF chipset */
901 if (ah
->ah_radio
== AR5K_RF5112
&&
902 ah
->ah_radio_5ghz_revision
<
903 AR5K_SREV_RAD_5112A
) {
905 ath5k_hw_reg_write(ah
, AR5K_PHY_CCKTXCTL_WORLD
,
907 if (channel
->band
== IEEE80211_BAND_5GHZ
)
911 ath5k_hw_reg_write(ah
, data
, AR5K_PHY_FRAME_CTL
);
914 if (ah
->ah_mac_srev
< AR5K_SREV_AR5211
) {
915 /* Clear QCU/DCU clock gating register */
916 ath5k_hw_reg_write(ah
, 0, AR5K_QCUDCU_CLKGT
);
917 /* Set DAC/ADC delays */
918 ath5k_hw_reg_write(ah
, AR5K_PHY_SCAL_32MHZ_5311
,
920 /* Enable PCU FIFO corruption ECO */
921 AR5K_REG_ENABLE_BITS(ah
, AR5K_DIAG_SW_5211
,
922 AR5K_DIAG_SW_ECO_ENABLE
);
926 /* Increase PHY switch and AGC settling time
927 * on turbo mode (ath5k_hw_commit_eeprom_settings
928 * will override settling time if available) */
929 if (ah
->ah_bwmode
== AR5K_BWMODE_40MHZ
) {
931 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_SETTLING
,
932 AR5K_PHY_SETTLING_AGC
,
933 AR5K_AGC_SETTLING_TURBO
);
935 /* XXX: Initvals indicate we only increase
936 * switch time on AR5212, 5211 and 5210
937 * only change agc time (bug?) */
938 if (ah
->ah_version
== AR5K_AR5212
)
939 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_SETTLING
,
940 AR5K_PHY_SETTLING_SWITCH
,
941 AR5K_SWITCH_SETTLING_TURBO
);
943 if (ah
->ah_version
== AR5K_AR5210
) {
944 /* Set Frame Control Register */
945 ath5k_hw_reg_write(ah
,
946 (AR5K_PHY_FRAME_CTL_INI
|
947 AR5K_PHY_TURBO_MODE
|
948 AR5K_PHY_TURBO_SHORT
| 0x2020),
949 AR5K_PHY_FRAME_CTL_5210
);
951 /* On 5413 PHY force window length for half/quarter rate*/
952 } else if ((ah
->ah_mac_srev
>= AR5K_SREV_AR5424
) &&
953 (ah
->ah_mac_srev
<= AR5K_SREV_AR5414
)) {
954 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_FRAME_CTL_5211
,
955 AR5K_PHY_FRAME_CTL_WIN_LEN
,
958 } else if (ah
->ah_version
== AR5K_AR5210
) {
959 /* Set Frame Control Register for normal operation */
960 ath5k_hw_reg_write(ah
, (AR5K_PHY_FRAME_CTL_INI
| 0x1020),
961 AR5K_PHY_FRAME_CTL_5210
);
966 * ath5k_hw_commit_eeprom_settings() - Commit settings from EEPROM
967 * @ah: The &struct ath5k_hw
968 * @channel: The &struct ieee80211_channel
970 * Use settings stored on EEPROM to properly initialize the card
971 * based on various infos and per-mode calibration data.
974 ath5k_hw_commit_eeprom_settings(struct ath5k_hw
*ah
,
975 struct ieee80211_channel
*channel
)
977 struct ath5k_eeprom_info
*ee
= &ah
->ah_capabilities
.cap_eeprom
;
978 s16 cck_ofdm_pwr_delta
;
981 /* TODO: Add support for AR5210 EEPROM */
982 if (ah
->ah_version
== AR5K_AR5210
)
985 ee_mode
= ath5k_eeprom_mode_from_channel(channel
);
987 /* Adjust power delta for channel 14 */
988 if (channel
->center_freq
== 2484)
990 ((ee
->ee_cck_ofdm_power_delta
-
991 ee
->ee_scaled_cck_delta
) * 2) / 10;
994 (ee
->ee_cck_ofdm_power_delta
* 2) / 10;
996 /* Set CCK to OFDM power delta on tx power
997 * adjustment register */
998 if (ah
->ah_phy_revision
>= AR5K_SREV_PHY_5212A
) {
999 if (channel
->hw_value
== AR5K_MODE_11G
)
1000 ath5k_hw_reg_write(ah
,
1001 AR5K_REG_SM((ee
->ee_cck_ofdm_gain_delta
* -1),
1002 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA
) |
1003 AR5K_REG_SM((cck_ofdm_pwr_delta
* -1),
1004 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX
),
1005 AR5K_PHY_TX_PWR_ADJ
);
1007 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_TX_PWR_ADJ
);
1009 /* For older revs we scale power on sw during tx power
1011 ah
->ah_txpower
.txp_cck_ofdm_pwr_delta
= cck_ofdm_pwr_delta
;
1012 ah
->ah_txpower
.txp_cck_ofdm_gainf_delta
=
1013 ee
->ee_cck_ofdm_gain_delta
;
1016 /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
1018 ath5k_hw_set_antenna_switch(ah
, ee_mode
);
1020 /* Noise floor threshold */
1021 ath5k_hw_reg_write(ah
,
1022 AR5K_PHY_NF_SVAL(ee
->ee_noise_floor_thr
[ee_mode
]),
1025 if ((ah
->ah_bwmode
== AR5K_BWMODE_40MHZ
) &&
1026 (ah
->ah_ee_version
>= AR5K_EEPROM_VERSION_5_0
)) {
1027 /* Switch settling time (Turbo) */
1028 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_SETTLING
,
1029 AR5K_PHY_SETTLING_SWITCH
,
1030 ee
->ee_switch_settling_turbo
[ee_mode
]);
1032 /* Tx/Rx attenuation (Turbo) */
1033 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_GAIN
,
1034 AR5K_PHY_GAIN_TXRX_ATTEN
,
1035 ee
->ee_atn_tx_rx_turbo
[ee_mode
]);
1037 /* ADC/PGA desired size (Turbo) */
1038 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_DESIRED_SIZE
,
1039 AR5K_PHY_DESIRED_SIZE_ADC
,
1040 ee
->ee_adc_desired_size_turbo
[ee_mode
]);
1042 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_DESIRED_SIZE
,
1043 AR5K_PHY_DESIRED_SIZE_PGA
,
1044 ee
->ee_pga_desired_size_turbo
[ee_mode
]);
1046 /* Tx/Rx margin (Turbo) */
1047 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_GAIN_2GHZ
,
1048 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX
,
1049 ee
->ee_margin_tx_rx_turbo
[ee_mode
]);
1052 /* Switch settling time */
1053 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_SETTLING
,
1054 AR5K_PHY_SETTLING_SWITCH
,
1055 ee
->ee_switch_settling
[ee_mode
]);
1057 /* Tx/Rx attenuation */
1058 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_GAIN
,
1059 AR5K_PHY_GAIN_TXRX_ATTEN
,
1060 ee
->ee_atn_tx_rx
[ee_mode
]);
1062 /* ADC/PGA desired size */
1063 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_DESIRED_SIZE
,
1064 AR5K_PHY_DESIRED_SIZE_ADC
,
1065 ee
->ee_adc_desired_size
[ee_mode
]);
1067 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_DESIRED_SIZE
,
1068 AR5K_PHY_DESIRED_SIZE_PGA
,
1069 ee
->ee_pga_desired_size
[ee_mode
]);
1072 if (ah
->ah_ee_version
>= AR5K_EEPROM_VERSION_4_1
)
1073 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_GAIN_2GHZ
,
1074 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX
,
1075 ee
->ee_margin_tx_rx
[ee_mode
]);
1079 ath5k_hw_reg_write(ah
,
1080 (ee
->ee_tx_end2xpa_disable
[ee_mode
] << 24) |
1081 (ee
->ee_tx_end2xpa_disable
[ee_mode
] << 16) |
1082 (ee
->ee_tx_frm2xpa_enable
[ee_mode
] << 8) |
1083 (ee
->ee_tx_frm2xpa_enable
[ee_mode
]), AR5K_PHY_RF_CTL4
);
1086 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_RF_CTL3
,
1087 AR5K_PHY_RF_CTL3_TXE2XLNA_ON
,
1088 ee
->ee_tx_end2xlna_enable
[ee_mode
]);
1090 /* Thresh64 (ANI) */
1091 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_NF
,
1092 AR5K_PHY_NF_THRESH62
,
1093 ee
->ee_thr_62
[ee_mode
]);
1095 /* False detect backoff for channels
1096 * that have spur noise. Write the new
1097 * cyclic power RSSI threshold. */
1098 if (ath5k_hw_chan_has_spur_noise(ah
, channel
))
1099 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_OFDM_SELFCORR
,
1100 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1
,
1101 AR5K_INIT_CYCRSSI_THR1
+
1102 ee
->ee_false_detect
[ee_mode
]);
1104 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_OFDM_SELFCORR
,
1105 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1
,
1106 AR5K_INIT_CYCRSSI_THR1
);
1108 /* I/Q correction (set enable bit last to match HAL sources) */
1109 /* TODO: Per channel i/q infos ? */
1110 if (ah
->ah_ee_version
>= AR5K_EEPROM_VERSION_4_0
) {
1111 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_Q_I_COFF
,
1112 ee
->ee_i_cal
[ee_mode
]);
1113 AR5K_REG_WRITE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_Q_Q_COFF
,
1114 ee
->ee_q_cal
[ee_mode
]);
1115 AR5K_REG_ENABLE_BITS(ah
, AR5K_PHY_IQ
, AR5K_PHY_IQ_CORR_ENABLE
);
1118 /* Heavy clipping -disable for now */
1119 if (ah
->ah_ee_version
>= AR5K_EEPROM_VERSION_5_1
)
1120 ath5k_hw_reg_write(ah
, 0, AR5K_PHY_HEAVY_CLIP_ENABLE
);
1124 /*********************\
1125 * Main reset function *
1126 \*********************/
1129 * ath5k_hw_reset() - The main reset function
1130 * @ah: The &struct ath5k_hw
1131 * @op_mode: One of enum nl80211_iftype
1132 * @channel: The &struct ieee80211_channel
1133 * @fast: Enable fast channel switching
1134 * @skip_pcu: Skip pcu initialization
1136 * This is the function we call each time we want to (re)initialize the
1137 * card and pass new settings to hw. We also call it when hw runs into
1138 * trouble to make it come back to a working state.
1140 * Returns 0 on success, -EINVAL on false op_mode or channel infos, or -EIO
1144 ath5k_hw_reset(struct ath5k_hw
*ah
, enum nl80211_iftype op_mode
,
1145 struct ieee80211_channel
*channel
, bool fast
, bool skip_pcu
)
1147 u32 s_seq
[10], s_led
[3], tsf_up
, tsf_lo
;
1156 * Sanity check for fast flag
1157 * Fast channel change only available
1160 if (fast
&& (ah
->ah_radio
!= AR5K_RF2413
) &&
1161 (ah
->ah_radio
!= AR5K_RF5413
))
1164 /* Disable sleep clock operation
1165 * to avoid register access delay on certain
1167 if (ah
->ah_version
== AR5K_AR5212
)
1168 ath5k_hw_set_sleep_clock(ah
, false);
1173 ath5k_hw_stop_rx_pcu(ah
);
1178 * Note: If DMA didn't stop continue
1179 * since only a reset will fix it.
1181 ret
= ath5k_hw_dma_stop(ah
);
1183 /* RF Bus grant won't work if we have pending
1186 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
1187 "DMA didn't stop, falling back to normal reset\n");
1189 /* Non fatal, just continue with
1194 mode
= channel
->hw_value
;
1199 if (ah
->ah_version
<= AR5K_AR5211
) {
1201 "G mode not available on 5210/5211");
1206 if (ah
->ah_version
< AR5K_AR5211
) {
1208 "B mode not available on 5210");
1214 "invalid channel: %d\n", channel
->center_freq
);
1219 * If driver requested fast channel change and DMA has stopped
1220 * go on. If it fails continue with a normal reset.
1223 ret
= ath5k_hw_phy_init(ah
, channel
, mode
, true);
1225 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
1226 "fast chan change failed, falling back to normal reset\n");
1227 /* Non fatal, can happen eg.
1231 ATH5K_DBG(ah
, ATH5K_DEBUG_RESET
,
1232 "fast chan change successful\n");
1238 * Save some registers before a reset
1240 if (ah
->ah_version
!= AR5K_AR5210
) {
1242 * Save frame sequence count
1243 * For revs. after Oahu, only save
1244 * seq num for DCU 0 (Global seq num)
1246 if (ah
->ah_mac_srev
< AR5K_SREV_AR5211
) {
1248 for (i
= 0; i
< 10; i
++)
1249 s_seq
[i
] = ath5k_hw_reg_read(ah
,
1250 AR5K_QUEUE_DCU_SEQNUM(i
));
1253 s_seq
[0] = ath5k_hw_reg_read(ah
,
1254 AR5K_QUEUE_DCU_SEQNUM(0));
1257 /* TSF accelerates on AR5211 during reset
1258 * As a workaround save it here and restore
1259 * it later so that it's back in time after
1260 * reset. This way it'll get re-synced on the
1261 * next beacon without breaking ad-hoc.
1263 * On AR5212 TSF is almost preserved across a
1264 * reset so it stays back in time anyway and
1265 * we don't have to save/restore it.
1267 * XXX: Since this breaks power saving we have
1268 * to disable power saving until we receive the
1269 * next beacon, so we can resync beacon timers */
1270 if (ah
->ah_version
== AR5K_AR5211
) {
1271 tsf_up
= ath5k_hw_reg_read(ah
, AR5K_TSF_U32
);
1272 tsf_lo
= ath5k_hw_reg_read(ah
, AR5K_TSF_L32
);
1278 s_led
[0] = ath5k_hw_reg_read(ah
, AR5K_PCICFG
) &
1279 AR5K_PCICFG_LEDSTATE
;
1280 s_led
[1] = ath5k_hw_reg_read(ah
, AR5K_GPIOCR
);
1281 s_led
[2] = ath5k_hw_reg_read(ah
, AR5K_GPIODO
);
1285 * Since we are going to write rf buffer
1286 * check if we have any pending gain_F
1287 * optimization settings
1289 if (ah
->ah_version
== AR5K_AR5212
&&
1290 (ah
->ah_radio
<= AR5K_RF5112
)) {
1291 if (!fast
&& ah
->ah_rf_banks
!= NULL
)
1292 ath5k_hw_gainf_calibrate(ah
);
1295 /* Wakeup the device */
1296 ret
= ath5k_hw_nic_wakeup(ah
, channel
);
1300 /* PHY access enable */
1301 if (ah
->ah_mac_srev
>= AR5K_SREV_AR5211
)
1302 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_5GHZ
, AR5K_PHY(0));
1304 ath5k_hw_reg_write(ah
, AR5K_PHY_SHIFT_5GHZ
| 0x40,
1307 /* Write initial settings */
1308 ret
= ath5k_hw_write_initvals(ah
, mode
, skip_pcu
);
1312 /* Initialize core clock settings */
1313 ath5k_hw_init_core_clock(ah
);
1316 * Tweak initval settings for revised
1317 * chipsets and add some more config
1320 ath5k_hw_tweak_initval_settings(ah
, channel
);
1322 /* Commit values from EEPROM */
1323 ath5k_hw_commit_eeprom_settings(ah
, channel
);
1327 * Restore saved values
1331 if (ah
->ah_version
!= AR5K_AR5210
) {
1332 if (ah
->ah_mac_srev
< AR5K_SREV_AR5211
) {
1333 for (i
= 0; i
< 10; i
++)
1334 ath5k_hw_reg_write(ah
, s_seq
[i
],
1335 AR5K_QUEUE_DCU_SEQNUM(i
));
1337 ath5k_hw_reg_write(ah
, s_seq
[0],
1338 AR5K_QUEUE_DCU_SEQNUM(0));
1341 if (ah
->ah_version
== AR5K_AR5211
) {
1342 ath5k_hw_reg_write(ah
, tsf_up
, AR5K_TSF_U32
);
1343 ath5k_hw_reg_write(ah
, tsf_lo
, AR5K_TSF_L32
);
1348 AR5K_REG_ENABLE_BITS(ah
, AR5K_PCICFG
, s_led
[0]);
1351 ath5k_hw_reg_write(ah
, s_led
[1], AR5K_GPIOCR
);
1352 ath5k_hw_reg_write(ah
, s_led
[2], AR5K_GPIODO
);
1357 ath5k_hw_pcu_init(ah
, op_mode
);
1362 ret
= ath5k_hw_phy_init(ah
, channel
, mode
, false);
1365 "failed to initialize PHY (%i) !\n", ret
);
1370 * Configure QCUs/DCUs
1372 ret
= ath5k_hw_init_queues(ah
);
1378 * Initialize DMA/Interrupts
1380 ath5k_hw_dma_init(ah
);
1384 * Enable 32KHz clock function for AR5212+ chips
1385 * Set clocks to 32KHz operation and use an
1386 * external 32KHz crystal when sleeping if one
1388 * Disabled by default because it is also disabled in
1389 * other drivers and it is known to cause stability
1390 * issues on some devices
1392 if (ah
->ah_use_32khz_clock
&& ah
->ah_version
== AR5K_AR5212
&&
1393 op_mode
!= NL80211_IFTYPE_AP
)
1394 ath5k_hw_set_sleep_clock(ah
, true);
1397 * Disable beacons and reset the TSF
1399 AR5K_REG_DISABLE_BITS(ah
, AR5K_BEACON
, AR5K_BEACON_ENABLE
);
1400 ath5k_hw_reset_tsf(ah
);