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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_calib.c
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include "ar9003_phy.h"
20 #include "ar9003_rtt.h"
21 #include "ar9003_mci.h"
22
23 #define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
24 #define MAX_MAG_DELTA 11
25 #define MAX_PHS_DELTA 10
26 #define MAXIQCAL 3
27
28 struct coeff {
29 int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
30 int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
31 int iqc_coeff[2];
32 };
33
34 enum ar9003_cal_types {
35 IQ_MISMATCH_CAL = BIT(0),
36 TEMP_COMP_CAL = BIT(1),
37 };
38
39 static void ar9003_hw_setup_calibration(struct ath_hw *ah,
40 struct ath9k_cal_list *currCal)
41 {
42 struct ath_common *common = ath9k_hw_common(ah);
43
44 /* Select calibration to run */
45 switch (currCal->calData->calType) {
46 case IQ_MISMATCH_CAL:
47 /*
48 * Start calibration with
49 * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
50 */
51 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
52 AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
53 currCal->calData->calCountMax);
54 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
55
56 ath_dbg(common, CALIBRATE,
57 "starting IQ Mismatch Calibration\n");
58
59 /* Kick-off cal */
60 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
61 break;
62 case TEMP_COMP_CAL:
63 ath_dbg(common, CALIBRATE,
64 "starting Temperature Compensation Calibration\n");
65 REG_SET_BIT(ah, AR_CH0_THERM, AR_CH0_THERM_LOCAL);
66 REG_SET_BIT(ah, AR_CH0_THERM, AR_CH0_THERM_START);
67 break;
68 default:
69 ath_err(common, "Invalid calibration type\n");
70 break;
71 }
72 }
73
74 /*
75 * Generic calibration routine.
76 * Recalibrate the lower PHY chips to account for temperature/environment
77 * changes.
78 */
79 static bool ar9003_hw_per_calibration(struct ath_hw *ah,
80 struct ath9k_channel *ichan,
81 u8 rxchainmask,
82 struct ath9k_cal_list *currCal)
83 {
84 struct ath9k_hw_cal_data *caldata = ah->caldata;
85 const struct ath9k_percal_data *cur_caldata = currCal->calData;
86
87 /* Calibration in progress. */
88 if (currCal->calState == CAL_RUNNING) {
89 /* Check to see if it has finished. */
90 if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)
91 return false;
92
93 /*
94 * Accumulate cal measures for active chains
95 */
96 if (cur_caldata->calCollect)
97 cur_caldata->calCollect(ah);
98 ah->cal_samples++;
99
100 if (ah->cal_samples >= cur_caldata->calNumSamples) {
101 unsigned int i, numChains = 0;
102 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
103 if (rxchainmask & (1 << i))
104 numChains++;
105 }
106
107 /*
108 * Process accumulated data
109 */
110 if (cur_caldata->calPostProc)
111 cur_caldata->calPostProc(ah, numChains);
112
113 /* Calibration has finished. */
114 caldata->CalValid |= cur_caldata->calType;
115 currCal->calState = CAL_DONE;
116 return true;
117 } else {
118 /*
119 * Set-up collection of another sub-sample until we
120 * get desired number
121 */
122 ar9003_hw_setup_calibration(ah, currCal);
123 }
124 } else if (!(caldata->CalValid & cur_caldata->calType)) {
125 /* If current cal is marked invalid in channel, kick it off */
126 ath9k_hw_reset_calibration(ah, currCal);
127 }
128
129 return false;
130 }
131
132 static int ar9003_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
133 u8 rxchainmask, bool longcal)
134 {
135 bool iscaldone = true;
136 struct ath9k_cal_list *currCal = ah->cal_list_curr;
137 int ret;
138
139 /*
140 * For given calibration:
141 * 1. Call generic cal routine
142 * 2. When this cal is done (isCalDone) if we have more cals waiting
143 * (eg after reset), mask this to upper layers by not propagating
144 * isCalDone if it is set to TRUE.
145 * Instead, change isCalDone to FALSE and setup the waiting cal(s)
146 * to be run.
147 */
148 if (currCal &&
149 (currCal->calState == CAL_RUNNING ||
150 currCal->calState == CAL_WAITING)) {
151 iscaldone = ar9003_hw_per_calibration(ah, chan,
152 rxchainmask, currCal);
153 if (iscaldone) {
154 ah->cal_list_curr = currCal = currCal->calNext;
155
156 if (currCal->calState == CAL_WAITING) {
157 iscaldone = false;
158 ath9k_hw_reset_calibration(ah, currCal);
159 }
160 }
161 }
162
163 /*
164 * Do NF cal only at longer intervals. Get the value from
165 * the previous NF cal and update history buffer.
166 */
167 if (longcal && ath9k_hw_getnf(ah, chan)) {
168 /*
169 * Load the NF from history buffer of the current channel.
170 * NF is slow time-variant, so it is OK to use a historical
171 * value.
172 */
173 ret = ath9k_hw_loadnf(ah, ah->curchan);
174 if (ret < 0)
175 return ret;
176
177 /* start NF calibration, without updating BB NF register */
178 ath9k_hw_start_nfcal(ah, false);
179 }
180
181 return iscaldone;
182 }
183
184 static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
185 {
186 int i;
187
188 /* Accumulate IQ cal measures for active chains */
189 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
190 if (ah->txchainmask & BIT(i)) {
191 ah->totalPowerMeasI[i] +=
192 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
193 ah->totalPowerMeasQ[i] +=
194 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
195 ah->totalIqCorrMeas[i] +=
196 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
197 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
198 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
199 ah->cal_samples, i, ah->totalPowerMeasI[i],
200 ah->totalPowerMeasQ[i],
201 ah->totalIqCorrMeas[i]);
202 }
203 }
204 }
205
206 static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
207 {
208 struct ath_common *common = ath9k_hw_common(ah);
209 u32 powerMeasQ, powerMeasI, iqCorrMeas;
210 u32 qCoffDenom, iCoffDenom;
211 int32_t qCoff, iCoff;
212 int iqCorrNeg, i;
213 static const u_int32_t offset_array[3] = {
214 AR_PHY_RX_IQCAL_CORR_B0,
215 AR_PHY_RX_IQCAL_CORR_B1,
216 AR_PHY_RX_IQCAL_CORR_B2,
217 };
218
219 for (i = 0; i < numChains; i++) {
220 powerMeasI = ah->totalPowerMeasI[i];
221 powerMeasQ = ah->totalPowerMeasQ[i];
222 iqCorrMeas = ah->totalIqCorrMeas[i];
223
224 ath_dbg(common, CALIBRATE,
225 "Starting IQ Cal and Correction for Chain %d\n", i);
226
227 ath_dbg(common, CALIBRATE,
228 "Original: Chn %d iq_corr_meas = 0x%08x\n",
229 i, ah->totalIqCorrMeas[i]);
230
231 iqCorrNeg = 0;
232
233 if (iqCorrMeas > 0x80000000) {
234 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
235 iqCorrNeg = 1;
236 }
237
238 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n",
239 i, powerMeasI);
240 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n",
241 i, powerMeasQ);
242 ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg);
243
244 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
245 qCoffDenom = powerMeasQ / 64;
246
247 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
248 iCoff = iqCorrMeas / iCoffDenom;
249 qCoff = powerMeasI / qCoffDenom - 64;
250 ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n",
251 i, iCoff);
252 ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n",
253 i, qCoff);
254
255 /* Force bounds on iCoff */
256 if (iCoff >= 63)
257 iCoff = 63;
258 else if (iCoff <= -63)
259 iCoff = -63;
260
261 /* Negate iCoff if iqCorrNeg == 0 */
262 if (iqCorrNeg == 0x0)
263 iCoff = -iCoff;
264
265 /* Force bounds on qCoff */
266 if (qCoff >= 63)
267 qCoff = 63;
268 else if (qCoff <= -63)
269 qCoff = -63;
270
271 iCoff = iCoff & 0x7f;
272 qCoff = qCoff & 0x7f;
273
274 ath_dbg(common, CALIBRATE,
275 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
276 i, iCoff, qCoff);
277 ath_dbg(common, CALIBRATE,
278 "Register offset (0x%04x) before update = 0x%x\n",
279 offset_array[i],
280 REG_READ(ah, offset_array[i]));
281
282 if (AR_SREV_9565(ah) &&
283 (iCoff == 63 || qCoff == 63 ||
284 iCoff == -63 || qCoff == -63))
285 return;
286
287 REG_RMW_FIELD(ah, offset_array[i],
288 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
289 iCoff);
290 REG_RMW_FIELD(ah, offset_array[i],
291 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
292 qCoff);
293 ath_dbg(common, CALIBRATE,
294 "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
295 offset_array[i],
296 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
297 REG_READ(ah, offset_array[i]));
298 ath_dbg(common, CALIBRATE,
299 "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
300 offset_array[i],
301 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
302 REG_READ(ah, offset_array[i]));
303
304 ath_dbg(common, CALIBRATE,
305 "IQ Cal and Correction done for Chain %d\n", i);
306 }
307 }
308
309 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
310 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
311 ath_dbg(common, CALIBRATE,
312 "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
313 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
314 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
315 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
316 }
317
318 static const struct ath9k_percal_data iq_cal_single_sample = {
319 IQ_MISMATCH_CAL,
320 MIN_CAL_SAMPLES,
321 PER_MAX_LOG_COUNT,
322 ar9003_hw_iqcal_collect,
323 ar9003_hw_iqcalibrate
324 };
325
326 static const struct ath9k_percal_data temp_cal_single_sample = {
327 TEMP_COMP_CAL,
328 MIN_CAL_SAMPLES,
329 PER_MAX_LOG_COUNT,
330 };
331
332 static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
333 {
334 ah->iq_caldata.calData = &iq_cal_single_sample;
335 ah->temp_caldata.calData = &temp_cal_single_sample;
336
337 if (AR_SREV_9300_20_OR_LATER(ah)) {
338 ah->enabled_cals |= TX_IQ_CAL;
339 if (AR_SREV_9485_OR_LATER(ah) && !AR_SREV_9340(ah))
340 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
341 }
342
343 ah->supp_cals = IQ_MISMATCH_CAL | TEMP_COMP_CAL;
344 }
345
346 #define OFF_UPPER_LT 24
347 #define OFF_LOWER_LT 7
348
349 static bool ar9003_hw_dynamic_osdac_selection(struct ath_hw *ah,
350 bool txiqcal_done)
351 {
352 struct ath_common *common = ath9k_hw_common(ah);
353 int ch0_done, osdac_ch0, dc_off_ch0_i1, dc_off_ch0_q1, dc_off_ch0_i2,
354 dc_off_ch0_q2, dc_off_ch0_i3, dc_off_ch0_q3;
355 int ch1_done, osdac_ch1, dc_off_ch1_i1, dc_off_ch1_q1, dc_off_ch1_i2,
356 dc_off_ch1_q2, dc_off_ch1_i3, dc_off_ch1_q3;
357 int ch2_done, osdac_ch2, dc_off_ch2_i1, dc_off_ch2_q1, dc_off_ch2_i2,
358 dc_off_ch2_q2, dc_off_ch2_i3, dc_off_ch2_q3;
359 bool status;
360 u32 temp, val;
361
362 /*
363 * Clear offset and IQ calibration, run AGC cal.
364 */
365 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
366 AR_PHY_AGC_CONTROL_OFFSET_CAL);
367 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
368 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
369 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
370 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
371
372 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
373 AR_PHY_AGC_CONTROL_CAL,
374 0, AH_WAIT_TIMEOUT);
375 if (!status) {
376 ath_dbg(common, CALIBRATE,
377 "AGC cal without offset cal failed to complete in 1ms");
378 return false;
379 }
380
381 /*
382 * Allow only offset calibration and disable the others
383 * (Carrier Leak calibration, TX Filter calibration and
384 * Peak Detector offset calibration).
385 */
386 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
387 AR_PHY_AGC_CONTROL_OFFSET_CAL);
388 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
389 AR_PHY_CL_CAL_ENABLE);
390 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
391 AR_PHY_AGC_CONTROL_FLTR_CAL);
392 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
393 AR_PHY_AGC_CONTROL_PKDET_CAL);
394
395 ch0_done = 0;
396 ch1_done = 0;
397 ch2_done = 0;
398
399 while ((ch0_done == 0) || (ch1_done == 0) || (ch2_done == 0)) {
400 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3;
401 osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3;
402 osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3;
403
404 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
405
406 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
407 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
408
409 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
410 AR_PHY_AGC_CONTROL_CAL,
411 0, AH_WAIT_TIMEOUT);
412 if (!status) {
413 ath_dbg(common, CALIBRATE,
414 "DC offset cal failed to complete in 1ms");
415 return false;
416 }
417
418 REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
419
420 /*
421 * High gain.
422 */
423 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
424 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8)));
425 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
426 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8)));
427 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
428 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8)));
429
430 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
431 dc_off_ch0_i1 = (temp >> 26) & 0x1f;
432 dc_off_ch0_q1 = (temp >> 21) & 0x1f;
433
434 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
435 dc_off_ch1_i1 = (temp >> 26) & 0x1f;
436 dc_off_ch1_q1 = (temp >> 21) & 0x1f;
437
438 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
439 dc_off_ch2_i1 = (temp >> 26) & 0x1f;
440 dc_off_ch2_q1 = (temp >> 21) & 0x1f;
441
442 /*
443 * Low gain.
444 */
445 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
446 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8)));
447 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
448 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8)));
449 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
450 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8)));
451
452 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
453 dc_off_ch0_i2 = (temp >> 26) & 0x1f;
454 dc_off_ch0_q2 = (temp >> 21) & 0x1f;
455
456 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
457 dc_off_ch1_i2 = (temp >> 26) & 0x1f;
458 dc_off_ch1_q2 = (temp >> 21) & 0x1f;
459
460 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
461 dc_off_ch2_i2 = (temp >> 26) & 0x1f;
462 dc_off_ch2_q2 = (temp >> 21) & 0x1f;
463
464 /*
465 * Loopback.
466 */
467 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
468 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8)));
469 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
470 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8)));
471 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
472 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8)));
473
474 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
475 dc_off_ch0_i3 = (temp >> 26) & 0x1f;
476 dc_off_ch0_q3 = (temp >> 21) & 0x1f;
477
478 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
479 dc_off_ch1_i3 = (temp >> 26) & 0x1f;
480 dc_off_ch1_q3 = (temp >> 21) & 0x1f;
481
482 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
483 dc_off_ch2_i3 = (temp >> 26) & 0x1f;
484 dc_off_ch2_q3 = (temp >> 21) & 0x1f;
485
486 if ((dc_off_ch0_i1 > OFF_UPPER_LT) || (dc_off_ch0_i1 < OFF_LOWER_LT) ||
487 (dc_off_ch0_i2 > OFF_UPPER_LT) || (dc_off_ch0_i2 < OFF_LOWER_LT) ||
488 (dc_off_ch0_i3 > OFF_UPPER_LT) || (dc_off_ch0_i3 < OFF_LOWER_LT) ||
489 (dc_off_ch0_q1 > OFF_UPPER_LT) || (dc_off_ch0_q1 < OFF_LOWER_LT) ||
490 (dc_off_ch0_q2 > OFF_UPPER_LT) || (dc_off_ch0_q2 < OFF_LOWER_LT) ||
491 (dc_off_ch0_q3 > OFF_UPPER_LT) || (dc_off_ch0_q3 < OFF_LOWER_LT)) {
492 if (osdac_ch0 == 3) {
493 ch0_done = 1;
494 } else {
495 osdac_ch0++;
496
497 val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff;
498 val |= (osdac_ch0 << 30);
499 REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val);
500
501 ch0_done = 0;
502 }
503 } else {
504 ch0_done = 1;
505 }
506
507 if ((dc_off_ch1_i1 > OFF_UPPER_LT) || (dc_off_ch1_i1 < OFF_LOWER_LT) ||
508 (dc_off_ch1_i2 > OFF_UPPER_LT) || (dc_off_ch1_i2 < OFF_LOWER_LT) ||
509 (dc_off_ch1_i3 > OFF_UPPER_LT) || (dc_off_ch1_i3 < OFF_LOWER_LT) ||
510 (dc_off_ch1_q1 > OFF_UPPER_LT) || (dc_off_ch1_q1 < OFF_LOWER_LT) ||
511 (dc_off_ch1_q2 > OFF_UPPER_LT) || (dc_off_ch1_q2 < OFF_LOWER_LT) ||
512 (dc_off_ch1_q3 > OFF_UPPER_LT) || (dc_off_ch1_q3 < OFF_LOWER_LT)) {
513 if (osdac_ch1 == 3) {
514 ch1_done = 1;
515 } else {
516 osdac_ch1++;
517
518 val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff;
519 val |= (osdac_ch1 << 30);
520 REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val);
521
522 ch1_done = 0;
523 }
524 } else {
525 ch1_done = 1;
526 }
527
528 if ((dc_off_ch2_i1 > OFF_UPPER_LT) || (dc_off_ch2_i1 < OFF_LOWER_LT) ||
529 (dc_off_ch2_i2 > OFF_UPPER_LT) || (dc_off_ch2_i2 < OFF_LOWER_LT) ||
530 (dc_off_ch2_i3 > OFF_UPPER_LT) || (dc_off_ch2_i3 < OFF_LOWER_LT) ||
531 (dc_off_ch2_q1 > OFF_UPPER_LT) || (dc_off_ch2_q1 < OFF_LOWER_LT) ||
532 (dc_off_ch2_q2 > OFF_UPPER_LT) || (dc_off_ch2_q2 < OFF_LOWER_LT) ||
533 (dc_off_ch2_q3 > OFF_UPPER_LT) || (dc_off_ch2_q3 < OFF_LOWER_LT)) {
534 if (osdac_ch2 == 3) {
535 ch2_done = 1;
536 } else {
537 osdac_ch2++;
538
539 val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff;
540 val |= (osdac_ch2 << 30);
541 REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val);
542
543 ch2_done = 0;
544 }
545 } else {
546 ch2_done = 1;
547 }
548 }
549
550 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
551 AR_PHY_AGC_CONTROL_OFFSET_CAL);
552 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
553
554 /*
555 * We don't need to check txiqcal_done here since it is always
556 * set for AR9550.
557 */
558 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
559 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
560
561 return true;
562 }
563
564 /*
565 * solve 4x4 linear equation used in loopback iq cal.
566 */
567 static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
568 s32 sin_2phi_1,
569 s32 cos_2phi_1,
570 s32 sin_2phi_2,
571 s32 cos_2phi_2,
572 s32 mag_a0_d0,
573 s32 phs_a0_d0,
574 s32 mag_a1_d0,
575 s32 phs_a1_d0,
576 s32 solved_eq[])
577 {
578 s32 f1 = cos_2phi_1 - cos_2phi_2,
579 f3 = sin_2phi_1 - sin_2phi_2,
580 f2;
581 s32 mag_tx, phs_tx, mag_rx, phs_rx;
582 const s32 result_shift = 1 << 15;
583 struct ath_common *common = ath9k_hw_common(ah);
584
585 f2 = ((f1 >> 3) * (f1 >> 3) + (f3 >> 3) * (f3 >> 3)) >> 9;
586
587 if (!f2) {
588 ath_dbg(common, CALIBRATE, "Divide by 0\n");
589 return false;
590 }
591
592 /* mag mismatch, tx */
593 mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
594 /* phs mismatch, tx */
595 phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
596
597 mag_tx = (mag_tx / f2);
598 phs_tx = (phs_tx / f2);
599
600 /* mag mismatch, rx */
601 mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
602 result_shift;
603 /* phs mismatch, rx */
604 phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
605 result_shift;
606
607 solved_eq[0] = mag_tx;
608 solved_eq[1] = phs_tx;
609 solved_eq[2] = mag_rx;
610 solved_eq[3] = phs_rx;
611
612 return true;
613 }
614
615 static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
616 {
617 s32 abs_i = abs(in_re),
618 abs_q = abs(in_im),
619 max_abs, min_abs;
620
621 if (abs_i > abs_q) {
622 max_abs = abs_i;
623 min_abs = abs_q;
624 } else {
625 max_abs = abs_q;
626 min_abs = abs_i;
627 }
628
629 return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
630 }
631
632 #define DELPT 32
633
634 static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
635 s32 chain_idx,
636 const s32 iq_res[],
637 s32 iqc_coeff[])
638 {
639 s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
640 i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
641 i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
642 i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
643 s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
644 phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
645 sin_2phi_1, cos_2phi_1,
646 sin_2phi_2, cos_2phi_2;
647 s32 mag_tx, phs_tx, mag_rx, phs_rx;
648 s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
649 q_q_coff, q_i_coff;
650 const s32 res_scale = 1 << 15;
651 const s32 delpt_shift = 1 << 8;
652 s32 mag1, mag2;
653 struct ath_common *common = ath9k_hw_common(ah);
654
655 i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
656 i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
657 iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
658
659 if (i2_m_q2_a0_d0 > 0x800)
660 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
661
662 if (i2_p_q2_a0_d0 > 0x800)
663 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
664
665 if (iq_corr_a0_d0 > 0x800)
666 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
667
668 i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
669 i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
670 iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
671
672 if (i2_m_q2_a0_d1 > 0x800)
673 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
674
675 if (iq_corr_a0_d1 > 0x800)
676 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
677
678 i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
679 i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
680 iq_corr_a1_d0 = iq_res[4] & 0xfff;
681
682 if (i2_m_q2_a1_d0 > 0x800)
683 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
684
685 if (i2_p_q2_a1_d0 > 0x800)
686 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
687
688 if (iq_corr_a1_d0 > 0x800)
689 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
690
691 i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
692 i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
693 iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
694
695 if (i2_m_q2_a1_d1 > 0x800)
696 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
697
698 if (i2_p_q2_a1_d1 > 0x800)
699 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
700
701 if (iq_corr_a1_d1 > 0x800)
702 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
703
704 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
705 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
706 ath_dbg(common, CALIBRATE,
707 "Divide by 0:\n"
708 "a0_d0=%d\n"
709 "a0_d1=%d\n"
710 "a2_d0=%d\n"
711 "a1_d1=%d\n",
712 i2_p_q2_a0_d0, i2_p_q2_a0_d1,
713 i2_p_q2_a1_d0, i2_p_q2_a1_d1);
714 return false;
715 }
716
717 if ((i2_p_q2_a0_d0 < 1024) || (i2_p_q2_a0_d0 > 2047) ||
718 (i2_p_q2_a1_d0 < 0) || (i2_p_q2_a1_d1 < 0) ||
719 (i2_p_q2_a0_d0 <= i2_m_q2_a0_d0) ||
720 (i2_p_q2_a0_d0 <= iq_corr_a0_d0) ||
721 (i2_p_q2_a0_d1 <= i2_m_q2_a0_d1) ||
722 (i2_p_q2_a0_d1 <= iq_corr_a0_d1) ||
723 (i2_p_q2_a1_d0 <= i2_m_q2_a1_d0) ||
724 (i2_p_q2_a1_d0 <= iq_corr_a1_d0) ||
725 (i2_p_q2_a1_d1 <= i2_m_q2_a1_d1) ||
726 (i2_p_q2_a1_d1 <= iq_corr_a1_d1)) {
727 return false;
728 }
729
730 mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
731 phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
732
733 mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
734 phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
735
736 mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
737 phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
738
739 mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
740 phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
741
742 /* w/o analog phase shift */
743 sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
744 /* w/o analog phase shift */
745 cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
746 /* w/ analog phase shift */
747 sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
748 /* w/ analog phase shift */
749 cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
750
751 /*
752 * force sin^2 + cos^2 = 1;
753 * find magnitude by approximation
754 */
755 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
756 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
757
758 if ((mag1 == 0) || (mag2 == 0)) {
759 ath_dbg(common, CALIBRATE, "Divide by 0: mag1=%d, mag2=%d\n",
760 mag1, mag2);
761 return false;
762 }
763
764 /* normalization sin and cos by mag */
765 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
766 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
767 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
768 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
769
770 /* calculate IQ mismatch */
771 if (!ar9003_hw_solve_iq_cal(ah,
772 sin_2phi_1, cos_2phi_1,
773 sin_2phi_2, cos_2phi_2,
774 mag_a0_d0, phs_a0_d0,
775 mag_a1_d0,
776 phs_a1_d0, solved_eq)) {
777 ath_dbg(common, CALIBRATE,
778 "Call to ar9003_hw_solve_iq_cal() failed\n");
779 return false;
780 }
781
782 mag_tx = solved_eq[0];
783 phs_tx = solved_eq[1];
784 mag_rx = solved_eq[2];
785 phs_rx = solved_eq[3];
786
787 ath_dbg(common, CALIBRATE,
788 "chain %d: mag mismatch=%d phase mismatch=%d\n",
789 chain_idx, mag_tx/res_scale, phs_tx/res_scale);
790
791 if (res_scale == mag_tx) {
792 ath_dbg(common, CALIBRATE,
793 "Divide by 0: mag_tx=%d, res_scale=%d\n",
794 mag_tx, res_scale);
795 return false;
796 }
797
798 /* calculate and quantize Tx IQ correction factor */
799 mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
800 phs_corr_tx = -phs_tx;
801
802 q_q_coff = (mag_corr_tx * 128 / res_scale);
803 q_i_coff = (phs_corr_tx * 256 / res_scale);
804
805 ath_dbg(common, CALIBRATE, "tx chain %d: mag corr=%d phase corr=%d\n",
806 chain_idx, q_q_coff, q_i_coff);
807
808 if (q_i_coff < -63)
809 q_i_coff = -63;
810 if (q_i_coff > 63)
811 q_i_coff = 63;
812 if (q_q_coff < -63)
813 q_q_coff = -63;
814 if (q_q_coff > 63)
815 q_q_coff = 63;
816
817 iqc_coeff[0] = (q_q_coff * 128) + (0x7f & q_i_coff);
818
819 ath_dbg(common, CALIBRATE, "tx chain %d: iq corr coeff=%x\n",
820 chain_idx, iqc_coeff[0]);
821
822 if (-mag_rx == res_scale) {
823 ath_dbg(common, CALIBRATE,
824 "Divide by 0: mag_rx=%d, res_scale=%d\n",
825 mag_rx, res_scale);
826 return false;
827 }
828
829 /* calculate and quantize Rx IQ correction factors */
830 mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
831 phs_corr_rx = -phs_rx;
832
833 q_q_coff = (mag_corr_rx * 128 / res_scale);
834 q_i_coff = (phs_corr_rx * 256 / res_scale);
835
836 ath_dbg(common, CALIBRATE, "rx chain %d: mag corr=%d phase corr=%d\n",
837 chain_idx, q_q_coff, q_i_coff);
838
839 if (q_i_coff < -63)
840 q_i_coff = -63;
841 if (q_i_coff > 63)
842 q_i_coff = 63;
843 if (q_q_coff < -63)
844 q_q_coff = -63;
845 if (q_q_coff > 63)
846 q_q_coff = 63;
847
848 iqc_coeff[1] = (q_q_coff * 128) + (0x7f & q_i_coff);
849
850 ath_dbg(common, CALIBRATE, "rx chain %d: iq corr coeff=%x\n",
851 chain_idx, iqc_coeff[1]);
852
853 return true;
854 }
855
856 static void ar9003_hw_detect_outlier(int mp_coeff[][MAXIQCAL],
857 int nmeasurement,
858 int max_delta)
859 {
860 int mp_max = -64, max_idx = 0;
861 int mp_min = 63, min_idx = 0;
862 int mp_avg = 0, i, outlier_idx = 0, mp_count = 0;
863
864 /* find min/max mismatch across all calibrated gains */
865 for (i = 0; i < nmeasurement; i++) {
866 if (mp_coeff[i][0] > mp_max) {
867 mp_max = mp_coeff[i][0];
868 max_idx = i;
869 } else if (mp_coeff[i][0] < mp_min) {
870 mp_min = mp_coeff[i][0];
871 min_idx = i;
872 }
873 }
874
875 /* find average (exclude max abs value) */
876 for (i = 0; i < nmeasurement; i++) {
877 if ((abs(mp_coeff[i][0]) < abs(mp_max)) ||
878 (abs(mp_coeff[i][0]) < abs(mp_min))) {
879 mp_avg += mp_coeff[i][0];
880 mp_count++;
881 }
882 }
883
884 /*
885 * finding mean magnitude/phase if possible, otherwise
886 * just use the last value as the mean
887 */
888 if (mp_count)
889 mp_avg /= mp_count;
890 else
891 mp_avg = mp_coeff[nmeasurement - 1][0];
892
893 /* detect outlier */
894 if (abs(mp_max - mp_min) > max_delta) {
895 if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
896 outlier_idx = max_idx;
897 else
898 outlier_idx = min_idx;
899
900 mp_coeff[outlier_idx][0] = mp_avg;
901 }
902 }
903
904 static void ar9003_hw_tx_iq_cal_outlier_detection(struct ath_hw *ah,
905 struct coeff *coeff,
906 bool is_reusable)
907 {
908 int i, im, nmeasurement;
909 int magnitude, phase;
910 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
911 struct ath9k_hw_cal_data *caldata = ah->caldata;
912
913 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
914 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
915 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
916 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
917 if (!AR_SREV_9485(ah)) {
918 tx_corr_coeff[i * 2][1] =
919 tx_corr_coeff[(i * 2) + 1][1] =
920 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
921
922 tx_corr_coeff[i * 2][2] =
923 tx_corr_coeff[(i * 2) + 1][2] =
924 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
925 }
926 }
927
928 /* Load the average of 2 passes */
929 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
930 if (!(ah->txchainmask & (1 << i)))
931 continue;
932 nmeasurement = REG_READ_FIELD(ah,
933 AR_PHY_TX_IQCAL_STATUS_B0,
934 AR_PHY_CALIBRATED_GAINS_0);
935
936 if (nmeasurement > MAX_MEASUREMENT)
937 nmeasurement = MAX_MEASUREMENT;
938
939 /*
940 * Skip normal outlier detection for AR9550.
941 */
942 if (!AR_SREV_9550(ah)) {
943 /* detect outlier only if nmeasurement > 1 */
944 if (nmeasurement > 1) {
945 /* Detect magnitude outlier */
946 ar9003_hw_detect_outlier(coeff->mag_coeff[i],
947 nmeasurement,
948 MAX_MAG_DELTA);
949
950 /* Detect phase outlier */
951 ar9003_hw_detect_outlier(coeff->phs_coeff[i],
952 nmeasurement,
953 MAX_PHS_DELTA);
954 }
955 }
956
957 for (im = 0; im < nmeasurement; im++) {
958 magnitude = coeff->mag_coeff[i][im][0];
959 phase = coeff->phs_coeff[i][im][0];
960
961 coeff->iqc_coeff[0] =
962 (phase & 0x7f) | ((magnitude & 0x7f) << 7);
963
964 if ((im % 2) == 0)
965 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
966 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
967 coeff->iqc_coeff[0]);
968 else
969 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
970 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
971 coeff->iqc_coeff[0]);
972
973 if (caldata)
974 caldata->tx_corr_coeff[im][i] =
975 coeff->iqc_coeff[0];
976 }
977 if (caldata)
978 caldata->num_measures[i] = nmeasurement;
979 }
980
981 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
982 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
983 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
984 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
985
986 if (caldata) {
987 if (is_reusable)
988 set_bit(TXIQCAL_DONE, &caldata->cal_flags);
989 else
990 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
991 }
992
993 return;
994 }
995
996 static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
997 {
998 struct ath_common *common = ath9k_hw_common(ah);
999 u8 tx_gain_forced;
1000
1001 tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
1002 AR_PHY_TXGAIN_FORCE);
1003 if (tx_gain_forced)
1004 REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
1005 AR_PHY_TXGAIN_FORCE, 0);
1006
1007 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
1008 AR_PHY_TX_IQCAL_START_DO_CAL, 1);
1009
1010 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
1011 AR_PHY_TX_IQCAL_START_DO_CAL, 0,
1012 AH_WAIT_TIMEOUT)) {
1013 ath_dbg(common, CALIBRATE, "Tx IQ Cal is not completed\n");
1014 return false;
1015 }
1016 return true;
1017 }
1018
1019 static void __ar955x_tx_iq_cal_sort(struct ath_hw *ah,
1020 struct coeff *coeff,
1021 int i, int nmeasurement)
1022 {
1023 struct ath_common *common = ath9k_hw_common(ah);
1024 int im, ix, iy, temp;
1025
1026 for (im = 0; im < nmeasurement; im++) {
1027 for (ix = 0; ix < MAXIQCAL - 1; ix++) {
1028 for (iy = ix + 1; iy <= MAXIQCAL - 1; iy++) {
1029 if (coeff->mag_coeff[i][im][iy] <
1030 coeff->mag_coeff[i][im][ix]) {
1031 temp = coeff->mag_coeff[i][im][ix];
1032 coeff->mag_coeff[i][im][ix] =
1033 coeff->mag_coeff[i][im][iy];
1034 coeff->mag_coeff[i][im][iy] = temp;
1035 }
1036 if (coeff->phs_coeff[i][im][iy] <
1037 coeff->phs_coeff[i][im][ix]) {
1038 temp = coeff->phs_coeff[i][im][ix];
1039 coeff->phs_coeff[i][im][ix] =
1040 coeff->phs_coeff[i][im][iy];
1041 coeff->phs_coeff[i][im][iy] = temp;
1042 }
1043 }
1044 }
1045 coeff->mag_coeff[i][im][0] = coeff->mag_coeff[i][im][MAXIQCAL / 2];
1046 coeff->phs_coeff[i][im][0] = coeff->phs_coeff[i][im][MAXIQCAL / 2];
1047
1048 ath_dbg(common, CALIBRATE,
1049 "IQCAL: Median [ch%d][gain%d]: mag = %d phase = %d\n",
1050 i, im,
1051 coeff->mag_coeff[i][im][0],
1052 coeff->phs_coeff[i][im][0]);
1053 }
1054 }
1055
1056 static bool ar955x_tx_iq_cal_median(struct ath_hw *ah,
1057 struct coeff *coeff,
1058 int iqcal_idx,
1059 int nmeasurement)
1060 {
1061 int i;
1062
1063 if ((iqcal_idx + 1) != MAXIQCAL)
1064 return false;
1065
1066 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1067 __ar955x_tx_iq_cal_sort(ah, coeff, i, nmeasurement);
1068 }
1069
1070 return true;
1071 }
1072
1073 static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah,
1074 int iqcal_idx,
1075 bool is_reusable)
1076 {
1077 struct ath_common *common = ath9k_hw_common(ah);
1078 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
1079 AR_PHY_TX_IQCAL_STATUS_B0,
1080 AR_PHY_TX_IQCAL_STATUS_B1,
1081 AR_PHY_TX_IQCAL_STATUS_B2,
1082 };
1083 const u_int32_t chan_info_tab[] = {
1084 AR_PHY_CHAN_INFO_TAB_0,
1085 AR_PHY_CHAN_INFO_TAB_1,
1086 AR_PHY_CHAN_INFO_TAB_2,
1087 };
1088 static struct coeff coeff;
1089 s32 iq_res[6];
1090 int i, im, j;
1091 int nmeasurement = 0;
1092 bool outlier_detect = true;
1093
1094 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1095 if (!(ah->txchainmask & (1 << i)))
1096 continue;
1097
1098 nmeasurement = REG_READ_FIELD(ah,
1099 AR_PHY_TX_IQCAL_STATUS_B0,
1100 AR_PHY_CALIBRATED_GAINS_0);
1101 if (nmeasurement > MAX_MEASUREMENT)
1102 nmeasurement = MAX_MEASUREMENT;
1103
1104 for (im = 0; im < nmeasurement; im++) {
1105 ath_dbg(common, CALIBRATE,
1106 "Doing Tx IQ Cal for chain %d\n", i);
1107
1108 if (REG_READ(ah, txiqcal_status[i]) &
1109 AR_PHY_TX_IQCAL_STATUS_FAILED) {
1110 ath_dbg(common, CALIBRATE,
1111 "Tx IQ Cal failed for chain %d\n", i);
1112 goto tx_iqcal_fail;
1113 }
1114
1115 for (j = 0; j < 3; j++) {
1116 u32 idx = 2 * j, offset = 4 * (3 * im + j);
1117
1118 REG_RMW_FIELD(ah,
1119 AR_PHY_CHAN_INFO_MEMORY,
1120 AR_PHY_CHAN_INFO_TAB_S2_READ,
1121 0);
1122
1123 /* 32 bits */
1124 iq_res[idx] = REG_READ(ah,
1125 chan_info_tab[i] +
1126 offset);
1127
1128 REG_RMW_FIELD(ah,
1129 AR_PHY_CHAN_INFO_MEMORY,
1130 AR_PHY_CHAN_INFO_TAB_S2_READ,
1131 1);
1132
1133 /* 16 bits */
1134 iq_res[idx + 1] = 0xffff & REG_READ(ah,
1135 chan_info_tab[i] + offset);
1136
1137 ath_dbg(common, CALIBRATE,
1138 "IQ_RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
1139 idx, iq_res[idx], idx + 1,
1140 iq_res[idx + 1]);
1141 }
1142
1143 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
1144 coeff.iqc_coeff)) {
1145 ath_dbg(common, CALIBRATE,
1146 "Failed in calculation of IQ correction\n");
1147 goto tx_iqcal_fail;
1148 }
1149
1150 coeff.phs_coeff[i][im][iqcal_idx] =
1151 coeff.iqc_coeff[0] & 0x7f;
1152 coeff.mag_coeff[i][im][iqcal_idx] =
1153 (coeff.iqc_coeff[0] >> 7) & 0x7f;
1154
1155 if (coeff.mag_coeff[i][im][iqcal_idx] > 63)
1156 coeff.mag_coeff[i][im][iqcal_idx] -= 128;
1157 if (coeff.phs_coeff[i][im][iqcal_idx] > 63)
1158 coeff.phs_coeff[i][im][iqcal_idx] -= 128;
1159 }
1160 }
1161
1162 if (AR_SREV_9550(ah))
1163 outlier_detect = ar955x_tx_iq_cal_median(ah, &coeff,
1164 iqcal_idx, nmeasurement);
1165 if (outlier_detect)
1166 ar9003_hw_tx_iq_cal_outlier_detection(ah, &coeff, is_reusable);
1167
1168 return;
1169
1170 tx_iqcal_fail:
1171 ath_dbg(common, CALIBRATE, "Tx IQ Cal failed\n");
1172 return;
1173 }
1174
1175 static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
1176 {
1177 struct ath9k_hw_cal_data *caldata = ah->caldata;
1178 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
1179 int i, im;
1180
1181 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
1182 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
1183 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
1184 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
1185 if (!AR_SREV_9485(ah)) {
1186 tx_corr_coeff[i * 2][1] =
1187 tx_corr_coeff[(i * 2) + 1][1] =
1188 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
1189
1190 tx_corr_coeff[i * 2][2] =
1191 tx_corr_coeff[(i * 2) + 1][2] =
1192 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
1193 }
1194 }
1195
1196 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1197 if (!(ah->txchainmask & (1 << i)))
1198 continue;
1199
1200 for (im = 0; im < caldata->num_measures[i]; im++) {
1201 if ((im % 2) == 0)
1202 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
1203 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
1204 caldata->tx_corr_coeff[im][i]);
1205 else
1206 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
1207 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
1208 caldata->tx_corr_coeff[im][i]);
1209 }
1210 }
1211
1212 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
1213 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
1214 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
1215 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
1216 }
1217
1218 static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
1219 {
1220 int offset[8] = {0}, total = 0, test;
1221 int agc_out, i, peak_detect_threshold = 0;
1222
1223 if (AR_SREV_9550(ah) || AR_SREV_9531(ah))
1224 peak_detect_threshold = 8;
1225 else if (AR_SREV_9561(ah))
1226 peak_detect_threshold = 11;
1227
1228 /*
1229 * Turn off LNA/SW.
1230 */
1231 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1232 AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE, 0x1);
1233 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1234 AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC, 0x0);
1235
1236 if (AR_SREV_9003_PCOEM(ah) || AR_SREV_9330_11(ah)) {
1237 if (is_2g)
1238 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1239 AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR, 0x0);
1240 else
1241 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1242 AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR, 0x0);
1243 }
1244
1245 /*
1246 * Turn off RXON.
1247 */
1248 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1249 AR_PHY_65NM_RXTX2_RXON_OVR, 0x1);
1250 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1251 AR_PHY_65NM_RXTX2_RXON, 0x0);
1252
1253 /*
1254 * Turn on AGC for cal.
1255 */
1256 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1257 AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE, 0x1);
1258 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1259 AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
1260 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1261 AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
1262
1263 if (AR_SREV_9330_11(ah))
1264 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1265 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
1266
1267 if (is_2g)
1268 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1269 AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR,
1270 peak_detect_threshold);
1271 else
1272 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1273 AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR,
1274 peak_detect_threshold);
1275
1276 for (i = 6; i > 0; i--) {
1277 offset[i] = BIT(i - 1);
1278 test = total + offset[i];
1279
1280 if (is_2g)
1281 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1282 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR,
1283 test);
1284 else
1285 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1286 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR,
1287 test);
1288 udelay(100);
1289 agc_out = REG_READ_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1290 AR_PHY_65NM_RXRF_AGC_AGC_OUT);
1291 offset[i] = (agc_out) ? 0 : 1;
1292 total += (offset[i] << (i - 1));
1293 }
1294
1295 if (is_2g)
1296 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1297 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, total);
1298 else
1299 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1300 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR, total);
1301
1302 /*
1303 * Turn on LNA.
1304 */
1305 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1306 AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE, 0);
1307 /*
1308 * Turn off RXON.
1309 */
1310 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1311 AR_PHY_65NM_RXTX2_RXON_OVR, 0);
1312 /*
1313 * Turn off peak detect calibration.
1314 */
1315 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1316 AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
1317 }
1318
1319 static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
1320 struct ath9k_channel *chan,
1321 bool run_rtt_cal)
1322 {
1323 struct ath9k_hw_cal_data *caldata = ah->caldata;
1324 int i;
1325
1326 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && !run_rtt_cal)
1327 return;
1328
1329 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1330 if (!(ah->rxchainmask & (1 << i)))
1331 continue;
1332 ar9003_hw_manual_peak_cal(ah, i, IS_CHAN_2GHZ(chan));
1333 }
1334
1335 if (caldata)
1336 set_bit(SW_PKDET_DONE, &caldata->cal_flags);
1337
1338 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && caldata) {
1339 if (IS_CHAN_2GHZ(chan)){
1340 caldata->caldac[0] = REG_READ_FIELD(ah,
1341 AR_PHY_65NM_RXRF_AGC(0),
1342 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR);
1343 caldata->caldac[1] = REG_READ_FIELD(ah,
1344 AR_PHY_65NM_RXRF_AGC(1),
1345 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR);
1346 } else {
1347 caldata->caldac[0] = REG_READ_FIELD(ah,
1348 AR_PHY_65NM_RXRF_AGC(0),
1349 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR);
1350 caldata->caldac[1] = REG_READ_FIELD(ah,
1351 AR_PHY_65NM_RXRF_AGC(1),
1352 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR);
1353 }
1354 }
1355 }
1356
1357 static void ar9003_hw_cl_cal_post_proc(struct ath_hw *ah, bool is_reusable)
1358 {
1359 u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
1360 AR_PHY_CL_TAB_1,
1361 AR_PHY_CL_TAB_2 };
1362 struct ath9k_hw_cal_data *caldata = ah->caldata;
1363 bool txclcal_done = false;
1364 int i, j;
1365
1366 if (!caldata || !(ah->enabled_cals & TX_CL_CAL))
1367 return;
1368
1369 txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
1370 AR_PHY_AGC_CONTROL_CLC_SUCCESS);
1371
1372 if (test_bit(TXCLCAL_DONE, &caldata->cal_flags)) {
1373 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1374 if (!(ah->txchainmask & (1 << i)))
1375 continue;
1376 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1377 REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
1378 caldata->tx_clcal[i][j]);
1379 }
1380 } else if (is_reusable && txclcal_done) {
1381 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1382 if (!(ah->txchainmask & (1 << i)))
1383 continue;
1384 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1385 caldata->tx_clcal[i][j] =
1386 REG_READ(ah, CL_TAB_ENTRY(cl_idx[i]));
1387 }
1388 set_bit(TXCLCAL_DONE, &caldata->cal_flags);
1389 }
1390 }
1391
1392 static void ar9003_hw_init_cal_common(struct ath_hw *ah)
1393 {
1394 struct ath9k_hw_cal_data *caldata = ah->caldata;
1395
1396 /* Initialize list pointers */
1397 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1398
1399 INIT_CAL(&ah->iq_caldata);
1400 INSERT_CAL(ah, &ah->iq_caldata);
1401
1402 INIT_CAL(&ah->temp_caldata);
1403 INSERT_CAL(ah, &ah->temp_caldata);
1404
1405 /* Initialize current pointer to first element in list */
1406 ah->cal_list_curr = ah->cal_list;
1407
1408 if (ah->cal_list_curr)
1409 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1410
1411 if (caldata)
1412 caldata->CalValid = 0;
1413 }
1414
1415 static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
1416 struct ath9k_channel *chan)
1417 {
1418 struct ath_common *common = ath9k_hw_common(ah);
1419 struct ath9k_hw_cal_data *caldata = ah->caldata;
1420 bool txiqcal_done = false;
1421 bool is_reusable = true, status = true;
1422 bool run_rtt_cal = false, run_agc_cal;
1423 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
1424 u32 rx_delay = 0;
1425 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
1426 AR_PHY_AGC_CONTROL_FLTR_CAL |
1427 AR_PHY_AGC_CONTROL_PKDET_CAL;
1428
1429 /* Use chip chainmask only for calibration */
1430 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1431
1432 if (rtt) {
1433 if (!ar9003_hw_rtt_restore(ah, chan))
1434 run_rtt_cal = true;
1435
1436 if (run_rtt_cal)
1437 ath_dbg(common, CALIBRATE, "RTT calibration to be done\n");
1438 }
1439
1440 run_agc_cal = run_rtt_cal;
1441
1442 if (run_rtt_cal) {
1443 ar9003_hw_rtt_enable(ah);
1444 ar9003_hw_rtt_set_mask(ah, 0x00);
1445 ar9003_hw_rtt_clear_hist(ah);
1446 }
1447
1448 if (rtt) {
1449 if (!run_rtt_cal) {
1450 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
1451 agc_supp_cals &= agc_ctrl;
1452 agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
1453 AR_PHY_AGC_CONTROL_FLTR_CAL |
1454 AR_PHY_AGC_CONTROL_PKDET_CAL);
1455 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1456 } else {
1457 if (ah->ah_flags & AH_FASTCC)
1458 run_agc_cal = true;
1459 }
1460 }
1461
1462 if (ah->enabled_cals & TX_CL_CAL) {
1463 if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))
1464 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
1465 AR_PHY_CL_CAL_ENABLE);
1466 else {
1467 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
1468 AR_PHY_CL_CAL_ENABLE);
1469 run_agc_cal = true;
1470 }
1471 }
1472
1473 if ((IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) ||
1474 !(ah->enabled_cals & TX_IQ_CAL))
1475 goto skip_tx_iqcal;
1476
1477 /* Do Tx IQ Calibration */
1478 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
1479 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
1480 DELPT);
1481
1482 /*
1483 * For AR9485 or later chips, TxIQ cal runs as part of
1484 * AGC calibration
1485 */
1486 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
1487 if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags))
1488 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1489 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
1490 else
1491 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1492 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
1493 txiqcal_done = run_agc_cal = true;
1494 }
1495
1496 skip_tx_iqcal:
1497 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1498 ar9003_mci_init_cal_req(ah, &is_reusable);
1499
1500 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
1501 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
1502 /* Disable BB_active */
1503 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1504 udelay(5);
1505 REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);
1506 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1507 }
1508
1509 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1510 /* Calibrate the AGC */
1511 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1512 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1513 AR_PHY_AGC_CONTROL_CAL);
1514
1515 /* Poll for offset calibration complete */
1516 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1517 AR_PHY_AGC_CONTROL_CAL,
1518 0, AH_WAIT_TIMEOUT);
1519
1520 ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
1521 }
1522
1523 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
1524 REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);
1525 udelay(5);
1526 }
1527
1528 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1529 ar9003_mci_init_cal_done(ah);
1530
1531 if (rtt && !run_rtt_cal) {
1532 agc_ctrl |= agc_supp_cals;
1533 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1534 }
1535
1536 if (!status) {
1537 if (run_rtt_cal)
1538 ar9003_hw_rtt_disable(ah);
1539
1540 ath_dbg(common, CALIBRATE,
1541 "offset calibration failed to complete in %d ms; noisy environment?\n",
1542 AH_WAIT_TIMEOUT / 1000);
1543 return false;
1544 }
1545
1546 if (txiqcal_done)
1547 ar9003_hw_tx_iq_cal_post_proc(ah, 0, is_reusable);
1548 else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))
1549 ar9003_hw_tx_iq_cal_reload(ah);
1550
1551 ar9003_hw_cl_cal_post_proc(ah, is_reusable);
1552
1553 if (run_rtt_cal && caldata) {
1554 if (is_reusable) {
1555 if (!ath9k_hw_rfbus_req(ah)) {
1556 ath_err(ath9k_hw_common(ah),
1557 "Could not stop baseband\n");
1558 } else {
1559 ar9003_hw_rtt_fill_hist(ah);
1560
1561 if (test_bit(SW_PKDET_DONE, &caldata->cal_flags))
1562 ar9003_hw_rtt_load_hist(ah);
1563 }
1564
1565 ath9k_hw_rfbus_done(ah);
1566 }
1567
1568 ar9003_hw_rtt_disable(ah);
1569 }
1570
1571 /* Revert chainmask to runtime parameters */
1572 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1573
1574 ar9003_hw_init_cal_common(ah);
1575
1576 return true;
1577 }
1578
1579 static bool do_ar9003_agc_cal(struct ath_hw *ah)
1580 {
1581 struct ath_common *common = ath9k_hw_common(ah);
1582 bool status;
1583
1584 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1585 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1586 AR_PHY_AGC_CONTROL_CAL);
1587
1588 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1589 AR_PHY_AGC_CONTROL_CAL,
1590 0, AH_WAIT_TIMEOUT);
1591 if (!status) {
1592 ath_dbg(common, CALIBRATE,
1593 "offset calibration failed to complete in %d ms,"
1594 "noisy environment?\n",
1595 AH_WAIT_TIMEOUT / 1000);
1596 return false;
1597 }
1598
1599 return true;
1600 }
1601
1602 static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
1603 struct ath9k_channel *chan)
1604 {
1605 bool txiqcal_done = false;
1606 bool status = true;
1607 bool run_agc_cal = false, sep_iq_cal = false;
1608 int i = 0;
1609
1610 /* Use chip chainmask only for calibration */
1611 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1612
1613 if (ah->enabled_cals & TX_CL_CAL) {
1614 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1615 run_agc_cal = true;
1616 }
1617
1618 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
1619 goto skip_tx_iqcal;
1620
1621 /* Do Tx IQ Calibration */
1622 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
1623 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
1624 DELPT);
1625
1626 /*
1627 * For AR9485 or later chips, TxIQ cal runs as part of
1628 * AGC calibration. Specifically, AR9550 in SoC chips.
1629 */
1630 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
1631 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1632 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) {
1633 txiqcal_done = true;
1634 } else {
1635 txiqcal_done = false;
1636 }
1637 run_agc_cal = true;
1638 } else {
1639 sep_iq_cal = true;
1640 run_agc_cal = true;
1641 }
1642
1643 /*
1644 * In the SoC family, this will run for AR9300, AR9331 and AR9340.
1645 */
1646 if (sep_iq_cal) {
1647 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
1648 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1649 udelay(5);
1650 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1651 }
1652
1653 if (AR_SREV_9550(ah) && IS_CHAN_2GHZ(chan)) {
1654 if (!ar9003_hw_dynamic_osdac_selection(ah, txiqcal_done))
1655 return false;
1656 }
1657
1658 skip_tx_iqcal:
1659 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1660 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1661 if (!(ah->rxchainmask & (1 << i)))
1662 continue;
1663
1664 ar9003_hw_manual_peak_cal(ah, i,
1665 IS_CHAN_2GHZ(chan));
1666 }
1667
1668 /*
1669 * For non-AR9550 chips, we just trigger AGC calibration
1670 * in the HW, poll for completion and then process
1671 * the results.
1672 *
1673 * For AR955x, we run it multiple times and use
1674 * median IQ correction.
1675 */
1676 if (!AR_SREV_9550(ah)) {
1677 status = do_ar9003_agc_cal(ah);
1678 if (!status)
1679 return false;
1680
1681 if (txiqcal_done)
1682 ar9003_hw_tx_iq_cal_post_proc(ah, 0, false);
1683 } else {
1684 if (!txiqcal_done) {
1685 status = do_ar9003_agc_cal(ah);
1686 if (!status)
1687 return false;
1688 } else {
1689 for (i = 0; i < MAXIQCAL; i++) {
1690 status = do_ar9003_agc_cal(ah);
1691 if (!status)
1692 return false;
1693 ar9003_hw_tx_iq_cal_post_proc(ah, i, false);
1694 }
1695 }
1696 }
1697 }
1698
1699 /* Revert chainmask to runtime parameters */
1700 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1701
1702 ar9003_hw_init_cal_common(ah);
1703
1704 return true;
1705 }
1706
1707 void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
1708 {
1709 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1710 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1711
1712 if (AR_SREV_9003_PCOEM(ah))
1713 priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
1714 else
1715 priv_ops->init_cal = ar9003_hw_init_cal_soc;
1716
1717 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
1718 priv_ops->setup_calibration = ar9003_hw_setup_calibration;
1719
1720 ops->calibrate = ar9003_hw_calibrate;
1721 }
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