2 * Copyright (c) 2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_phy.h"
19 #include "ar9003_eeprom.h"
21 #define COMP_HDR_LEN 4
22 #define COMP_CKSUM_LEN 2
24 #define AR_CH0_TOP (0x00016288)
25 #define AR_CH0_TOP_XPABIASLVL (0x300)
26 #define AR_CH0_TOP_XPABIASLVL_S (8)
28 #define AR_CH0_THERM (0x00016290)
29 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
30 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
31 #define AR_CH0_THERM_XPASHORT2GND 0x4
32 #define AR_CH0_THERM_XPASHORT2GND_S 2
34 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
35 #define AR_SWITCH_TABLE_COM_ALL_S (0)
37 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
38 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
40 #define AR_SWITCH_TABLE_ALL (0xfff)
41 #define AR_SWITCH_TABLE_ALL_S (0)
43 #define LE16(x) __constant_cpu_to_le16(x)
44 #define LE32(x) __constant_cpu_to_le32(x)
46 /* Local defines to distinguish between extension and control CTL's */
47 #define EXT_ADDITIVE (0x8000)
48 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
49 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
50 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
51 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
52 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
53 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
54 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
55 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
57 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
58 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
60 static int ar9003_hw_power_interpolate(int32_t x
,
61 int32_t *px
, int32_t *py
, u_int16_t np
);
62 static const struct ar9300_eeprom ar9300_default
= {
65 .macAddr
= {1, 2, 3, 4, 5, 6},
66 .custData
= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
67 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
69 .regDmn
= { LE16(0), LE16(0x1f) },
70 .txrxMask
= 0x77, /* 4 bits tx and 4 bits rx */
72 .opFlags
= AR9300_OPFLAGS_11G
| AR9300_OPFLAGS_11A
,
76 .blueToothOptions
= 0,
78 .deviceType
= 5, /* takes lower byte in eeprom location */
79 .pwrTableOffset
= AR9300_PWR_TABLE_OFFSET
,
80 .params_for_tuning_caps
= {0, 0},
81 .featureEnable
= 0x0c,
83 * bit0 - enable tx temp comp - disabled
84 * bit1 - enable tx volt comp - disabled
85 * bit2 - enable fastClock - enabled
86 * bit3 - enable doubling - enabled
87 * bit4 - enable internal regulator - disabled
88 * bit5 - enable pa predistortion - disabled
90 .miscConfiguration
= 0, /* bit0 - turn down drivestrength */
91 .eepromWriteEnableGpio
= 3,
94 .rxBandSelectGpio
= 0xff,
99 /* ar9300_modal_eep_header 2g */
100 /* 4 idle,t1,t2,b(4 bits per setting) */
101 .antCtrlCommon
= LE32(0x110),
102 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
103 .antCtrlCommon2
= LE32(0x22222),
106 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
107 * rx1, rx12, b (2 bits each)
109 .antCtrlChain
= { LE16(0x150), LE16(0x150), LE16(0x150) },
112 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
113 * for ar9280 (0xa20c/b20c 5:0)
115 .xatten1DB
= {0, 0, 0},
118 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
119 * for ar9280 (0xa20c/b20c 16:12
121 .xatten1Margin
= {0, 0, 0},
126 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
127 * channels in usual fbin coding format
129 .spurChans
= {0, 0, 0, 0, 0},
132 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
133 * if the register is per chain
135 .noiseFloorThreshCh
= {-1, 0, 0},
136 .ob
= {1, 1, 1},/* 3 chain */
137 .db_stage2
= {1, 1, 1}, /* 3 chain */
138 .db_stage3
= {0, 0, 0},
139 .db_stage4
= {0, 0, 0},
141 .txFrameToDataStart
= 0x0e,
142 .txFrameToPaOn
= 0x0e,
143 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
145 .switchSettling
= 0x2c,
146 .adcDesiredSize
= -30,
149 .txFrameToXpaOn
= 0xe,
151 .papdRateMaskHt20
= LE32(0x0cf0e0e0),
152 .papdRateMaskHt40
= LE32(0x6cf0e0e0),
154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
158 .ant_div_control
= 0,
159 .future
= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
166 /* ar9300_cal_data_per_freq_op_loop 2g */
168 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
169 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
170 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
172 .calTarget_freqbin_Cck
= {
176 .calTarget_freqbin_2G
= {
181 .calTarget_freqbin_2GHT20
= {
186 .calTarget_freqbin_2GHT40
= {
191 .calTargetPowerCck
= {
192 /* 1L-5L,5S,11L,11S */
193 { {36, 36, 36, 36} },
194 { {36, 36, 36, 36} },
196 .calTargetPower2G
= {
198 { {32, 32, 28, 24} },
199 { {32, 32, 28, 24} },
200 { {32, 32, 28, 24} },
202 .calTargetPower2GHT20
= {
203 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
204 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
205 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
207 .calTargetPower2GHT40
= {
208 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
209 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
210 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
213 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
214 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
244 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
245 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
246 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
247 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
251 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
252 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
253 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
258 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
259 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
265 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
266 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
267 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
268 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
272 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
273 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
274 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
278 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
279 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
280 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
285 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
286 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
287 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
292 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
293 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
294 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
295 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
299 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
300 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
301 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
303 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
304 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
305 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
307 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
308 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
309 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
311 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
312 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
313 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
316 /* 4 idle,t1,t2,b (4 bits per setting) */
317 .antCtrlCommon
= LE32(0x110),
318 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
319 .antCtrlCommon2
= LE32(0x22222),
320 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
322 LE16(0x000), LE16(0x000), LE16(0x000),
324 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
325 .xatten1DB
= {0, 0, 0},
328 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
329 * for merlin (0xa20c/b20c 16:12
331 .xatten1Margin
= {0, 0, 0},
334 /* spurChans spur channels in usual fbin coding format */
335 .spurChans
= {0, 0, 0, 0, 0},
336 /* noiseFloorThreshCh Check if the register is per chain */
337 .noiseFloorThreshCh
= {-1, 0, 0},
338 .ob
= {3, 3, 3}, /* 3 chain */
339 .db_stage2
= {3, 3, 3}, /* 3 chain */
340 .db_stage3
= {3, 3, 3}, /* doesn't exist for 2G */
341 .db_stage4
= {3, 3, 3}, /* don't exist for 2G */
343 .txFrameToDataStart
= 0x0e,
344 .txFrameToPaOn
= 0x0e,
345 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
347 .switchSettling
= 0x2d,
348 .adcDesiredSize
= -30,
351 .txFrameToXpaOn
= 0xe,
353 .papdRateMaskHt20
= LE32(0x0c80c080),
354 .papdRateMaskHt40
= LE32(0x0080c080),
356 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
362 .xatten1DBLow
= {0, 0, 0},
363 .xatten1MarginLow
= {0, 0, 0},
364 .xatten1DBHigh
= {0, 0, 0},
365 .xatten1MarginHigh
= {0, 0, 0}
410 .calTarget_freqbin_5G
= {
420 .calTarget_freqbin_5GHT20
= {
430 .calTarget_freqbin_5GHT40
= {
440 .calTargetPower5G
= {
442 { {20, 20, 20, 10} },
443 { {20, 20, 20, 10} },
444 { {20, 20, 20, 10} },
445 { {20, 20, 20, 10} },
446 { {20, 20, 20, 10} },
447 { {20, 20, 20, 10} },
448 { {20, 20, 20, 10} },
449 { {20, 20, 20, 10} },
451 .calTargetPower5GHT20
= {
453 * 0_8_16,1-3_9-11_17-19,
454 * 4,5,6,7,12,13,14,15,20,21,22,23
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
465 .calTargetPower5GHT40
= {
467 * 0_8_16,1-3_9-11_17-19,
468 * 4,5,6,7,12,13,14,15,20,21,22,23
470 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
472 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
473 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
474 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
475 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
476 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
477 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
480 0x10, 0x16, 0x18, 0x40, 0x46,
481 0x48, 0x30, 0x36, 0x38
485 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
486 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
487 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
488 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
489 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
490 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
491 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
492 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
495 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
496 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
497 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
498 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
499 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
500 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
501 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
502 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
506 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
507 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
508 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
509 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
510 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
511 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
512 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
513 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
517 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
518 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
519 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
520 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
521 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
522 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
523 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
524 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
528 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
529 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
530 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
531 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
532 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
533 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
534 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
535 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
539 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
540 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
541 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
542 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
543 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
544 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
545 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
546 /* Data[5].ctlEdges[7].bChannel */ 0xFF
550 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
551 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
552 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
553 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
554 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
555 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
556 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
557 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
561 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
562 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
563 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
564 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
565 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
566 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
567 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
568 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
572 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
573 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
574 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
575 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
576 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
577 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
578 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
579 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
585 {60, 1}, {60, 1}, {60, 1}, {60, 1},
586 {60, 1}, {60, 1}, {60, 1}, {60, 0},
591 {60, 1}, {60, 1}, {60, 1}, {60, 1},
592 {60, 1}, {60, 1}, {60, 1}, {60, 0},
597 {60, 0}, {60, 1}, {60, 0}, {60, 1},
598 {60, 1}, {60, 1}, {60, 1}, {60, 1},
603 {60, 0}, {60, 1}, {60, 1}, {60, 0},
604 {60, 1}, {60, 0}, {60, 0}, {60, 0},
609 {60, 1}, {60, 1}, {60, 1}, {60, 0},
610 {60, 0}, {60, 0}, {60, 0}, {60, 0},
615 {60, 1}, {60, 1}, {60, 1}, {60, 1},
616 {60, 1}, {60, 0}, {60, 0}, {60, 0},
621 {60, 1}, {60, 1}, {60, 1}, {60, 1},
622 {60, 1}, {60, 1}, {60, 1}, {60, 1},
627 {60, 1}, {60, 1}, {60, 0}, {60, 1},
628 {60, 1}, {60, 1}, {60, 1}, {60, 0},
633 {60, 1}, {60, 0}, {60, 1}, {60, 1},
634 {60, 1}, {60, 1}, {60, 0}, {60, 1},
640 static const struct ar9300_eeprom ar9300_x113
= {
642 .templateVersion
= 6,
643 .macAddr
= {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
644 .custData
= {"x113-023-f0000"},
646 .regDmn
= { LE16(0), LE16(0x1f) },
647 .txrxMask
= 0x77, /* 4 bits tx and 4 bits rx */
649 .opFlags
= AR9300_OPFLAGS_11G
| AR9300_OPFLAGS_11A
,
653 .blueToothOptions
= 0,
655 .deviceType
= 5, /* takes lower byte in eeprom location */
656 .pwrTableOffset
= AR9300_PWR_TABLE_OFFSET
,
657 .params_for_tuning_caps
= {0, 0},
658 .featureEnable
= 0x0d,
660 * bit0 - enable tx temp comp - disabled
661 * bit1 - enable tx volt comp - disabled
662 * bit2 - enable fastClock - enabled
663 * bit3 - enable doubling - enabled
664 * bit4 - enable internal regulator - disabled
665 * bit5 - enable pa predistortion - disabled
667 .miscConfiguration
= 0, /* bit0 - turn down drivestrength */
668 .eepromWriteEnableGpio
= 6,
669 .wlanDisableGpio
= 0,
671 .rxBandSelectGpio
= 0xff,
676 /* ar9300_modal_eep_header 2g */
677 /* 4 idle,t1,t2,b(4 bits per setting) */
678 .antCtrlCommon
= LE32(0x110),
679 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
680 .antCtrlCommon2
= LE32(0x44444),
683 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
684 * rx1, rx12, b (2 bits each)
686 .antCtrlChain
= { LE16(0x150), LE16(0x150), LE16(0x150) },
689 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
690 * for ar9280 (0xa20c/b20c 5:0)
692 .xatten1DB
= {0, 0, 0},
695 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
696 * for ar9280 (0xa20c/b20c 16:12
698 .xatten1Margin
= {0, 0, 0},
703 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
704 * channels in usual fbin coding format
706 .spurChans
= {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
709 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
710 * if the register is per chain
712 .noiseFloorThreshCh
= {-1, 0, 0},
713 .ob
= {1, 1, 1},/* 3 chain */
714 .db_stage2
= {1, 1, 1}, /* 3 chain */
715 .db_stage3
= {0, 0, 0},
716 .db_stage4
= {0, 0, 0},
718 .txFrameToDataStart
= 0x0e,
719 .txFrameToPaOn
= 0x0e,
720 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
722 .switchSettling
= 0x2c,
723 .adcDesiredSize
= -30,
726 .txFrameToXpaOn
= 0xe,
728 .papdRateMaskHt20
= LE32(0x0c80c080),
729 .papdRateMaskHt40
= LE32(0x0080c080),
731 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
735 .ant_div_control
= 0,
736 .future
= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
743 /* ar9300_cal_data_per_freq_op_loop 2g */
745 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
746 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
747 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
749 .calTarget_freqbin_Cck
= {
753 .calTarget_freqbin_2G
= {
758 .calTarget_freqbin_2GHT20
= {
763 .calTarget_freqbin_2GHT40
= {
768 .calTargetPowerCck
= {
769 /* 1L-5L,5S,11L,11S */
770 { {34, 34, 34, 34} },
771 { {34, 34, 34, 34} },
773 .calTargetPower2G
= {
775 { {34, 34, 32, 32} },
776 { {34, 34, 32, 32} },
777 { {34, 34, 32, 32} },
779 .calTargetPower2GHT20
= {
780 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
781 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
782 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
784 .calTargetPower2GHT40
= {
785 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
786 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
787 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
790 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
791 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
821 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
822 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
823 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
824 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
828 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
829 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
830 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
835 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
836 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
842 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
843 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
844 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
845 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
849 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
850 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
851 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
855 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
856 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
857 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
862 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
863 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
864 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
869 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
870 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
871 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
872 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
876 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
877 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
878 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
880 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
881 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
882 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
884 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
885 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
886 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
888 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
889 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
890 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
893 /* 4 idle,t1,t2,b (4 bits per setting) */
894 .antCtrlCommon
= LE32(0x220),
895 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
896 .antCtrlCommon2
= LE32(0x11111),
897 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
899 LE16(0x150), LE16(0x150), LE16(0x150),
901 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
902 .xatten1DB
= {0, 0, 0},
905 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
906 * for merlin (0xa20c/b20c 16:12
908 .xatten1Margin
= {0, 0, 0},
911 /* spurChans spur channels in usual fbin coding format */
912 .spurChans
= {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
913 /* noiseFloorThreshCh Check if the register is per chain */
914 .noiseFloorThreshCh
= {-1, 0, 0},
915 .ob
= {3, 3, 3}, /* 3 chain */
916 .db_stage2
= {3, 3, 3}, /* 3 chain */
917 .db_stage3
= {3, 3, 3}, /* doesn't exist for 2G */
918 .db_stage4
= {3, 3, 3}, /* don't exist for 2G */
920 .txFrameToDataStart
= 0x0e,
921 .txFrameToPaOn
= 0x0e,
922 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
924 .switchSettling
= 0x2d,
925 .adcDesiredSize
= -30,
928 .txFrameToXpaOn
= 0xe,
930 .papdRateMaskHt20
= LE32(0x0cf0e0e0),
931 .papdRateMaskHt40
= LE32(0x6cf0e0e0),
933 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
938 .tempSlopeHigh
= 105,
939 .xatten1DBLow
= {0, 0, 0},
940 .xatten1MarginLow
= {0, 0, 0},
941 .xatten1DBHigh
= {0, 0, 0},
942 .xatten1MarginHigh
= {0, 0, 0}
987 .calTarget_freqbin_5G
= {
997 .calTarget_freqbin_5GHT20
= {
1007 .calTarget_freqbin_5GHT40
= {
1017 .calTargetPower5G
= {
1019 { {42, 40, 40, 34} },
1020 { {42, 40, 40, 34} },
1021 { {42, 40, 40, 34} },
1022 { {42, 40, 40, 34} },
1023 { {42, 40, 40, 34} },
1024 { {42, 40, 40, 34} },
1025 { {42, 40, 40, 34} },
1026 { {42, 40, 40, 34} },
1028 .calTargetPower5GHT20
= {
1030 * 0_8_16,1-3_9-11_17-19,
1031 * 4,5,6,7,12,13,14,15,20,21,22,23
1033 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1034 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1035 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1036 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1037 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1038 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1039 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1040 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1042 .calTargetPower5GHT40
= {
1044 * 0_8_16,1-3_9-11_17-19,
1045 * 4,5,6,7,12,13,14,15,20,21,22,23
1047 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1048 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1049 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1050 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1051 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1052 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1053 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1054 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1057 0x10, 0x16, 0x18, 0x40, 0x46,
1058 0x48, 0x30, 0x36, 0x38
1062 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1063 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1064 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1065 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1066 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1067 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1068 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1069 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1072 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1073 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1074 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1075 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1076 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1077 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1078 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1079 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1083 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1084 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1085 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1086 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1087 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1088 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1089 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1090 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1094 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1095 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1096 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1097 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1098 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1099 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1100 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1101 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1105 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1106 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1107 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1108 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1109 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1110 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1111 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1112 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1116 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1117 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1118 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1119 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1120 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1121 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1122 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1123 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1127 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1128 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1129 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1130 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1131 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1132 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1133 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1134 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1138 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1139 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1140 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1141 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1142 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1143 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1144 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1145 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1149 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1150 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1151 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1152 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1153 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1154 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1155 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1156 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1159 .ctlPowerData_5G
= {
1162 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1163 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1168 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1169 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1174 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1175 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1180 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1181 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1186 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1187 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1192 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1193 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1198 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1199 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1204 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1205 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1210 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1211 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1218 static const struct ar9300_eeprom ar9300_h112
= {
1220 .templateVersion
= 3,
1221 .macAddr
= {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1222 .custData
= {"h112-241-f0000"},
1224 .regDmn
= { LE16(0), LE16(0x1f) },
1225 .txrxMask
= 0x77, /* 4 bits tx and 4 bits rx */
1227 .opFlags
= AR9300_OPFLAGS_11G
| AR9300_OPFLAGS_11A
,
1231 .blueToothOptions
= 0,
1233 .deviceType
= 5, /* takes lower byte in eeprom location */
1234 .pwrTableOffset
= AR9300_PWR_TABLE_OFFSET
,
1235 .params_for_tuning_caps
= {0, 0},
1236 .featureEnable
= 0x0d,
1238 * bit0 - enable tx temp comp - disabled
1239 * bit1 - enable tx volt comp - disabled
1240 * bit2 - enable fastClock - enabled
1241 * bit3 - enable doubling - enabled
1242 * bit4 - enable internal regulator - disabled
1243 * bit5 - enable pa predistortion - disabled
1245 .miscConfiguration
= 0, /* bit0 - turn down drivestrength */
1246 .eepromWriteEnableGpio
= 6,
1247 .wlanDisableGpio
= 0,
1249 .rxBandSelectGpio
= 0xff,
1254 /* ar9300_modal_eep_header 2g */
1255 /* 4 idle,t1,t2,b(4 bits per setting) */
1256 .antCtrlCommon
= LE32(0x110),
1257 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1258 .antCtrlCommon2
= LE32(0x44444),
1261 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1262 * rx1, rx12, b (2 bits each)
1264 .antCtrlChain
= { LE16(0x150), LE16(0x150), LE16(0x150) },
1267 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1268 * for ar9280 (0xa20c/b20c 5:0)
1270 .xatten1DB
= {0, 0, 0},
1273 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1274 * for ar9280 (0xa20c/b20c 16:12
1276 .xatten1Margin
= {0, 0, 0},
1281 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1282 * channels in usual fbin coding format
1284 .spurChans
= {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1287 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1288 * if the register is per chain
1290 .noiseFloorThreshCh
= {-1, 0, 0},
1291 .ob
= {1, 1, 1},/* 3 chain */
1292 .db_stage2
= {1, 1, 1}, /* 3 chain */
1293 .db_stage3
= {0, 0, 0},
1294 .db_stage4
= {0, 0, 0},
1296 .txFrameToDataStart
= 0x0e,
1297 .txFrameToPaOn
= 0x0e,
1298 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1300 .switchSettling
= 0x2c,
1301 .adcDesiredSize
= -30,
1304 .txFrameToXpaOn
= 0xe,
1306 .papdRateMaskHt20
= LE32(0x80c080),
1307 .papdRateMaskHt40
= LE32(0x80c080),
1309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1313 .ant_div_control
= 0,
1314 .future
= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1321 /* ar9300_cal_data_per_freq_op_loop 2g */
1323 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1324 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1325 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1327 .calTarget_freqbin_Cck
= {
1331 .calTarget_freqbin_2G
= {
1336 .calTarget_freqbin_2GHT20
= {
1341 .calTarget_freqbin_2GHT40
= {
1346 .calTargetPowerCck
= {
1347 /* 1L-5L,5S,11L,11S */
1348 { {34, 34, 34, 34} },
1349 { {34, 34, 34, 34} },
1351 .calTargetPower2G
= {
1353 { {34, 34, 32, 32} },
1354 { {34, 34, 32, 32} },
1355 { {34, 34, 32, 32} },
1357 .calTargetPower2GHT20
= {
1358 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1359 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1360 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1362 .calTargetPower2GHT40
= {
1363 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1364 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1365 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1368 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1369 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1399 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1400 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1401 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1402 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1406 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1413 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1420 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1427 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1428 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1429 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1433 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1434 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1435 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1440 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1441 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1442 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1447 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1448 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1449 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1450 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1453 .ctlPowerData_2G
= {
1454 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1455 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1456 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
1458 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
1459 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1460 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1462 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
1463 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1464 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1466 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1467 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1468 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1471 /* 4 idle,t1,t2,b (4 bits per setting) */
1472 .antCtrlCommon
= LE32(0x220),
1473 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1474 .antCtrlCommon2
= LE32(0x44444),
1475 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1477 LE16(0x150), LE16(0x150), LE16(0x150),
1479 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1480 .xatten1DB
= {0, 0, 0},
1483 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1484 * for merlin (0xa20c/b20c 16:12
1486 .xatten1Margin
= {0, 0, 0},
1489 /* spurChans spur channels in usual fbin coding format */
1490 .spurChans
= {0, 0, 0, 0, 0},
1491 /* noiseFloorThreshCh Check if the register is per chain */
1492 .noiseFloorThreshCh
= {-1, 0, 0},
1493 .ob
= {3, 3, 3}, /* 3 chain */
1494 .db_stage2
= {3, 3, 3}, /* 3 chain */
1495 .db_stage3
= {3, 3, 3}, /* doesn't exist for 2G */
1496 .db_stage4
= {3, 3, 3}, /* don't exist for 2G */
1498 .txFrameToDataStart
= 0x0e,
1499 .txFrameToPaOn
= 0x0e,
1500 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1502 .switchSettling
= 0x2d,
1503 .adcDesiredSize
= -30,
1506 .txFrameToXpaOn
= 0xe,
1508 .papdRateMaskHt20
= LE32(0x0cf0e0e0),
1509 .papdRateMaskHt40
= LE32(0x6cf0e0e0),
1511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1516 .tempSlopeHigh
= 50,
1517 .xatten1DBLow
= {0, 0, 0},
1518 .xatten1MarginLow
= {0, 0, 0},
1519 .xatten1DBHigh
= {0, 0, 0},
1520 .xatten1MarginHigh
= {0, 0, 0}
1565 .calTarget_freqbin_5G
= {
1575 .calTarget_freqbin_5GHT20
= {
1585 .calTarget_freqbin_5GHT40
= {
1595 .calTargetPower5G
= {
1597 { {30, 30, 28, 24} },
1598 { {30, 30, 28, 24} },
1599 { {30, 30, 28, 24} },
1600 { {30, 30, 28, 24} },
1601 { {30, 30, 28, 24} },
1602 { {30, 30, 28, 24} },
1603 { {30, 30, 28, 24} },
1604 { {30, 30, 28, 24} },
1606 .calTargetPower5GHT20
= {
1608 * 0_8_16,1-3_9-11_17-19,
1609 * 4,5,6,7,12,13,14,15,20,21,22,23
1611 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1612 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1613 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1614 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1615 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1616 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1617 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1618 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1620 .calTargetPower5GHT40
= {
1622 * 0_8_16,1-3_9-11_17-19,
1623 * 4,5,6,7,12,13,14,15,20,21,22,23
1625 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1626 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1627 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1628 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1629 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1630 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1631 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1632 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1635 0x10, 0x16, 0x18, 0x40, 0x46,
1636 0x48, 0x30, 0x36, 0x38
1640 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1641 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1642 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1643 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1644 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1645 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1646 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1647 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1650 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1651 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1652 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1653 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1654 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1655 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1656 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1657 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1661 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1662 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1663 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1664 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1665 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1666 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1667 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1668 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1672 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1673 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1674 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1675 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1676 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1677 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1678 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1679 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1683 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1684 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1685 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1686 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1687 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1688 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1689 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1690 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1694 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1695 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1696 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1697 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1698 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1699 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1700 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1701 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1705 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1706 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1707 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1708 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1709 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1710 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1711 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1712 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1716 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1717 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1718 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1719 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1720 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1721 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1722 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1723 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1727 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1728 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1729 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1730 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1731 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1732 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1733 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1734 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1737 .ctlPowerData_5G
= {
1740 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1741 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1746 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1747 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1752 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1753 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1758 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1759 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1764 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1765 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1770 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1771 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1776 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1777 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1782 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1783 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1788 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1789 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1796 static const struct ar9300_eeprom ar9300_x112
= {
1798 .templateVersion
= 5,
1799 .macAddr
= {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1800 .custData
= {"x112-041-f0000"},
1802 .regDmn
= { LE16(0), LE16(0x1f) },
1803 .txrxMask
= 0x77, /* 4 bits tx and 4 bits rx */
1805 .opFlags
= AR9300_OPFLAGS_11G
| AR9300_OPFLAGS_11A
,
1809 .blueToothOptions
= 0,
1811 .deviceType
= 5, /* takes lower byte in eeprom location */
1812 .pwrTableOffset
= AR9300_PWR_TABLE_OFFSET
,
1813 .params_for_tuning_caps
= {0, 0},
1814 .featureEnable
= 0x0d,
1816 * bit0 - enable tx temp comp - disabled
1817 * bit1 - enable tx volt comp - disabled
1818 * bit2 - enable fastclock - enabled
1819 * bit3 - enable doubling - enabled
1820 * bit4 - enable internal regulator - disabled
1821 * bit5 - enable pa predistortion - disabled
1823 .miscConfiguration
= 0, /* bit0 - turn down drivestrength */
1824 .eepromWriteEnableGpio
= 6,
1825 .wlanDisableGpio
= 0,
1827 .rxBandSelectGpio
= 0xff,
1832 /* ar9300_modal_eep_header 2g */
1833 /* 4 idle,t1,t2,b(4 bits per setting) */
1834 .antCtrlCommon
= LE32(0x110),
1835 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1836 .antCtrlCommon2
= LE32(0x22222),
1839 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1840 * rx1, rx12, b (2 bits each)
1842 .antCtrlChain
= { LE16(0x10), LE16(0x10), LE16(0x10) },
1845 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1846 * for ar9280 (0xa20c/b20c 5:0)
1848 .xatten1DB
= {0x1b, 0x1b, 0x1b},
1851 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1852 * for ar9280 (0xa20c/b20c 16:12
1854 .xatten1Margin
= {0x15, 0x15, 0x15},
1859 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1860 * channels in usual fbin coding format
1862 .spurChans
= {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1865 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1866 * if the register is per chain
1868 .noiseFloorThreshCh
= {-1, 0, 0},
1869 .ob
= {1, 1, 1},/* 3 chain */
1870 .db_stage2
= {1, 1, 1}, /* 3 chain */
1871 .db_stage3
= {0, 0, 0},
1872 .db_stage4
= {0, 0, 0},
1874 .txFrameToDataStart
= 0x0e,
1875 .txFrameToPaOn
= 0x0e,
1876 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1878 .switchSettling
= 0x2c,
1879 .adcDesiredSize
= -30,
1882 .txFrameToXpaOn
= 0xe,
1884 .papdRateMaskHt20
= LE32(0x0c80c080),
1885 .papdRateMaskHt40
= LE32(0x0080c080),
1887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1891 .ant_div_control
= 0,
1892 .future
= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1899 /* ar9300_cal_data_per_freq_op_loop 2g */
1901 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1902 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1903 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1905 .calTarget_freqbin_Cck
= {
1909 .calTarget_freqbin_2G
= {
1914 .calTarget_freqbin_2GHT20
= {
1919 .calTarget_freqbin_2GHT40
= {
1924 .calTargetPowerCck
= {
1925 /* 1L-5L,5S,11L,11s */
1926 { {38, 38, 38, 38} },
1927 { {38, 38, 38, 38} },
1929 .calTargetPower2G
= {
1931 { {38, 38, 36, 34} },
1932 { {38, 38, 36, 34} },
1933 { {38, 38, 34, 32} },
1935 .calTargetPower2GHT20
= {
1936 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1937 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1938 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1940 .calTargetPower2GHT40
= {
1941 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1942 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1943 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1946 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1947 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1977 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1978 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1979 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1980 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1984 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1985 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1986 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1991 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1998 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1999 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2000 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2001 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2005 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2006 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2007 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2011 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2012 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2013 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2018 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2019 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2020 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2025 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2026 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2027 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2028 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2031 .ctlPowerData_2G
= {
2032 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2033 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2034 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2036 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2037 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2038 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2040 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2041 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2042 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2044 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2045 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2046 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2049 /* 4 idle,t1,t2,b (4 bits per setting) */
2050 .antCtrlCommon
= LE32(0x110),
2051 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2052 .antCtrlCommon2
= LE32(0x22222),
2053 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2055 LE16(0x0), LE16(0x0), LE16(0x0),
2057 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2058 .xatten1DB
= {0x13, 0x19, 0x17},
2061 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2062 * for merlin (0xa20c/b20c 16:12
2064 .xatten1Margin
= {0x19, 0x19, 0x19},
2067 /* spurChans spur channels in usual fbin coding format */
2068 .spurChans
= {0, 0, 0, 0, 0},
2069 /* noiseFloorThreshch check if the register is per chain */
2070 .noiseFloorThreshCh
= {-1, 0, 0},
2071 .ob
= {3, 3, 3}, /* 3 chain */
2072 .db_stage2
= {3, 3, 3}, /* 3 chain */
2073 .db_stage3
= {3, 3, 3}, /* doesn't exist for 2G */
2074 .db_stage4
= {3, 3, 3}, /* don't exist for 2G */
2076 .txFrameToDataStart
= 0x0e,
2077 .txFrameToPaOn
= 0x0e,
2078 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2080 .switchSettling
= 0x2d,
2081 .adcDesiredSize
= -30,
2084 .txFrameToXpaOn
= 0xe,
2086 .papdRateMaskHt20
= LE32(0x0cf0e0e0),
2087 .papdRateMaskHt40
= LE32(0x6cf0e0e0),
2089 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2094 .tempSlopeHigh
= 105,
2095 .xatten1DBLow
= {0x10, 0x14, 0x10},
2096 .xatten1MarginLow
= {0x19, 0x19 , 0x19},
2097 .xatten1DBHigh
= {0x1d, 0x20, 0x24},
2098 .xatten1MarginHigh
= {0x10, 0x10, 0x10}
2143 .calTarget_freqbin_5G
= {
2153 .calTarget_freqbin_5GHT20
= {
2163 .calTarget_freqbin_5GHT40
= {
2173 .calTargetPower5G
= {
2175 { {32, 32, 28, 26} },
2176 { {32, 32, 28, 26} },
2177 { {32, 32, 28, 26} },
2178 { {32, 32, 26, 24} },
2179 { {32, 32, 26, 24} },
2180 { {32, 32, 24, 22} },
2181 { {30, 30, 24, 22} },
2182 { {30, 30, 24, 22} },
2184 .calTargetPower5GHT20
= {
2186 * 0_8_16,1-3_9-11_17-19,
2187 * 4,5,6,7,12,13,14,15,20,21,22,23
2189 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2190 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2191 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2192 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2193 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2194 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2195 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2196 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2198 .calTargetPower5GHT40
= {
2200 * 0_8_16,1-3_9-11_17-19,
2201 * 4,5,6,7,12,13,14,15,20,21,22,23
2203 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2204 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2205 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2206 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2207 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2208 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2209 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2210 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2213 0x10, 0x16, 0x18, 0x40, 0x46,
2214 0x48, 0x30, 0x36, 0x38
2218 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2219 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2220 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2221 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2222 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2223 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2224 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2225 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2228 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2231 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2232 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2233 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2234 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2235 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2239 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2241 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2242 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2243 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2244 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2245 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2246 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2250 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2253 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2254 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2256 /* Data[3].ctledges[6].bchannel */ 0xFF,
2257 /* Data[3].ctledges[7].bchannel */ 0xFF,
2261 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2264 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2265 /* Data[4].ctledges[4].bchannel */ 0xFF,
2266 /* Data[4].ctledges[5].bchannel */ 0xFF,
2267 /* Data[4].ctledges[6].bchannel */ 0xFF,
2268 /* Data[4].ctledges[7].bchannel */ 0xFF,
2272 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2274 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2275 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2277 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278 /* Data[5].ctledges[6].bchannel */ 0xFF,
2279 /* Data[5].ctledges[7].bchannel */ 0xFF
2283 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2284 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2285 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2286 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2287 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2288 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2289 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2290 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2294 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2295 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2296 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2297 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2298 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2299 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2300 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2301 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2305 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2306 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2307 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2308 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2309 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2310 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2311 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2312 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2315 .ctlPowerData_5G
= {
2318 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2319 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2324 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2325 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2330 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2331 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2336 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2337 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2342 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2343 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2348 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2349 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2354 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2355 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2360 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2361 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2366 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2367 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2373 static const struct ar9300_eeprom ar9300_h116
= {
2375 .templateVersion
= 4,
2376 .macAddr
= {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2377 .custData
= {"h116-041-f0000"},
2379 .regDmn
= { LE16(0), LE16(0x1f) },
2380 .txrxMask
= 0x33, /* 4 bits tx and 4 bits rx */
2382 .opFlags
= AR9300_OPFLAGS_11G
| AR9300_OPFLAGS_11A
,
2386 .blueToothOptions
= 0,
2388 .deviceType
= 5, /* takes lower byte in eeprom location */
2389 .pwrTableOffset
= AR9300_PWR_TABLE_OFFSET
,
2390 .params_for_tuning_caps
= {0, 0},
2391 .featureEnable
= 0x0d,
2393 * bit0 - enable tx temp comp - disabled
2394 * bit1 - enable tx volt comp - disabled
2395 * bit2 - enable fastClock - enabled
2396 * bit3 - enable doubling - enabled
2397 * bit4 - enable internal regulator - disabled
2398 * bit5 - enable pa predistortion - disabled
2400 .miscConfiguration
= 0, /* bit0 - turn down drivestrength */
2401 .eepromWriteEnableGpio
= 6,
2402 .wlanDisableGpio
= 0,
2404 .rxBandSelectGpio
= 0xff,
2409 /* ar9300_modal_eep_header 2g */
2410 /* 4 idle,t1,t2,b(4 bits per setting) */
2411 .antCtrlCommon
= LE32(0x110),
2412 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2413 .antCtrlCommon2
= LE32(0x44444),
2416 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2417 * rx1, rx12, b (2 bits each)
2419 .antCtrlChain
= { LE16(0x10), LE16(0x10), LE16(0x10) },
2422 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2423 * for ar9280 (0xa20c/b20c 5:0)
2425 .xatten1DB
= {0x1f, 0x1f, 0x1f},
2428 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2429 * for ar9280 (0xa20c/b20c 16:12
2431 .xatten1Margin
= {0x12, 0x12, 0x12},
2436 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2437 * channels in usual fbin coding format
2439 .spurChans
= {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2442 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2443 * if the register is per chain
2445 .noiseFloorThreshCh
= {-1, 0, 0},
2446 .ob
= {1, 1, 1},/* 3 chain */
2447 .db_stage2
= {1, 1, 1}, /* 3 chain */
2448 .db_stage3
= {0, 0, 0},
2449 .db_stage4
= {0, 0, 0},
2451 .txFrameToDataStart
= 0x0e,
2452 .txFrameToPaOn
= 0x0e,
2453 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2455 .switchSettling
= 0x2c,
2456 .adcDesiredSize
= -30,
2459 .txFrameToXpaOn
= 0xe,
2461 .papdRateMaskHt20
= LE32(0x0c80C080),
2462 .papdRateMaskHt40
= LE32(0x0080C080),
2464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468 .ant_div_control
= 0,
2469 .future
= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2476 /* ar9300_cal_data_per_freq_op_loop 2g */
2478 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2479 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2480 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2482 .calTarget_freqbin_Cck
= {
2486 .calTarget_freqbin_2G
= {
2491 .calTarget_freqbin_2GHT20
= {
2496 .calTarget_freqbin_2GHT40
= {
2501 .calTargetPowerCck
= {
2502 /* 1L-5L,5S,11L,11S */
2503 { {34, 34, 34, 34} },
2504 { {34, 34, 34, 34} },
2506 .calTargetPower2G
= {
2508 { {34, 34, 32, 32} },
2509 { {34, 34, 32, 32} },
2510 { {34, 34, 32, 32} },
2512 .calTargetPower2GHT20
= {
2513 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2514 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2515 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2517 .calTargetPower2GHT40
= {
2518 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2519 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2520 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2523 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2524 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2554 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2555 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2556 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2557 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2561 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2568 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2575 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2576 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2577 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2578 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2582 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2583 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2584 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2588 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2589 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2590 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2595 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2596 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2597 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2602 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2603 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2604 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2605 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2608 .ctlPowerData_2G
= {
2609 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2610 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2611 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2613 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2614 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2615 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2617 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2618 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2619 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2621 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2622 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2623 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2626 /* 4 idle,t1,t2,b (4 bits per setting) */
2627 .antCtrlCommon
= LE32(0x220),
2628 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2629 .antCtrlCommon2
= LE32(0x44444),
2630 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2632 LE16(0x150), LE16(0x150), LE16(0x150),
2634 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2635 .xatten1DB
= {0x19, 0x19, 0x19},
2638 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2639 * for merlin (0xa20c/b20c 16:12
2641 .xatten1Margin
= {0x14, 0x14, 0x14},
2644 /* spurChans spur channels in usual fbin coding format */
2645 .spurChans
= {0, 0, 0, 0, 0},
2646 /* noiseFloorThreshCh Check if the register is per chain */
2647 .noiseFloorThreshCh
= {-1, 0, 0},
2648 .ob
= {3, 3, 3}, /* 3 chain */
2649 .db_stage2
= {3, 3, 3}, /* 3 chain */
2650 .db_stage3
= {3, 3, 3}, /* doesn't exist for 2G */
2651 .db_stage4
= {3, 3, 3}, /* don't exist for 2G */
2653 .txFrameToDataStart
= 0x0e,
2654 .txFrameToPaOn
= 0x0e,
2655 .txClip
= 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2657 .switchSettling
= 0x2d,
2658 .adcDesiredSize
= -30,
2661 .txFrameToXpaOn
= 0xe,
2663 .papdRateMaskHt20
= LE32(0x0cf0e0e0),
2664 .papdRateMaskHt40
= LE32(0x6cf0e0e0),
2666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2671 .tempSlopeHigh
= 50,
2672 .xatten1DBLow
= {0, 0, 0},
2673 .xatten1MarginLow
= {0, 0, 0},
2674 .xatten1DBHigh
= {0, 0, 0},
2675 .xatten1MarginHigh
= {0, 0, 0}
2720 .calTarget_freqbin_5G
= {
2730 .calTarget_freqbin_5GHT20
= {
2740 .calTarget_freqbin_5GHT40
= {
2750 .calTargetPower5G
= {
2752 { {30, 30, 28, 24} },
2753 { {30, 30, 28, 24} },
2754 { {30, 30, 28, 24} },
2755 { {30, 30, 28, 24} },
2756 { {30, 30, 28, 24} },
2757 { {30, 30, 28, 24} },
2758 { {30, 30, 28, 24} },
2759 { {30, 30, 28, 24} },
2761 .calTargetPower5GHT20
= {
2763 * 0_8_16,1-3_9-11_17-19,
2764 * 4,5,6,7,12,13,14,15,20,21,22,23
2766 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2767 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2768 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2769 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2770 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2771 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2772 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2773 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2775 .calTargetPower5GHT40
= {
2777 * 0_8_16,1-3_9-11_17-19,
2778 * 4,5,6,7,12,13,14,15,20,21,22,23
2780 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2781 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2782 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2783 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2784 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2785 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2786 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2787 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2790 0x10, 0x16, 0x18, 0x40, 0x46,
2791 0x48, 0x30, 0x36, 0x38
2795 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2796 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2797 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2798 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2799 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2800 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2801 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2802 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2805 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2806 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2807 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2808 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2809 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2810 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2811 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2812 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2816 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2817 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2818 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2819 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2820 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2821 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2822 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2823 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2827 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2828 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2829 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2830 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2831 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2832 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2833 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2834 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2838 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2839 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2840 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2841 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2842 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2843 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2844 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2845 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2849 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2850 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2851 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2852 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2853 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2854 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2855 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2856 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2860 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2861 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2862 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2863 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2864 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2865 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2866 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2867 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2871 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2872 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2873 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2874 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2875 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2876 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2877 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2878 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2882 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2883 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2884 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2885 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2886 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2887 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2888 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2889 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2892 .ctlPowerData_5G
= {
2895 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2896 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2901 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2902 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2907 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2908 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2913 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2914 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2919 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2920 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2925 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2926 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2931 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2932 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2937 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2938 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2943 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2944 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2951 static const struct ar9300_eeprom
*ar9300_eep_templates
[] = {
2959 static const struct ar9300_eeprom
*ar9003_eeprom_struct_find_by_id(int id
)
2961 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2964 for (it
= 0; it
< N_LOOP
; it
++)
2965 if (ar9300_eep_templates
[it
]->templateVersion
== id
)
2966 return ar9300_eep_templates
[it
];
2972 static u16
ath9k_hw_fbin2freq(u8 fbin
, bool is2GHz
)
2974 if (fbin
== AR9300_BCHAN_UNUSED
)
2977 return (u16
) ((is2GHz
) ? (2300 + fbin
) : (4800 + 5 * fbin
));
2980 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw
*ah
)
2985 static int interpolate(int x
, int xa
, int xb
, int ya
, int yb
)
2987 int bf
, factor
, plus
;
2989 bf
= 2 * (yb
- ya
) * (x
- xa
) / (xb
- xa
);
2992 return ya
+ factor
+ plus
;
2995 static u32
ath9k_hw_ar9300_get_eeprom(struct ath_hw
*ah
,
2996 enum eeprom_param param
)
2998 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
2999 struct ar9300_base_eep_hdr
*pBase
= &eep
->baseEepHeader
;
3003 return eep
->macAddr
[0] << 8 | eep
->macAddr
[1];
3005 return eep
->macAddr
[2] << 8 | eep
->macAddr
[3];
3007 return eep
->macAddr
[4] << 8 | eep
->macAddr
[5];
3009 return le16_to_cpu(pBase
->regDmn
[0]);
3011 return le16_to_cpu(pBase
->regDmn
[1]);
3013 return pBase
->deviceCap
;
3015 return pBase
->opCapFlags
.opFlags
;
3017 return pBase
->rfSilent
;
3019 return (pBase
->txrxMask
>> 4) & 0xf;
3021 return pBase
->txrxMask
& 0xf;
3022 case EEP_DRIVE_STRENGTH
:
3023 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3024 return pBase
->miscConfiguration
& AR9300_EEP_BASE_DRIV_STRENGTH
;
3025 case EEP_INTERNAL_REGULATOR
:
3026 /* Bit 4 is internal regulator flag */
3027 return (pBase
->featureEnable
& 0x10) >> 4;
3029 return le32_to_cpu(pBase
->swreg
);
3031 return !!(pBase
->featureEnable
& BIT(5));
3037 static bool ar9300_eeprom_read_byte(struct ath_common
*common
, int address
,
3042 if (unlikely(!ath9k_hw_nvram_read(common
, address
/ 2, &val
)))
3045 *buffer
= (val
>> (8 * (address
% 2))) & 0xff;
3049 static bool ar9300_eeprom_read_word(struct ath_common
*common
, int address
,
3054 if (unlikely(!ath9k_hw_nvram_read(common
, address
/ 2, &val
)))
3057 buffer
[0] = val
>> 8;
3058 buffer
[1] = val
& 0xff;
3063 static bool ar9300_read_eeprom(struct ath_hw
*ah
, int address
, u8
*buffer
,
3066 struct ath_common
*common
= ath9k_hw_common(ah
);
3069 if ((address
< 0) || ((address
+ count
) / 2 > AR9300_EEPROM_SIZE
- 1)) {
3070 ath_print(common
, ATH_DBG_EEPROM
,
3071 "eeprom address not in range\n");
3076 * Since we're reading the bytes in reverse order from a little-endian
3077 * word stream, an even address means we only use the lower half of
3078 * the 16-bit word at that address
3080 if (address
% 2 == 0) {
3081 if (!ar9300_eeprom_read_byte(common
, address
--, buffer
++))
3087 for (i
= 0; i
< count
/ 2; i
++) {
3088 if (!ar9300_eeprom_read_word(common
, address
, buffer
))
3096 if (!ar9300_eeprom_read_byte(common
, address
, buffer
))
3102 ath_print(common
, ATH_DBG_EEPROM
,
3103 "unable to read eeprom region at offset %d\n", address
);
3107 static bool ar9300_otp_read_word(struct ath_hw
*ah
, int addr
, u32
*data
)
3109 REG_READ(ah
, AR9300_OTP_BASE
+ (4 * addr
));
3111 if (!ath9k_hw_wait(ah
, AR9300_OTP_STATUS
, AR9300_OTP_STATUS_TYPE
,
3112 AR9300_OTP_STATUS_VALID
, 1000))
3115 *data
= REG_READ(ah
, AR9300_OTP_READ_DATA
);
3119 static bool ar9300_read_otp(struct ath_hw
*ah
, int address
, u8
*buffer
,
3125 for (i
= 0; i
< count
; i
++) {
3126 int offset
= 8 * ((address
- i
) % 4);
3127 if (!ar9300_otp_read_word(ah
, (address
- i
) / 4, &data
))
3130 buffer
[i
] = (data
>> offset
) & 0xff;
3137 static void ar9300_comp_hdr_unpack(u8
*best
, int *code
, int *reference
,
3138 int *length
, int *major
, int *minor
)
3140 unsigned long value
[4];
3146 *code
= ((value
[0] >> 5) & 0x0007);
3147 *reference
= (value
[0] & 0x001f) | ((value
[1] >> 2) & 0x0020);
3148 *length
= ((value
[1] << 4) & 0x07f0) | ((value
[2] >> 4) & 0x000f);
3149 *major
= (value
[2] & 0x000f);
3150 *minor
= (value
[3] & 0x00ff);
3153 static u16
ar9300_comp_cksum(u8
*data
, int dsize
)
3155 int it
, checksum
= 0;
3157 for (it
= 0; it
< dsize
; it
++) {
3158 checksum
+= data
[it
];
3165 static bool ar9300_uncompress_block(struct ath_hw
*ah
,
3175 struct ath_common
*common
= ath9k_hw_common(ah
);
3179 for (it
= 0; it
< size
; it
+= (length
+2)) {
3183 length
= block
[it
+1];
3186 if (length
> 0 && spot
>= 0 && spot
+length
<= mdataSize
) {
3187 ath_print(common
, ATH_DBG_EEPROM
,
3188 "Restore at %d: spot=%d "
3189 "offset=%d length=%d\n",
3190 it
, spot
, offset
, length
);
3191 memcpy(&mptr
[spot
], &block
[it
+2], length
);
3193 } else if (length
> 0) {
3194 ath_print(common
, ATH_DBG_EEPROM
,
3195 "Bad restore at %d: spot=%d "
3196 "offset=%d length=%d\n",
3197 it
, spot
, offset
, length
);
3204 static int ar9300_compress_decision(struct ath_hw
*ah
,
3209 u8
*word
, int length
, int mdata_size
)
3211 struct ath_common
*common
= ath9k_hw_common(ah
);
3213 const struct ar9300_eeprom
*eep
= NULL
;
3217 if (length
!= mdata_size
) {
3218 ath_print(common
, ATH_DBG_EEPROM
,
3219 "EEPROM structure size mismatch"
3220 "memory=%d eeprom=%d\n", mdata_size
, length
);
3223 memcpy(mptr
, (u8
*) (word
+ COMP_HDR_LEN
), length
);
3224 ath_print(common
, ATH_DBG_EEPROM
, "restored eeprom %d:"
3225 " uncompressed, length %d\n", it
, length
);
3227 case _CompressBlock
:
3228 if (reference
== 0) {
3231 eep
= ar9003_eeprom_struct_find_by_id(reference
);
3233 ath_print(common
, ATH_DBG_EEPROM
,
3234 "cant find reference eeprom"
3235 "struct %d\n", reference
);
3238 memcpy(mptr
, eep
, mdata_size
);
3240 ath_print(common
, ATH_DBG_EEPROM
,
3241 "restore eeprom %d: block, reference %d,"
3242 " length %d\n", it
, reference
, length
);
3243 ar9300_uncompress_block(ah
, mptr
, mdata_size
,
3244 (u8
*) (word
+ COMP_HDR_LEN
), length
);
3247 ath_print(common
, ATH_DBG_EEPROM
, "unknown compression"
3248 " code %d\n", code
);
3254 typedef bool (*eeprom_read_op
)(struct ath_hw
*ah
, int address
, u8
*buffer
,
3257 static bool ar9300_check_header(void *data
)
3260 return !(*word
== 0 || *word
== ~0);
3263 static bool ar9300_check_eeprom_header(struct ath_hw
*ah
, eeprom_read_op read
,
3268 if (!read(ah
, base_addr
, header
, 4))
3271 return ar9300_check_header(header
);
3274 static int ar9300_eeprom_restore_flash(struct ath_hw
*ah
, u8
*mptr
,
3277 struct ath_common
*common
= ath9k_hw_common(ah
);
3278 u16
*data
= (u16
*) mptr
;
3281 for (i
= 0; i
< mdata_size
/ 2; i
++, data
++)
3282 ath9k_hw_nvram_read(common
, i
, data
);
3287 * Read the configuration data from the eeprom.
3288 * The data can be put in any specified memory buffer.
3290 * Returns -1 on error.
3291 * Returns address of next memory location on success.
3293 static int ar9300_eeprom_restore_internal(struct ath_hw
*ah
,
3294 u8
*mptr
, int mdata_size
)
3301 int reference
, length
, major
, minor
;
3304 u16 checksum
, mchecksum
;
3305 struct ath_common
*common
= ath9k_hw_common(ah
);
3306 eeprom_read_op read
;
3308 if (ath9k_hw_use_flash(ah
))
3309 return ar9300_eeprom_restore_flash(ah
, mptr
, mdata_size
);
3311 word
= kzalloc(2048, GFP_KERNEL
);
3315 memcpy(mptr
, &ar9300_default
, mdata_size
);
3317 read
= ar9300_read_eeprom
;
3318 cptr
= AR9300_BASE_ADDR
;
3319 ath_print(common
, ATH_DBG_EEPROM
,
3320 "Trying EEPROM accesss at Address 0x%04x\n", cptr
);
3321 if (ar9300_check_eeprom_header(ah
, read
, cptr
))
3324 cptr
= AR9300_BASE_ADDR_512
;
3325 ath_print(common
, ATH_DBG_EEPROM
,
3326 "Trying EEPROM accesss at Address 0x%04x\n", cptr
);
3327 if (ar9300_check_eeprom_header(ah
, read
, cptr
))
3330 read
= ar9300_read_otp
;
3331 cptr
= AR9300_BASE_ADDR
;
3332 ath_print(common
, ATH_DBG_EEPROM
,
3333 "Trying OTP accesss at Address 0x%04x\n", cptr
);
3334 if (ar9300_check_eeprom_header(ah
, read
, cptr
))
3337 cptr
= AR9300_BASE_ADDR_512
;
3338 ath_print(common
, ATH_DBG_EEPROM
,
3339 "Trying OTP accesss at Address 0x%04x\n", cptr
);
3340 if (ar9300_check_eeprom_header(ah
, read
, cptr
))
3346 ath_print(common
, ATH_DBG_EEPROM
, "Found valid EEPROM data");
3348 for (it
= 0; it
< MSTATE
; it
++) {
3349 if (!read(ah
, cptr
, word
, COMP_HDR_LEN
))
3352 if (!ar9300_check_header(word
))
3355 ar9300_comp_hdr_unpack(word
, &code
, &reference
,
3356 &length
, &major
, &minor
);
3357 ath_print(common
, ATH_DBG_EEPROM
,
3358 "Found block at %x: code=%d ref=%d"
3359 "length=%d major=%d minor=%d\n", cptr
, code
,
3360 reference
, length
, major
, minor
);
3361 if (length
>= 1024) {
3362 ath_print(common
, ATH_DBG_EEPROM
,
3363 "Skipping bad header\n");
3364 cptr
-= COMP_HDR_LEN
;
3369 read(ah
, cptr
, word
, COMP_HDR_LEN
+ osize
+ COMP_CKSUM_LEN
);
3370 checksum
= ar9300_comp_cksum(&word
[COMP_HDR_LEN
], length
);
3371 mchecksum
= word
[COMP_HDR_LEN
+ osize
] |
3372 (word
[COMP_HDR_LEN
+ osize
+ 1] << 8);
3373 ath_print(common
, ATH_DBG_EEPROM
,
3374 "checksum %x %x\n", checksum
, mchecksum
);
3375 if (checksum
== mchecksum
) {
3376 ar9300_compress_decision(ah
, it
, code
, reference
, mptr
,
3377 word
, length
, mdata_size
);
3379 ath_print(common
, ATH_DBG_EEPROM
,
3380 "skipping block with bad checksum\n");
3382 cptr
-= (COMP_HDR_LEN
+ osize
+ COMP_CKSUM_LEN
);
3394 * Restore the configuration structure by reading the eeprom.
3395 * This function destroys any existing in-memory structure
3398 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw
*ah
)
3400 u8
*mptr
= (u8
*) &ah
->eeprom
.ar9300_eep
;
3402 if (ar9300_eeprom_restore_internal(ah
, mptr
,
3403 sizeof(struct ar9300_eeprom
)) < 0)
3409 /* XXX: review hardware docs */
3410 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw
*ah
)
3412 return ah
->eeprom
.ar9300_eep
.eepromVersion
;
3415 /* XXX: could be read from the eepromVersion, not sure yet */
3416 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw
*ah
)
3421 static u8
ath9k_hw_ar9300_get_num_ant_config(struct ath_hw
*ah
,
3422 enum ath9k_hal_freq_band freq_band
)
3427 static u32
ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw
*ah
,
3428 struct ath9k_channel
*chan
)
3433 static s32
ar9003_hw_xpa_bias_level_get(struct ath_hw
*ah
, bool is2ghz
)
3435 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3438 return eep
->modalHeader2G
.xpaBiasLvl
;
3440 return eep
->modalHeader5G
.xpaBiasLvl
;
3443 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw
*ah
, bool is2ghz
)
3445 int bias
= ar9003_hw_xpa_bias_level_get(ah
, is2ghz
);
3446 REG_RMW_FIELD(ah
, AR_CH0_TOP
, AR_CH0_TOP_XPABIASLVL
, bias
);
3447 REG_RMW_FIELD(ah
, AR_CH0_THERM
, AR_CH0_THERM_XPABIASLVL_MSB
, bias
>> 2);
3448 REG_RMW_FIELD(ah
, AR_CH0_THERM
, AR_CH0_THERM_XPASHORT2GND
, 1);
3451 static u32
ar9003_hw_ant_ctrl_common_get(struct ath_hw
*ah
, bool is2ghz
)
3453 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3457 val
= eep
->modalHeader2G
.antCtrlCommon
;
3459 val
= eep
->modalHeader5G
.antCtrlCommon
;
3460 return le32_to_cpu(val
);
3463 static u32
ar9003_hw_ant_ctrl_common_2_get(struct ath_hw
*ah
, bool is2ghz
)
3465 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3469 val
= eep
->modalHeader2G
.antCtrlCommon2
;
3471 val
= eep
->modalHeader5G
.antCtrlCommon2
;
3472 return le32_to_cpu(val
);
3475 static u16
ar9003_hw_ant_ctrl_chain_get(struct ath_hw
*ah
,
3479 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3482 if (chain
>= 0 && chain
< AR9300_MAX_CHAINS
) {
3484 val
= eep
->modalHeader2G
.antCtrlChain
[chain
];
3486 val
= eep
->modalHeader5G
.antCtrlChain
[chain
];
3489 return le16_to_cpu(val
);
3492 static void ar9003_hw_ant_ctrl_apply(struct ath_hw
*ah
, bool is2ghz
)
3494 u32 value
= ar9003_hw_ant_ctrl_common_get(ah
, is2ghz
);
3495 REG_RMW_FIELD(ah
, AR_PHY_SWITCH_COM
, AR_SWITCH_TABLE_COM_ALL
, value
);
3497 value
= ar9003_hw_ant_ctrl_common_2_get(ah
, is2ghz
);
3498 REG_RMW_FIELD(ah
, AR_PHY_SWITCH_COM_2
, AR_SWITCH_TABLE_COM2_ALL
, value
);
3500 value
= ar9003_hw_ant_ctrl_chain_get(ah
, 0, is2ghz
);
3501 REG_RMW_FIELD(ah
, AR_PHY_SWITCH_CHAIN_0
, AR_SWITCH_TABLE_ALL
, value
);
3503 value
= ar9003_hw_ant_ctrl_chain_get(ah
, 1, is2ghz
);
3504 REG_RMW_FIELD(ah
, AR_PHY_SWITCH_CHAIN_1
, AR_SWITCH_TABLE_ALL
, value
);
3506 value
= ar9003_hw_ant_ctrl_chain_get(ah
, 2, is2ghz
);
3507 REG_RMW_FIELD(ah
, AR_PHY_SWITCH_CHAIN_2
, AR_SWITCH_TABLE_ALL
, value
);
3510 static void ar9003_hw_drive_strength_apply(struct ath_hw
*ah
)
3515 drive_strength
= ath9k_hw_ar9300_get_eeprom(ah
, EEP_DRIVE_STRENGTH
);
3517 if (!drive_strength
)
3520 reg
= REG_READ(ah
, AR_PHY_65NM_CH0_BIAS1
);
3528 REG_WRITE(ah
, AR_PHY_65NM_CH0_BIAS1
, reg
);
3530 reg
= REG_READ(ah
, AR_PHY_65NM_CH0_BIAS2
);
3541 REG_WRITE(ah
, AR_PHY_65NM_CH0_BIAS2
, reg
);
3543 reg
= REG_READ(ah
, AR_PHY_65NM_CH0_BIAS4
);
3548 REG_WRITE(ah
, AR_PHY_65NM_CH0_BIAS4
, reg
);
3551 static u16
ar9003_hw_atten_chain_get(struct ath_hw
*ah
, int chain
,
3552 struct ath9k_channel
*chan
)
3556 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3558 if (chain
>= 0 && chain
< 3) {
3559 if (IS_CHAN_2GHZ(chan
))
3560 return eep
->modalHeader2G
.xatten1DB
[chain
];
3561 else if (eep
->base_ext2
.xatten1DBLow
[chain
] != 0) {
3562 t
[0] = eep
->base_ext2
.xatten1DBLow
[chain
];
3564 t
[1] = eep
->modalHeader5G
.xatten1DB
[chain
];
3566 t
[2] = eep
->base_ext2
.xatten1DBHigh
[chain
];
3568 value
= ar9003_hw_power_interpolate((s32
) chan
->channel
,
3572 return eep
->modalHeader5G
.xatten1DB
[chain
];
3579 static u16
ar9003_hw_atten_chain_get_margin(struct ath_hw
*ah
, int chain
,
3580 struct ath9k_channel
*chan
)
3584 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3586 if (chain
>= 0 && chain
< 3) {
3587 if (IS_CHAN_2GHZ(chan
))
3588 return eep
->modalHeader2G
.xatten1Margin
[chain
];
3589 else if (eep
->base_ext2
.xatten1MarginLow
[chain
] != 0) {
3590 t
[0] = eep
->base_ext2
.xatten1MarginLow
[chain
];
3592 t
[1] = eep
->modalHeader5G
.xatten1Margin
[chain
];
3594 t
[2] = eep
->base_ext2
.xatten1MarginHigh
[chain
];
3596 value
= ar9003_hw_power_interpolate((s32
) chan
->channel
,
3600 return eep
->modalHeader5G
.xatten1Margin
[chain
];
3606 static void ar9003_hw_atten_apply(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
3610 unsigned long ext_atten_reg
[3] = {AR_PHY_EXT_ATTEN_CTL_0
,
3611 AR_PHY_EXT_ATTEN_CTL_1
,
3612 AR_PHY_EXT_ATTEN_CTL_2
,
3615 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3616 for (i
= 0; i
< 3; i
++) {
3617 value
= ar9003_hw_atten_chain_get(ah
, i
, chan
);
3618 REG_RMW_FIELD(ah
, ext_atten_reg
[i
],
3619 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB
, value
);
3621 value
= ar9003_hw_atten_chain_get_margin(ah
, i
, chan
);
3622 REG_RMW_FIELD(ah
, ext_atten_reg
[i
],
3623 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN
, value
);
3627 static void ar9003_hw_internal_regulator_apply(struct ath_hw
*ah
)
3629 int internal_regulator
=
3630 ath9k_hw_ar9300_get_eeprom(ah
, EEP_INTERNAL_REGULATOR
);
3632 if (internal_regulator
) {
3633 /* Internal regulator is ON. Write swreg register. */
3634 int swreg
= ath9k_hw_ar9300_get_eeprom(ah
, EEP_SWREG
);
3635 REG_WRITE(ah
, AR_RTC_REG_CONTROL1
,
3636 REG_READ(ah
, AR_RTC_REG_CONTROL1
) &
3637 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM
));
3638 REG_WRITE(ah
, AR_RTC_REG_CONTROL0
, swreg
);
3639 /* Set REG_CONTROL1.SWREG_PROGRAM */
3640 REG_WRITE(ah
, AR_RTC_REG_CONTROL1
,
3642 AR_RTC_REG_CONTROL1
) |
3643 AR_RTC_REG_CONTROL1_SWREG_PROGRAM
);
3645 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
,
3648 AR_RTC_FORCE_SWREG_PRD
));
3652 static void ath9k_hw_ar9300_set_board_values(struct ath_hw
*ah
,
3653 struct ath9k_channel
*chan
)
3655 ar9003_hw_xpa_bias_level_apply(ah
, IS_CHAN_2GHZ(chan
));
3656 ar9003_hw_ant_ctrl_apply(ah
, IS_CHAN_2GHZ(chan
));
3657 ar9003_hw_drive_strength_apply(ah
);
3658 ar9003_hw_atten_apply(ah
, chan
);
3659 ar9003_hw_internal_regulator_apply(ah
);
3662 static void ath9k_hw_ar9300_set_addac(struct ath_hw
*ah
,
3663 struct ath9k_channel
*chan
)
3668 * Returns the interpolated y value corresponding to the specified x value
3669 * from the np ordered pairs of data (px,py).
3670 * The pairs do not have to be in any order.
3671 * If the specified x value is less than any of the px,
3672 * the returned y value is equal to the py for the lowest px.
3673 * If the specified x value is greater than any of the px,
3674 * the returned y value is equal to the py for the highest px.
3676 static int ar9003_hw_power_interpolate(int32_t x
,
3677 int32_t *px
, int32_t *py
, u_int16_t np
)
3680 int lx
= 0, ly
= 0, lhave
= 0;
3681 int hx
= 0, hy
= 0, hhave
= 0;
3688 /* identify best lower and higher x calibration measurement */
3689 for (ip
= 0; ip
< np
; ip
++) {
3692 /* this measurement is higher than our desired x */
3694 if (!hhave
|| dx
> (x
- hx
)) {
3695 /* new best higher x measurement */
3701 /* this measurement is lower than our desired x */
3703 if (!lhave
|| dx
< (x
- lx
)) {
3704 /* new best lower x measurement */
3712 /* the low x is good */
3714 /* so is the high x */
3716 /* they're the same, so just pick one */
3719 else /* interpolate */
3720 y
= interpolate(x
, lx
, hx
, ly
, hy
);
3721 } else /* only low is good, use it */
3723 } else if (hhave
) /* only high is good, use it */
3725 else /* nothing is good,this should never happen unless np=0, ???? */
3730 static u8
ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw
*ah
,
3731 u16 rateIndex
, u16 freq
, bool is2GHz
)
3734 s32 targetPowerArray
[AR9300_NUM_5G_20_TARGET_POWERS
];
3735 s32 freqArray
[AR9300_NUM_5G_20_TARGET_POWERS
];
3736 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3737 struct cal_tgt_pow_legacy
*pEepromTargetPwr
;
3741 numPiers
= AR9300_NUM_2G_20_TARGET_POWERS
;
3742 pEepromTargetPwr
= eep
->calTargetPower2G
;
3743 pFreqBin
= eep
->calTarget_freqbin_2G
;
3745 numPiers
= AR9300_NUM_5G_20_TARGET_POWERS
;
3746 pEepromTargetPwr
= eep
->calTargetPower5G
;
3747 pFreqBin
= eep
->calTarget_freqbin_5G
;
3751 * create array of channels and targetpower from
3752 * targetpower piers stored on eeprom
3754 for (i
= 0; i
< numPiers
; i
++) {
3755 freqArray
[i
] = FBIN2FREQ(pFreqBin
[i
], is2GHz
);
3756 targetPowerArray
[i
] = pEepromTargetPwr
[i
].tPow2x
[rateIndex
];
3759 /* interpolate to get target power for given frequency */
3760 return (u8
) ar9003_hw_power_interpolate((s32
) freq
,
3762 targetPowerArray
, numPiers
);
3765 static u8
ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw
*ah
,
3767 u16 freq
, bool is2GHz
)
3770 s32 targetPowerArray
[AR9300_NUM_5G_20_TARGET_POWERS
];
3771 s32 freqArray
[AR9300_NUM_5G_20_TARGET_POWERS
];
3772 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3773 struct cal_tgt_pow_ht
*pEepromTargetPwr
;
3777 numPiers
= AR9300_NUM_2G_20_TARGET_POWERS
;
3778 pEepromTargetPwr
= eep
->calTargetPower2GHT20
;
3779 pFreqBin
= eep
->calTarget_freqbin_2GHT20
;
3781 numPiers
= AR9300_NUM_5G_20_TARGET_POWERS
;
3782 pEepromTargetPwr
= eep
->calTargetPower5GHT20
;
3783 pFreqBin
= eep
->calTarget_freqbin_5GHT20
;
3787 * create array of channels and targetpower
3788 * from targetpower piers stored on eeprom
3790 for (i
= 0; i
< numPiers
; i
++) {
3791 freqArray
[i
] = FBIN2FREQ(pFreqBin
[i
], is2GHz
);
3792 targetPowerArray
[i
] = pEepromTargetPwr
[i
].tPow2x
[rateIndex
];
3795 /* interpolate to get target power for given frequency */
3796 return (u8
) ar9003_hw_power_interpolate((s32
) freq
,
3798 targetPowerArray
, numPiers
);
3801 static u8
ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw
*ah
,
3803 u16 freq
, bool is2GHz
)
3806 s32 targetPowerArray
[AR9300_NUM_5G_40_TARGET_POWERS
];
3807 s32 freqArray
[AR9300_NUM_5G_40_TARGET_POWERS
];
3808 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3809 struct cal_tgt_pow_ht
*pEepromTargetPwr
;
3813 numPiers
= AR9300_NUM_2G_40_TARGET_POWERS
;
3814 pEepromTargetPwr
= eep
->calTargetPower2GHT40
;
3815 pFreqBin
= eep
->calTarget_freqbin_2GHT40
;
3817 numPiers
= AR9300_NUM_5G_40_TARGET_POWERS
;
3818 pEepromTargetPwr
= eep
->calTargetPower5GHT40
;
3819 pFreqBin
= eep
->calTarget_freqbin_5GHT40
;
3823 * create array of channels and targetpower from
3824 * targetpower piers stored on eeprom
3826 for (i
= 0; i
< numPiers
; i
++) {
3827 freqArray
[i
] = FBIN2FREQ(pFreqBin
[i
], is2GHz
);
3828 targetPowerArray
[i
] = pEepromTargetPwr
[i
].tPow2x
[rateIndex
];
3831 /* interpolate to get target power for given frequency */
3832 return (u8
) ar9003_hw_power_interpolate((s32
) freq
,
3834 targetPowerArray
, numPiers
);
3837 static u8
ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw
*ah
,
3838 u16 rateIndex
, u16 freq
)
3840 u16 numPiers
= AR9300_NUM_2G_CCK_TARGET_POWERS
, i
;
3841 s32 targetPowerArray
[AR9300_NUM_2G_CCK_TARGET_POWERS
];
3842 s32 freqArray
[AR9300_NUM_2G_CCK_TARGET_POWERS
];
3843 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
3844 struct cal_tgt_pow_legacy
*pEepromTargetPwr
= eep
->calTargetPowerCck
;
3845 u8
*pFreqBin
= eep
->calTarget_freqbin_Cck
;
3848 * create array of channels and targetpower from
3849 * targetpower piers stored on eeprom
3851 for (i
= 0; i
< numPiers
; i
++) {
3852 freqArray
[i
] = FBIN2FREQ(pFreqBin
[i
], 1);
3853 targetPowerArray
[i
] = pEepromTargetPwr
[i
].tPow2x
[rateIndex
];
3856 /* interpolate to get target power for given frequency */
3857 return (u8
) ar9003_hw_power_interpolate((s32
) freq
,
3859 targetPowerArray
, numPiers
);
3862 /* Set tx power registers to array of values passed in */
3863 static int ar9003_hw_tx_power_regwrite(struct ath_hw
*ah
, u8
* pPwrArray
)
3865 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
3866 /* make sure forced gain is not set */
3867 REG_WRITE(ah
, 0xa458, 0);
3869 /* Write the OFDM power per rate set */
3871 /* 6 (LSB), 9, 12, 18 (MSB) */
3872 REG_WRITE(ah
, 0xa3c0,
3873 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_6_24
], 24) |
3874 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_6_24
], 16) |
3875 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_6_24
], 8) |
3876 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_6_24
], 0));
3878 /* 24 (LSB), 36, 48, 54 (MSB) */
3879 REG_WRITE(ah
, 0xa3c4,
3880 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_54
], 24) |
3881 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_48
], 16) |
3882 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_36
], 8) |
3883 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_6_24
], 0));
3885 /* Write the CCK power per rate set */
3887 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3888 REG_WRITE(ah
, 0xa3c8,
3889 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_1L_5L
], 24) |
3890 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_1L_5L
], 16) |
3891 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
3892 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_1L_5L
], 0));
3894 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3895 REG_WRITE(ah
, 0xa3cc,
3896 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_11S
], 24) |
3897 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_11L
], 16) |
3898 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_5S
], 8) |
3899 POW_SM(pPwrArray
[ALL_TARGET_LEGACY_1L_5L
], 0)
3902 /* Write the HT20 power per rate set */
3904 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3905 REG_WRITE(ah
, 0xa3d0,
3906 POW_SM(pPwrArray
[ALL_TARGET_HT20_5
], 24) |
3907 POW_SM(pPwrArray
[ALL_TARGET_HT20_4
], 16) |
3908 POW_SM(pPwrArray
[ALL_TARGET_HT20_1_3_9_11_17_19
], 8) |
3909 POW_SM(pPwrArray
[ALL_TARGET_HT20_0_8_16
], 0)
3912 /* 6 (LSB), 7, 12, 13 (MSB) */
3913 REG_WRITE(ah
, 0xa3d4,
3914 POW_SM(pPwrArray
[ALL_TARGET_HT20_13
], 24) |
3915 POW_SM(pPwrArray
[ALL_TARGET_HT20_12
], 16) |
3916 POW_SM(pPwrArray
[ALL_TARGET_HT20_7
], 8) |
3917 POW_SM(pPwrArray
[ALL_TARGET_HT20_6
], 0)
3920 /* 14 (LSB), 15, 20, 21 */
3921 REG_WRITE(ah
, 0xa3e4,
3922 POW_SM(pPwrArray
[ALL_TARGET_HT20_21
], 24) |
3923 POW_SM(pPwrArray
[ALL_TARGET_HT20_20
], 16) |
3924 POW_SM(pPwrArray
[ALL_TARGET_HT20_15
], 8) |
3925 POW_SM(pPwrArray
[ALL_TARGET_HT20_14
], 0)
3928 /* Mixed HT20 and HT40 rates */
3930 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3931 REG_WRITE(ah
, 0xa3e8,
3932 POW_SM(pPwrArray
[ALL_TARGET_HT40_23
], 24) |
3933 POW_SM(pPwrArray
[ALL_TARGET_HT40_22
], 16) |
3934 POW_SM(pPwrArray
[ALL_TARGET_HT20_23
], 8) |
3935 POW_SM(pPwrArray
[ALL_TARGET_HT20_22
], 0)
3939 * Write the HT40 power per rate set
3940 * correct PAR difference between HT40 and HT20/LEGACY
3941 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
3943 REG_WRITE(ah
, 0xa3d8,
3944 POW_SM(pPwrArray
[ALL_TARGET_HT40_5
], 24) |
3945 POW_SM(pPwrArray
[ALL_TARGET_HT40_4
], 16) |
3946 POW_SM(pPwrArray
[ALL_TARGET_HT40_1_3_9_11_17_19
], 8) |
3947 POW_SM(pPwrArray
[ALL_TARGET_HT40_0_8_16
], 0)
3950 /* 6 (LSB), 7, 12, 13 (MSB) */
3951 REG_WRITE(ah
, 0xa3dc,
3952 POW_SM(pPwrArray
[ALL_TARGET_HT40_13
], 24) |
3953 POW_SM(pPwrArray
[ALL_TARGET_HT40_12
], 16) |
3954 POW_SM(pPwrArray
[ALL_TARGET_HT40_7
], 8) |
3955 POW_SM(pPwrArray
[ALL_TARGET_HT40_6
], 0)
3958 /* 14 (LSB), 15, 20, 21 */
3959 REG_WRITE(ah
, 0xa3ec,
3960 POW_SM(pPwrArray
[ALL_TARGET_HT40_21
], 24) |
3961 POW_SM(pPwrArray
[ALL_TARGET_HT40_20
], 16) |
3962 POW_SM(pPwrArray
[ALL_TARGET_HT40_15
], 8) |
3963 POW_SM(pPwrArray
[ALL_TARGET_HT40_14
], 0)
3970 static void ar9003_hw_set_target_power_eeprom(struct ath_hw
*ah
, u16 freq
,
3971 u8
*targetPowerValT2
)
3973 /* XXX: hard code for now, need to get from eeprom struct */
3974 u8 ht40PowerIncForPdadc
= 0;
3975 bool is2GHz
= false;
3977 struct ath_common
*common
= ath9k_hw_common(ah
);
3982 targetPowerValT2
[ALL_TARGET_LEGACY_6_24
] =
3983 ar9003_hw_eeprom_get_tgt_pwr(ah
, LEGACY_TARGET_RATE_6_24
, freq
,
3985 targetPowerValT2
[ALL_TARGET_LEGACY_36
] =
3986 ar9003_hw_eeprom_get_tgt_pwr(ah
, LEGACY_TARGET_RATE_36
, freq
,
3988 targetPowerValT2
[ALL_TARGET_LEGACY_48
] =
3989 ar9003_hw_eeprom_get_tgt_pwr(ah
, LEGACY_TARGET_RATE_48
, freq
,
3991 targetPowerValT2
[ALL_TARGET_LEGACY_54
] =
3992 ar9003_hw_eeprom_get_tgt_pwr(ah
, LEGACY_TARGET_RATE_54
, freq
,
3994 targetPowerValT2
[ALL_TARGET_LEGACY_1L_5L
] =
3995 ar9003_hw_eeprom_get_cck_tgt_pwr(ah
, LEGACY_TARGET_RATE_1L_5L
,
3997 targetPowerValT2
[ALL_TARGET_LEGACY_5S
] =
3998 ar9003_hw_eeprom_get_cck_tgt_pwr(ah
, LEGACY_TARGET_RATE_5S
, freq
);
3999 targetPowerValT2
[ALL_TARGET_LEGACY_11L
] =
4000 ar9003_hw_eeprom_get_cck_tgt_pwr(ah
, LEGACY_TARGET_RATE_11L
, freq
);
4001 targetPowerValT2
[ALL_TARGET_LEGACY_11S
] =
4002 ar9003_hw_eeprom_get_cck_tgt_pwr(ah
, LEGACY_TARGET_RATE_11S
, freq
);
4003 targetPowerValT2
[ALL_TARGET_HT20_0_8_16
] =
4004 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_0_8_16
, freq
,
4006 targetPowerValT2
[ALL_TARGET_HT20_1_3_9_11_17_19
] =
4007 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_1_3_9_11_17_19
,
4009 targetPowerValT2
[ALL_TARGET_HT20_4
] =
4010 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_4
, freq
,
4012 targetPowerValT2
[ALL_TARGET_HT20_5
] =
4013 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_5
, freq
,
4015 targetPowerValT2
[ALL_TARGET_HT20_6
] =
4016 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_6
, freq
,
4018 targetPowerValT2
[ALL_TARGET_HT20_7
] =
4019 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_7
, freq
,
4021 targetPowerValT2
[ALL_TARGET_HT20_12
] =
4022 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_12
, freq
,
4024 targetPowerValT2
[ALL_TARGET_HT20_13
] =
4025 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_13
, freq
,
4027 targetPowerValT2
[ALL_TARGET_HT20_14
] =
4028 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_14
, freq
,
4030 targetPowerValT2
[ALL_TARGET_HT20_15
] =
4031 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_15
, freq
,
4033 targetPowerValT2
[ALL_TARGET_HT20_20
] =
4034 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_20
, freq
,
4036 targetPowerValT2
[ALL_TARGET_HT20_21
] =
4037 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_21
, freq
,
4039 targetPowerValT2
[ALL_TARGET_HT20_22
] =
4040 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_22
, freq
,
4042 targetPowerValT2
[ALL_TARGET_HT20_23
] =
4043 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah
, HT_TARGET_RATE_23
, freq
,
4045 targetPowerValT2
[ALL_TARGET_HT40_0_8_16
] =
4046 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_0_8_16
, freq
,
4047 is2GHz
) + ht40PowerIncForPdadc
;
4048 targetPowerValT2
[ALL_TARGET_HT40_1_3_9_11_17_19
] =
4049 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_1_3_9_11_17_19
,
4051 is2GHz
) + ht40PowerIncForPdadc
;
4052 targetPowerValT2
[ALL_TARGET_HT40_4
] =
4053 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_4
, freq
,
4054 is2GHz
) + ht40PowerIncForPdadc
;
4055 targetPowerValT2
[ALL_TARGET_HT40_5
] =
4056 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_5
, freq
,
4057 is2GHz
) + ht40PowerIncForPdadc
;
4058 targetPowerValT2
[ALL_TARGET_HT40_6
] =
4059 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_6
, freq
,
4060 is2GHz
) + ht40PowerIncForPdadc
;
4061 targetPowerValT2
[ALL_TARGET_HT40_7
] =
4062 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_7
, freq
,
4063 is2GHz
) + ht40PowerIncForPdadc
;
4064 targetPowerValT2
[ALL_TARGET_HT40_12
] =
4065 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_12
, freq
,
4066 is2GHz
) + ht40PowerIncForPdadc
;
4067 targetPowerValT2
[ALL_TARGET_HT40_13
] =
4068 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_13
, freq
,
4069 is2GHz
) + ht40PowerIncForPdadc
;
4070 targetPowerValT2
[ALL_TARGET_HT40_14
] =
4071 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_14
, freq
,
4072 is2GHz
) + ht40PowerIncForPdadc
;
4073 targetPowerValT2
[ALL_TARGET_HT40_15
] =
4074 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_15
, freq
,
4075 is2GHz
) + ht40PowerIncForPdadc
;
4076 targetPowerValT2
[ALL_TARGET_HT40_20
] =
4077 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_20
, freq
,
4078 is2GHz
) + ht40PowerIncForPdadc
;
4079 targetPowerValT2
[ALL_TARGET_HT40_21
] =
4080 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_21
, freq
,
4081 is2GHz
) + ht40PowerIncForPdadc
;
4082 targetPowerValT2
[ALL_TARGET_HT40_22
] =
4083 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_22
, freq
,
4084 is2GHz
) + ht40PowerIncForPdadc
;
4085 targetPowerValT2
[ALL_TARGET_HT40_23
] =
4086 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah
, HT_TARGET_RATE_23
, freq
,
4087 is2GHz
) + ht40PowerIncForPdadc
;
4089 while (i
< ar9300RateSize
) {
4090 ath_print(common
, ATH_DBG_EEPROM
,
4091 "TPC[%02d] 0x%08x ", i
, targetPowerValT2
[i
]);
4094 ath_print(common
, ATH_DBG_EEPROM
,
4095 "TPC[%02d] 0x%08x ", i
, targetPowerValT2
[i
]);
4098 ath_print(common
, ATH_DBG_EEPROM
,
4099 "TPC[%02d] 0x%08x ", i
, targetPowerValT2
[i
]);
4102 ath_print(common
, ATH_DBG_EEPROM
,
4103 "TPC[%02d] 0x%08x\n", i
, targetPowerValT2
[i
]);
4108 static int ar9003_hw_cal_pier_get(struct ath_hw
*ah
,
4114 int *ptemperature
, int *pvoltage
)
4117 struct ar9300_cal_data_per_freq_op_loop
*pCalPierStruct
;
4119 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
4120 struct ath_common
*common
= ath9k_hw_common(ah
);
4122 if (ichain
>= AR9300_MAX_CHAINS
) {
4123 ath_print(common
, ATH_DBG_EEPROM
,
4124 "Invalid chain index, must be less than %d\n",
4129 if (mode
) { /* 5GHz */
4130 if (ipier
>= AR9300_NUM_5G_CAL_PIERS
) {
4131 ath_print(common
, ATH_DBG_EEPROM
,
4132 "Invalid 5GHz cal pier index, must "
4133 "be less than %d\n",
4134 AR9300_NUM_5G_CAL_PIERS
);
4137 pCalPier
= &(eep
->calFreqPier5G
[ipier
]);
4138 pCalPierStruct
= &(eep
->calPierData5G
[ichain
][ipier
]);
4141 if (ipier
>= AR9300_NUM_2G_CAL_PIERS
) {
4142 ath_print(common
, ATH_DBG_EEPROM
,
4143 "Invalid 2GHz cal pier index, must "
4144 "be less than %d\n", AR9300_NUM_2G_CAL_PIERS
);
4148 pCalPier
= &(eep
->calFreqPier2G
[ipier
]);
4149 pCalPierStruct
= &(eep
->calPierData2G
[ichain
][ipier
]);
4153 *pfrequency
= FBIN2FREQ(*pCalPier
, is2GHz
);
4154 *pcorrection
= pCalPierStruct
->refPower
;
4155 *ptemperature
= pCalPierStruct
->tempMeas
;
4156 *pvoltage
= pCalPierStruct
->voltMeas
;
4161 static int ar9003_hw_power_control_override(struct ath_hw
*ah
,
4164 int *voltage
, int *temperature
)
4167 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
4170 REG_RMW(ah
, AR_PHY_TPC_11_B0
,
4171 (correction
[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S
),
4172 AR_PHY_TPC_OLPC_GAIN_DELTA
);
4173 REG_RMW(ah
, AR_PHY_TPC_11_B1
,
4174 (correction
[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S
),
4175 AR_PHY_TPC_OLPC_GAIN_DELTA
);
4176 REG_RMW(ah
, AR_PHY_TPC_11_B2
,
4177 (correction
[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S
),
4178 AR_PHY_TPC_OLPC_GAIN_DELTA
);
4180 /* enable open loop power control on chip */
4181 REG_RMW(ah
, AR_PHY_TPC_6_B0
,
4182 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S
),
4183 AR_PHY_TPC_6_ERROR_EST_MODE
);
4184 REG_RMW(ah
, AR_PHY_TPC_6_B1
,
4185 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S
),
4186 AR_PHY_TPC_6_ERROR_EST_MODE
);
4187 REG_RMW(ah
, AR_PHY_TPC_6_B2
,
4188 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S
),
4189 AR_PHY_TPC_6_ERROR_EST_MODE
);
4192 * enable temperature compensation
4193 * Need to use register names
4195 if (frequency
< 4000)
4196 tempSlope
= eep
->modalHeader2G
.tempSlope
;
4197 else if (eep
->base_ext2
.tempSlopeLow
!= 0) {
4198 t
[0] = eep
->base_ext2
.tempSlopeLow
;
4200 t
[1] = eep
->modalHeader5G
.tempSlope
;
4202 t
[2] = eep
->base_ext2
.tempSlopeHigh
;
4204 tempSlope
= ar9003_hw_power_interpolate((s32
) frequency
,
4207 tempSlope
= eep
->modalHeader5G
.tempSlope
;
4209 REG_RMW_FIELD(ah
, AR_PHY_TPC_19
, AR_PHY_TPC_19_ALPHA_THERM
, tempSlope
);
4210 REG_RMW_FIELD(ah
, AR_PHY_TPC_18
, AR_PHY_TPC_18_THERM_CAL_VALUE
,
4216 /* Apply the recorded correction values. */
4217 static int ar9003_hw_calibration_apply(struct ath_hw
*ah
, int frequency
)
4219 int ichain
, ipier
, npier
;
4221 int lfrequency
[AR9300_MAX_CHAINS
],
4222 lcorrection
[AR9300_MAX_CHAINS
],
4223 ltemperature
[AR9300_MAX_CHAINS
], lvoltage
[AR9300_MAX_CHAINS
];
4224 int hfrequency
[AR9300_MAX_CHAINS
],
4225 hcorrection
[AR9300_MAX_CHAINS
],
4226 htemperature
[AR9300_MAX_CHAINS
], hvoltage
[AR9300_MAX_CHAINS
];
4228 int correction
[AR9300_MAX_CHAINS
],
4229 voltage
[AR9300_MAX_CHAINS
], temperature
[AR9300_MAX_CHAINS
];
4230 int pfrequency
, pcorrection
, ptemperature
, pvoltage
;
4231 struct ath_common
*common
= ath9k_hw_common(ah
);
4233 mode
= (frequency
>= 4000);
4235 npier
= AR9300_NUM_5G_CAL_PIERS
;
4237 npier
= AR9300_NUM_2G_CAL_PIERS
;
4239 for (ichain
= 0; ichain
< AR9300_MAX_CHAINS
; ichain
++) {
4240 lfrequency
[ichain
] = 0;
4241 hfrequency
[ichain
] = 100000;
4243 /* identify best lower and higher frequency calibration measurement */
4244 for (ichain
= 0; ichain
< AR9300_MAX_CHAINS
; ichain
++) {
4245 for (ipier
= 0; ipier
< npier
; ipier
++) {
4246 if (!ar9003_hw_cal_pier_get(ah
, mode
, ipier
, ichain
,
4247 &pfrequency
, &pcorrection
,
4248 &ptemperature
, &pvoltage
)) {
4249 fdiff
= frequency
- pfrequency
;
4252 * this measurement is higher than
4253 * our desired frequency
4256 if (hfrequency
[ichain
] <= 0 ||
4257 hfrequency
[ichain
] >= 100000 ||
4259 (frequency
- hfrequency
[ichain
])) {
4262 * frequency measurement
4264 hfrequency
[ichain
] = pfrequency
;
4265 hcorrection
[ichain
] =
4267 htemperature
[ichain
] =
4269 hvoltage
[ichain
] = pvoltage
;
4273 if (lfrequency
[ichain
] <= 0
4275 (frequency
- lfrequency
[ichain
])) {
4278 * frequency measurement
4280 lfrequency
[ichain
] = pfrequency
;
4281 lcorrection
[ichain
] =
4283 ltemperature
[ichain
] =
4285 lvoltage
[ichain
] = pvoltage
;
4293 for (ichain
= 0; ichain
< AR9300_MAX_CHAINS
; ichain
++) {
4294 ath_print(common
, ATH_DBG_EEPROM
,
4295 "ch=%d f=%d low=%d %d h=%d %d\n",
4296 ichain
, frequency
, lfrequency
[ichain
],
4297 lcorrection
[ichain
], hfrequency
[ichain
],
4298 hcorrection
[ichain
]);
4299 /* they're the same, so just pick one */
4300 if (hfrequency
[ichain
] == lfrequency
[ichain
]) {
4301 correction
[ichain
] = lcorrection
[ichain
];
4302 voltage
[ichain
] = lvoltage
[ichain
];
4303 temperature
[ichain
] = ltemperature
[ichain
];
4305 /* the low frequency is good */
4306 else if (frequency
- lfrequency
[ichain
] < 1000) {
4307 /* so is the high frequency, interpolate */
4308 if (hfrequency
[ichain
] - frequency
< 1000) {
4310 correction
[ichain
] = interpolate(frequency
,
4313 lcorrection
[ichain
],
4314 hcorrection
[ichain
]);
4316 temperature
[ichain
] = interpolate(frequency
,
4319 ltemperature
[ichain
],
4320 htemperature
[ichain
]);
4322 voltage
[ichain
] = interpolate(frequency
,
4328 /* only low is good, use it */
4330 correction
[ichain
] = lcorrection
[ichain
];
4331 temperature
[ichain
] = ltemperature
[ichain
];
4332 voltage
[ichain
] = lvoltage
[ichain
];
4335 /* only high is good, use it */
4336 else if (hfrequency
[ichain
] - frequency
< 1000) {
4337 correction
[ichain
] = hcorrection
[ichain
];
4338 temperature
[ichain
] = htemperature
[ichain
];
4339 voltage
[ichain
] = hvoltage
[ichain
];
4340 } else { /* nothing is good, presume 0???? */
4341 correction
[ichain
] = 0;
4342 temperature
[ichain
] = 0;
4343 voltage
[ichain
] = 0;
4347 ar9003_hw_power_control_override(ah
, frequency
, correction
, voltage
,
4350 ath_print(common
, ATH_DBG_EEPROM
,
4351 "for frequency=%d, calibration correction = %d %d %d\n",
4352 frequency
, correction
[0], correction
[1], correction
[2]);
4357 static u16
ar9003_hw_get_direct_edge_power(struct ar9300_eeprom
*eep
,
4362 struct cal_ctl_data_2g
*ctl_2g
= eep
->ctlPowerData_2G
;
4363 struct cal_ctl_data_5g
*ctl_5g
= eep
->ctlPowerData_5G
;
4366 return ctl_2g
[idx
].ctlEdges
[edge
].tPower
;
4368 return ctl_5g
[idx
].ctlEdges
[edge
].tPower
;
4371 static u16
ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom
*eep
,
4377 struct cal_ctl_data_2g
*ctl_2g
= eep
->ctlPowerData_2G
;
4378 struct cal_ctl_data_5g
*ctl_5g
= eep
->ctlPowerData_5G
;
4380 u8
*ctl_freqbin
= is2GHz
?
4381 &eep
->ctl_freqbin_2G
[idx
][0] :
4382 &eep
->ctl_freqbin_5G
[idx
][0];
4385 if (ath9k_hw_fbin2freq(ctl_freqbin
[edge
- 1], 1) < freq
&&
4386 ctl_2g
[idx
].ctlEdges
[edge
- 1].flag
)
4387 return ctl_2g
[idx
].ctlEdges
[edge
- 1].tPower
;
4389 if (ath9k_hw_fbin2freq(ctl_freqbin
[edge
- 1], 0) < freq
&&
4390 ctl_5g
[idx
].ctlEdges
[edge
- 1].flag
)
4391 return ctl_5g
[idx
].ctlEdges
[edge
- 1].tPower
;
4394 return AR9300_MAX_RATE_POWER
;
4398 * Find the maximum conformance test limit for the given channel and CTL info
4400 static u16
ar9003_hw_get_max_edge_power(struct ar9300_eeprom
*eep
,
4401 u16 freq
, int idx
, bool is2GHz
)
4403 u16 twiceMaxEdgePower
= AR9300_MAX_RATE_POWER
;
4404 u8
*ctl_freqbin
= is2GHz
?
4405 &eep
->ctl_freqbin_2G
[idx
][0] :
4406 &eep
->ctl_freqbin_5G
[idx
][0];
4407 u16 num_edges
= is2GHz
?
4408 AR9300_NUM_BAND_EDGES_2G
: AR9300_NUM_BAND_EDGES_5G
;
4411 /* Get the edge power */
4413 (edge
< num_edges
) && (ctl_freqbin
[edge
] != AR9300_BCHAN_UNUSED
);
4416 * If there's an exact channel match or an inband flag set
4417 * on the lower channel use the given rdEdgePower
4419 if (freq
== ath9k_hw_fbin2freq(ctl_freqbin
[edge
], is2GHz
)) {
4421 ar9003_hw_get_direct_edge_power(eep
, idx
,
4424 } else if ((edge
> 0) &&
4425 (freq
< ath9k_hw_fbin2freq(ctl_freqbin
[edge
],
4428 ar9003_hw_get_indirect_edge_power(eep
, idx
,
4432 * Leave loop - no more affecting edges possible in
4433 * this monotonic increasing list
4438 return twiceMaxEdgePower
;
4441 static void ar9003_hw_set_power_per_rate_table(struct ath_hw
*ah
,
4442 struct ath9k_channel
*chan
,
4443 u8
*pPwrArray
, u16 cfgCtl
,
4444 u8 twiceAntennaReduction
,
4445 u8 twiceMaxRegulatoryPower
,
4448 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
4449 struct ath_common
*common
= ath9k_hw_common(ah
);
4450 struct ar9300_eeprom
*pEepData
= &ah
->eeprom
.ar9300_eep
;
4451 u16 twiceMaxEdgePower
= AR9300_MAX_RATE_POWER
;
4452 static const u16 tpScaleReductionTable
[5] = {
4453 0, 3, 6, 9, AR9300_MAX_RATE_POWER
4456 int16_t twiceLargestAntenna
;
4457 u16 scaledPower
= 0, minCtlPower
, maxRegAllowedPower
;
4458 static const u16 ctlModesFor11a
[] = {
4459 CTL_11A
, CTL_5GHT20
, CTL_11A_EXT
, CTL_5GHT40
4461 static const u16 ctlModesFor11g
[] = {
4462 CTL_11B
, CTL_11G
, CTL_2GHT20
, CTL_11B_EXT
,
4463 CTL_11G_EXT
, CTL_2GHT40
4466 const u16
*pCtlMode
;
4468 struct chan_centers centers
;
4471 u16 twiceMinEdgePower
;
4472 bool is2ghz
= IS_CHAN_2GHZ(chan
);
4474 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
4476 /* Compute TxPower reduction due to Antenna Gain */
4478 twiceLargestAntenna
= pEepData
->modalHeader2G
.antennaGain
;
4480 twiceLargestAntenna
= pEepData
->modalHeader5G
.antennaGain
;
4482 twiceLargestAntenna
= (int16_t)min((twiceAntennaReduction
) -
4483 twiceLargestAntenna
, 0);
4486 * scaledPower is the minimum of the user input power level
4487 * and the regulatory allowed power level
4489 maxRegAllowedPower
= twiceMaxRegulatoryPower
+ twiceLargestAntenna
;
4491 if (regulatory
->tp_scale
!= ATH9K_TP_SCALE_MAX
) {
4492 maxRegAllowedPower
-=
4493 (tpScaleReductionTable
[(regulatory
->tp_scale
)] * 2);
4496 scaledPower
= min(powerLimit
, maxRegAllowedPower
);
4499 * Reduce scaled Power by number of chains active to get
4500 * to per chain tx power level
4502 switch (ar5416_get_ntxchains(ah
->txchainmask
)) {
4506 scaledPower
-= REDUCE_SCALED_POWER_BY_TWO_CHAIN
;
4509 scaledPower
-= REDUCE_SCALED_POWER_BY_THREE_CHAIN
;
4513 scaledPower
= max((u16
)0, scaledPower
);
4516 * Get target powers from EEPROM - our baseline for TX Power
4519 /* Setup for CTL modes */
4520 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4522 ARRAY_SIZE(ctlModesFor11g
) -
4523 SUB_NUM_CTL_MODES_AT_2G_40
;
4524 pCtlMode
= ctlModesFor11g
;
4525 if (IS_CHAN_HT40(chan
))
4527 numCtlModes
= ARRAY_SIZE(ctlModesFor11g
);
4529 /* Setup for CTL modes */
4530 /* CTL_11A, CTL_5GHT20 */
4531 numCtlModes
= ARRAY_SIZE(ctlModesFor11a
) -
4532 SUB_NUM_CTL_MODES_AT_5G_40
;
4533 pCtlMode
= ctlModesFor11a
;
4534 if (IS_CHAN_HT40(chan
))
4536 numCtlModes
= ARRAY_SIZE(ctlModesFor11a
);
4540 * For MIMO, need to apply regulatory caps individually across
4541 * dynamically running modes: CCK, OFDM, HT20, HT40
4543 * The outer loop walks through each possible applicable runtime mode.
4544 * The inner loop walks through each ctlIndex entry in EEPROM.
4545 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4547 for (ctlMode
= 0; ctlMode
< numCtlModes
; ctlMode
++) {
4548 bool isHt40CtlMode
= (pCtlMode
[ctlMode
] == CTL_5GHT40
) ||
4549 (pCtlMode
[ctlMode
] == CTL_2GHT40
);
4551 freq
= centers
.synth_center
;
4552 else if (pCtlMode
[ctlMode
] & EXT_ADDITIVE
)
4553 freq
= centers
.ext_center
;
4555 freq
= centers
.ctl_center
;
4557 ath_print(common
, ATH_DBG_REGULATORY
,
4558 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4559 "EXT_ADDITIVE %d\n",
4560 ctlMode
, numCtlModes
, isHt40CtlMode
,
4561 (pCtlMode
[ctlMode
] & EXT_ADDITIVE
));
4563 /* walk through each CTL index stored in EEPROM */
4565 ctlIndex
= pEepData
->ctlIndex_2G
;
4566 ctlNum
= AR9300_NUM_CTLS_2G
;
4568 ctlIndex
= pEepData
->ctlIndex_5G
;
4569 ctlNum
= AR9300_NUM_CTLS_5G
;
4572 for (i
= 0; (i
< ctlNum
) && ctlIndex
[i
]; i
++) {
4573 ath_print(common
, ATH_DBG_REGULATORY
,
4574 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4575 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4577 i
, cfgCtl
, pCtlMode
[ctlMode
], ctlIndex
[i
],
4581 * compare test group from regulatory
4582 * channel list with test mode from pCtlMode
4585 if ((((cfgCtl
& ~CTL_MODE_M
) |
4586 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
4588 (((cfgCtl
& ~CTL_MODE_M
) |
4589 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
4590 ((ctlIndex
[i
] & CTL_MODE_M
) |
4593 ar9003_hw_get_max_edge_power(pEepData
,
4597 if ((cfgCtl
& ~CTL_MODE_M
) == SD_NO_CTL
)
4599 * Find the minimum of all CTL
4600 * edge powers that apply to
4604 min(twiceMaxEdgePower
,
4615 minCtlPower
= (u8
)min(twiceMaxEdgePower
, scaledPower
);
4617 ath_print(common
, ATH_DBG_REGULATORY
,
4618 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
4619 "sP %d minCtlPwr %d\n",
4620 ctlMode
, pCtlMode
[ctlMode
], twiceMaxEdgePower
,
4621 scaledPower
, minCtlPower
);
4623 /* Apply ctl mode to correct target power set */
4624 switch (pCtlMode
[ctlMode
]) {
4626 for (i
= ALL_TARGET_LEGACY_1L_5L
;
4627 i
<= ALL_TARGET_LEGACY_11S
; i
++)
4629 (u8
)min((u16
)pPwrArray
[i
],
4634 for (i
= ALL_TARGET_LEGACY_6_24
;
4635 i
<= ALL_TARGET_LEGACY_54
; i
++)
4637 (u8
)min((u16
)pPwrArray
[i
],
4642 for (i
= ALL_TARGET_HT20_0_8_16
;
4643 i
<= ALL_TARGET_HT20_21
; i
++)
4645 (u8
)min((u16
)pPwrArray
[i
],
4647 pPwrArray
[ALL_TARGET_HT20_22
] =
4648 (u8
)min((u16
)pPwrArray
[ALL_TARGET_HT20_22
],
4650 pPwrArray
[ALL_TARGET_HT20_23
] =
4651 (u8
)min((u16
)pPwrArray
[ALL_TARGET_HT20_23
],
4656 for (i
= ALL_TARGET_HT40_0_8_16
;
4657 i
<= ALL_TARGET_HT40_23
; i
++)
4659 (u8
)min((u16
)pPwrArray
[i
],
4665 } /* end ctl mode checking */
4668 static void ath9k_hw_ar9300_set_txpower(struct ath_hw
*ah
,
4669 struct ath9k_channel
*chan
, u16 cfgCtl
,
4670 u8 twiceAntennaReduction
,
4671 u8 twiceMaxRegulatoryPower
,
4672 u8 powerLimit
, bool test
)
4674 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
4675 struct ath_common
*common
= ath9k_hw_common(ah
);
4676 u8 targetPowerValT2
[ar9300RateSize
];
4679 ar9003_hw_set_target_power_eeprom(ah
, chan
->channel
, targetPowerValT2
);
4680 ar9003_hw_set_power_per_rate_table(ah
, chan
,
4681 targetPowerValT2
, cfgCtl
,
4682 twiceAntennaReduction
,
4683 twiceMaxRegulatoryPower
,
4686 regulatory
->max_power_level
= 0;
4687 for (i
= 0; i
< ar9300RateSize
; i
++) {
4688 if (targetPowerValT2
[i
] > regulatory
->max_power_level
)
4689 regulatory
->max_power_level
= targetPowerValT2
[i
];
4695 for (i
= 0; i
< ar9300RateSize
; i
++) {
4696 ath_print(common
, ATH_DBG_EEPROM
,
4697 "TPC[%02d] 0x%08x ", i
, targetPowerValT2
[i
]);
4699 ath_print(common
, ATH_DBG_EEPROM
,
4700 "TPC[%02d] 0x%08x ", i
, targetPowerValT2
[i
]);
4702 ath_print(common
, ATH_DBG_EEPROM
,
4703 "TPC[%02d] 0x%08x ", i
, targetPowerValT2
[i
]);
4705 ath_print(common
, ATH_DBG_EEPROM
,
4706 "TPC[%02d] 0x%08x\n\n", i
, targetPowerValT2
[i
]);
4711 * This is the TX power we send back to driver core,
4712 * and it can use to pass to userspace to display our
4713 * currently configured TX power setting.
4715 * Since power is rate dependent, use one of the indices
4716 * from the AR9300_Rates enum to select an entry from
4717 * targetPowerValT2[] to report. Currently returns the
4718 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4719 * as CCK power is less interesting (?).
4721 i
= ALL_TARGET_LEGACY_6_24
; /* legacy */
4722 if (IS_CHAN_HT40(chan
))
4723 i
= ALL_TARGET_HT40_0_8_16
; /* ht40 */
4724 else if (IS_CHAN_HT20(chan
))
4725 i
= ALL_TARGET_HT20_0_8_16
; /* ht20 */
4727 ah
->txpower_limit
= targetPowerValT2
[i
];
4728 regulatory
->max_power_level
= targetPowerValT2
[i
];
4730 /* Write target power array to registers */
4731 ar9003_hw_tx_power_regwrite(ah
, targetPowerValT2
);
4732 ar9003_hw_calibration_apply(ah
, chan
->channel
);
4735 static u16
ath9k_hw_ar9300_get_spur_channel(struct ath_hw
*ah
,
4741 s32
ar9003_hw_get_tx_gain_idx(struct ath_hw
*ah
)
4743 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
4745 return (eep
->baseEepHeader
.txrxgain
>> 4) & 0xf; /* bits 7:4 */
4748 s32
ar9003_hw_get_rx_gain_idx(struct ath_hw
*ah
)
4750 struct ar9300_eeprom
*eep
= &ah
->eeprom
.ar9300_eep
;
4752 return (eep
->baseEepHeader
.txrxgain
) & 0xf; /* bits 3:0 */
4755 const struct eeprom_ops eep_ar9300_ops
= {
4756 .check_eeprom
= ath9k_hw_ar9300_check_eeprom
,
4757 .get_eeprom
= ath9k_hw_ar9300_get_eeprom
,
4758 .fill_eeprom
= ath9k_hw_ar9300_fill_eeprom
,
4759 .get_eeprom_ver
= ath9k_hw_ar9300_get_eeprom_ver
,
4760 .get_eeprom_rev
= ath9k_hw_ar9300_get_eeprom_rev
,
4761 .get_num_ant_config
= ath9k_hw_ar9300_get_num_ant_config
,
4762 .get_eeprom_antenna_cfg
= ath9k_hw_ar9300_get_eeprom_antenna_cfg
,
4763 .set_board_values
= ath9k_hw_ar9300_set_board_values
,
4764 .set_addac
= ath9k_hw_ar9300_set_addac
,
4765 .set_txpower
= ath9k_hw_ar9300_set_txpower
,
4766 .get_spur_channel
= ath9k_hw_ar9300_get_spur_channel