]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ath9k_hw: add eeprom templates for ar9003 family chipsets
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
1 /*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "ar9003_phy.h"
19 #include "ar9003_eeprom.h"
20
21 #define COMP_HDR_LEN 4
22 #define COMP_CKSUM_LEN 2
23
24 #define AR_CH0_TOP (0x00016288)
25 #define AR_CH0_TOP_XPABIASLVL (0x3)
26 #define AR_CH0_TOP_XPABIASLVL_S (8)
27
28 #define AR_CH0_THERM (0x00016290)
29 #define AR_CH0_THERM_SPARE (0x3f)
30 #define AR_CH0_THERM_SPARE_S (0)
31
32 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
33 #define AR_SWITCH_TABLE_COM_ALL_S (0)
34
35 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
36 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
37
38 #define AR_SWITCH_TABLE_ALL (0xfff)
39 #define AR_SWITCH_TABLE_ALL_S (0)
40
41 #define LE16(x) __constant_cpu_to_le16(x)
42 #define LE32(x) __constant_cpu_to_le32(x)
43
44 /* Local defines to distinguish between extension and control CTL's */
45 #define EXT_ADDITIVE (0x8000)
46 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
47 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
48 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
49 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
50 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
51 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
52 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
53 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
54
55 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
56 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
57
58 static const struct ar9300_eeprom ar9300_default = {
59 .eepromVersion = 2,
60 .templateVersion = 2,
61 .macAddr = {1, 2, 3, 4, 5, 6},
62 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
63 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
64 .baseEepHeader = {
65 .regDmn = { LE16(0), LE16(0x1f) },
66 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
67 .opCapFlags = {
68 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
69 .eepMisc = 0,
70 },
71 .rfSilent = 0,
72 .blueToothOptions = 0,
73 .deviceCap = 0,
74 .deviceType = 5, /* takes lower byte in eeprom location */
75 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
76 .params_for_tuning_caps = {0, 0},
77 .featureEnable = 0x0c,
78 /*
79 * bit0 - enable tx temp comp - disabled
80 * bit1 - enable tx volt comp - disabled
81 * bit2 - enable fastClock - enabled
82 * bit3 - enable doubling - enabled
83 * bit4 - enable internal regulator - disabled
84 * bit5 - enable pa predistortion - disabled
85 */
86 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
87 .eepromWriteEnableGpio = 3,
88 .wlanDisableGpio = 0,
89 .wlanLedGpio = 8,
90 .rxBandSelectGpio = 0xff,
91 .txrxgain = 0,
92 .swreg = 0,
93 },
94 .modalHeader2G = {
95 /* ar9300_modal_eep_header 2g */
96 /* 4 idle,t1,t2,b(4 bits per setting) */
97 .antCtrlCommon = LE32(0x110),
98 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
99 .antCtrlCommon2 = LE32(0x22222),
100
101 /*
102 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
103 * rx1, rx12, b (2 bits each)
104 */
105 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
106
107 /*
108 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
109 * for ar9280 (0xa20c/b20c 5:0)
110 */
111 .xatten1DB = {0, 0, 0},
112
113 /*
114 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
115 * for ar9280 (0xa20c/b20c 16:12
116 */
117 .xatten1Margin = {0, 0, 0},
118 .tempSlope = 36,
119 .voltSlope = 0,
120
121 /*
122 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
123 * channels in usual fbin coding format
124 */
125 .spurChans = {0, 0, 0, 0, 0},
126
127 /*
128 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
129 * if the register is per chain
130 */
131 .noiseFloorThreshCh = {-1, 0, 0},
132 .ob = {1, 1, 1},/* 3 chain */
133 .db_stage2 = {1, 1, 1}, /* 3 chain */
134 .db_stage3 = {0, 0, 0},
135 .db_stage4 = {0, 0, 0},
136 .xpaBiasLvl = 0,
137 .txFrameToDataStart = 0x0e,
138 .txFrameToPaOn = 0x0e,
139 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
140 .antennaGain = 0,
141 .switchSettling = 0x2c,
142 .adcDesiredSize = -30,
143 .txEndToXpaOff = 0,
144 .txEndToRxOn = 0x2,
145 .txFrameToXpaOn = 0xe,
146 .thresh62 = 28,
147 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
148 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
149 .futureModal = {
150 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
151 },
152 },
153 .base_ext1 = {
154 .ant_div_control = 0,
155 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
156 },
157 .calFreqPier2G = {
158 FREQ2FBIN(2412, 1),
159 FREQ2FBIN(2437, 1),
160 FREQ2FBIN(2472, 1),
161 },
162 /* ar9300_cal_data_per_freq_op_loop 2g */
163 .calPierData2G = {
164 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
165 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
166 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
167 },
168 .calTarget_freqbin_Cck = {
169 FREQ2FBIN(2412, 1),
170 FREQ2FBIN(2484, 1),
171 },
172 .calTarget_freqbin_2G = {
173 FREQ2FBIN(2412, 1),
174 FREQ2FBIN(2437, 1),
175 FREQ2FBIN(2472, 1)
176 },
177 .calTarget_freqbin_2GHT20 = {
178 FREQ2FBIN(2412, 1),
179 FREQ2FBIN(2437, 1),
180 FREQ2FBIN(2472, 1)
181 },
182 .calTarget_freqbin_2GHT40 = {
183 FREQ2FBIN(2412, 1),
184 FREQ2FBIN(2437, 1),
185 FREQ2FBIN(2472, 1)
186 },
187 .calTargetPowerCck = {
188 /* 1L-5L,5S,11L,11S */
189 { {36, 36, 36, 36} },
190 { {36, 36, 36, 36} },
191 },
192 .calTargetPower2G = {
193 /* 6-24,36,48,54 */
194 { {32, 32, 28, 24} },
195 { {32, 32, 28, 24} },
196 { {32, 32, 28, 24} },
197 },
198 .calTargetPower2GHT20 = {
199 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
200 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
201 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
202 },
203 .calTargetPower2GHT40 = {
204 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
205 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
206 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
207 },
208 .ctlIndex_2G = {
209 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
210 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
211 },
212 .ctl_freqbin_2G = {
213 {
214 FREQ2FBIN(2412, 1),
215 FREQ2FBIN(2417, 1),
216 FREQ2FBIN(2457, 1),
217 FREQ2FBIN(2462, 1)
218 },
219 {
220 FREQ2FBIN(2412, 1),
221 FREQ2FBIN(2417, 1),
222 FREQ2FBIN(2462, 1),
223 0xFF,
224 },
225
226 {
227 FREQ2FBIN(2412, 1),
228 FREQ2FBIN(2417, 1),
229 FREQ2FBIN(2462, 1),
230 0xFF,
231 },
232 {
233 FREQ2FBIN(2422, 1),
234 FREQ2FBIN(2427, 1),
235 FREQ2FBIN(2447, 1),
236 FREQ2FBIN(2452, 1)
237 },
238
239 {
240 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
241 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
242 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
243 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
244 },
245
246 {
247 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
248 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
249 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
250 0,
251 },
252
253 {
254 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
255 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
256 FREQ2FBIN(2472, 1),
257 0,
258 },
259
260 {
261 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
262 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
263 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
264 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
265 },
266
267 {
268 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
269 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
270 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
271 },
272
273 {
274 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
275 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
276 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
277 0
278 },
279
280 {
281 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
282 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
283 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
284 0
285 },
286
287 {
288 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
289 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
290 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
291 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
292 }
293 },
294 .ctlPowerData_2G = {
295 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
296 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
297 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
298
299 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
300 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
301 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
302
303 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
304 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
305 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
306
307 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
308 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
309 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
310 },
311 .modalHeader5G = {
312 /* 4 idle,t1,t2,b (4 bits per setting) */
313 .antCtrlCommon = LE32(0x110),
314 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
315 .antCtrlCommon2 = LE32(0x22222),
316 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
317 .antCtrlChain = {
318 LE16(0x000), LE16(0x000), LE16(0x000),
319 },
320 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
321 .xatten1DB = {0, 0, 0},
322
323 /*
324 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
325 * for merlin (0xa20c/b20c 16:12
326 */
327 .xatten1Margin = {0, 0, 0},
328 .tempSlope = 68,
329 .voltSlope = 0,
330 /* spurChans spur channels in usual fbin coding format */
331 .spurChans = {0, 0, 0, 0, 0},
332 /* noiseFloorThreshCh Check if the register is per chain */
333 .noiseFloorThreshCh = {-1, 0, 0},
334 .ob = {3, 3, 3}, /* 3 chain */
335 .db_stage2 = {3, 3, 3}, /* 3 chain */
336 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
337 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
338 .xpaBiasLvl = 0,
339 .txFrameToDataStart = 0x0e,
340 .txFrameToPaOn = 0x0e,
341 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
342 .antennaGain = 0,
343 .switchSettling = 0x2d,
344 .adcDesiredSize = -30,
345 .txEndToXpaOff = 0,
346 .txEndToRxOn = 0x2,
347 .txFrameToXpaOn = 0xe,
348 .thresh62 = 28,
349 .papdRateMaskHt20 = LE32(0x0c80c080),
350 .papdRateMaskHt40 = LE32(0x0080c080),
351 .futureModal = {
352 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
353 },
354 },
355 .base_ext2 = {
356 .tempSlopeLow = 0,
357 .tempSlopeHigh = 0,
358 .xatten1DBLow = {0, 0, 0},
359 .xatten1MarginLow = {0, 0, 0},
360 .xatten1DBHigh = {0, 0, 0},
361 .xatten1MarginHigh = {0, 0, 0}
362 },
363 .calFreqPier5G = {
364 FREQ2FBIN(5180, 0),
365 FREQ2FBIN(5220, 0),
366 FREQ2FBIN(5320, 0),
367 FREQ2FBIN(5400, 0),
368 FREQ2FBIN(5500, 0),
369 FREQ2FBIN(5600, 0),
370 FREQ2FBIN(5725, 0),
371 FREQ2FBIN(5825, 0)
372 },
373 .calPierData5G = {
374 {
375 {0, 0, 0, 0, 0},
376 {0, 0, 0, 0, 0},
377 {0, 0, 0, 0, 0},
378 {0, 0, 0, 0, 0},
379 {0, 0, 0, 0, 0},
380 {0, 0, 0, 0, 0},
381 {0, 0, 0, 0, 0},
382 {0, 0, 0, 0, 0},
383 },
384 {
385 {0, 0, 0, 0, 0},
386 {0, 0, 0, 0, 0},
387 {0, 0, 0, 0, 0},
388 {0, 0, 0, 0, 0},
389 {0, 0, 0, 0, 0},
390 {0, 0, 0, 0, 0},
391 {0, 0, 0, 0, 0},
392 {0, 0, 0, 0, 0},
393 },
394 {
395 {0, 0, 0, 0, 0},
396 {0, 0, 0, 0, 0},
397 {0, 0, 0, 0, 0},
398 {0, 0, 0, 0, 0},
399 {0, 0, 0, 0, 0},
400 {0, 0, 0, 0, 0},
401 {0, 0, 0, 0, 0},
402 {0, 0, 0, 0, 0},
403 },
404
405 },
406 .calTarget_freqbin_5G = {
407 FREQ2FBIN(5180, 0),
408 FREQ2FBIN(5220, 0),
409 FREQ2FBIN(5320, 0),
410 FREQ2FBIN(5400, 0),
411 FREQ2FBIN(5500, 0),
412 FREQ2FBIN(5600, 0),
413 FREQ2FBIN(5725, 0),
414 FREQ2FBIN(5825, 0)
415 },
416 .calTarget_freqbin_5GHT20 = {
417 FREQ2FBIN(5180, 0),
418 FREQ2FBIN(5240, 0),
419 FREQ2FBIN(5320, 0),
420 FREQ2FBIN(5500, 0),
421 FREQ2FBIN(5700, 0),
422 FREQ2FBIN(5745, 0),
423 FREQ2FBIN(5725, 0),
424 FREQ2FBIN(5825, 0)
425 },
426 .calTarget_freqbin_5GHT40 = {
427 FREQ2FBIN(5180, 0),
428 FREQ2FBIN(5240, 0),
429 FREQ2FBIN(5320, 0),
430 FREQ2FBIN(5500, 0),
431 FREQ2FBIN(5700, 0),
432 FREQ2FBIN(5745, 0),
433 FREQ2FBIN(5725, 0),
434 FREQ2FBIN(5825, 0)
435 },
436 .calTargetPower5G = {
437 /* 6-24,36,48,54 */
438 { {20, 20, 20, 10} },
439 { {20, 20, 20, 10} },
440 { {20, 20, 20, 10} },
441 { {20, 20, 20, 10} },
442 { {20, 20, 20, 10} },
443 { {20, 20, 20, 10} },
444 { {20, 20, 20, 10} },
445 { {20, 20, 20, 10} },
446 },
447 .calTargetPower5GHT20 = {
448 /*
449 * 0_8_16,1-3_9-11_17-19,
450 * 4,5,6,7,12,13,14,15,20,21,22,23
451 */
452 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
453 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 },
461 .calTargetPower5GHT40 = {
462 /*
463 * 0_8_16,1-3_9-11_17-19,
464 * 4,5,6,7,12,13,14,15,20,21,22,23
465 */
466 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
467 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
468 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
469 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
470 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
472 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
473 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
474 },
475 .ctlIndex_5G = {
476 0x10, 0x16, 0x18, 0x40, 0x46,
477 0x48, 0x30, 0x36, 0x38
478 },
479 .ctl_freqbin_5G = {
480 {
481 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
482 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
483 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
484 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
485 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
486 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
487 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
488 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
489 },
490 {
491 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
492 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
493 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
494 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
495 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
496 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
497 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
498 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
499 },
500
501 {
502 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
503 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
504 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
505 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
506 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
507 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
508 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
509 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
510 },
511
512 {
513 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
514 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
515 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
516 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
517 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
518 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
519 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
520 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
521 },
522
523 {
524 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
525 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
526 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
527 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
528 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
529 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
530 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
531 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
532 },
533
534 {
535 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
536 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
537 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
538 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
539 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
540 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
541 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
542 /* Data[5].ctlEdges[7].bChannel */ 0xFF
543 },
544
545 {
546 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
547 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
548 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
549 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
550 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
551 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
552 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
553 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
554 },
555
556 {
557 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
558 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
559 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
560 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
561 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
562 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
563 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
564 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
565 },
566
567 {
568 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
569 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
570 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
571 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
572 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
573 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
574 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
575 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
576 }
577 },
578 .ctlPowerData_5G = {
579 {
580 {
581 {60, 1}, {60, 1}, {60, 1}, {60, 1},
582 {60, 1}, {60, 1}, {60, 1}, {60, 0},
583 }
584 },
585 {
586 {
587 {60, 1}, {60, 1}, {60, 1}, {60, 1},
588 {60, 1}, {60, 1}, {60, 1}, {60, 0},
589 }
590 },
591 {
592 {
593 {60, 0}, {60, 1}, {60, 0}, {60, 1},
594 {60, 1}, {60, 1}, {60, 1}, {60, 1},
595 }
596 },
597 {
598 {
599 {60, 0}, {60, 1}, {60, 1}, {60, 0},
600 {60, 1}, {60, 0}, {60, 0}, {60, 0},
601 }
602 },
603 {
604 {
605 {60, 1}, {60, 1}, {60, 1}, {60, 0},
606 {60, 0}, {60, 0}, {60, 0}, {60, 0},
607 }
608 },
609 {
610 {
611 {60, 1}, {60, 1}, {60, 1}, {60, 1},
612 {60, 1}, {60, 0}, {60, 0}, {60, 0},
613 }
614 },
615 {
616 {
617 {60, 1}, {60, 1}, {60, 1}, {60, 1},
618 {60, 1}, {60, 1}, {60, 1}, {60, 1},
619 }
620 },
621 {
622 {
623 {60, 1}, {60, 1}, {60, 0}, {60, 1},
624 {60, 1}, {60, 1}, {60, 1}, {60, 0},
625 }
626 },
627 {
628 {
629 {60, 1}, {60, 0}, {60, 1}, {60, 1},
630 {60, 1}, {60, 1}, {60, 0}, {60, 1},
631 }
632 },
633 }
634 };
635
636 static const struct ar9300_eeprom ar9300_x113 = {
637 .eepromVersion = 2,
638 .templateVersion = 6,
639 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
640 .custData = {"x113-023-f0000"},
641 .baseEepHeader = {
642 .regDmn = { LE16(0), LE16(0x1f) },
643 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
644 .opCapFlags = {
645 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
646 .eepMisc = 0,
647 },
648 .rfSilent = 0,
649 .blueToothOptions = 0,
650 .deviceCap = 0,
651 .deviceType = 5, /* takes lower byte in eeprom location */
652 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
653 .params_for_tuning_caps = {0, 0},
654 .featureEnable = 0x0d,
655 /*
656 * bit0 - enable tx temp comp - disabled
657 * bit1 - enable tx volt comp - disabled
658 * bit2 - enable fastClock - enabled
659 * bit3 - enable doubling - enabled
660 * bit4 - enable internal regulator - disabled
661 * bit5 - enable pa predistortion - disabled
662 */
663 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
664 .eepromWriteEnableGpio = 6,
665 .wlanDisableGpio = 0,
666 .wlanLedGpio = 8,
667 .rxBandSelectGpio = 0xff,
668 .txrxgain = 0x21,
669 .swreg = 0,
670 },
671 .modalHeader2G = {
672 /* ar9300_modal_eep_header 2g */
673 /* 4 idle,t1,t2,b(4 bits per setting) */
674 .antCtrlCommon = LE32(0x110),
675 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
676 .antCtrlCommon2 = LE32(0x44444),
677
678 /*
679 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
680 * rx1, rx12, b (2 bits each)
681 */
682 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
683
684 /*
685 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
686 * for ar9280 (0xa20c/b20c 5:0)
687 */
688 .xatten1DB = {0, 0, 0},
689
690 /*
691 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
692 * for ar9280 (0xa20c/b20c 16:12
693 */
694 .xatten1Margin = {0, 0, 0},
695 .tempSlope = 25,
696 .voltSlope = 0,
697
698 /*
699 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
700 * channels in usual fbin coding format
701 */
702 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
703
704 /*
705 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
706 * if the register is per chain
707 */
708 .noiseFloorThreshCh = {-1, 0, 0},
709 .ob = {1, 1, 1},/* 3 chain */
710 .db_stage2 = {1, 1, 1}, /* 3 chain */
711 .db_stage3 = {0, 0, 0},
712 .db_stage4 = {0, 0, 0},
713 .xpaBiasLvl = 0,
714 .txFrameToDataStart = 0x0e,
715 .txFrameToPaOn = 0x0e,
716 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
717 .antennaGain = 0,
718 .switchSettling = 0x2c,
719 .adcDesiredSize = -30,
720 .txEndToXpaOff = 0,
721 .txEndToRxOn = 0x2,
722 .txFrameToXpaOn = 0xe,
723 .thresh62 = 28,
724 .papdRateMaskHt20 = LE32(0x0c80c080),
725 .papdRateMaskHt40 = LE32(0x0080c080),
726 .futureModal = {
727 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
728 },
729 },
730 .base_ext1 = {
731 .ant_div_control = 0,
732 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
733 },
734 .calFreqPier2G = {
735 FREQ2FBIN(2412, 1),
736 FREQ2FBIN(2437, 1),
737 FREQ2FBIN(2472, 1),
738 },
739 /* ar9300_cal_data_per_freq_op_loop 2g */
740 .calPierData2G = {
741 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
742 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
743 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
744 },
745 .calTarget_freqbin_Cck = {
746 FREQ2FBIN(2412, 1),
747 FREQ2FBIN(2472, 1),
748 },
749 .calTarget_freqbin_2G = {
750 FREQ2FBIN(2412, 1),
751 FREQ2FBIN(2437, 1),
752 FREQ2FBIN(2472, 1)
753 },
754 .calTarget_freqbin_2GHT20 = {
755 FREQ2FBIN(2412, 1),
756 FREQ2FBIN(2437, 1),
757 FREQ2FBIN(2472, 1)
758 },
759 .calTarget_freqbin_2GHT40 = {
760 FREQ2FBIN(2412, 1),
761 FREQ2FBIN(2437, 1),
762 FREQ2FBIN(2472, 1)
763 },
764 .calTargetPowerCck = {
765 /* 1L-5L,5S,11L,11S */
766 { {34, 34, 34, 34} },
767 { {34, 34, 34, 34} },
768 },
769 .calTargetPower2G = {
770 /* 6-24,36,48,54 */
771 { {34, 34, 32, 32} },
772 { {34, 34, 32, 32} },
773 { {34, 34, 32, 32} },
774 },
775 .calTargetPower2GHT20 = {
776 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
777 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
778 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
779 },
780 .calTargetPower2GHT40 = {
781 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
782 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
783 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
784 },
785 .ctlIndex_2G = {
786 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
787 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
788 },
789 .ctl_freqbin_2G = {
790 {
791 FREQ2FBIN(2412, 1),
792 FREQ2FBIN(2417, 1),
793 FREQ2FBIN(2457, 1),
794 FREQ2FBIN(2462, 1)
795 },
796 {
797 FREQ2FBIN(2412, 1),
798 FREQ2FBIN(2417, 1),
799 FREQ2FBIN(2462, 1),
800 0xFF,
801 },
802
803 {
804 FREQ2FBIN(2412, 1),
805 FREQ2FBIN(2417, 1),
806 FREQ2FBIN(2462, 1),
807 0xFF,
808 },
809 {
810 FREQ2FBIN(2422, 1),
811 FREQ2FBIN(2427, 1),
812 FREQ2FBIN(2447, 1),
813 FREQ2FBIN(2452, 1)
814 },
815
816 {
817 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
818 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
819 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
820 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
821 },
822
823 {
824 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
825 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
826 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
827 0,
828 },
829
830 {
831 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
832 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
833 FREQ2FBIN(2472, 1),
834 0,
835 },
836
837 {
838 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
839 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
840 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
841 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
842 },
843
844 {
845 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
846 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
847 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
848 },
849
850 {
851 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
852 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
853 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
854 0
855 },
856
857 {
858 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
859 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
860 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
861 0
862 },
863
864 {
865 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
866 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
867 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
868 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
869 }
870 },
871 .ctlPowerData_2G = {
872 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
873 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
874 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
875
876 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
877 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
878 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
879
880 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
881 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
882 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
883
884 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
885 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
886 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
887 },
888 .modalHeader5G = {
889 /* 4 idle,t1,t2,b (4 bits per setting) */
890 .antCtrlCommon = LE32(0x220),
891 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
892 .antCtrlCommon2 = LE32(0x11111),
893 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
894 .antCtrlChain = {
895 LE16(0x150), LE16(0x150), LE16(0x150),
896 },
897 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
898 .xatten1DB = {0, 0, 0},
899
900 /*
901 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
902 * for merlin (0xa20c/b20c 16:12
903 */
904 .xatten1Margin = {0, 0, 0},
905 .tempSlope = 68,
906 .voltSlope = 0,
907 /* spurChans spur channels in usual fbin coding format */
908 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
909 /* noiseFloorThreshCh Check if the register is per chain */
910 .noiseFloorThreshCh = {-1, 0, 0},
911 .ob = {3, 3, 3}, /* 3 chain */
912 .db_stage2 = {3, 3, 3}, /* 3 chain */
913 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
914 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
915 .xpaBiasLvl = 0,
916 .txFrameToDataStart = 0x0e,
917 .txFrameToPaOn = 0x0e,
918 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
919 .antennaGain = 0,
920 .switchSettling = 0x2d,
921 .adcDesiredSize = -30,
922 .txEndToXpaOff = 0,
923 .txEndToRxOn = 0x2,
924 .txFrameToXpaOn = 0xe,
925 .thresh62 = 28,
926 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
927 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
928 .futureModal = {
929 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
930 },
931 },
932 .base_ext2 = {
933 .tempSlopeLow = 72,
934 .tempSlopeHigh = 105,
935 .xatten1DBLow = {0, 0, 0},
936 .xatten1MarginLow = {0, 0, 0},
937 .xatten1DBHigh = {0, 0, 0},
938 .xatten1MarginHigh = {0, 0, 0}
939 },
940 .calFreqPier5G = {
941 FREQ2FBIN(5180, 0),
942 FREQ2FBIN(5240, 0),
943 FREQ2FBIN(5320, 0),
944 FREQ2FBIN(5400, 0),
945 FREQ2FBIN(5500, 0),
946 FREQ2FBIN(5600, 0),
947 FREQ2FBIN(5745, 0),
948 FREQ2FBIN(5785, 0)
949 },
950 .calPierData5G = {
951 {
952 {0, 0, 0, 0, 0},
953 {0, 0, 0, 0, 0},
954 {0, 0, 0, 0, 0},
955 {0, 0, 0, 0, 0},
956 {0, 0, 0, 0, 0},
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 {0, 0, 0, 0, 0},
960 },
961 {
962 {0, 0, 0, 0, 0},
963 {0, 0, 0, 0, 0},
964 {0, 0, 0, 0, 0},
965 {0, 0, 0, 0, 0},
966 {0, 0, 0, 0, 0},
967 {0, 0, 0, 0, 0},
968 {0, 0, 0, 0, 0},
969 {0, 0, 0, 0, 0},
970 },
971 {
972 {0, 0, 0, 0, 0},
973 {0, 0, 0, 0, 0},
974 {0, 0, 0, 0, 0},
975 {0, 0, 0, 0, 0},
976 {0, 0, 0, 0, 0},
977 {0, 0, 0, 0, 0},
978 {0, 0, 0, 0, 0},
979 {0, 0, 0, 0, 0},
980 },
981
982 },
983 .calTarget_freqbin_5G = {
984 FREQ2FBIN(5180, 0),
985 FREQ2FBIN(5220, 0),
986 FREQ2FBIN(5320, 0),
987 FREQ2FBIN(5400, 0),
988 FREQ2FBIN(5500, 0),
989 FREQ2FBIN(5600, 0),
990 FREQ2FBIN(5745, 0),
991 FREQ2FBIN(5785, 0)
992 },
993 .calTarget_freqbin_5GHT20 = {
994 FREQ2FBIN(5180, 0),
995 FREQ2FBIN(5240, 0),
996 FREQ2FBIN(5320, 0),
997 FREQ2FBIN(5400, 0),
998 FREQ2FBIN(5500, 0),
999 FREQ2FBIN(5700, 0),
1000 FREQ2FBIN(5745, 0),
1001 FREQ2FBIN(5825, 0)
1002 },
1003 .calTarget_freqbin_5GHT40 = {
1004 FREQ2FBIN(5190, 0),
1005 FREQ2FBIN(5230, 0),
1006 FREQ2FBIN(5320, 0),
1007 FREQ2FBIN(5410, 0),
1008 FREQ2FBIN(5510, 0),
1009 FREQ2FBIN(5670, 0),
1010 FREQ2FBIN(5755, 0),
1011 FREQ2FBIN(5825, 0)
1012 },
1013 .calTargetPower5G = {
1014 /* 6-24,36,48,54 */
1015 { {42, 40, 40, 34} },
1016 { {42, 40, 40, 34} },
1017 { {42, 40, 40, 34} },
1018 { {42, 40, 40, 34} },
1019 { {42, 40, 40, 34} },
1020 { {42, 40, 40, 34} },
1021 { {42, 40, 40, 34} },
1022 { {42, 40, 40, 34} },
1023 },
1024 .calTargetPower5GHT20 = {
1025 /*
1026 * 0_8_16,1-3_9-11_17-19,
1027 * 4,5,6,7,12,13,14,15,20,21,22,23
1028 */
1029 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1030 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1031 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1032 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1033 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1034 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1035 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1036 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1037 },
1038 .calTargetPower5GHT40 = {
1039 /*
1040 * 0_8_16,1-3_9-11_17-19,
1041 * 4,5,6,7,12,13,14,15,20,21,22,23
1042 */
1043 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1044 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1045 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1046 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1047 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1048 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1049 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1050 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1051 },
1052 .ctlIndex_5G = {
1053 0x10, 0x16, 0x18, 0x40, 0x46,
1054 0x48, 0x30, 0x36, 0x38
1055 },
1056 .ctl_freqbin_5G = {
1057 {
1058 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1059 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1060 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1061 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1062 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1063 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1064 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1065 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1066 },
1067 {
1068 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1069 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1070 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1071 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1072 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1073 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1074 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1075 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1076 },
1077
1078 {
1079 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1080 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1081 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1082 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1083 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1084 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1085 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1086 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1087 },
1088
1089 {
1090 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1091 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1092 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1093 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1094 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1095 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1096 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1097 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1098 },
1099
1100 {
1101 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1102 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1103 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1104 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1105 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1106 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1107 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1108 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1109 },
1110
1111 {
1112 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1113 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1114 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1115 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1116 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1117 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1118 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1119 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1120 },
1121
1122 {
1123 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1124 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1125 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1126 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1127 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1128 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1129 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1130 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1131 },
1132
1133 {
1134 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1135 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1136 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1137 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1138 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1139 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1140 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1141 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1142 },
1143
1144 {
1145 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1146 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1147 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1148 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1149 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1150 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1151 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1152 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1153 }
1154 },
1155 .ctlPowerData_5G = {
1156 {
1157 {
1158 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1159 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1160 }
1161 },
1162 {
1163 {
1164 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1165 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1166 }
1167 },
1168 {
1169 {
1170 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1171 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1172 }
1173 },
1174 {
1175 {
1176 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1177 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1178 }
1179 },
1180 {
1181 {
1182 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1183 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1184 }
1185 },
1186 {
1187 {
1188 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1189 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1190 }
1191 },
1192 {
1193 {
1194 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1195 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1196 }
1197 },
1198 {
1199 {
1200 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1201 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1202 }
1203 },
1204 {
1205 {
1206 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1207 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1208 }
1209 },
1210 }
1211 };
1212
1213
1214 static const struct ar9300_eeprom ar9300_h112 = {
1215 .eepromVersion = 2,
1216 .templateVersion = 3,
1217 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1218 .custData = {"h112-241-f0000"},
1219 .baseEepHeader = {
1220 .regDmn = { LE16(0), LE16(0x1f) },
1221 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1222 .opCapFlags = {
1223 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1224 .eepMisc = 0,
1225 },
1226 .rfSilent = 0,
1227 .blueToothOptions = 0,
1228 .deviceCap = 0,
1229 .deviceType = 5, /* takes lower byte in eeprom location */
1230 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1231 .params_for_tuning_caps = {0, 0},
1232 .featureEnable = 0x0d,
1233 /*
1234 * bit0 - enable tx temp comp - disabled
1235 * bit1 - enable tx volt comp - disabled
1236 * bit2 - enable fastClock - enabled
1237 * bit3 - enable doubling - enabled
1238 * bit4 - enable internal regulator - disabled
1239 * bit5 - enable pa predistortion - disabled
1240 */
1241 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1242 .eepromWriteEnableGpio = 6,
1243 .wlanDisableGpio = 0,
1244 .wlanLedGpio = 8,
1245 .rxBandSelectGpio = 0xff,
1246 .txrxgain = 0x10,
1247 .swreg = 0,
1248 },
1249 .modalHeader2G = {
1250 /* ar9300_modal_eep_header 2g */
1251 /* 4 idle,t1,t2,b(4 bits per setting) */
1252 .antCtrlCommon = LE32(0x110),
1253 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1254 .antCtrlCommon2 = LE32(0x44444),
1255
1256 /*
1257 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1258 * rx1, rx12, b (2 bits each)
1259 */
1260 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1261
1262 /*
1263 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1264 * for ar9280 (0xa20c/b20c 5:0)
1265 */
1266 .xatten1DB = {0, 0, 0},
1267
1268 /*
1269 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1270 * for ar9280 (0xa20c/b20c 16:12
1271 */
1272 .xatten1Margin = {0, 0, 0},
1273 .tempSlope = 25,
1274 .voltSlope = 0,
1275
1276 /*
1277 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1278 * channels in usual fbin coding format
1279 */
1280 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1281
1282 /*
1283 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1284 * if the register is per chain
1285 */
1286 .noiseFloorThreshCh = {-1, 0, 0},
1287 .ob = {1, 1, 1},/* 3 chain */
1288 .db_stage2 = {1, 1, 1}, /* 3 chain */
1289 .db_stage3 = {0, 0, 0},
1290 .db_stage4 = {0, 0, 0},
1291 .xpaBiasLvl = 0,
1292 .txFrameToDataStart = 0x0e,
1293 .txFrameToPaOn = 0x0e,
1294 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1295 .antennaGain = 0,
1296 .switchSettling = 0x2c,
1297 .adcDesiredSize = -30,
1298 .txEndToXpaOff = 0,
1299 .txEndToRxOn = 0x2,
1300 .txFrameToXpaOn = 0xe,
1301 .thresh62 = 28,
1302 .papdRateMaskHt20 = LE32(0x80c080),
1303 .papdRateMaskHt40 = LE32(0x80c080),
1304 .futureModal = {
1305 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1306 },
1307 },
1308 .base_ext1 = {
1309 .ant_div_control = 0,
1310 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1311 },
1312 .calFreqPier2G = {
1313 FREQ2FBIN(2412, 1),
1314 FREQ2FBIN(2437, 1),
1315 FREQ2FBIN(2472, 1),
1316 },
1317 /* ar9300_cal_data_per_freq_op_loop 2g */
1318 .calPierData2G = {
1319 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1320 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1321 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1322 },
1323 .calTarget_freqbin_Cck = {
1324 FREQ2FBIN(2412, 1),
1325 FREQ2FBIN(2484, 1),
1326 },
1327 .calTarget_freqbin_2G = {
1328 FREQ2FBIN(2412, 1),
1329 FREQ2FBIN(2437, 1),
1330 FREQ2FBIN(2472, 1)
1331 },
1332 .calTarget_freqbin_2GHT20 = {
1333 FREQ2FBIN(2412, 1),
1334 FREQ2FBIN(2437, 1),
1335 FREQ2FBIN(2472, 1)
1336 },
1337 .calTarget_freqbin_2GHT40 = {
1338 FREQ2FBIN(2412, 1),
1339 FREQ2FBIN(2437, 1),
1340 FREQ2FBIN(2472, 1)
1341 },
1342 .calTargetPowerCck = {
1343 /* 1L-5L,5S,11L,11S */
1344 { {34, 34, 34, 34} },
1345 { {34, 34, 34, 34} },
1346 },
1347 .calTargetPower2G = {
1348 /* 6-24,36,48,54 */
1349 { {34, 34, 32, 32} },
1350 { {34, 34, 32, 32} },
1351 { {34, 34, 32, 32} },
1352 },
1353 .calTargetPower2GHT20 = {
1354 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1355 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1356 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1357 },
1358 .calTargetPower2GHT40 = {
1359 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1360 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1361 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1362 },
1363 .ctlIndex_2G = {
1364 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1365 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1366 },
1367 .ctl_freqbin_2G = {
1368 {
1369 FREQ2FBIN(2412, 1),
1370 FREQ2FBIN(2417, 1),
1371 FREQ2FBIN(2457, 1),
1372 FREQ2FBIN(2462, 1)
1373 },
1374 {
1375 FREQ2FBIN(2412, 1),
1376 FREQ2FBIN(2417, 1),
1377 FREQ2FBIN(2462, 1),
1378 0xFF,
1379 },
1380
1381 {
1382 FREQ2FBIN(2412, 1),
1383 FREQ2FBIN(2417, 1),
1384 FREQ2FBIN(2462, 1),
1385 0xFF,
1386 },
1387 {
1388 FREQ2FBIN(2422, 1),
1389 FREQ2FBIN(2427, 1),
1390 FREQ2FBIN(2447, 1),
1391 FREQ2FBIN(2452, 1)
1392 },
1393
1394 {
1395 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1396 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1397 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1398 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1399 },
1400
1401 {
1402 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1403 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1404 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1405 0,
1406 },
1407
1408 {
1409 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1410 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1411 FREQ2FBIN(2472, 1),
1412 0,
1413 },
1414
1415 {
1416 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1417 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1418 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1419 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1420 },
1421
1422 {
1423 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1424 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1425 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1426 },
1427
1428 {
1429 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1430 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1431 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1432 0
1433 },
1434
1435 {
1436 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1437 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1438 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1439 0
1440 },
1441
1442 {
1443 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1444 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1445 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1446 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1447 }
1448 },
1449 .ctlPowerData_2G = {
1450 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1451 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1452 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
1453
1454 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
1455 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1456 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1457
1458 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
1459 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1460 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1461
1462 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1463 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1464 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1465 },
1466 .modalHeader5G = {
1467 /* 4 idle,t1,t2,b (4 bits per setting) */
1468 .antCtrlCommon = LE32(0x220),
1469 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1470 .antCtrlCommon2 = LE32(0x44444),
1471 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1472 .antCtrlChain = {
1473 LE16(0x150), LE16(0x150), LE16(0x150),
1474 },
1475 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1476 .xatten1DB = {0, 0, 0},
1477
1478 /*
1479 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1480 * for merlin (0xa20c/b20c 16:12
1481 */
1482 .xatten1Margin = {0, 0, 0},
1483 .tempSlope = 45,
1484 .voltSlope = 0,
1485 /* spurChans spur channels in usual fbin coding format */
1486 .spurChans = {0, 0, 0, 0, 0},
1487 /* noiseFloorThreshCh Check if the register is per chain */
1488 .noiseFloorThreshCh = {-1, 0, 0},
1489 .ob = {3, 3, 3}, /* 3 chain */
1490 .db_stage2 = {3, 3, 3}, /* 3 chain */
1491 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1492 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1493 .xpaBiasLvl = 0,
1494 .txFrameToDataStart = 0x0e,
1495 .txFrameToPaOn = 0x0e,
1496 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1497 .antennaGain = 0,
1498 .switchSettling = 0x2d,
1499 .adcDesiredSize = -30,
1500 .txEndToXpaOff = 0,
1501 .txEndToRxOn = 0x2,
1502 .txFrameToXpaOn = 0xe,
1503 .thresh62 = 28,
1504 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1505 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1506 .futureModal = {
1507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1508 },
1509 },
1510 .base_ext2 = {
1511 .tempSlopeLow = 40,
1512 .tempSlopeHigh = 50,
1513 .xatten1DBLow = {0, 0, 0},
1514 .xatten1MarginLow = {0, 0, 0},
1515 .xatten1DBHigh = {0, 0, 0},
1516 .xatten1MarginHigh = {0, 0, 0}
1517 },
1518 .calFreqPier5G = {
1519 FREQ2FBIN(5180, 0),
1520 FREQ2FBIN(5220, 0),
1521 FREQ2FBIN(5320, 0),
1522 FREQ2FBIN(5400, 0),
1523 FREQ2FBIN(5500, 0),
1524 FREQ2FBIN(5600, 0),
1525 FREQ2FBIN(5700, 0),
1526 FREQ2FBIN(5825, 0)
1527 },
1528 .calPierData5G = {
1529 {
1530 {0, 0, 0, 0, 0},
1531 {0, 0, 0, 0, 0},
1532 {0, 0, 0, 0, 0},
1533 {0, 0, 0, 0, 0},
1534 {0, 0, 0, 0, 0},
1535 {0, 0, 0, 0, 0},
1536 {0, 0, 0, 0, 0},
1537 {0, 0, 0, 0, 0},
1538 },
1539 {
1540 {0, 0, 0, 0, 0},
1541 {0, 0, 0, 0, 0},
1542 {0, 0, 0, 0, 0},
1543 {0, 0, 0, 0, 0},
1544 {0, 0, 0, 0, 0},
1545 {0, 0, 0, 0, 0},
1546 {0, 0, 0, 0, 0},
1547 {0, 0, 0, 0, 0},
1548 },
1549 {
1550 {0, 0, 0, 0, 0},
1551 {0, 0, 0, 0, 0},
1552 {0, 0, 0, 0, 0},
1553 {0, 0, 0, 0, 0},
1554 {0, 0, 0, 0, 0},
1555 {0, 0, 0, 0, 0},
1556 {0, 0, 0, 0, 0},
1557 {0, 0, 0, 0, 0},
1558 },
1559
1560 },
1561 .calTarget_freqbin_5G = {
1562 FREQ2FBIN(5180, 0),
1563 FREQ2FBIN(5240, 0),
1564 FREQ2FBIN(5320, 0),
1565 FREQ2FBIN(5400, 0),
1566 FREQ2FBIN(5500, 0),
1567 FREQ2FBIN(5600, 0),
1568 FREQ2FBIN(5700, 0),
1569 FREQ2FBIN(5825, 0)
1570 },
1571 .calTarget_freqbin_5GHT20 = {
1572 FREQ2FBIN(5180, 0),
1573 FREQ2FBIN(5240, 0),
1574 FREQ2FBIN(5320, 0),
1575 FREQ2FBIN(5400, 0),
1576 FREQ2FBIN(5500, 0),
1577 FREQ2FBIN(5700, 0),
1578 FREQ2FBIN(5745, 0),
1579 FREQ2FBIN(5825, 0)
1580 },
1581 .calTarget_freqbin_5GHT40 = {
1582 FREQ2FBIN(5180, 0),
1583 FREQ2FBIN(5240, 0),
1584 FREQ2FBIN(5320, 0),
1585 FREQ2FBIN(5400, 0),
1586 FREQ2FBIN(5500, 0),
1587 FREQ2FBIN(5700, 0),
1588 FREQ2FBIN(5745, 0),
1589 FREQ2FBIN(5825, 0)
1590 },
1591 .calTargetPower5G = {
1592 /* 6-24,36,48,54 */
1593 { {30, 30, 28, 24} },
1594 { {30, 30, 28, 24} },
1595 { {30, 30, 28, 24} },
1596 { {30, 30, 28, 24} },
1597 { {30, 30, 28, 24} },
1598 { {30, 30, 28, 24} },
1599 { {30, 30, 28, 24} },
1600 { {30, 30, 28, 24} },
1601 },
1602 .calTargetPower5GHT20 = {
1603 /*
1604 * 0_8_16,1-3_9-11_17-19,
1605 * 4,5,6,7,12,13,14,15,20,21,22,23
1606 */
1607 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1608 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1609 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1610 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1611 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1612 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1613 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1614 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1615 },
1616 .calTargetPower5GHT40 = {
1617 /*
1618 * 0_8_16,1-3_9-11_17-19,
1619 * 4,5,6,7,12,13,14,15,20,21,22,23
1620 */
1621 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1622 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1623 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1624 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1625 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1626 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1627 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1628 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1629 },
1630 .ctlIndex_5G = {
1631 0x10, 0x16, 0x18, 0x40, 0x46,
1632 0x48, 0x30, 0x36, 0x38
1633 },
1634 .ctl_freqbin_5G = {
1635 {
1636 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1637 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1638 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1639 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1640 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1641 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1642 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1643 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1644 },
1645 {
1646 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1647 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1648 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1649 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1650 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1651 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1652 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1653 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1654 },
1655
1656 {
1657 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1658 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1659 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1660 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1661 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1662 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1663 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1664 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1665 },
1666
1667 {
1668 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1669 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1670 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1671 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1672 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1673 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1674 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1675 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1676 },
1677
1678 {
1679 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1680 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1681 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1682 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1683 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1684 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1685 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1686 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1687 },
1688
1689 {
1690 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1691 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1692 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1693 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1694 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1695 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1696 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1697 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1698 },
1699
1700 {
1701 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1702 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1703 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1704 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1705 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1706 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1707 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1708 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1709 },
1710
1711 {
1712 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1713 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1714 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1715 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1716 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1717 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1718 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1719 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1720 },
1721
1722 {
1723 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1724 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1725 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1726 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1727 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1728 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1729 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1730 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1731 }
1732 },
1733 .ctlPowerData_5G = {
1734 {
1735 {
1736 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1737 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1738 }
1739 },
1740 {
1741 {
1742 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1743 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1744 }
1745 },
1746 {
1747 {
1748 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1749 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1750 }
1751 },
1752 {
1753 {
1754 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1755 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1756 }
1757 },
1758 {
1759 {
1760 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1761 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1762 }
1763 },
1764 {
1765 {
1766 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1767 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1768 }
1769 },
1770 {
1771 {
1772 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1773 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1774 }
1775 },
1776 {
1777 {
1778 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1779 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1780 }
1781 },
1782 {
1783 {
1784 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1785 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1786 }
1787 },
1788 }
1789 };
1790
1791
1792 static const struct ar9300_eeprom ar9300_x112 = {
1793 .eepromVersion = 2,
1794 .templateVersion = 5,
1795 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1796 .custData = {"x112-041-f0000"},
1797 .baseEepHeader = {
1798 .regDmn = { LE16(0), LE16(0x1f) },
1799 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1800 .opCapFlags = {
1801 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1802 .eepMisc = 0,
1803 },
1804 .rfSilent = 0,
1805 .blueToothOptions = 0,
1806 .deviceCap = 0,
1807 .deviceType = 5, /* takes lower byte in eeprom location */
1808 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1809 .params_for_tuning_caps = {0, 0},
1810 .featureEnable = 0x0d,
1811 /*
1812 * bit0 - enable tx temp comp - disabled
1813 * bit1 - enable tx volt comp - disabled
1814 * bit2 - enable fastclock - enabled
1815 * bit3 - enable doubling - enabled
1816 * bit4 - enable internal regulator - disabled
1817 * bit5 - enable pa predistortion - disabled
1818 */
1819 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1820 .eepromWriteEnableGpio = 6,
1821 .wlanDisableGpio = 0,
1822 .wlanLedGpio = 8,
1823 .rxBandSelectGpio = 0xff,
1824 .txrxgain = 0x0,
1825 .swreg = 0,
1826 },
1827 .modalHeader2G = {
1828 /* ar9300_modal_eep_header 2g */
1829 /* 4 idle,t1,t2,b(4 bits per setting) */
1830 .antCtrlCommon = LE32(0x110),
1831 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1832 .antCtrlCommon2 = LE32(0x22222),
1833
1834 /*
1835 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1836 * rx1, rx12, b (2 bits each)
1837 */
1838 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1839
1840 /*
1841 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1842 * for ar9280 (0xa20c/b20c 5:0)
1843 */
1844 .xatten1DB = {0x1b, 0x1b, 0x1b},
1845
1846 /*
1847 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1848 * for ar9280 (0xa20c/b20c 16:12
1849 */
1850 .xatten1Margin = {0x15, 0x15, 0x15},
1851 .tempSlope = 50,
1852 .voltSlope = 0,
1853
1854 /*
1855 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1856 * channels in usual fbin coding format
1857 */
1858 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1859
1860 /*
1861 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1862 * if the register is per chain
1863 */
1864 .noiseFloorThreshCh = {-1, 0, 0},
1865 .ob = {1, 1, 1},/* 3 chain */
1866 .db_stage2 = {1, 1, 1}, /* 3 chain */
1867 .db_stage3 = {0, 0, 0},
1868 .db_stage4 = {0, 0, 0},
1869 .xpaBiasLvl = 0,
1870 .txFrameToDataStart = 0x0e,
1871 .txFrameToPaOn = 0x0e,
1872 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1873 .antennaGain = 0,
1874 .switchSettling = 0x2c,
1875 .adcDesiredSize = -30,
1876 .txEndToXpaOff = 0,
1877 .txEndToRxOn = 0x2,
1878 .txFrameToXpaOn = 0xe,
1879 .thresh62 = 28,
1880 .papdRateMaskHt20 = LE32(0x0c80c080),
1881 .papdRateMaskHt40 = LE32(0x0080c080),
1882 .futureModal = {
1883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1884 },
1885 },
1886 .base_ext1 = {
1887 .ant_div_control = 0,
1888 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1889 },
1890 .calFreqPier2G = {
1891 FREQ2FBIN(2412, 1),
1892 FREQ2FBIN(2437, 1),
1893 FREQ2FBIN(2472, 1),
1894 },
1895 /* ar9300_cal_data_per_freq_op_loop 2g */
1896 .calPierData2G = {
1897 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1898 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1899 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1900 },
1901 .calTarget_freqbin_Cck = {
1902 FREQ2FBIN(2412, 1),
1903 FREQ2FBIN(2472, 1),
1904 },
1905 .calTarget_freqbin_2G = {
1906 FREQ2FBIN(2412, 1),
1907 FREQ2FBIN(2437, 1),
1908 FREQ2FBIN(2472, 1)
1909 },
1910 .calTarget_freqbin_2GHT20 = {
1911 FREQ2FBIN(2412, 1),
1912 FREQ2FBIN(2437, 1),
1913 FREQ2FBIN(2472, 1)
1914 },
1915 .calTarget_freqbin_2GHT40 = {
1916 FREQ2FBIN(2412, 1),
1917 FREQ2FBIN(2437, 1),
1918 FREQ2FBIN(2472, 1)
1919 },
1920 .calTargetPowerCck = {
1921 /* 1L-5L,5S,11L,11s */
1922 { {38, 38, 38, 38} },
1923 { {38, 38, 38, 38} },
1924 },
1925 .calTargetPower2G = {
1926 /* 6-24,36,48,54 */
1927 { {38, 38, 36, 34} },
1928 { {38, 38, 36, 34} },
1929 { {38, 38, 34, 32} },
1930 },
1931 .calTargetPower2GHT20 = {
1932 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1933 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1934 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1935 },
1936 .calTargetPower2GHT40 = {
1937 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1938 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1939 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1940 },
1941 .ctlIndex_2G = {
1942 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1943 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1944 },
1945 .ctl_freqbin_2G = {
1946 {
1947 FREQ2FBIN(2412, 1),
1948 FREQ2FBIN(2417, 1),
1949 FREQ2FBIN(2457, 1),
1950 FREQ2FBIN(2462, 1)
1951 },
1952 {
1953 FREQ2FBIN(2412, 1),
1954 FREQ2FBIN(2417, 1),
1955 FREQ2FBIN(2462, 1),
1956 0xFF,
1957 },
1958
1959 {
1960 FREQ2FBIN(2412, 1),
1961 FREQ2FBIN(2417, 1),
1962 FREQ2FBIN(2462, 1),
1963 0xFF,
1964 },
1965 {
1966 FREQ2FBIN(2422, 1),
1967 FREQ2FBIN(2427, 1),
1968 FREQ2FBIN(2447, 1),
1969 FREQ2FBIN(2452, 1)
1970 },
1971
1972 {
1973 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1974 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1975 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1976 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1977 },
1978
1979 {
1980 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1981 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1982 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1983 0,
1984 },
1985
1986 {
1987 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1988 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1989 FREQ2FBIN(2472, 1),
1990 0,
1991 },
1992
1993 {
1994 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1995 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1996 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1997 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1998 },
1999
2000 {
2001 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2002 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2003 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2004 },
2005
2006 {
2007 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2008 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2009 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2010 0
2011 },
2012
2013 {
2014 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2015 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2016 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2017 0
2018 },
2019
2020 {
2021 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2022 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2023 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2024 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2025 }
2026 },
2027 .ctlPowerData_2G = {
2028 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2029 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2030 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2031
2032 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2033 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2034 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2035
2036 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2037 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2038 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2039
2040 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2041 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2042 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2043 },
2044 .modalHeader5G = {
2045 /* 4 idle,t1,t2,b (4 bits per setting) */
2046 .antCtrlCommon = LE32(0x110),
2047 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2048 .antCtrlCommon2 = LE32(0x22222),
2049 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2050 .antCtrlChain = {
2051 LE16(0x0), LE16(0x0), LE16(0x0),
2052 },
2053 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2054 .xatten1DB = {0x13, 0x19, 0x17},
2055
2056 /*
2057 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2058 * for merlin (0xa20c/b20c 16:12
2059 */
2060 .xatten1Margin = {0x19, 0x19, 0x19},
2061 .tempSlope = 70,
2062 .voltSlope = 15,
2063 /* spurChans spur channels in usual fbin coding format */
2064 .spurChans = {0, 0, 0, 0, 0},
2065 /* noiseFloorThreshch check if the register is per chain */
2066 .noiseFloorThreshCh = {-1, 0, 0},
2067 .ob = {3, 3, 3}, /* 3 chain */
2068 .db_stage2 = {3, 3, 3}, /* 3 chain */
2069 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2070 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2071 .xpaBiasLvl = 0,
2072 .txFrameToDataStart = 0x0e,
2073 .txFrameToPaOn = 0x0e,
2074 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2075 .antennaGain = 0,
2076 .switchSettling = 0x2d,
2077 .adcDesiredSize = -30,
2078 .txEndToXpaOff = 0,
2079 .txEndToRxOn = 0x2,
2080 .txFrameToXpaOn = 0xe,
2081 .thresh62 = 28,
2082 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2083 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2084 .futureModal = {
2085 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2086 },
2087 },
2088 .base_ext2 = {
2089 .tempSlopeLow = 72,
2090 .tempSlopeHigh = 105,
2091 .xatten1DBLow = {0x10, 0x14, 0x10},
2092 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2093 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2094 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2095 },
2096 .calFreqPier5G = {
2097 FREQ2FBIN(5180, 0),
2098 FREQ2FBIN(5220, 0),
2099 FREQ2FBIN(5320, 0),
2100 FREQ2FBIN(5400, 0),
2101 FREQ2FBIN(5500, 0),
2102 FREQ2FBIN(5600, 0),
2103 FREQ2FBIN(5700, 0),
2104 FREQ2FBIN(5785, 0)
2105 },
2106 .calPierData5G = {
2107 {
2108 {0, 0, 0, 0, 0},
2109 {0, 0, 0, 0, 0},
2110 {0, 0, 0, 0, 0},
2111 {0, 0, 0, 0, 0},
2112 {0, 0, 0, 0, 0},
2113 {0, 0, 0, 0, 0},
2114 {0, 0, 0, 0, 0},
2115 {0, 0, 0, 0, 0},
2116 },
2117 {
2118 {0, 0, 0, 0, 0},
2119 {0, 0, 0, 0, 0},
2120 {0, 0, 0, 0, 0},
2121 {0, 0, 0, 0, 0},
2122 {0, 0, 0, 0, 0},
2123 {0, 0, 0, 0, 0},
2124 {0, 0, 0, 0, 0},
2125 {0, 0, 0, 0, 0},
2126 },
2127 {
2128 {0, 0, 0, 0, 0},
2129 {0, 0, 0, 0, 0},
2130 {0, 0, 0, 0, 0},
2131 {0, 0, 0, 0, 0},
2132 {0, 0, 0, 0, 0},
2133 {0, 0, 0, 0, 0},
2134 {0, 0, 0, 0, 0},
2135 {0, 0, 0, 0, 0},
2136 },
2137
2138 },
2139 .calTarget_freqbin_5G = {
2140 FREQ2FBIN(5180, 0),
2141 FREQ2FBIN(5220, 0),
2142 FREQ2FBIN(5320, 0),
2143 FREQ2FBIN(5400, 0),
2144 FREQ2FBIN(5500, 0),
2145 FREQ2FBIN(5600, 0),
2146 FREQ2FBIN(5725, 0),
2147 FREQ2FBIN(5825, 0)
2148 },
2149 .calTarget_freqbin_5GHT20 = {
2150 FREQ2FBIN(5180, 0),
2151 FREQ2FBIN(5220, 0),
2152 FREQ2FBIN(5320, 0),
2153 FREQ2FBIN(5400, 0),
2154 FREQ2FBIN(5500, 0),
2155 FREQ2FBIN(5600, 0),
2156 FREQ2FBIN(5725, 0),
2157 FREQ2FBIN(5825, 0)
2158 },
2159 .calTarget_freqbin_5GHT40 = {
2160 FREQ2FBIN(5180, 0),
2161 FREQ2FBIN(5220, 0),
2162 FREQ2FBIN(5320, 0),
2163 FREQ2FBIN(5400, 0),
2164 FREQ2FBIN(5500, 0),
2165 FREQ2FBIN(5600, 0),
2166 FREQ2FBIN(5725, 0),
2167 FREQ2FBIN(5825, 0)
2168 },
2169 .calTargetPower5G = {
2170 /* 6-24,36,48,54 */
2171 { {32, 32, 28, 26} },
2172 { {32, 32, 28, 26} },
2173 { {32, 32, 28, 26} },
2174 { {32, 32, 26, 24} },
2175 { {32, 32, 26, 24} },
2176 { {32, 32, 24, 22} },
2177 { {30, 30, 24, 22} },
2178 { {30, 30, 24, 22} },
2179 },
2180 .calTargetPower5GHT20 = {
2181 /*
2182 * 0_8_16,1-3_9-11_17-19,
2183 * 4,5,6,7,12,13,14,15,20,21,22,23
2184 */
2185 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2186 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2187 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2188 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2189 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2190 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2191 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2192 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2193 },
2194 .calTargetPower5GHT40 = {
2195 /*
2196 * 0_8_16,1-3_9-11_17-19,
2197 * 4,5,6,7,12,13,14,15,20,21,22,23
2198 */
2199 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2200 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2201 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2202 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2203 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2204 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2205 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2206 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2207 },
2208 .ctlIndex_5G = {
2209 0x10, 0x16, 0x18, 0x40, 0x46,
2210 0x48, 0x30, 0x36, 0x38
2211 },
2212 .ctl_freqbin_5G = {
2213 {
2214 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2215 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2216 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2217 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2218 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2219 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2220 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2221 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2222 },
2223 {
2224 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2225 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2226 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2227 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2228 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2229 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2230 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2231 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2232 },
2233
2234 {
2235 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2236 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2237 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2238 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2239 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2240 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2241 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2242 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2243 },
2244
2245 {
2246 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2247 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2248 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2249 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2250 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2251 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2252 /* Data[3].ctledges[6].bchannel */ 0xFF,
2253 /* Data[3].ctledges[7].bchannel */ 0xFF,
2254 },
2255
2256 {
2257 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2258 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2259 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2260 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2261 /* Data[4].ctledges[4].bchannel */ 0xFF,
2262 /* Data[4].ctledges[5].bchannel */ 0xFF,
2263 /* Data[4].ctledges[6].bchannel */ 0xFF,
2264 /* Data[4].ctledges[7].bchannel */ 0xFF,
2265 },
2266
2267 {
2268 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2269 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2270 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2271 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2272 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2273 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2274 /* Data[5].ctledges[6].bchannel */ 0xFF,
2275 /* Data[5].ctledges[7].bchannel */ 0xFF
2276 },
2277
2278 {
2279 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2280 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2281 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2282 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2283 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2284 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2285 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2286 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2287 },
2288
2289 {
2290 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2291 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2292 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2293 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2294 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2295 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2296 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2297 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2298 },
2299
2300 {
2301 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2302 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2303 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2304 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2305 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2306 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2307 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2308 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2309 }
2310 },
2311 .ctlPowerData_5G = {
2312 {
2313 {
2314 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2315 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2316 }
2317 },
2318 {
2319 {
2320 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2321 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2322 }
2323 },
2324 {
2325 {
2326 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2327 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2328 }
2329 },
2330 {
2331 {
2332 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2333 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2334 }
2335 },
2336 {
2337 {
2338 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2339 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2340 }
2341 },
2342 {
2343 {
2344 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2345 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2346 }
2347 },
2348 {
2349 {
2350 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2351 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2352 }
2353 },
2354 {
2355 {
2356 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2357 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2358 }
2359 },
2360 {
2361 {
2362 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2363 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2364 }
2365 },
2366 }
2367 };
2368
2369 static const struct ar9300_eeprom ar9300_h116 = {
2370 .eepromVersion = 2,
2371 .templateVersion = 4,
2372 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2373 .custData = {"h116-041-f0000"},
2374 .baseEepHeader = {
2375 .regDmn = { LE16(0), LE16(0x1f) },
2376 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2377 .opCapFlags = {
2378 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
2379 .eepMisc = 0,
2380 },
2381 .rfSilent = 0,
2382 .blueToothOptions = 0,
2383 .deviceCap = 0,
2384 .deviceType = 5, /* takes lower byte in eeprom location */
2385 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2386 .params_for_tuning_caps = {0, 0},
2387 .featureEnable = 0x0d,
2388 /*
2389 * bit0 - enable tx temp comp - disabled
2390 * bit1 - enable tx volt comp - disabled
2391 * bit2 - enable fastClock - enabled
2392 * bit3 - enable doubling - enabled
2393 * bit4 - enable internal regulator - disabled
2394 * bit5 - enable pa predistortion - disabled
2395 */
2396 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2397 .eepromWriteEnableGpio = 6,
2398 .wlanDisableGpio = 0,
2399 .wlanLedGpio = 8,
2400 .rxBandSelectGpio = 0xff,
2401 .txrxgain = 0x10,
2402 .swreg = 0,
2403 },
2404 .modalHeader2G = {
2405 /* ar9300_modal_eep_header 2g */
2406 /* 4 idle,t1,t2,b(4 bits per setting) */
2407 .antCtrlCommon = LE32(0x110),
2408 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2409 .antCtrlCommon2 = LE32(0x44444),
2410
2411 /*
2412 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2413 * rx1, rx12, b (2 bits each)
2414 */
2415 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2416
2417 /*
2418 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2419 * for ar9280 (0xa20c/b20c 5:0)
2420 */
2421 .xatten1DB = {0x1f, 0x1f, 0x1f},
2422
2423 /*
2424 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2425 * for ar9280 (0xa20c/b20c 16:12
2426 */
2427 .xatten1Margin = {0x12, 0x12, 0x12},
2428 .tempSlope = 25,
2429 .voltSlope = 0,
2430
2431 /*
2432 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2433 * channels in usual fbin coding format
2434 */
2435 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2436
2437 /*
2438 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2439 * if the register is per chain
2440 */
2441 .noiseFloorThreshCh = {-1, 0, 0},
2442 .ob = {1, 1, 1},/* 3 chain */
2443 .db_stage2 = {1, 1, 1}, /* 3 chain */
2444 .db_stage3 = {0, 0, 0},
2445 .db_stage4 = {0, 0, 0},
2446 .xpaBiasLvl = 0,
2447 .txFrameToDataStart = 0x0e,
2448 .txFrameToPaOn = 0x0e,
2449 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2450 .antennaGain = 0,
2451 .switchSettling = 0x2c,
2452 .adcDesiredSize = -30,
2453 .txEndToXpaOff = 0,
2454 .txEndToRxOn = 0x2,
2455 .txFrameToXpaOn = 0xe,
2456 .thresh62 = 28,
2457 .papdRateMaskHt20 = LE32(0x0c80C080),
2458 .papdRateMaskHt40 = LE32(0x0080C080),
2459 .futureModal = {
2460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2461 },
2462 },
2463 .base_ext1 = {
2464 .ant_div_control = 0,
2465 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2466 },
2467 .calFreqPier2G = {
2468 FREQ2FBIN(2412, 1),
2469 FREQ2FBIN(2437, 1),
2470 FREQ2FBIN(2472, 1),
2471 },
2472 /* ar9300_cal_data_per_freq_op_loop 2g */
2473 .calPierData2G = {
2474 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2475 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2476 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2477 },
2478 .calTarget_freqbin_Cck = {
2479 FREQ2FBIN(2412, 1),
2480 FREQ2FBIN(2472, 1),
2481 },
2482 .calTarget_freqbin_2G = {
2483 FREQ2FBIN(2412, 1),
2484 FREQ2FBIN(2437, 1),
2485 FREQ2FBIN(2472, 1)
2486 },
2487 .calTarget_freqbin_2GHT20 = {
2488 FREQ2FBIN(2412, 1),
2489 FREQ2FBIN(2437, 1),
2490 FREQ2FBIN(2472, 1)
2491 },
2492 .calTarget_freqbin_2GHT40 = {
2493 FREQ2FBIN(2412, 1),
2494 FREQ2FBIN(2437, 1),
2495 FREQ2FBIN(2472, 1)
2496 },
2497 .calTargetPowerCck = {
2498 /* 1L-5L,5S,11L,11S */
2499 { {34, 34, 34, 34} },
2500 { {34, 34, 34, 34} },
2501 },
2502 .calTargetPower2G = {
2503 /* 6-24,36,48,54 */
2504 { {34, 34, 32, 32} },
2505 { {34, 34, 32, 32} },
2506 { {34, 34, 32, 32} },
2507 },
2508 .calTargetPower2GHT20 = {
2509 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2510 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2511 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2512 },
2513 .calTargetPower2GHT40 = {
2514 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2515 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2516 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2517 },
2518 .ctlIndex_2G = {
2519 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2520 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2521 },
2522 .ctl_freqbin_2G = {
2523 {
2524 FREQ2FBIN(2412, 1),
2525 FREQ2FBIN(2417, 1),
2526 FREQ2FBIN(2457, 1),
2527 FREQ2FBIN(2462, 1)
2528 },
2529 {
2530 FREQ2FBIN(2412, 1),
2531 FREQ2FBIN(2417, 1),
2532 FREQ2FBIN(2462, 1),
2533 0xFF,
2534 },
2535
2536 {
2537 FREQ2FBIN(2412, 1),
2538 FREQ2FBIN(2417, 1),
2539 FREQ2FBIN(2462, 1),
2540 0xFF,
2541 },
2542 {
2543 FREQ2FBIN(2422, 1),
2544 FREQ2FBIN(2427, 1),
2545 FREQ2FBIN(2447, 1),
2546 FREQ2FBIN(2452, 1)
2547 },
2548
2549 {
2550 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2551 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2552 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2553 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2554 },
2555
2556 {
2557 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2558 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2559 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2560 0,
2561 },
2562
2563 {
2564 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2565 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2566 FREQ2FBIN(2472, 1),
2567 0,
2568 },
2569
2570 {
2571 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2572 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2573 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2574 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2575 },
2576
2577 {
2578 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2579 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2580 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2581 },
2582
2583 {
2584 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2585 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2586 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2587 0
2588 },
2589
2590 {
2591 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2592 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2593 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2594 0
2595 },
2596
2597 {
2598 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2599 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2600 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2601 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2602 }
2603 },
2604 .ctlPowerData_2G = {
2605 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2606 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2607 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2608
2609 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2610 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2611 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2612
2613 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2614 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2615 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2616
2617 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2618 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2619 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2620 },
2621 .modalHeader5G = {
2622 /* 4 idle,t1,t2,b (4 bits per setting) */
2623 .antCtrlCommon = LE32(0x220),
2624 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2625 .antCtrlCommon2 = LE32(0x44444),
2626 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2627 .antCtrlChain = {
2628 LE16(0x150), LE16(0x150), LE16(0x150),
2629 },
2630 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2631 .xatten1DB = {0x19, 0x19, 0x19},
2632
2633 /*
2634 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2635 * for merlin (0xa20c/b20c 16:12
2636 */
2637 .xatten1Margin = {0x14, 0x14, 0x14},
2638 .tempSlope = 70,
2639 .voltSlope = 0,
2640 /* spurChans spur channels in usual fbin coding format */
2641 .spurChans = {0, 0, 0, 0, 0},
2642 /* noiseFloorThreshCh Check if the register is per chain */
2643 .noiseFloorThreshCh = {-1, 0, 0},
2644 .ob = {3, 3, 3}, /* 3 chain */
2645 .db_stage2 = {3, 3, 3}, /* 3 chain */
2646 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2647 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2648 .xpaBiasLvl = 0,
2649 .txFrameToDataStart = 0x0e,
2650 .txFrameToPaOn = 0x0e,
2651 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2652 .antennaGain = 0,
2653 .switchSettling = 0x2d,
2654 .adcDesiredSize = -30,
2655 .txEndToXpaOff = 0,
2656 .txEndToRxOn = 0x2,
2657 .txFrameToXpaOn = 0xe,
2658 .thresh62 = 28,
2659 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2660 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2661 .futureModal = {
2662 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2663 },
2664 },
2665 .base_ext2 = {
2666 .tempSlopeLow = 35,
2667 .tempSlopeHigh = 50,
2668 .xatten1DBLow = {0, 0, 0},
2669 .xatten1MarginLow = {0, 0, 0},
2670 .xatten1DBHigh = {0, 0, 0},
2671 .xatten1MarginHigh = {0, 0, 0}
2672 },
2673 .calFreqPier5G = {
2674 FREQ2FBIN(5180, 0),
2675 FREQ2FBIN(5220, 0),
2676 FREQ2FBIN(5320, 0),
2677 FREQ2FBIN(5400, 0),
2678 FREQ2FBIN(5500, 0),
2679 FREQ2FBIN(5600, 0),
2680 FREQ2FBIN(5700, 0),
2681 FREQ2FBIN(5785, 0)
2682 },
2683 .calPierData5G = {
2684 {
2685 {0, 0, 0, 0, 0},
2686 {0, 0, 0, 0, 0},
2687 {0, 0, 0, 0, 0},
2688 {0, 0, 0, 0, 0},
2689 {0, 0, 0, 0, 0},
2690 {0, 0, 0, 0, 0},
2691 {0, 0, 0, 0, 0},
2692 {0, 0, 0, 0, 0},
2693 },
2694 {
2695 {0, 0, 0, 0, 0},
2696 {0, 0, 0, 0, 0},
2697 {0, 0, 0, 0, 0},
2698 {0, 0, 0, 0, 0},
2699 {0, 0, 0, 0, 0},
2700 {0, 0, 0, 0, 0},
2701 {0, 0, 0, 0, 0},
2702 {0, 0, 0, 0, 0},
2703 },
2704 {
2705 {0, 0, 0, 0, 0},
2706 {0, 0, 0, 0, 0},
2707 {0, 0, 0, 0, 0},
2708 {0, 0, 0, 0, 0},
2709 {0, 0, 0, 0, 0},
2710 {0, 0, 0, 0, 0},
2711 {0, 0, 0, 0, 0},
2712 {0, 0, 0, 0, 0},
2713 },
2714
2715 },
2716 .calTarget_freqbin_5G = {
2717 FREQ2FBIN(5180, 0),
2718 FREQ2FBIN(5240, 0),
2719 FREQ2FBIN(5320, 0),
2720 FREQ2FBIN(5400, 0),
2721 FREQ2FBIN(5500, 0),
2722 FREQ2FBIN(5600, 0),
2723 FREQ2FBIN(5700, 0),
2724 FREQ2FBIN(5825, 0)
2725 },
2726 .calTarget_freqbin_5GHT20 = {
2727 FREQ2FBIN(5180, 0),
2728 FREQ2FBIN(5240, 0),
2729 FREQ2FBIN(5320, 0),
2730 FREQ2FBIN(5400, 0),
2731 FREQ2FBIN(5500, 0),
2732 FREQ2FBIN(5700, 0),
2733 FREQ2FBIN(5745, 0),
2734 FREQ2FBIN(5825, 0)
2735 },
2736 .calTarget_freqbin_5GHT40 = {
2737 FREQ2FBIN(5180, 0),
2738 FREQ2FBIN(5240, 0),
2739 FREQ2FBIN(5320, 0),
2740 FREQ2FBIN(5400, 0),
2741 FREQ2FBIN(5500, 0),
2742 FREQ2FBIN(5700, 0),
2743 FREQ2FBIN(5745, 0),
2744 FREQ2FBIN(5825, 0)
2745 },
2746 .calTargetPower5G = {
2747 /* 6-24,36,48,54 */
2748 { {30, 30, 28, 24} },
2749 { {30, 30, 28, 24} },
2750 { {30, 30, 28, 24} },
2751 { {30, 30, 28, 24} },
2752 { {30, 30, 28, 24} },
2753 { {30, 30, 28, 24} },
2754 { {30, 30, 28, 24} },
2755 { {30, 30, 28, 24} },
2756 },
2757 .calTargetPower5GHT20 = {
2758 /*
2759 * 0_8_16,1-3_9-11_17-19,
2760 * 4,5,6,7,12,13,14,15,20,21,22,23
2761 */
2762 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2763 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2764 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2765 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2766 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2767 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2768 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2769 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2770 },
2771 .calTargetPower5GHT40 = {
2772 /*
2773 * 0_8_16,1-3_9-11_17-19,
2774 * 4,5,6,7,12,13,14,15,20,21,22,23
2775 */
2776 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2777 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2778 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2779 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2780 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2781 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2782 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2783 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2784 },
2785 .ctlIndex_5G = {
2786 0x10, 0x16, 0x18, 0x40, 0x46,
2787 0x48, 0x30, 0x36, 0x38
2788 },
2789 .ctl_freqbin_5G = {
2790 {
2791 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2792 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2793 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2794 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2795 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2796 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2797 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2798 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2799 },
2800 {
2801 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2802 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2803 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2804 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2805 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2806 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2807 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2808 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2809 },
2810
2811 {
2812 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2813 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2814 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2815 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2816 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2817 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2818 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2819 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2820 },
2821
2822 {
2823 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2824 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2825 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2826 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2827 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2828 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2829 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2830 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2831 },
2832
2833 {
2834 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2835 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2836 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2837 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2838 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2839 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2840 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2841 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2842 },
2843
2844 {
2845 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2846 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2847 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2848 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2849 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2850 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2851 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2852 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2853 },
2854
2855 {
2856 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2857 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2858 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2859 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2860 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2861 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2862 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2863 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2864 },
2865
2866 {
2867 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2868 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2869 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2870 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2871 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2872 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2873 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2874 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2875 },
2876
2877 {
2878 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2879 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2880 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2881 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2882 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2883 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2884 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2885 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2886 }
2887 },
2888 .ctlPowerData_5G = {
2889 {
2890 {
2891 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2892 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2893 }
2894 },
2895 {
2896 {
2897 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2898 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2899 }
2900 },
2901 {
2902 {
2903 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2904 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2905 }
2906 },
2907 {
2908 {
2909 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2910 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2911 }
2912 },
2913 {
2914 {
2915 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2916 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2917 }
2918 },
2919 {
2920 {
2921 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2922 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2923 }
2924 },
2925 {
2926 {
2927 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2928 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2929 }
2930 },
2931 {
2932 {
2933 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2934 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2935 }
2936 },
2937 {
2938 {
2939 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2940 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2941 }
2942 },
2943 }
2944 };
2945
2946
2947 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2948 &ar9300_default,
2949 &ar9300_x112,
2950 &ar9300_h116,
2951 &ar9300_h112,
2952 &ar9300_x113,
2953 };
2954
2955 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2956 {
2957 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2958 int it;
2959
2960 for (it = 0; it < N_LOOP; it++)
2961 if (ar9300_eep_templates[it]->templateVersion == id)
2962 return ar9300_eep_templates[it];
2963 return NULL;
2964 #undef N_LOOP
2965 }
2966
2967
2968 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2969 {
2970 if (fbin == AR9300_BCHAN_UNUSED)
2971 return fbin;
2972
2973 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2974 }
2975
2976 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2977 {
2978 return 0;
2979 }
2980
2981 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2982 enum eeprom_param param)
2983 {
2984 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2985 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2986
2987 switch (param) {
2988 case EEP_MAC_LSW:
2989 return eep->macAddr[0] << 8 | eep->macAddr[1];
2990 case EEP_MAC_MID:
2991 return eep->macAddr[2] << 8 | eep->macAddr[3];
2992 case EEP_MAC_MSW:
2993 return eep->macAddr[4] << 8 | eep->macAddr[5];
2994 case EEP_REG_0:
2995 return le16_to_cpu(pBase->regDmn[0]);
2996 case EEP_REG_1:
2997 return le16_to_cpu(pBase->regDmn[1]);
2998 case EEP_OP_CAP:
2999 return pBase->deviceCap;
3000 case EEP_OP_MODE:
3001 return pBase->opCapFlags.opFlags;
3002 case EEP_RF_SILENT:
3003 return pBase->rfSilent;
3004 case EEP_TX_MASK:
3005 return (pBase->txrxMask >> 4) & 0xf;
3006 case EEP_RX_MASK:
3007 return pBase->txrxMask & 0xf;
3008 case EEP_DRIVE_STRENGTH:
3009 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3010 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3011 case EEP_INTERNAL_REGULATOR:
3012 /* Bit 4 is internal regulator flag */
3013 return (pBase->featureEnable & 0x10) >> 4;
3014 case EEP_SWREG:
3015 return le32_to_cpu(pBase->swreg);
3016 case EEP_PAPRD:
3017 return !!(pBase->featureEnable & BIT(5));
3018 default:
3019 return 0;
3020 }
3021 }
3022
3023 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3024 u8 *buffer)
3025 {
3026 u16 val;
3027
3028 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3029 return false;
3030
3031 *buffer = (val >> (8 * (address % 2))) & 0xff;
3032 return true;
3033 }
3034
3035 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3036 u8 *buffer)
3037 {
3038 u16 val;
3039
3040 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3041 return false;
3042
3043 buffer[0] = val >> 8;
3044 buffer[1] = val & 0xff;
3045
3046 return true;
3047 }
3048
3049 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3050 int count)
3051 {
3052 struct ath_common *common = ath9k_hw_common(ah);
3053 int i;
3054
3055 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3056 ath_print(common, ATH_DBG_EEPROM,
3057 "eeprom address not in range\n");
3058 return false;
3059 }
3060
3061 /*
3062 * Since we're reading the bytes in reverse order from a little-endian
3063 * word stream, an even address means we only use the lower half of
3064 * the 16-bit word at that address
3065 */
3066 if (address % 2 == 0) {
3067 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3068 goto error;
3069
3070 count--;
3071 }
3072
3073 for (i = 0; i < count / 2; i++) {
3074 if (!ar9300_eeprom_read_word(common, address, buffer))
3075 goto error;
3076
3077 address -= 2;
3078 buffer += 2;
3079 }
3080
3081 if (count % 2)
3082 if (!ar9300_eeprom_read_byte(common, address, buffer))
3083 goto error;
3084
3085 return true;
3086
3087 error:
3088 ath_print(common, ATH_DBG_EEPROM,
3089 "unable to read eeprom region at offset %d\n", address);
3090 return false;
3091 }
3092
3093 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3094 int *length, int *major, int *minor)
3095 {
3096 unsigned long value[4];
3097
3098 value[0] = best[0];
3099 value[1] = best[1];
3100 value[2] = best[2];
3101 value[3] = best[3];
3102 *code = ((value[0] >> 5) & 0x0007);
3103 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3104 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3105 *major = (value[2] & 0x000f);
3106 *minor = (value[3] & 0x00ff);
3107 }
3108
3109 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3110 {
3111 int it, checksum = 0;
3112
3113 for (it = 0; it < dsize; it++) {
3114 checksum += data[it];
3115 checksum &= 0xffff;
3116 }
3117
3118 return checksum;
3119 }
3120
3121 static bool ar9300_uncompress_block(struct ath_hw *ah,
3122 u8 *mptr,
3123 int mdataSize,
3124 u8 *block,
3125 int size)
3126 {
3127 int it;
3128 int spot;
3129 int offset;
3130 int length;
3131 struct ath_common *common = ath9k_hw_common(ah);
3132
3133 spot = 0;
3134
3135 for (it = 0; it < size; it += (length+2)) {
3136 offset = block[it];
3137 offset &= 0xff;
3138 spot += offset;
3139 length = block[it+1];
3140 length &= 0xff;
3141
3142 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3143 ath_print(common, ATH_DBG_EEPROM,
3144 "Restore at %d: spot=%d "
3145 "offset=%d length=%d\n",
3146 it, spot, offset, length);
3147 memcpy(&mptr[spot], &block[it+2], length);
3148 spot += length;
3149 } else if (length > 0) {
3150 ath_print(common, ATH_DBG_EEPROM,
3151 "Bad restore at %d: spot=%d "
3152 "offset=%d length=%d\n",
3153 it, spot, offset, length);
3154 return false;
3155 }
3156 }
3157 return true;
3158 }
3159
3160 static int ar9300_compress_decision(struct ath_hw *ah,
3161 int it,
3162 int code,
3163 int reference,
3164 u8 *mptr,
3165 u8 *word, int length, int mdata_size)
3166 {
3167 struct ath_common *common = ath9k_hw_common(ah);
3168 u8 *dptr;
3169 const struct ar9300_eeprom *eep = NULL;
3170
3171 switch (code) {
3172 case _CompressNone:
3173 if (length != mdata_size) {
3174 ath_print(common, ATH_DBG_EEPROM,
3175 "EEPROM structure size mismatch"
3176 "memory=%d eeprom=%d\n", mdata_size, length);
3177 return -1;
3178 }
3179 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3180 ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
3181 " uncompressed, length %d\n", it, length);
3182 break;
3183 case _CompressBlock:
3184 if (reference == 0) {
3185 dptr = mptr;
3186 } else {
3187 eep = ar9003_eeprom_struct_find_by_id(reference);
3188 if (eep == NULL) {
3189 ath_print(common, ATH_DBG_EEPROM,
3190 "cant find reference eeprom"
3191 "struct %d\n", reference);
3192 return -1;
3193 }
3194 memcpy(mptr, eep, mdata_size);
3195 }
3196 ath_print(common, ATH_DBG_EEPROM,
3197 "restore eeprom %d: block, reference %d,"
3198 " length %d\n", it, reference, length);
3199 ar9300_uncompress_block(ah, mptr, mdata_size,
3200 (u8 *) (word + COMP_HDR_LEN), length);
3201 break;
3202 default:
3203 ath_print(common, ATH_DBG_EEPROM, "unknown compression"
3204 " code %d\n", code);
3205 return -1;
3206 }
3207 return 0;
3208 }
3209
3210 /*
3211 * Read the configuration data from the eeprom.
3212 * The data can be put in any specified memory buffer.
3213 *
3214 * Returns -1 on error.
3215 * Returns address of next memory location on success.
3216 */
3217 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3218 u8 *mptr, int mdata_size)
3219 {
3220 #define MDEFAULT 15
3221 #define MSTATE 100
3222 int cptr;
3223 u8 *word;
3224 int code;
3225 int reference, length, major, minor;
3226 int osize;
3227 int it;
3228 u16 checksum, mchecksum;
3229 struct ath_common *common = ath9k_hw_common(ah);
3230
3231 word = kzalloc(2048, GFP_KERNEL);
3232 if (!word)
3233 return -1;
3234
3235 memcpy(mptr, &ar9300_default, mdata_size);
3236
3237 cptr = AR9300_BASE_ADDR;
3238 for (it = 0; it < MSTATE; it++) {
3239 if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
3240 goto fail;
3241
3242 if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
3243 word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
3244 && word[2] == 0xff && word[3] == 0xff))
3245 break;
3246
3247 ar9300_comp_hdr_unpack(word, &code, &reference,
3248 &length, &major, &minor);
3249 ath_print(common, ATH_DBG_EEPROM,
3250 "Found block at %x: code=%d ref=%d"
3251 "length=%d major=%d minor=%d\n", cptr, code,
3252 reference, length, major, minor);
3253 if (length >= 1024) {
3254 ath_print(common, ATH_DBG_EEPROM,
3255 "Skipping bad header\n");
3256 cptr -= COMP_HDR_LEN;
3257 continue;
3258 }
3259
3260 osize = length;
3261 ar9300_read_eeprom(ah, cptr, word,
3262 COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3263 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3264 mchecksum = word[COMP_HDR_LEN + osize] |
3265 (word[COMP_HDR_LEN + osize + 1] << 8);
3266 ath_print(common, ATH_DBG_EEPROM,
3267 "checksum %x %x\n", checksum, mchecksum);
3268 if (checksum == mchecksum) {
3269 ar9300_compress_decision(ah, it, code, reference, mptr,
3270 word, length, mdata_size);
3271 } else {
3272 ath_print(common, ATH_DBG_EEPROM,
3273 "skipping block with bad checksum\n");
3274 }
3275 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3276 }
3277
3278 kfree(word);
3279 return cptr;
3280
3281 fail:
3282 kfree(word);
3283 return -1;
3284 }
3285
3286 /*
3287 * Restore the configuration structure by reading the eeprom.
3288 * This function destroys any existing in-memory structure
3289 * content.
3290 */
3291 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3292 {
3293 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3294
3295 if (ar9300_eeprom_restore_internal(ah, mptr,
3296 sizeof(struct ar9300_eeprom)) < 0)
3297 return false;
3298
3299 return true;
3300 }
3301
3302 /* XXX: review hardware docs */
3303 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3304 {
3305 return ah->eeprom.ar9300_eep.eepromVersion;
3306 }
3307
3308 /* XXX: could be read from the eepromVersion, not sure yet */
3309 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3310 {
3311 return 0;
3312 }
3313
3314 static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
3315 enum ath9k_hal_freq_band freq_band)
3316 {
3317 return 1;
3318 }
3319
3320 static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
3321 struct ath9k_channel *chan)
3322 {
3323 return -EINVAL;
3324 }
3325
3326 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3327 {
3328 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3329
3330 if (is2ghz)
3331 return eep->modalHeader2G.xpaBiasLvl;
3332 else
3333 return eep->modalHeader5G.xpaBiasLvl;
3334 }
3335
3336 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3337 {
3338 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3339 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
3340 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
3341 ((bias >> 2) & 0x3));
3342 }
3343
3344 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3345 {
3346 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3347 __le32 val;
3348
3349 if (is2ghz)
3350 val = eep->modalHeader2G.antCtrlCommon;
3351 else
3352 val = eep->modalHeader5G.antCtrlCommon;
3353 return le32_to_cpu(val);
3354 }
3355
3356 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3357 {
3358 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3359 __le32 val;
3360
3361 if (is2ghz)
3362 val = eep->modalHeader2G.antCtrlCommon2;
3363 else
3364 val = eep->modalHeader5G.antCtrlCommon2;
3365 return le32_to_cpu(val);
3366 }
3367
3368 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3369 int chain,
3370 bool is2ghz)
3371 {
3372 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3373 __le16 val = 0;
3374
3375 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3376 if (is2ghz)
3377 val = eep->modalHeader2G.antCtrlChain[chain];
3378 else
3379 val = eep->modalHeader5G.antCtrlChain[chain];
3380 }
3381
3382 return le16_to_cpu(val);
3383 }
3384
3385 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3386 {
3387 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3388 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3389
3390 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3391 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3392
3393 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3394 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3395
3396 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3397 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
3398
3399 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3400 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
3401 }
3402
3403 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3404 {
3405 int drive_strength;
3406 unsigned long reg;
3407
3408 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3409
3410 if (!drive_strength)
3411 return;
3412
3413 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3414 reg &= ~0x00ffffc0;
3415 reg |= 0x5 << 21;
3416 reg |= 0x5 << 18;
3417 reg |= 0x5 << 15;
3418 reg |= 0x5 << 12;
3419 reg |= 0x5 << 9;
3420 reg |= 0x5 << 6;
3421 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3422
3423 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3424 reg &= ~0xffffffe0;
3425 reg |= 0x5 << 29;
3426 reg |= 0x5 << 26;
3427 reg |= 0x5 << 23;
3428 reg |= 0x5 << 20;
3429 reg |= 0x5 << 17;
3430 reg |= 0x5 << 14;
3431 reg |= 0x5 << 11;
3432 reg |= 0x5 << 8;
3433 reg |= 0x5 << 5;
3434 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3435
3436 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3437 reg &= ~0xff800000;
3438 reg |= 0x5 << 29;
3439 reg |= 0x5 << 26;
3440 reg |= 0x5 << 23;
3441 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3442 }
3443
3444 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3445 {
3446 int internal_regulator =
3447 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3448
3449 if (internal_regulator) {
3450 /* Internal regulator is ON. Write swreg register. */
3451 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3452 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3453 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3454 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3455 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3456 /* Set REG_CONTROL1.SWREG_PROGRAM */
3457 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3458 REG_READ(ah,
3459 AR_RTC_REG_CONTROL1) |
3460 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3461 } else {
3462 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3463 (REG_READ(ah,
3464 AR_RTC_SLEEP_CLK) |
3465 AR_RTC_FORCE_SWREG_PRD));
3466 }
3467 }
3468
3469 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3470 struct ath9k_channel *chan)
3471 {
3472 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3473 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3474 ar9003_hw_drive_strength_apply(ah);
3475 ar9003_hw_internal_regulator_apply(ah);
3476 }
3477
3478 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3479 struct ath9k_channel *chan)
3480 {
3481 }
3482
3483 /*
3484 * Returns the interpolated y value corresponding to the specified x value
3485 * from the np ordered pairs of data (px,py).
3486 * The pairs do not have to be in any order.
3487 * If the specified x value is less than any of the px,
3488 * the returned y value is equal to the py for the lowest px.
3489 * If the specified x value is greater than any of the px,
3490 * the returned y value is equal to the py for the highest px.
3491 */
3492 static int ar9003_hw_power_interpolate(int32_t x,
3493 int32_t *px, int32_t *py, u_int16_t np)
3494 {
3495 int ip = 0;
3496 int lx = 0, ly = 0, lhave = 0;
3497 int hx = 0, hy = 0, hhave = 0;
3498 int dx = 0;
3499 int y = 0;
3500
3501 lhave = 0;
3502 hhave = 0;
3503
3504 /* identify best lower and higher x calibration measurement */
3505 for (ip = 0; ip < np; ip++) {
3506 dx = x - px[ip];
3507
3508 /* this measurement is higher than our desired x */
3509 if (dx <= 0) {
3510 if (!hhave || dx > (x - hx)) {
3511 /* new best higher x measurement */
3512 hx = px[ip];
3513 hy = py[ip];
3514 hhave = 1;
3515 }
3516 }
3517 /* this measurement is lower than our desired x */
3518 if (dx >= 0) {
3519 if (!lhave || dx < (x - lx)) {
3520 /* new best lower x measurement */
3521 lx = px[ip];
3522 ly = py[ip];
3523 lhave = 1;
3524 }
3525 }
3526 }
3527
3528 /* the low x is good */
3529 if (lhave) {
3530 /* so is the high x */
3531 if (hhave) {
3532 /* they're the same, so just pick one */
3533 if (hx == lx)
3534 y = ly;
3535 else /* interpolate */
3536 y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
3537 } else /* only low is good, use it */
3538 y = ly;
3539 } else if (hhave) /* only high is good, use it */
3540 y = hy;
3541 else /* nothing is good,this should never happen unless np=0, ???? */
3542 y = -(1 << 30);
3543 return y;
3544 }
3545
3546 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3547 u16 rateIndex, u16 freq, bool is2GHz)
3548 {
3549 u16 numPiers, i;
3550 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3551 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3552 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3553 struct cal_tgt_pow_legacy *pEepromTargetPwr;
3554 u8 *pFreqBin;
3555
3556 if (is2GHz) {
3557 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3558 pEepromTargetPwr = eep->calTargetPower2G;
3559 pFreqBin = eep->calTarget_freqbin_2G;
3560 } else {
3561 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3562 pEepromTargetPwr = eep->calTargetPower5G;
3563 pFreqBin = eep->calTarget_freqbin_5G;
3564 }
3565
3566 /*
3567 * create array of channels and targetpower from
3568 * targetpower piers stored on eeprom
3569 */
3570 for (i = 0; i < numPiers; i++) {
3571 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3572 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3573 }
3574
3575 /* interpolate to get target power for given frequency */
3576 return (u8) ar9003_hw_power_interpolate((s32) freq,
3577 freqArray,
3578 targetPowerArray, numPiers);
3579 }
3580
3581 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3582 u16 rateIndex,
3583 u16 freq, bool is2GHz)
3584 {
3585 u16 numPiers, i;
3586 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3587 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3588 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3589 struct cal_tgt_pow_ht *pEepromTargetPwr;
3590 u8 *pFreqBin;
3591
3592 if (is2GHz) {
3593 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3594 pEepromTargetPwr = eep->calTargetPower2GHT20;
3595 pFreqBin = eep->calTarget_freqbin_2GHT20;
3596 } else {
3597 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3598 pEepromTargetPwr = eep->calTargetPower5GHT20;
3599 pFreqBin = eep->calTarget_freqbin_5GHT20;
3600 }
3601
3602 /*
3603 * create array of channels and targetpower
3604 * from targetpower piers stored on eeprom
3605 */
3606 for (i = 0; i < numPiers; i++) {
3607 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3608 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3609 }
3610
3611 /* interpolate to get target power for given frequency */
3612 return (u8) ar9003_hw_power_interpolate((s32) freq,
3613 freqArray,
3614 targetPowerArray, numPiers);
3615 }
3616
3617 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3618 u16 rateIndex,
3619 u16 freq, bool is2GHz)
3620 {
3621 u16 numPiers, i;
3622 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3623 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3624 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3625 struct cal_tgt_pow_ht *pEepromTargetPwr;
3626 u8 *pFreqBin;
3627
3628 if (is2GHz) {
3629 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3630 pEepromTargetPwr = eep->calTargetPower2GHT40;
3631 pFreqBin = eep->calTarget_freqbin_2GHT40;
3632 } else {
3633 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3634 pEepromTargetPwr = eep->calTargetPower5GHT40;
3635 pFreqBin = eep->calTarget_freqbin_5GHT40;
3636 }
3637
3638 /*
3639 * create array of channels and targetpower from
3640 * targetpower piers stored on eeprom
3641 */
3642 for (i = 0; i < numPiers; i++) {
3643 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3644 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3645 }
3646
3647 /* interpolate to get target power for given frequency */
3648 return (u8) ar9003_hw_power_interpolate((s32) freq,
3649 freqArray,
3650 targetPowerArray, numPiers);
3651 }
3652
3653 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3654 u16 rateIndex, u16 freq)
3655 {
3656 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3657 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3658 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3659 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3660 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3661 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3662
3663 /*
3664 * create array of channels and targetpower from
3665 * targetpower piers stored on eeprom
3666 */
3667 for (i = 0; i < numPiers; i++) {
3668 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3669 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3670 }
3671
3672 /* interpolate to get target power for given frequency */
3673 return (u8) ar9003_hw_power_interpolate((s32) freq,
3674 freqArray,
3675 targetPowerArray, numPiers);
3676 }
3677
3678 /* Set tx power registers to array of values passed in */
3679 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
3680 {
3681 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
3682 /* make sure forced gain is not set */
3683 REG_WRITE(ah, 0xa458, 0);
3684
3685 /* Write the OFDM power per rate set */
3686
3687 /* 6 (LSB), 9, 12, 18 (MSB) */
3688 REG_WRITE(ah, 0xa3c0,
3689 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
3690 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
3691 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
3692 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3693
3694 /* 24 (LSB), 36, 48, 54 (MSB) */
3695 REG_WRITE(ah, 0xa3c4,
3696 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
3697 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
3698 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
3699 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3700
3701 /* Write the CCK power per rate set */
3702
3703 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3704 REG_WRITE(ah, 0xa3c8,
3705 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
3706 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
3707 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
3708 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
3709
3710 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3711 REG_WRITE(ah, 0xa3cc,
3712 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
3713 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
3714 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
3715 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
3716 );
3717
3718 /* Write the HT20 power per rate set */
3719
3720 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3721 REG_WRITE(ah, 0xa3d0,
3722 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
3723 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
3724 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
3725 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
3726 );
3727
3728 /* 6 (LSB), 7, 12, 13 (MSB) */
3729 REG_WRITE(ah, 0xa3d4,
3730 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
3731 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
3732 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
3733 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
3734 );
3735
3736 /* 14 (LSB), 15, 20, 21 */
3737 REG_WRITE(ah, 0xa3e4,
3738 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
3739 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
3740 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
3741 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
3742 );
3743
3744 /* Mixed HT20 and HT40 rates */
3745
3746 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3747 REG_WRITE(ah, 0xa3e8,
3748 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
3749 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
3750 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
3751 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
3752 );
3753
3754 /*
3755 * Write the HT40 power per rate set
3756 * correct PAR difference between HT40 and HT20/LEGACY
3757 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
3758 */
3759 REG_WRITE(ah, 0xa3d8,
3760 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
3761 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
3762 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
3763 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
3764 );
3765
3766 /* 6 (LSB), 7, 12, 13 (MSB) */
3767 REG_WRITE(ah, 0xa3dc,
3768 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
3769 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
3770 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
3771 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
3772 );
3773
3774 /* 14 (LSB), 15, 20, 21 */
3775 REG_WRITE(ah, 0xa3ec,
3776 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
3777 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
3778 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
3779 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
3780 );
3781
3782 return 0;
3783 #undef POW_SM
3784 }
3785
3786 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
3787 u8 *targetPowerValT2)
3788 {
3789 /* XXX: hard code for now, need to get from eeprom struct */
3790 u8 ht40PowerIncForPdadc = 0;
3791 bool is2GHz = false;
3792 unsigned int i = 0;
3793 struct ath_common *common = ath9k_hw_common(ah);
3794
3795 if (freq < 4000)
3796 is2GHz = true;
3797
3798 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
3799 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
3800 is2GHz);
3801 targetPowerValT2[ALL_TARGET_LEGACY_36] =
3802 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
3803 is2GHz);
3804 targetPowerValT2[ALL_TARGET_LEGACY_48] =
3805 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
3806 is2GHz);
3807 targetPowerValT2[ALL_TARGET_LEGACY_54] =
3808 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
3809 is2GHz);
3810 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
3811 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
3812 freq);
3813 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
3814 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
3815 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
3816 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
3817 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
3818 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
3819 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
3820 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
3821 is2GHz);
3822 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
3823 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
3824 freq, is2GHz);
3825 targetPowerValT2[ALL_TARGET_HT20_4] =
3826 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
3827 is2GHz);
3828 targetPowerValT2[ALL_TARGET_HT20_5] =
3829 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
3830 is2GHz);
3831 targetPowerValT2[ALL_TARGET_HT20_6] =
3832 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
3833 is2GHz);
3834 targetPowerValT2[ALL_TARGET_HT20_7] =
3835 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
3836 is2GHz);
3837 targetPowerValT2[ALL_TARGET_HT20_12] =
3838 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
3839 is2GHz);
3840 targetPowerValT2[ALL_TARGET_HT20_13] =
3841 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
3842 is2GHz);
3843 targetPowerValT2[ALL_TARGET_HT20_14] =
3844 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
3845 is2GHz);
3846 targetPowerValT2[ALL_TARGET_HT20_15] =
3847 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
3848 is2GHz);
3849 targetPowerValT2[ALL_TARGET_HT20_20] =
3850 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
3851 is2GHz);
3852 targetPowerValT2[ALL_TARGET_HT20_21] =
3853 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
3854 is2GHz);
3855 targetPowerValT2[ALL_TARGET_HT20_22] =
3856 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
3857 is2GHz);
3858 targetPowerValT2[ALL_TARGET_HT20_23] =
3859 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
3860 is2GHz);
3861 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
3862 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
3863 is2GHz) + ht40PowerIncForPdadc;
3864 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
3865 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
3866 freq,
3867 is2GHz) + ht40PowerIncForPdadc;
3868 targetPowerValT2[ALL_TARGET_HT40_4] =
3869 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
3870 is2GHz) + ht40PowerIncForPdadc;
3871 targetPowerValT2[ALL_TARGET_HT40_5] =
3872 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
3873 is2GHz) + ht40PowerIncForPdadc;
3874 targetPowerValT2[ALL_TARGET_HT40_6] =
3875 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
3876 is2GHz) + ht40PowerIncForPdadc;
3877 targetPowerValT2[ALL_TARGET_HT40_7] =
3878 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
3879 is2GHz) + ht40PowerIncForPdadc;
3880 targetPowerValT2[ALL_TARGET_HT40_12] =
3881 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
3882 is2GHz) + ht40PowerIncForPdadc;
3883 targetPowerValT2[ALL_TARGET_HT40_13] =
3884 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
3885 is2GHz) + ht40PowerIncForPdadc;
3886 targetPowerValT2[ALL_TARGET_HT40_14] =
3887 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
3888 is2GHz) + ht40PowerIncForPdadc;
3889 targetPowerValT2[ALL_TARGET_HT40_15] =
3890 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
3891 is2GHz) + ht40PowerIncForPdadc;
3892 targetPowerValT2[ALL_TARGET_HT40_20] =
3893 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
3894 is2GHz) + ht40PowerIncForPdadc;
3895 targetPowerValT2[ALL_TARGET_HT40_21] =
3896 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
3897 is2GHz) + ht40PowerIncForPdadc;
3898 targetPowerValT2[ALL_TARGET_HT40_22] =
3899 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
3900 is2GHz) + ht40PowerIncForPdadc;
3901 targetPowerValT2[ALL_TARGET_HT40_23] =
3902 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
3903 is2GHz) + ht40PowerIncForPdadc;
3904
3905 while (i < ar9300RateSize) {
3906 ath_print(common, ATH_DBG_EEPROM,
3907 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3908 i++;
3909
3910 ath_print(common, ATH_DBG_EEPROM,
3911 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3912 i++;
3913
3914 ath_print(common, ATH_DBG_EEPROM,
3915 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3916 i++;
3917
3918 ath_print(common, ATH_DBG_EEPROM,
3919 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
3920 i++;
3921 }
3922 }
3923
3924 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
3925 int mode,
3926 int ipier,
3927 int ichain,
3928 int *pfrequency,
3929 int *pcorrection,
3930 int *ptemperature, int *pvoltage)
3931 {
3932 u8 *pCalPier;
3933 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
3934 int is2GHz;
3935 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3936 struct ath_common *common = ath9k_hw_common(ah);
3937
3938 if (ichain >= AR9300_MAX_CHAINS) {
3939 ath_print(common, ATH_DBG_EEPROM,
3940 "Invalid chain index, must be less than %d\n",
3941 AR9300_MAX_CHAINS);
3942 return -1;
3943 }
3944
3945 if (mode) { /* 5GHz */
3946 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
3947 ath_print(common, ATH_DBG_EEPROM,
3948 "Invalid 5GHz cal pier index, must "
3949 "be less than %d\n",
3950 AR9300_NUM_5G_CAL_PIERS);
3951 return -1;
3952 }
3953 pCalPier = &(eep->calFreqPier5G[ipier]);
3954 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
3955 is2GHz = 0;
3956 } else {
3957 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
3958 ath_print(common, ATH_DBG_EEPROM,
3959 "Invalid 2GHz cal pier index, must "
3960 "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
3961 return -1;
3962 }
3963
3964 pCalPier = &(eep->calFreqPier2G[ipier]);
3965 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
3966 is2GHz = 1;
3967 }
3968
3969 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
3970 *pcorrection = pCalPierStruct->refPower;
3971 *ptemperature = pCalPierStruct->tempMeas;
3972 *pvoltage = pCalPierStruct->voltMeas;
3973
3974 return 0;
3975 }
3976
3977 static int ar9003_hw_power_control_override(struct ath_hw *ah,
3978 int frequency,
3979 int *correction,
3980 int *voltage, int *temperature)
3981 {
3982 int tempSlope = 0;
3983 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3984
3985 REG_RMW(ah, AR_PHY_TPC_11_B0,
3986 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3987 AR_PHY_TPC_OLPC_GAIN_DELTA);
3988 REG_RMW(ah, AR_PHY_TPC_11_B1,
3989 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3990 AR_PHY_TPC_OLPC_GAIN_DELTA);
3991 REG_RMW(ah, AR_PHY_TPC_11_B2,
3992 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3993 AR_PHY_TPC_OLPC_GAIN_DELTA);
3994
3995 /* enable open loop power control on chip */
3996 REG_RMW(ah, AR_PHY_TPC_6_B0,
3997 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
3998 AR_PHY_TPC_6_ERROR_EST_MODE);
3999 REG_RMW(ah, AR_PHY_TPC_6_B1,
4000 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4001 AR_PHY_TPC_6_ERROR_EST_MODE);
4002 REG_RMW(ah, AR_PHY_TPC_6_B2,
4003 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4004 AR_PHY_TPC_6_ERROR_EST_MODE);
4005
4006 /*
4007 * enable temperature compensation
4008 * Need to use register names
4009 */
4010 if (frequency < 4000)
4011 tempSlope = eep->modalHeader2G.tempSlope;
4012 else
4013 tempSlope = eep->modalHeader5G.tempSlope;
4014
4015 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4016 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4017 temperature[0]);
4018
4019 return 0;
4020 }
4021
4022 /* Apply the recorded correction values. */
4023 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4024 {
4025 int ichain, ipier, npier;
4026 int mode;
4027 int lfrequency[AR9300_MAX_CHAINS],
4028 lcorrection[AR9300_MAX_CHAINS],
4029 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4030 int hfrequency[AR9300_MAX_CHAINS],
4031 hcorrection[AR9300_MAX_CHAINS],
4032 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4033 int fdiff;
4034 int correction[AR9300_MAX_CHAINS],
4035 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4036 int pfrequency, pcorrection, ptemperature, pvoltage;
4037 struct ath_common *common = ath9k_hw_common(ah);
4038
4039 mode = (frequency >= 4000);
4040 if (mode)
4041 npier = AR9300_NUM_5G_CAL_PIERS;
4042 else
4043 npier = AR9300_NUM_2G_CAL_PIERS;
4044
4045 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4046 lfrequency[ichain] = 0;
4047 hfrequency[ichain] = 100000;
4048 }
4049 /* identify best lower and higher frequency calibration measurement */
4050 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4051 for (ipier = 0; ipier < npier; ipier++) {
4052 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4053 &pfrequency, &pcorrection,
4054 &ptemperature, &pvoltage)) {
4055 fdiff = frequency - pfrequency;
4056
4057 /*
4058 * this measurement is higher than
4059 * our desired frequency
4060 */
4061 if (fdiff <= 0) {
4062 if (hfrequency[ichain] <= 0 ||
4063 hfrequency[ichain] >= 100000 ||
4064 fdiff >
4065 (frequency - hfrequency[ichain])) {
4066 /*
4067 * new best higher
4068 * frequency measurement
4069 */
4070 hfrequency[ichain] = pfrequency;
4071 hcorrection[ichain] =
4072 pcorrection;
4073 htemperature[ichain] =
4074 ptemperature;
4075 hvoltage[ichain] = pvoltage;
4076 }
4077 }
4078 if (fdiff >= 0) {
4079 if (lfrequency[ichain] <= 0
4080 || fdiff <
4081 (frequency - lfrequency[ichain])) {
4082 /*
4083 * new best lower
4084 * frequency measurement
4085 */
4086 lfrequency[ichain] = pfrequency;
4087 lcorrection[ichain] =
4088 pcorrection;
4089 ltemperature[ichain] =
4090 ptemperature;
4091 lvoltage[ichain] = pvoltage;
4092 }
4093 }
4094 }
4095 }
4096 }
4097
4098 /* interpolate */
4099 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4100 ath_print(common, ATH_DBG_EEPROM,
4101 "ch=%d f=%d low=%d %d h=%d %d\n",
4102 ichain, frequency, lfrequency[ichain],
4103 lcorrection[ichain], hfrequency[ichain],
4104 hcorrection[ichain]);
4105 /* they're the same, so just pick one */
4106 if (hfrequency[ichain] == lfrequency[ichain]) {
4107 correction[ichain] = lcorrection[ichain];
4108 voltage[ichain] = lvoltage[ichain];
4109 temperature[ichain] = ltemperature[ichain];
4110 }
4111 /* the low frequency is good */
4112 else if (frequency - lfrequency[ichain] < 1000) {
4113 /* so is the high frequency, interpolate */
4114 if (hfrequency[ichain] - frequency < 1000) {
4115
4116 correction[ichain] = lcorrection[ichain] +
4117 (((frequency - lfrequency[ichain]) *
4118 (hcorrection[ichain] -
4119 lcorrection[ichain])) /
4120 (hfrequency[ichain] - lfrequency[ichain]));
4121
4122 temperature[ichain] = ltemperature[ichain] +
4123 (((frequency - lfrequency[ichain]) *
4124 (htemperature[ichain] -
4125 ltemperature[ichain])) /
4126 (hfrequency[ichain] - lfrequency[ichain]));
4127
4128 voltage[ichain] =
4129 lvoltage[ichain] +
4130 (((frequency -
4131 lfrequency[ichain]) * (hvoltage[ichain] -
4132 lvoltage[ichain]))
4133 / (hfrequency[ichain] -
4134 lfrequency[ichain]));
4135 }
4136 /* only low is good, use it */
4137 else {
4138 correction[ichain] = lcorrection[ichain];
4139 temperature[ichain] = ltemperature[ichain];
4140 voltage[ichain] = lvoltage[ichain];
4141 }
4142 }
4143 /* only high is good, use it */
4144 else if (hfrequency[ichain] - frequency < 1000) {
4145 correction[ichain] = hcorrection[ichain];
4146 temperature[ichain] = htemperature[ichain];
4147 voltage[ichain] = hvoltage[ichain];
4148 } else { /* nothing is good, presume 0???? */
4149 correction[ichain] = 0;
4150 temperature[ichain] = 0;
4151 voltage[ichain] = 0;
4152 }
4153 }
4154
4155 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4156 temperature);
4157
4158 ath_print(common, ATH_DBG_EEPROM,
4159 "for frequency=%d, calibration correction = %d %d %d\n",
4160 frequency, correction[0], correction[1], correction[2]);
4161
4162 return 0;
4163 }
4164
4165 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4166 int idx,
4167 int edge,
4168 bool is2GHz)
4169 {
4170 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4171 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4172
4173 if (is2GHz)
4174 return ctl_2g[idx].ctlEdges[edge].tPower;
4175 else
4176 return ctl_5g[idx].ctlEdges[edge].tPower;
4177 }
4178
4179 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4180 int idx,
4181 unsigned int edge,
4182 u16 freq,
4183 bool is2GHz)
4184 {
4185 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4186 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4187
4188 u8 *ctl_freqbin = is2GHz ?
4189 &eep->ctl_freqbin_2G[idx][0] :
4190 &eep->ctl_freqbin_5G[idx][0];
4191
4192 if (is2GHz) {
4193 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4194 ctl_2g[idx].ctlEdges[edge - 1].flag)
4195 return ctl_2g[idx].ctlEdges[edge - 1].tPower;
4196 } else {
4197 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4198 ctl_5g[idx].ctlEdges[edge - 1].flag)
4199 return ctl_5g[idx].ctlEdges[edge - 1].tPower;
4200 }
4201
4202 return AR9300_MAX_RATE_POWER;
4203 }
4204
4205 /*
4206 * Find the maximum conformance test limit for the given channel and CTL info
4207 */
4208 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4209 u16 freq, int idx, bool is2GHz)
4210 {
4211 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4212 u8 *ctl_freqbin = is2GHz ?
4213 &eep->ctl_freqbin_2G[idx][0] :
4214 &eep->ctl_freqbin_5G[idx][0];
4215 u16 num_edges = is2GHz ?
4216 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4217 unsigned int edge;
4218
4219 /* Get the edge power */
4220 for (edge = 0;
4221 (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
4222 edge++) {
4223 /*
4224 * If there's an exact channel match or an inband flag set
4225 * on the lower channel use the given rdEdgePower
4226 */
4227 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4228 twiceMaxEdgePower =
4229 ar9003_hw_get_direct_edge_power(eep, idx,
4230 edge, is2GHz);
4231 break;
4232 } else if ((edge > 0) &&
4233 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4234 is2GHz))) {
4235 twiceMaxEdgePower =
4236 ar9003_hw_get_indirect_edge_power(eep, idx,
4237 edge, freq,
4238 is2GHz);
4239 /*
4240 * Leave loop - no more affecting edges possible in
4241 * this monotonic increasing list
4242 */
4243 break;
4244 }
4245 }
4246 return twiceMaxEdgePower;
4247 }
4248
4249 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4250 struct ath9k_channel *chan,
4251 u8 *pPwrArray, u16 cfgCtl,
4252 u8 twiceAntennaReduction,
4253 u8 twiceMaxRegulatoryPower,
4254 u16 powerLimit)
4255 {
4256 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4257 struct ath_common *common = ath9k_hw_common(ah);
4258 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4259 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4260 static const u16 tpScaleReductionTable[5] = {
4261 0, 3, 6, 9, AR9300_MAX_RATE_POWER
4262 };
4263 int i;
4264 int16_t twiceLargestAntenna;
4265 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4266 u16 ctlModesFor11a[] = {
4267 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4268 };
4269 u16 ctlModesFor11g[] = {
4270 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4271 CTL_11G_EXT, CTL_2GHT40
4272 };
4273 u16 numCtlModes, *pCtlMode, ctlMode, freq;
4274 struct chan_centers centers;
4275 u8 *ctlIndex;
4276 u8 ctlNum;
4277 u16 twiceMinEdgePower;
4278 bool is2ghz = IS_CHAN_2GHZ(chan);
4279
4280 ath9k_hw_get_channel_centers(ah, chan, &centers);
4281
4282 /* Compute TxPower reduction due to Antenna Gain */
4283 if (is2ghz)
4284 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4285 else
4286 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4287
4288 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4289 twiceLargestAntenna, 0);
4290
4291 /*
4292 * scaledPower is the minimum of the user input power level
4293 * and the regulatory allowed power level
4294 */
4295 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4296
4297 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4298 maxRegAllowedPower -=
4299 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4300 }
4301
4302 scaledPower = min(powerLimit, maxRegAllowedPower);
4303
4304 /*
4305 * Reduce scaled Power by number of chains active to get
4306 * to per chain tx power level
4307 */
4308 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4309 case 1:
4310 break;
4311 case 2:
4312 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4313 break;
4314 case 3:
4315 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4316 break;
4317 }
4318
4319 scaledPower = max((u16)0, scaledPower);
4320
4321 /*
4322 * Get target powers from EEPROM - our baseline for TX Power
4323 */
4324 if (is2ghz) {
4325 /* Setup for CTL modes */
4326 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4327 numCtlModes =
4328 ARRAY_SIZE(ctlModesFor11g) -
4329 SUB_NUM_CTL_MODES_AT_2G_40;
4330 pCtlMode = ctlModesFor11g;
4331 if (IS_CHAN_HT40(chan))
4332 /* All 2G CTL's */
4333 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4334 } else {
4335 /* Setup for CTL modes */
4336 /* CTL_11A, CTL_5GHT20 */
4337 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4338 SUB_NUM_CTL_MODES_AT_5G_40;
4339 pCtlMode = ctlModesFor11a;
4340 if (IS_CHAN_HT40(chan))
4341 /* All 5G CTL's */
4342 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4343 }
4344
4345 /*
4346 * For MIMO, need to apply regulatory caps individually across
4347 * dynamically running modes: CCK, OFDM, HT20, HT40
4348 *
4349 * The outer loop walks through each possible applicable runtime mode.
4350 * The inner loop walks through each ctlIndex entry in EEPROM.
4351 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4352 */
4353 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4354 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4355 (pCtlMode[ctlMode] == CTL_2GHT40);
4356 if (isHt40CtlMode)
4357 freq = centers.synth_center;
4358 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4359 freq = centers.ext_center;
4360 else
4361 freq = centers.ctl_center;
4362
4363 ath_print(common, ATH_DBG_REGULATORY,
4364 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4365 "EXT_ADDITIVE %d\n",
4366 ctlMode, numCtlModes, isHt40CtlMode,
4367 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4368
4369 /* walk through each CTL index stored in EEPROM */
4370 if (is2ghz) {
4371 ctlIndex = pEepData->ctlIndex_2G;
4372 ctlNum = AR9300_NUM_CTLS_2G;
4373 } else {
4374 ctlIndex = pEepData->ctlIndex_5G;
4375 ctlNum = AR9300_NUM_CTLS_5G;
4376 }
4377
4378 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4379 ath_print(common, ATH_DBG_REGULATORY,
4380 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4381 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4382 "chan %dn",
4383 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4384 chan->channel);
4385
4386 /*
4387 * compare test group from regulatory
4388 * channel list with test mode from pCtlMode
4389 * list
4390 */
4391 if ((((cfgCtl & ~CTL_MODE_M) |
4392 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4393 ctlIndex[i]) ||
4394 (((cfgCtl & ~CTL_MODE_M) |
4395 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4396 ((ctlIndex[i] & CTL_MODE_M) |
4397 SD_NO_CTL))) {
4398 twiceMinEdgePower =
4399 ar9003_hw_get_max_edge_power(pEepData,
4400 freq, i,
4401 is2ghz);
4402
4403 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4404 /*
4405 * Find the minimum of all CTL
4406 * edge powers that apply to
4407 * this channel
4408 */
4409 twiceMaxEdgePower =
4410 min(twiceMaxEdgePower,
4411 twiceMinEdgePower);
4412 else {
4413 /* specific */
4414 twiceMaxEdgePower =
4415 twiceMinEdgePower;
4416 break;
4417 }
4418 }
4419 }
4420
4421 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4422
4423 ath_print(common, ATH_DBG_REGULATORY,
4424 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
4425 "sP %d minCtlPwr %d\n",
4426 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4427 scaledPower, minCtlPower);
4428
4429 /* Apply ctl mode to correct target power set */
4430 switch (pCtlMode[ctlMode]) {
4431 case CTL_11B:
4432 for (i = ALL_TARGET_LEGACY_1L_5L;
4433 i <= ALL_TARGET_LEGACY_11S; i++)
4434 pPwrArray[i] =
4435 (u8)min((u16)pPwrArray[i],
4436 minCtlPower);
4437 break;
4438 case CTL_11A:
4439 case CTL_11G:
4440 for (i = ALL_TARGET_LEGACY_6_24;
4441 i <= ALL_TARGET_LEGACY_54; i++)
4442 pPwrArray[i] =
4443 (u8)min((u16)pPwrArray[i],
4444 minCtlPower);
4445 break;
4446 case CTL_5GHT20:
4447 case CTL_2GHT20:
4448 for (i = ALL_TARGET_HT20_0_8_16;
4449 i <= ALL_TARGET_HT20_21; i++)
4450 pPwrArray[i] =
4451 (u8)min((u16)pPwrArray[i],
4452 minCtlPower);
4453 pPwrArray[ALL_TARGET_HT20_22] =
4454 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4455 minCtlPower);
4456 pPwrArray[ALL_TARGET_HT20_23] =
4457 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4458 minCtlPower);
4459 break;
4460 case CTL_5GHT40:
4461 case CTL_2GHT40:
4462 for (i = ALL_TARGET_HT40_0_8_16;
4463 i <= ALL_TARGET_HT40_23; i++)
4464 pPwrArray[i] =
4465 (u8)min((u16)pPwrArray[i],
4466 minCtlPower);
4467 break;
4468 default:
4469 break;
4470 }
4471 } /* end ctl mode checking */
4472 }
4473
4474 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4475 struct ath9k_channel *chan, u16 cfgCtl,
4476 u8 twiceAntennaReduction,
4477 u8 twiceMaxRegulatoryPower,
4478 u8 powerLimit, bool test)
4479 {
4480 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4481 struct ath_common *common = ath9k_hw_common(ah);
4482 u8 targetPowerValT2[ar9300RateSize];
4483 unsigned int i = 0;
4484
4485 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4486 ar9003_hw_set_power_per_rate_table(ah, chan,
4487 targetPowerValT2, cfgCtl,
4488 twiceAntennaReduction,
4489 twiceMaxRegulatoryPower,
4490 powerLimit);
4491
4492 regulatory->max_power_level = 0;
4493 for (i = 0; i < ar9300RateSize; i++) {
4494 if (targetPowerValT2[i] > regulatory->max_power_level)
4495 regulatory->max_power_level = targetPowerValT2[i];
4496 }
4497
4498 if (test)
4499 return;
4500
4501 for (i = 0; i < ar9300RateSize; i++) {
4502 ath_print(common, ATH_DBG_EEPROM,
4503 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4504 i++;
4505 ath_print(common, ATH_DBG_EEPROM,
4506 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4507 i++;
4508 ath_print(common, ATH_DBG_EEPROM,
4509 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4510 i++;
4511 ath_print(common, ATH_DBG_EEPROM,
4512 "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
4513 i++;
4514 }
4515
4516 /*
4517 * This is the TX power we send back to driver core,
4518 * and it can use to pass to userspace to display our
4519 * currently configured TX power setting.
4520 *
4521 * Since power is rate dependent, use one of the indices
4522 * from the AR9300_Rates enum to select an entry from
4523 * targetPowerValT2[] to report. Currently returns the
4524 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4525 * as CCK power is less interesting (?).
4526 */
4527 i = ALL_TARGET_LEGACY_6_24; /* legacy */
4528 if (IS_CHAN_HT40(chan))
4529 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4530 else if (IS_CHAN_HT20(chan))
4531 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4532
4533 ah->txpower_limit = targetPowerValT2[i];
4534 regulatory->max_power_level = targetPowerValT2[i];
4535
4536 /* Write target power array to registers */
4537 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4538 ar9003_hw_calibration_apply(ah, chan->channel);
4539 }
4540
4541 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4542 u16 i, bool is2GHz)
4543 {
4544 return AR_NO_SPUR;
4545 }
4546
4547 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4548 {
4549 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4550
4551 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4552 }
4553
4554 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4555 {
4556 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4557
4558 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4559 }
4560
4561 const struct eeprom_ops eep_ar9300_ops = {
4562 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4563 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4564 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4565 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4566 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
4567 .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
4568 .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
4569 .set_board_values = ath9k_hw_ar9300_set_board_values,
4570 .set_addac = ath9k_hw_ar9300_set_addac,
4571 .set_txpower = ath9k_hw_ar9300_set_txpower,
4572 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
4573 };
ubuntu-bionic-kernel mirror