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Merge branch 'staging-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <asm/unaligned.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
21
22 #define COMP_HDR_LEN 4
23 #define COMP_CKSUM_LEN 2
24
25 #define AR_CH0_TOP (0x00016288)
26 #define AR_CH0_TOP_XPABIASLVL (0x300)
27 #define AR_CH0_TOP_XPABIASLVL_S (8)
28
29 #define AR_CH0_THERM (0x00016290)
30 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
31 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
32 #define AR_CH0_THERM_XPASHORT2GND 0x4
33 #define AR_CH0_THERM_XPASHORT2GND_S 2
34
35 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
36 #define AR_SWITCH_TABLE_COM_ALL_S (0)
37
38 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
39 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
40
41 #define AR_SWITCH_TABLE_ALL (0xfff)
42 #define AR_SWITCH_TABLE_ALL_S (0)
43
44 #define LE16(x) __constant_cpu_to_le16(x)
45 #define LE32(x) __constant_cpu_to_le32(x)
46
47 /* Local defines to distinguish between extension and control CTL's */
48 #define EXT_ADDITIVE (0x8000)
49 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
50 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
51 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
52 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
53 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
54 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
55 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
56 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
57
58 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
59 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
60
61 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
62
63 #define EEPROM_DATA_LEN_9485 1088
64
65 static int ar9003_hw_power_interpolate(int32_t x,
66 int32_t *px, int32_t *py, u_int16_t np);
67
68
69 static const struct ar9300_eeprom ar9300_default = {
70 .eepromVersion = 2,
71 .templateVersion = 2,
72 .macAddr = {1, 2, 3, 4, 5, 6},
73 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
74 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
75 .baseEepHeader = {
76 .regDmn = { LE16(0), LE16(0x1f) },
77 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
78 .opCapFlags = {
79 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
80 .eepMisc = 0,
81 },
82 .rfSilent = 0,
83 .blueToothOptions = 0,
84 .deviceCap = 0,
85 .deviceType = 5, /* takes lower byte in eeprom location */
86 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
87 .params_for_tuning_caps = {0, 0},
88 .featureEnable = 0x0c,
89 /*
90 * bit0 - enable tx temp comp - disabled
91 * bit1 - enable tx volt comp - disabled
92 * bit2 - enable fastClock - enabled
93 * bit3 - enable doubling - enabled
94 * bit4 - enable internal regulator - disabled
95 * bit5 - enable pa predistortion - disabled
96 */
97 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
98 .eepromWriteEnableGpio = 3,
99 .wlanDisableGpio = 0,
100 .wlanLedGpio = 8,
101 .rxBandSelectGpio = 0xff,
102 .txrxgain = 0,
103 .swreg = 0,
104 },
105 .modalHeader2G = {
106 /* ar9300_modal_eep_header 2g */
107 /* 4 idle,t1,t2,b(4 bits per setting) */
108 .antCtrlCommon = LE32(0x110),
109 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
110 .antCtrlCommon2 = LE32(0x22222),
111
112 /*
113 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
114 * rx1, rx12, b (2 bits each)
115 */
116 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
117
118 /*
119 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
120 * for ar9280 (0xa20c/b20c 5:0)
121 */
122 .xatten1DB = {0, 0, 0},
123
124 /*
125 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
126 * for ar9280 (0xa20c/b20c 16:12
127 */
128 .xatten1Margin = {0, 0, 0},
129 .tempSlope = 36,
130 .voltSlope = 0,
131
132 /*
133 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
134 * channels in usual fbin coding format
135 */
136 .spurChans = {0, 0, 0, 0, 0},
137
138 /*
139 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
140 * if the register is per chain
141 */
142 .noiseFloorThreshCh = {-1, 0, 0},
143 .ob = {1, 1, 1},/* 3 chain */
144 .db_stage2 = {1, 1, 1}, /* 3 chain */
145 .db_stage3 = {0, 0, 0},
146 .db_stage4 = {0, 0, 0},
147 .xpaBiasLvl = 0,
148 .txFrameToDataStart = 0x0e,
149 .txFrameToPaOn = 0x0e,
150 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
151 .antennaGain = 0,
152 .switchSettling = 0x2c,
153 .adcDesiredSize = -30,
154 .txEndToXpaOff = 0,
155 .txEndToRxOn = 0x2,
156 .txFrameToXpaOn = 0xe,
157 .thresh62 = 28,
158 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
159 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
160 .futureModal = {
161 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
162 },
163 },
164 .base_ext1 = {
165 .ant_div_control = 0,
166 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
167 },
168 .calFreqPier2G = {
169 FREQ2FBIN(2412, 1),
170 FREQ2FBIN(2437, 1),
171 FREQ2FBIN(2472, 1),
172 },
173 /* ar9300_cal_data_per_freq_op_loop 2g */
174 .calPierData2G = {
175 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
176 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
177 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
178 },
179 .calTarget_freqbin_Cck = {
180 FREQ2FBIN(2412, 1),
181 FREQ2FBIN(2484, 1),
182 },
183 .calTarget_freqbin_2G = {
184 FREQ2FBIN(2412, 1),
185 FREQ2FBIN(2437, 1),
186 FREQ2FBIN(2472, 1)
187 },
188 .calTarget_freqbin_2GHT20 = {
189 FREQ2FBIN(2412, 1),
190 FREQ2FBIN(2437, 1),
191 FREQ2FBIN(2472, 1)
192 },
193 .calTarget_freqbin_2GHT40 = {
194 FREQ2FBIN(2412, 1),
195 FREQ2FBIN(2437, 1),
196 FREQ2FBIN(2472, 1)
197 },
198 .calTargetPowerCck = {
199 /* 1L-5L,5S,11L,11S */
200 { {36, 36, 36, 36} },
201 { {36, 36, 36, 36} },
202 },
203 .calTargetPower2G = {
204 /* 6-24,36,48,54 */
205 { {32, 32, 28, 24} },
206 { {32, 32, 28, 24} },
207 { {32, 32, 28, 24} },
208 },
209 .calTargetPower2GHT20 = {
210 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
211 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
212 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
213 },
214 .calTargetPower2GHT40 = {
215 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
216 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
217 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
218 },
219 .ctlIndex_2G = {
220 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
221 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
222 },
223 .ctl_freqbin_2G = {
224 {
225 FREQ2FBIN(2412, 1),
226 FREQ2FBIN(2417, 1),
227 FREQ2FBIN(2457, 1),
228 FREQ2FBIN(2462, 1)
229 },
230 {
231 FREQ2FBIN(2412, 1),
232 FREQ2FBIN(2417, 1),
233 FREQ2FBIN(2462, 1),
234 0xFF,
235 },
236
237 {
238 FREQ2FBIN(2412, 1),
239 FREQ2FBIN(2417, 1),
240 FREQ2FBIN(2462, 1),
241 0xFF,
242 },
243 {
244 FREQ2FBIN(2422, 1),
245 FREQ2FBIN(2427, 1),
246 FREQ2FBIN(2447, 1),
247 FREQ2FBIN(2452, 1)
248 },
249
250 {
251 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
252 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
253 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
254 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
255 },
256
257 {
258 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
259 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
260 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
261 0,
262 },
263
264 {
265 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
266 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
267 FREQ2FBIN(2472, 1),
268 0,
269 },
270
271 {
272 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
273 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
274 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
275 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
276 },
277
278 {
279 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
280 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
281 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
282 },
283
284 {
285 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
286 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
287 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
288 0
289 },
290
291 {
292 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
293 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
294 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
295 0
296 },
297
298 {
299 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
300 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
301 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
302 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
303 }
304 },
305 .ctlPowerData_2G = {
306 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
307 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
308 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
309
310 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
311 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
312 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
313
314 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
315 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
316 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
317
318 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
319 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
320 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
321 },
322 .modalHeader5G = {
323 /* 4 idle,t1,t2,b (4 bits per setting) */
324 .antCtrlCommon = LE32(0x110),
325 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
326 .antCtrlCommon2 = LE32(0x22222),
327 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
328 .antCtrlChain = {
329 LE16(0x000), LE16(0x000), LE16(0x000),
330 },
331 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
332 .xatten1DB = {0, 0, 0},
333
334 /*
335 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
336 * for merlin (0xa20c/b20c 16:12
337 */
338 .xatten1Margin = {0, 0, 0},
339 .tempSlope = 68,
340 .voltSlope = 0,
341 /* spurChans spur channels in usual fbin coding format */
342 .spurChans = {0, 0, 0, 0, 0},
343 /* noiseFloorThreshCh Check if the register is per chain */
344 .noiseFloorThreshCh = {-1, 0, 0},
345 .ob = {3, 3, 3}, /* 3 chain */
346 .db_stage2 = {3, 3, 3}, /* 3 chain */
347 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
348 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
349 .xpaBiasLvl = 0,
350 .txFrameToDataStart = 0x0e,
351 .txFrameToPaOn = 0x0e,
352 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
353 .antennaGain = 0,
354 .switchSettling = 0x2d,
355 .adcDesiredSize = -30,
356 .txEndToXpaOff = 0,
357 .txEndToRxOn = 0x2,
358 .txFrameToXpaOn = 0xe,
359 .thresh62 = 28,
360 .papdRateMaskHt20 = LE32(0x0c80c080),
361 .papdRateMaskHt40 = LE32(0x0080c080),
362 .futureModal = {
363 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
364 },
365 },
366 .base_ext2 = {
367 .tempSlopeLow = 0,
368 .tempSlopeHigh = 0,
369 .xatten1DBLow = {0, 0, 0},
370 .xatten1MarginLow = {0, 0, 0},
371 .xatten1DBHigh = {0, 0, 0},
372 .xatten1MarginHigh = {0, 0, 0}
373 },
374 .calFreqPier5G = {
375 FREQ2FBIN(5180, 0),
376 FREQ2FBIN(5220, 0),
377 FREQ2FBIN(5320, 0),
378 FREQ2FBIN(5400, 0),
379 FREQ2FBIN(5500, 0),
380 FREQ2FBIN(5600, 0),
381 FREQ2FBIN(5725, 0),
382 FREQ2FBIN(5825, 0)
383 },
384 .calPierData5G = {
385 {
386 {0, 0, 0, 0, 0},
387 {0, 0, 0, 0, 0},
388 {0, 0, 0, 0, 0},
389 {0, 0, 0, 0, 0},
390 {0, 0, 0, 0, 0},
391 {0, 0, 0, 0, 0},
392 {0, 0, 0, 0, 0},
393 {0, 0, 0, 0, 0},
394 },
395 {
396 {0, 0, 0, 0, 0},
397 {0, 0, 0, 0, 0},
398 {0, 0, 0, 0, 0},
399 {0, 0, 0, 0, 0},
400 {0, 0, 0, 0, 0},
401 {0, 0, 0, 0, 0},
402 {0, 0, 0, 0, 0},
403 {0, 0, 0, 0, 0},
404 },
405 {
406 {0, 0, 0, 0, 0},
407 {0, 0, 0, 0, 0},
408 {0, 0, 0, 0, 0},
409 {0, 0, 0, 0, 0},
410 {0, 0, 0, 0, 0},
411 {0, 0, 0, 0, 0},
412 {0, 0, 0, 0, 0},
413 {0, 0, 0, 0, 0},
414 },
415
416 },
417 .calTarget_freqbin_5G = {
418 FREQ2FBIN(5180, 0),
419 FREQ2FBIN(5220, 0),
420 FREQ2FBIN(5320, 0),
421 FREQ2FBIN(5400, 0),
422 FREQ2FBIN(5500, 0),
423 FREQ2FBIN(5600, 0),
424 FREQ2FBIN(5725, 0),
425 FREQ2FBIN(5825, 0)
426 },
427 .calTarget_freqbin_5GHT20 = {
428 FREQ2FBIN(5180, 0),
429 FREQ2FBIN(5240, 0),
430 FREQ2FBIN(5320, 0),
431 FREQ2FBIN(5500, 0),
432 FREQ2FBIN(5700, 0),
433 FREQ2FBIN(5745, 0),
434 FREQ2FBIN(5725, 0),
435 FREQ2FBIN(5825, 0)
436 },
437 .calTarget_freqbin_5GHT40 = {
438 FREQ2FBIN(5180, 0),
439 FREQ2FBIN(5240, 0),
440 FREQ2FBIN(5320, 0),
441 FREQ2FBIN(5500, 0),
442 FREQ2FBIN(5700, 0),
443 FREQ2FBIN(5745, 0),
444 FREQ2FBIN(5725, 0),
445 FREQ2FBIN(5825, 0)
446 },
447 .calTargetPower5G = {
448 /* 6-24,36,48,54 */
449 { {20, 20, 20, 10} },
450 { {20, 20, 20, 10} },
451 { {20, 20, 20, 10} },
452 { {20, 20, 20, 10} },
453 { {20, 20, 20, 10} },
454 { {20, 20, 20, 10} },
455 { {20, 20, 20, 10} },
456 { {20, 20, 20, 10} },
457 },
458 .calTargetPower5GHT20 = {
459 /*
460 * 0_8_16,1-3_9-11_17-19,
461 * 4,5,6,7,12,13,14,15,20,21,22,23
462 */
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
464 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
465 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
466 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
467 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
468 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
469 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
470 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471 },
472 .calTargetPower5GHT40 = {
473 /*
474 * 0_8_16,1-3_9-11_17-19,
475 * 4,5,6,7,12,13,14,15,20,21,22,23
476 */
477 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
478 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
479 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
480 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
481 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
482 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
483 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
484 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
485 },
486 .ctlIndex_5G = {
487 0x10, 0x16, 0x18, 0x40, 0x46,
488 0x48, 0x30, 0x36, 0x38
489 },
490 .ctl_freqbin_5G = {
491 {
492 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
493 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
494 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
495 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
496 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
497 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
498 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
499 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
500 },
501 {
502 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
503 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
504 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
505 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
506 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
507 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
508 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
509 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
510 },
511
512 {
513 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
514 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
515 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
516 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
517 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
518 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
519 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
520 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
521 },
522
523 {
524 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
525 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
526 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
527 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
528 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
529 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
530 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
531 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
532 },
533
534 {
535 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
536 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
537 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
538 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
539 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
540 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
541 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
542 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
543 },
544
545 {
546 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
547 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
548 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
549 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
550 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
551 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
552 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
553 /* Data[5].ctlEdges[7].bChannel */ 0xFF
554 },
555
556 {
557 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
558 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
559 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
560 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
561 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
562 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
563 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
564 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
565 },
566
567 {
568 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
569 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
570 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
571 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
572 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
573 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
574 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
575 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
576 },
577
578 {
579 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
580 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
581 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
582 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
583 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
584 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
585 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
586 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
587 }
588 },
589 .ctlPowerData_5G = {
590 {
591 {
592 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
593 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
594 }
595 },
596 {
597 {
598 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
599 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
600 }
601 },
602 {
603 {
604 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
605 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
606 }
607 },
608 {
609 {
610 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
611 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
612 }
613 },
614 {
615 {
616 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
617 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
618 }
619 },
620 {
621 {
622 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
623 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
624 }
625 },
626 {
627 {
628 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
629 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
630 }
631 },
632 {
633 {
634 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
635 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
636 }
637 },
638 {
639 {
640 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
641 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
642 }
643 },
644 }
645 };
646
647 static const struct ar9300_eeprom ar9300_x113 = {
648 .eepromVersion = 2,
649 .templateVersion = 6,
650 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
651 .custData = {"x113-023-f0000"},
652 .baseEepHeader = {
653 .regDmn = { LE16(0), LE16(0x1f) },
654 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
655 .opCapFlags = {
656 .opFlags = AR5416_OPFLAGS_11A,
657 .eepMisc = 0,
658 },
659 .rfSilent = 0,
660 .blueToothOptions = 0,
661 .deviceCap = 0,
662 .deviceType = 5, /* takes lower byte in eeprom location */
663 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
664 .params_for_tuning_caps = {0, 0},
665 .featureEnable = 0x0d,
666 /*
667 * bit0 - enable tx temp comp - disabled
668 * bit1 - enable tx volt comp - disabled
669 * bit2 - enable fastClock - enabled
670 * bit3 - enable doubling - enabled
671 * bit4 - enable internal regulator - disabled
672 * bit5 - enable pa predistortion - disabled
673 */
674 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
675 .eepromWriteEnableGpio = 6,
676 .wlanDisableGpio = 0,
677 .wlanLedGpio = 8,
678 .rxBandSelectGpio = 0xff,
679 .txrxgain = 0x21,
680 .swreg = 0,
681 },
682 .modalHeader2G = {
683 /* ar9300_modal_eep_header 2g */
684 /* 4 idle,t1,t2,b(4 bits per setting) */
685 .antCtrlCommon = LE32(0x110),
686 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
687 .antCtrlCommon2 = LE32(0x44444),
688
689 /*
690 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
691 * rx1, rx12, b (2 bits each)
692 */
693 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
694
695 /*
696 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
697 * for ar9280 (0xa20c/b20c 5:0)
698 */
699 .xatten1DB = {0, 0, 0},
700
701 /*
702 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
703 * for ar9280 (0xa20c/b20c 16:12
704 */
705 .xatten1Margin = {0, 0, 0},
706 .tempSlope = 25,
707 .voltSlope = 0,
708
709 /*
710 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
711 * channels in usual fbin coding format
712 */
713 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
714
715 /*
716 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
717 * if the register is per chain
718 */
719 .noiseFloorThreshCh = {-1, 0, 0},
720 .ob = {1, 1, 1},/* 3 chain */
721 .db_stage2 = {1, 1, 1}, /* 3 chain */
722 .db_stage3 = {0, 0, 0},
723 .db_stage4 = {0, 0, 0},
724 .xpaBiasLvl = 0,
725 .txFrameToDataStart = 0x0e,
726 .txFrameToPaOn = 0x0e,
727 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
728 .antennaGain = 0,
729 .switchSettling = 0x2c,
730 .adcDesiredSize = -30,
731 .txEndToXpaOff = 0,
732 .txEndToRxOn = 0x2,
733 .txFrameToXpaOn = 0xe,
734 .thresh62 = 28,
735 .papdRateMaskHt20 = LE32(0x0c80c080),
736 .papdRateMaskHt40 = LE32(0x0080c080),
737 .futureModal = {
738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
739 },
740 },
741 .base_ext1 = {
742 .ant_div_control = 0,
743 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
744 },
745 .calFreqPier2G = {
746 FREQ2FBIN(2412, 1),
747 FREQ2FBIN(2437, 1),
748 FREQ2FBIN(2472, 1),
749 },
750 /* ar9300_cal_data_per_freq_op_loop 2g */
751 .calPierData2G = {
752 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
753 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
754 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
755 },
756 .calTarget_freqbin_Cck = {
757 FREQ2FBIN(2412, 1),
758 FREQ2FBIN(2472, 1),
759 },
760 .calTarget_freqbin_2G = {
761 FREQ2FBIN(2412, 1),
762 FREQ2FBIN(2437, 1),
763 FREQ2FBIN(2472, 1)
764 },
765 .calTarget_freqbin_2GHT20 = {
766 FREQ2FBIN(2412, 1),
767 FREQ2FBIN(2437, 1),
768 FREQ2FBIN(2472, 1)
769 },
770 .calTarget_freqbin_2GHT40 = {
771 FREQ2FBIN(2412, 1),
772 FREQ2FBIN(2437, 1),
773 FREQ2FBIN(2472, 1)
774 },
775 .calTargetPowerCck = {
776 /* 1L-5L,5S,11L,11S */
777 { {34, 34, 34, 34} },
778 { {34, 34, 34, 34} },
779 },
780 .calTargetPower2G = {
781 /* 6-24,36,48,54 */
782 { {34, 34, 32, 32} },
783 { {34, 34, 32, 32} },
784 { {34, 34, 32, 32} },
785 },
786 .calTargetPower2GHT20 = {
787 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
788 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
789 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
790 },
791 .calTargetPower2GHT40 = {
792 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
793 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
794 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
795 },
796 .ctlIndex_2G = {
797 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
798 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
799 },
800 .ctl_freqbin_2G = {
801 {
802 FREQ2FBIN(2412, 1),
803 FREQ2FBIN(2417, 1),
804 FREQ2FBIN(2457, 1),
805 FREQ2FBIN(2462, 1)
806 },
807 {
808 FREQ2FBIN(2412, 1),
809 FREQ2FBIN(2417, 1),
810 FREQ2FBIN(2462, 1),
811 0xFF,
812 },
813
814 {
815 FREQ2FBIN(2412, 1),
816 FREQ2FBIN(2417, 1),
817 FREQ2FBIN(2462, 1),
818 0xFF,
819 },
820 {
821 FREQ2FBIN(2422, 1),
822 FREQ2FBIN(2427, 1),
823 FREQ2FBIN(2447, 1),
824 FREQ2FBIN(2452, 1)
825 },
826
827 {
828 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
829 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
830 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
831 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
832 },
833
834 {
835 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
836 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
837 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
838 0,
839 },
840
841 {
842 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
843 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
844 FREQ2FBIN(2472, 1),
845 0,
846 },
847
848 {
849 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
850 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
851 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
852 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
853 },
854
855 {
856 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
857 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
858 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
859 },
860
861 {
862 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
863 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
864 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
865 0
866 },
867
868 {
869 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
870 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
871 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
872 0
873 },
874
875 {
876 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
877 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
878 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
879 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
880 }
881 },
882 .ctlPowerData_2G = {
883 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
884 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
885 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
886
887 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
888 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
889 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
890
891 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
892 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
893 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
894
895 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
896 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
897 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
898 },
899 .modalHeader5G = {
900 /* 4 idle,t1,t2,b (4 bits per setting) */
901 .antCtrlCommon = LE32(0x220),
902 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
903 .antCtrlCommon2 = LE32(0x11111),
904 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
905 .antCtrlChain = {
906 LE16(0x150), LE16(0x150), LE16(0x150),
907 },
908 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
909 .xatten1DB = {0, 0, 0},
910
911 /*
912 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
913 * for merlin (0xa20c/b20c 16:12
914 */
915 .xatten1Margin = {0, 0, 0},
916 .tempSlope = 68,
917 .voltSlope = 0,
918 /* spurChans spur channels in usual fbin coding format */
919 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
920 /* noiseFloorThreshCh Check if the register is per chain */
921 .noiseFloorThreshCh = {-1, 0, 0},
922 .ob = {3, 3, 3}, /* 3 chain */
923 .db_stage2 = {3, 3, 3}, /* 3 chain */
924 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
925 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
926 .xpaBiasLvl = 0xf,
927 .txFrameToDataStart = 0x0e,
928 .txFrameToPaOn = 0x0e,
929 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
930 .antennaGain = 0,
931 .switchSettling = 0x2d,
932 .adcDesiredSize = -30,
933 .txEndToXpaOff = 0,
934 .txEndToRxOn = 0x2,
935 .txFrameToXpaOn = 0xe,
936 .thresh62 = 28,
937 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
938 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
939 .futureModal = {
940 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
941 },
942 },
943 .base_ext2 = {
944 .tempSlopeLow = 72,
945 .tempSlopeHigh = 105,
946 .xatten1DBLow = {0, 0, 0},
947 .xatten1MarginLow = {0, 0, 0},
948 .xatten1DBHigh = {0, 0, 0},
949 .xatten1MarginHigh = {0, 0, 0}
950 },
951 .calFreqPier5G = {
952 FREQ2FBIN(5180, 0),
953 FREQ2FBIN(5240, 0),
954 FREQ2FBIN(5320, 0),
955 FREQ2FBIN(5400, 0),
956 FREQ2FBIN(5500, 0),
957 FREQ2FBIN(5600, 0),
958 FREQ2FBIN(5745, 0),
959 FREQ2FBIN(5785, 0)
960 },
961 .calPierData5G = {
962 {
963 {0, 0, 0, 0, 0},
964 {0, 0, 0, 0, 0},
965 {0, 0, 0, 0, 0},
966 {0, 0, 0, 0, 0},
967 {0, 0, 0, 0, 0},
968 {0, 0, 0, 0, 0},
969 {0, 0, 0, 0, 0},
970 {0, 0, 0, 0, 0},
971 },
972 {
973 {0, 0, 0, 0, 0},
974 {0, 0, 0, 0, 0},
975 {0, 0, 0, 0, 0},
976 {0, 0, 0, 0, 0},
977 {0, 0, 0, 0, 0},
978 {0, 0, 0, 0, 0},
979 {0, 0, 0, 0, 0},
980 {0, 0, 0, 0, 0},
981 },
982 {
983 {0, 0, 0, 0, 0},
984 {0, 0, 0, 0, 0},
985 {0, 0, 0, 0, 0},
986 {0, 0, 0, 0, 0},
987 {0, 0, 0, 0, 0},
988 {0, 0, 0, 0, 0},
989 {0, 0, 0, 0, 0},
990 {0, 0, 0, 0, 0},
991 },
992
993 },
994 .calTarget_freqbin_5G = {
995 FREQ2FBIN(5180, 0),
996 FREQ2FBIN(5220, 0),
997 FREQ2FBIN(5320, 0),
998 FREQ2FBIN(5400, 0),
999 FREQ2FBIN(5500, 0),
1000 FREQ2FBIN(5600, 0),
1001 FREQ2FBIN(5745, 0),
1002 FREQ2FBIN(5785, 0)
1003 },
1004 .calTarget_freqbin_5GHT20 = {
1005 FREQ2FBIN(5180, 0),
1006 FREQ2FBIN(5240, 0),
1007 FREQ2FBIN(5320, 0),
1008 FREQ2FBIN(5400, 0),
1009 FREQ2FBIN(5500, 0),
1010 FREQ2FBIN(5700, 0),
1011 FREQ2FBIN(5745, 0),
1012 FREQ2FBIN(5825, 0)
1013 },
1014 .calTarget_freqbin_5GHT40 = {
1015 FREQ2FBIN(5190, 0),
1016 FREQ2FBIN(5230, 0),
1017 FREQ2FBIN(5320, 0),
1018 FREQ2FBIN(5410, 0),
1019 FREQ2FBIN(5510, 0),
1020 FREQ2FBIN(5670, 0),
1021 FREQ2FBIN(5755, 0),
1022 FREQ2FBIN(5825, 0)
1023 },
1024 .calTargetPower5G = {
1025 /* 6-24,36,48,54 */
1026 { {42, 40, 40, 34} },
1027 { {42, 40, 40, 34} },
1028 { {42, 40, 40, 34} },
1029 { {42, 40, 40, 34} },
1030 { {42, 40, 40, 34} },
1031 { {42, 40, 40, 34} },
1032 { {42, 40, 40, 34} },
1033 { {42, 40, 40, 34} },
1034 },
1035 .calTargetPower5GHT20 = {
1036 /*
1037 * 0_8_16,1-3_9-11_17-19,
1038 * 4,5,6,7,12,13,14,15,20,21,22,23
1039 */
1040 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1041 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1042 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1043 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1044 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1045 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1046 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1047 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1048 },
1049 .calTargetPower5GHT40 = {
1050 /*
1051 * 0_8_16,1-3_9-11_17-19,
1052 * 4,5,6,7,12,13,14,15,20,21,22,23
1053 */
1054 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1055 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1056 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1057 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1058 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1059 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1060 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1061 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1062 },
1063 .ctlIndex_5G = {
1064 0x10, 0x16, 0x18, 0x40, 0x46,
1065 0x48, 0x30, 0x36, 0x38
1066 },
1067 .ctl_freqbin_5G = {
1068 {
1069 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1070 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1071 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1072 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1073 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1074 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1075 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1076 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1077 },
1078 {
1079 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1080 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1081 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1082 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1083 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1084 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1085 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1086 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1087 },
1088
1089 {
1090 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1091 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1092 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1093 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1094 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1095 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1096 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1097 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1098 },
1099
1100 {
1101 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1102 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1103 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1104 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1105 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1106 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1107 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1108 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1109 },
1110
1111 {
1112 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1113 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1114 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1115 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1116 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1117 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1118 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1119 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1120 },
1121
1122 {
1123 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1124 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1125 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1126 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1127 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1128 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1129 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1130 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1131 },
1132
1133 {
1134 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1135 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1136 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1137 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1138 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1139 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1140 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1141 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1142 },
1143
1144 {
1145 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1146 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1147 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1148 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1149 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1150 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1151 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1152 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1153 },
1154
1155 {
1156 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1157 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1158 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1159 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1160 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1161 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1162 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1163 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1164 }
1165 },
1166 .ctlPowerData_5G = {
1167 {
1168 {
1169 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1170 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1171 }
1172 },
1173 {
1174 {
1175 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1176 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1177 }
1178 },
1179 {
1180 {
1181 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1182 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1183 }
1184 },
1185 {
1186 {
1187 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1188 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1189 }
1190 },
1191 {
1192 {
1193 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1194 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1195 }
1196 },
1197 {
1198 {
1199 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1200 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1201 }
1202 },
1203 {
1204 {
1205 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1206 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1207 }
1208 },
1209 {
1210 {
1211 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1212 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1213 }
1214 },
1215 {
1216 {
1217 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1218 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1219 }
1220 },
1221 }
1222 };
1223
1224
1225 static const struct ar9300_eeprom ar9300_h112 = {
1226 .eepromVersion = 2,
1227 .templateVersion = 3,
1228 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1229 .custData = {"h112-241-f0000"},
1230 .baseEepHeader = {
1231 .regDmn = { LE16(0), LE16(0x1f) },
1232 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1233 .opCapFlags = {
1234 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1235 .eepMisc = 0,
1236 },
1237 .rfSilent = 0,
1238 .blueToothOptions = 0,
1239 .deviceCap = 0,
1240 .deviceType = 5, /* takes lower byte in eeprom location */
1241 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1242 .params_for_tuning_caps = {0, 0},
1243 .featureEnable = 0x0d,
1244 /*
1245 * bit0 - enable tx temp comp - disabled
1246 * bit1 - enable tx volt comp - disabled
1247 * bit2 - enable fastClock - enabled
1248 * bit3 - enable doubling - enabled
1249 * bit4 - enable internal regulator - disabled
1250 * bit5 - enable pa predistortion - disabled
1251 */
1252 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1253 .eepromWriteEnableGpio = 6,
1254 .wlanDisableGpio = 0,
1255 .wlanLedGpio = 8,
1256 .rxBandSelectGpio = 0xff,
1257 .txrxgain = 0x10,
1258 .swreg = 0,
1259 },
1260 .modalHeader2G = {
1261 /* ar9300_modal_eep_header 2g */
1262 /* 4 idle,t1,t2,b(4 bits per setting) */
1263 .antCtrlCommon = LE32(0x110),
1264 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1265 .antCtrlCommon2 = LE32(0x44444),
1266
1267 /*
1268 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1269 * rx1, rx12, b (2 bits each)
1270 */
1271 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1272
1273 /*
1274 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1275 * for ar9280 (0xa20c/b20c 5:0)
1276 */
1277 .xatten1DB = {0, 0, 0},
1278
1279 /*
1280 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1281 * for ar9280 (0xa20c/b20c 16:12
1282 */
1283 .xatten1Margin = {0, 0, 0},
1284 .tempSlope = 25,
1285 .voltSlope = 0,
1286
1287 /*
1288 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1289 * channels in usual fbin coding format
1290 */
1291 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1292
1293 /*
1294 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1295 * if the register is per chain
1296 */
1297 .noiseFloorThreshCh = {-1, 0, 0},
1298 .ob = {1, 1, 1},/* 3 chain */
1299 .db_stage2 = {1, 1, 1}, /* 3 chain */
1300 .db_stage3 = {0, 0, 0},
1301 .db_stage4 = {0, 0, 0},
1302 .xpaBiasLvl = 0,
1303 .txFrameToDataStart = 0x0e,
1304 .txFrameToPaOn = 0x0e,
1305 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1306 .antennaGain = 0,
1307 .switchSettling = 0x2c,
1308 .adcDesiredSize = -30,
1309 .txEndToXpaOff = 0,
1310 .txEndToRxOn = 0x2,
1311 .txFrameToXpaOn = 0xe,
1312 .thresh62 = 28,
1313 .papdRateMaskHt20 = LE32(0x80c080),
1314 .papdRateMaskHt40 = LE32(0x80c080),
1315 .futureModal = {
1316 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1317 },
1318 },
1319 .base_ext1 = {
1320 .ant_div_control = 0,
1321 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1322 },
1323 .calFreqPier2G = {
1324 FREQ2FBIN(2412, 1),
1325 FREQ2FBIN(2437, 1),
1326 FREQ2FBIN(2472, 1),
1327 },
1328 /* ar9300_cal_data_per_freq_op_loop 2g */
1329 .calPierData2G = {
1330 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1331 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1332 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1333 },
1334 .calTarget_freqbin_Cck = {
1335 FREQ2FBIN(2412, 1),
1336 FREQ2FBIN(2484, 1),
1337 },
1338 .calTarget_freqbin_2G = {
1339 FREQ2FBIN(2412, 1),
1340 FREQ2FBIN(2437, 1),
1341 FREQ2FBIN(2472, 1)
1342 },
1343 .calTarget_freqbin_2GHT20 = {
1344 FREQ2FBIN(2412, 1),
1345 FREQ2FBIN(2437, 1),
1346 FREQ2FBIN(2472, 1)
1347 },
1348 .calTarget_freqbin_2GHT40 = {
1349 FREQ2FBIN(2412, 1),
1350 FREQ2FBIN(2437, 1),
1351 FREQ2FBIN(2472, 1)
1352 },
1353 .calTargetPowerCck = {
1354 /* 1L-5L,5S,11L,11S */
1355 { {34, 34, 34, 34} },
1356 { {34, 34, 34, 34} },
1357 },
1358 .calTargetPower2G = {
1359 /* 6-24,36,48,54 */
1360 { {34, 34, 32, 32} },
1361 { {34, 34, 32, 32} },
1362 { {34, 34, 32, 32} },
1363 },
1364 .calTargetPower2GHT20 = {
1365 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1366 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1367 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1368 },
1369 .calTargetPower2GHT40 = {
1370 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1371 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1372 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1373 },
1374 .ctlIndex_2G = {
1375 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1376 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1377 },
1378 .ctl_freqbin_2G = {
1379 {
1380 FREQ2FBIN(2412, 1),
1381 FREQ2FBIN(2417, 1),
1382 FREQ2FBIN(2457, 1),
1383 FREQ2FBIN(2462, 1)
1384 },
1385 {
1386 FREQ2FBIN(2412, 1),
1387 FREQ2FBIN(2417, 1),
1388 FREQ2FBIN(2462, 1),
1389 0xFF,
1390 },
1391
1392 {
1393 FREQ2FBIN(2412, 1),
1394 FREQ2FBIN(2417, 1),
1395 FREQ2FBIN(2462, 1),
1396 0xFF,
1397 },
1398 {
1399 FREQ2FBIN(2422, 1),
1400 FREQ2FBIN(2427, 1),
1401 FREQ2FBIN(2447, 1),
1402 FREQ2FBIN(2452, 1)
1403 },
1404
1405 {
1406 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1409 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1410 },
1411
1412 {
1413 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1416 0,
1417 },
1418
1419 {
1420 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1421 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1422 FREQ2FBIN(2472, 1),
1423 0,
1424 },
1425
1426 {
1427 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1428 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1429 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1430 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1431 },
1432
1433 {
1434 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1435 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1436 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1437 },
1438
1439 {
1440 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1441 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1442 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1443 0
1444 },
1445
1446 {
1447 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1448 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1449 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1450 0
1451 },
1452
1453 {
1454 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1455 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1456 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1457 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1458 }
1459 },
1460 .ctlPowerData_2G = {
1461 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1462 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1463 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1464
1465 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1466 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1467 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1468
1469 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1470 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1471 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1472
1473 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1474 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1475 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1476 },
1477 .modalHeader5G = {
1478 /* 4 idle,t1,t2,b (4 bits per setting) */
1479 .antCtrlCommon = LE32(0x220),
1480 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1481 .antCtrlCommon2 = LE32(0x44444),
1482 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1483 .antCtrlChain = {
1484 LE16(0x150), LE16(0x150), LE16(0x150),
1485 },
1486 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1487 .xatten1DB = {0, 0, 0},
1488
1489 /*
1490 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1491 * for merlin (0xa20c/b20c 16:12
1492 */
1493 .xatten1Margin = {0, 0, 0},
1494 .tempSlope = 45,
1495 .voltSlope = 0,
1496 /* spurChans spur channels in usual fbin coding format */
1497 .spurChans = {0, 0, 0, 0, 0},
1498 /* noiseFloorThreshCh Check if the register is per chain */
1499 .noiseFloorThreshCh = {-1, 0, 0},
1500 .ob = {3, 3, 3}, /* 3 chain */
1501 .db_stage2 = {3, 3, 3}, /* 3 chain */
1502 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1503 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1504 .xpaBiasLvl = 0,
1505 .txFrameToDataStart = 0x0e,
1506 .txFrameToPaOn = 0x0e,
1507 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1508 .antennaGain = 0,
1509 .switchSettling = 0x2d,
1510 .adcDesiredSize = -30,
1511 .txEndToXpaOff = 0,
1512 .txEndToRxOn = 0x2,
1513 .txFrameToXpaOn = 0xe,
1514 .thresh62 = 28,
1515 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1516 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1517 .futureModal = {
1518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1519 },
1520 },
1521 .base_ext2 = {
1522 .tempSlopeLow = 40,
1523 .tempSlopeHigh = 50,
1524 .xatten1DBLow = {0, 0, 0},
1525 .xatten1MarginLow = {0, 0, 0},
1526 .xatten1DBHigh = {0, 0, 0},
1527 .xatten1MarginHigh = {0, 0, 0}
1528 },
1529 .calFreqPier5G = {
1530 FREQ2FBIN(5180, 0),
1531 FREQ2FBIN(5220, 0),
1532 FREQ2FBIN(5320, 0),
1533 FREQ2FBIN(5400, 0),
1534 FREQ2FBIN(5500, 0),
1535 FREQ2FBIN(5600, 0),
1536 FREQ2FBIN(5700, 0),
1537 FREQ2FBIN(5825, 0)
1538 },
1539 .calPierData5G = {
1540 {
1541 {0, 0, 0, 0, 0},
1542 {0, 0, 0, 0, 0},
1543 {0, 0, 0, 0, 0},
1544 {0, 0, 0, 0, 0},
1545 {0, 0, 0, 0, 0},
1546 {0, 0, 0, 0, 0},
1547 {0, 0, 0, 0, 0},
1548 {0, 0, 0, 0, 0},
1549 },
1550 {
1551 {0, 0, 0, 0, 0},
1552 {0, 0, 0, 0, 0},
1553 {0, 0, 0, 0, 0},
1554 {0, 0, 0, 0, 0},
1555 {0, 0, 0, 0, 0},
1556 {0, 0, 0, 0, 0},
1557 {0, 0, 0, 0, 0},
1558 {0, 0, 0, 0, 0},
1559 },
1560 {
1561 {0, 0, 0, 0, 0},
1562 {0, 0, 0, 0, 0},
1563 {0, 0, 0, 0, 0},
1564 {0, 0, 0, 0, 0},
1565 {0, 0, 0, 0, 0},
1566 {0, 0, 0, 0, 0},
1567 {0, 0, 0, 0, 0},
1568 {0, 0, 0, 0, 0},
1569 },
1570
1571 },
1572 .calTarget_freqbin_5G = {
1573 FREQ2FBIN(5180, 0),
1574 FREQ2FBIN(5240, 0),
1575 FREQ2FBIN(5320, 0),
1576 FREQ2FBIN(5400, 0),
1577 FREQ2FBIN(5500, 0),
1578 FREQ2FBIN(5600, 0),
1579 FREQ2FBIN(5700, 0),
1580 FREQ2FBIN(5825, 0)
1581 },
1582 .calTarget_freqbin_5GHT20 = {
1583 FREQ2FBIN(5180, 0),
1584 FREQ2FBIN(5240, 0),
1585 FREQ2FBIN(5320, 0),
1586 FREQ2FBIN(5400, 0),
1587 FREQ2FBIN(5500, 0),
1588 FREQ2FBIN(5700, 0),
1589 FREQ2FBIN(5745, 0),
1590 FREQ2FBIN(5825, 0)
1591 },
1592 .calTarget_freqbin_5GHT40 = {
1593 FREQ2FBIN(5180, 0),
1594 FREQ2FBIN(5240, 0),
1595 FREQ2FBIN(5320, 0),
1596 FREQ2FBIN(5400, 0),
1597 FREQ2FBIN(5500, 0),
1598 FREQ2FBIN(5700, 0),
1599 FREQ2FBIN(5745, 0),
1600 FREQ2FBIN(5825, 0)
1601 },
1602 .calTargetPower5G = {
1603 /* 6-24,36,48,54 */
1604 { {30, 30, 28, 24} },
1605 { {30, 30, 28, 24} },
1606 { {30, 30, 28, 24} },
1607 { {30, 30, 28, 24} },
1608 { {30, 30, 28, 24} },
1609 { {30, 30, 28, 24} },
1610 { {30, 30, 28, 24} },
1611 { {30, 30, 28, 24} },
1612 },
1613 .calTargetPower5GHT20 = {
1614 /*
1615 * 0_8_16,1-3_9-11_17-19,
1616 * 4,5,6,7,12,13,14,15,20,21,22,23
1617 */
1618 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1619 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1620 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1621 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1622 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1623 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1624 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1625 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1626 },
1627 .calTargetPower5GHT40 = {
1628 /*
1629 * 0_8_16,1-3_9-11_17-19,
1630 * 4,5,6,7,12,13,14,15,20,21,22,23
1631 */
1632 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1633 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1634 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1635 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1636 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1637 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1638 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1639 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1640 },
1641 .ctlIndex_5G = {
1642 0x10, 0x16, 0x18, 0x40, 0x46,
1643 0x48, 0x30, 0x36, 0x38
1644 },
1645 .ctl_freqbin_5G = {
1646 {
1647 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1648 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1649 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1650 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1651 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1652 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1653 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1654 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1655 },
1656 {
1657 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1658 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1659 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1660 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1661 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1662 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1663 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1664 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1665 },
1666
1667 {
1668 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1669 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1670 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1671 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1672 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1673 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1674 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1675 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1676 },
1677
1678 {
1679 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1680 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1681 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1682 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1683 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1684 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1685 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1686 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1687 },
1688
1689 {
1690 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1691 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1692 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1693 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1694 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1695 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1696 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1697 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1698 },
1699
1700 {
1701 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1702 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1703 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1704 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1705 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1706 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1707 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1708 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1709 },
1710
1711 {
1712 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1713 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1714 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1715 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1716 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1717 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1718 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1719 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1720 },
1721
1722 {
1723 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1724 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1725 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1726 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1727 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1728 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1729 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1730 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1731 },
1732
1733 {
1734 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1735 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1736 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1737 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1738 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1739 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1740 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1741 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1742 }
1743 },
1744 .ctlPowerData_5G = {
1745 {
1746 {
1747 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1748 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1749 }
1750 },
1751 {
1752 {
1753 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1754 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1755 }
1756 },
1757 {
1758 {
1759 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1760 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1761 }
1762 },
1763 {
1764 {
1765 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1766 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1767 }
1768 },
1769 {
1770 {
1771 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1772 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1773 }
1774 },
1775 {
1776 {
1777 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1778 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1779 }
1780 },
1781 {
1782 {
1783 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1784 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1785 }
1786 },
1787 {
1788 {
1789 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1790 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1791 }
1792 },
1793 {
1794 {
1795 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1796 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1797 }
1798 },
1799 }
1800 };
1801
1802
1803 static const struct ar9300_eeprom ar9300_x112 = {
1804 .eepromVersion = 2,
1805 .templateVersion = 5,
1806 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1807 .custData = {"x112-041-f0000"},
1808 .baseEepHeader = {
1809 .regDmn = { LE16(0), LE16(0x1f) },
1810 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1811 .opCapFlags = {
1812 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1813 .eepMisc = 0,
1814 },
1815 .rfSilent = 0,
1816 .blueToothOptions = 0,
1817 .deviceCap = 0,
1818 .deviceType = 5, /* takes lower byte in eeprom location */
1819 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1820 .params_for_tuning_caps = {0, 0},
1821 .featureEnable = 0x0d,
1822 /*
1823 * bit0 - enable tx temp comp - disabled
1824 * bit1 - enable tx volt comp - disabled
1825 * bit2 - enable fastclock - enabled
1826 * bit3 - enable doubling - enabled
1827 * bit4 - enable internal regulator - disabled
1828 * bit5 - enable pa predistortion - disabled
1829 */
1830 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1831 .eepromWriteEnableGpio = 6,
1832 .wlanDisableGpio = 0,
1833 .wlanLedGpio = 8,
1834 .rxBandSelectGpio = 0xff,
1835 .txrxgain = 0x0,
1836 .swreg = 0,
1837 },
1838 .modalHeader2G = {
1839 /* ar9300_modal_eep_header 2g */
1840 /* 4 idle,t1,t2,b(4 bits per setting) */
1841 .antCtrlCommon = LE32(0x110),
1842 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1843 .antCtrlCommon2 = LE32(0x22222),
1844
1845 /*
1846 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1847 * rx1, rx12, b (2 bits each)
1848 */
1849 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1850
1851 /*
1852 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1853 * for ar9280 (0xa20c/b20c 5:0)
1854 */
1855 .xatten1DB = {0x1b, 0x1b, 0x1b},
1856
1857 /*
1858 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1859 * for ar9280 (0xa20c/b20c 16:12
1860 */
1861 .xatten1Margin = {0x15, 0x15, 0x15},
1862 .tempSlope = 50,
1863 .voltSlope = 0,
1864
1865 /*
1866 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1867 * channels in usual fbin coding format
1868 */
1869 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1870
1871 /*
1872 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1873 * if the register is per chain
1874 */
1875 .noiseFloorThreshCh = {-1, 0, 0},
1876 .ob = {1, 1, 1},/* 3 chain */
1877 .db_stage2 = {1, 1, 1}, /* 3 chain */
1878 .db_stage3 = {0, 0, 0},
1879 .db_stage4 = {0, 0, 0},
1880 .xpaBiasLvl = 0,
1881 .txFrameToDataStart = 0x0e,
1882 .txFrameToPaOn = 0x0e,
1883 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1884 .antennaGain = 0,
1885 .switchSettling = 0x2c,
1886 .adcDesiredSize = -30,
1887 .txEndToXpaOff = 0,
1888 .txEndToRxOn = 0x2,
1889 .txFrameToXpaOn = 0xe,
1890 .thresh62 = 28,
1891 .papdRateMaskHt20 = LE32(0x0c80c080),
1892 .papdRateMaskHt40 = LE32(0x0080c080),
1893 .futureModal = {
1894 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1895 },
1896 },
1897 .base_ext1 = {
1898 .ant_div_control = 0,
1899 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1900 },
1901 .calFreqPier2G = {
1902 FREQ2FBIN(2412, 1),
1903 FREQ2FBIN(2437, 1),
1904 FREQ2FBIN(2472, 1),
1905 },
1906 /* ar9300_cal_data_per_freq_op_loop 2g */
1907 .calPierData2G = {
1908 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1909 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1910 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1911 },
1912 .calTarget_freqbin_Cck = {
1913 FREQ2FBIN(2412, 1),
1914 FREQ2FBIN(2472, 1),
1915 },
1916 .calTarget_freqbin_2G = {
1917 FREQ2FBIN(2412, 1),
1918 FREQ2FBIN(2437, 1),
1919 FREQ2FBIN(2472, 1)
1920 },
1921 .calTarget_freqbin_2GHT20 = {
1922 FREQ2FBIN(2412, 1),
1923 FREQ2FBIN(2437, 1),
1924 FREQ2FBIN(2472, 1)
1925 },
1926 .calTarget_freqbin_2GHT40 = {
1927 FREQ2FBIN(2412, 1),
1928 FREQ2FBIN(2437, 1),
1929 FREQ2FBIN(2472, 1)
1930 },
1931 .calTargetPowerCck = {
1932 /* 1L-5L,5S,11L,11s */
1933 { {38, 38, 38, 38} },
1934 { {38, 38, 38, 38} },
1935 },
1936 .calTargetPower2G = {
1937 /* 6-24,36,48,54 */
1938 { {38, 38, 36, 34} },
1939 { {38, 38, 36, 34} },
1940 { {38, 38, 34, 32} },
1941 },
1942 .calTargetPower2GHT20 = {
1943 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1944 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1945 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1946 },
1947 .calTargetPower2GHT40 = {
1948 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1949 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1950 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1951 },
1952 .ctlIndex_2G = {
1953 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1954 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1955 },
1956 .ctl_freqbin_2G = {
1957 {
1958 FREQ2FBIN(2412, 1),
1959 FREQ2FBIN(2417, 1),
1960 FREQ2FBIN(2457, 1),
1961 FREQ2FBIN(2462, 1)
1962 },
1963 {
1964 FREQ2FBIN(2412, 1),
1965 FREQ2FBIN(2417, 1),
1966 FREQ2FBIN(2462, 1),
1967 0xFF,
1968 },
1969
1970 {
1971 FREQ2FBIN(2412, 1),
1972 FREQ2FBIN(2417, 1),
1973 FREQ2FBIN(2462, 1),
1974 0xFF,
1975 },
1976 {
1977 FREQ2FBIN(2422, 1),
1978 FREQ2FBIN(2427, 1),
1979 FREQ2FBIN(2447, 1),
1980 FREQ2FBIN(2452, 1)
1981 },
1982
1983 {
1984 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1985 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1986 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1987 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1988 },
1989
1990 {
1991 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1994 0,
1995 },
1996
1997 {
1998 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1999 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2000 FREQ2FBIN(2472, 1),
2001 0,
2002 },
2003
2004 {
2005 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2006 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2007 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2008 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2009 },
2010
2011 {
2012 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2013 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2014 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2015 },
2016
2017 {
2018 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2019 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2020 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2021 0
2022 },
2023
2024 {
2025 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2026 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2027 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2028 0
2029 },
2030
2031 {
2032 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2033 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2034 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2035 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2036 }
2037 },
2038 .ctlPowerData_2G = {
2039 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2040 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2041 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2042
2043 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2044 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2045 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2046
2047 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2048 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2049 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2050
2051 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2052 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2053 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2054 },
2055 .modalHeader5G = {
2056 /* 4 idle,t1,t2,b (4 bits per setting) */
2057 .antCtrlCommon = LE32(0x110),
2058 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2059 .antCtrlCommon2 = LE32(0x22222),
2060 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2061 .antCtrlChain = {
2062 LE16(0x0), LE16(0x0), LE16(0x0),
2063 },
2064 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2065 .xatten1DB = {0x13, 0x19, 0x17},
2066
2067 /*
2068 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2069 * for merlin (0xa20c/b20c 16:12
2070 */
2071 .xatten1Margin = {0x19, 0x19, 0x19},
2072 .tempSlope = 70,
2073 .voltSlope = 15,
2074 /* spurChans spur channels in usual fbin coding format */
2075 .spurChans = {0, 0, 0, 0, 0},
2076 /* noiseFloorThreshch check if the register is per chain */
2077 .noiseFloorThreshCh = {-1, 0, 0},
2078 .ob = {3, 3, 3}, /* 3 chain */
2079 .db_stage2 = {3, 3, 3}, /* 3 chain */
2080 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2081 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2082 .xpaBiasLvl = 0,
2083 .txFrameToDataStart = 0x0e,
2084 .txFrameToPaOn = 0x0e,
2085 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2086 .antennaGain = 0,
2087 .switchSettling = 0x2d,
2088 .adcDesiredSize = -30,
2089 .txEndToXpaOff = 0,
2090 .txEndToRxOn = 0x2,
2091 .txFrameToXpaOn = 0xe,
2092 .thresh62 = 28,
2093 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2094 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2095 .futureModal = {
2096 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2097 },
2098 },
2099 .base_ext2 = {
2100 .tempSlopeLow = 72,
2101 .tempSlopeHigh = 105,
2102 .xatten1DBLow = {0x10, 0x14, 0x10},
2103 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2104 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2105 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2106 },
2107 .calFreqPier5G = {
2108 FREQ2FBIN(5180, 0),
2109 FREQ2FBIN(5220, 0),
2110 FREQ2FBIN(5320, 0),
2111 FREQ2FBIN(5400, 0),
2112 FREQ2FBIN(5500, 0),
2113 FREQ2FBIN(5600, 0),
2114 FREQ2FBIN(5700, 0),
2115 FREQ2FBIN(5785, 0)
2116 },
2117 .calPierData5G = {
2118 {
2119 {0, 0, 0, 0, 0},
2120 {0, 0, 0, 0, 0},
2121 {0, 0, 0, 0, 0},
2122 {0, 0, 0, 0, 0},
2123 {0, 0, 0, 0, 0},
2124 {0, 0, 0, 0, 0},
2125 {0, 0, 0, 0, 0},
2126 {0, 0, 0, 0, 0},
2127 },
2128 {
2129 {0, 0, 0, 0, 0},
2130 {0, 0, 0, 0, 0},
2131 {0, 0, 0, 0, 0},
2132 {0, 0, 0, 0, 0},
2133 {0, 0, 0, 0, 0},
2134 {0, 0, 0, 0, 0},
2135 {0, 0, 0, 0, 0},
2136 {0, 0, 0, 0, 0},
2137 },
2138 {
2139 {0, 0, 0, 0, 0},
2140 {0, 0, 0, 0, 0},
2141 {0, 0, 0, 0, 0},
2142 {0, 0, 0, 0, 0},
2143 {0, 0, 0, 0, 0},
2144 {0, 0, 0, 0, 0},
2145 {0, 0, 0, 0, 0},
2146 {0, 0, 0, 0, 0},
2147 },
2148
2149 },
2150 .calTarget_freqbin_5G = {
2151 FREQ2FBIN(5180, 0),
2152 FREQ2FBIN(5220, 0),
2153 FREQ2FBIN(5320, 0),
2154 FREQ2FBIN(5400, 0),
2155 FREQ2FBIN(5500, 0),
2156 FREQ2FBIN(5600, 0),
2157 FREQ2FBIN(5725, 0),
2158 FREQ2FBIN(5825, 0)
2159 },
2160 .calTarget_freqbin_5GHT20 = {
2161 FREQ2FBIN(5180, 0),
2162 FREQ2FBIN(5220, 0),
2163 FREQ2FBIN(5320, 0),
2164 FREQ2FBIN(5400, 0),
2165 FREQ2FBIN(5500, 0),
2166 FREQ2FBIN(5600, 0),
2167 FREQ2FBIN(5725, 0),
2168 FREQ2FBIN(5825, 0)
2169 },
2170 .calTarget_freqbin_5GHT40 = {
2171 FREQ2FBIN(5180, 0),
2172 FREQ2FBIN(5220, 0),
2173 FREQ2FBIN(5320, 0),
2174 FREQ2FBIN(5400, 0),
2175 FREQ2FBIN(5500, 0),
2176 FREQ2FBIN(5600, 0),
2177 FREQ2FBIN(5725, 0),
2178 FREQ2FBIN(5825, 0)
2179 },
2180 .calTargetPower5G = {
2181 /* 6-24,36,48,54 */
2182 { {32, 32, 28, 26} },
2183 { {32, 32, 28, 26} },
2184 { {32, 32, 28, 26} },
2185 { {32, 32, 26, 24} },
2186 { {32, 32, 26, 24} },
2187 { {32, 32, 24, 22} },
2188 { {30, 30, 24, 22} },
2189 { {30, 30, 24, 22} },
2190 },
2191 .calTargetPower5GHT20 = {
2192 /*
2193 * 0_8_16,1-3_9-11_17-19,
2194 * 4,5,6,7,12,13,14,15,20,21,22,23
2195 */
2196 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2197 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2198 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2199 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2200 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2201 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2202 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2203 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2204 },
2205 .calTargetPower5GHT40 = {
2206 /*
2207 * 0_8_16,1-3_9-11_17-19,
2208 * 4,5,6,7,12,13,14,15,20,21,22,23
2209 */
2210 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2211 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2212 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2213 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2214 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2215 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2216 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2217 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2218 },
2219 .ctlIndex_5G = {
2220 0x10, 0x16, 0x18, 0x40, 0x46,
2221 0x48, 0x30, 0x36, 0x38
2222 },
2223 .ctl_freqbin_5G = {
2224 {
2225 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2226 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2227 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2228 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2229 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2230 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2231 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2232 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2233 },
2234 {
2235 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2236 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2237 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2238 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2239 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2240 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2241 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2242 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2243 },
2244
2245 {
2246 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2247 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2248 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2249 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2250 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2251 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2252 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2253 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2254 },
2255
2256 {
2257 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2258 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2259 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2260 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2261 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2262 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2263 /* Data[3].ctledges[6].bchannel */ 0xFF,
2264 /* Data[3].ctledges[7].bchannel */ 0xFF,
2265 },
2266
2267 {
2268 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2269 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2270 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2271 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2272 /* Data[4].ctledges[4].bchannel */ 0xFF,
2273 /* Data[4].ctledges[5].bchannel */ 0xFF,
2274 /* Data[4].ctledges[6].bchannel */ 0xFF,
2275 /* Data[4].ctledges[7].bchannel */ 0xFF,
2276 },
2277
2278 {
2279 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2280 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2281 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2282 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2283 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2284 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2285 /* Data[5].ctledges[6].bchannel */ 0xFF,
2286 /* Data[5].ctledges[7].bchannel */ 0xFF
2287 },
2288
2289 {
2290 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2291 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2292 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2293 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2294 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2295 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2296 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2297 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2298 },
2299
2300 {
2301 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2302 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2303 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2304 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2305 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2306 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2307 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2308 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2309 },
2310
2311 {
2312 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2313 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2314 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2315 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2316 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2317 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2318 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2319 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2320 }
2321 },
2322 .ctlPowerData_5G = {
2323 {
2324 {
2325 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2326 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2327 }
2328 },
2329 {
2330 {
2331 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2332 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2333 }
2334 },
2335 {
2336 {
2337 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2338 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2339 }
2340 },
2341 {
2342 {
2343 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2344 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2345 }
2346 },
2347 {
2348 {
2349 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2350 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2351 }
2352 },
2353 {
2354 {
2355 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2356 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2357 }
2358 },
2359 {
2360 {
2361 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2362 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2363 }
2364 },
2365 {
2366 {
2367 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2368 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2369 }
2370 },
2371 {
2372 {
2373 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2374 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2375 }
2376 },
2377 }
2378 };
2379
2380 static const struct ar9300_eeprom ar9300_h116 = {
2381 .eepromVersion = 2,
2382 .templateVersion = 4,
2383 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2384 .custData = {"h116-041-f0000"},
2385 .baseEepHeader = {
2386 .regDmn = { LE16(0), LE16(0x1f) },
2387 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2388 .opCapFlags = {
2389 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2390 .eepMisc = 0,
2391 },
2392 .rfSilent = 0,
2393 .blueToothOptions = 0,
2394 .deviceCap = 0,
2395 .deviceType = 5, /* takes lower byte in eeprom location */
2396 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2397 .params_for_tuning_caps = {0, 0},
2398 .featureEnable = 0x0d,
2399 /*
2400 * bit0 - enable tx temp comp - disabled
2401 * bit1 - enable tx volt comp - disabled
2402 * bit2 - enable fastClock - enabled
2403 * bit3 - enable doubling - enabled
2404 * bit4 - enable internal regulator - disabled
2405 * bit5 - enable pa predistortion - disabled
2406 */
2407 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2408 .eepromWriteEnableGpio = 6,
2409 .wlanDisableGpio = 0,
2410 .wlanLedGpio = 8,
2411 .rxBandSelectGpio = 0xff,
2412 .txrxgain = 0x10,
2413 .swreg = 0,
2414 },
2415 .modalHeader2G = {
2416 /* ar9300_modal_eep_header 2g */
2417 /* 4 idle,t1,t2,b(4 bits per setting) */
2418 .antCtrlCommon = LE32(0x110),
2419 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2420 .antCtrlCommon2 = LE32(0x44444),
2421
2422 /*
2423 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2424 * rx1, rx12, b (2 bits each)
2425 */
2426 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2427
2428 /*
2429 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2430 * for ar9280 (0xa20c/b20c 5:0)
2431 */
2432 .xatten1DB = {0x1f, 0x1f, 0x1f},
2433
2434 /*
2435 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2436 * for ar9280 (0xa20c/b20c 16:12
2437 */
2438 .xatten1Margin = {0x12, 0x12, 0x12},
2439 .tempSlope = 25,
2440 .voltSlope = 0,
2441
2442 /*
2443 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2444 * channels in usual fbin coding format
2445 */
2446 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2447
2448 /*
2449 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2450 * if the register is per chain
2451 */
2452 .noiseFloorThreshCh = {-1, 0, 0},
2453 .ob = {1, 1, 1},/* 3 chain */
2454 .db_stage2 = {1, 1, 1}, /* 3 chain */
2455 .db_stage3 = {0, 0, 0},
2456 .db_stage4 = {0, 0, 0},
2457 .xpaBiasLvl = 0,
2458 .txFrameToDataStart = 0x0e,
2459 .txFrameToPaOn = 0x0e,
2460 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2461 .antennaGain = 0,
2462 .switchSettling = 0x2c,
2463 .adcDesiredSize = -30,
2464 .txEndToXpaOff = 0,
2465 .txEndToRxOn = 0x2,
2466 .txFrameToXpaOn = 0xe,
2467 .thresh62 = 28,
2468 .papdRateMaskHt20 = LE32(0x0c80C080),
2469 .papdRateMaskHt40 = LE32(0x0080C080),
2470 .futureModal = {
2471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2472 },
2473 },
2474 .base_ext1 = {
2475 .ant_div_control = 0,
2476 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2477 },
2478 .calFreqPier2G = {
2479 FREQ2FBIN(2412, 1),
2480 FREQ2FBIN(2437, 1),
2481 FREQ2FBIN(2472, 1),
2482 },
2483 /* ar9300_cal_data_per_freq_op_loop 2g */
2484 .calPierData2G = {
2485 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2486 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2487 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2488 },
2489 .calTarget_freqbin_Cck = {
2490 FREQ2FBIN(2412, 1),
2491 FREQ2FBIN(2472, 1),
2492 },
2493 .calTarget_freqbin_2G = {
2494 FREQ2FBIN(2412, 1),
2495 FREQ2FBIN(2437, 1),
2496 FREQ2FBIN(2472, 1)
2497 },
2498 .calTarget_freqbin_2GHT20 = {
2499 FREQ2FBIN(2412, 1),
2500 FREQ2FBIN(2437, 1),
2501 FREQ2FBIN(2472, 1)
2502 },
2503 .calTarget_freqbin_2GHT40 = {
2504 FREQ2FBIN(2412, 1),
2505 FREQ2FBIN(2437, 1),
2506 FREQ2FBIN(2472, 1)
2507 },
2508 .calTargetPowerCck = {
2509 /* 1L-5L,5S,11L,11S */
2510 { {34, 34, 34, 34} },
2511 { {34, 34, 34, 34} },
2512 },
2513 .calTargetPower2G = {
2514 /* 6-24,36,48,54 */
2515 { {34, 34, 32, 32} },
2516 { {34, 34, 32, 32} },
2517 { {34, 34, 32, 32} },
2518 },
2519 .calTargetPower2GHT20 = {
2520 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2521 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2522 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2523 },
2524 .calTargetPower2GHT40 = {
2525 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2526 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2527 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2528 },
2529 .ctlIndex_2G = {
2530 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2531 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2532 },
2533 .ctl_freqbin_2G = {
2534 {
2535 FREQ2FBIN(2412, 1),
2536 FREQ2FBIN(2417, 1),
2537 FREQ2FBIN(2457, 1),
2538 FREQ2FBIN(2462, 1)
2539 },
2540 {
2541 FREQ2FBIN(2412, 1),
2542 FREQ2FBIN(2417, 1),
2543 FREQ2FBIN(2462, 1),
2544 0xFF,
2545 },
2546
2547 {
2548 FREQ2FBIN(2412, 1),
2549 FREQ2FBIN(2417, 1),
2550 FREQ2FBIN(2462, 1),
2551 0xFF,
2552 },
2553 {
2554 FREQ2FBIN(2422, 1),
2555 FREQ2FBIN(2427, 1),
2556 FREQ2FBIN(2447, 1),
2557 FREQ2FBIN(2452, 1)
2558 },
2559
2560 {
2561 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2564 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2565 },
2566
2567 {
2568 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2570 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2571 0,
2572 },
2573
2574 {
2575 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2576 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2577 FREQ2FBIN(2472, 1),
2578 0,
2579 },
2580
2581 {
2582 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2583 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2584 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2585 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2586 },
2587
2588 {
2589 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2590 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2591 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2592 },
2593
2594 {
2595 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2596 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2597 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2598 0
2599 },
2600
2601 {
2602 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2603 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2604 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2605 0
2606 },
2607
2608 {
2609 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2610 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2611 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2612 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2613 }
2614 },
2615 .ctlPowerData_2G = {
2616 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2617 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2618 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2619
2620 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2621 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2622 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2623
2624 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2625 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2626 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2627
2628 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2629 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2630 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2631 },
2632 .modalHeader5G = {
2633 /* 4 idle,t1,t2,b (4 bits per setting) */
2634 .antCtrlCommon = LE32(0x220),
2635 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2636 .antCtrlCommon2 = LE32(0x44444),
2637 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2638 .antCtrlChain = {
2639 LE16(0x150), LE16(0x150), LE16(0x150),
2640 },
2641 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2642 .xatten1DB = {0x19, 0x19, 0x19},
2643
2644 /*
2645 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2646 * for merlin (0xa20c/b20c 16:12
2647 */
2648 .xatten1Margin = {0x14, 0x14, 0x14},
2649 .tempSlope = 70,
2650 .voltSlope = 0,
2651 /* spurChans spur channels in usual fbin coding format */
2652 .spurChans = {0, 0, 0, 0, 0},
2653 /* noiseFloorThreshCh Check if the register is per chain */
2654 .noiseFloorThreshCh = {-1, 0, 0},
2655 .ob = {3, 3, 3}, /* 3 chain */
2656 .db_stage2 = {3, 3, 3}, /* 3 chain */
2657 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2658 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2659 .xpaBiasLvl = 0,
2660 .txFrameToDataStart = 0x0e,
2661 .txFrameToPaOn = 0x0e,
2662 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2663 .antennaGain = 0,
2664 .switchSettling = 0x2d,
2665 .adcDesiredSize = -30,
2666 .txEndToXpaOff = 0,
2667 .txEndToRxOn = 0x2,
2668 .txFrameToXpaOn = 0xe,
2669 .thresh62 = 28,
2670 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2671 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2672 .futureModal = {
2673 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2674 },
2675 },
2676 .base_ext2 = {
2677 .tempSlopeLow = 35,
2678 .tempSlopeHigh = 50,
2679 .xatten1DBLow = {0, 0, 0},
2680 .xatten1MarginLow = {0, 0, 0},
2681 .xatten1DBHigh = {0, 0, 0},
2682 .xatten1MarginHigh = {0, 0, 0}
2683 },
2684 .calFreqPier5G = {
2685 FREQ2FBIN(5180, 0),
2686 FREQ2FBIN(5220, 0),
2687 FREQ2FBIN(5320, 0),
2688 FREQ2FBIN(5400, 0),
2689 FREQ2FBIN(5500, 0),
2690 FREQ2FBIN(5600, 0),
2691 FREQ2FBIN(5700, 0),
2692 FREQ2FBIN(5785, 0)
2693 },
2694 .calPierData5G = {
2695 {
2696 {0, 0, 0, 0, 0},
2697 {0, 0, 0, 0, 0},
2698 {0, 0, 0, 0, 0},
2699 {0, 0, 0, 0, 0},
2700 {0, 0, 0, 0, 0},
2701 {0, 0, 0, 0, 0},
2702 {0, 0, 0, 0, 0},
2703 {0, 0, 0, 0, 0},
2704 },
2705 {
2706 {0, 0, 0, 0, 0},
2707 {0, 0, 0, 0, 0},
2708 {0, 0, 0, 0, 0},
2709 {0, 0, 0, 0, 0},
2710 {0, 0, 0, 0, 0},
2711 {0, 0, 0, 0, 0},
2712 {0, 0, 0, 0, 0},
2713 {0, 0, 0, 0, 0},
2714 },
2715 {
2716 {0, 0, 0, 0, 0},
2717 {0, 0, 0, 0, 0},
2718 {0, 0, 0, 0, 0},
2719 {0, 0, 0, 0, 0},
2720 {0, 0, 0, 0, 0},
2721 {0, 0, 0, 0, 0},
2722 {0, 0, 0, 0, 0},
2723 {0, 0, 0, 0, 0},
2724 },
2725
2726 },
2727 .calTarget_freqbin_5G = {
2728 FREQ2FBIN(5180, 0),
2729 FREQ2FBIN(5240, 0),
2730 FREQ2FBIN(5320, 0),
2731 FREQ2FBIN(5400, 0),
2732 FREQ2FBIN(5500, 0),
2733 FREQ2FBIN(5600, 0),
2734 FREQ2FBIN(5700, 0),
2735 FREQ2FBIN(5825, 0)
2736 },
2737 .calTarget_freqbin_5GHT20 = {
2738 FREQ2FBIN(5180, 0),
2739 FREQ2FBIN(5240, 0),
2740 FREQ2FBIN(5320, 0),
2741 FREQ2FBIN(5400, 0),
2742 FREQ2FBIN(5500, 0),
2743 FREQ2FBIN(5700, 0),
2744 FREQ2FBIN(5745, 0),
2745 FREQ2FBIN(5825, 0)
2746 },
2747 .calTarget_freqbin_5GHT40 = {
2748 FREQ2FBIN(5180, 0),
2749 FREQ2FBIN(5240, 0),
2750 FREQ2FBIN(5320, 0),
2751 FREQ2FBIN(5400, 0),
2752 FREQ2FBIN(5500, 0),
2753 FREQ2FBIN(5700, 0),
2754 FREQ2FBIN(5745, 0),
2755 FREQ2FBIN(5825, 0)
2756 },
2757 .calTargetPower5G = {
2758 /* 6-24,36,48,54 */
2759 { {30, 30, 28, 24} },
2760 { {30, 30, 28, 24} },
2761 { {30, 30, 28, 24} },
2762 { {30, 30, 28, 24} },
2763 { {30, 30, 28, 24} },
2764 { {30, 30, 28, 24} },
2765 { {30, 30, 28, 24} },
2766 { {30, 30, 28, 24} },
2767 },
2768 .calTargetPower5GHT20 = {
2769 /*
2770 * 0_8_16,1-3_9-11_17-19,
2771 * 4,5,6,7,12,13,14,15,20,21,22,23
2772 */
2773 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2774 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2775 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2776 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2777 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2778 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2779 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2780 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2781 },
2782 .calTargetPower5GHT40 = {
2783 /*
2784 * 0_8_16,1-3_9-11_17-19,
2785 * 4,5,6,7,12,13,14,15,20,21,22,23
2786 */
2787 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2788 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2789 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2790 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2791 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2792 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2793 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2794 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2795 },
2796 .ctlIndex_5G = {
2797 0x10, 0x16, 0x18, 0x40, 0x46,
2798 0x48, 0x30, 0x36, 0x38
2799 },
2800 .ctl_freqbin_5G = {
2801 {
2802 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2803 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2804 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2805 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2806 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2807 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2808 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2809 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2810 },
2811 {
2812 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2813 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2814 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2815 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2816 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2817 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2818 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2819 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2820 },
2821
2822 {
2823 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2824 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2825 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2826 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2827 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2828 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2829 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2830 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2831 },
2832
2833 {
2834 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2835 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2836 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2837 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2838 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2839 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2840 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2841 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2842 },
2843
2844 {
2845 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2846 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2847 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2848 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2849 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2850 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2851 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2852 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2853 },
2854
2855 {
2856 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2857 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2858 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2859 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2860 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2861 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2862 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2863 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2864 },
2865
2866 {
2867 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2868 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2869 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2870 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2871 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2872 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2873 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2874 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2875 },
2876
2877 {
2878 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2879 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2880 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2881 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2882 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2883 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2884 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2885 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2886 },
2887
2888 {
2889 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2890 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2891 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2892 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2893 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2894 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2895 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2896 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2897 }
2898 },
2899 .ctlPowerData_5G = {
2900 {
2901 {
2902 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2903 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2904 }
2905 },
2906 {
2907 {
2908 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2909 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2910 }
2911 },
2912 {
2913 {
2914 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2915 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2916 }
2917 },
2918 {
2919 {
2920 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2921 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2922 }
2923 },
2924 {
2925 {
2926 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2927 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2928 }
2929 },
2930 {
2931 {
2932 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2933 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2934 }
2935 },
2936 {
2937 {
2938 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2939 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2940 }
2941 },
2942 {
2943 {
2944 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2945 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2946 }
2947 },
2948 {
2949 {
2950 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2951 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2952 }
2953 },
2954 }
2955 };
2956
2957
2958 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2959 &ar9300_default,
2960 &ar9300_x112,
2961 &ar9300_h116,
2962 &ar9300_h112,
2963 &ar9300_x113,
2964 };
2965
2966 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2967 {
2968 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2969 int it;
2970
2971 for (it = 0; it < N_LOOP; it++)
2972 if (ar9300_eep_templates[it]->templateVersion == id)
2973 return ar9300_eep_templates[it];
2974 return NULL;
2975 #undef N_LOOP
2976 }
2977
2978
2979 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2980 {
2981 if (fbin == AR5416_BCHAN_UNUSED)
2982 return fbin;
2983
2984 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2985 }
2986
2987 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2988 {
2989 return 0;
2990 }
2991
2992 static int interpolate(int x, int xa, int xb, int ya, int yb)
2993 {
2994 int bf, factor, plus;
2995
2996 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2997 factor = bf / 2;
2998 plus = bf % 2;
2999 return ya + factor + plus;
3000 }
3001
3002 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3003 enum eeprom_param param)
3004 {
3005 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3006 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3007
3008 switch (param) {
3009 case EEP_MAC_LSW:
3010 return get_unaligned_be16(eep->macAddr);
3011 case EEP_MAC_MID:
3012 return get_unaligned_be16(eep->macAddr + 2);
3013 case EEP_MAC_MSW:
3014 return get_unaligned_be16(eep->macAddr + 4);
3015 case EEP_REG_0:
3016 return le16_to_cpu(pBase->regDmn[0]);
3017 case EEP_REG_1:
3018 return le16_to_cpu(pBase->regDmn[1]);
3019 case EEP_OP_CAP:
3020 return pBase->deviceCap;
3021 case EEP_OP_MODE:
3022 return pBase->opCapFlags.opFlags;
3023 case EEP_RF_SILENT:
3024 return pBase->rfSilent;
3025 case EEP_TX_MASK:
3026 return (pBase->txrxMask >> 4) & 0xf;
3027 case EEP_RX_MASK:
3028 return pBase->txrxMask & 0xf;
3029 case EEP_DRIVE_STRENGTH:
3030 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3031 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3032 case EEP_INTERNAL_REGULATOR:
3033 /* Bit 4 is internal regulator flag */
3034 return (pBase->featureEnable & 0x10) >> 4;
3035 case EEP_SWREG:
3036 return le32_to_cpu(pBase->swreg);
3037 case EEP_PAPRD:
3038 return !!(pBase->featureEnable & BIT(5));
3039 case EEP_CHAIN_MASK_REDUCE:
3040 return (pBase->miscConfiguration >> 0x3) & 0x1;
3041 case EEP_ANT_DIV_CTL1:
3042 return eep->base_ext1.ant_div_control;
3043 default:
3044 return 0;
3045 }
3046 }
3047
3048 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3049 u8 *buffer)
3050 {
3051 u16 val;
3052
3053 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3054 return false;
3055
3056 *buffer = (val >> (8 * (address % 2))) & 0xff;
3057 return true;
3058 }
3059
3060 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3061 u8 *buffer)
3062 {
3063 u16 val;
3064
3065 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3066 return false;
3067
3068 buffer[0] = val >> 8;
3069 buffer[1] = val & 0xff;
3070
3071 return true;
3072 }
3073
3074 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3075 int count)
3076 {
3077 struct ath_common *common = ath9k_hw_common(ah);
3078 int i;
3079
3080 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3081 ath_dbg(common, ATH_DBG_EEPROM,
3082 "eeprom address not in range\n");
3083 return false;
3084 }
3085
3086 /*
3087 * Since we're reading the bytes in reverse order from a little-endian
3088 * word stream, an even address means we only use the lower half of
3089 * the 16-bit word at that address
3090 */
3091 if (address % 2 == 0) {
3092 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3093 goto error;
3094
3095 count--;
3096 }
3097
3098 for (i = 0; i < count / 2; i++) {
3099 if (!ar9300_eeprom_read_word(common, address, buffer))
3100 goto error;
3101
3102 address -= 2;
3103 buffer += 2;
3104 }
3105
3106 if (count % 2)
3107 if (!ar9300_eeprom_read_byte(common, address, buffer))
3108 goto error;
3109
3110 return true;
3111
3112 error:
3113 ath_dbg(common, ATH_DBG_EEPROM,
3114 "unable to read eeprom region at offset %d\n", address);
3115 return false;
3116 }
3117
3118 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3119 {
3120 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3121
3122 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3123 AR9300_OTP_STATUS_VALID, 1000))
3124 return false;
3125
3126 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3127 return true;
3128 }
3129
3130 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3131 int count)
3132 {
3133 u32 data;
3134 int i;
3135
3136 for (i = 0; i < count; i++) {
3137 int offset = 8 * ((address - i) % 4);
3138 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3139 return false;
3140
3141 buffer[i] = (data >> offset) & 0xff;
3142 }
3143
3144 return true;
3145 }
3146
3147
3148 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3149 int *length, int *major, int *minor)
3150 {
3151 unsigned long value[4];
3152
3153 value[0] = best[0];
3154 value[1] = best[1];
3155 value[2] = best[2];
3156 value[3] = best[3];
3157 *code = ((value[0] >> 5) & 0x0007);
3158 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3159 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3160 *major = (value[2] & 0x000f);
3161 *minor = (value[3] & 0x00ff);
3162 }
3163
3164 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3165 {
3166 int it, checksum = 0;
3167
3168 for (it = 0; it < dsize; it++) {
3169 checksum += data[it];
3170 checksum &= 0xffff;
3171 }
3172
3173 return checksum;
3174 }
3175
3176 static bool ar9300_uncompress_block(struct ath_hw *ah,
3177 u8 *mptr,
3178 int mdataSize,
3179 u8 *block,
3180 int size)
3181 {
3182 int it;
3183 int spot;
3184 int offset;
3185 int length;
3186 struct ath_common *common = ath9k_hw_common(ah);
3187
3188 spot = 0;
3189
3190 for (it = 0; it < size; it += (length+2)) {
3191 offset = block[it];
3192 offset &= 0xff;
3193 spot += offset;
3194 length = block[it+1];
3195 length &= 0xff;
3196
3197 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3198 ath_dbg(common, ATH_DBG_EEPROM,
3199 "Restore at %d: spot=%d offset=%d length=%d\n",
3200 it, spot, offset, length);
3201 memcpy(&mptr[spot], &block[it+2], length);
3202 spot += length;
3203 } else if (length > 0) {
3204 ath_dbg(common, ATH_DBG_EEPROM,
3205 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3206 it, spot, offset, length);
3207 return false;
3208 }
3209 }
3210 return true;
3211 }
3212
3213 static int ar9300_compress_decision(struct ath_hw *ah,
3214 int it,
3215 int code,
3216 int reference,
3217 u8 *mptr,
3218 u8 *word, int length, int mdata_size)
3219 {
3220 struct ath_common *common = ath9k_hw_common(ah);
3221 const struct ar9300_eeprom *eep = NULL;
3222
3223 switch (code) {
3224 case _CompressNone:
3225 if (length != mdata_size) {
3226 ath_dbg(common, ATH_DBG_EEPROM,
3227 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3228 mdata_size, length);
3229 return -1;
3230 }
3231 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3232 ath_dbg(common, ATH_DBG_EEPROM,
3233 "restored eeprom %d: uncompressed, length %d\n",
3234 it, length);
3235 break;
3236 case _CompressBlock:
3237 if (reference == 0) {
3238 } else {
3239 eep = ar9003_eeprom_struct_find_by_id(reference);
3240 if (eep == NULL) {
3241 ath_dbg(common, ATH_DBG_EEPROM,
3242 "can't find reference eeprom struct %d\n",
3243 reference);
3244 return -1;
3245 }
3246 memcpy(mptr, eep, mdata_size);
3247 }
3248 ath_dbg(common, ATH_DBG_EEPROM,
3249 "restore eeprom %d: block, reference %d, length %d\n",
3250 it, reference, length);
3251 ar9300_uncompress_block(ah, mptr, mdata_size,
3252 (u8 *) (word + COMP_HDR_LEN), length);
3253 break;
3254 default:
3255 ath_dbg(common, ATH_DBG_EEPROM,
3256 "unknown compression code %d\n", code);
3257 return -1;
3258 }
3259 return 0;
3260 }
3261
3262 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3263 int count);
3264
3265 static bool ar9300_check_header(void *data)
3266 {
3267 u32 *word = data;
3268 return !(*word == 0 || *word == ~0);
3269 }
3270
3271 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3272 int base_addr)
3273 {
3274 u8 header[4];
3275
3276 if (!read(ah, base_addr, header, 4))
3277 return false;
3278
3279 return ar9300_check_header(header);
3280 }
3281
3282 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3283 int mdata_size)
3284 {
3285 struct ath_common *common = ath9k_hw_common(ah);
3286 u16 *data = (u16 *) mptr;
3287 int i;
3288
3289 for (i = 0; i < mdata_size / 2; i++, data++)
3290 ath9k_hw_nvram_read(common, i, data);
3291
3292 return 0;
3293 }
3294 /*
3295 * Read the configuration data from the eeprom.
3296 * The data can be put in any specified memory buffer.
3297 *
3298 * Returns -1 on error.
3299 * Returns address of next memory location on success.
3300 */
3301 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3302 u8 *mptr, int mdata_size)
3303 {
3304 #define MDEFAULT 15
3305 #define MSTATE 100
3306 int cptr;
3307 u8 *word;
3308 int code;
3309 int reference, length, major, minor;
3310 int osize;
3311 int it;
3312 u16 checksum, mchecksum;
3313 struct ath_common *common = ath9k_hw_common(ah);
3314 eeprom_read_op read;
3315
3316 if (ath9k_hw_use_flash(ah))
3317 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3318
3319 word = kzalloc(2048, GFP_KERNEL);
3320 if (!word)
3321 return -1;
3322
3323 memcpy(mptr, &ar9300_default, mdata_size);
3324
3325 read = ar9300_read_eeprom;
3326 if (AR_SREV_9485(ah))
3327 cptr = AR9300_BASE_ADDR_4K;
3328 else if (AR_SREV_9330(ah))
3329 cptr = AR9300_BASE_ADDR_512;
3330 else
3331 cptr = AR9300_BASE_ADDR;
3332 ath_dbg(common, ATH_DBG_EEPROM,
3333 "Trying EEPROM access at Address 0x%04x\n", cptr);
3334 if (ar9300_check_eeprom_header(ah, read, cptr))
3335 goto found;
3336
3337 cptr = AR9300_BASE_ADDR_512;
3338 ath_dbg(common, ATH_DBG_EEPROM,
3339 "Trying EEPROM access at Address 0x%04x\n", cptr);
3340 if (ar9300_check_eeprom_header(ah, read, cptr))
3341 goto found;
3342
3343 read = ar9300_read_otp;
3344 cptr = AR9300_BASE_ADDR;
3345 ath_dbg(common, ATH_DBG_EEPROM,
3346 "Trying OTP access at Address 0x%04x\n", cptr);
3347 if (ar9300_check_eeprom_header(ah, read, cptr))
3348 goto found;
3349
3350 cptr = AR9300_BASE_ADDR_512;
3351 ath_dbg(common, ATH_DBG_EEPROM,
3352 "Trying OTP access at Address 0x%04x\n", cptr);
3353 if (ar9300_check_eeprom_header(ah, read, cptr))
3354 goto found;
3355
3356 goto fail;
3357
3358 found:
3359 ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
3360
3361 for (it = 0; it < MSTATE; it++) {
3362 if (!read(ah, cptr, word, COMP_HDR_LEN))
3363 goto fail;
3364
3365 if (!ar9300_check_header(word))
3366 break;
3367
3368 ar9300_comp_hdr_unpack(word, &code, &reference,
3369 &length, &major, &minor);
3370 ath_dbg(common, ATH_DBG_EEPROM,
3371 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3372 cptr, code, reference, length, major, minor);
3373 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3374 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3375 ath_dbg(common, ATH_DBG_EEPROM,
3376 "Skipping bad header\n");
3377 cptr -= COMP_HDR_LEN;
3378 continue;
3379 }
3380
3381 osize = length;
3382 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3383 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3384 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3385 ath_dbg(common, ATH_DBG_EEPROM,
3386 "checksum %x %x\n", checksum, mchecksum);
3387 if (checksum == mchecksum) {
3388 ar9300_compress_decision(ah, it, code, reference, mptr,
3389 word, length, mdata_size);
3390 } else {
3391 ath_dbg(common, ATH_DBG_EEPROM,
3392 "skipping block with bad checksum\n");
3393 }
3394 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3395 }
3396
3397 kfree(word);
3398 return cptr;
3399
3400 fail:
3401 kfree(word);
3402 return -1;
3403 }
3404
3405 /*
3406 * Restore the configuration structure by reading the eeprom.
3407 * This function destroys any existing in-memory structure
3408 * content.
3409 */
3410 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3411 {
3412 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3413
3414 if (ar9300_eeprom_restore_internal(ah, mptr,
3415 sizeof(struct ar9300_eeprom)) < 0)
3416 return false;
3417
3418 return true;
3419 }
3420
3421 /* XXX: review hardware docs */
3422 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3423 {
3424 return ah->eeprom.ar9300_eep.eepromVersion;
3425 }
3426
3427 /* XXX: could be read from the eepromVersion, not sure yet */
3428 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3429 {
3430 return 0;
3431 }
3432
3433 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3434 {
3435 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3436
3437 if (is2ghz)
3438 return eep->modalHeader2G.xpaBiasLvl;
3439 else
3440 return eep->modalHeader5G.xpaBiasLvl;
3441 }
3442
3443 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3444 {
3445 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3446
3447 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3448 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3449 else {
3450 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3451 REG_RMW_FIELD(ah, AR_CH0_THERM,
3452 AR_CH0_THERM_XPABIASLVL_MSB,
3453 bias >> 2);
3454 REG_RMW_FIELD(ah, AR_CH0_THERM,
3455 AR_CH0_THERM_XPASHORT2GND, 1);
3456 }
3457 }
3458
3459 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3460 {
3461 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3462 __le32 val;
3463
3464 if (is2ghz)
3465 val = eep->modalHeader2G.antCtrlCommon;
3466 else
3467 val = eep->modalHeader5G.antCtrlCommon;
3468 return le32_to_cpu(val);
3469 }
3470
3471 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3472 {
3473 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3474 __le32 val;
3475
3476 if (is2ghz)
3477 val = eep->modalHeader2G.antCtrlCommon2;
3478 else
3479 val = eep->modalHeader5G.antCtrlCommon2;
3480 return le32_to_cpu(val);
3481 }
3482
3483 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3484 int chain,
3485 bool is2ghz)
3486 {
3487 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3488 __le16 val = 0;
3489
3490 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3491 if (is2ghz)
3492 val = eep->modalHeader2G.antCtrlChain[chain];
3493 else
3494 val = eep->modalHeader5G.antCtrlChain[chain];
3495 }
3496
3497 return le16_to_cpu(val);
3498 }
3499
3500 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3501 {
3502 int chain;
3503 u32 regval;
3504 u32 ant_div_ctl1;
3505 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3506 AR_PHY_SWITCH_CHAIN_0,
3507 AR_PHY_SWITCH_CHAIN_1,
3508 AR_PHY_SWITCH_CHAIN_2,
3509 };
3510
3511 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3512
3513 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3514
3515 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3516 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3517
3518 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3519 if ((ah->rxchainmask & BIT(chain)) ||
3520 (ah->txchainmask & BIT(chain))) {
3521 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3522 is2ghz);
3523 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3524 AR_SWITCH_TABLE_ALL, value);
3525 }
3526 }
3527
3528 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3529 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3530 /*
3531 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3532 * are the fields present
3533 */
3534 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3535 regval &= (~AR_ANT_DIV_CTRL_ALL);
3536 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3537 /* enable_lnadiv */
3538 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3539 regval |= ((value >> 6) & 0x1) <<
3540 AR_PHY_9485_ANT_DIV_LNADIV_S;
3541 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3542
3543 /*enable fast_div */
3544 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3545 regval &= (~AR_FAST_DIV_ENABLE);
3546 regval |= ((value >> 7) & 0x1) <<
3547 AR_FAST_DIV_ENABLE_S;
3548 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3549 ant_div_ctl1 =
3550 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3551 /* check whether antenna diversity is enabled */
3552 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3553 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3554 /*
3555 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3556 * main_tb, alt_tb
3557 */
3558 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3559 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3560 AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3561 AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3562 /* by default use LNA1 for the main antenna */
3563 regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3564 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3565 regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3566 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3567 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3568 }
3569
3570
3571 }
3572
3573 }
3574
3575 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3576 {
3577 int drive_strength;
3578 unsigned long reg;
3579
3580 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3581
3582 if (!drive_strength)
3583 return;
3584
3585 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3586 reg &= ~0x00ffffc0;
3587 reg |= 0x5 << 21;
3588 reg |= 0x5 << 18;
3589 reg |= 0x5 << 15;
3590 reg |= 0x5 << 12;
3591 reg |= 0x5 << 9;
3592 reg |= 0x5 << 6;
3593 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3594
3595 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3596 reg &= ~0xffffffe0;
3597 reg |= 0x5 << 29;
3598 reg |= 0x5 << 26;
3599 reg |= 0x5 << 23;
3600 reg |= 0x5 << 20;
3601 reg |= 0x5 << 17;
3602 reg |= 0x5 << 14;
3603 reg |= 0x5 << 11;
3604 reg |= 0x5 << 8;
3605 reg |= 0x5 << 5;
3606 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3607
3608 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3609 reg &= ~0xff800000;
3610 reg |= 0x5 << 29;
3611 reg |= 0x5 << 26;
3612 reg |= 0x5 << 23;
3613 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3614 }
3615
3616 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3617 struct ath9k_channel *chan)
3618 {
3619 int f[3], t[3];
3620 u16 value;
3621 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3622
3623 if (chain >= 0 && chain < 3) {
3624 if (IS_CHAN_2GHZ(chan))
3625 return eep->modalHeader2G.xatten1DB[chain];
3626 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3627 t[0] = eep->base_ext2.xatten1DBLow[chain];
3628 f[0] = 5180;
3629 t[1] = eep->modalHeader5G.xatten1DB[chain];
3630 f[1] = 5500;
3631 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3632 f[2] = 5785;
3633 value = ar9003_hw_power_interpolate((s32) chan->channel,
3634 f, t, 3);
3635 return value;
3636 } else
3637 return eep->modalHeader5G.xatten1DB[chain];
3638 }
3639
3640 return 0;
3641 }
3642
3643
3644 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3645 struct ath9k_channel *chan)
3646 {
3647 int f[3], t[3];
3648 u16 value;
3649 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3650
3651 if (chain >= 0 && chain < 3) {
3652 if (IS_CHAN_2GHZ(chan))
3653 return eep->modalHeader2G.xatten1Margin[chain];
3654 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3655 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3656 f[0] = 5180;
3657 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3658 f[1] = 5500;
3659 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3660 f[2] = 5785;
3661 value = ar9003_hw_power_interpolate((s32) chan->channel,
3662 f, t, 3);
3663 return value;
3664 } else
3665 return eep->modalHeader5G.xatten1Margin[chain];
3666 }
3667
3668 return 0;
3669 }
3670
3671 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3672 {
3673 int i;
3674 u16 value;
3675 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3676 AR_PHY_EXT_ATTEN_CTL_1,
3677 AR_PHY_EXT_ATTEN_CTL_2,
3678 };
3679
3680 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3681 for (i = 0; i < 3; i++) {
3682 if (ah->txchainmask & BIT(i)) {
3683 value = ar9003_hw_atten_chain_get(ah, i, chan);
3684 REG_RMW_FIELD(ah, ext_atten_reg[i],
3685 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3686
3687 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3688 REG_RMW_FIELD(ah, ext_atten_reg[i],
3689 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3690 value);
3691 }
3692 }
3693 }
3694
3695 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3696 {
3697 int timeout = 100;
3698
3699 while (pmu_set != REG_READ(ah, pmu_reg)) {
3700 if (timeout-- == 0)
3701 return false;
3702 REG_WRITE(ah, pmu_reg, pmu_set);
3703 udelay(10);
3704 }
3705
3706 return true;
3707 }
3708
3709 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3710 {
3711 int internal_regulator =
3712 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3713
3714 if (internal_regulator) {
3715 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3716 int reg_pmu_set;
3717
3718 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3719 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3720 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3721 return;
3722
3723 if (AR_SREV_9330(ah)) {
3724 if (ah->is_clk_25mhz) {
3725 reg_pmu_set = (3 << 1) | (8 << 4) |
3726 (3 << 8) | (1 << 14) |
3727 (6 << 17) | (1 << 20) |
3728 (3 << 24);
3729 } else {
3730 reg_pmu_set = (4 << 1) | (7 << 4) |
3731 (3 << 8) | (1 << 14) |
3732 (6 << 17) | (1 << 20) |
3733 (3 << 24);
3734 }
3735 } else {
3736 reg_pmu_set = (5 << 1) | (7 << 4) |
3737 (2 << 8) | (2 << 14) |
3738 (6 << 17) | (1 << 20) |
3739 (3 << 24) | (1 << 28);
3740 }
3741
3742 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3743 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3744 return;
3745
3746 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3747 | (4 << 26);
3748 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3749 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3750 return;
3751
3752 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3753 | (1 << 21);
3754 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3755 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3756 return;
3757 } else {
3758 /* Internal regulator is ON. Write swreg register. */
3759 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3760 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3761 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3762 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3763 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3764 /* Set REG_CONTROL1.SWREG_PROGRAM */
3765 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3766 REG_READ(ah,
3767 AR_RTC_REG_CONTROL1) |
3768 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3769 }
3770 } else {
3771 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3772 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3773 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3774 AR_PHY_PMU2_PGM))
3775 udelay(10);
3776
3777 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3778 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3779 AR_PHY_PMU1_PWD))
3780 udelay(10);
3781 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3782 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3783 AR_PHY_PMU2_PGM))
3784 udelay(10);
3785 } else
3786 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3787 (REG_READ(ah,
3788 AR_RTC_SLEEP_CLK) |
3789 AR_RTC_FORCE_SWREG_PRD));
3790 }
3791
3792 }
3793
3794 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3795 {
3796 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3797 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3798
3799 if (eep->baseEepHeader.featureEnable & 0x40) {
3800 tuning_caps_param &= 0x7f;
3801 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3802 tuning_caps_param);
3803 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3804 tuning_caps_param);
3805 }
3806 }
3807
3808 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3809 struct ath9k_channel *chan)
3810 {
3811 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3812 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3813 ar9003_hw_drive_strength_apply(ah);
3814 ar9003_hw_atten_apply(ah, chan);
3815 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
3816 ar9003_hw_internal_regulator_apply(ah);
3817 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3818 ar9003_hw_apply_tuning_caps(ah);
3819 }
3820
3821 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3822 struct ath9k_channel *chan)
3823 {
3824 }
3825
3826 /*
3827 * Returns the interpolated y value corresponding to the specified x value
3828 * from the np ordered pairs of data (px,py).
3829 * The pairs do not have to be in any order.
3830 * If the specified x value is less than any of the px,
3831 * the returned y value is equal to the py for the lowest px.
3832 * If the specified x value is greater than any of the px,
3833 * the returned y value is equal to the py for the highest px.
3834 */
3835 static int ar9003_hw_power_interpolate(int32_t x,
3836 int32_t *px, int32_t *py, u_int16_t np)
3837 {
3838 int ip = 0;
3839 int lx = 0, ly = 0, lhave = 0;
3840 int hx = 0, hy = 0, hhave = 0;
3841 int dx = 0;
3842 int y = 0;
3843
3844 lhave = 0;
3845 hhave = 0;
3846
3847 /* identify best lower and higher x calibration measurement */
3848 for (ip = 0; ip < np; ip++) {
3849 dx = x - px[ip];
3850
3851 /* this measurement is higher than our desired x */
3852 if (dx <= 0) {
3853 if (!hhave || dx > (x - hx)) {
3854 /* new best higher x measurement */
3855 hx = px[ip];
3856 hy = py[ip];
3857 hhave = 1;
3858 }
3859 }
3860 /* this measurement is lower than our desired x */
3861 if (dx >= 0) {
3862 if (!lhave || dx < (x - lx)) {
3863 /* new best lower x measurement */
3864 lx = px[ip];
3865 ly = py[ip];
3866 lhave = 1;
3867 }
3868 }
3869 }
3870
3871 /* the low x is good */
3872 if (lhave) {
3873 /* so is the high x */
3874 if (hhave) {
3875 /* they're the same, so just pick one */
3876 if (hx == lx)
3877 y = ly;
3878 else /* interpolate */
3879 y = interpolate(x, lx, hx, ly, hy);
3880 } else /* only low is good, use it */
3881 y = ly;
3882 } else if (hhave) /* only high is good, use it */
3883 y = hy;
3884 else /* nothing is good,this should never happen unless np=0, ???? */
3885 y = -(1 << 30);
3886 return y;
3887 }
3888
3889 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3890 u16 rateIndex, u16 freq, bool is2GHz)
3891 {
3892 u16 numPiers, i;
3893 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3894 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3895 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3896 struct cal_tgt_pow_legacy *pEepromTargetPwr;
3897 u8 *pFreqBin;
3898
3899 if (is2GHz) {
3900 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3901 pEepromTargetPwr = eep->calTargetPower2G;
3902 pFreqBin = eep->calTarget_freqbin_2G;
3903 } else {
3904 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3905 pEepromTargetPwr = eep->calTargetPower5G;
3906 pFreqBin = eep->calTarget_freqbin_5G;
3907 }
3908
3909 /*
3910 * create array of channels and targetpower from
3911 * targetpower piers stored on eeprom
3912 */
3913 for (i = 0; i < numPiers; i++) {
3914 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3915 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3916 }
3917
3918 /* interpolate to get target power for given frequency */
3919 return (u8) ar9003_hw_power_interpolate((s32) freq,
3920 freqArray,
3921 targetPowerArray, numPiers);
3922 }
3923
3924 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3925 u16 rateIndex,
3926 u16 freq, bool is2GHz)
3927 {
3928 u16 numPiers, i;
3929 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3930 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3931 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3932 struct cal_tgt_pow_ht *pEepromTargetPwr;
3933 u8 *pFreqBin;
3934
3935 if (is2GHz) {
3936 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3937 pEepromTargetPwr = eep->calTargetPower2GHT20;
3938 pFreqBin = eep->calTarget_freqbin_2GHT20;
3939 } else {
3940 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3941 pEepromTargetPwr = eep->calTargetPower5GHT20;
3942 pFreqBin = eep->calTarget_freqbin_5GHT20;
3943 }
3944
3945 /*
3946 * create array of channels and targetpower
3947 * from targetpower piers stored on eeprom
3948 */
3949 for (i = 0; i < numPiers; i++) {
3950 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3951 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3952 }
3953
3954 /* interpolate to get target power for given frequency */
3955 return (u8) ar9003_hw_power_interpolate((s32) freq,
3956 freqArray,
3957 targetPowerArray, numPiers);
3958 }
3959
3960 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3961 u16 rateIndex,
3962 u16 freq, bool is2GHz)
3963 {
3964 u16 numPiers, i;
3965 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3966 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3967 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3968 struct cal_tgt_pow_ht *pEepromTargetPwr;
3969 u8 *pFreqBin;
3970
3971 if (is2GHz) {
3972 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3973 pEepromTargetPwr = eep->calTargetPower2GHT40;
3974 pFreqBin = eep->calTarget_freqbin_2GHT40;
3975 } else {
3976 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3977 pEepromTargetPwr = eep->calTargetPower5GHT40;
3978 pFreqBin = eep->calTarget_freqbin_5GHT40;
3979 }
3980
3981 /*
3982 * create array of channels and targetpower from
3983 * targetpower piers stored on eeprom
3984 */
3985 for (i = 0; i < numPiers; i++) {
3986 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3987 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3988 }
3989
3990 /* interpolate to get target power for given frequency */
3991 return (u8) ar9003_hw_power_interpolate((s32) freq,
3992 freqArray,
3993 targetPowerArray, numPiers);
3994 }
3995
3996 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3997 u16 rateIndex, u16 freq)
3998 {
3999 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4000 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4001 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4002 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4003 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4004 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4005
4006 /*
4007 * create array of channels and targetpower from
4008 * targetpower piers stored on eeprom
4009 */
4010 for (i = 0; i < numPiers; i++) {
4011 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
4012 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4013 }
4014
4015 /* interpolate to get target power for given frequency */
4016 return (u8) ar9003_hw_power_interpolate((s32) freq,
4017 freqArray,
4018 targetPowerArray, numPiers);
4019 }
4020
4021 /* Set tx power registers to array of values passed in */
4022 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4023 {
4024 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4025 /* make sure forced gain is not set */
4026 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4027
4028 /* Write the OFDM power per rate set */
4029
4030 /* 6 (LSB), 9, 12, 18 (MSB) */
4031 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4032 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4033 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4034 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4035 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4036
4037 /* 24 (LSB), 36, 48, 54 (MSB) */
4038 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4039 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4040 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4041 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4042 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4043
4044 /* Write the CCK power per rate set */
4045
4046 /* 1L (LSB), reserved, 2L, 2S (MSB) */
4047 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4048 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4049 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4050 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4051 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4052
4053 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4054 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4055 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4056 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4057 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4058 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4059 );
4060
4061 /* Write the power for duplicated frames - HT40 */
4062
4063 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4064 REG_WRITE(ah, 0xa3e0,
4065 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4066 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4067 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4068 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4069 );
4070
4071 /* Write the HT20 power per rate set */
4072
4073 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4074 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4075 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4076 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4077 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4078 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4079 );
4080
4081 /* 6 (LSB), 7, 12, 13 (MSB) */
4082 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4083 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4084 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4085 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4086 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4087 );
4088
4089 /* 14 (LSB), 15, 20, 21 */
4090 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4091 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4092 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4093 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4094 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4095 );
4096
4097 /* Mixed HT20 and HT40 rates */
4098
4099 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4100 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4101 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4102 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4103 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4104 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4105 );
4106
4107 /*
4108 * Write the HT40 power per rate set
4109 * correct PAR difference between HT40 and HT20/LEGACY
4110 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4111 */
4112 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4113 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4114 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4115 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4116 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4117 );
4118
4119 /* 6 (LSB), 7, 12, 13 (MSB) */
4120 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4121 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4122 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4123 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4124 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4125 );
4126
4127 /* 14 (LSB), 15, 20, 21 */
4128 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4129 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4130 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4131 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4132 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4133 );
4134
4135 return 0;
4136 #undef POW_SM
4137 }
4138
4139 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4140 u8 *targetPowerValT2)
4141 {
4142 /* XXX: hard code for now, need to get from eeprom struct */
4143 u8 ht40PowerIncForPdadc = 0;
4144 bool is2GHz = false;
4145 unsigned int i = 0;
4146 struct ath_common *common = ath9k_hw_common(ah);
4147
4148 if (freq < 4000)
4149 is2GHz = true;
4150
4151 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4152 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4153 is2GHz);
4154 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4155 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4156 is2GHz);
4157 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4158 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4159 is2GHz);
4160 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4161 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4162 is2GHz);
4163 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4164 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4165 freq);
4166 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4167 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4168 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4169 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4170 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4171 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4172 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4173 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4174 is2GHz);
4175 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4176 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4177 freq, is2GHz);
4178 targetPowerValT2[ALL_TARGET_HT20_4] =
4179 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4180 is2GHz);
4181 targetPowerValT2[ALL_TARGET_HT20_5] =
4182 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4183 is2GHz);
4184 targetPowerValT2[ALL_TARGET_HT20_6] =
4185 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4186 is2GHz);
4187 targetPowerValT2[ALL_TARGET_HT20_7] =
4188 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4189 is2GHz);
4190 targetPowerValT2[ALL_TARGET_HT20_12] =
4191 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4192 is2GHz);
4193 targetPowerValT2[ALL_TARGET_HT20_13] =
4194 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4195 is2GHz);
4196 targetPowerValT2[ALL_TARGET_HT20_14] =
4197 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4198 is2GHz);
4199 targetPowerValT2[ALL_TARGET_HT20_15] =
4200 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4201 is2GHz);
4202 targetPowerValT2[ALL_TARGET_HT20_20] =
4203 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4204 is2GHz);
4205 targetPowerValT2[ALL_TARGET_HT20_21] =
4206 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4207 is2GHz);
4208 targetPowerValT2[ALL_TARGET_HT20_22] =
4209 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4210 is2GHz);
4211 targetPowerValT2[ALL_TARGET_HT20_23] =
4212 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4213 is2GHz);
4214 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4215 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4216 is2GHz) + ht40PowerIncForPdadc;
4217 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4218 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4219 freq,
4220 is2GHz) + ht40PowerIncForPdadc;
4221 targetPowerValT2[ALL_TARGET_HT40_4] =
4222 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4223 is2GHz) + ht40PowerIncForPdadc;
4224 targetPowerValT2[ALL_TARGET_HT40_5] =
4225 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4226 is2GHz) + ht40PowerIncForPdadc;
4227 targetPowerValT2[ALL_TARGET_HT40_6] =
4228 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4229 is2GHz) + ht40PowerIncForPdadc;
4230 targetPowerValT2[ALL_TARGET_HT40_7] =
4231 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4232 is2GHz) + ht40PowerIncForPdadc;
4233 targetPowerValT2[ALL_TARGET_HT40_12] =
4234 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4235 is2GHz) + ht40PowerIncForPdadc;
4236 targetPowerValT2[ALL_TARGET_HT40_13] =
4237 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4238 is2GHz) + ht40PowerIncForPdadc;
4239 targetPowerValT2[ALL_TARGET_HT40_14] =
4240 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4241 is2GHz) + ht40PowerIncForPdadc;
4242 targetPowerValT2[ALL_TARGET_HT40_15] =
4243 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4244 is2GHz) + ht40PowerIncForPdadc;
4245 targetPowerValT2[ALL_TARGET_HT40_20] =
4246 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4247 is2GHz) + ht40PowerIncForPdadc;
4248 targetPowerValT2[ALL_TARGET_HT40_21] =
4249 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4250 is2GHz) + ht40PowerIncForPdadc;
4251 targetPowerValT2[ALL_TARGET_HT40_22] =
4252 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4253 is2GHz) + ht40PowerIncForPdadc;
4254 targetPowerValT2[ALL_TARGET_HT40_23] =
4255 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4256 is2GHz) + ht40PowerIncForPdadc;
4257
4258 for (i = 0; i < ar9300RateSize; i++) {
4259 ath_dbg(common, ATH_DBG_EEPROM,
4260 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4261 }
4262 }
4263
4264 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4265 int mode,
4266 int ipier,
4267 int ichain,
4268 int *pfrequency,
4269 int *pcorrection,
4270 int *ptemperature, int *pvoltage)
4271 {
4272 u8 *pCalPier;
4273 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4274 int is2GHz;
4275 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4276 struct ath_common *common = ath9k_hw_common(ah);
4277
4278 if (ichain >= AR9300_MAX_CHAINS) {
4279 ath_dbg(common, ATH_DBG_EEPROM,
4280 "Invalid chain index, must be less than %d\n",
4281 AR9300_MAX_CHAINS);
4282 return -1;
4283 }
4284
4285 if (mode) { /* 5GHz */
4286 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4287 ath_dbg(common, ATH_DBG_EEPROM,
4288 "Invalid 5GHz cal pier index, must be less than %d\n",
4289 AR9300_NUM_5G_CAL_PIERS);
4290 return -1;
4291 }
4292 pCalPier = &(eep->calFreqPier5G[ipier]);
4293 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4294 is2GHz = 0;
4295 } else {
4296 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4297 ath_dbg(common, ATH_DBG_EEPROM,
4298 "Invalid 2GHz cal pier index, must be less than %d\n",
4299 AR9300_NUM_2G_CAL_PIERS);
4300 return -1;
4301 }
4302
4303 pCalPier = &(eep->calFreqPier2G[ipier]);
4304 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4305 is2GHz = 1;
4306 }
4307
4308 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4309 *pcorrection = pCalPierStruct->refPower;
4310 *ptemperature = pCalPierStruct->tempMeas;
4311 *pvoltage = pCalPierStruct->voltMeas;
4312
4313 return 0;
4314 }
4315
4316 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4317 int frequency,
4318 int *correction,
4319 int *voltage, int *temperature)
4320 {
4321 int tempSlope = 0;
4322 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4323 int f[3], t[3];
4324
4325 REG_RMW(ah, AR_PHY_TPC_11_B0,
4326 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4327 AR_PHY_TPC_OLPC_GAIN_DELTA);
4328 if (ah->caps.tx_chainmask & BIT(1))
4329 REG_RMW(ah, AR_PHY_TPC_11_B1,
4330 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4331 AR_PHY_TPC_OLPC_GAIN_DELTA);
4332 if (ah->caps.tx_chainmask & BIT(2))
4333 REG_RMW(ah, AR_PHY_TPC_11_B2,
4334 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4335 AR_PHY_TPC_OLPC_GAIN_DELTA);
4336
4337 /* enable open loop power control on chip */
4338 REG_RMW(ah, AR_PHY_TPC_6_B0,
4339 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4340 AR_PHY_TPC_6_ERROR_EST_MODE);
4341 if (ah->caps.tx_chainmask & BIT(1))
4342 REG_RMW(ah, AR_PHY_TPC_6_B1,
4343 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4344 AR_PHY_TPC_6_ERROR_EST_MODE);
4345 if (ah->caps.tx_chainmask & BIT(2))
4346 REG_RMW(ah, AR_PHY_TPC_6_B2,
4347 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4348 AR_PHY_TPC_6_ERROR_EST_MODE);
4349
4350 /*
4351 * enable temperature compensation
4352 * Need to use register names
4353 */
4354 if (frequency < 4000)
4355 tempSlope = eep->modalHeader2G.tempSlope;
4356 else if (eep->base_ext2.tempSlopeLow != 0) {
4357 t[0] = eep->base_ext2.tempSlopeLow;
4358 f[0] = 5180;
4359 t[1] = eep->modalHeader5G.tempSlope;
4360 f[1] = 5500;
4361 t[2] = eep->base_ext2.tempSlopeHigh;
4362 f[2] = 5785;
4363 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4364 f, t, 3);
4365 } else
4366 tempSlope = eep->modalHeader5G.tempSlope;
4367
4368 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4369 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4370 temperature[0]);
4371
4372 return 0;
4373 }
4374
4375 /* Apply the recorded correction values. */
4376 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4377 {
4378 int ichain, ipier, npier;
4379 int mode;
4380 int lfrequency[AR9300_MAX_CHAINS],
4381 lcorrection[AR9300_MAX_CHAINS],
4382 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4383 int hfrequency[AR9300_MAX_CHAINS],
4384 hcorrection[AR9300_MAX_CHAINS],
4385 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4386 int fdiff;
4387 int correction[AR9300_MAX_CHAINS],
4388 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4389 int pfrequency, pcorrection, ptemperature, pvoltage;
4390 struct ath_common *common = ath9k_hw_common(ah);
4391
4392 mode = (frequency >= 4000);
4393 if (mode)
4394 npier = AR9300_NUM_5G_CAL_PIERS;
4395 else
4396 npier = AR9300_NUM_2G_CAL_PIERS;
4397
4398 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4399 lfrequency[ichain] = 0;
4400 hfrequency[ichain] = 100000;
4401 }
4402 /* identify best lower and higher frequency calibration measurement */
4403 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4404 for (ipier = 0; ipier < npier; ipier++) {
4405 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4406 &pfrequency, &pcorrection,
4407 &ptemperature, &pvoltage)) {
4408 fdiff = frequency - pfrequency;
4409
4410 /*
4411 * this measurement is higher than
4412 * our desired frequency
4413 */
4414 if (fdiff <= 0) {
4415 if (hfrequency[ichain] <= 0 ||
4416 hfrequency[ichain] >= 100000 ||
4417 fdiff >
4418 (frequency - hfrequency[ichain])) {
4419 /*
4420 * new best higher
4421 * frequency measurement
4422 */
4423 hfrequency[ichain] = pfrequency;
4424 hcorrection[ichain] =
4425 pcorrection;
4426 htemperature[ichain] =
4427 ptemperature;
4428 hvoltage[ichain] = pvoltage;
4429 }
4430 }
4431 if (fdiff >= 0) {
4432 if (lfrequency[ichain] <= 0
4433 || fdiff <
4434 (frequency - lfrequency[ichain])) {
4435 /*
4436 * new best lower
4437 * frequency measurement
4438 */
4439 lfrequency[ichain] = pfrequency;
4440 lcorrection[ichain] =
4441 pcorrection;
4442 ltemperature[ichain] =
4443 ptemperature;
4444 lvoltage[ichain] = pvoltage;
4445 }
4446 }
4447 }
4448 }
4449 }
4450
4451 /* interpolate */
4452 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4453 ath_dbg(common, ATH_DBG_EEPROM,
4454 "ch=%d f=%d low=%d %d h=%d %d\n",
4455 ichain, frequency, lfrequency[ichain],
4456 lcorrection[ichain], hfrequency[ichain],
4457 hcorrection[ichain]);
4458 /* they're the same, so just pick one */
4459 if (hfrequency[ichain] == lfrequency[ichain]) {
4460 correction[ichain] = lcorrection[ichain];
4461 voltage[ichain] = lvoltage[ichain];
4462 temperature[ichain] = ltemperature[ichain];
4463 }
4464 /* the low frequency is good */
4465 else if (frequency - lfrequency[ichain] < 1000) {
4466 /* so is the high frequency, interpolate */
4467 if (hfrequency[ichain] - frequency < 1000) {
4468
4469 correction[ichain] = interpolate(frequency,
4470 lfrequency[ichain],
4471 hfrequency[ichain],
4472 lcorrection[ichain],
4473 hcorrection[ichain]);
4474
4475 temperature[ichain] = interpolate(frequency,
4476 lfrequency[ichain],
4477 hfrequency[ichain],
4478 ltemperature[ichain],
4479 htemperature[ichain]);
4480
4481 voltage[ichain] = interpolate(frequency,
4482 lfrequency[ichain],
4483 hfrequency[ichain],
4484 lvoltage[ichain],
4485 hvoltage[ichain]);
4486 }
4487 /* only low is good, use it */
4488 else {
4489 correction[ichain] = lcorrection[ichain];
4490 temperature[ichain] = ltemperature[ichain];
4491 voltage[ichain] = lvoltage[ichain];
4492 }
4493 }
4494 /* only high is good, use it */
4495 else if (hfrequency[ichain] - frequency < 1000) {
4496 correction[ichain] = hcorrection[ichain];
4497 temperature[ichain] = htemperature[ichain];
4498 voltage[ichain] = hvoltage[ichain];
4499 } else { /* nothing is good, presume 0???? */
4500 correction[ichain] = 0;
4501 temperature[ichain] = 0;
4502 voltage[ichain] = 0;
4503 }
4504 }
4505
4506 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4507 temperature);
4508
4509 ath_dbg(common, ATH_DBG_EEPROM,
4510 "for frequency=%d, calibration correction = %d %d %d\n",
4511 frequency, correction[0], correction[1], correction[2]);
4512
4513 return 0;
4514 }
4515
4516 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4517 int idx,
4518 int edge,
4519 bool is2GHz)
4520 {
4521 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4522 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4523
4524 if (is2GHz)
4525 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4526 else
4527 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4528 }
4529
4530 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4531 int idx,
4532 unsigned int edge,
4533 u16 freq,
4534 bool is2GHz)
4535 {
4536 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4537 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4538
4539 u8 *ctl_freqbin = is2GHz ?
4540 &eep->ctl_freqbin_2G[idx][0] :
4541 &eep->ctl_freqbin_5G[idx][0];
4542
4543 if (is2GHz) {
4544 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4545 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4546 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4547 } else {
4548 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4549 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4550 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4551 }
4552
4553 return MAX_RATE_POWER;
4554 }
4555
4556 /*
4557 * Find the maximum conformance test limit for the given channel and CTL info
4558 */
4559 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4560 u16 freq, int idx, bool is2GHz)
4561 {
4562 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4563 u8 *ctl_freqbin = is2GHz ?
4564 &eep->ctl_freqbin_2G[idx][0] :
4565 &eep->ctl_freqbin_5G[idx][0];
4566 u16 num_edges = is2GHz ?
4567 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4568 unsigned int edge;
4569
4570 /* Get the edge power */
4571 for (edge = 0;
4572 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4573 edge++) {
4574 /*
4575 * If there's an exact channel match or an inband flag set
4576 * on the lower channel use the given rdEdgePower
4577 */
4578 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4579 twiceMaxEdgePower =
4580 ar9003_hw_get_direct_edge_power(eep, idx,
4581 edge, is2GHz);
4582 break;
4583 } else if ((edge > 0) &&
4584 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4585 is2GHz))) {
4586 twiceMaxEdgePower =
4587 ar9003_hw_get_indirect_edge_power(eep, idx,
4588 edge, freq,
4589 is2GHz);
4590 /*
4591 * Leave loop - no more affecting edges possible in
4592 * this monotonic increasing list
4593 */
4594 break;
4595 }
4596 }
4597 return twiceMaxEdgePower;
4598 }
4599
4600 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4601 struct ath9k_channel *chan,
4602 u8 *pPwrArray, u16 cfgCtl,
4603 u8 twiceAntennaReduction,
4604 u8 twiceMaxRegulatoryPower,
4605 u16 powerLimit)
4606 {
4607 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4608 struct ath_common *common = ath9k_hw_common(ah);
4609 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4610 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4611 static const u16 tpScaleReductionTable[5] = {
4612 0, 3, 6, 9, MAX_RATE_POWER
4613 };
4614 int i;
4615 int16_t twiceLargestAntenna;
4616 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4617 static const u16 ctlModesFor11a[] = {
4618 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4619 };
4620 static const u16 ctlModesFor11g[] = {
4621 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4622 CTL_11G_EXT, CTL_2GHT40
4623 };
4624 u16 numCtlModes;
4625 const u16 *pCtlMode;
4626 u16 ctlMode, freq;
4627 struct chan_centers centers;
4628 u8 *ctlIndex;
4629 u8 ctlNum;
4630 u16 twiceMinEdgePower;
4631 bool is2ghz = IS_CHAN_2GHZ(chan);
4632
4633 ath9k_hw_get_channel_centers(ah, chan, &centers);
4634
4635 /* Compute TxPower reduction due to Antenna Gain */
4636 if (is2ghz)
4637 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4638 else
4639 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4640
4641 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4642 twiceLargestAntenna, 0);
4643
4644 /*
4645 * scaledPower is the minimum of the user input power level
4646 * and the regulatory allowed power level
4647 */
4648 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4649
4650 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4651 maxRegAllowedPower -=
4652 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4653 }
4654
4655 scaledPower = min(powerLimit, maxRegAllowedPower);
4656
4657 /*
4658 * Reduce scaled Power by number of chains active to get
4659 * to per chain tx power level
4660 */
4661 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4662 case 1:
4663 break;
4664 case 2:
4665 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4666 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4667 else
4668 scaledPower = 0;
4669 break;
4670 case 3:
4671 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4672 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4673 else
4674 scaledPower = 0;
4675 break;
4676 }
4677
4678 scaledPower = max((u16)0, scaledPower);
4679
4680 /*
4681 * Get target powers from EEPROM - our baseline for TX Power
4682 */
4683 if (is2ghz) {
4684 /* Setup for CTL modes */
4685 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4686 numCtlModes =
4687 ARRAY_SIZE(ctlModesFor11g) -
4688 SUB_NUM_CTL_MODES_AT_2G_40;
4689 pCtlMode = ctlModesFor11g;
4690 if (IS_CHAN_HT40(chan))
4691 /* All 2G CTL's */
4692 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4693 } else {
4694 /* Setup for CTL modes */
4695 /* CTL_11A, CTL_5GHT20 */
4696 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4697 SUB_NUM_CTL_MODES_AT_5G_40;
4698 pCtlMode = ctlModesFor11a;
4699 if (IS_CHAN_HT40(chan))
4700 /* All 5G CTL's */
4701 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4702 }
4703
4704 /*
4705 * For MIMO, need to apply regulatory caps individually across
4706 * dynamically running modes: CCK, OFDM, HT20, HT40
4707 *
4708 * The outer loop walks through each possible applicable runtime mode.
4709 * The inner loop walks through each ctlIndex entry in EEPROM.
4710 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4711 */
4712 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4713 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4714 (pCtlMode[ctlMode] == CTL_2GHT40);
4715 if (isHt40CtlMode)
4716 freq = centers.synth_center;
4717 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4718 freq = centers.ext_center;
4719 else
4720 freq = centers.ctl_center;
4721
4722 ath_dbg(common, ATH_DBG_REGULATORY,
4723 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4724 ctlMode, numCtlModes, isHt40CtlMode,
4725 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4726
4727 /* walk through each CTL index stored in EEPROM */
4728 if (is2ghz) {
4729 ctlIndex = pEepData->ctlIndex_2G;
4730 ctlNum = AR9300_NUM_CTLS_2G;
4731 } else {
4732 ctlIndex = pEepData->ctlIndex_5G;
4733 ctlNum = AR9300_NUM_CTLS_5G;
4734 }
4735
4736 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4737 ath_dbg(common, ATH_DBG_REGULATORY,
4738 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4739 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4740 chan->channel);
4741
4742 /*
4743 * compare test group from regulatory
4744 * channel list with test mode from pCtlMode
4745 * list
4746 */
4747 if ((((cfgCtl & ~CTL_MODE_M) |
4748 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4749 ctlIndex[i]) ||
4750 (((cfgCtl & ~CTL_MODE_M) |
4751 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4752 ((ctlIndex[i] & CTL_MODE_M) |
4753 SD_NO_CTL))) {
4754 twiceMinEdgePower =
4755 ar9003_hw_get_max_edge_power(pEepData,
4756 freq, i,
4757 is2ghz);
4758
4759 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4760 /*
4761 * Find the minimum of all CTL
4762 * edge powers that apply to
4763 * this channel
4764 */
4765 twiceMaxEdgePower =
4766 min(twiceMaxEdgePower,
4767 twiceMinEdgePower);
4768 else {
4769 /* specific */
4770 twiceMaxEdgePower =
4771 twiceMinEdgePower;
4772 break;
4773 }
4774 }
4775 }
4776
4777 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4778
4779 ath_dbg(common, ATH_DBG_REGULATORY,
4780 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4781 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4782 scaledPower, minCtlPower);
4783
4784 /* Apply ctl mode to correct target power set */
4785 switch (pCtlMode[ctlMode]) {
4786 case CTL_11B:
4787 for (i = ALL_TARGET_LEGACY_1L_5L;
4788 i <= ALL_TARGET_LEGACY_11S; i++)
4789 pPwrArray[i] =
4790 (u8)min((u16)pPwrArray[i],
4791 minCtlPower);
4792 break;
4793 case CTL_11A:
4794 case CTL_11G:
4795 for (i = ALL_TARGET_LEGACY_6_24;
4796 i <= ALL_TARGET_LEGACY_54; i++)
4797 pPwrArray[i] =
4798 (u8)min((u16)pPwrArray[i],
4799 minCtlPower);
4800 break;
4801 case CTL_5GHT20:
4802 case CTL_2GHT20:
4803 for (i = ALL_TARGET_HT20_0_8_16;
4804 i <= ALL_TARGET_HT20_21; i++)
4805 pPwrArray[i] =
4806 (u8)min((u16)pPwrArray[i],
4807 minCtlPower);
4808 pPwrArray[ALL_TARGET_HT20_22] =
4809 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4810 minCtlPower);
4811 pPwrArray[ALL_TARGET_HT20_23] =
4812 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4813 minCtlPower);
4814 break;
4815 case CTL_5GHT40:
4816 case CTL_2GHT40:
4817 for (i = ALL_TARGET_HT40_0_8_16;
4818 i <= ALL_TARGET_HT40_23; i++)
4819 pPwrArray[i] =
4820 (u8)min((u16)pPwrArray[i],
4821 minCtlPower);
4822 break;
4823 default:
4824 break;
4825 }
4826 } /* end ctl mode checking */
4827 }
4828
4829 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4830 {
4831 u8 mod_idx = mcs_idx % 8;
4832
4833 if (mod_idx <= 3)
4834 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4835 else
4836 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4837 }
4838
4839 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4840 struct ath9k_channel *chan, u16 cfgCtl,
4841 u8 twiceAntennaReduction,
4842 u8 twiceMaxRegulatoryPower,
4843 u8 powerLimit, bool test)
4844 {
4845 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4846 struct ath_common *common = ath9k_hw_common(ah);
4847 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4848 struct ar9300_modal_eep_header *modal_hdr;
4849 u8 targetPowerValT2[ar9300RateSize];
4850 u8 target_power_val_t2_eep[ar9300RateSize];
4851 unsigned int i = 0, paprd_scale_factor = 0;
4852 u8 pwr_idx, min_pwridx = 0;
4853
4854 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4855
4856 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4857 if (IS_CHAN_2GHZ(chan))
4858 modal_hdr = &eep->modalHeader2G;
4859 else
4860 modal_hdr = &eep->modalHeader5G;
4861
4862 ah->paprd_ratemask =
4863 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
4864 AR9300_PAPRD_RATE_MASK;
4865
4866 ah->paprd_ratemask_ht40 =
4867 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
4868 AR9300_PAPRD_RATE_MASK;
4869
4870 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4871 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4872 ALL_TARGET_HT20_0_8_16;
4873
4874 if (!ah->paprd_table_write_done) {
4875 memcpy(target_power_val_t2_eep, targetPowerValT2,
4876 sizeof(targetPowerValT2));
4877 for (i = 0; i < 24; i++) {
4878 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4879 if (ah->paprd_ratemask & (1 << i)) {
4880 if (targetPowerValT2[pwr_idx] &&
4881 targetPowerValT2[pwr_idx] ==
4882 target_power_val_t2_eep[pwr_idx])
4883 targetPowerValT2[pwr_idx] -=
4884 paprd_scale_factor;
4885 }
4886 }
4887 }
4888 memcpy(target_power_val_t2_eep, targetPowerValT2,
4889 sizeof(targetPowerValT2));
4890 }
4891
4892 ar9003_hw_set_power_per_rate_table(ah, chan,
4893 targetPowerValT2, cfgCtl,
4894 twiceAntennaReduction,
4895 twiceMaxRegulatoryPower,
4896 powerLimit);
4897
4898 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4899 for (i = 0; i < ar9300RateSize; i++) {
4900 if ((ah->paprd_ratemask & (1 << i)) &&
4901 (abs(targetPowerValT2[i] -
4902 target_power_val_t2_eep[i]) >
4903 paprd_scale_factor)) {
4904 ah->paprd_ratemask &= ~(1 << i);
4905 ath_dbg(common, ATH_DBG_EEPROM,
4906 "paprd disabled for mcs %d\n", i);
4907 }
4908 }
4909 }
4910
4911 regulatory->max_power_level = 0;
4912 for (i = 0; i < ar9300RateSize; i++) {
4913 if (targetPowerValT2[i] > regulatory->max_power_level)
4914 regulatory->max_power_level = targetPowerValT2[i];
4915 }
4916
4917 if (test)
4918 return;
4919
4920 for (i = 0; i < ar9300RateSize; i++) {
4921 ath_dbg(common, ATH_DBG_EEPROM,
4922 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4923 }
4924
4925 /*
4926 * This is the TX power we send back to driver core,
4927 * and it can use to pass to userspace to display our
4928 * currently configured TX power setting.
4929 *
4930 * Since power is rate dependent, use one of the indices
4931 * from the AR9300_Rates enum to select an entry from
4932 * targetPowerValT2[] to report. Currently returns the
4933 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4934 * as CCK power is less interesting (?).
4935 */
4936 i = ALL_TARGET_LEGACY_6_24; /* legacy */
4937 if (IS_CHAN_HT40(chan))
4938 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4939 else if (IS_CHAN_HT20(chan))
4940 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4941
4942 ah->txpower_limit = targetPowerValT2[i];
4943 regulatory->max_power_level = targetPowerValT2[i];
4944
4945 /* Write target power array to registers */
4946 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4947 ar9003_hw_calibration_apply(ah, chan->channel);
4948
4949 if (IS_CHAN_2GHZ(chan)) {
4950 if (IS_CHAN_HT40(chan))
4951 i = ALL_TARGET_HT40_0_8_16;
4952 else
4953 i = ALL_TARGET_HT20_0_8_16;
4954 } else {
4955 if (IS_CHAN_HT40(chan))
4956 i = ALL_TARGET_HT40_7;
4957 else
4958 i = ALL_TARGET_HT20_7;
4959 }
4960 ah->paprd_target_power = targetPowerValT2[i];
4961 }
4962
4963 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4964 u16 i, bool is2GHz)
4965 {
4966 return AR_NO_SPUR;
4967 }
4968
4969 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4970 {
4971 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4972
4973 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4974 }
4975
4976 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4977 {
4978 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4979
4980 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4981 }
4982
4983 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
4984 {
4985 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4986
4987 if (is_2ghz)
4988 return eep->modalHeader2G.spurChans;
4989 else
4990 return eep->modalHeader5G.spurChans;
4991 }
4992
4993 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
4994 struct ath9k_channel *chan)
4995 {
4996 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4997
4998 if (IS_CHAN_2GHZ(chan))
4999 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5000 AR9300_PAPRD_SCALE_1);
5001 else {
5002 if (chan->channel >= 5700)
5003 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5004 AR9300_PAPRD_SCALE_1);
5005 else if (chan->channel >= 5400)
5006 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5007 AR9300_PAPRD_SCALE_2);
5008 else
5009 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5010 AR9300_PAPRD_SCALE_1);
5011 }
5012 }
5013
5014 const struct eeprom_ops eep_ar9300_ops = {
5015 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5016 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5017 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5018 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5019 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5020 .set_board_values = ath9k_hw_ar9300_set_board_values,
5021 .set_addac = ath9k_hw_ar9300_set_addac,
5022 .set_txpower = ath9k_hw_ar9300_set_txpower,
5023 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5024 };
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