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ath9k: Initialize QCA953x INI arrays
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29 /*
30 * register values to turn OFDM weak signal detection OFF
31 */
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
42
43 /**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69 {
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
80 if (ah->is_clk_25mhz)
81 div = 75;
82 else
83 div = 120;
84
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
89 /*
90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
94 */
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
98 } else if (AR_SREV_9340(ah)) {
99 if (ah->is_clk_25mhz) {
100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
103 } else {
104 channelSel = CHANSEL_2G(freq) >> 1;
105 }
106 } else if (AR_SREV_9550(ah)) {
107 if (ah->is_clk_25mhz)
108 div = 75;
109 else
110 div = 120;
111
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
115 } else {
116 channelSel = CHANSEL_2G(freq);
117 }
118 /* Set to 2G mode */
119 bMode = 1;
120 } else {
121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
122 ah->is_clk_25mhz) {
123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
125 channelSel = (channelSel << 17) | chan_frac;
126 } else {
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
129 channelSel >>= 1;
130 }
131 /* Set to 5G mode */
132 bMode = 0;
133 }
134
135 /* Enable fractional mode for all channels */
136 fracMode = 1;
137 aModeRefSel = 0;
138 loadSynthChannel = 0;
139
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
142
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
146
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
151
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
157
158 ah->curchan = chan;
159
160 return 0;
161 }
162
163 /**
164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
165 * @ah: atheros hardware structure
166 * @chan:
167 *
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
170 *
171 * Spur mitigation for MRC CCK
172 */
173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
175 {
176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
177 int cur_bb_spur, negative = 0, cck_spur_freq;
178 int i;
179 int range, max_spur_cnts, synth_freq;
180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
181
182 /*
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
185 */
186
187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
188 AR_SREV_9550(ah)) {
189 if (spur_fbin_ptr[0] == 0) /* No spur */
190 return;
191 max_spur_cnts = 5;
192 if (IS_CHAN_HT40(chan)) {
193 range = 19;
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
197 else
198 synth_freq = chan->channel - 10;
199 } else {
200 range = 10;
201 synth_freq = chan->channel;
202 }
203 } else {
204 range = AR_SREV_9462(ah) ? 5 : 10;
205 max_spur_cnts = 4;
206 synth_freq = chan->channel;
207 }
208
209 for (i = 0; i < max_spur_cnts; i++) {
210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
211 continue;
212
213 negative = 0;
214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
215 AR_SREV_9550(ah))
216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
217 IS_CHAN_2GHZ(chan));
218 else
219 cur_bb_spur = spur_freq[i];
220
221 cur_bb_spur -= synth_freq;
222 if (cur_bb_spur < 0) {
223 negative = 1;
224 cur_bb_spur = -cur_bb_spur;
225 }
226 if (cur_bb_spur < range) {
227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
228
229 if (negative == 1)
230 cck_spur_freq = -cck_spur_freq;
231
232 cck_spur_freq = cck_spur_freq & 0xfffff;
233
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
240 0x2);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
243 0x1);
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
246 cck_spur_freq);
247
248 return;
249 }
250 }
251
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
258 }
259
260 /* Clean all spur register fields */
261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
262 {
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
281
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
302 }
303
304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
305 int freq_offset,
306 int spur_freq_sd,
307 int spur_delta_phase,
308 int spur_subchannel_sd,
309 int range,
310 int synth_freq)
311 {
312 int mask_index = 0;
313
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
325
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
329
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
336
337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
342
343 mask_index = (freq_offset << 4) / 5;
344 if (mask_index < 0)
345 mask_index = mask_index - 1;
346
347 mask_index = mask_index & 0x7f;
348
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
369 }
370
371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
372 int freq_offset)
373 {
374 int mask_index = 0;
375
376 mask_index = (freq_offset << 4) / 5;
377 if (mask_index < 0)
378 mask_index = mask_index - 1;
379
380 mask_index = mask_index & 0x7f;
381
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
384 mask_index);
385
386 /* A == B */
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
389 mask_index);
390
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
393 mask_index);
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
398
399 /* A == B */
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
402 }
403
404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
406 int freq_offset,
407 int range,
408 int synth_freq)
409 {
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
413
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
419 else
420 spur_subchannel_sd = 0;
421
422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
423
424 } else {
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
428 else
429 spur_subchannel_sd = 1;
430
431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
432
433 }
434
435 spur_delta_phase = (freq_offset << 17) / 5;
436
437 } else {
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
441 }
442
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
445
446 ar9003_hw_spur_ofdm(ah,
447 freq_offset,
448 spur_freq_sd,
449 spur_delta_phase,
450 spur_subchannel_sd,
451 range, synth_freq);
452 }
453
454 /* Spur mitigation for OFDM */
455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
457 {
458 int synth_freq;
459 int range = 10;
460 int freq_offset = 0;
461 int mode;
462 u8* spurChansPtr;
463 unsigned int i;
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
465
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
468 mode = 0;
469 }
470 else {
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
472 mode = 1;
473 }
474
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
477
478 if (IS_CHAN_HT40(chan)) {
479 range = 19;
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
483 else
484 synth_freq = chan->channel + 10;
485 } else {
486 range = 10;
487 synth_freq = chan->channel;
488 }
489
490 ar9003_hw_spur_ofdm_clear(ah);
491
492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
495 if (abs(freq_offset) < range) {
496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
497 range, synth_freq);
498
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
501 mode);
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
505 }
506
507 break;
508 }
509 }
510 }
511
512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
514 {
515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
518 }
519
520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
521 struct ath9k_channel *chan)
522 {
523 u32 pll;
524
525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
526
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
531
532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
533
534 return pll;
535 }
536
537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539 {
540 u32 phymode;
541 u32 enableDacFifo = 0;
542
543 enableDacFifo =
544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
545
546 /* Enable 11n HT, 20 MHz */
547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
549
550 /* Configure baseband for dynamic 20/40 operation */
551 if (IS_CHAN_HT40(chan)) {
552 phymode |= AR_PHY_GC_DYN2040_EN;
553 /* Configure control (primary) channel at +-10MHz */
554 if (IS_CHAN_HT40PLUS(chan))
555 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
556
557 }
558
559 /* make sure we preserve INI settings */
560 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
561 /* turn off Green Field detection for STA for now */
562 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
563
564 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
565
566 /* Configure MAC for 20/40 operation */
567 ath9k_hw_set11nmac2040(ah, chan);
568
569 /* global transmit timeout (25 TUs default)*/
570 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
571 /* carrier sense timeout */
572 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
573 }
574
575 static void ar9003_hw_init_bb(struct ath_hw *ah,
576 struct ath9k_channel *chan)
577 {
578 u32 synthDelay;
579
580 /*
581 * Wait for the frequency synth to settle (synth goes on
582 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
583 * Value is in 100ns increments.
584 */
585 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
586
587 /* Activate the PHY (includes baseband activate + synthesizer on) */
588 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
589 ath9k_hw_synth_delay(ah, chan, synthDelay);
590 }
591
592 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
593 {
594 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
595 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
596 AR_PHY_SWAP_ALT_CHAIN);
597
598 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
599 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
600
601 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
602 tx = 3;
603
604 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
605 }
606
607 /*
608 * Override INI values with chip specific configuration.
609 */
610 static void ar9003_hw_override_ini(struct ath_hw *ah)
611 {
612 u32 val;
613
614 /*
615 * Set the RX_ABORT and RX_DIS and clear it only after
616 * RXE is set for MAC. This prevents frames with
617 * corrupted descriptor status.
618 */
619 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
620
621 /*
622 * For AR9280 and above, there is a new feature that allows
623 * Multicast search based on both MAC Address and Key ID. By default,
624 * this feature is enabled. But since the driver is not using this
625 * feature, we switch it off; otherwise multicast search based on
626 * MAC addr only will fail.
627 */
628 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
629 val |= AR_AGG_WEP_ENABLE_FIX |
630 AR_AGG_WEP_ENABLE |
631 AR_PCU_MISC_MODE2_CFP_IGNORE;
632 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
633
634 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
635 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
636 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
637
638 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
639 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
640 ah->enabled_cals |= TX_IQ_CAL;
641 else
642 ah->enabled_cals &= ~TX_IQ_CAL;
643
644 }
645
646 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
647 ah->enabled_cals |= TX_CL_CAL;
648 else
649 ah->enabled_cals &= ~TX_CL_CAL;
650 }
651
652 static void ar9003_hw_prog_ini(struct ath_hw *ah,
653 struct ar5416IniArray *iniArr,
654 int column)
655 {
656 unsigned int i, regWrites = 0;
657
658 /* New INI format: Array may be undefined (pre, core, post arrays) */
659 if (!iniArr->ia_array)
660 return;
661
662 /*
663 * New INI format: Pre, core, and post arrays for a given subsystem
664 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
665 * the array is non-modal and force the column to 1.
666 */
667 if (column >= iniArr->ia_columns)
668 column = 1;
669
670 for (i = 0; i < iniArr->ia_rows; i++) {
671 u32 reg = INI_RA(iniArr, i, 0);
672 u32 val = INI_RA(iniArr, i, column);
673
674 REG_WRITE(ah, reg, val);
675
676 DO_DELAY(regWrites);
677 }
678 }
679
680 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
681 struct ath9k_channel *chan)
682 {
683 int ret;
684
685 if (IS_CHAN_2GHZ(chan)) {
686 if (IS_CHAN_HT40(chan))
687 return 7;
688 else
689 return 8;
690 }
691
692 if (chan->channel <= 5350)
693 ret = 1;
694 else if ((chan->channel > 5350) && (chan->channel <= 5600))
695 ret = 3;
696 else
697 ret = 5;
698
699 if (IS_CHAN_HT40(chan))
700 ret++;
701
702 return ret;
703 }
704
705 static void ar9003_doubler_fix(struct ath_hw *ah)
706 {
707 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
708 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
709 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
710 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
711 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
712 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
713 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
714 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
715 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
716 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
717
718 udelay(200);
719
720 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
721 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
722 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
723 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
724 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
725 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
726
727 udelay(1);
728
729 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
730 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
731 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
732 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
733 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
734 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
735
736 udelay(200);
737
738 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
739 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
740
741 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
742 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
743 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
744 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
745 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
746 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
747 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
748 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
749 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
750 }
751 }
752
753 static int ar9003_hw_process_ini(struct ath_hw *ah,
754 struct ath9k_channel *chan)
755 {
756 unsigned int regWrites = 0, i;
757 u32 modesIndex;
758
759 if (IS_CHAN_5GHZ(chan))
760 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
761 else
762 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
763
764 /*
765 * SOC, MAC, BB, RADIO initvals.
766 */
767 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
768 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
769 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
770 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
771 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
772 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
773 ar9003_hw_prog_ini(ah,
774 &ah->ini_radio_post_sys2ant,
775 modesIndex);
776 }
777
778 ar9003_doubler_fix(ah);
779
780 /*
781 * RXGAIN initvals.
782 */
783 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
784
785 if (AR_SREV_9462_20_OR_LATER(ah)) {
786 /*
787 * CUS217 mix LNA mode.
788 */
789 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
790 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
791 1, regWrites);
792 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
793 modesIndex, regWrites);
794 }
795
796 /*
797 * 5G-XLNA
798 */
799 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
800 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
801 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
802 modesIndex, regWrites);
803 }
804 }
805
806 if (AR_SREV_9550(ah))
807 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
808 regWrites);
809
810 /*
811 * TXGAIN initvals.
812 */
813 if (AR_SREV_9550(ah)) {
814 int modes_txgain_index;
815
816 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
817 if (modes_txgain_index < 0)
818 return -EINVAL;
819
820 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
821 regWrites);
822 } else {
823 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
824 }
825
826 /*
827 * For 5GHz channels requiring Fast Clock, apply
828 * different modal values.
829 */
830 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
831 REG_WRITE_ARRAY(&ah->iniModesFastClock,
832 modesIndex, regWrites);
833
834 /*
835 * Clock frequency initvals.
836 */
837 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
838
839 /*
840 * JAPAN regulatory.
841 */
842 if (chan->channel == 2484)
843 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
844
845 ah->modes_index = modesIndex;
846 ar9003_hw_override_ini(ah);
847 ar9003_hw_set_channel_regs(ah, chan);
848 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
849 ath9k_hw_apply_txpower(ah, chan, false);
850
851 return 0;
852 }
853
854 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
855 struct ath9k_channel *chan)
856 {
857 u32 rfMode = 0;
858
859 if (chan == NULL)
860 return;
861
862 if (IS_CHAN_2GHZ(chan))
863 rfMode |= AR_PHY_MODE_DYNAMIC;
864 else
865 rfMode |= AR_PHY_MODE_OFDM;
866
867 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
868 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
869 if (IS_CHAN_QUARTER_RATE(chan))
870 rfMode |= AR_PHY_MODE_QUARTER;
871 if (IS_CHAN_HALF_RATE(chan))
872 rfMode |= AR_PHY_MODE_HALF;
873
874 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
875 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
876 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
877
878 REG_WRITE(ah, AR_PHY_MODE, rfMode);
879 }
880
881 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
882 {
883 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
884 }
885
886 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
887 struct ath9k_channel *chan)
888 {
889 u32 coef_scaled, ds_coef_exp, ds_coef_man;
890 u32 clockMhzScaled = 0x64000000;
891 struct chan_centers centers;
892
893 /*
894 * half and quarter rate can divide the scaled clock by 2 or 4
895 * scale for selected channel bandwidth
896 */
897 if (IS_CHAN_HALF_RATE(chan))
898 clockMhzScaled = clockMhzScaled >> 1;
899 else if (IS_CHAN_QUARTER_RATE(chan))
900 clockMhzScaled = clockMhzScaled >> 2;
901
902 /*
903 * ALGO -> coef = 1e8/fcarrier*fclock/40;
904 * scaled coef to provide precision for this floating calculation
905 */
906 ath9k_hw_get_channel_centers(ah, chan, &centers);
907 coef_scaled = clockMhzScaled / centers.synth_center;
908
909 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
910 &ds_coef_exp);
911
912 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
913 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
914 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
915 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
916
917 /*
918 * For Short GI,
919 * scaled coeff is 9/10 that of normal coeff
920 */
921 coef_scaled = (9 * coef_scaled) / 10;
922
923 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
924 &ds_coef_exp);
925
926 /* for short gi */
927 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
928 AR_PHY_SGI_DSC_MAN, ds_coef_man);
929 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
930 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
931 }
932
933 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
934 {
935 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
936 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
937 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
938 }
939
940 /*
941 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
942 * Read the phy active delay register. Value is in 100ns increments.
943 */
944 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
945 {
946 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
947
948 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
949
950 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
951 }
952
953 static bool ar9003_hw_ani_control(struct ath_hw *ah,
954 enum ath9k_ani_cmd cmd, int param)
955 {
956 struct ath_common *common = ath9k_hw_common(ah);
957 struct ath9k_channel *chan = ah->curchan;
958 struct ar5416AniState *aniState = &ah->ani;
959 int m1ThreshLow, m2ThreshLow;
960 int m1Thresh, m2Thresh;
961 int m2CountThr, m2CountThrLow;
962 int m1ThreshLowExt, m2ThreshLowExt;
963 int m1ThreshExt, m2ThreshExt;
964 s32 value, value2;
965
966 switch (cmd & ah->ani_function) {
967 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
968 /*
969 * on == 1 means ofdm weak signal detection is ON
970 * on == 1 is the default, for less noise immunity
971 *
972 * on == 0 means ofdm weak signal detection is OFF
973 * on == 0 means more noise imm
974 */
975 u32 on = param ? 1 : 0;
976
977 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
978 goto skip_ws_det;
979
980 m1ThreshLow = on ?
981 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
982 m2ThreshLow = on ?
983 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
984 m1Thresh = on ?
985 aniState->iniDef.m1Thresh : m1Thresh_off;
986 m2Thresh = on ?
987 aniState->iniDef.m2Thresh : m2Thresh_off;
988 m2CountThr = on ?
989 aniState->iniDef.m2CountThr : m2CountThr_off;
990 m2CountThrLow = on ?
991 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
992 m1ThreshLowExt = on ?
993 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
994 m2ThreshLowExt = on ?
995 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
996 m1ThreshExt = on ?
997 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
998 m2ThreshExt = on ?
999 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1000
1001 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1002 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1003 m1ThreshLow);
1004 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1005 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1006 m2ThreshLow);
1007 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1008 AR_PHY_SFCORR_M1_THRESH,
1009 m1Thresh);
1010 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1011 AR_PHY_SFCORR_M2_THRESH,
1012 m2Thresh);
1013 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1014 AR_PHY_SFCORR_M2COUNT_THR,
1015 m2CountThr);
1016 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1017 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1018 m2CountThrLow);
1019 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1020 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1021 m1ThreshLowExt);
1022 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1023 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1024 m2ThreshLowExt);
1025 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1026 AR_PHY_SFCORR_EXT_M1_THRESH,
1027 m1ThreshExt);
1028 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1029 AR_PHY_SFCORR_EXT_M2_THRESH,
1030 m2ThreshExt);
1031 skip_ws_det:
1032 if (on)
1033 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1034 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1035 else
1036 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1037 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1038
1039 if (on != aniState->ofdmWeakSigDetect) {
1040 ath_dbg(common, ANI,
1041 "** ch %d: ofdm weak signal: %s=>%s\n",
1042 chan->channel,
1043 aniState->ofdmWeakSigDetect ?
1044 "on" : "off",
1045 on ? "on" : "off");
1046 if (on)
1047 ah->stats.ast_ani_ofdmon++;
1048 else
1049 ah->stats.ast_ani_ofdmoff++;
1050 aniState->ofdmWeakSigDetect = on;
1051 }
1052 break;
1053 }
1054 case ATH9K_ANI_FIRSTEP_LEVEL:{
1055 u32 level = param;
1056
1057 if (level >= ARRAY_SIZE(firstep_table)) {
1058 ath_dbg(common, ANI,
1059 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1060 level, ARRAY_SIZE(firstep_table));
1061 return false;
1062 }
1063
1064 /*
1065 * make register setting relative to default
1066 * from INI file & cap value
1067 */
1068 value = firstep_table[level] -
1069 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1070 aniState->iniDef.firstep;
1071 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1072 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1073 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1074 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1075 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1076 AR_PHY_FIND_SIG_FIRSTEP,
1077 value);
1078 /*
1079 * we need to set first step low register too
1080 * make register setting relative to default
1081 * from INI file & cap value
1082 */
1083 value2 = firstep_table[level] -
1084 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1085 aniState->iniDef.firstepLow;
1086 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1087 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1088 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1089 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1090
1091 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1092 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1093
1094 if (level != aniState->firstepLevel) {
1095 ath_dbg(common, ANI,
1096 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1097 chan->channel,
1098 aniState->firstepLevel,
1099 level,
1100 ATH9K_ANI_FIRSTEP_LVL,
1101 value,
1102 aniState->iniDef.firstep);
1103 ath_dbg(common, ANI,
1104 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1105 chan->channel,
1106 aniState->firstepLevel,
1107 level,
1108 ATH9K_ANI_FIRSTEP_LVL,
1109 value2,
1110 aniState->iniDef.firstepLow);
1111 if (level > aniState->firstepLevel)
1112 ah->stats.ast_ani_stepup++;
1113 else if (level < aniState->firstepLevel)
1114 ah->stats.ast_ani_stepdown++;
1115 aniState->firstepLevel = level;
1116 }
1117 break;
1118 }
1119 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1120 u32 level = param;
1121
1122 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1123 ath_dbg(common, ANI,
1124 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1125 level, ARRAY_SIZE(cycpwrThr1_table));
1126 return false;
1127 }
1128 /*
1129 * make register setting relative to default
1130 * from INI file & cap value
1131 */
1132 value = cycpwrThr1_table[level] -
1133 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1134 aniState->iniDef.cycpwrThr1;
1135 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1136 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1137 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1138 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1139 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1140 AR_PHY_TIMING5_CYCPWR_THR1,
1141 value);
1142
1143 /*
1144 * set AR_PHY_EXT_CCA for extension channel
1145 * make register setting relative to default
1146 * from INI file & cap value
1147 */
1148 value2 = cycpwrThr1_table[level] -
1149 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1150 aniState->iniDef.cycpwrThr1Ext;
1151 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1152 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1153 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1154 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1155 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1156 AR_PHY_EXT_CYCPWR_THR1, value2);
1157
1158 if (level != aniState->spurImmunityLevel) {
1159 ath_dbg(common, ANI,
1160 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1161 chan->channel,
1162 aniState->spurImmunityLevel,
1163 level,
1164 ATH9K_ANI_SPUR_IMMUNE_LVL,
1165 value,
1166 aniState->iniDef.cycpwrThr1);
1167 ath_dbg(common, ANI,
1168 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1169 chan->channel,
1170 aniState->spurImmunityLevel,
1171 level,
1172 ATH9K_ANI_SPUR_IMMUNE_LVL,
1173 value2,
1174 aniState->iniDef.cycpwrThr1Ext);
1175 if (level > aniState->spurImmunityLevel)
1176 ah->stats.ast_ani_spurup++;
1177 else if (level < aniState->spurImmunityLevel)
1178 ah->stats.ast_ani_spurdown++;
1179 aniState->spurImmunityLevel = level;
1180 }
1181 break;
1182 }
1183 case ATH9K_ANI_MRC_CCK:{
1184 /*
1185 * is_on == 1 means MRC CCK ON (default, less noise imm)
1186 * is_on == 0 means MRC CCK is OFF (more noise imm)
1187 */
1188 bool is_on = param ? 1 : 0;
1189
1190 if (ah->caps.rx_chainmask == 1)
1191 break;
1192
1193 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1194 AR_PHY_MRC_CCK_ENABLE, is_on);
1195 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1196 AR_PHY_MRC_CCK_MUX_REG, is_on);
1197 if (is_on != aniState->mrcCCK) {
1198 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1199 chan->channel,
1200 aniState->mrcCCK ? "on" : "off",
1201 is_on ? "on" : "off");
1202 if (is_on)
1203 ah->stats.ast_ani_ccklow++;
1204 else
1205 ah->stats.ast_ani_cckhigh++;
1206 aniState->mrcCCK = is_on;
1207 }
1208 break;
1209 }
1210 default:
1211 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1212 return false;
1213 }
1214
1215 ath_dbg(common, ANI,
1216 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1217 aniState->spurImmunityLevel,
1218 aniState->ofdmWeakSigDetect ? "on" : "off",
1219 aniState->firstepLevel,
1220 aniState->mrcCCK ? "on" : "off",
1221 aniState->listenTime,
1222 aniState->ofdmPhyErrCount,
1223 aniState->cckPhyErrCount);
1224 return true;
1225 }
1226
1227 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1228 int16_t nfarray[NUM_NF_READINGS])
1229 {
1230 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1231 #define AR_PHY_CH_MINCCA_PWR_S 20
1232 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1233 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1234
1235 int16_t nf;
1236 int i;
1237
1238 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1239 if (ah->rxchainmask & BIT(i)) {
1240 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1241 AR_PHY_CH_MINCCA_PWR);
1242 nfarray[i] = sign_extend32(nf, 8);
1243
1244 if (IS_CHAN_HT40(ah->curchan)) {
1245 u8 ext_idx = AR9300_MAX_CHAINS + i;
1246
1247 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1248 AR_PHY_CH_EXT_MINCCA_PWR);
1249 nfarray[ext_idx] = sign_extend32(nf, 8);
1250 }
1251 }
1252 }
1253 }
1254
1255 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1256 {
1257 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1258 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1259 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1260 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1261 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1262 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1263
1264 if (AR_SREV_9330(ah))
1265 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1266
1267 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1268 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1269 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1270 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1271 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1272 }
1273 }
1274
1275 /*
1276 * Initialize the ANI register values with default (ini) values.
1277 * This routine is called during a (full) hardware reset after
1278 * all the registers are initialised from the INI.
1279 */
1280 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1281 {
1282 struct ar5416AniState *aniState;
1283 struct ath_common *common = ath9k_hw_common(ah);
1284 struct ath9k_channel *chan = ah->curchan;
1285 struct ath9k_ani_default *iniDef;
1286 u32 val;
1287
1288 aniState = &ah->ani;
1289 iniDef = &aniState->iniDef;
1290
1291 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1292 ah->hw_version.macVersion,
1293 ah->hw_version.macRev,
1294 ah->opmode,
1295 chan->channel);
1296
1297 val = REG_READ(ah, AR_PHY_SFCORR);
1298 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1299 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1300 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1301
1302 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1303 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1304 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1305 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1306
1307 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1308 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1309 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1310 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1311 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1312 iniDef->firstep = REG_READ_FIELD(ah,
1313 AR_PHY_FIND_SIG,
1314 AR_PHY_FIND_SIG_FIRSTEP);
1315 iniDef->firstepLow = REG_READ_FIELD(ah,
1316 AR_PHY_FIND_SIG_LOW,
1317 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1318 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1319 AR_PHY_TIMING5,
1320 AR_PHY_TIMING5_CYCPWR_THR1);
1321 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1322 AR_PHY_EXT_CCA,
1323 AR_PHY_EXT_CYCPWR_THR1);
1324
1325 /* these levels just got reset to defaults by the INI */
1326 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1327 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1328 aniState->ofdmWeakSigDetect = true;
1329 aniState->mrcCCK = true;
1330 }
1331
1332 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1333 struct ath_hw_radar_conf *conf)
1334 {
1335 unsigned int regWrites = 0;
1336 u32 radar_0 = 0, radar_1 = 0;
1337
1338 if (!conf) {
1339 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1340 return;
1341 }
1342
1343 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1344 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1345 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1346 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1347 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1348 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1349
1350 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1351 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1352 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1353 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1354 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1355
1356 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1357 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1358 if (conf->ext_channel)
1359 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1360 else
1361 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1362
1363 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1364 REG_WRITE_ARRAY(&ah->ini_dfs,
1365 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1366 }
1367 }
1368
1369 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1370 {
1371 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1372
1373 conf->fir_power = -28;
1374 conf->radar_rssi = 0;
1375 conf->pulse_height = 10;
1376 conf->pulse_rssi = 24;
1377 conf->pulse_inband = 8;
1378 conf->pulse_maxlen = 255;
1379 conf->pulse_inband_step = 12;
1380 conf->radar_inband = 8;
1381 }
1382
1383 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1384 struct ath_hw_antcomb_conf *antconf)
1385 {
1386 u32 regval;
1387
1388 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1389 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1390 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1391 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1392 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1393 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1394 AR_PHY_ANT_FAST_DIV_BIAS_S;
1395
1396 if (AR_SREV_9330_11(ah)) {
1397 antconf->lna1_lna2_switch_delta = -1;
1398 antconf->lna1_lna2_delta = -9;
1399 antconf->div_group = 1;
1400 } else if (AR_SREV_9485(ah)) {
1401 antconf->lna1_lna2_switch_delta = -1;
1402 antconf->lna1_lna2_delta = -9;
1403 antconf->div_group = 2;
1404 } else if (AR_SREV_9565(ah)) {
1405 antconf->lna1_lna2_switch_delta = 3;
1406 antconf->lna1_lna2_delta = -9;
1407 antconf->div_group = 3;
1408 } else {
1409 antconf->lna1_lna2_switch_delta = -1;
1410 antconf->lna1_lna2_delta = -3;
1411 antconf->div_group = 0;
1412 }
1413 }
1414
1415 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1416 struct ath_hw_antcomb_conf *antconf)
1417 {
1418 u32 regval;
1419
1420 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1421 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1422 AR_PHY_ANT_DIV_ALT_LNACONF |
1423 AR_PHY_ANT_FAST_DIV_BIAS |
1424 AR_PHY_ANT_DIV_MAIN_GAINTB |
1425 AR_PHY_ANT_DIV_ALT_GAINTB);
1426 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1427 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1428 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1429 & AR_PHY_ANT_DIV_ALT_LNACONF);
1430 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1431 & AR_PHY_ANT_FAST_DIV_BIAS);
1432 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1433 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1434 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1435 & AR_PHY_ANT_DIV_ALT_GAINTB);
1436
1437 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1438 }
1439
1440 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1441
1442 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1443 {
1444 struct ath9k_hw_capabilities *pCap = &ah->caps;
1445 u8 ant_div_ctl1;
1446 u32 regval;
1447
1448 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1449 return;
1450
1451 if (AR_SREV_9485(ah)) {
1452 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1453 IS_CHAN_2GHZ(ah->curchan));
1454 if (enable) {
1455 regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1456 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1457 }
1458 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1459 AR_SWITCH_TABLE_COM2_ALL, regval);
1460 }
1461
1462 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1463
1464 /*
1465 * Set MAIN/ALT LNA conf.
1466 * Set MAIN/ALT gain_tb.
1467 */
1468 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1469 regval &= (~AR_ANT_DIV_CTRL_ALL);
1470 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1471 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1472
1473 if (AR_SREV_9485_11_OR_LATER(ah)) {
1474 /*
1475 * Enable LNA diversity.
1476 */
1477 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1478 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1479 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1480 if (enable)
1481 regval |= AR_ANT_DIV_ENABLE;
1482
1483 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1484
1485 /*
1486 * Enable fast antenna diversity.
1487 */
1488 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1489 regval &= ~AR_FAST_DIV_ENABLE;
1490 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1491 if (enable)
1492 regval |= AR_FAST_DIV_ENABLE;
1493
1494 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1495
1496 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1497 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1498 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1499 AR_PHY_ANT_DIV_ALT_LNACONF |
1500 AR_PHY_ANT_DIV_ALT_GAINTB |
1501 AR_PHY_ANT_DIV_MAIN_GAINTB));
1502 /*
1503 * Set MAIN to LNA1 and ALT to LNA2 at the
1504 * beginning.
1505 */
1506 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1507 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1508 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1509 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1510 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1511 }
1512 } else if (AR_SREV_9565(ah)) {
1513 if (enable) {
1514 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1515 AR_ANT_DIV_ENABLE);
1516 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1517 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1518 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1519 AR_FAST_DIV_ENABLE);
1520 REG_SET_BIT(ah, AR_PHY_RESTART,
1521 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1522 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1523 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1524 } else {
1525 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1526 AR_ANT_DIV_ENABLE);
1527 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1528 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1529 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1530 AR_FAST_DIV_ENABLE);
1531 REG_CLR_BIT(ah, AR_PHY_RESTART,
1532 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1533 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1534 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1535
1536 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1537 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1538 AR_PHY_ANT_DIV_ALT_LNACONF |
1539 AR_PHY_ANT_DIV_MAIN_GAINTB |
1540 AR_PHY_ANT_DIV_ALT_GAINTB);
1541 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1542 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1543 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1544 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1545 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1546 }
1547 }
1548 }
1549
1550 #endif
1551
1552 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1553 struct ath9k_channel *chan,
1554 u8 *ini_reloaded)
1555 {
1556 unsigned int regWrites = 0;
1557 u32 modesIndex;
1558
1559 if (IS_CHAN_5GHZ(chan))
1560 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1561 else
1562 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1563
1564 if (modesIndex == ah->modes_index) {
1565 *ini_reloaded = false;
1566 goto set_rfmode;
1567 }
1568
1569 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1570 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1571 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1572 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1573
1574 if (AR_SREV_9462_20_OR_LATER(ah))
1575 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1576 modesIndex);
1577
1578 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1579
1580 if (AR_SREV_9462_20_OR_LATER(ah)) {
1581 /*
1582 * CUS217 mix LNA mode.
1583 */
1584 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1585 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1586 1, regWrites);
1587 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1588 modesIndex, regWrites);
1589 }
1590 }
1591
1592 /*
1593 * For 5GHz channels requiring Fast Clock, apply
1594 * different modal values.
1595 */
1596 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1597 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1598
1599 if (AR_SREV_9565(ah))
1600 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1601
1602 /*
1603 * JAPAN regulatory.
1604 */
1605 if (chan->channel == 2484)
1606 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1607
1608 ah->modes_index = modesIndex;
1609 *ini_reloaded = true;
1610
1611 set_rfmode:
1612 ar9003_hw_set_rfmode(ah, chan);
1613 return 0;
1614 }
1615
1616 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1617 struct ath_spec_scan *param)
1618 {
1619 u8 count;
1620
1621 if (!param->enabled) {
1622 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1623 AR_PHY_SPECTRAL_SCAN_ENABLE);
1624 return;
1625 }
1626
1627 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1628 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1629
1630 /* on AR93xx and newer, count = 0 will make the the chip send
1631 * spectral samples endlessly. Check if this really was intended,
1632 * and fix otherwise.
1633 */
1634 count = param->count;
1635 if (param->endless)
1636 count = 0;
1637 else if (param->count == 0)
1638 count = 1;
1639
1640 if (param->short_repeat)
1641 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1642 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1643 else
1644 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1645 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1646
1647 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1648 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1649 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1650 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1651 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1652 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1653
1654 return;
1655 }
1656
1657 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1658 {
1659 /* Activate spectral scan */
1660 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1661 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1662 }
1663
1664 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1665 {
1666 struct ath_common *common = ath9k_hw_common(ah);
1667
1668 /* Poll for spectral scan complete */
1669 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1670 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1671 0, AH_WAIT_TIMEOUT)) {
1672 ath_err(common, "spectral scan wait failed\n");
1673 return;
1674 }
1675 }
1676
1677 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1678 {
1679 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1680 REG_SET_BIT(ah, 0x9864, 0x7f000);
1681 REG_SET_BIT(ah, 0x9924, 0x7f00fe);
1682 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1683 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1684 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1685 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1686 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1687 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1688 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1689 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1690 }
1691
1692 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1693 {
1694 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1695 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1696 }
1697
1698 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1699 {
1700 static s16 p_pwr_array[ar9300RateSize] = { 0 };
1701 unsigned int i;
1702
1703 if (txpower <= MAX_RATE_POWER) {
1704 for (i = 0; i < ar9300RateSize; i++)
1705 p_pwr_array[i] = txpower;
1706 } else {
1707 for (i = 0; i < ar9300RateSize; i++)
1708 p_pwr_array[i] = MAX_RATE_POWER;
1709 }
1710
1711 REG_WRITE(ah, 0xa458, 0);
1712
1713 REG_WRITE(ah, 0xa3c0,
1714 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
1715 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
1716 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) |
1717 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1718 REG_WRITE(ah, 0xa3c4,
1719 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) |
1720 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) |
1721 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) |
1722 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1723 REG_WRITE(ah, 0xa3c8,
1724 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
1725 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
1726 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1727 REG_WRITE(ah, 0xa3cc,
1728 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) |
1729 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) |
1730 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) |
1731 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1732 REG_WRITE(ah, 0xa3d0,
1733 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) |
1734 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) |
1735 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
1736 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
1737 REG_WRITE(ah, 0xa3d4,
1738 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
1739 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
1740 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) |
1741 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0));
1742 REG_WRITE(ah, 0xa3e4,
1743 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
1744 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
1745 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) |
1746 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0));
1747 REG_WRITE(ah, 0xa3e8,
1748 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
1749 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
1750 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) |
1751 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0));
1752 REG_WRITE(ah, 0xa3d8,
1753 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
1754 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
1755 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1756 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
1757 REG_WRITE(ah, 0xa3dc,
1758 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
1759 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
1760 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) |
1761 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0));
1762 REG_WRITE(ah, 0xa3ec,
1763 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
1764 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
1765 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) |
1766 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
1767 }
1768
1769 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1770 {
1771 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1772 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1773 static const u32 ar9300_cca_regs[6] = {
1774 AR_PHY_CCA_0,
1775 AR_PHY_CCA_1,
1776 AR_PHY_CCA_2,
1777 AR_PHY_EXT_CCA,
1778 AR_PHY_EXT_CCA_1,
1779 AR_PHY_EXT_CCA_2,
1780 };
1781
1782 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1783 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1784 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1785 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1786 priv_ops->init_bb = ar9003_hw_init_bb;
1787 priv_ops->process_ini = ar9003_hw_process_ini;
1788 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1789 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1790 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1791 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1792 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1793 priv_ops->ani_control = ar9003_hw_ani_control;
1794 priv_ops->do_getnf = ar9003_hw_do_getnf;
1795 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1796 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1797 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1798
1799 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1800 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1801 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1802 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1803 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1804
1805 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1806 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1807 #endif
1808 ops->tx99_start = ar9003_hw_tx99_start;
1809 ops->tx99_stop = ar9003_hw_tx99_stop;
1810 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
1811
1812 ar9003_hw_set_nf_limits(ah);
1813 ar9003_hw_set_radar_conf(ah);
1814 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1815 }
1816
1817 /*
1818 * Baseband Watchdog signatures:
1819 *
1820 * 0x04000539: BB hang when operating in HT40 DFS Channel.
1821 * Full chip reset is not required, but a recovery
1822 * mechanism is needed.
1823 *
1824 * 0x1300000a: Related to CAC deafness.
1825 * Chip reset is not required.
1826 *
1827 * 0x0400000a: Related to CAC deafness.
1828 * Full chip reset is required.
1829 *
1830 * 0x04000b09: RX state machine gets into an illegal state
1831 * when a packet with unsupported rate is received.
1832 * Full chip reset is required and PHY_RESTART has
1833 * to be disabled.
1834 *
1835 * 0x04000409: Packet stuck on receive.
1836 * Full chip reset is required for all chips except AR9340.
1837 */
1838
1839 /*
1840 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
1841 */
1842 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
1843 {
1844 u32 val;
1845
1846 switch(ah->bb_watchdog_last_status) {
1847 case 0x04000539:
1848 val = REG_READ(ah, AR_PHY_RADAR_0);
1849 val &= (~AR_PHY_RADAR_0_FIRPWR);
1850 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
1851 REG_WRITE(ah, AR_PHY_RADAR_0, val);
1852 udelay(1);
1853 val = REG_READ(ah, AR_PHY_RADAR_0);
1854 val &= ~AR_PHY_RADAR_0_FIRPWR;
1855 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
1856 REG_WRITE(ah, AR_PHY_RADAR_0, val);
1857
1858 return false;
1859 case 0x1300000a:
1860 return false;
1861 case 0x0400000a:
1862 case 0x04000b09:
1863 return true;
1864 case 0x04000409:
1865 if (AR_SREV_9340(ah))
1866 return false;
1867 else
1868 return true;
1869 default:
1870 /*
1871 * For any other unknown signatures, do a
1872 * full chip reset.
1873 */
1874 return true;
1875 }
1876 }
1877 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
1878
1879 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1880 {
1881 struct ath_common *common = ath9k_hw_common(ah);
1882 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1883 u32 val, idle_count;
1884
1885 if (!idle_tmo_ms) {
1886 /* disable IRQ, disable chip-reset for BB panic */
1887 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1888 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1889 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1890 AR_PHY_WATCHDOG_IRQ_ENABLE));
1891
1892 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1893 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1894 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1895 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1896 AR_PHY_WATCHDOG_IDLE_ENABLE));
1897
1898 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1899 return;
1900 }
1901
1902 /* enable IRQ, disable chip-reset for BB watchdog */
1903 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1904 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1905 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1906 ~AR_PHY_WATCHDOG_RST_ENABLE);
1907
1908 /* bound limit to 10 secs */
1909 if (idle_tmo_ms > 10000)
1910 idle_tmo_ms = 10000;
1911
1912 /*
1913 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1914 *
1915 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1916 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1917 *
1918 * Given we use fast clock now in 5 GHz, these time units should
1919 * be common for both 2 GHz and 5 GHz.
1920 */
1921 idle_count = (100 * idle_tmo_ms) / 74;
1922 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1923 idle_count = (100 * idle_tmo_ms) / 37;
1924
1925 /*
1926 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1927 * set idle time-out.
1928 */
1929 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1930 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1931 AR_PHY_WATCHDOG_IDLE_MASK |
1932 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1933
1934 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1935 idle_tmo_ms);
1936 }
1937
1938 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1939 {
1940 /*
1941 * we want to avoid printing in ISR context so we save the
1942 * watchdog status to be printed later in bottom half context.
1943 */
1944 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1945
1946 /*
1947 * the watchdog timer should reset on status read but to be sure
1948 * sure we write 0 to the watchdog status bit.
1949 */
1950 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1951 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1952 }
1953
1954 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1955 {
1956 struct ath_common *common = ath9k_hw_common(ah);
1957 u32 status;
1958
1959 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1960 return;
1961
1962 status = ah->bb_watchdog_last_status;
1963 ath_dbg(common, RESET,
1964 "\n==== BB update: BB status=0x%08x ====\n", status);
1965 ath_dbg(common, RESET,
1966 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1967 MS(status, AR_PHY_WATCHDOG_INFO),
1968 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1969 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1970 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1971 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1972 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1973 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1974 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1975 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1976
1977 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1978 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1979 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1980 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1981 REG_READ(ah, AR_PHY_GEN_CTRL));
1982
1983 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1984 if (common->cc_survey.cycles)
1985 ath_dbg(common, RESET,
1986 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1987 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1988
1989 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1990 }
1991 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1992
1993 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1994 {
1995 u8 result;
1996 u32 val;
1997
1998 /* While receiving unsupported rate frame rx state machine
1999 * gets into a state 0xb and if phy_restart happens in that
2000 * state, BB would go hang. If RXSM is in 0xb state after
2001 * first bb panic, ensure to disable the phy_restart.
2002 */
2003 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
2004
2005 if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2006 ah->bb_hang_rx_ofdm = true;
2007 val = REG_READ(ah, AR_PHY_RESTART);
2008 val &= ~AR_PHY_RESTART_ENA;
2009 REG_WRITE(ah, AR_PHY_RESTART, val);
2010 }
2011 }
2012 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
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