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Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetoot...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20
21 static const int firstep_table[] =
22 /* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25 static const int cycpwrThr1_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29 /*
30 * register values to turn OFDM weak signal detection OFF
31 */
32 static const int m1ThreshLow_off = 127;
33 static const int m2ThreshLow_off = 127;
34 static const int m1Thresh_off = 127;
35 static const int m2Thresh_off = 127;
36 static const int m2CountThr_off = 31;
37 static const int m2CountThrLow_off = 63;
38 static const int m1ThreshLowExt_off = 127;
39 static const int m2ThreshLowExt_off = 127;
40 static const int m1ThreshExt_off = 127;
41 static const int m2ThreshExt_off = 127;
42
43 /**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
49 * for AR9300 family of chipsets.
50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69 {
70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 if (AR_SREV_9330(ah)) {
80 if (ah->is_clk_25mhz)
81 div = 75;
82 else
83 div = 120;
84
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
89 /*
90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
94 */
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
98 } else if (AR_SREV_9340(ah)) {
99 if (ah->is_clk_25mhz) {
100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
103 } else {
104 channelSel = CHANSEL_2G(freq) >> 1;
105 }
106 } else if (AR_SREV_9550(ah)) {
107 if (ah->is_clk_25mhz)
108 div = 75;
109 else
110 div = 120;
111
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
115 } else {
116 channelSel = CHANSEL_2G(freq);
117 }
118 /* Set to 2G mode */
119 bMode = 1;
120 } else {
121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
122 ah->is_clk_25mhz) {
123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
125 channelSel = (channelSel << 17) | chan_frac;
126 } else {
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
129 channelSel >>= 1;
130 }
131 /* Set to 5G mode */
132 bMode = 0;
133 }
134
135 /* Enable fractional mode for all channels */
136 fracMode = 1;
137 aModeRefSel = 0;
138 loadSynthChannel = 0;
139
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
142
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
146
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
151
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
157
158 ah->curchan = chan;
159
160 return 0;
161 }
162
163 /**
164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
165 * @ah: atheros hardware structure
166 * @chan:
167 *
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
170 *
171 * Spur mitigation for MRC CCK
172 */
173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
175 {
176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
177 int cur_bb_spur, negative = 0, cck_spur_freq;
178 int i;
179 int range, max_spur_cnts, synth_freq;
180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
181
182 /*
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
185 */
186
187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
188 AR_SREV_9550(ah)) {
189 if (spur_fbin_ptr[0] == 0) /* No spur */
190 return;
191 max_spur_cnts = 5;
192 if (IS_CHAN_HT40(chan)) {
193 range = 19;
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
197 else
198 synth_freq = chan->channel - 10;
199 } else {
200 range = 10;
201 synth_freq = chan->channel;
202 }
203 } else {
204 range = AR_SREV_9462(ah) ? 5 : 10;
205 max_spur_cnts = 4;
206 synth_freq = chan->channel;
207 }
208
209 for (i = 0; i < max_spur_cnts; i++) {
210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
211 continue;
212
213 negative = 0;
214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
215 AR_SREV_9550(ah))
216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
217 IS_CHAN_2GHZ(chan));
218 else
219 cur_bb_spur = spur_freq[i];
220
221 cur_bb_spur -= synth_freq;
222 if (cur_bb_spur < 0) {
223 negative = 1;
224 cur_bb_spur = -cur_bb_spur;
225 }
226 if (cur_bb_spur < range) {
227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
228
229 if (negative == 1)
230 cck_spur_freq = -cck_spur_freq;
231
232 cck_spur_freq = cck_spur_freq & 0xfffff;
233
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
240 0x2);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
243 0x1);
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
246 cck_spur_freq);
247
248 return;
249 }
250 }
251
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
258 }
259
260 /* Clean all spur register fields */
261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
262 {
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
281
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
302 }
303
304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
305 int freq_offset,
306 int spur_freq_sd,
307 int spur_delta_phase,
308 int spur_subchannel_sd,
309 int range,
310 int synth_freq)
311 {
312 int mask_index = 0;
313
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
325
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
329
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
336
337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
342
343 mask_index = (freq_offset << 4) / 5;
344 if (mask_index < 0)
345 mask_index = mask_index - 1;
346
347 mask_index = mask_index & 0x7f;
348
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
369 }
370
371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
372 int freq_offset)
373 {
374 int mask_index = 0;
375
376 mask_index = (freq_offset << 4) / 5;
377 if (mask_index < 0)
378 mask_index = mask_index - 1;
379
380 mask_index = mask_index & 0x7f;
381
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
384 mask_index);
385
386 /* A == B */
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
389 mask_index);
390
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
393 mask_index);
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
398
399 /* A == B */
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
402 }
403
404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
406 int freq_offset,
407 int range,
408 int synth_freq)
409 {
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
413
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
419 else
420 spur_subchannel_sd = 0;
421
422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
423
424 } else {
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
428 else
429 spur_subchannel_sd = 1;
430
431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
432
433 }
434
435 spur_delta_phase = (freq_offset << 17) / 5;
436
437 } else {
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
441 }
442
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
445
446 ar9003_hw_spur_ofdm(ah,
447 freq_offset,
448 spur_freq_sd,
449 spur_delta_phase,
450 spur_subchannel_sd,
451 range, synth_freq);
452 }
453
454 /* Spur mitigation for OFDM */
455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
457 {
458 int synth_freq;
459 int range = 10;
460 int freq_offset = 0;
461 int mode;
462 u8* spurChansPtr;
463 unsigned int i;
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
465
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
468 mode = 0;
469 }
470 else {
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
472 mode = 1;
473 }
474
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
477
478 if (IS_CHAN_HT40(chan)) {
479 range = 19;
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
483 else
484 synth_freq = chan->channel + 10;
485 } else {
486 range = 10;
487 synth_freq = chan->channel;
488 }
489
490 ar9003_hw_spur_ofdm_clear(ah);
491
492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
495 if (abs(freq_offset) < range) {
496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
497 range, synth_freq);
498
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
501 mode);
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
505 }
506
507 break;
508 }
509 }
510 }
511
512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
514 {
515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
518 }
519
520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
521 struct ath9k_channel *chan)
522 {
523 u32 pll;
524
525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
526
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
531
532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
533
534 return pll;
535 }
536
537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539 {
540 u32 phymode;
541 u32 enableDacFifo = 0;
542
543 enableDacFifo =
544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
545
546 /* Enable 11n HT, 20 MHz */
547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
549
550 /* Configure baseband for dynamic 20/40 operation */
551 if (IS_CHAN_HT40(chan)) {
552 phymode |= AR_PHY_GC_DYN2040_EN;
553 /* Configure control (primary) channel at +-10MHz */
554 if (IS_CHAN_HT40PLUS(chan))
555 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
556
557 }
558
559 /* make sure we preserve INI settings */
560 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
561 /* turn off Green Field detection for STA for now */
562 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
563
564 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
565
566 /* Configure MAC for 20/40 operation */
567 ath9k_hw_set11nmac2040(ah, chan);
568
569 /* global transmit timeout (25 TUs default)*/
570 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
571 /* carrier sense timeout */
572 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
573 }
574
575 static void ar9003_hw_init_bb(struct ath_hw *ah,
576 struct ath9k_channel *chan)
577 {
578 u32 synthDelay;
579
580 /*
581 * Wait for the frequency synth to settle (synth goes on
582 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
583 * Value is in 100ns increments.
584 */
585 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
586
587 /* Activate the PHY (includes baseband activate + synthesizer on) */
588 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
589 ath9k_hw_synth_delay(ah, chan, synthDelay);
590 }
591
592 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
593 {
594 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
595 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
596 AR_PHY_SWAP_ALT_CHAIN);
597
598 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
599 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
600
601 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
602 tx = 3;
603
604 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
605 }
606
607 /*
608 * Override INI values with chip specific configuration.
609 */
610 static void ar9003_hw_override_ini(struct ath_hw *ah)
611 {
612 u32 val;
613
614 /*
615 * Set the RX_ABORT and RX_DIS and clear it only after
616 * RXE is set for MAC. This prevents frames with
617 * corrupted descriptor status.
618 */
619 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
620
621 /*
622 * For AR9280 and above, there is a new feature that allows
623 * Multicast search based on both MAC Address and Key ID. By default,
624 * this feature is enabled. But since the driver is not using this
625 * feature, we switch it off; otherwise multicast search based on
626 * MAC addr only will fail.
627 */
628 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
629 val |= AR_AGG_WEP_ENABLE_FIX |
630 AR_AGG_WEP_ENABLE |
631 AR_PCU_MISC_MODE2_CFP_IGNORE;
632 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
633
634 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
635 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
636 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
637
638 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
639 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
640 ah->enabled_cals |= TX_IQ_CAL;
641 else
642 ah->enabled_cals &= ~TX_IQ_CAL;
643
644 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
645 ah->enabled_cals |= TX_CL_CAL;
646 else
647 ah->enabled_cals &= ~TX_CL_CAL;
648 }
649 }
650
651 static void ar9003_hw_prog_ini(struct ath_hw *ah,
652 struct ar5416IniArray *iniArr,
653 int column)
654 {
655 unsigned int i, regWrites = 0;
656
657 /* New INI format: Array may be undefined (pre, core, post arrays) */
658 if (!iniArr->ia_array)
659 return;
660
661 /*
662 * New INI format: Pre, core, and post arrays for a given subsystem
663 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
664 * the array is non-modal and force the column to 1.
665 */
666 if (column >= iniArr->ia_columns)
667 column = 1;
668
669 for (i = 0; i < iniArr->ia_rows; i++) {
670 u32 reg = INI_RA(iniArr, i, 0);
671 u32 val = INI_RA(iniArr, i, column);
672
673 REG_WRITE(ah, reg, val);
674
675 DO_DELAY(regWrites);
676 }
677 }
678
679 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
680 struct ath9k_channel *chan)
681 {
682 int ret;
683
684 if (IS_CHAN_2GHZ(chan)) {
685 if (IS_CHAN_HT40(chan))
686 return 7;
687 else
688 return 8;
689 }
690
691 if (chan->channel <= 5350)
692 ret = 1;
693 else if ((chan->channel > 5350) && (chan->channel <= 5600))
694 ret = 3;
695 else
696 ret = 5;
697
698 if (IS_CHAN_HT40(chan))
699 ret++;
700
701 return ret;
702 }
703
704 static int ar9003_hw_process_ini(struct ath_hw *ah,
705 struct ath9k_channel *chan)
706 {
707 unsigned int regWrites = 0, i;
708 u32 modesIndex;
709
710 if (IS_CHAN_5GHZ(chan))
711 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
712 else
713 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
714
715 /*
716 * SOC, MAC, BB, RADIO initvals.
717 */
718 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
719 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
720 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
721 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
722 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
723 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
724 ar9003_hw_prog_ini(ah,
725 &ah->ini_radio_post_sys2ant,
726 modesIndex);
727 }
728
729 /*
730 * RXGAIN initvals.
731 */
732 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
733
734 if (AR_SREV_9462_20_OR_LATER(ah)) {
735 /*
736 * CUS217 mix LNA mode.
737 */
738 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
739 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
740 1, regWrites);
741 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
742 modesIndex, regWrites);
743 }
744
745 /*
746 * 5G-XLNA
747 */
748 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
749 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
750 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
751 modesIndex, regWrites);
752 }
753 }
754
755 if (AR_SREV_9550(ah))
756 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
757 regWrites);
758
759 /*
760 * TXGAIN initvals.
761 */
762 if (AR_SREV_9550(ah)) {
763 int modes_txgain_index;
764
765 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
766 if (modes_txgain_index < 0)
767 return -EINVAL;
768
769 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
770 regWrites);
771 } else {
772 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
773 }
774
775 /*
776 * For 5GHz channels requiring Fast Clock, apply
777 * different modal values.
778 */
779 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
780 REG_WRITE_ARRAY(&ah->iniModesFastClock,
781 modesIndex, regWrites);
782
783 /*
784 * Clock frequency initvals.
785 */
786 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
787
788 /*
789 * JAPAN regulatory.
790 */
791 if (chan->channel == 2484)
792 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
793
794 ah->modes_index = modesIndex;
795 ar9003_hw_override_ini(ah);
796 ar9003_hw_set_channel_regs(ah, chan);
797 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
798 ath9k_hw_apply_txpower(ah, chan, false);
799
800 return 0;
801 }
802
803 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
804 struct ath9k_channel *chan)
805 {
806 u32 rfMode = 0;
807
808 if (chan == NULL)
809 return;
810
811 if (IS_CHAN_2GHZ(chan))
812 rfMode |= AR_PHY_MODE_DYNAMIC;
813 else
814 rfMode |= AR_PHY_MODE_OFDM;
815
816 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
817 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
818 if (IS_CHAN_QUARTER_RATE(chan))
819 rfMode |= AR_PHY_MODE_QUARTER;
820 if (IS_CHAN_HALF_RATE(chan))
821 rfMode |= AR_PHY_MODE_HALF;
822
823 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
824 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
825 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
826
827 REG_WRITE(ah, AR_PHY_MODE, rfMode);
828 }
829
830 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
831 {
832 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
833 }
834
835 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
836 struct ath9k_channel *chan)
837 {
838 u32 coef_scaled, ds_coef_exp, ds_coef_man;
839 u32 clockMhzScaled = 0x64000000;
840 struct chan_centers centers;
841
842 /*
843 * half and quarter rate can divide the scaled clock by 2 or 4
844 * scale for selected channel bandwidth
845 */
846 if (IS_CHAN_HALF_RATE(chan))
847 clockMhzScaled = clockMhzScaled >> 1;
848 else if (IS_CHAN_QUARTER_RATE(chan))
849 clockMhzScaled = clockMhzScaled >> 2;
850
851 /*
852 * ALGO -> coef = 1e8/fcarrier*fclock/40;
853 * scaled coef to provide precision for this floating calculation
854 */
855 ath9k_hw_get_channel_centers(ah, chan, &centers);
856 coef_scaled = clockMhzScaled / centers.synth_center;
857
858 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
859 &ds_coef_exp);
860
861 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
862 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
863 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
864 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
865
866 /*
867 * For Short GI,
868 * scaled coeff is 9/10 that of normal coeff
869 */
870 coef_scaled = (9 * coef_scaled) / 10;
871
872 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
873 &ds_coef_exp);
874
875 /* for short gi */
876 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
877 AR_PHY_SGI_DSC_MAN, ds_coef_man);
878 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
879 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
880 }
881
882 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
883 {
884 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
885 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
886 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
887 }
888
889 /*
890 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
891 * Read the phy active delay register. Value is in 100ns increments.
892 */
893 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
894 {
895 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
896
897 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
898
899 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
900 }
901
902 static bool ar9003_hw_ani_control(struct ath_hw *ah,
903 enum ath9k_ani_cmd cmd, int param)
904 {
905 struct ath_common *common = ath9k_hw_common(ah);
906 struct ath9k_channel *chan = ah->curchan;
907 struct ar5416AniState *aniState = &ah->ani;
908 int m1ThreshLow, m2ThreshLow;
909 int m1Thresh, m2Thresh;
910 int m2CountThr, m2CountThrLow;
911 int m1ThreshLowExt, m2ThreshLowExt;
912 int m1ThreshExt, m2ThreshExt;
913 s32 value, value2;
914
915 switch (cmd & ah->ani_function) {
916 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
917 /*
918 * on == 1 means ofdm weak signal detection is ON
919 * on == 1 is the default, for less noise immunity
920 *
921 * on == 0 means ofdm weak signal detection is OFF
922 * on == 0 means more noise imm
923 */
924 u32 on = param ? 1 : 0;
925
926 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
927 goto skip_ws_det;
928
929 m1ThreshLow = on ?
930 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
931 m2ThreshLow = on ?
932 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
933 m1Thresh = on ?
934 aniState->iniDef.m1Thresh : m1Thresh_off;
935 m2Thresh = on ?
936 aniState->iniDef.m2Thresh : m2Thresh_off;
937 m2CountThr = on ?
938 aniState->iniDef.m2CountThr : m2CountThr_off;
939 m2CountThrLow = on ?
940 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
941 m1ThreshLowExt = on ?
942 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
943 m2ThreshLowExt = on ?
944 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
945 m1ThreshExt = on ?
946 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
947 m2ThreshExt = on ?
948 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
949
950 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
951 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
952 m1ThreshLow);
953 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
954 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
955 m2ThreshLow);
956 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
957 AR_PHY_SFCORR_M1_THRESH,
958 m1Thresh);
959 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
960 AR_PHY_SFCORR_M2_THRESH,
961 m2Thresh);
962 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
963 AR_PHY_SFCORR_M2COUNT_THR,
964 m2CountThr);
965 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
966 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
967 m2CountThrLow);
968 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
969 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
970 m1ThreshLowExt);
971 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
972 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
973 m2ThreshLowExt);
974 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
975 AR_PHY_SFCORR_EXT_M1_THRESH,
976 m1ThreshExt);
977 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
978 AR_PHY_SFCORR_EXT_M2_THRESH,
979 m2ThreshExt);
980 skip_ws_det:
981 if (on)
982 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
983 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
984 else
985 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
986 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
987
988 if (on != aniState->ofdmWeakSigDetect) {
989 ath_dbg(common, ANI,
990 "** ch %d: ofdm weak signal: %s=>%s\n",
991 chan->channel,
992 aniState->ofdmWeakSigDetect ?
993 "on" : "off",
994 on ? "on" : "off");
995 if (on)
996 ah->stats.ast_ani_ofdmon++;
997 else
998 ah->stats.ast_ani_ofdmoff++;
999 aniState->ofdmWeakSigDetect = on;
1000 }
1001 break;
1002 }
1003 case ATH9K_ANI_FIRSTEP_LEVEL:{
1004 u32 level = param;
1005
1006 if (level >= ARRAY_SIZE(firstep_table)) {
1007 ath_dbg(common, ANI,
1008 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1009 level, ARRAY_SIZE(firstep_table));
1010 return false;
1011 }
1012
1013 /*
1014 * make register setting relative to default
1015 * from INI file & cap value
1016 */
1017 value = firstep_table[level] -
1018 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1019 aniState->iniDef.firstep;
1020 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1021 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1022 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1023 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1024 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1025 AR_PHY_FIND_SIG_FIRSTEP,
1026 value);
1027 /*
1028 * we need to set first step low register too
1029 * make register setting relative to default
1030 * from INI file & cap value
1031 */
1032 value2 = firstep_table[level] -
1033 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1034 aniState->iniDef.firstepLow;
1035 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1036 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1037 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1038 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1039
1040 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1041 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1042
1043 if (level != aniState->firstepLevel) {
1044 ath_dbg(common, ANI,
1045 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1046 chan->channel,
1047 aniState->firstepLevel,
1048 level,
1049 ATH9K_ANI_FIRSTEP_LVL,
1050 value,
1051 aniState->iniDef.firstep);
1052 ath_dbg(common, ANI,
1053 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1054 chan->channel,
1055 aniState->firstepLevel,
1056 level,
1057 ATH9K_ANI_FIRSTEP_LVL,
1058 value2,
1059 aniState->iniDef.firstepLow);
1060 if (level > aniState->firstepLevel)
1061 ah->stats.ast_ani_stepup++;
1062 else if (level < aniState->firstepLevel)
1063 ah->stats.ast_ani_stepdown++;
1064 aniState->firstepLevel = level;
1065 }
1066 break;
1067 }
1068 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1069 u32 level = param;
1070
1071 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1072 ath_dbg(common, ANI,
1073 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1074 level, ARRAY_SIZE(cycpwrThr1_table));
1075 return false;
1076 }
1077 /*
1078 * make register setting relative to default
1079 * from INI file & cap value
1080 */
1081 value = cycpwrThr1_table[level] -
1082 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1083 aniState->iniDef.cycpwrThr1;
1084 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1085 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1086 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1087 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1088 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1089 AR_PHY_TIMING5_CYCPWR_THR1,
1090 value);
1091
1092 /*
1093 * set AR_PHY_EXT_CCA for extension channel
1094 * make register setting relative to default
1095 * from INI file & cap value
1096 */
1097 value2 = cycpwrThr1_table[level] -
1098 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1099 aniState->iniDef.cycpwrThr1Ext;
1100 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1101 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1102 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1103 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1104 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1105 AR_PHY_EXT_CYCPWR_THR1, value2);
1106
1107 if (level != aniState->spurImmunityLevel) {
1108 ath_dbg(common, ANI,
1109 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1110 chan->channel,
1111 aniState->spurImmunityLevel,
1112 level,
1113 ATH9K_ANI_SPUR_IMMUNE_LVL,
1114 value,
1115 aniState->iniDef.cycpwrThr1);
1116 ath_dbg(common, ANI,
1117 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1118 chan->channel,
1119 aniState->spurImmunityLevel,
1120 level,
1121 ATH9K_ANI_SPUR_IMMUNE_LVL,
1122 value2,
1123 aniState->iniDef.cycpwrThr1Ext);
1124 if (level > aniState->spurImmunityLevel)
1125 ah->stats.ast_ani_spurup++;
1126 else if (level < aniState->spurImmunityLevel)
1127 ah->stats.ast_ani_spurdown++;
1128 aniState->spurImmunityLevel = level;
1129 }
1130 break;
1131 }
1132 case ATH9K_ANI_MRC_CCK:{
1133 /*
1134 * is_on == 1 means MRC CCK ON (default, less noise imm)
1135 * is_on == 0 means MRC CCK is OFF (more noise imm)
1136 */
1137 bool is_on = param ? 1 : 0;
1138
1139 if (ah->caps.rx_chainmask == 1)
1140 break;
1141
1142 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1143 AR_PHY_MRC_CCK_ENABLE, is_on);
1144 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1145 AR_PHY_MRC_CCK_MUX_REG, is_on);
1146 if (is_on != aniState->mrcCCK) {
1147 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1148 chan->channel,
1149 aniState->mrcCCK ? "on" : "off",
1150 is_on ? "on" : "off");
1151 if (is_on)
1152 ah->stats.ast_ani_ccklow++;
1153 else
1154 ah->stats.ast_ani_cckhigh++;
1155 aniState->mrcCCK = is_on;
1156 }
1157 break;
1158 }
1159 default:
1160 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1161 return false;
1162 }
1163
1164 ath_dbg(common, ANI,
1165 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1166 aniState->spurImmunityLevel,
1167 aniState->ofdmWeakSigDetect ? "on" : "off",
1168 aniState->firstepLevel,
1169 aniState->mrcCCK ? "on" : "off",
1170 aniState->listenTime,
1171 aniState->ofdmPhyErrCount,
1172 aniState->cckPhyErrCount);
1173 return true;
1174 }
1175
1176 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1177 int16_t nfarray[NUM_NF_READINGS])
1178 {
1179 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1180 #define AR_PHY_CH_MINCCA_PWR_S 20
1181 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1182 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1183
1184 int16_t nf;
1185 int i;
1186
1187 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1188 if (ah->rxchainmask & BIT(i)) {
1189 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1190 AR_PHY_CH_MINCCA_PWR);
1191 nfarray[i] = sign_extend32(nf, 8);
1192
1193 if (IS_CHAN_HT40(ah->curchan)) {
1194 u8 ext_idx = AR9300_MAX_CHAINS + i;
1195
1196 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1197 AR_PHY_CH_EXT_MINCCA_PWR);
1198 nfarray[ext_idx] = sign_extend32(nf, 8);
1199 }
1200 }
1201 }
1202 }
1203
1204 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1205 {
1206 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1207 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1208 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1209 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1210 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1211 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1212
1213 if (AR_SREV_9330(ah))
1214 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1215
1216 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1217 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1218 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1219 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1220 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1221 }
1222 }
1223
1224 /*
1225 * Initialize the ANI register values with default (ini) values.
1226 * This routine is called during a (full) hardware reset after
1227 * all the registers are initialised from the INI.
1228 */
1229 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1230 {
1231 struct ar5416AniState *aniState;
1232 struct ath_common *common = ath9k_hw_common(ah);
1233 struct ath9k_channel *chan = ah->curchan;
1234 struct ath9k_ani_default *iniDef;
1235 u32 val;
1236
1237 aniState = &ah->ani;
1238 iniDef = &aniState->iniDef;
1239
1240 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1241 ah->hw_version.macVersion,
1242 ah->hw_version.macRev,
1243 ah->opmode,
1244 chan->channel);
1245
1246 val = REG_READ(ah, AR_PHY_SFCORR);
1247 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1248 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1249 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1250
1251 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1252 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1253 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1254 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1255
1256 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1257 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1258 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1259 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1260 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1261 iniDef->firstep = REG_READ_FIELD(ah,
1262 AR_PHY_FIND_SIG,
1263 AR_PHY_FIND_SIG_FIRSTEP);
1264 iniDef->firstepLow = REG_READ_FIELD(ah,
1265 AR_PHY_FIND_SIG_LOW,
1266 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1267 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1268 AR_PHY_TIMING5,
1269 AR_PHY_TIMING5_CYCPWR_THR1);
1270 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1271 AR_PHY_EXT_CCA,
1272 AR_PHY_EXT_CYCPWR_THR1);
1273
1274 /* these levels just got reset to defaults by the INI */
1275 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1276 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1277 aniState->ofdmWeakSigDetect = true;
1278 aniState->mrcCCK = true;
1279 }
1280
1281 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1282 struct ath_hw_radar_conf *conf)
1283 {
1284 u32 radar_0 = 0, radar_1 = 0;
1285
1286 if (!conf) {
1287 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1288 return;
1289 }
1290
1291 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1292 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1293 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1294 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1295 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1296 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1297
1298 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1299 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1300 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1301 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1302 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1303
1304 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1305 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1306 if (conf->ext_channel)
1307 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1308 else
1309 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1310 }
1311
1312 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1313 {
1314 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1315
1316 conf->fir_power = -28;
1317 conf->radar_rssi = 0;
1318 conf->pulse_height = 10;
1319 conf->pulse_rssi = 24;
1320 conf->pulse_inband = 8;
1321 conf->pulse_maxlen = 255;
1322 conf->pulse_inband_step = 12;
1323 conf->radar_inband = 8;
1324 }
1325
1326 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1327 struct ath_hw_antcomb_conf *antconf)
1328 {
1329 u32 regval;
1330
1331 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1332 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1333 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1334 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1335 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1336 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1337 AR_PHY_ANT_FAST_DIV_BIAS_S;
1338
1339 if (AR_SREV_9330_11(ah)) {
1340 antconf->lna1_lna2_switch_delta = -1;
1341 antconf->lna1_lna2_delta = -9;
1342 antconf->div_group = 1;
1343 } else if (AR_SREV_9485(ah)) {
1344 antconf->lna1_lna2_switch_delta = -1;
1345 antconf->lna1_lna2_delta = -9;
1346 antconf->div_group = 2;
1347 } else if (AR_SREV_9565(ah)) {
1348 antconf->lna1_lna2_switch_delta = 3;
1349 antconf->lna1_lna2_delta = -9;
1350 antconf->div_group = 3;
1351 } else {
1352 antconf->lna1_lna2_switch_delta = -1;
1353 antconf->lna1_lna2_delta = -3;
1354 antconf->div_group = 0;
1355 }
1356 }
1357
1358 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1359 struct ath_hw_antcomb_conf *antconf)
1360 {
1361 u32 regval;
1362
1363 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1364 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1365 AR_PHY_ANT_DIV_ALT_LNACONF |
1366 AR_PHY_ANT_FAST_DIV_BIAS |
1367 AR_PHY_ANT_DIV_MAIN_GAINTB |
1368 AR_PHY_ANT_DIV_ALT_GAINTB);
1369 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1370 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1371 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1372 & AR_PHY_ANT_DIV_ALT_LNACONF);
1373 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1374 & AR_PHY_ANT_FAST_DIV_BIAS);
1375 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1376 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1377 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1378 & AR_PHY_ANT_DIV_ALT_GAINTB);
1379
1380 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1381 }
1382
1383 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1384
1385 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1386 {
1387 struct ath9k_hw_capabilities *pCap = &ah->caps;
1388 u8 ant_div_ctl1;
1389 u32 regval;
1390
1391 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1392 return;
1393
1394 if (AR_SREV_9485(ah)) {
1395 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1396 IS_CHAN_2GHZ(ah->curchan));
1397 if (enable) {
1398 regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1399 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1400 }
1401 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1402 AR_SWITCH_TABLE_COM2_ALL, regval);
1403 }
1404
1405 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1406
1407 /*
1408 * Set MAIN/ALT LNA conf.
1409 * Set MAIN/ALT gain_tb.
1410 */
1411 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1412 regval &= (~AR_ANT_DIV_CTRL_ALL);
1413 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1414 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1415
1416 if (AR_SREV_9485_11_OR_LATER(ah)) {
1417 /*
1418 * Enable LNA diversity.
1419 */
1420 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1421 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1422 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1423 if (enable)
1424 regval |= AR_ANT_DIV_ENABLE;
1425
1426 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1427
1428 /*
1429 * Enable fast antenna diversity.
1430 */
1431 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1432 regval &= ~AR_FAST_DIV_ENABLE;
1433 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1434 if (enable)
1435 regval |= AR_FAST_DIV_ENABLE;
1436
1437 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1438
1439 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1440 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1441 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1442 AR_PHY_ANT_DIV_ALT_LNACONF |
1443 AR_PHY_ANT_DIV_ALT_GAINTB |
1444 AR_PHY_ANT_DIV_MAIN_GAINTB));
1445 /*
1446 * Set MAIN to LNA1 and ALT to LNA2 at the
1447 * beginning.
1448 */
1449 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1450 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1451 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1452 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1453 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1454 }
1455 } else if (AR_SREV_9565(ah)) {
1456 if (enable) {
1457 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1458 AR_ANT_DIV_ENABLE);
1459 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1460 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1461 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1462 AR_FAST_DIV_ENABLE);
1463 REG_SET_BIT(ah, AR_PHY_RESTART,
1464 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1465 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1466 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1467 } else {
1468 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1469 AR_ANT_DIV_ENABLE);
1470 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1471 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1472 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1473 AR_FAST_DIV_ENABLE);
1474 REG_CLR_BIT(ah, AR_PHY_RESTART,
1475 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1476 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1477 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1478
1479 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1480 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1481 AR_PHY_ANT_DIV_ALT_LNACONF |
1482 AR_PHY_ANT_DIV_MAIN_GAINTB |
1483 AR_PHY_ANT_DIV_ALT_GAINTB);
1484 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1485 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1486 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1487 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1488 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1489 }
1490 }
1491 }
1492
1493 #endif
1494
1495 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1496 struct ath9k_channel *chan,
1497 u8 *ini_reloaded)
1498 {
1499 unsigned int regWrites = 0;
1500 u32 modesIndex;
1501
1502 if (IS_CHAN_5GHZ(chan))
1503 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1504 else
1505 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1506
1507 if (modesIndex == ah->modes_index) {
1508 *ini_reloaded = false;
1509 goto set_rfmode;
1510 }
1511
1512 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1513 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1514 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1515 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1516
1517 if (AR_SREV_9462_20_OR_LATER(ah))
1518 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1519 modesIndex);
1520
1521 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1522
1523 if (AR_SREV_9462_20_OR_LATER(ah)) {
1524 /*
1525 * CUS217 mix LNA mode.
1526 */
1527 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1528 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1529 1, regWrites);
1530 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1531 modesIndex, regWrites);
1532 }
1533 }
1534
1535 /*
1536 * For 5GHz channels requiring Fast Clock, apply
1537 * different modal values.
1538 */
1539 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1540 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1541
1542 if (AR_SREV_9565(ah))
1543 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1544
1545 /*
1546 * JAPAN regulatory.
1547 */
1548 if (chan->channel == 2484)
1549 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1550
1551 ah->modes_index = modesIndex;
1552 *ini_reloaded = true;
1553
1554 set_rfmode:
1555 ar9003_hw_set_rfmode(ah, chan);
1556 return 0;
1557 }
1558
1559 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1560 struct ath_spec_scan *param)
1561 {
1562 u8 count;
1563
1564 if (!param->enabled) {
1565 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1566 AR_PHY_SPECTRAL_SCAN_ENABLE);
1567 return;
1568 }
1569
1570 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1571 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1572
1573 /* on AR93xx and newer, count = 0 will make the the chip send
1574 * spectral samples endlessly. Check if this really was intended,
1575 * and fix otherwise.
1576 */
1577 count = param->count;
1578 if (param->endless)
1579 count = 0;
1580 else if (param->count == 0)
1581 count = 1;
1582
1583 if (param->short_repeat)
1584 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1585 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1586 else
1587 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1588 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1589
1590 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1591 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1592 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1593 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1594 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1595 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1596
1597 return;
1598 }
1599
1600 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1601 {
1602 /* Activate spectral scan */
1603 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1604 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1605 }
1606
1607 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1608 {
1609 struct ath_common *common = ath9k_hw_common(ah);
1610
1611 /* Poll for spectral scan complete */
1612 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1613 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1614 0, AH_WAIT_TIMEOUT)) {
1615 ath_err(common, "spectral scan wait failed\n");
1616 return;
1617 }
1618 }
1619
1620 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1621 {
1622 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1623 REG_SET_BIT(ah, 0x9864, 0x7f000);
1624 REG_SET_BIT(ah, 0x9924, 0x7f00fe);
1625 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1626 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1627 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1628 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1629 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1630 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1631 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1632 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1633 }
1634
1635 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1636 {
1637 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1638 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1639 }
1640
1641 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1642 {
1643 static s16 p_pwr_array[ar9300RateSize] = { 0 };
1644 unsigned int i;
1645
1646 if (txpower <= MAX_RATE_POWER) {
1647 for (i = 0; i < ar9300RateSize; i++)
1648 p_pwr_array[i] = txpower;
1649 } else {
1650 for (i = 0; i < ar9300RateSize; i++)
1651 p_pwr_array[i] = MAX_RATE_POWER;
1652 }
1653
1654 REG_WRITE(ah, 0xa458, 0);
1655
1656 REG_WRITE(ah, 0xa3c0,
1657 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
1658 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
1659 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) |
1660 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1661 REG_WRITE(ah, 0xa3c4,
1662 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) |
1663 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) |
1664 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) |
1665 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1666 REG_WRITE(ah, 0xa3c8,
1667 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
1668 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
1669 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1670 REG_WRITE(ah, 0xa3cc,
1671 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) |
1672 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) |
1673 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) |
1674 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1675 REG_WRITE(ah, 0xa3d0,
1676 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) |
1677 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) |
1678 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
1679 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
1680 REG_WRITE(ah, 0xa3d4,
1681 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
1682 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
1683 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) |
1684 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0));
1685 REG_WRITE(ah, 0xa3e4,
1686 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
1687 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
1688 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) |
1689 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0));
1690 REG_WRITE(ah, 0xa3e8,
1691 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
1692 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
1693 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) |
1694 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0));
1695 REG_WRITE(ah, 0xa3d8,
1696 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
1697 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
1698 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1699 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
1700 REG_WRITE(ah, 0xa3dc,
1701 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
1702 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
1703 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) |
1704 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0));
1705 REG_WRITE(ah, 0xa3ec,
1706 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
1707 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
1708 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) |
1709 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
1710 }
1711
1712 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1713 {
1714 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1715 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1716 static const u32 ar9300_cca_regs[6] = {
1717 AR_PHY_CCA_0,
1718 AR_PHY_CCA_1,
1719 AR_PHY_CCA_2,
1720 AR_PHY_EXT_CCA,
1721 AR_PHY_EXT_CCA_1,
1722 AR_PHY_EXT_CCA_2,
1723 };
1724
1725 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1726 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1727 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1728 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1729 priv_ops->init_bb = ar9003_hw_init_bb;
1730 priv_ops->process_ini = ar9003_hw_process_ini;
1731 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1732 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1733 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1734 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1735 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1736 priv_ops->ani_control = ar9003_hw_ani_control;
1737 priv_ops->do_getnf = ar9003_hw_do_getnf;
1738 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1739 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1740 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1741
1742 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1743 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1744 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1745 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1746 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1747
1748 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1749 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1750 #endif
1751 ops->tx99_start = ar9003_hw_tx99_start;
1752 ops->tx99_stop = ar9003_hw_tx99_stop;
1753 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
1754
1755 ar9003_hw_set_nf_limits(ah);
1756 ar9003_hw_set_radar_conf(ah);
1757 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1758 }
1759
1760 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1761 {
1762 struct ath_common *common = ath9k_hw_common(ah);
1763 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1764 u32 val, idle_count;
1765
1766 if (!idle_tmo_ms) {
1767 /* disable IRQ, disable chip-reset for BB panic */
1768 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1769 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1770 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1771 AR_PHY_WATCHDOG_IRQ_ENABLE));
1772
1773 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1774 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1775 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1776 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1777 AR_PHY_WATCHDOG_IDLE_ENABLE));
1778
1779 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1780 return;
1781 }
1782
1783 /* enable IRQ, disable chip-reset for BB watchdog */
1784 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1785 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1786 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1787 ~AR_PHY_WATCHDOG_RST_ENABLE);
1788
1789 /* bound limit to 10 secs */
1790 if (idle_tmo_ms > 10000)
1791 idle_tmo_ms = 10000;
1792
1793 /*
1794 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1795 *
1796 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1797 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1798 *
1799 * Given we use fast clock now in 5 GHz, these time units should
1800 * be common for both 2 GHz and 5 GHz.
1801 */
1802 idle_count = (100 * idle_tmo_ms) / 74;
1803 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1804 idle_count = (100 * idle_tmo_ms) / 37;
1805
1806 /*
1807 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1808 * set idle time-out.
1809 */
1810 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1811 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1812 AR_PHY_WATCHDOG_IDLE_MASK |
1813 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1814
1815 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1816 idle_tmo_ms);
1817 }
1818
1819 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1820 {
1821 /*
1822 * we want to avoid printing in ISR context so we save the
1823 * watchdog status to be printed later in bottom half context.
1824 */
1825 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1826
1827 /*
1828 * the watchdog timer should reset on status read but to be sure
1829 * sure we write 0 to the watchdog status bit.
1830 */
1831 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1832 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1833 }
1834
1835 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1836 {
1837 struct ath_common *common = ath9k_hw_common(ah);
1838 u32 status;
1839
1840 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1841 return;
1842
1843 status = ah->bb_watchdog_last_status;
1844 ath_dbg(common, RESET,
1845 "\n==== BB update: BB status=0x%08x ====\n", status);
1846 ath_dbg(common, RESET,
1847 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1848 MS(status, AR_PHY_WATCHDOG_INFO),
1849 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1850 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1851 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1852 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1853 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1854 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1855 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1856 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1857
1858 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1859 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1860 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1861 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1862 REG_READ(ah, AR_PHY_GEN_CTRL));
1863
1864 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1865 if (common->cc_survey.cycles)
1866 ath_dbg(common, RESET,
1867 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1868 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1869
1870 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1871 }
1872 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1873
1874 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1875 {
1876 u32 val;
1877
1878 /* While receiving unsupported rate frame rx state machine
1879 * gets into a state 0xb and if phy_restart happens in that
1880 * state, BB would go hang. If RXSM is in 0xb state after
1881 * first bb panic, ensure to disable the phy_restart.
1882 */
1883 if (!((MS(ah->bb_watchdog_last_status,
1884 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1885 ah->bb_hang_rx_ofdm))
1886 return;
1887
1888 ah->bb_hang_rx_ofdm = true;
1889 val = REG_READ(ah, AR_PHY_RESTART);
1890 val &= ~AR_PHY_RESTART_ENA;
1891
1892 REG_WRITE(ah, AR_PHY_RESTART, val);
1893 }
1894 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
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