drivers/net/wireless/ath/ath9k/ar9003_wow.c

   1 /*
   2  * Copyright (c) 2012 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "ath9k.h"
  19 #include "reg.h"
  20 #include "reg_wow.h"
  21 #include "hw-ops.h"
  22
  23 static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
  24 {
  25         struct ath_common *common = ath9k_hw_common(ah);
  26
  27         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  28
  29         /* set rx disable bit */
  30         REG_WRITE(ah, AR_CR, AR_CR_RXD);
  31
  32         if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
  33                 ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
  34                         REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
  35                 return;
  36         }
  37
  38         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
  39 }
  40
  41 static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
  42 {
  43         struct ath_common *common = ath9k_hw_common(ah);
  44         u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
  45         u32 ctl[13] = {0};
  46         u32 data_word[KAL_NUM_DATA_WORDS];
  47         u8 i;
  48         u32 wow_ka_data_word0;
  49
  50         memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
  51         memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
  52
  53         /* set the transmit buffer */
  54         ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
  55         ctl[1] = 0;
  56         ctl[3] = 0xb;   /* OFDM_6M hardware value for this rate */
  57         ctl[4] = 0;
  58         ctl[7] = (ah->txchainmask) << 2;
  59         ctl[2] = 0xf << 16; /* tx_tries 0 */
  60
  61         for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
  62                 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
  63
  64         REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
  65
  66         data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
  67                        (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
  68         data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
  69                        (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
  70         data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
  71                        (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
  72         data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
  73                        (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
  74         data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
  75                        (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
  76         data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
  77
  78         if (AR_SREV_9462_20(ah)) {
  79                 /* AR9462 2.0 has an extra descriptor word (time based
  80                  * discard) compared to other chips */
  81                 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
  82                 wow_ka_data_word0 = AR_WOW_TXBUF(13);
  83         } else {
  84                 wow_ka_data_word0 = AR_WOW_TXBUF(12);
  85         }
  86
  87         for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
  88                 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
  89
  90 }
  91
  92 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
  93                                u8 *user_mask, int pattern_count,
  94                                int pattern_len)
  95 {
  96         int i;
  97         u32 pattern_val, mask_val;
  98         u32 set, clr;
  99
 100         if (pattern_count >= ah->wow.max_patterns)
 101                 return -ENOSPC;
 102
 103         REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
 104
 105         /* set the registers for pattern */
 106         for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
 107                 memcpy(&pattern_val, user_pattern, 4);
 108                 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
 109                           pattern_val);
 110                 user_pattern += 4;
 111         }
 112
 113         /* set the registers for mask */
 114         for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
 115                 memcpy(&mask_val, user_mask, 4);
 116                 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
 117                 user_mask += 4;
 118         }
 119
 120         /* set the pattern length to be matched
 121          *
 122          * AR_WOW_LENGTH1_REG1
 123          * bit 31:24 pattern 0 length
 124          * bit 23:16 pattern 1 length
 125          * bit 15:8 pattern 2 length
 126          * bit 7:0 pattern 3 length
 127          *
 128          * AR_WOW_LENGTH1_REG2
 129          * bit 31:24 pattern 4 length
 130          * bit 23:16 pattern 5 length
 131          * bit 15:8 pattern 6 length
 132          * bit 7:0 pattern 7 length
 133          *
 134          * the below logic writes out the new
 135          * pattern length for the corresponding
 136          * pattern_count, while masking out the
 137          * other fields
 138          */
 139
 140         ah->wow.wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
 141
 142         if (pattern_count < 4) {
 143                 /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
 144                 set = (pattern_len & AR_WOW_LENGTH_MAX) <<
 145                        AR_WOW_LEN1_SHIFT(pattern_count);
 146                 clr = AR_WOW_LENGTH1_MASK(pattern_count);
 147                 REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
 148         } else {
 149                 /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
 150                 set = (pattern_len & AR_WOW_LENGTH_MAX) <<
 151                        AR_WOW_LEN2_SHIFT(pattern_count);
 152                 clr = AR_WOW_LENGTH2_MASK(pattern_count);
 153                 REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
 154         }
 155
 156         return 0;
 157 }
 158 EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
 159
 160 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
 161 {
 162         u32 wow_status = 0;
 163         u32 val = 0, rval;
 164
 165         /*
 166          * read the WoW status register to know
 167          * the wakeup reason
 168          */
 169         rval = REG_READ(ah, AR_WOW_PATTERN);
 170         val = AR_WOW_STATUS(rval);
 171
 172         /*
 173          * mask only the WoW events that we have enabled. Sometimes
 174          * we have spurious WoW events from the AR_WOW_PATTERN
 175          * register. This mask will clean it up.
 176          */
 177
 178         val &= ah->wow.wow_event_mask;
 179
 180         if (val) {
 181                 if (val & AR_WOW_MAGIC_PAT_FOUND)
 182                         wow_status |= AH_WOW_MAGIC_PATTERN_EN;
 183                 if (AR_WOW_PATTERN_FOUND(val))
 184                         wow_status |= AH_WOW_USER_PATTERN_EN;
 185                 if (val & AR_WOW_KEEP_ALIVE_FAIL)
 186                         wow_status |= AH_WOW_LINK_CHANGE;
 187                 if (val & AR_WOW_BEACON_FAIL)
 188                         wow_status |= AH_WOW_BEACON_MISS;
 189         }
 190
 191         /*
 192          * set and clear WOW_PME_CLEAR registers for the chip to
 193          * generate next wow signal.
 194          * disable D3 before accessing other registers ?
 195          */
 196
 197         /* do we need to check the bit value 0x01000000 (7-10) ?? */
 198         REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
 199                 AR_PMCTRL_PWR_STATE_D1D3);
 200
 201         /*
 202          * clear all events
 203          */
 204         REG_WRITE(ah, AR_WOW_PATTERN,
 205                   AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
 206
 207         /*
 208          * restore the beacon threshold to init value
 209          */
 210         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
 211
 212         /*
 213          * Restore the way the PCI-E reset, Power-On-Reset, external
 214          * PCIE_POR_SHORT pins are tied to its original value.
 215          * Previously just before WoW sleep, we untie the PCI-E
 216          * reset to our Chip's Power On Reset so that any PCI-E
 217          * reset from the bus will not reset our chip
 218          */
 219         if (ah->is_pciexpress)
 220                 ath9k_hw_configpcipowersave(ah, false);
 221
 222         ah->wow.wow_event_mask = 0;
 223
 224         return wow_status;
 225 }
 226 EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
 227
 228 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
 229 {
 230         u32 wow_event_mask;
 231         u32 set, clr;
 232
 233         /*
 234          * wow_event_mask is a mask to the AR_WOW_PATTERN register to
 235          * indicate which WoW events we have enabled. The WoW events
 236          * are from the 'pattern_enable' in this function and
 237          * 'pattern_count' of ath9k_hw_wow_apply_pattern()
 238          */
 239         wow_event_mask = ah->wow.wow_event_mask;
 240
 241         /*
 242          * Untie Power-on-Reset from the PCI-E-Reset. When we are in
 243          * WOW sleep, we do want the Reset from the PCI-E to disturb
 244          * our hw state
 245          */
 246         if (ah->is_pciexpress) {
 247                 /*
 248                  * we need to untie the internal POR (power-on-reset)
 249                  * to the external PCI-E reset. We also need to tie
 250                  * the PCI-E Phy reset to the PCI-E reset.
 251                  */
 252                 set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
 253                 clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
 254                 REG_RMW(ah, AR_WA, set, clr);
 255         }
 256
 257         /*
 258          * set the power states appropriately and enable PME
 259          */
 260         set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
 261               AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
 262
 263         /*
 264          * set and clear WOW_PME_CLEAR registers for the chip
 265          * to generate next wow signal.
 266          */
 267         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
 268         clr = AR_PMCTRL_WOW_PME_CLR;
 269         REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
 270
 271         /*
 272          * Setup for:
 273          *      - beacon misses
 274          *      - magic pattern
 275          *      - keep alive timeout
 276          *      - pattern matching
 277          */
 278
 279         /*
 280          * Program default values for pattern backoff, aifs/slot/KAL count,
 281          * beacon miss timeout, KAL timeout, etc.
 282          */
 283         set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
 284         REG_SET_BIT(ah, AR_WOW_PATTERN, set);
 285
 286         set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
 287               AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
 288               AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
 289         REG_SET_BIT(ah, AR_WOW_COUNT, set);
 290
 291         if (pattern_enable & AH_WOW_BEACON_MISS)
 292                 set = AR_WOW_BEACON_TIMO;
 293         /* We are not using beacon miss, program a large value */
 294         else
 295                 set = AR_WOW_BEACON_TIMO_MAX;
 296
 297         REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
 298
 299         /*
 300          * Keep alive timo in ms except AR9280
 301          */
 302         if (!pattern_enable)
 303                 set = AR_WOW_KEEP_ALIVE_NEVER;
 304         else
 305                 set = KAL_TIMEOUT * 32;
 306
 307         REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
 308
 309         /*
 310          * Keep alive delay in us. based on 'power on clock',
 311          * therefore in usec
 312          */
 313         set = KAL_DELAY * 1000;
 314         REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
 315
 316         /*
 317          * Create keep alive pattern to respond to beacons
 318          */
 319         ath9k_wow_create_keep_alive_pattern(ah);
 320
 321         /*
 322          * Configure MAC WoW Registers
 323          */
 324         set = 0;
 325         /* Send keep alive timeouts anyway */
 326         clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
 327
 328         if (pattern_enable & AH_WOW_LINK_CHANGE)
 329                 wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
 330         else
 331                 set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
 332
 333         set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
 334         REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
 335
 336         /*
 337          * we are relying on a bmiss failure. ensure we have
 338          * enough threshold to prevent false positives
 339          */
 340         REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
 341                       AR_WOW_BMISSTHRESHOLD);
 342
 343         set = 0;
 344         clr = 0;
 345
 346         if (pattern_enable & AH_WOW_BEACON_MISS) {
 347                 set = AR_WOW_BEACON_FAIL_EN;
 348                 wow_event_mask |= AR_WOW_BEACON_FAIL;
 349         } else {
 350                 clr = AR_WOW_BEACON_FAIL_EN;
 351         }
 352
 353         REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
 354
 355         set = 0;
 356         clr = 0;
 357         /*
 358          * Enable the magic packet registers
 359          */
 360         if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
 361                 set = AR_WOW_MAGIC_EN;
 362                 wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
 363         } else {
 364                 clr = AR_WOW_MAGIC_EN;
 365         }
 366         set |= AR_WOW_MAC_INTR_EN;
 367         REG_RMW(ah, AR_WOW_PATTERN, set, clr);
 368
 369         REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
 370                   AR_WOW_PATTERN_SUPPORTED);
 371
 372         /*
 373          * Set the power states appropriately and enable PME
 374          */
 375         clr = 0;
 376         set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
 377               AR_PMCTRL_PWR_PM_CTRL_ENA;
 378
 379         clr = AR_PCIE_PM_CTRL_ENA;
 380         REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
 381
 382         /*
 383          * this is needed to prevent the chip waking up
 384          * the host within 3-4 seconds with certain
 385          * platform/BIOS. The fix is to enable
 386          * D1 & D3 to match original definition and
 387          * also match the OTP value. Anyway this
 388          * is more related to SW WOW.
 389          */
 390         clr = AR_PMCTRL_PWR_STATE_D1D3;
 391         REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
 392
 393         set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
 394         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
 395
 396         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
 397
 398         /* to bring down WOW power low margin */
 399         set = BIT(13);
 400         REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
 401         /* HW WoW */
 402         clr = BIT(5);
 403         REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
 404
 405         ath9k_hw_set_powermode_wow_sleep(ah);
 406         ah->wow.wow_event_mask = wow_event_mask;
 407 }
 408 EXPORT_SYMBOL(ath9k_hw_wow_enable);