drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <linux/leds.h>
  23 #include <linux/completion.h>
  24
  25 #include "debug.h"
  26 #include "common.h"
  27
  28 /*
  29  * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
  30  * should rely on this file or its contents.
  31  */
  32
  33 struct ath_node;
  34
  35 /* Macro to expand scalars to 64-bit objects */
  36
  37 #define ito64(x) (sizeof(x) == 1) ?                     \
  38         (((unsigned long long int)(x)) & (0xff)) :      \
  39         (sizeof(x) == 2) ?                              \
  40         (((unsigned long long int)(x)) & 0xffff) :      \
  41         ((sizeof(x) == 4) ?                             \
  42          (((unsigned long long int)(x)) & 0xffffffff) : \
  43          (unsigned long long int)(x))
  44
  45 /* increment with wrap-around */
  46 #define INCR(_l, _sz)   do {                    \
  47                 (_l)++;                         \
  48                 (_l) &= ((_sz) - 1);            \
  49         } while (0)
  50
  51 /* decrement with wrap-around */
  52 #define DECR(_l,  _sz)  do {                    \
  53                 (_l)--;                         \
  54                 (_l) &= ((_sz) - 1);            \
  55         } while (0)
  56
  57 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  58
  59 #define TSF_TO_TU(_h,_l) \
  60         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  61
  62 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  63
  64 struct ath_config {
  65         u32 ath_aggr_prot;
  66         u16 txpowlimit;
  67         u8 cabqReadytime;
  68 };
  69
  70 /*************************/
  71 /* Descriptor Management */
  72 /*************************/
  73
  74 #define ATH_TXBUF_RESET(_bf) do {                               \
  75                 (_bf)->bf_stale = false;                        \
  76                 (_bf)->bf_lastbf = NULL;                        \
  77                 (_bf)->bf_next = NULL;                          \
  78                 memset(&((_bf)->bf_state), 0,                   \
  79                        sizeof(struct ath_buf_state));           \
  80         } while (0)
  81
  82 #define ATH_RXBUF_RESET(_bf) do {               \
  83                 (_bf)->bf_stale = false;        \
  84         } while (0)
  85
  86 /**
  87  * enum buffer_type - Buffer type flags
  88  *
  89  * @BUF_HT: Send this buffer using HT capabilities
  90  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  91  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  92  *      (used in aggregation scheduling)
  93  * @BUF_RETRY: Indicates whether the buffer is retried
  94  * @BUF_XRETRY: To denote excessive retries of the buffer
  95  */
  96 enum buffer_type {
  97         BUF_HT                  = BIT(1),
  98         BUF_AMPDU               = BIT(2),
  99         BUF_AGGR                = BIT(3),
 100         BUF_RETRY               = BIT(4),
 101         BUF_XRETRY              = BIT(5),
 102 };
 103
 104 #define bf_nframes              bf_state.bfs_nframes
 105 #define bf_al                   bf_state.bfs_al
 106 #define bf_frmlen               bf_state.bfs_frmlen
 107 #define bf_retries              bf_state.bfs_retries
 108 #define bf_seqno                bf_state.bfs_seqno
 109 #define bf_tidno                bf_state.bfs_tidno
 110 #define bf_keyix                bf_state.bfs_keyix
 111 #define bf_keytype              bf_state.bfs_keytype
 112 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 113 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 114 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 115 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 116 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 117
 118 #define ATH_TXSTATUS_RING_SIZE 64
 119
 120 struct ath_descdma {
 121         void *dd_desc;
 122         dma_addr_t dd_desc_paddr;
 123         u32 dd_desc_len;
 124         struct ath_buf *dd_bufptr;
 125 };
 126
 127 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 128                       struct list_head *head, const char *name,
 129                       int nbuf, int ndesc, bool is_tx);
 130 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 131                          struct list_head *head);
 132
 133 /***********/
 134 /* RX / TX */
 135 /***********/
 136
 137 #define ATH_MAX_ANTENNA         3
 138 #define ATH_RXBUF               512
 139 #define ATH_TXBUF               512
 140 #define ATH_TXBUF_RESERVE       5
 141 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 142 #define ATH_TXMAXTRY            13
 143 #define ATH_MGT_TXMAXTRY        4
 144
 145 #define TID_TO_WME_AC(_tid)                             \
 146         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 147          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 148          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 149          WME_AC_VO)
 150
 151 #define ADDBA_EXCHANGE_ATTEMPTS    10
 152 #define ATH_AGGR_DELIM_SZ          4
 153 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 154 /* number of delimiters for encryption padding */
 155 #define ATH_AGGR_ENCRYPTDELIM      10
 156 /* minimum h/w qdepth to be sustained to maximize aggregation */
 157 #define ATH_AGGR_MIN_QDEPTH        2
 158 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 159
 160 #define IEEE80211_SEQ_SEQ_SHIFT    4
 161 #define IEEE80211_SEQ_MAX          4096
 162 #define IEEE80211_WEP_IVLEN        3
 163 #define IEEE80211_WEP_KIDLEN       1
 164 #define IEEE80211_WEP_CRCLEN       4
 165 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 166                                     (IEEE80211_WEP_IVLEN +      \
 167                                      IEEE80211_WEP_KIDLEN +     \
 168                                      IEEE80211_WEP_CRCLEN))
 169
 170 /* return whether a bit at index _n in bitmap _bm is set
 171  * _sz is the size of the bitmap  */
 172 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 173                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 174
 175 /* return block-ack bitmap index given sequence and starting sequence */
 176 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 177
 178 /* returns delimiter padding required given the packet length */
 179 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 180         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 181           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 182
 183 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 184         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 185
 186 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 187
 188 #define ATH_TX_COMPLETE_POLL_INT        1000
 189
 190 enum ATH_AGGR_STATUS {
 191         ATH_AGGR_DONE,
 192         ATH_AGGR_BAW_CLOSED,
 193         ATH_AGGR_LIMITED,
 194 };
 195
 196 #define ATH_TXFIFO_DEPTH 8
 197 struct ath_txq {
 198         int axq_class;
 199         u32 axq_qnum;
 200         u32 *axq_link;
 201         struct list_head axq_q;
 202         spinlock_t axq_lock;
 203         u32 axq_depth;
 204         bool stopped;
 205         bool axq_tx_inprogress;
 206         struct list_head axq_acq;
 207         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
 208         struct list_head txq_fifo_pending;
 209         u8 txq_headidx;
 210         u8 txq_tailidx;
 211 };
 212
 213 struct ath_atx_ac {
 214         int sched;
 215         int qnum;
 216         struct list_head list;
 217         struct list_head tid_q;
 218 };
 219
 220 struct ath_buf_state {
 221         int bfs_nframes;
 222         u16 bfs_al;
 223         u16 bfs_frmlen;
 224         int bfs_seqno;
 225         int bfs_tidno;
 226         int bfs_retries;
 227         u8 bf_type;
 228         u8 bfs_paprd;
 229         unsigned long bfs_paprd_timestamp;
 230         u32 bfs_keyix;
 231         enum ath9k_key_type bfs_keytype;
 232 };
 233
 234 struct ath_buf {
 235         struct list_head list;
 236         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 237                                            an aggregate) */
 238         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 239         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 240         void *bf_desc;                  /* virtual addr of desc */
 241         dma_addr_t bf_daddr;            /* physical addr of desc */
 242         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 243         bool bf_stale;
 244         bool bf_isnullfunc;
 245         bool bf_tx_aborted;
 246         u16 bf_flags;
 247         struct ath_buf_state bf_state;
 248         dma_addr_t bf_dmacontext;
 249         struct ath_wiphy *aphy;
 250 };
 251
 252 struct ath_atx_tid {
 253         struct list_head list;
 254         struct list_head buf_q;
 255         struct ath_node *an;
 256         struct ath_atx_ac *ac;
 257         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
 258         u16 seq_start;
 259         u16 seq_next;
 260         u16 baw_size;
 261         int tidno;
 262         int baw_head;   /* first un-acked tx buffer */
 263         int baw_tail;   /* next unused tx buffer slot */
 264         int sched;
 265         int paused;
 266         u8 state;
 267 };
 268
 269 struct ath_node {
 270         struct ath_common *common;
 271         struct ath_atx_tid tid[WME_NUM_TID];
 272         struct ath_atx_ac ac[WME_NUM_AC];
 273         u16 maxampdu;
 274         u8 mpdudensity;
 275         int last_rssi;
 276 };
 277
 278 #define AGGR_CLEANUP         BIT(1)
 279 #define AGGR_ADDBA_COMPLETE  BIT(2)
 280 #define AGGR_ADDBA_PROGRESS  BIT(3)
 281
 282 struct ath_tx_control {
 283         struct ath_txq *txq;
 284         int if_id;
 285         enum ath9k_internal_frame_type frame_type;
 286         u8 paprd;
 287 };
 288
 289 #define ATH_TX_ERROR        0x01
 290 #define ATH_TX_XRETRY       0x02
 291 #define ATH_TX_BAR          0x04
 292
 293 struct ath_tx {
 294         u16 seq_no;
 295         u32 txqsetup;
 296         int hwq_map[WME_NUM_AC];
 297         spinlock_t txbuflock;
 298         struct list_head txbuf;
 299         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 300         struct ath_descdma txdma;
 301         int pending_frames[WME_NUM_AC];
 302 };
 303
 304 struct ath_rx_edma {
 305         struct sk_buff_head rx_fifo;
 306         struct sk_buff_head rx_buffers;
 307         u32 rx_fifo_hwsize;
 308 };
 309
 310 struct ath_rx {
 311         u8 defant;
 312         u8 rxotherant;
 313         u32 *rxlink;
 314         unsigned int rxfilter;
 315         spinlock_t rxflushlock;
 316         spinlock_t rxbuflock;
 317         struct list_head rxbuf;
 318         struct ath_descdma rxdma;
 319         struct ath_buf *rx_bufptr;
 320         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
 321 };
 322
 323 int ath_startrecv(struct ath_softc *sc);
 324 bool ath_stoprecv(struct ath_softc *sc);
 325 void ath_flushrecv(struct ath_softc *sc);
 326 u32 ath_calcrxfilter(struct ath_softc *sc);
 327 int ath_rx_init(struct ath_softc *sc, int nbufs);
 328 void ath_rx_cleanup(struct ath_softc *sc);
 329 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 330 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 331 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 332 int ath_tx_setup(struct ath_softc *sc, int haltype);
 333 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 334 void ath_draintxq(struct ath_softc *sc,
 335                      struct ath_txq *txq, bool retry_tx);
 336 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 337 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 338 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 339 int ath_tx_init(struct ath_softc *sc, int nbufs);
 340 void ath_tx_cleanup(struct ath_softc *sc);
 341 int ath_txq_update(struct ath_softc *sc, int qnum,
 342                    struct ath9k_tx_queue_info *q);
 343 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 344                  struct ath_tx_control *txctl);
 345 void ath_tx_tasklet(struct ath_softc *sc);
 346 void ath_tx_edma_tasklet(struct ath_softc *sc);
 347 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
 348 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 349                       u16 tid, u16 *ssn);
 350 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 351 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 352 void ath9k_enable_ps(struct ath_softc *sc);
 353
 354 /********/
 355 /* VIFs */
 356 /********/
 357
 358 struct ath_vif {
 359         int av_bslot;
 360         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 361         enum nl80211_iftype av_opmode;
 362         struct ath_buf *av_bcbuf;
 363         struct ath_tx_control av_btxctl;
 364         u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
 365 };
 366
 367 /*******************/
 368 /* Beacon Handling */
 369 /*******************/
 370
 371 /*
 372  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 373  * number of BSSIDs) if a given beacon does not go out even after waiting this
 374  * number of beacon intervals, the game's up.
 375  */
 376 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 377 #define ATH_BCBUF                       4
 378 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 379 #define ATH_DEFAULT_BMISS_LIMIT         10
 380 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 381
 382 struct ath_beacon_config {
 383         u16 beacon_interval;
 384         u16 listen_interval;
 385         u16 dtim_period;
 386         u16 bmiss_timeout;
 387         u8 dtim_count;
 388 };
 389
 390 struct ath_beacon {
 391         enum {
 392                 OK,             /* no change needed */
 393                 UPDATE,         /* update pending */
 394                 COMMIT          /* beacon sent, commit change */
 395         } updateslot;           /* slot time update fsm */
 396
 397         u32 beaconq;
 398         u32 bmisscnt;
 399         u32 ast_be_xmit;
 400         u64 bc_tstamp;
 401         struct ieee80211_vif *bslot[ATH_BCBUF];
 402         struct ath_wiphy *bslot_aphy[ATH_BCBUF];
 403         int slottime;
 404         int slotupdate;
 405         struct ath9k_tx_queue_info beacon_qi;
 406         struct ath_descdma bdma;
 407         struct ath_txq *cabq;
 408         struct list_head bbuf;
 409 };
 410
 411 void ath_beacon_tasklet(unsigned long data);
 412 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 413 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
 414 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 415 int ath_beaconq_config(struct ath_softc *sc);
 416
 417 /*******/
 418 /* ANI */
 419 /*******/
 420
 421 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 422 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 423 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 424 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
 425 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 426 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 427 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 428
 429 #define ATH_PAPRD_TIMEOUT       100 /* msecs */
 430
 431 void ath_hw_check(struct work_struct *work);
 432 void ath_paprd_calibrate(struct work_struct *work);
 433 void ath_ani_calibrate(unsigned long data);
 434
 435 /**********/
 436 /* BTCOEX */
 437 /**********/
 438
 439 struct ath_btcoex {
 440         bool hw_timer_enabled;
 441         spinlock_t btcoex_lock;
 442         struct timer_list period_timer; /* Timer for BT period */
 443         u32 bt_priority_cnt;
 444         unsigned long bt_priority_time;
 445         int bt_stomp_type; /* Types of BT stomping */
 446         u32 btcoex_no_stomp; /* in usec */
 447         u32 btcoex_period; /* in usec */
 448         u32 btscan_no_stomp; /* in usec */
 449         struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
 450 };
 451
 452 int ath_init_btcoex_timer(struct ath_softc *sc);
 453 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
 454 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 455
 456 /********************/
 457 /*   LED Control    */
 458 /********************/
 459
 460 #define ATH_LED_PIN_DEF                 1
 461 #define ATH_LED_PIN_9287                8
 462 #define ATH_LED_ON_DURATION_IDLE        350     /* in msecs */
 463 #define ATH_LED_OFF_DURATION_IDLE       250     /* in msecs */
 464
 465 enum ath_led_type {
 466         ATH_LED_RADIO,
 467         ATH_LED_ASSOC,
 468         ATH_LED_TX,
 469         ATH_LED_RX
 470 };
 471
 472 struct ath_led {
 473         struct ath_softc *sc;
 474         struct led_classdev led_cdev;
 475         enum ath_led_type led_type;
 476         char name[32];
 477         bool registered;
 478 };
 479
 480 void ath_init_leds(struct ath_softc *sc);
 481 void ath_deinit_leds(struct ath_softc *sc);
 482
 483 /* Antenna diversity/combining */
 484 #define ATH_ANT_RX_CURRENT_SHIFT 4
 485 #define ATH_ANT_RX_MAIN_SHIFT 2
 486 #define ATH_ANT_RX_MASK 0x3
 487
 488 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
 489 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
 490 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
 491 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
 492 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
 493 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
 494 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
 495
 496 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3
 497 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
 498 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
 499 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
 500 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
 501
 502 enum ath9k_ant_div_comb_lna_conf {
 503         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
 504         ATH_ANT_DIV_COMB_LNA2,
 505         ATH_ANT_DIV_COMB_LNA1,
 506         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
 507 };
 508
 509 struct ath_ant_comb {
 510         u16 count;
 511         u16 total_pkt_count;
 512         bool scan;
 513         bool scan_not_start;
 514         int main_total_rssi;
 515         int alt_total_rssi;
 516         int alt_recv_cnt;
 517         int main_recv_cnt;
 518         int rssi_lna1;
 519         int rssi_lna2;
 520         int rssi_add;
 521         int rssi_sub;
 522         int rssi_first;
 523         int rssi_second;
 524         int rssi_third;
 525         bool alt_good;
 526         int quick_scan_cnt;
 527         int main_conf;
 528         enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
 529         enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
 530         int first_bias;
 531         int second_bias;
 532         bool first_ratio;
 533         bool second_ratio;
 534         unsigned long scan_start_time;
 535 };
 536
 537 /********************/
 538 /* Main driver core */
 539 /********************/
 540
 541 /*
 542  * Default cache line size, in bytes.
 543  * Used when PCI device not fully initialized by bootrom/BIOS
 544 */
 545 #define DEFAULT_CACHELINE       32
 546 #define ATH_REGCLASSIDS_MAX     10
 547 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 548 #define ATH_MAX_SW_RETRIES      10
 549 #define ATH_CHAN_MAX            255
 550 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 551
 552 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 553 #define ATH_RATE_DUMMY_MARKER   0
 554
 555 #define SC_OP_INVALID                BIT(0)
 556 #define SC_OP_BEACONS                BIT(1)
 557 #define SC_OP_RXAGGR                 BIT(2)
 558 #define SC_OP_TXAGGR                 BIT(3)
 559 #define SC_OP_OFFCHANNEL             BIT(4)
 560 #define SC_OP_PREAMBLE_SHORT         BIT(5)
 561 #define SC_OP_PROTECT_ENABLE         BIT(6)
 562 #define SC_OP_RXFLUSH                BIT(7)
 563 #define SC_OP_LED_ASSOCIATED         BIT(8)
 564 #define SC_OP_LED_ON                 BIT(9)
 565 #define SC_OP_TSF_RESET              BIT(11)
 566 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 567 #define SC_OP_BT_SCAN                BIT(13)
 568 #define SC_OP_ANI_RUN                BIT(14)
 569
 570 /* Powersave flags */
 571 #define PS_WAIT_FOR_BEACON        BIT(0)
 572 #define PS_WAIT_FOR_CAB           BIT(1)
 573 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 574 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 575 #define PS_BEACON_SYNC            BIT(4)
 576 #define PS_NULLFUNC_COMPLETED     BIT(5)
 577 #define PS_ENABLED                BIT(6)
 578
 579 struct ath_wiphy;
 580 struct ath_rate_table;
 581
 582 struct ath_softc {
 583         struct ieee80211_hw *hw;
 584         struct device *dev;
 585
 586         spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
 587         struct ath_wiphy *pri_wiphy;
 588         struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
 589                                        * have NULL entries */
 590         int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
 591         int chan_idx;
 592         int chan_is_ht;
 593         struct ath_wiphy *next_wiphy;
 594         struct work_struct chan_work;
 595         int wiphy_select_failures;
 596         unsigned long wiphy_select_first_fail;
 597         struct delayed_work wiphy_work;
 598         unsigned long wiphy_scheduler_int;
 599         int wiphy_scheduler_index;
 600
 601         struct tasklet_struct intr_tq;
 602         struct tasklet_struct bcon_tasklet;
 603         struct ath_hw *sc_ah;
 604         void __iomem *mem;
 605         int irq;
 606         spinlock_t sc_resetlock;
 607         spinlock_t sc_serial_rw;
 608         spinlock_t sc_pm_lock;
 609         struct mutex mutex;
 610         struct work_struct paprd_work;
 611         struct work_struct hw_check_work;
 612         struct completion paprd_complete;
 613
 614         u32 intrstatus;
 615         u32 sc_flags; /* SC_OP_* */
 616         u16 ps_flags; /* PS_* */
 617         u16 curtxpow;
 618         u8 nbcnvifs;
 619         u16 nvifs;
 620         bool ps_enabled;
 621         bool ps_idle;
 622         unsigned long ps_usecount;
 623
 624         struct ath_config config;
 625         struct ath_rx rx;
 626         struct ath_tx tx;
 627         struct ath_beacon beacon;
 628         const struct ath_rate_table *cur_rate_table;
 629         enum wireless_mode cur_rate_mode;
 630         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 631
 632         struct ath_led radio_led;
 633         struct ath_led assoc_led;
 634         struct ath_led tx_led;
 635         struct ath_led rx_led;
 636         struct delayed_work ath_led_blink_work;
 637         int led_on_duration;
 638         int led_off_duration;
 639         int led_on_cnt;
 640         int led_off_cnt;
 641
 642         int beacon_interval;
 643
 644 #ifdef CONFIG_ATH9K_DEBUGFS
 645         struct ath9k_debug debug;
 646 #endif
 647         struct ath_beacon_config cur_beacon_conf;
 648         struct delayed_work tx_complete_work;
 649         struct ath_btcoex btcoex;
 650
 651         struct ath_descdma txsdma;
 652
 653         struct ath_ant_comb ant_comb;
 654 };
 655
 656 struct ath_wiphy {
 657         struct ath_softc *sc; /* shared for all virtual wiphys */
 658         struct ieee80211_hw *hw;
 659         struct ath9k_hw_cal_data caldata;
 660         enum ath_wiphy_state {
 661                 ATH_WIPHY_INACTIVE,
 662                 ATH_WIPHY_ACTIVE,
 663                 ATH_WIPHY_PAUSING,
 664                 ATH_WIPHY_PAUSED,
 665                 ATH_WIPHY_SCAN,
 666         } state;
 667         bool idle;
 668         int chan_idx;
 669         int chan_is_ht;
 670 };
 671
 672 void ath9k_tasklet(unsigned long data);
 673 int ath_reset(struct ath_softc *sc, bool retry_tx);
 674 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 675 int ath_cabq_update(struct ath_softc *);
 676
 677 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 678 {
 679         common->bus_ops->read_cachesize(common, csz);
 680 }
 681
 682 extern struct ieee80211_ops ath9k_ops;
 683 extern int modparam_nohwcrypt;
 684 extern int led_blink;
 685
 686 irqreturn_t ath_isr(int irq, void *dev);
 687 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
 688                     const struct ath_bus_ops *bus_ops);
 689 void ath9k_deinit_device(struct ath_softc *sc);
 690 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 691 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
 692                            struct ath9k_channel *ichan);
 693 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 694 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 695                     struct ath9k_channel *hchan);
 696
 697 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
 698 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
 699 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
 700
 701 #ifdef CONFIG_PCI
 702 int ath_pci_init(void);
 703 void ath_pci_exit(void);
 704 #else
 705 static inline int ath_pci_init(void) { return 0; };
 706 static inline void ath_pci_exit(void) {};
 707 #endif
 708
 709 #ifdef CONFIG_ATHEROS_AR71XX
 710 int ath_ahb_init(void);
 711 void ath_ahb_exit(void);
 712 #else
 713 static inline int ath_ahb_init(void) { return 0; };
 714 static inline void ath_ahb_exit(void) {};
 715 #endif
 716
 717 void ath9k_ps_wakeup(struct ath_softc *sc);
 718 void ath9k_ps_restore(struct ath_softc *sc);
 719
 720 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
 721 int ath9k_wiphy_add(struct ath_softc *sc);
 722 int ath9k_wiphy_del(struct ath_wiphy *aphy);
 723 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
 724 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
 725 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
 726 int ath9k_wiphy_select(struct ath_wiphy *aphy);
 727 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
 728 void ath9k_wiphy_chan_work(struct work_struct *work);
 729 bool ath9k_wiphy_started(struct ath_softc *sc);
 730 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
 731                                   struct ath_wiphy *selected);
 732 bool ath9k_wiphy_scanning(struct ath_softc *sc);
 733 void ath9k_wiphy_work(struct work_struct *work);
 734 bool ath9k_all_wiphys_idle(struct ath_softc *sc);
 735 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
 736
 737 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
 738 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
 739
 740 void ath_start_rfkill_poll(struct ath_softc *sc);
 741 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
 742
 743 #endif /* ATH9K_H */