drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/leds.h>
  24 #include <linux/completion.h>
  25
  26 #include "debug.h"
  27 #include "common.h"
  28 #include "mci.h"
  29 #include "dfs.h"
  30 #include "spectral.h"
  31
  32 struct ath_node;
  33 struct ath_rate_table;
  34
  35 extern struct ieee80211_ops ath9k_ops;
  36 extern int ath9k_modparam_nohwcrypt;
  37 extern int led_blink;
  38 extern bool is_ath9k_unloaded;
  39
  40 struct ath_config {
  41         u16 txpowlimit;
  42 };
  43
  44 /*************************/
  45 /* Descriptor Management */
  46 /*************************/
  47
  48 #define ATH_TXSTATUS_RING_SIZE 512
  49
  50 /* Macro to expand scalars to 64-bit objects */
  51 #define ito64(x) (sizeof(x) == 1) ?                     \
  52         (((unsigned long long int)(x)) & (0xff)) :      \
  53         (sizeof(x) == 2) ?                              \
  54         (((unsigned long long int)(x)) & 0xffff) :      \
  55         ((sizeof(x) == 4) ?                             \
  56          (((unsigned long long int)(x)) & 0xffffffff) : \
  57          (unsigned long long int)(x))
  58
  59 #define ATH_TXBUF_RESET(_bf) do {                               \
  60                 (_bf)->bf_lastbf = NULL;                        \
  61                 (_bf)->bf_next = NULL;                          \
  62                 memset(&((_bf)->bf_state), 0,                   \
  63                        sizeof(struct ath_buf_state));           \
  64         } while (0)
  65
  66 #define DS2PHYS(_dd, _ds)                                               \
  67         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
  68 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
  69 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
  70
  71 struct ath_descdma {
  72         void *dd_desc;
  73         dma_addr_t dd_desc_paddr;
  74         u32 dd_desc_len;
  75 };
  76
  77 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
  78                       struct list_head *head, const char *name,
  79                       int nbuf, int ndesc, bool is_tx);
  80
  81 /***********/
  82 /* RX / TX */
  83 /***********/
  84
  85 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
  86
  87 /* increment with wrap-around */
  88 #define INCR(_l, _sz)   do {                    \
  89                 (_l)++;                         \
  90                 (_l) &= ((_sz) - 1);            \
  91         } while (0)
  92
  93 #define ATH_RXBUF               512
  94 #define ATH_TXBUF               512
  95 #define ATH_TXBUF_RESERVE       5
  96 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
  97 #define ATH_TXMAXTRY            13
  98 #define ATH_MAX_SW_RETRIES      30
  99
 100 #define TID_TO_WME_AC(_tid)                             \
 101         ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE :   \
 102          (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK :   \
 103          (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI :   \
 104          IEEE80211_AC_VO)
 105
 106 #define ATH_AGGR_DELIM_SZ          4
 107 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 108 /* number of delimiters for encryption padding */
 109 #define ATH_AGGR_ENCRYPTDELIM      10
 110 /* minimum h/w qdepth to be sustained to maximize aggregation */
 111 #define ATH_AGGR_MIN_QDEPTH        2
 112 /* minimum h/w qdepth for non-aggregated traffic */
 113 #define ATH_NON_AGGR_MIN_QDEPTH    8
 114 #define ATH_TX_COMPLETE_POLL_INT   1000
 115 #define ATH_TXFIFO_DEPTH           8
 116 #define ATH_TX_ERROR               0x01
 117
 118 #define IEEE80211_SEQ_SEQ_SHIFT    4
 119 #define IEEE80211_SEQ_MAX          4096
 120 #define IEEE80211_WEP_IVLEN        3
 121 #define IEEE80211_WEP_KIDLEN       1
 122 #define IEEE80211_WEP_CRCLEN       4
 123 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 124                                     (IEEE80211_WEP_IVLEN +      \
 125                                      IEEE80211_WEP_KIDLEN +     \
 126                                      IEEE80211_WEP_CRCLEN))
 127
 128 /* return whether a bit at index _n in bitmap _bm is set
 129  * _sz is the size of the bitmap  */
 130 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 131                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 132
 133 /* return block-ack bitmap index given sequence and starting sequence */
 134 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 135
 136 /* return the seqno for _start + _offset */
 137 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
 138
 139 /* returns delimiter padding required given the packet length */
 140 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 141        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
 142         DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 143
 144 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 145         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 146
 147 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 148
 149 #define IS_HT_RATE(rate)   (rate & 0x80)
 150 #define IS_CCK_RATE(rate)  ((rate >= 0x18) && (rate <= 0x1e))
 151 #define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf))
 152
 153 struct ath_txq {
 154         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
 155         u32 axq_qnum; /* ath9k hardware queue number */
 156         void *axq_link;
 157         struct list_head axq_q;
 158         spinlock_t axq_lock;
 159         u32 axq_depth;
 160         u32 axq_ampdu_depth;
 161         bool stopped;
 162         bool axq_tx_inprogress;
 163         struct list_head axq_acq;
 164         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
 165         u8 txq_headidx;
 166         u8 txq_tailidx;
 167         int pending_frames;
 168         struct sk_buff_head complete_q;
 169 };
 170
 171 struct ath_atx_ac {
 172         struct ath_txq *txq;
 173         struct list_head list;
 174         struct list_head tid_q;
 175         bool clear_ps_filter;
 176         bool sched;
 177 };
 178
 179 struct ath_frame_info {
 180         struct ath_buf *bf;
 181         int framelen;
 182         enum ath9k_key_type keytype;
 183         u8 keyix;
 184         u8 rtscts_rate;
 185         u8 retries : 7;
 186         u8 baw_tracked : 1;
 187 };
 188
 189 struct ath_rxbuf {
 190         struct list_head list;
 191         struct sk_buff *bf_mpdu;
 192         void *bf_desc;
 193         dma_addr_t bf_daddr;
 194         dma_addr_t bf_buf_addr;
 195 };
 196
 197 /**
 198  * enum buffer_type - Buffer type flags
 199  *
 200  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
 201  * @BUF_AGGR: Indicates whether the buffer can be aggregated
 202  *      (used in aggregation scheduling)
 203  */
 204 enum buffer_type {
 205         BUF_AMPDU               = BIT(0),
 206         BUF_AGGR                = BIT(1),
 207 };
 208
 209 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 210 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 211
 212 struct ath_buf_state {
 213         u8 bf_type;
 214         u8 bfs_paprd;
 215         u8 ndelim;
 216         bool stale;
 217         u16 seqno;
 218         unsigned long bfs_paprd_timestamp;
 219 };
 220
 221 struct ath_buf {
 222         struct list_head list;
 223         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 224                                            an aggregate) */
 225         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 226         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 227         void *bf_desc;                  /* virtual addr of desc */
 228         dma_addr_t bf_daddr;            /* physical addr of desc */
 229         dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
 230         struct ieee80211_tx_rate rates[4];
 231         struct ath_buf_state bf_state;
 232 };
 233
 234 struct ath_atx_tid {
 235         struct list_head list;
 236         struct sk_buff_head buf_q;
 237         struct sk_buff_head retry_q;
 238         struct ath_node *an;
 239         struct ath_atx_ac *ac;
 240         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
 241         u16 seq_start;
 242         u16 seq_next;
 243         u16 baw_size;
 244         u8 tidno;
 245         int baw_head;   /* first un-acked tx buffer */
 246         int baw_tail;   /* next unused tx buffer slot */
 247
 248         s8 bar_index;
 249         bool sched;
 250         bool paused;
 251         bool active;
 252 };
 253
 254 struct ath_node {
 255         struct ath_softc *sc;
 256         struct ieee80211_sta *sta; /* station struct we're part of */
 257         struct ieee80211_vif *vif; /* interface with which we're associated */
 258         struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
 259         struct ath_atx_ac ac[IEEE80211_NUM_ACS];
 260
 261         u16 maxampdu;
 262         u8 mpdudensity;
 263         s8 ps_key;
 264
 265         bool sleeping;
 266         bool no_ps_filter;
 267
 268 #ifdef CONFIG_ATH9K_STATION_STATISTICS
 269         struct ath_rx_rate_stats rx_rate_stats;
 270 #endif
 271 };
 272
 273 struct ath_tx_control {
 274         struct ath_txq *txq;
 275         struct ath_node *an;
 276         u8 paprd;
 277         struct ieee80211_sta *sta;
 278 };
 279
 280
 281 /**
 282  * @txq_map:  Index is mac80211 queue number.  This is
 283  *  not necessarily the same as the hardware queue number
 284  *  (axq_qnum).
 285  */
 286 struct ath_tx {
 287         u16 seq_no;
 288         u32 txqsetup;
 289         spinlock_t txbuflock;
 290         struct list_head txbuf;
 291         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 292         struct ath_descdma txdma;
 293         struct ath_txq *txq_map[IEEE80211_NUM_ACS];
 294         struct ath_txq *uapsdq;
 295         u32 txq_max_pending[IEEE80211_NUM_ACS];
 296         u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
 297 };
 298
 299 struct ath_rx_edma {
 300         struct sk_buff_head rx_fifo;
 301         u32 rx_fifo_hwsize;
 302 };
 303
 304 struct ath_rx {
 305         u8 defant;
 306         u8 rxotherant;
 307         bool discard_next;
 308         u32 *rxlink;
 309         u32 num_pkts;
 310         unsigned int rxfilter;
 311         struct list_head rxbuf;
 312         struct ath_descdma rxdma;
 313         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
 314
 315         struct ath_rxbuf *buf_hold;
 316         struct sk_buff *frag;
 317
 318         u32 ampdu_ref;
 319 };
 320
 321 int ath_startrecv(struct ath_softc *sc);
 322 bool ath_stoprecv(struct ath_softc *sc);
 323 u32 ath_calcrxfilter(struct ath_softc *sc);
 324 int ath_rx_init(struct ath_softc *sc, int nbufs);
 325 void ath_rx_cleanup(struct ath_softc *sc);
 326 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 327 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 328 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
 329 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
 330 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
 331 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 332 bool ath_drain_all_txq(struct ath_softc *sc);
 333 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
 334 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 335 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 336 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 337 int ath_tx_init(struct ath_softc *sc, int nbufs);
 338 int ath_txq_update(struct ath_softc *sc, int qnum,
 339                    struct ath9k_tx_queue_info *q);
 340 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
 341 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 342                  struct ath_tx_control *txctl);
 343 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 344                  struct sk_buff *skb);
 345 void ath_tx_tasklet(struct ath_softc *sc);
 346 void ath_tx_edma_tasklet(struct ath_softc *sc);
 347 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 348                       u16 tid, u16 *ssn);
 349 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 350 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 351
 352 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
 353 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
 354                        struct ath_node *an);
 355 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
 356                                    struct ieee80211_sta *sta,
 357                                    u16 tids, int nframes,
 358                                    enum ieee80211_frame_release_type reason,
 359                                    bool more_data);
 360
 361 /********/
 362 /* VIFs */
 363 /********/
 364
 365 struct ath_vif {
 366         struct ath_node mcast_node;
 367         int av_bslot;
 368         bool primary_sta_vif;
 369         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 370         struct ath_buf *av_bcbuf;
 371 };
 372
 373 struct ath9k_vif_iter_data {
 374         u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
 375         u8 mask[ETH_ALEN]; /* bssid mask */
 376         bool has_hw_macaddr;
 377
 378         int naps;      /* number of AP vifs */
 379         int nmeshes;   /* number of mesh vifs */
 380         int nstations; /* number of station vifs */
 381         int nwds;      /* number of WDS vifs */
 382         int nadhocs;   /* number of adhoc vifs */
 383 };
 384
 385 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
 386                                struct ieee80211_vif *vif,
 387                                struct ath9k_vif_iter_data *iter_data);
 388
 389 /*******************/
 390 /* Beacon Handling */
 391 /*******************/
 392
 393 /*
 394  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 395  * number of BSSIDs) if a given beacon does not go out even after waiting this
 396  * number of beacon intervals, the game's up.
 397  */
 398 #define BSTUCK_THRESH                   9
 399 #define ATH_BCBUF                       8
 400 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 401 #define ATH_DEFAULT_BMISS_LIMIT         10
 402 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 403
 404 #define TSF_TO_TU(_h,_l) \
 405         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
 406
 407 struct ath_beacon_config {
 408         int beacon_interval;
 409         u16 listen_interval;
 410         u16 dtim_period;
 411         u16 bmiss_timeout;
 412         u8 dtim_count;
 413         bool enable_beacon;
 414         bool ibss_creator;
 415 };
 416
 417 struct ath_beacon {
 418         enum {
 419                 OK,             /* no change needed */
 420                 UPDATE,         /* update pending */
 421                 COMMIT          /* beacon sent, commit change */
 422         } updateslot;           /* slot time update fsm */
 423
 424         u32 beaconq;
 425         u32 bmisscnt;
 426         u32 bc_tstamp;
 427         struct ieee80211_vif *bslot[ATH_BCBUF];
 428         int slottime;
 429         int slotupdate;
 430         struct ath9k_tx_queue_info beacon_qi;
 431         struct ath_descdma bdma;
 432         struct ath_txq *cabq;
 433         struct list_head bbuf;
 434
 435         bool tx_processed;
 436         bool tx_last;
 437 };
 438
 439 void ath9k_beacon_tasklet(unsigned long data);
 440 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
 441                          u32 changed);
 442 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
 443 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
 444 void ath9k_set_beacon(struct ath_softc *sc);
 445 bool ath9k_csa_is_finished(struct ath_softc *sc);
 446
 447 /*******************/
 448 /* Link Monitoring */
 449 /*******************/
 450
 451 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 452 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 453 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 454 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
 455 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 456 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 457 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 458 #define ATH_ANI_MAX_SKIP_COUNT    10
 459 #define ATH_PAPRD_TIMEOUT         100 /* msecs */
 460 #define ATH_PLL_WORK_INTERVAL     100
 461
 462 void ath_tx_complete_poll_work(struct work_struct *work);
 463 void ath_reset_work(struct work_struct *work);
 464 bool ath_hw_check(struct ath_softc *sc);
 465 void ath_hw_pll_work(struct work_struct *work);
 466 void ath_paprd_calibrate(struct work_struct *work);
 467 void ath_ani_calibrate(unsigned long data);
 468 void ath_start_ani(struct ath_softc *sc);
 469 void ath_stop_ani(struct ath_softc *sc);
 470 void ath_check_ani(struct ath_softc *sc);
 471 int ath_update_survey_stats(struct ath_softc *sc);
 472 void ath_update_survey_nf(struct ath_softc *sc, int channel);
 473 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
 474 void ath_ps_full_sleep(unsigned long data);
 475
 476 /**********/
 477 /* BTCOEX */
 478 /**********/
 479
 480 #define ATH_DUMP_BTCOEX(_s, _val)                               \
 481         do {                                                    \
 482                 len += scnprintf(buf + len, size - len,         \
 483                                  "%20s : %10d\n", _s, (_val));  \
 484         } while (0)
 485
 486 enum bt_op_flags {
 487         BT_OP_PRIORITY_DETECTED,
 488         BT_OP_SCAN,
 489 };
 490
 491 struct ath_btcoex {
 492         spinlock_t btcoex_lock;
 493         struct timer_list period_timer; /* Timer for BT period */
 494         struct timer_list no_stomp_timer;
 495         u32 bt_priority_cnt;
 496         unsigned long bt_priority_time;
 497         unsigned long op_flags;
 498         int bt_stomp_type; /* Types of BT stomping */
 499         u32 btcoex_no_stomp; /* in msec */
 500         u32 btcoex_period; /* in msec */
 501         u32 btscan_no_stomp; /* in msec */
 502         u32 duty_cycle;
 503         u32 bt_wait_time;
 504         int rssi_count;
 505         struct ath_mci_profile mci;
 506         u8 stomp_audio;
 507 };
 508
 509 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 510 int ath9k_init_btcoex(struct ath_softc *sc);
 511 void ath9k_deinit_btcoex(struct ath_softc *sc);
 512 void ath9k_start_btcoex(struct ath_softc *sc);
 513 void ath9k_stop_btcoex(struct ath_softc *sc);
 514 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
 515 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 516 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
 517 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
 518 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
 519 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
 520 #else
 521 static inline int ath9k_init_btcoex(struct ath_softc *sc)
 522 {
 523         return 0;
 524 }
 525 static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
 526 {
 527 }
 528 static inline void ath9k_start_btcoex(struct ath_softc *sc)
 529 {
 530 }
 531 static inline void ath9k_stop_btcoex(struct ath_softc *sc)
 532 {
 533 }
 534 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
 535                                                  u32 status)
 536 {
 537 }
 538 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
 539                                           u32 max_4ms_framelen)
 540 {
 541         return 0;
 542 }
 543 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
 544 {
 545 }
 546 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
 547 {
 548         return 0;
 549 }
 550 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
 551
 552 /********************/
 553 /*   LED Control    */
 554 /********************/
 555
 556 #define ATH_LED_PIN_DEF                 1
 557 #define ATH_LED_PIN_9287                8
 558 #define ATH_LED_PIN_9300                10
 559 #define ATH_LED_PIN_9485                6
 560 #define ATH_LED_PIN_9462                4
 561
 562 #ifdef CONFIG_MAC80211_LEDS
 563 void ath_init_leds(struct ath_softc *sc);
 564 void ath_deinit_leds(struct ath_softc *sc);
 565 void ath_fill_led_pin(struct ath_softc *sc);
 566 #else
 567 static inline void ath_init_leds(struct ath_softc *sc)
 568 {
 569 }
 570
 571 static inline void ath_deinit_leds(struct ath_softc *sc)
 572 {
 573 }
 574 static inline void ath_fill_led_pin(struct ath_softc *sc)
 575 {
 576 }
 577 #endif
 578
 579 /************************/
 580 /* Wake on Wireless LAN */
 581 /************************/
 582
 583 struct ath9k_wow_pattern {
 584         u8 pattern_bytes[MAX_PATTERN_SIZE];
 585         u8 mask_bytes[MAX_PATTERN_SIZE];
 586         u32 pattern_len;
 587 };
 588
 589 #ifdef CONFIG_ATH9K_WOW
 590 void ath9k_init_wow(struct ieee80211_hw *hw);
 591 int ath9k_suspend(struct ieee80211_hw *hw,
 592                   struct cfg80211_wowlan *wowlan);
 593 int ath9k_resume(struct ieee80211_hw *hw);
 594 void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
 595 #else
 596 static inline void ath9k_init_wow(struct ieee80211_hw *hw)
 597 {
 598 }
 599 static inline int ath9k_suspend(struct ieee80211_hw *hw,
 600                                 struct cfg80211_wowlan *wowlan)
 601 {
 602         return 0;
 603 }
 604 static inline int ath9k_resume(struct ieee80211_hw *hw)
 605 {
 606         return 0;
 607 }
 608 static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
 609 {
 610 }
 611 #endif /* CONFIG_ATH9K_WOW */
 612
 613 /*******************************/
 614 /* Antenna diversity/combining */
 615 /*******************************/
 616
 617 #define ATH_ANT_RX_CURRENT_SHIFT 4
 618 #define ATH_ANT_RX_MAIN_SHIFT 2
 619 #define ATH_ANT_RX_MASK 0x3
 620
 621 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
 622 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
 623 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
 624 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
 625 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
 626 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
 627 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
 628 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50
 629 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50
 630
 631 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
 632 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
 633 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
 634
 635 struct ath_ant_comb {
 636         u16 count;
 637         u16 total_pkt_count;
 638         bool scan;
 639         bool scan_not_start;
 640         int main_total_rssi;
 641         int alt_total_rssi;
 642         int alt_recv_cnt;
 643         int main_recv_cnt;
 644         int rssi_lna1;
 645         int rssi_lna2;
 646         int rssi_add;
 647         int rssi_sub;
 648         int rssi_first;
 649         int rssi_second;
 650         int rssi_third;
 651         int ant_ratio;
 652         int ant_ratio2;
 653         bool alt_good;
 654         int quick_scan_cnt;
 655         enum ath9k_ant_div_comb_lna_conf main_conf;
 656         enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
 657         enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
 658         bool first_ratio;
 659         bool second_ratio;
 660         unsigned long scan_start_time;
 661
 662         /*
 663          * Card-specific config values.
 664          */
 665         int low_rssi_thresh;
 666         int fast_div_bias;
 667 };
 668
 669 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
 670
 671 /********************/
 672 /* Main driver core */
 673 /********************/
 674
 675 #define ATH9K_PCI_CUS198          0x0001
 676 #define ATH9K_PCI_CUS230          0x0002
 677 #define ATH9K_PCI_CUS217          0x0004
 678 #define ATH9K_PCI_CUS252          0x0008
 679 #define ATH9K_PCI_WOW             0x0010
 680 #define ATH9K_PCI_BT_ANT_DIV      0x0020
 681 #define ATH9K_PCI_D3_L1_WAR       0x0040
 682 #define ATH9K_PCI_AR9565_1ANT     0x0080
 683 #define ATH9K_PCI_AR9565_2ANT     0x0100
 684 #define ATH9K_PCI_NO_PLL_PWRSAVE  0x0200
 685 #define ATH9K_PCI_KILLER          0x0400
 686
 687 /*
 688  * Default cache line size, in bytes.
 689  * Used when PCI device not fully initialized by bootrom/BIOS
 690 */
 691 #define DEFAULT_CACHELINE       32
 692 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 693 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 694
 695 enum sc_op_flags {
 696         SC_OP_INVALID,
 697         SC_OP_BEACONS,
 698         SC_OP_ANI_RUN,
 699         SC_OP_PRIM_STA_VIF,
 700         SC_OP_HW_RESET,
 701         SC_OP_SCANNING,
 702 };
 703
 704 /* Powersave flags */
 705 #define PS_WAIT_FOR_BEACON        BIT(0)
 706 #define PS_WAIT_FOR_CAB           BIT(1)
 707 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 708 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 709 #define PS_BEACON_SYNC            BIT(4)
 710 #define PS_WAIT_FOR_ANI           BIT(5)
 711
 712 struct ath_softc {
 713         struct ieee80211_hw *hw;
 714         struct device *dev;
 715
 716         struct survey_info *cur_survey;
 717         struct survey_info survey[ATH9K_NUM_CHANNELS];
 718
 719         struct tasklet_struct intr_tq;
 720         struct tasklet_struct bcon_tasklet;
 721         struct ath_hw *sc_ah;
 722         void __iomem *mem;
 723         int irq;
 724         spinlock_t sc_serial_rw;
 725         spinlock_t sc_pm_lock;
 726         spinlock_t sc_pcu_lock;
 727         struct mutex mutex;
 728         struct work_struct paprd_work;
 729         struct work_struct hw_reset_work;
 730         struct completion paprd_complete;
 731         wait_queue_head_t tx_wait;
 732
 733         unsigned long sc_flags;
 734         unsigned long driver_data;
 735
 736         u32 intrstatus;
 737         u16 ps_flags; /* PS_* */
 738         u16 curtxpow;
 739         bool ps_enabled;
 740         bool ps_idle;
 741         short nbcnvifs;
 742         short nvifs;
 743         unsigned long ps_usecount;
 744
 745         struct ath_config config;
 746         struct ath_rx rx;
 747         struct ath_tx tx;
 748         struct ath_beacon beacon;
 749         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 750
 751 #ifdef CONFIG_MAC80211_LEDS
 752         bool led_registered;
 753         char led_name[32];
 754         struct led_classdev led_cdev;
 755 #endif
 756
 757         struct ath9k_hw_cal_data caldata;
 758         int last_rssi;
 759
 760 #ifdef CONFIG_ATH9K_DEBUGFS
 761         struct ath9k_debug debug;
 762 #endif
 763         struct ath_beacon_config cur_beacon_conf;
 764         struct delayed_work tx_complete_work;
 765         struct delayed_work hw_pll_work;
 766         struct timer_list sleep_timer;
 767
 768 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 769         struct ath_btcoex btcoex;
 770         struct ath_mci_coex mci_coex;
 771         struct work_struct mci_work;
 772 #endif
 773
 774         struct ath_descdma txsdma;
 775         struct ieee80211_vif *csa_vif;
 776
 777         struct ath_ant_comb ant_comb;
 778         u8 ant_tx, ant_rx;
 779         struct dfs_pattern_detector *dfs_detector;
 780         u32 wow_enabled;
 781         /* relay(fs) channel for spectral scan */
 782         struct rchan *rfs_chan_spec_scan;
 783         enum spectral_mode spectral_mode;
 784         struct ath_spec_scan spec_config;
 785
 786         struct ieee80211_vif *tx99_vif;
 787         struct sk_buff *tx99_skb;
 788         bool tx99_state;
 789         s16 tx99_power;
 790
 791 #ifdef CONFIG_ATH9K_WOW
 792         atomic_t wow_got_bmiss_intr;
 793         atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
 794         u32 wow_intr_before_sleep;
 795 #endif
 796 };
 797
 798 /********/
 799 /* TX99 */
 800 /********/
 801
 802 #ifdef CONFIG_ATH9K_TX99
 803 void ath9k_tx99_init_debug(struct ath_softc *sc);
 804 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
 805                     struct ath_tx_control *txctl);
 806 #else
 807 static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
 808 {
 809 }
 810 static inline int ath9k_tx99_send(struct ath_softc *sc,
 811                                   struct sk_buff *skb,
 812                                   struct ath_tx_control *txctl)
 813 {
 814         return 0;
 815 }
 816 #endif /* CONFIG_ATH9K_TX99 */
 817
 818 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 819 {
 820         common->bus_ops->read_cachesize(common, csz);
 821 }
 822
 823 void ath9k_tasklet(unsigned long data);
 824 int ath_cabq_update(struct ath_softc *);
 825 u8 ath9k_parse_mpdudensity(u8 mpdudensity);
 826 irqreturn_t ath_isr(int irq, void *dev);
 827 int ath_reset(struct ath_softc *sc);
 828 void ath_cancel_work(struct ath_softc *sc);
 829 void ath_restart_work(struct ath_softc *sc);
 830 int ath9k_init_device(u16 devid, struct ath_softc *sc,
 831                     const struct ath_bus_ops *bus_ops);
 832 void ath9k_deinit_device(struct ath_softc *sc);
 833 void ath9k_reload_chainmask_settings(struct ath_softc *sc);
 834 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 835 void ath_start_rfkill_poll(struct ath_softc *sc);
 836 void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
 837 void ath9k_ps_wakeup(struct ath_softc *sc);
 838 void ath9k_ps_restore(struct ath_softc *sc);
 839
 840 #ifdef CONFIG_ATH9K_PCI
 841 int ath_pci_init(void);
 842 void ath_pci_exit(void);
 843 #else
 844 static inline int ath_pci_init(void) { return 0; };
 845 static inline void ath_pci_exit(void) {};
 846 #endif
 847
 848 #ifdef CONFIG_ATH9K_AHB
 849 int ath_ahb_init(void);
 850 void ath_ahb_exit(void);
 851 #else
 852 static inline int ath_ahb_init(void) { return 0; };
 853 static inline void ath_ahb_exit(void) {};
 854 #endif
 855
 856 #endif /* ATH9K_H */