drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <linux/leds.h>
  23 #include <linux/completion.h>
  24
  25 #include "debug.h"
  26 #include "common.h"
  27
  28 /*
  29  * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
  30  * should rely on this file or its contents.
  31  */
  32
  33 struct ath_node;
  34
  35 /* Macro to expand scalars to 64-bit objects */
  36
  37 #define ito64(x) (sizeof(x) == 1) ?                     \
  38         (((unsigned long long int)(x)) & (0xff)) :      \
  39         (sizeof(x) == 2) ?                              \
  40         (((unsigned long long int)(x)) & 0xffff) :      \
  41         ((sizeof(x) == 4) ?                             \
  42          (((unsigned long long int)(x)) & 0xffffffff) : \
  43          (unsigned long long int)(x))
  44
  45 /* increment with wrap-around */
  46 #define INCR(_l, _sz)   do {                    \
  47                 (_l)++;                         \
  48                 (_l) &= ((_sz) - 1);            \
  49         } while (0)
  50
  51 /* decrement with wrap-around */
  52 #define DECR(_l,  _sz)  do {                    \
  53                 (_l)--;                         \
  54                 (_l) &= ((_sz) - 1);            \
  55         } while (0)
  56
  57 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  58
  59 #define TSF_TO_TU(_h,_l) \
  60         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  61
  62 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  63
  64 struct ath_config {
  65         u16 txpowlimit;
  66         u8 cabqReadytime;
  67 };
  68
  69 /*************************/
  70 /* Descriptor Management */
  71 /*************************/
  72
  73 #define ATH_TXBUF_RESET(_bf) do {                               \
  74                 (_bf)->bf_stale = false;                        \
  75                 (_bf)->bf_lastbf = NULL;                        \
  76                 (_bf)->bf_next = NULL;                          \
  77                 memset(&((_bf)->bf_state), 0,                   \
  78                        sizeof(struct ath_buf_state));           \
  79         } while (0)
  80
  81 #define ATH_RXBUF_RESET(_bf) do {               \
  82                 (_bf)->bf_stale = false;        \
  83         } while (0)
  84
  85 /**
  86  * enum buffer_type - Buffer type flags
  87  *
  88  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  89  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  90  *      (used in aggregation scheduling)
  91  * @BUF_XRETRY: To denote excessive retries of the buffer
  92  */
  93 enum buffer_type {
  94         BUF_AMPDU               = BIT(0),
  95         BUF_AGGR                = BIT(1),
  96         BUF_XRETRY              = BIT(2),
  97 };
  98
  99 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 100 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 101 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 102
 103 #define ATH_TXSTATUS_RING_SIZE 64
 104
 105 struct ath_descdma {
 106         void *dd_desc;
 107         dma_addr_t dd_desc_paddr;
 108         u32 dd_desc_len;
 109         struct ath_buf *dd_bufptr;
 110 };
 111
 112 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 113                       struct list_head *head, const char *name,
 114                       int nbuf, int ndesc, bool is_tx);
 115 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 116                          struct list_head *head);
 117
 118 /***********/
 119 /* RX / TX */
 120 /***********/
 121
 122 #define ATH_RXBUF               512
 123 #define ATH_TXBUF               512
 124 #define ATH_TXBUF_RESERVE       5
 125 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 126 #define ATH_TXMAXTRY            13
 127
 128 #define TID_TO_WME_AC(_tid)                             \
 129         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 130          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 131          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 132          WME_AC_VO)
 133
 134 #define ATH_AGGR_DELIM_SZ          4
 135 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 136 /* number of delimiters for encryption padding */
 137 #define ATH_AGGR_ENCRYPTDELIM      10
 138 /* minimum h/w qdepth to be sustained to maximize aggregation */
 139 #define ATH_AGGR_MIN_QDEPTH        2
 140 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 141
 142 #define IEEE80211_SEQ_SEQ_SHIFT    4
 143 #define IEEE80211_SEQ_MAX          4096
 144 #define IEEE80211_WEP_IVLEN        3
 145 #define IEEE80211_WEP_KIDLEN       1
 146 #define IEEE80211_WEP_CRCLEN       4
 147 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 148                                     (IEEE80211_WEP_IVLEN +      \
 149                                      IEEE80211_WEP_KIDLEN +     \
 150                                      IEEE80211_WEP_CRCLEN))
 151
 152 /* return whether a bit at index _n in bitmap _bm is set
 153  * _sz is the size of the bitmap  */
 154 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 155                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 156
 157 /* return block-ack bitmap index given sequence and starting sequence */
 158 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 159
 160 /* returns delimiter padding required given the packet length */
 161 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 162        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
 163         DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 164
 165 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 166         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 167
 168 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 169
 170 #define ATH_TX_COMPLETE_POLL_INT        1000
 171
 172 enum ATH_AGGR_STATUS {
 173         ATH_AGGR_DONE,
 174         ATH_AGGR_BAW_CLOSED,
 175         ATH_AGGR_LIMITED,
 176 };
 177
 178 #define ATH_TXFIFO_DEPTH 8
 179 struct ath_txq {
 180         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
 181         u32 axq_qnum; /* ath9k hardware queue number */
 182         u32 *axq_link;
 183         struct list_head axq_q;
 184         spinlock_t axq_lock;
 185         u32 axq_depth;
 186         u32 axq_ampdu_depth;
 187         bool stopped;
 188         bool axq_tx_inprogress;
 189         struct list_head axq_acq;
 190         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
 191         struct list_head txq_fifo_pending;
 192         u8 txq_headidx;
 193         u8 txq_tailidx;
 194         int pending_frames;
 195 };
 196
 197 struct ath_atx_ac {
 198         struct ath_txq *txq;
 199         int sched;
 200         struct list_head list;
 201         struct list_head tid_q;
 202         bool clear_ps_filter;
 203 };
 204
 205 struct ath_frame_info {
 206         int framelen;
 207         u32 keyix;
 208         enum ath9k_key_type keytype;
 209         u8 retries;
 210         u16 seqno;
 211 };
 212
 213 struct ath_buf_state {
 214         u8 bf_type;
 215         u8 bfs_paprd;
 216         unsigned long bfs_paprd_timestamp;
 217         enum ath9k_internal_frame_type bfs_ftype;
 218 };
 219
 220 struct ath_buf {
 221         struct list_head list;
 222         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 223                                            an aggregate) */
 224         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 225         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 226         void *bf_desc;                  /* virtual addr of desc */
 227         dma_addr_t bf_daddr;            /* physical addr of desc */
 228         dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
 229         bool bf_stale;
 230         u16 bf_flags;
 231         struct ath_buf_state bf_state;
 232 };
 233
 234 struct ath_atx_tid {
 235         struct list_head list;
 236         struct list_head buf_q;
 237         struct ath_node *an;
 238         struct ath_atx_ac *ac;
 239         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
 240         u16 seq_start;
 241         u16 seq_next;
 242         u16 baw_size;
 243         int tidno;
 244         int baw_head;   /* first un-acked tx buffer */
 245         int baw_tail;   /* next unused tx buffer slot */
 246         int sched;
 247         int paused;
 248         u8 state;
 249 };
 250
 251 struct ath_node {
 252 #ifdef CONFIG_ATH9K_DEBUGFS
 253         struct list_head list; /* for sc->nodes */
 254         struct ieee80211_sta *sta; /* station struct we're part of */
 255 #endif
 256         struct ath_atx_tid tid[WME_NUM_TID];
 257         struct ath_atx_ac ac[WME_NUM_AC];
 258         int ps_key;
 259
 260         u16 maxampdu;
 261         u8 mpdudensity;
 262
 263         bool sleeping;
 264 };
 265
 266 #define AGGR_CLEANUP         BIT(1)
 267 #define AGGR_ADDBA_COMPLETE  BIT(2)
 268 #define AGGR_ADDBA_PROGRESS  BIT(3)
 269
 270 struct ath_tx_control {
 271         struct ath_txq *txq;
 272         struct ath_node *an;
 273         int if_id;
 274         enum ath9k_internal_frame_type frame_type;
 275         u8 paprd;
 276 };
 277
 278 #define ATH_TX_ERROR        0x01
 279 #define ATH_TX_XRETRY       0x02
 280 #define ATH_TX_BAR          0x04
 281
 282 /**
 283  * @txq_map:  Index is mac80211 queue number.  This is
 284  *  not necessarily the same as the hardware queue number
 285  *  (axq_qnum).
 286  */
 287 struct ath_tx {
 288         u16 seq_no;
 289         u32 txqsetup;
 290         spinlock_t txbuflock;
 291         struct list_head txbuf;
 292         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 293         struct ath_descdma txdma;
 294         struct ath_txq *txq_map[WME_NUM_AC];
 295 };
 296
 297 struct ath_rx_edma {
 298         struct sk_buff_head rx_fifo;
 299         struct sk_buff_head rx_buffers;
 300         u32 rx_fifo_hwsize;
 301 };
 302
 303 struct ath_rx {
 304         u8 defant;
 305         u8 rxotherant;
 306         u32 *rxlink;
 307         unsigned int rxfilter;
 308         spinlock_t rxbuflock;
 309         struct list_head rxbuf;
 310         struct ath_descdma rxdma;
 311         struct ath_buf *rx_bufptr;
 312         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
 313
 314         struct sk_buff *frag;
 315 };
 316
 317 int ath_startrecv(struct ath_softc *sc);
 318 bool ath_stoprecv(struct ath_softc *sc);
 319 void ath_flushrecv(struct ath_softc *sc);
 320 u32 ath_calcrxfilter(struct ath_softc *sc);
 321 int ath_rx_init(struct ath_softc *sc, int nbufs);
 322 void ath_rx_cleanup(struct ath_softc *sc);
 323 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 324 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 325 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 326 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 327 void ath_draintxq(struct ath_softc *sc,
 328                      struct ath_txq *txq, bool retry_tx);
 329 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 330 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 331 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 332 int ath_tx_init(struct ath_softc *sc, int nbufs);
 333 void ath_tx_cleanup(struct ath_softc *sc);
 334 int ath_txq_update(struct ath_softc *sc, int qnum,
 335                    struct ath9k_tx_queue_info *q);
 336 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 337                  struct ath_tx_control *txctl);
 338 void ath_tx_tasklet(struct ath_softc *sc);
 339 void ath_tx_edma_tasklet(struct ath_softc *sc);
 340 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 341                       u16 tid, u16 *ssn);
 342 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 343 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 344
 345 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
 346 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an);
 347
 348 /********/
 349 /* VIFs */
 350 /********/
 351
 352 struct ath_vif {
 353         int av_bslot;
 354         bool is_bslot_active, primary_sta_vif;
 355         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 356         struct ath_buf *av_bcbuf;
 357 };
 358
 359 /*******************/
 360 /* Beacon Handling */
 361 /*******************/
 362
 363 /*
 364  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 365  * number of BSSIDs) if a given beacon does not go out even after waiting this
 366  * number of beacon intervals, the game's up.
 367  */
 368 #define BSTUCK_THRESH                   9
 369 #define ATH_BCBUF                       4
 370 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 371 #define ATH_DEFAULT_BMISS_LIMIT         10
 372 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 373
 374 struct ath_beacon_config {
 375         int beacon_interval;
 376         u16 listen_interval;
 377         u16 dtim_period;
 378         u16 bmiss_timeout;
 379         u8 dtim_count;
 380 };
 381
 382 struct ath_beacon {
 383         enum {
 384                 OK,             /* no change needed */
 385                 UPDATE,         /* update pending */
 386                 COMMIT          /* beacon sent, commit change */
 387         } updateslot;           /* slot time update fsm */
 388
 389         u32 beaconq;
 390         u32 bmisscnt;
 391         u32 ast_be_xmit;
 392         u32 bc_tstamp;
 393         struct ieee80211_vif *bslot[ATH_BCBUF];
 394         int slottime;
 395         int slotupdate;
 396         struct ath9k_tx_queue_info beacon_qi;
 397         struct ath_descdma bdma;
 398         struct ath_txq *cabq;
 399         struct list_head bbuf;
 400 };
 401
 402 void ath_beacon_tasklet(unsigned long data);
 403 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 404 int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
 405 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 406 int ath_beaconq_config(struct ath_softc *sc);
 407 void ath_set_beacon(struct ath_softc *sc);
 408 void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
 409
 410 /*******/
 411 /* ANI */
 412 /*******/
 413
 414 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 415 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 416 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 417 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
 418 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 419 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 420 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 421
 422 #define ATH_PAPRD_TIMEOUT       100 /* msecs */
 423
 424 void ath_hw_check(struct work_struct *work);
 425 void ath_hw_pll_work(struct work_struct *work);
 426 void ath_paprd_calibrate(struct work_struct *work);
 427 void ath_ani_calibrate(unsigned long data);
 428
 429 /**********/
 430 /* BTCOEX */
 431 /**********/
 432
 433 struct ath_btcoex {
 434         bool hw_timer_enabled;
 435         spinlock_t btcoex_lock;
 436         struct timer_list period_timer; /* Timer for BT period */
 437         u32 bt_priority_cnt;
 438         unsigned long bt_priority_time;
 439         int bt_stomp_type; /* Types of BT stomping */
 440         u32 btcoex_no_stomp; /* in usec */
 441         u32 btcoex_period; /* in usec */
 442         u32 btscan_no_stomp; /* in usec */
 443         struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
 444 };
 445
 446 int ath_init_btcoex_timer(struct ath_softc *sc);
 447 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
 448 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 449
 450 /********************/
 451 /*   LED Control    */
 452 /********************/
 453
 454 #define ATH_LED_PIN_DEF                 1
 455 #define ATH_LED_PIN_9287                8
 456 #define ATH_LED_PIN_9300                10
 457 #define ATH_LED_PIN_9485                6
 458
 459 #ifdef CONFIG_MAC80211_LEDS
 460 void ath_init_leds(struct ath_softc *sc);
 461 void ath_deinit_leds(struct ath_softc *sc);
 462 #else
 463 static inline void ath_init_leds(struct ath_softc *sc)
 464 {
 465 }
 466
 467 static inline void ath_deinit_leds(struct ath_softc *sc)
 468 {
 469 }
 470 #endif
 471
 472
 473 /* Antenna diversity/combining */
 474 #define ATH_ANT_RX_CURRENT_SHIFT 4
 475 #define ATH_ANT_RX_MAIN_SHIFT 2
 476 #define ATH_ANT_RX_MASK 0x3
 477
 478 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
 479 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
 480 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
 481 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
 482 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
 483 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
 484 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
 485
 486 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
 487 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
 488 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
 489 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
 490
 491 enum ath9k_ant_div_comb_lna_conf {
 492         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
 493         ATH_ANT_DIV_COMB_LNA2,
 494         ATH_ANT_DIV_COMB_LNA1,
 495         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
 496 };
 497
 498 struct ath_ant_comb {
 499         u16 count;
 500         u16 total_pkt_count;
 501         bool scan;
 502         bool scan_not_start;
 503         int main_total_rssi;
 504         int alt_total_rssi;
 505         int alt_recv_cnt;
 506         int main_recv_cnt;
 507         int rssi_lna1;
 508         int rssi_lna2;
 509         int rssi_add;
 510         int rssi_sub;
 511         int rssi_first;
 512         int rssi_second;
 513         int rssi_third;
 514         bool alt_good;
 515         int quick_scan_cnt;
 516         int main_conf;
 517         enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
 518         enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
 519         int first_bias;
 520         int second_bias;
 521         bool first_ratio;
 522         bool second_ratio;
 523         unsigned long scan_start_time;
 524 };
 525
 526 /********************/
 527 /* Main driver core */
 528 /********************/
 529
 530 /*
 531  * Default cache line size, in bytes.
 532  * Used when PCI device not fully initialized by bootrom/BIOS
 533 */
 534 #define DEFAULT_CACHELINE       32
 535 #define ATH_REGCLASSIDS_MAX     10
 536 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 537 #define ATH_MAX_SW_RETRIES      10
 538 #define ATH_CHAN_MAX            255
 539
 540 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 541 #define ATH_RATE_DUMMY_MARKER   0
 542
 543 #define SC_OP_INVALID                BIT(0)
 544 #define SC_OP_BEACONS                BIT(1)
 545 #define SC_OP_RXAGGR                 BIT(2)
 546 #define SC_OP_TXAGGR                 BIT(3)
 547 #define SC_OP_OFFCHANNEL             BIT(4)
 548 #define SC_OP_PREAMBLE_SHORT         BIT(5)
 549 #define SC_OP_PROTECT_ENABLE         BIT(6)
 550 #define SC_OP_RXFLUSH                BIT(7)
 551 #define SC_OP_LED_ASSOCIATED         BIT(8)
 552 #define SC_OP_LED_ON                 BIT(9)
 553 #define SC_OP_TSF_RESET              BIT(11)
 554 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 555 #define SC_OP_BT_SCAN                BIT(13)
 556 #define SC_OP_ANI_RUN                BIT(14)
 557 #define SC_OP_ENABLE_APM             BIT(15)
 558 #define SC_OP_PRIM_STA_VIF           BIT(16)
 559
 560 /* Powersave flags */
 561 #define PS_WAIT_FOR_BEACON        BIT(0)
 562 #define PS_WAIT_FOR_CAB           BIT(1)
 563 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 564 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 565 #define PS_BEACON_SYNC            BIT(4)
 566 #define PS_TSFOOR_SYNC            BIT(5)
 567
 568 struct ath_rate_table;
 569
 570 struct ath9k_vif_iter_data {
 571         const u8 *hw_macaddr; /* phy's hardware address, set
 572                                * before starting iteration for
 573                                * valid bssid mask.
 574                                */
 575         u8 mask[ETH_ALEN]; /* bssid mask */
 576         int naps;      /* number of AP vifs */
 577         int nmeshes;   /* number of mesh vifs */
 578         int nstations; /* number of station vifs */
 579         int nwds;      /* number of nwd vifs */
 580         int nadhocs;   /* number of adhoc vifs */
 581         int nothers;   /* number of vifs not specified above. */
 582 };
 583
 584 struct ath_softc {
 585         struct ieee80211_hw *hw;
 586         struct device *dev;
 587
 588         int chan_idx;
 589         int chan_is_ht;
 590         struct survey_info *cur_survey;
 591         struct survey_info survey[ATH9K_NUM_CHANNELS];
 592
 593         struct tasklet_struct intr_tq;
 594         struct tasklet_struct bcon_tasklet;
 595         struct ath_hw *sc_ah;
 596         void __iomem *mem;
 597         int irq;
 598         spinlock_t sc_serial_rw;
 599         spinlock_t sc_pm_lock;
 600         spinlock_t sc_pcu_lock;
 601         struct mutex mutex;
 602         struct work_struct paprd_work;
 603         struct work_struct hw_check_work;
 604         struct completion paprd_complete;
 605
 606         unsigned int hw_busy_count;
 607
 608         u32 intrstatus;
 609         u32 sc_flags; /* SC_OP_* */
 610         u16 ps_flags; /* PS_* */
 611         u16 curtxpow;
 612         bool ps_enabled;
 613         bool ps_idle;
 614         short nbcnvifs;
 615         short nvifs;
 616         unsigned long ps_usecount;
 617
 618         struct ath_config config;
 619         struct ath_rx rx;
 620         struct ath_tx tx;
 621         struct ath_beacon beacon;
 622         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 623
 624 #ifdef CONFIG_MAC80211_LEDS
 625         bool led_registered;
 626         char led_name[32];
 627         struct led_classdev led_cdev;
 628 #endif
 629
 630         struct ath9k_hw_cal_data caldata;
 631         int last_rssi;
 632
 633 #ifdef CONFIG_ATH9K_DEBUGFS
 634         struct ath9k_debug debug;
 635         spinlock_t nodes_lock;
 636         struct list_head nodes; /* basically, stations */
 637         unsigned int tx_complete_poll_work_seen;
 638 #endif
 639         struct ath_beacon_config cur_beacon_conf;
 640         struct delayed_work tx_complete_work;
 641         struct delayed_work hw_pll_work;
 642         struct ath_btcoex btcoex;
 643
 644         struct ath_descdma txsdma;
 645
 646         struct ath_ant_comb ant_comb;
 647 };
 648
 649 void ath9k_tasklet(unsigned long data);
 650 int ath_reset(struct ath_softc *sc, bool retry_tx);
 651 int ath_cabq_update(struct ath_softc *);
 652
 653 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 654 {
 655         common->bus_ops->read_cachesize(common, csz);
 656 }
 657
 658 extern struct ieee80211_ops ath9k_ops;
 659 extern int ath9k_modparam_nohwcrypt;
 660 extern int led_blink;
 661 extern bool is_ath9k_unloaded;
 662
 663 irqreturn_t ath_isr(int irq, void *dev);
 664 void ath9k_init_crypto(struct ath_softc *sc);
 665 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
 666                     const struct ath_bus_ops *bus_ops);
 667 void ath9k_deinit_device(struct ath_softc *sc);
 668 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 669 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 670                     struct ath9k_channel *hchan);
 671
 672 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
 673 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
 674 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
 675 bool ath9k_uses_beacons(int type);
 676
 677 #ifdef CONFIG_ATH9K_PCI
 678 int ath_pci_init(void);
 679 void ath_pci_exit(void);
 680 #else
 681 static inline int ath_pci_init(void) { return 0; };
 682 static inline void ath_pci_exit(void) {};
 683 #endif
 684
 685 #ifdef CONFIG_ATH9K_AHB
 686 int ath_ahb_init(void);
 687 void ath_ahb_exit(void);
 688 #else
 689 static inline int ath_ahb_init(void) { return 0; };
 690 static inline void ath_ahb_exit(void) {};
 691 #endif
 692
 693 void ath9k_ps_wakeup(struct ath_softc *sc);
 694 void ath9k_ps_restore(struct ath_softc *sc);
 695
 696 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 697
 698 void ath_start_rfkill_poll(struct ath_softc *sc);
 699 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
 700 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
 701                                struct ieee80211_vif *vif,
 702                                struct ath9k_vif_iter_data *iter_data);
 703
 704
 705 #endif /* ATH9K_H */