drivers/net/wireless/ath/ath9k/debug.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef DEBUG_H
  18 #define DEBUG_H
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "dfs_debug.h"
  23
  24 struct ath_txq;
  25 struct ath_buf;
  26
  27 #ifdef CONFIG_ATH9K_DEBUGFS
  28 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  29 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
  30 #else
  31 #define TX_STAT_INC(q, c) do { } while (0)
  32 #define RESET_STAT_INC(sc, type) do { } while (0)
  33 #endif
  34
  35 enum ath_reset_type {
  36         RESET_TYPE_BB_HANG,
  37         RESET_TYPE_BB_WATCHDOG,
  38         RESET_TYPE_FATAL_INT,
  39         RESET_TYPE_TX_ERROR,
  40         RESET_TYPE_TX_HANG,
  41         RESET_TYPE_PLL_HANG,
  42         RESET_TYPE_MAC_HANG,
  43         RESET_TYPE_BEACON_STUCK,
  44         RESET_TYPE_MCI,
  45         __RESET_TYPE_MAX
  46 };
  47
  48 #ifdef CONFIG_ATH9K_DEBUGFS
  49
  50 /**
  51  * struct ath_interrupt_stats - Contains statistics about interrupts
  52  * @total: Total no. of interrupts generated so far
  53  * @rxok: RX with no errors
  54  * @rxlp: RX with low priority RX
  55  * @rxhp: RX with high priority, uapsd only
  56  * @rxeol: RX with no more RXDESC available
  57  * @rxorn: RX FIFO overrun
  58  * @txok: TX completed at the requested rate
  59  * @txurn: TX FIFO underrun
  60  * @mib: MIB regs reaching its threshold
  61  * @rxphyerr: RX with phy errors
  62  * @rx_keycache_miss: RX with key cache misses
  63  * @swba: Software Beacon Alert
  64  * @bmiss: Beacon Miss
  65  * @bnr: Beacon Not Ready
  66  * @cst: Carrier Sense TImeout
  67  * @gtt: Global TX Timeout
  68  * @tim: RX beacon TIM occurrence
  69  * @cabend: RX End of CAB traffic
  70  * @dtimsync: DTIM sync lossage
  71  * @dtim: RX Beacon with DTIM
  72  * @bb_watchdog: Baseband watchdog
  73  * @tsfoor: TSF out of range, indicates that the corrected TSF received
  74  * from a beacon differs from the PCU's internal TSF by more than a
  75  * (programmable) threshold
  76  * @local_timeout: Internal bus timeout.
  77  */
  78 struct ath_interrupt_stats {
  79         u32 total;
  80         u32 rxok;
  81         u32 rxlp;
  82         u32 rxhp;
  83         u32 rxeol;
  84         u32 rxorn;
  85         u32 txok;
  86         u32 txeol;
  87         u32 txurn;
  88         u32 mib;
  89         u32 rxphyerr;
  90         u32 rx_keycache_miss;
  91         u32 swba;
  92         u32 bmiss;
  93         u32 bnr;
  94         u32 cst;
  95         u32 gtt;
  96         u32 tim;
  97         u32 cabend;
  98         u32 dtimsync;
  99         u32 dtim;
 100         u32 bb_watchdog;
 101         u32 tsfoor;
 102         u32 mci;
 103
 104         /* Sync-cause stats */
 105         u32 sync_cause_all;
 106         u32 sync_rtc_irq;
 107         u32 sync_mac_irq;
 108         u32 eeprom_illegal_access;
 109         u32 apb_timeout;
 110         u32 pci_mode_conflict;
 111         u32 host1_fatal;
 112         u32 host1_perr;
 113         u32 trcv_fifo_perr;
 114         u32 radm_cpl_ep;
 115         u32 radm_cpl_dllp_abort;
 116         u32 radm_cpl_tlp_abort;
 117         u32 radm_cpl_ecrc_err;
 118         u32 radm_cpl_timeout;
 119         u32 local_timeout;
 120         u32 pm_access;
 121         u32 mac_awake;
 122         u32 mac_asleep;
 123         u32 mac_sleep_access;
 124 };
 125
 126
 127 /**
 128  * struct ath_tx_stats - Statistics about TX
 129  * @tx_pkts_all:  No. of total frames transmitted, including ones that
 130         may have had errors.
 131  * @tx_bytes_all:  No. of total bytes transmitted, including ones that
 132         may have had errors.
 133  * @queued: Total MPDUs (non-aggr) queued
 134  * @completed: Total MPDUs (non-aggr) completed
 135  * @a_aggr: Total no. of aggregates queued
 136  * @a_queued_hw: Total AMPDUs queued to hardware
 137  * @a_queued_sw: Total AMPDUs queued to software queues
 138  * @a_completed: Total AMPDUs completed
 139  * @a_retries: No. of AMPDUs retried (SW)
 140  * @a_xretries: No. of AMPDUs dropped due to xretries
 141  * @fifo_underrun: FIFO underrun occurrences
 142         Valid only for:
 143                 - non-aggregate condition.
 144                 - first packet of aggregate.
 145  * @xtxop: No. of frames filtered because of TXOP limit
 146  * @timer_exp: Transmit timer expiry
 147  * @desc_cfg_err: Descriptor configuration errors
 148  * @data_urn: TX data underrun errors
 149  * @delim_urn: TX delimiter underrun errors
 150  * @puttxbuf: Number of times hardware was given txbuf to write.
 151  * @txstart:  Number of times hardware was told to start tx.
 152  * @txprocdesc:  Number of times tx descriptor was processed
 153  * @txfailed:  Out-of-memory or other errors in xmit path.
 154  */
 155 struct ath_tx_stats {
 156         u32 tx_pkts_all;
 157         u32 tx_bytes_all;
 158         u32 queued;
 159         u32 completed;
 160         u32 xretries;
 161         u32 a_aggr;
 162         u32 a_queued_hw;
 163         u32 a_queued_sw;
 164         u32 a_completed;
 165         u32 a_retries;
 166         u32 a_xretries;
 167         u32 fifo_underrun;
 168         u32 xtxop;
 169         u32 timer_exp;
 170         u32 desc_cfg_err;
 171         u32 data_underrun;
 172         u32 delim_underrun;
 173         u32 puttxbuf;
 174         u32 txstart;
 175         u32 txprocdesc;
 176         u32 txfailed;
 177 };
 178
 179 #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
 180
 181 /**
 182  * struct ath_rx_stats - RX Statistics
 183  * @rx_pkts_all:  No. of total frames received, including ones that
 184         may have had errors.
 185  * @rx_bytes_all:  No. of total bytes received, including ones that
 186         may have had errors.
 187  * @crc_err: No. of frames with incorrect CRC value
 188  * @decrypt_crc_err: No. of frames whose CRC check failed after
 189         decryption process completed
 190  * @phy_err: No. of frames whose reception failed because the PHY
 191         encountered an error
 192  * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 193  * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 194  * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 195  * @decrypt_busy_err: Decryption interruptions counter
 196  * @phy_err_stats: Individual PHY error statistics
 197  * @rx_len_err:  No. of frames discarded due to bad length.
 198  * @rx_oom_err:  No. of frames dropped due to OOM issues.
 199  * @rx_rate_err:  No. of frames dropped due to rate errors.
 200  * @rx_too_many_frags_err:  Frames dropped due to too-many-frags received.
 201  * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
 202  * @rx_beacons:  No. of beacons received.
 203  * @rx_frags:  No. of rx-fragements received.
 204  */
 205 struct ath_rx_stats {
 206         u32 rx_pkts_all;
 207         u32 rx_bytes_all;
 208         u32 crc_err;
 209         u32 decrypt_crc_err;
 210         u32 phy_err;
 211         u32 mic_err;
 212         u32 pre_delim_crc_err;
 213         u32 post_delim_crc_err;
 214         u32 decrypt_busy_err;
 215         u32 phy_err_stats[ATH9K_PHYERR_MAX];
 216         u32 rx_len_err;
 217         u32 rx_oom_err;
 218         u32 rx_rate_err;
 219         u32 rx_too_many_frags_err;
 220         u32 rx_drop_rxflush;
 221         u32 rx_beacons;
 222         u32 rx_frags;
 223 };
 224
 225 struct ath_stats {
 226         struct ath_interrupt_stats istats;
 227         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
 228         struct ath_rx_stats rxstats;
 229         struct ath_dfs_stats dfs_stats;
 230         u32 reset[__RESET_TYPE_MAX];
 231 };
 232
 233 #define ATH_DBG_MAX_SAMPLES     10
 234 struct ath_dbg_bb_mac_samp {
 235         u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
 236         u32 pcu_obs, pcu_cr, noise;
 237         struct {
 238                 u64 jiffies;
 239                 int8_t rssi_ctl0;
 240                 int8_t rssi_ctl1;
 241                 int8_t rssi_ctl2;
 242                 int8_t rssi_ext0;
 243                 int8_t rssi_ext1;
 244                 int8_t rssi_ext2;
 245                 int8_t rssi;
 246                 bool isok;
 247                 u8 rts_fail_cnt;
 248                 u8 data_fail_cnt;
 249                 u8 rateindex;
 250                 u8 qid;
 251                 u8 tid;
 252                 u32 ba_low;
 253                 u32 ba_high;
 254         } ts[ATH_DBG_MAX_SAMPLES];
 255         struct {
 256                 u64 jiffies;
 257                 int8_t rssi_ctl0;
 258                 int8_t rssi_ctl1;
 259                 int8_t rssi_ctl2;
 260                 int8_t rssi_ext0;
 261                 int8_t rssi_ext1;
 262                 int8_t rssi_ext2;
 263                 int8_t rssi;
 264                 bool is_mybeacon;
 265                 u8 antenna;
 266                 u8 rate;
 267         } rs[ATH_DBG_MAX_SAMPLES];
 268         struct ath_cycle_counters cc;
 269         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 270 };
 271
 272 struct ath9k_debug {
 273         struct dentry *debugfs_phy;
 274         u32 regidx;
 275         struct ath_stats stats;
 276 #ifdef CONFIG_ATH9K_MAC_DEBUG
 277         spinlock_t samp_lock;
 278         struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
 279         u8 sampidx;
 280         u8 tsidx;
 281         u8 rsidx;
 282 #endif
 283 };
 284
 285 int ath9k_init_debug(struct ath_hw *ah);
 286
 287 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
 288 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
 289                        struct ath_tx_status *ts, struct ath_txq *txq,
 290                        unsigned int flags);
 291 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
 292
 293 #else
 294
 295 #define RX_STAT_INC(c) /* NOP */
 296
 297 static inline int ath9k_init_debug(struct ath_hw *ah)
 298 {
 299         return 0;
 300 }
 301
 302 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
 303                                             enum ath9k_int status)
 304 {
 305 }
 306
 307 static inline void ath_debug_stat_tx(struct ath_softc *sc,
 308                                      struct ath_buf *bf,
 309                                      struct ath_tx_status *ts,
 310                                      struct ath_txq *txq,
 311                                      unsigned int flags)
 312 {
 313 }
 314
 315 static inline void ath_debug_stat_rx(struct ath_softc *sc,
 316                                      struct ath_rx_status *rs)
 317 {
 318 }
 319
 320 #endif /* CONFIG_ATH9K_DEBUGFS */
 321
 322 #ifdef CONFIG_ATH9K_MAC_DEBUG
 323
 324 void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
 325
 326 #else
 327
 328 static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
 329 {
 330 }
 331
 332 #endif
 333
 334
 335 #endif /* DEBUG_H */