drivers/net/wireless/ath/ath9k/eeprom.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef EEPROM_H
  18 #define EEPROM_H
  19
  20 #include "../ath.h"
  21 #include <net/cfg80211.h>
  22 #include "ar9003_eeprom.h"
  23
  24 #define AH_USE_EEPROM   0x1
  25
  26 #ifdef __BIG_ENDIAN
  27 #define AR5416_EEPROM_MAGIC 0x5aa5
  28 #else
  29 #define AR5416_EEPROM_MAGIC 0xa55a
  30 #endif
  31
  32 #define CTRY_DEBUG   0x1ff
  33 #define CTRY_DEFAULT 0
  34
  35 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
  36 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
  37 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
  38 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
  39 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
  40 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
  41 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
  42 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
  43 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
  44
  45 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
  46 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
  47 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
  48 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
  49 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
  50 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
  51
  52 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
  53 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
  54
  55 #define AR5416_EEPROM_MAGIC_OFFSET  0x0
  56 #define AR5416_EEPROM_S             2
  57 #define AR5416_EEPROM_OFFSET        0x2000
  58 #define AR5416_EEPROM_MAX           0xae0
  59
  60 #define AR5416_EEPROM_START_ADDR \
  61         (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
  62
  63 #define SD_NO_CTL               0xE0
  64 #define NO_CTL                  0xff
  65 #define CTL_MODE_M              0xf
  66 #define CTL_11A                 0
  67 #define CTL_11B                 1
  68 #define CTL_11G                 2
  69 #define CTL_2GHT20              5
  70 #define CTL_5GHT20              6
  71 #define CTL_2GHT40              7
  72 #define CTL_5GHT40              8
  73
  74 #define EXT_ADDITIVE (0x8000)
  75 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  76 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  77 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  78
  79 #define SUB_NUM_CTL_MODES_AT_5G_40 2
  80 #define SUB_NUM_CTL_MODES_AT_2G_40 3
  81
  82 #define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  83 #define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
  84
  85 /*
  86  * For AR9285 and later chipsets, the following bits are not being programmed
  87  * in EEPROM and so need to be enabled always.
  88  *
  89  * Bit 0: en_fcc_mid
  90  * Bit 1: en_jap_mid
  91  * Bit 2: en_fcc_dfs_ht40
  92  * Bit 3: en_jap_ht40
  93  * Bit 4: en_jap_dfs_ht40
  94  */
  95 #define AR9285_RDEXT_DEFAULT    0x1F
  96
  97 #define ATH9K_POW_SM(_r, _s)    (((_r) & 0x3f) << (_s))
  98 #define FREQ2FBIN(x, y)         ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
  99 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
 100
 101 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
 102 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
 103                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 104 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
 105                                  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
 106
 107 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
 108 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 109 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 110 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 111
 112 #define EEP_RFSILENT_ENABLED        0x0001
 113 #define EEP_RFSILENT_ENABLED_S      0
 114 #define EEP_RFSILENT_POLARITY       0x0002
 115 #define EEP_RFSILENT_POLARITY_S     1
 116 #define EEP_RFSILENT_GPIO_SEL       0x001c
 117 #define EEP_RFSILENT_GPIO_SEL_S     2
 118
 119 #define AR5416_OPFLAGS_11A           0x01
 120 #define AR5416_OPFLAGS_11G           0x02
 121 #define AR5416_OPFLAGS_N_5G_HT40     0x04
 122 #define AR5416_OPFLAGS_N_2G_HT40     0x08
 123 #define AR5416_OPFLAGS_N_5G_HT20     0x10
 124 #define AR5416_OPFLAGS_N_2G_HT20     0x20
 125
 126 #define AR5416_EEP_NO_BACK_VER       0x1
 127 #define AR5416_EEP_VER               0xE
 128 #define AR5416_EEP_VER_MINOR_MASK    0x0FFF
 129 #define AR5416_EEP_MINOR_VER_2       0x2
 130 #define AR5416_EEP_MINOR_VER_3       0x3
 131 #define AR5416_EEP_MINOR_VER_7       0x7
 132 #define AR5416_EEP_MINOR_VER_9       0x9
 133 #define AR5416_EEP_MINOR_VER_16      0x10
 134 #define AR5416_EEP_MINOR_VER_17      0x11
 135 #define AR5416_EEP_MINOR_VER_19      0x13
 136 #define AR5416_EEP_MINOR_VER_20      0x14
 137 #define AR5416_EEP_MINOR_VER_21      0x15
 138 #define AR5416_EEP_MINOR_VER_22      0x16
 139
 140 #define AR5416_NUM_5G_CAL_PIERS         8
 141 #define AR5416_NUM_2G_CAL_PIERS         4
 142 #define AR5416_NUM_5G_20_TARGET_POWERS  8
 143 #define AR5416_NUM_5G_40_TARGET_POWERS  8
 144 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
 145 #define AR5416_NUM_2G_20_TARGET_POWERS  4
 146 #define AR5416_NUM_2G_40_TARGET_POWERS  4
 147 #define AR5416_NUM_CTLS                 24
 148 #define AR5416_NUM_BAND_EDGES           8
 149 #define AR5416_NUM_PD_GAINS             4
 150 #define AR5416_PD_GAINS_IN_MASK         4
 151 #define AR5416_PD_GAIN_ICEPTS           5
 152 #define AR5416_EEPROM_MODAL_SPURS       5
 153 #define AR5416_MAX_RATE_POWER           63
 154 #define AR5416_NUM_PDADC_VALUES         128
 155 #define AR5416_BCHAN_UNUSED             0xFF
 156 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
 157 #define AR5416_MAX_CHAINS               3
 158 #define AR9300_MAX_CHAINS               3
 159 #define AR5416_PWR_TABLE_OFFSET_DB     -5
 160
 161 /* Rx gain type values */
 162 #define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
 163 #define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
 164 #define AR5416_EEP_RXGAIN_ORIG             2
 165
 166 /* Tx gain type values */
 167 #define AR5416_EEP_TXGAIN_ORIGINAL         0
 168 #define AR5416_EEP_TXGAIN_HIGH_POWER       1
 169
 170 #define AR5416_EEP4K_START_LOC                64
 171 #define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
 172 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
 173 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
 174 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
 175 #define AR5416_EEP4K_NUM_CTLS                 12
 176 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 177 #define AR5416_EEP4K_NUM_PD_GAINS             2
 178 #define AR5416_EEP4K_PD_GAINS_IN_MASK         4
 179 #define AR5416_EEP4K_PD_GAIN_ICEPTS           5
 180 #define AR5416_EEP4K_MAX_CHAINS               1
 181
 182 #define AR9280_TX_GAIN_TABLE_SIZE 22
 183
 184 #define AR9287_EEP_VER               0xE
 185 #define AR9287_EEP_VER_MINOR_MASK    0xFFF
 186 #define AR9287_EEP_MINOR_VER_1       0x1
 187 #define AR9287_EEP_MINOR_VER_2       0x2
 188 #define AR9287_EEP_MINOR_VER_3       0x3
 189 #define AR9287_EEP_MINOR_VER         AR9287_EEP_MINOR_VER_3
 190 #define AR9287_EEP_MINOR_VER_b       AR9287_EEP_MINOR_VER
 191 #define AR9287_EEP_NO_BACK_VER       AR9287_EEP_MINOR_VER_1
 192
 193 #define AR9287_EEP_START_LOC            128
 194 #define AR9287_HTC_EEP_START_LOC        256
 195 #define AR9287_NUM_2G_CAL_PIERS         3
 196 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
 197 #define AR9287_NUM_2G_20_TARGET_POWERS  3
 198 #define AR9287_NUM_2G_40_TARGET_POWERS  3
 199 #define AR9287_NUM_CTLS                 12
 200 #define AR9287_NUM_BAND_EDGES           4
 201 #define AR9287_NUM_PD_GAINS             4
 202 #define AR9287_PD_GAINS_IN_MASK         4
 203 #define AR9287_PD_GAIN_ICEPTS           1
 204 #define AR9287_EEPROM_MODAL_SPURS       5
 205 #define AR9287_MAX_RATE_POWER           63
 206 #define AR9287_NUM_PDADC_VALUES         128
 207 #define AR9287_NUM_RATES                16
 208 #define AR9287_BCHAN_UNUSED             0xFF
 209 #define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
 210 #define AR9287_OPFLAGS_11A              0x01
 211 #define AR9287_OPFLAGS_11G              0x02
 212 #define AR9287_OPFLAGS_2G_HT40          0x08
 213 #define AR9287_OPFLAGS_2G_HT20          0x20
 214 #define AR9287_OPFLAGS_5G_HT40          0x04
 215 #define AR9287_OPFLAGS_5G_HT20          0x10
 216 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
 217 #define AR9287_EEPMISC_WOW              0x02
 218 #define AR9287_MAX_CHAINS               2
 219 #define AR9287_ANT_16S                  32
 220 #define AR9287_custdatasize             20
 221
 222 #define AR9287_NUM_ANT_CHAIN_FIELDS     6
 223 #define AR9287_NUM_ANT_COMMON_FIELDS    4
 224 #define AR9287_SIZE_ANT_CHAIN_FIELD     2
 225 #define AR9287_SIZE_ANT_COMMON_FIELD    4
 226 #define AR9287_ANT_CHAIN_MASK           0x3
 227 #define AR9287_ANT_COMMON_MASK          0xf
 228 #define AR9287_CHAIN_0_IDX              0
 229 #define AR9287_CHAIN_1_IDX              1
 230 #define AR9287_DATA_SZ                  32
 231
 232 #define AR9287_PWR_TABLE_OFFSET_DB  -5
 233
 234 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
 235
 236 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
 237 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
 238
 239 #define LNA_CTL_BUF_MODE        BIT(0)
 240 #define LNA_CTL_ISEL_LO         BIT(1)
 241 #define LNA_CTL_ISEL_HI         BIT(2)
 242 #define LNA_CTL_BUF_IN          BIT(3)
 243 #define LNA_CTL_FEM_BAND        BIT(4)
 244 #define LNA_CTL_LOCAL_BIAS      BIT(5)
 245 #define LNA_CTL_FORCE_XPA       BIT(6)
 246 #define LNA_CTL_USE_ANT1        BIT(7)
 247
 248 enum eeprom_param {
 249         EEP_NFTHRESH_5,
 250         EEP_NFTHRESH_2,
 251         EEP_MAC_MSW,
 252         EEP_MAC_MID,
 253         EEP_MAC_LSW,
 254         EEP_REG_0,
 255         EEP_REG_1,
 256         EEP_OP_CAP,
 257         EEP_OP_MODE,
 258         EEP_RF_SILENT,
 259         EEP_OB_5,
 260         EEP_DB_5,
 261         EEP_OB_2,
 262         EEP_DB_2,
 263         EEP_MINOR_REV,
 264         EEP_TX_MASK,
 265         EEP_RX_MASK,
 266         EEP_FSTCLK_5G,
 267         EEP_RXGAIN_TYPE,
 268         EEP_OL_PWRCTRL,
 269         EEP_TXGAIN_TYPE,
 270         EEP_RC_CHAIN_MASK,
 271         EEP_DAC_HPWR_5G,
 272         EEP_FRAC_N_5G,
 273         EEP_DEV_TYPE,
 274         EEP_TEMPSENSE_SLOPE,
 275         EEP_TEMPSENSE_SLOPE_PAL_ON,
 276         EEP_PWR_TABLE_OFFSET,
 277         EEP_DRIVE_STRENGTH,
 278         EEP_INTERNAL_REGULATOR,
 279         EEP_SWREG,
 280         EEP_PAPRD,
 281         EEP_MODAL_VER,
 282         EEP_ANT_DIV_CTL1,
 283 };
 284
 285 enum ar5416_rates {
 286         rate6mb, rate9mb, rate12mb, rate18mb,
 287         rate24mb, rate36mb, rate48mb, rate54mb,
 288         rate1l, rate2l, rate2s, rate5_5l,
 289         rate5_5s, rate11l, rate11s, rateXr,
 290         rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
 291         rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
 292         rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
 293         rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
 294         rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
 295         Ar5416RateSize
 296 };
 297
 298 enum ath9k_hal_freq_band {
 299         ATH9K_HAL_FREQ_BAND_5GHZ = 0,
 300         ATH9K_HAL_FREQ_BAND_2GHZ = 1
 301 };
 302
 303 struct base_eep_header {
 304         u16 length;
 305         u16 checksum;
 306         u16 version;
 307         u8 opCapFlags;
 308         u8 eepMisc;
 309         u16 regDmn[2];
 310         u8 macAddr[6];
 311         u8 rxMask;
 312         u8 txMask;
 313         u16 rfSilent;
 314         u16 blueToothOptions;
 315         u16 deviceCap;
 316         u32 binBuildNumber;
 317         u8 deviceType;
 318         u8 pwdclkind;
 319         u8 fastClk5g;
 320         u8 divChain;
 321         u8 rxGainType;
 322         u8 dacHiPwrMode_5G;
 323         u8 openLoopPwrCntl;
 324         u8 dacLpMode;
 325         u8 txGainType;
 326         u8 rcChainMask;
 327         u8 desiredScaleCCK;
 328         u8 pwr_table_offset;
 329         u8 frac_n_5g;
 330         u8 futureBase_3[21];
 331 } __packed;
 332
 333 struct base_eep_header_4k {
 334         u16 length;
 335         u16 checksum;
 336         u16 version;
 337         u8 opCapFlags;
 338         u8 eepMisc;
 339         u16 regDmn[2];
 340         u8 macAddr[6];
 341         u8 rxMask;
 342         u8 txMask;
 343         u16 rfSilent;
 344         u16 blueToothOptions;
 345         u16 deviceCap;
 346         u32 binBuildNumber;
 347         u8 deviceType;
 348         u8 txGainType;
 349 } __packed;
 350
 351
 352 struct spur_chan {
 353         u16 spurChan;
 354         u8 spurRangeLow;
 355         u8 spurRangeHigh;
 356 } __packed;
 357
 358 struct modal_eep_header {
 359         u32 antCtrlChain[AR5416_MAX_CHAINS];
 360         u32 antCtrlCommon;
 361         u8 antennaGainCh[AR5416_MAX_CHAINS];
 362         u8 switchSettling;
 363         u8 txRxAttenCh[AR5416_MAX_CHAINS];
 364         u8 rxTxMarginCh[AR5416_MAX_CHAINS];
 365         u8 adcDesiredSize;
 366         u8 pgaDesiredSize;
 367         u8 xlnaGainCh[AR5416_MAX_CHAINS];
 368         u8 txEndToXpaOff;
 369         u8 txEndToRxOn;
 370         u8 txFrameToXpaOn;
 371         u8 thresh62;
 372         u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
 373         u8 xpdGain;
 374         u8 xpd;
 375         u8 iqCalICh[AR5416_MAX_CHAINS];
 376         u8 iqCalQCh[AR5416_MAX_CHAINS];
 377         u8 pdGainOverlap;
 378         u8 ob;
 379         u8 db;
 380         u8 xpaBiasLvl;
 381         u8 pwrDecreaseFor2Chain;
 382         u8 pwrDecreaseFor3Chain;
 383         u8 txFrameToDataStart;
 384         u8 txFrameToPaOn;
 385         u8 ht40PowerIncForPdadc;
 386         u8 bswAtten[AR5416_MAX_CHAINS];
 387         u8 bswMargin[AR5416_MAX_CHAINS];
 388         u8 swSettleHt40;
 389         u8 xatten2Db[AR5416_MAX_CHAINS];
 390         u8 xatten2Margin[AR5416_MAX_CHAINS];
 391         u8 ob_ch1;
 392         u8 db_ch1;
 393         u8 lna_ctl;
 394         u8 miscBits;
 395         u16 xpaBiasLvlFreq[3];
 396         u8 futureModal[6];
 397
 398         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 399 } __packed;
 400
 401 struct calDataPerFreqOpLoop {
 402         u8 pwrPdg[2][5];
 403         u8 vpdPdg[2][5];
 404         u8 pcdac[2][5];
 405         u8 empty[2][5];
 406 } __packed;
 407
 408 struct modal_eep_4k_header {
 409         u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
 410         u32 antCtrlCommon;
 411         u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
 412         u8 switchSettling;
 413         u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
 414         u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
 415         u8 adcDesiredSize;
 416         u8 pgaDesiredSize;
 417         u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
 418         u8 txEndToXpaOff;
 419         u8 txEndToRxOn;
 420         u8 txFrameToXpaOn;
 421         u8 thresh62;
 422         u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
 423         u8 xpdGain;
 424         u8 xpd;
 425         u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
 426         u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
 427         u8 pdGainOverlap;
 428 #ifdef __BIG_ENDIAN_BITFIELD
 429         u8 ob_1:4, ob_0:4;
 430         u8 db1_1:4, db1_0:4;
 431 #else
 432         u8 ob_0:4, ob_1:4;
 433         u8 db1_0:4, db1_1:4;
 434 #endif
 435         u8 xpaBiasLvl;
 436         u8 txFrameToDataStart;
 437         u8 txFrameToPaOn;
 438         u8 ht40PowerIncForPdadc;
 439         u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
 440         u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
 441         u8 swSettleHt40;
 442         u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
 443         u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
 444 #ifdef __BIG_ENDIAN_BITFIELD
 445         u8 db2_1:4, db2_0:4;
 446 #else
 447         u8 db2_0:4, db2_1:4;
 448 #endif
 449         u8 version;
 450 #ifdef __BIG_ENDIAN_BITFIELD
 451         u8 ob_3:4, ob_2:4;
 452         u8 antdiv_ctl1:4, ob_4:4;
 453         u8 db1_3:4, db1_2:4;
 454         u8 antdiv_ctl2:4, db1_4:4;
 455         u8 db2_2:4, db2_3:4;
 456         u8 reserved:4, db2_4:4;
 457 #else
 458         u8 ob_2:4, ob_3:4;
 459         u8 ob_4:4, antdiv_ctl1:4;
 460         u8 db1_2:4, db1_3:4;
 461         u8 db1_4:4, antdiv_ctl2:4;
 462         u8 db2_2:4, db2_3:4;
 463         u8 db2_4:4, reserved:4;
 464 #endif
 465         u8 futureModal[4];
 466         struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
 467 } __packed;
 468
 469 struct base_eep_ar9287_header {
 470         u16 length;
 471         u16 checksum;
 472         u16 version;
 473         u8 opCapFlags;
 474         u8 eepMisc;
 475         u16 regDmn[2];
 476         u8 macAddr[6];
 477         u8 rxMask;
 478         u8 txMask;
 479         u16 rfSilent;
 480         u16 blueToothOptions;
 481         u16 deviceCap;
 482         u32 binBuildNumber;
 483         u8 deviceType;
 484         u8 openLoopPwrCntl;
 485         int8_t pwrTableOffset;
 486         int8_t tempSensSlope;
 487         int8_t tempSensSlopePalOn;
 488         u8 futureBase[29];
 489 } __packed;
 490
 491 struct modal_eep_ar9287_header {
 492         u32 antCtrlChain[AR9287_MAX_CHAINS];
 493         u32 antCtrlCommon;
 494         int8_t antennaGainCh[AR9287_MAX_CHAINS];
 495         u8 switchSettling;
 496         u8 txRxAttenCh[AR9287_MAX_CHAINS];
 497         u8 rxTxMarginCh[AR9287_MAX_CHAINS];
 498         int8_t adcDesiredSize;
 499         u8 txEndToXpaOff;
 500         u8 txEndToRxOn;
 501         u8 txFrameToXpaOn;
 502         u8 thresh62;
 503         int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
 504         u8 xpdGain;
 505         u8 xpd;
 506         int8_t iqCalICh[AR9287_MAX_CHAINS];
 507         int8_t iqCalQCh[AR9287_MAX_CHAINS];
 508         u8 pdGainOverlap;
 509         u8 xpaBiasLvl;
 510         u8 txFrameToDataStart;
 511         u8 txFrameToPaOn;
 512         u8 ht40PowerIncForPdadc;
 513         u8 bswAtten[AR9287_MAX_CHAINS];
 514         u8 bswMargin[AR9287_MAX_CHAINS];
 515         u8 swSettleHt40;
 516         u8 version;
 517         u8 db1;
 518         u8 db2;
 519         u8 ob_cck;
 520         u8 ob_psk;
 521         u8 ob_qam;
 522         u8 ob_pal_off;
 523         u8 futureModal[30];
 524         struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
 525 } __packed;
 526
 527 struct cal_data_per_freq {
 528         u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 529         u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 530 } __packed;
 531
 532 struct cal_data_per_freq_4k {
 533         u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 534         u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
 535 } __packed;
 536
 537 struct cal_target_power_leg {
 538         u8 bChannel;
 539         u8 tPow2x[4];
 540 } __packed;
 541
 542 struct cal_target_power_ht {
 543         u8 bChannel;
 544         u8 tPow2x[8];
 545 } __packed;
 546
 547 struct cal_ctl_edges {
 548         u8 bChannel;
 549         u8 ctl;
 550 } __packed;
 551
 552 struct cal_data_op_loop_ar9287 {
 553         u8 pwrPdg[2][5];
 554         u8 vpdPdg[2][5];
 555         u8 pcdac[2][5];
 556         u8 empty[2][5];
 557 } __packed;
 558
 559 struct cal_data_per_freq_ar9287 {
 560         u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 561         u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 562 } __packed;
 563
 564 union cal_data_per_freq_ar9287_u {
 565         struct cal_data_op_loop_ar9287 calDataOpen;
 566         struct cal_data_per_freq_ar9287 calDataClose;
 567 } __packed;
 568
 569 struct cal_ctl_data_ar9287 {
 570         struct cal_ctl_edges
 571         ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
 572 } __packed;
 573
 574 struct cal_ctl_data {
 575         struct cal_ctl_edges
 576         ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 577 } __packed;
 578
 579 struct cal_ctl_data_4k {
 580         struct cal_ctl_edges
 581         ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
 582 } __packed;
 583
 584 struct ar5416_eeprom_def {
 585         struct base_eep_header baseEepHeader;
 586         u8 custData[64];
 587         struct modal_eep_header modalHeader[2];
 588         u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
 589         u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 590         struct cal_data_per_freq
 591          calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 592         struct cal_data_per_freq
 593          calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
 594         struct cal_target_power_leg
 595          calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
 596         struct cal_target_power_ht
 597          calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
 598         struct cal_target_power_ht
 599          calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
 600         struct cal_target_power_leg
 601          calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
 602         struct cal_target_power_leg
 603          calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
 604         struct cal_target_power_ht
 605          calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 606         struct cal_target_power_ht
 607          calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
 608         u8 ctlIndex[AR5416_NUM_CTLS];
 609         struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
 610         u8 padding;
 611 } __packed;
 612
 613 struct ar5416_eeprom_4k {
 614         struct base_eep_header_4k baseEepHeader;
 615         u8 custData[20];
 616         struct modal_eep_4k_header modalHeader;
 617         u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
 618         struct cal_data_per_freq_4k
 619         calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
 620         struct cal_target_power_leg
 621         calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
 622         struct cal_target_power_leg
 623         calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 624         struct cal_target_power_ht
 625         calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
 626         struct cal_target_power_ht
 627         calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
 628         u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
 629         struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
 630         u8 padding;
 631 } __packed;
 632
 633 struct ar9287_eeprom {
 634         struct base_eep_ar9287_header baseEepHeader;
 635         u8 custData[AR9287_DATA_SZ];
 636         struct modal_eep_ar9287_header modalHeader;
 637         u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
 638         union cal_data_per_freq_ar9287_u
 639         calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
 640         struct cal_target_power_leg
 641         calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
 642         struct cal_target_power_leg
 643         calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
 644         struct cal_target_power_ht
 645         calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
 646         struct cal_target_power_ht
 647         calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
 648         u8 ctlIndex[AR9287_NUM_CTLS];
 649         struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
 650         u8 padding;
 651 } __packed;
 652
 653 enum reg_ext_bitmap {
 654         REG_EXT_FCC_MIDBAND = 0,
 655         REG_EXT_JAPAN_MIDBAND = 1,
 656         REG_EXT_FCC_DFS_HT40 = 2,
 657         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 658         REG_EXT_JAPAN_DFS_HT40 = 4
 659 };
 660
 661 struct ath9k_country_entry {
 662         u16 countryCode;
 663         u16 regDmnEnum;
 664         u16 regDmn5G;
 665         u16 regDmn2G;
 666         u8 isMultidomain;
 667         u8 iso[3];
 668 };
 669
 670 struct eeprom_ops {
 671         int (*check_eeprom)(struct ath_hw *hw);
 672         u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
 673         bool (*fill_eeprom)(struct ath_hw *hw);
 674         int (*get_eeprom_ver)(struct ath_hw *hw);
 675         int (*get_eeprom_rev)(struct ath_hw *hw);
 676         u8 (*get_num_ant_config)(struct ath_hw *hw,
 677                                  enum ath9k_hal_freq_band band);
 678         u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
 679                                       struct ath9k_channel *chan);
 680         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
 681         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
 682         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
 683                            u16 cfgCtl, u8 twiceAntennaReduction,
 684                            u8 twiceMaxRegulatoryPower, u8 powerLimit);
 685         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 686 };
 687
 688 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
 689 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
 690                                u32 shift, u32 val);
 691 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
 692                              int16_t targetLeft,
 693                              int16_t targetRight);
 694 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
 695                                     u16 *indexL, u16 *indexR);
 696 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
 697 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
 698                              u8 *pVpdList, u16 numIntercepts,
 699                              u8 *pRetVpdList);
 700 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
 701                                        struct ath9k_channel *chan,
 702                                        struct cal_target_power_leg *powInfo,
 703                                        u16 numChannels,
 704                                        struct cal_target_power_leg *pNewPower,
 705                                        u16 numRates, bool isExtTarget);
 706 void ath9k_hw_get_target_powers(struct ath_hw *ah,
 707                                 struct ath9k_channel *chan,
 708                                 struct cal_target_power_ht *powInfo,
 709                                 u16 numChannels,
 710                                 struct cal_target_power_ht *pNewPower,
 711                                 u16 numRates, bool isHt40Target);
 712 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
 713                                 bool is2GHz, int num_band_edges);
 714 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
 715 int ath9k_hw_eeprom_init(struct ath_hw *ah);
 716
 717 #define ar5416_get_ntxchains(_txchainmask)                      \
 718         (((_txchainmask >> 2) & 1) +                            \
 719          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
 720
 721 extern const struct eeprom_ops eep_def_ops;
 722 extern const struct eeprom_ops eep_4k_ops;
 723 extern const struct eeprom_ops eep_ar9287_ops;
 724 extern const struct eeprom_ops eep_ar9287_ops;
 725 extern const struct eeprom_ops eep_ar9300_ops;
 726
 727 #endif /* EEPROM_H */