]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/net/wireless/ath/ath9k/eeprom_9287.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:


13579752a3006c9ccf883ed0cb55c19d818285c5
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / eeprom_9287.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "ar9002_phy.h"
19
20 #define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
21
22 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
23 {
24 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
25 }
26
27 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
28 {
29 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
30 }
31
32 static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
33 {
34 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
35 struct ath_common *common = ath9k_hw_common(ah);
36 u16 *eep_data;
37 int addr, eep_start_loc = AR9287_EEP_START_LOC;
38 eep_data = (u16 *)eep;
39
40 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
41 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
42 eep_data)) {
43 ath_dbg(common, ATH_DBG_EEPROM,
44 "Unable to read eeprom region\n");
45 return false;
46 }
47 eep_data++;
48 }
49
50 return true;
51 }
52
53 static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
54 {
55 u16 *eep_data = (u16 *)&ah->eeprom.map9287;
56
57 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
58 AR9287_HTC_EEP_START_LOC,
59 SIZE_EEPROM_AR9287);
60 return true;
61 }
62
63 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
64 {
65 struct ath_common *common = ath9k_hw_common(ah);
66
67 if (!ath9k_hw_use_flash(ah)) {
68 ath_dbg(common, ATH_DBG_EEPROM,
69 "Reading from EEPROM, not flash\n");
70 }
71
72 if (common->bus_ops->ath_bus_type == ATH_USB)
73 return __ath9k_hw_usb_ar9287_fill_eeprom(ah);
74 else
75 return __ath9k_hw_ar9287_fill_eeprom(ah);
76 }
77
78 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
79 {
80 u32 sum = 0, el, integer;
81 u16 temp, word, magic, magic2, *eepdata;
82 int i, addr;
83 bool need_swap = false;
84 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
85 struct ath_common *common = ath9k_hw_common(ah);
86
87 if (!ath9k_hw_use_flash(ah)) {
88 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
89 &magic)) {
90 ath_err(common, "Reading Magic # failed\n");
91 return false;
92 }
93
94 ath_dbg(common, ATH_DBG_EEPROM,
95 "Read Magic = 0x%04X\n", magic);
96
97 if (magic != AR5416_EEPROM_MAGIC) {
98 magic2 = swab16(magic);
99
100 if (magic2 == AR5416_EEPROM_MAGIC) {
101 need_swap = true;
102 eepdata = (u16 *)(&ah->eeprom);
103
104 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
105 temp = swab16(*eepdata);
106 *eepdata = temp;
107 eepdata++;
108 }
109 } else {
110 ath_err(common,
111 "Invalid EEPROM Magic. Endianness mismatch.\n");
112 return -EINVAL;
113 }
114 }
115 }
116
117 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
118 need_swap ? "True" : "False");
119
120 if (need_swap)
121 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
122 else
123 el = ah->eeprom.map9287.baseEepHeader.length;
124
125 if (el > sizeof(struct ar9287_eeprom))
126 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
127 else
128 el = el / sizeof(u16);
129
130 eepdata = (u16 *)(&ah->eeprom);
131
132 for (i = 0; i < el; i++)
133 sum ^= *eepdata++;
134
135 if (need_swap) {
136 word = swab16(eep->baseEepHeader.length);
137 eep->baseEepHeader.length = word;
138
139 word = swab16(eep->baseEepHeader.checksum);
140 eep->baseEepHeader.checksum = word;
141
142 word = swab16(eep->baseEepHeader.version);
143 eep->baseEepHeader.version = word;
144
145 word = swab16(eep->baseEepHeader.regDmn[0]);
146 eep->baseEepHeader.regDmn[0] = word;
147
148 word = swab16(eep->baseEepHeader.regDmn[1]);
149 eep->baseEepHeader.regDmn[1] = word;
150
151 word = swab16(eep->baseEepHeader.rfSilent);
152 eep->baseEepHeader.rfSilent = word;
153
154 word = swab16(eep->baseEepHeader.blueToothOptions);
155 eep->baseEepHeader.blueToothOptions = word;
156
157 word = swab16(eep->baseEepHeader.deviceCap);
158 eep->baseEepHeader.deviceCap = word;
159
160 integer = swab32(eep->modalHeader.antCtrlCommon);
161 eep->modalHeader.antCtrlCommon = integer;
162
163 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
164 integer = swab32(eep->modalHeader.antCtrlChain[i]);
165 eep->modalHeader.antCtrlChain[i] = integer;
166 }
167
168 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
169 word = swab16(eep->modalHeader.spurChans[i].spurChan);
170 eep->modalHeader.spurChans[i].spurChan = word;
171 }
172 }
173
174 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
175 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
176 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
177 sum, ah->eep_ops->get_eeprom_ver(ah));
178 return -EINVAL;
179 }
180
181 return 0;
182 }
183
184 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
185 enum eeprom_param param)
186 {
187 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
188 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
189 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
190 u16 ver_minor;
191
192 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
193
194 switch (param) {
195 case EEP_NFTHRESH_2:
196 return pModal->noiseFloorThreshCh[0];
197 case EEP_MAC_LSW:
198 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
199 case EEP_MAC_MID:
200 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
201 case EEP_MAC_MSW:
202 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
203 case EEP_REG_0:
204 return pBase->regDmn[0];
205 case EEP_REG_1:
206 return pBase->regDmn[1];
207 case EEP_OP_CAP:
208 return pBase->deviceCap;
209 case EEP_OP_MODE:
210 return pBase->opCapFlags;
211 case EEP_RF_SILENT:
212 return pBase->rfSilent;
213 case EEP_MINOR_REV:
214 return ver_minor;
215 case EEP_TX_MASK:
216 return pBase->txMask;
217 case EEP_RX_MASK:
218 return pBase->rxMask;
219 case EEP_DEV_TYPE:
220 return pBase->deviceType;
221 case EEP_OL_PWRCTRL:
222 return pBase->openLoopPwrCntl;
223 case EEP_TEMPSENSE_SLOPE:
224 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
225 return pBase->tempSensSlope;
226 else
227 return 0;
228 case EEP_TEMPSENSE_SLOPE_PAL_ON:
229 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
230 return pBase->tempSensSlopePalOn;
231 else
232 return 0;
233 default:
234 return 0;
235 }
236 }
237
238 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
239 struct ath9k_channel *chan,
240 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
241 u8 *pCalChans, u16 availPiers, int8_t *pPwr)
242 {
243 u16 idxL = 0, idxR = 0, numPiers;
244 bool match;
245 struct chan_centers centers;
246
247 ath9k_hw_get_channel_centers(ah, chan, &centers);
248
249 for (numPiers = 0; numPiers < availPiers; numPiers++) {
250 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
251 break;
252 }
253
254 match = ath9k_hw_get_lower_upper_index(
255 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
256 pCalChans, numPiers, &idxL, &idxR);
257
258 if (match) {
259 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
260 } else {
261 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
262 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
263 }
264
265 }
266
267 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
268 int32_t txPower, u16 chain)
269 {
270 u32 tmpVal;
271 u32 a;
272
273 /* Enable OLPC for chain 0 */
274
275 tmpVal = REG_READ(ah, 0xa270);
276 tmpVal = tmpVal & 0xFCFFFFFF;
277 tmpVal = tmpVal | (0x3 << 24);
278 REG_WRITE(ah, 0xa270, tmpVal);
279
280 /* Enable OLPC for chain 1 */
281
282 tmpVal = REG_READ(ah, 0xb270);
283 tmpVal = tmpVal & 0xFCFFFFFF;
284 tmpVal = tmpVal | (0x3 << 24);
285 REG_WRITE(ah, 0xb270, tmpVal);
286
287 /* Write the OLPC ref power for chain 0 */
288
289 if (chain == 0) {
290 tmpVal = REG_READ(ah, 0xa398);
291 tmpVal = tmpVal & 0xff00ffff;
292 a = (txPower)&0xff;
293 tmpVal = tmpVal | (a << 16);
294 REG_WRITE(ah, 0xa398, tmpVal);
295 }
296
297 /* Write the OLPC ref power for chain 1 */
298
299 if (chain == 1) {
300 tmpVal = REG_READ(ah, 0xb398);
301 tmpVal = tmpVal & 0xff00ffff;
302 a = (txPower)&0xff;
303 tmpVal = tmpVal | (a << 16);
304 REG_WRITE(ah, 0xb398, tmpVal);
305 }
306 }
307
308 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
309 struct ath9k_channel *chan,
310 int16_t *pTxPowerIndexOffset)
311 {
312 struct cal_data_per_freq_ar9287 *pRawDataset;
313 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
314 u8 *pCalBChans = NULL;
315 u16 pdGainOverlap_t2;
316 u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
317 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
318 u16 numPiers = 0, i, j;
319 u16 numXpdGain, xpdMask;
320 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
321 u32 reg32, regOffset, regChainOffset, regval;
322 int16_t modalIdx, diff = 0;
323 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
324
325 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
326 xpdMask = pEepData->modalHeader.xpdGain;
327
328 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
329 AR9287_EEP_MINOR_VER_2)
330 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
331 else
332 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
333 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
334
335 if (IS_CHAN_2GHZ(chan)) {
336 pCalBChans = pEepData->calFreqPier2G;
337 numPiers = AR9287_NUM_2G_CAL_PIERS;
338 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
339 pRawDatasetOpenLoop =
340 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
341 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
342 }
343 }
344
345 numXpdGain = 0;
346
347 /* Calculate the value of xpdgains from the xpdGain Mask */
348 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
349 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
350 if (numXpdGain >= AR5416_NUM_PD_GAINS)
351 break;
352 xpdGainValues[numXpdGain] =
353 (u16)(AR5416_PD_GAINS_IN_MASK-i);
354 numXpdGain++;
355 }
356 }
357
358 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
359 (numXpdGain - 1) & 0x3);
360 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
361 xpdGainValues[0]);
362 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
363 xpdGainValues[1]);
364 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
365 xpdGainValues[2]);
366
367 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
368 regChainOffset = i * 0x1000;
369
370 if (pEepData->baseEepHeader.txMask & (1 << i)) {
371 pRawDatasetOpenLoop =
372 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
373
374 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
375 int8_t txPower;
376 ar9287_eeprom_get_tx_gain_index(ah, chan,
377 pRawDatasetOpenLoop,
378 pCalBChans, numPiers,
379 &txPower);
380 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
381 } else {
382 pRawDataset =
383 (struct cal_data_per_freq_ar9287 *)
384 pEepData->calPierData2G[i];
385
386 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
387 pRawDataset,
388 pCalBChans, numPiers,
389 pdGainOverlap_t2,
390 gainBoundaries,
391 pdadcValues,
392 numXpdGain);
393 }
394
395 ENABLE_REGWRITE_BUFFER(ah);
396
397 if (i == 0) {
398 if (!ath9k_hw_ar9287_get_eeprom(ah,
399 EEP_OL_PWRCTRL)) {
400
401 regval = SM(pdGainOverlap_t2,
402 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
403 | SM(gainBoundaries[0],
404 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
405 | SM(gainBoundaries[1],
406 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
407 | SM(gainBoundaries[2],
408 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
409 | SM(gainBoundaries[3],
410 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4);
411
412 REG_WRITE(ah,
413 AR_PHY_TPCRG5 + regChainOffset,
414 regval);
415 }
416 }
417
418 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
419 pEepData->baseEepHeader.pwrTableOffset) {
420 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
421 (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
422 diff *= 2;
423
424 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
425 pdadcValues[j] = pdadcValues[j+diff];
426
427 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
428 j < AR5416_NUM_PDADC_VALUES; j++)
429 pdadcValues[j] =
430 pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
431 }
432
433 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
434 regOffset = AR_PHY_BASE +
435 (672 << 2) + regChainOffset;
436
437 for (j = 0; j < 32; j++) {
438 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0)
439 | ((pdadcValues[4*j + 1] & 0xFF) << 8)
440 | ((pdadcValues[4*j + 2] & 0xFF) << 16)
441 | ((pdadcValues[4*j + 3] & 0xFF) << 24);
442
443 REG_WRITE(ah, regOffset, reg32);
444 regOffset += 4;
445 }
446 }
447 REGWRITE_BUFFER_FLUSH(ah);
448 }
449 }
450
451 *pTxPowerIndexOffset = 0;
452 }
453
454 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
455 struct ath9k_channel *chan,
456 int16_t *ratesArray,
457 u16 cfgCtl,
458 u16 AntennaReduction,
459 u16 twiceMaxRegulatoryPower,
460 u16 powerLimit)
461 {
462 #define CMP_CTL \
463 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
464 pEepData->ctlIndex[i])
465
466 #define CMP_NO_CTL \
467 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
468 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
469
470 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
471 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
472
473 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
474 u16 twiceMaxEdgePower = MAX_RATE_POWER;
475 static const u16 tpScaleReductionTable[5] =
476 { 0, 3, 6, 9, MAX_RATE_POWER };
477 int i;
478 int16_t twiceLargestAntenna;
479 struct cal_ctl_data_ar9287 *rep;
480 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
481 targetPowerCck = {0, {0, 0, 0, 0} };
482 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
483 targetPowerCckExt = {0, {0, 0, 0, 0} };
484 struct cal_target_power_ht targetPowerHt20,
485 targetPowerHt40 = {0, {0, 0, 0, 0} };
486 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
487 static const u16 ctlModesFor11g[] = {
488 CTL_11B, CTL_11G, CTL_2GHT20,
489 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
490 };
491 u16 numCtlModes = 0;
492 const u16 *pCtlMode = NULL;
493 u16 ctlMode, freq;
494 struct chan_centers centers;
495 int tx_chainmask;
496 u16 twiceMinEdgePower;
497 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
498 tx_chainmask = ah->txchainmask;
499
500 ath9k_hw_get_channel_centers(ah, chan, &centers);
501
502 /* Compute TxPower reduction due to Antenna Gain */
503 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
504 pEepData->modalHeader.antennaGainCh[1]);
505 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
506 twiceLargestAntenna, 0);
507
508 /*
509 * scaledPower is the minimum of the user input power level
510 * and the regulatory allowed power level.
511 */
512 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
513
514 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
515 maxRegAllowedPower -=
516 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
517
518 scaledPower = min(powerLimit, maxRegAllowedPower);
519
520 /*
521 * Reduce scaled Power by number of chains active
522 * to get the per chain tx power level.
523 */
524 switch (ar5416_get_ntxchains(tx_chainmask)) {
525 case 1:
526 break;
527 case 2:
528 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
529 break;
530 case 3:
531 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
532 break;
533 }
534 scaledPower = max((u16)0, scaledPower);
535
536 /*
537 * Get TX power from EEPROM.
538 */
539 if (IS_CHAN_2GHZ(chan)) {
540 /* CTL_11B, CTL_11G, CTL_2GHT20 */
541 numCtlModes =
542 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
543
544 pCtlMode = ctlModesFor11g;
545
546 ath9k_hw_get_legacy_target_powers(ah, chan,
547 pEepData->calTargetPowerCck,
548 AR9287_NUM_2G_CCK_TARGET_POWERS,
549 &targetPowerCck, 4, false);
550 ath9k_hw_get_legacy_target_powers(ah, chan,
551 pEepData->calTargetPower2G,
552 AR9287_NUM_2G_20_TARGET_POWERS,
553 &targetPowerOfdm, 4, false);
554 ath9k_hw_get_target_powers(ah, chan,
555 pEepData->calTargetPower2GHT20,
556 AR9287_NUM_2G_20_TARGET_POWERS,
557 &targetPowerHt20, 8, false);
558
559 if (IS_CHAN_HT40(chan)) {
560 /* All 2G CTLs */
561 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
562 ath9k_hw_get_target_powers(ah, chan,
563 pEepData->calTargetPower2GHT40,
564 AR9287_NUM_2G_40_TARGET_POWERS,
565 &targetPowerHt40, 8, true);
566 ath9k_hw_get_legacy_target_powers(ah, chan,
567 pEepData->calTargetPowerCck,
568 AR9287_NUM_2G_CCK_TARGET_POWERS,
569 &targetPowerCckExt, 4, true);
570 ath9k_hw_get_legacy_target_powers(ah, chan,
571 pEepData->calTargetPower2G,
572 AR9287_NUM_2G_20_TARGET_POWERS,
573 &targetPowerOfdmExt, 4, true);
574 }
575 }
576
577 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
578 bool isHt40CtlMode =
579 (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false;
580
581 if (isHt40CtlMode)
582 freq = centers.synth_center;
583 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
584 freq = centers.ext_center;
585 else
586 freq = centers.ctl_center;
587
588 /* Walk through the CTL indices stored in EEPROM */
589 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
590 struct cal_ctl_edges *pRdEdgesPower;
591
592 /*
593 * Compare test group from regulatory channel list
594 * with test mode from pCtlMode list
595 */
596 if (CMP_CTL || CMP_NO_CTL) {
597 rep = &(pEepData->ctlData[i]);
598 pRdEdgesPower =
599 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
600
601 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
602 pRdEdgesPower,
603 IS_CHAN_2GHZ(chan),
604 AR5416_NUM_BAND_EDGES);
605
606 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
607 twiceMaxEdgePower = min(twiceMaxEdgePower,
608 twiceMinEdgePower);
609 } else {
610 twiceMaxEdgePower = twiceMinEdgePower;
611 break;
612 }
613 }
614 }
615
616 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
617
618 /* Apply ctl mode to correct target power set */
619 switch (pCtlMode[ctlMode]) {
620 case CTL_11B:
621 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
622 targetPowerCck.tPow2x[i] =
623 (u8)min((u16)targetPowerCck.tPow2x[i],
624 minCtlPower);
625 }
626 break;
627 case CTL_11A:
628 case CTL_11G:
629 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
630 targetPowerOfdm.tPow2x[i] =
631 (u8)min((u16)targetPowerOfdm.tPow2x[i],
632 minCtlPower);
633 }
634 break;
635 case CTL_5GHT20:
636 case CTL_2GHT20:
637 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
638 targetPowerHt20.tPow2x[i] =
639 (u8)min((u16)targetPowerHt20.tPow2x[i],
640 minCtlPower);
641 }
642 break;
643 case CTL_11B_EXT:
644 targetPowerCckExt.tPow2x[0] =
645 (u8)min((u16)targetPowerCckExt.tPow2x[0],
646 minCtlPower);
647 break;
648 case CTL_11A_EXT:
649 case CTL_11G_EXT:
650 targetPowerOfdmExt.tPow2x[0] =
651 (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
652 minCtlPower);
653 break;
654 case CTL_5GHT40:
655 case CTL_2GHT40:
656 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
657 targetPowerHt40.tPow2x[i] =
658 (u8)min((u16)targetPowerHt40.tPow2x[i],
659 minCtlPower);
660 }
661 break;
662 default:
663 break;
664 }
665 }
666
667 /* Now set the rates array */
668
669 ratesArray[rate6mb] =
670 ratesArray[rate9mb] =
671 ratesArray[rate12mb] =
672 ratesArray[rate18mb] =
673 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
674
675 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
676 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
677 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
678 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
679
680 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
681 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
682
683 if (IS_CHAN_2GHZ(chan)) {
684 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
685 ratesArray[rate2s] =
686 ratesArray[rate2l] = targetPowerCck.tPow2x[1];
687 ratesArray[rate5_5s] =
688 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
689 ratesArray[rate11s] =
690 ratesArray[rate11l] = targetPowerCck.tPow2x[3];
691 }
692 if (IS_CHAN_HT40(chan)) {
693 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
694 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
695
696 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
697 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
698 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
699
700 if (IS_CHAN_2GHZ(chan))
701 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
702 }
703
704 #undef CMP_CTL
705 #undef CMP_NO_CTL
706 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
707 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
708 }
709
710 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
711 struct ath9k_channel *chan, u16 cfgCtl,
712 u8 twiceAntennaReduction,
713 u8 twiceMaxRegulatoryPower,
714 u8 powerLimit, bool test)
715 {
716 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
717 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
718 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
719 int16_t ratesArray[Ar5416RateSize];
720 int16_t txPowerIndexOffset = 0;
721 u8 ht40PowerIncForPdadc = 2;
722 int i;
723
724 memset(ratesArray, 0, sizeof(ratesArray));
725
726 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
727 AR9287_EEP_MINOR_VER_2)
728 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
729
730 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
731 &ratesArray[0], cfgCtl,
732 twiceAntennaReduction,
733 twiceMaxRegulatoryPower,
734 powerLimit);
735
736 ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
737
738 regulatory->max_power_level = 0;
739 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
740 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
741 if (ratesArray[i] > MAX_RATE_POWER)
742 ratesArray[i] = MAX_RATE_POWER;
743
744 if (ratesArray[i] > regulatory->max_power_level)
745 regulatory->max_power_level = ratesArray[i];
746 }
747
748 if (test)
749 return;
750
751 if (IS_CHAN_2GHZ(chan))
752 i = rate1l;
753 else
754 i = rate6mb;
755
756 regulatory->max_power_level = ratesArray[i];
757
758 if (AR_SREV_9280_20_OR_LATER(ah)) {
759 for (i = 0; i < Ar5416RateSize; i++)
760 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
761 }
762
763 ENABLE_REGWRITE_BUFFER(ah);
764
765 /* OFDM power per rate */
766 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
767 ATH9K_POW_SM(ratesArray[rate18mb], 24)
768 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
769 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
770 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
771
772 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
773 ATH9K_POW_SM(ratesArray[rate54mb], 24)
774 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
775 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
776 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
777
778 /* CCK power per rate */
779 if (IS_CHAN_2GHZ(chan)) {
780 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
781 ATH9K_POW_SM(ratesArray[rate2s], 24)
782 | ATH9K_POW_SM(ratesArray[rate2l], 16)
783 | ATH9K_POW_SM(ratesArray[rateXr], 8)
784 | ATH9K_POW_SM(ratesArray[rate1l], 0));
785 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
786 ATH9K_POW_SM(ratesArray[rate11s], 24)
787 | ATH9K_POW_SM(ratesArray[rate11l], 16)
788 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
789 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
790 }
791
792 /* HT20 power per rate */
793 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
794 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
795 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
796 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
797 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
798
799 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
800 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
801 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
802 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
803 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
804
805 /* HT40 power per rate */
806 if (IS_CHAN_HT40(chan)) {
807 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
808 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
809 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
810 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
811 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
812 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
813
814 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
815 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
816 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
817 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
818 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
819 } else {
820 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
821 ATH9K_POW_SM(ratesArray[rateHt40_3] +
822 ht40PowerIncForPdadc, 24)
823 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
824 ht40PowerIncForPdadc, 16)
825 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
826 ht40PowerIncForPdadc, 8)
827 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
828 ht40PowerIncForPdadc, 0));
829
830 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
831 ATH9K_POW_SM(ratesArray[rateHt40_7] +
832 ht40PowerIncForPdadc, 24)
833 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
834 ht40PowerIncForPdadc, 16)
835 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
836 ht40PowerIncForPdadc, 8)
837 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
838 ht40PowerIncForPdadc, 0));
839 }
840
841 /* Dup/Ext power per rate */
842 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
843 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
844 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
845 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
846 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
847 }
848 REGWRITE_BUFFER_FLUSH(ah);
849 }
850
851 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
852 struct ath9k_channel *chan)
853 {
854 }
855
856 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
857 struct ath9k_channel *chan)
858 {
859 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
860 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
861 u32 regChainOffset, regval;
862 u8 txRxAttenLocal;
863 int i;
864
865 pModal = &eep->modalHeader;
866
867 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
868
869 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
870 regChainOffset = i * 0x1000;
871
872 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
873 pModal->antCtrlChain[i]);
874
875 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
876 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
877 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
878 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
879 SM(pModal->iqCalICh[i],
880 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
881 SM(pModal->iqCalQCh[i],
882 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
883
884 txRxAttenLocal = pModal->txRxAttenCh[i];
885
886 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
887 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
888 pModal->bswMargin[i]);
889 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
890 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
891 pModal->bswAtten[i]);
892 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
893 AR9280_PHY_RXGAIN_TXRX_ATTEN,
894 txRxAttenLocal);
895 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
896 AR9280_PHY_RXGAIN_TXRX_MARGIN,
897 pModal->rxTxMarginCh[i]);
898 }
899
900
901 if (IS_CHAN_HT40(chan))
902 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
903 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
904 else
905 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
906 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
907
908 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
909 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
910
911 REG_WRITE(ah, AR_PHY_RF_CTL4,
912 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
913 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
914 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
915 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
916
917 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
918 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
919
920 REG_RMW_FIELD(ah, AR_PHY_CCA,
921 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
922 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
923 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
924
925 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
926 regval &= ~(AR9287_AN_RF2G3_DB1 |
927 AR9287_AN_RF2G3_DB2 |
928 AR9287_AN_RF2G3_OB_CCK |
929 AR9287_AN_RF2G3_OB_PSK |
930 AR9287_AN_RF2G3_OB_QAM |
931 AR9287_AN_RF2G3_OB_PAL_OFF);
932 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
933 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
934 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
935 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
936 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
937 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
938
939 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
940
941 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
942 regval &= ~(AR9287_AN_RF2G3_DB1 |
943 AR9287_AN_RF2G3_DB2 |
944 AR9287_AN_RF2G3_OB_CCK |
945 AR9287_AN_RF2G3_OB_PSK |
946 AR9287_AN_RF2G3_OB_QAM |
947 AR9287_AN_RF2G3_OB_PAL_OFF);
948 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
949 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
950 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
951 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
952 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
953 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
954
955 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
956
957 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
958 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
959 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
960 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
961
962 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
963 AR9287_AN_TOP2_XPABIAS_LVL,
964 AR9287_AN_TOP2_XPABIAS_LVL_S,
965 pModal->xpaBiasLvl);
966 }
967
968 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
969 u16 i, bool is2GHz)
970 {
971 #define EEP_MAP9287_SPURCHAN \
972 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
973
974 struct ath_common *common = ath9k_hw_common(ah);
975 u16 spur_val = AR_NO_SPUR;
976
977 ath_dbg(common, ATH_DBG_ANI,
978 "Getting spur idx:%d is2Ghz:%d val:%x\n",
979 i, is2GHz, ah->config.spurchans[i][is2GHz]);
980
981 switch (ah->config.spurmode) {
982 case SPUR_DISABLE:
983 break;
984 case SPUR_ENABLE_IOCTL:
985 spur_val = ah->config.spurchans[i][is2GHz];
986 ath_dbg(common, ATH_DBG_ANI,
987 "Getting spur val from new loc. %d\n", spur_val);
988 break;
989 case SPUR_ENABLE_EEPROM:
990 spur_val = EEP_MAP9287_SPURCHAN;
991 break;
992 }
993
994 return spur_val;
995
996 #undef EEP_MAP9287_SPURCHAN
997 }
998
999 const struct eeprom_ops eep_ar9287_ops = {
1000 .check_eeprom = ath9k_hw_ar9287_check_eeprom,
1001 .get_eeprom = ath9k_hw_ar9287_get_eeprom,
1002 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1003 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1004 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1005 .set_board_values = ath9k_hw_ar9287_set_board_values,
1006 .set_addac = ath9k_hw_ar9287_set_addac,
1007 .set_txpower = ath9k_hw_ar9287_set_txpower,
1008 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel
1009 };
ubuntu-bionic-kernel mirror