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ath9k: Fix warnings from -Wunused-but-set-variable
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
96 else
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
103 }
104
105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
106 {
107 struct ath_common *common = ath9k_hw_common(ah);
108
109 return usecs * common->clockrate;
110 }
111
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
113 {
114 int i;
115
116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
124
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
128
129 return false;
130 }
131 EXPORT_SYMBOL(ath9k_hw_wait);
132
133 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135 {
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145 }
146
147 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
148 {
149 u32 retval;
150 int i;
151
152 for (i = 0, retval = 0; i < n; i++) {
153 retval = (retval << 1) | (val & 1);
154 val >>= 1;
155 }
156 return retval;
157 }
158
159 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
160 u8 phy, int kbps,
161 u32 frameLen, u16 rateix,
162 bool shortPreamble)
163 {
164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
165
166 if (kbps == 0)
167 return 0;
168
169 switch (phy) {
170 case WLAN_RC_PHY_CCK:
171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
172 if (shortPreamble)
173 phyTime >>= 1;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
176 break;
177 case WLAN_RC_PHY_OFDM:
178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
193 } else {
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
199 }
200 break;
201 default:
202 ath_err(ath9k_hw_common(ah),
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
204 txTime = 0;
205 break;
206 }
207
208 return txTime;
209 }
210 EXPORT_SYMBOL(ath9k_hw_computetxtime);
211
212 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
215 {
216 int8_t extoff;
217
218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
221 return;
222 }
223
224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
228 extoff = 1;
229 } else {
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
232 extoff = -1;
233 }
234
235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
237 /* 25 MHz spacing is supported by hw but not on upper layers */
238 centers->ext_center =
239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
240 }
241
242 /******************/
243 /* Chip Revisions */
244 /******************/
245
246 static void ath9k_hw_read_revisions(struct ath_hw *ah)
247 {
248 u32 val;
249
250 switch (ah->hw_version.devid) {
251 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
253 break;
254 case AR9300_DEVID_AR9340:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
256 val = REG_READ(ah, AR_SREV);
257 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
258 return;
259 }
260
261 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
262
263 if (val == 0xFF) {
264 val = REG_READ(ah, AR_SREV);
265 ah->hw_version.macVersion =
266 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
267 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
268 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
269 } else {
270 if (!AR_SREV_9100(ah))
271 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
272
273 ah->hw_version.macRev = val & AR_SREV_REVISION;
274
275 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
276 ah->is_pciexpress = true;
277 }
278 }
279
280 /************************************/
281 /* HW Attach, Detach, Init Routines */
282 /************************************/
283
284 static void ath9k_hw_disablepcie(struct ath_hw *ah)
285 {
286 if (!AR_SREV_5416(ah))
287 return;
288
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
298
299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
300 }
301
302 /* This should work for all families including legacy */
303 static bool ath9k_hw_chip_test(struct ath_hw *ah)
304 {
305 struct ath_common *common = ath9k_hw_common(ah);
306 u32 regAddr[2] = { AR_STA_ID0 };
307 u32 regHold[2];
308 static const u32 patternData[4] = {
309 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
310 };
311 int i, j, loop_max;
312
313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
314 loop_max = 2;
315 regAddr[1] = AR_PHY_BASE + (8 << 2);
316 } else
317 loop_max = 1;
318
319 for (i = 0; i < loop_max; i++) {
320 u32 addr = regAddr[i];
321 u32 wrData, rdData;
322
323 regHold[i] = REG_READ(ah, addr);
324 for (j = 0; j < 0x100; j++) {
325 wrData = (j << 16) | j;
326 REG_WRITE(ah, addr, wrData);
327 rdData = REG_READ(ah, addr);
328 if (rdData != wrData) {
329 ath_err(common,
330 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
331 addr, wrData, rdData);
332 return false;
333 }
334 }
335 for (j = 0; j < 4; j++) {
336 wrData = patternData[j];
337 REG_WRITE(ah, addr, wrData);
338 rdData = REG_READ(ah, addr);
339 if (wrData != rdData) {
340 ath_err(common,
341 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
342 addr, wrData, rdData);
343 return false;
344 }
345 }
346 REG_WRITE(ah, regAddr[i], regHold[i]);
347 }
348 udelay(100);
349
350 return true;
351 }
352
353 static void ath9k_hw_init_config(struct ath_hw *ah)
354 {
355 int i;
356
357 ah->config.dma_beacon_response_time = 2;
358 ah->config.sw_beacon_response_time = 10;
359 ah->config.additional_swba_backoff = 0;
360 ah->config.ack_6mb = 0x0;
361 ah->config.cwm_ignore_extcca = 0;
362 ah->config.pcie_powersave_enable = 0;
363 ah->config.pcie_clock_req = 0;
364 ah->config.pcie_waen = 0;
365 ah->config.analog_shiftreg = 1;
366 ah->config.enable_ani = true;
367
368 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
369 ah->config.spurchans[i][0] = AR_NO_SPUR;
370 ah->config.spurchans[i][1] = AR_NO_SPUR;
371 }
372
373 /* PAPRD needs some more work to be enabled */
374 ah->config.paprd_disable = 1;
375
376 ah->config.rx_intr_mitigation = true;
377 ah->config.pcieSerDesWrite = true;
378
379 /*
380 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
381 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
382 * This means we use it for all AR5416 devices, and the few
383 * minor PCI AR9280 devices out there.
384 *
385 * Serialization is required because these devices do not handle
386 * well the case of two concurrent reads/writes due to the latency
387 * involved. During one read/write another read/write can be issued
388 * on another CPU while the previous read/write may still be working
389 * on our hardware, if we hit this case the hardware poops in a loop.
390 * We prevent this by serializing reads and writes.
391 *
392 * This issue is not present on PCI-Express devices or pre-AR5416
393 * devices (legacy, 802.11abg).
394 */
395 if (num_possible_cpus() > 1)
396 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
397 }
398
399 static void ath9k_hw_init_defaults(struct ath_hw *ah)
400 {
401 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
402
403 regulatory->country_code = CTRY_DEFAULT;
404 regulatory->power_limit = MAX_RATE_POWER;
405 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
406
407 ah->hw_version.magic = AR5416_MAGIC;
408 ah->hw_version.subvendorid = 0;
409
410 ah->atim_window = 0;
411 ah->sta_id1_defaults =
412 AR_STA_ID1_CRPT_MIC_ENABLE |
413 AR_STA_ID1_MCAST_KSRCH;
414 if (AR_SREV_9100(ah))
415 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
416 ah->enable_32kHz_clock = DONT_USE_32KHZ;
417 ah->slottime = 20;
418 ah->globaltxtimeout = (u32) -1;
419 ah->power_mode = ATH9K_PM_UNDEFINED;
420 }
421
422 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
423 {
424 struct ath_common *common = ath9k_hw_common(ah);
425 u32 sum;
426 int i;
427 u16 eeval;
428 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
429
430 sum = 0;
431 for (i = 0; i < 3; i++) {
432 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
433 sum += eeval;
434 common->macaddr[2 * i] = eeval >> 8;
435 common->macaddr[2 * i + 1] = eeval & 0xff;
436 }
437 if (sum == 0 || sum == 0xffff * 3)
438 return -EADDRNOTAVAIL;
439
440 return 0;
441 }
442
443 static int ath9k_hw_post_init(struct ath_hw *ah)
444 {
445 struct ath_common *common = ath9k_hw_common(ah);
446 int ecode;
447
448 if (common->bus_ops->ath_bus_type != ATH_USB) {
449 if (!ath9k_hw_chip_test(ah))
450 return -ENODEV;
451 }
452
453 if (!AR_SREV_9300_20_OR_LATER(ah)) {
454 ecode = ar9002_hw_rf_claim(ah);
455 if (ecode != 0)
456 return ecode;
457 }
458
459 ecode = ath9k_hw_eeprom_init(ah);
460 if (ecode != 0)
461 return ecode;
462
463 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
464 "Eeprom VER: %d, REV: %d\n",
465 ah->eep_ops->get_eeprom_ver(ah),
466 ah->eep_ops->get_eeprom_rev(ah));
467
468 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
469 if (ecode) {
470 ath_err(ath9k_hw_common(ah),
471 "Failed allocating banks for external radio\n");
472 ath9k_hw_rf_free_ext_banks(ah);
473 return ecode;
474 }
475
476 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
477 ath9k_hw_ani_setup(ah);
478 ath9k_hw_ani_init(ah);
479 }
480
481 return 0;
482 }
483
484 static void ath9k_hw_attach_ops(struct ath_hw *ah)
485 {
486 if (AR_SREV_9300_20_OR_LATER(ah))
487 ar9003_hw_attach_ops(ah);
488 else
489 ar9002_hw_attach_ops(ah);
490 }
491
492 /* Called for all hardware families */
493 static int __ath9k_hw_init(struct ath_hw *ah)
494 {
495 struct ath_common *common = ath9k_hw_common(ah);
496 int r = 0;
497
498 ath9k_hw_read_revisions(ah);
499
500 /*
501 * Read back AR_WA into a permanent copy and set bits 14 and 17.
502 * We need to do this to avoid RMW of this register. We cannot
503 * read the reg when chip is asleep.
504 */
505 ah->WARegVal = REG_READ(ah, AR_WA);
506 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
507 AR_WA_ASPM_TIMER_BASED_DISABLE);
508
509 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
510 ath_err(common, "Couldn't reset chip\n");
511 return -EIO;
512 }
513
514 ath9k_hw_init_defaults(ah);
515 ath9k_hw_init_config(ah);
516
517 ath9k_hw_attach_ops(ah);
518
519 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
520 ath_err(common, "Couldn't wakeup chip\n");
521 return -EIO;
522 }
523
524 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
525 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
526 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
527 !ah->is_pciexpress)) {
528 ah->config.serialize_regmode =
529 SER_REG_MODE_ON;
530 } else {
531 ah->config.serialize_regmode =
532 SER_REG_MODE_OFF;
533 }
534 }
535
536 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
537 ah->config.serialize_regmode);
538
539 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
540 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
541 else
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
543
544 switch (ah->hw_version.macVersion) {
545 case AR_SREV_VERSION_5416_PCI:
546 case AR_SREV_VERSION_5416_PCIE:
547 case AR_SREV_VERSION_9160:
548 case AR_SREV_VERSION_9100:
549 case AR_SREV_VERSION_9280:
550 case AR_SREV_VERSION_9285:
551 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300:
554 case AR_SREV_VERSION_9485:
555 case AR_SREV_VERSION_9340:
556 break;
557 default:
558 ath_err(common,
559 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
560 ah->hw_version.macVersion, ah->hw_version.macRev);
561 return -EOPNOTSUPP;
562 }
563
564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
565 ah->is_pciexpress = false;
566
567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
568 ath9k_hw_init_cal_settings(ah);
569
570 ah->ani_function = ATH9K_ANI_ALL;
571 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
572 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
573 if (!AR_SREV_9300_20_OR_LATER(ah))
574 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
575
576 ath9k_hw_init_mode_regs(ah);
577
578
579 if (ah->is_pciexpress)
580 ath9k_hw_configpcipowersave(ah, 0, 0);
581 else
582 ath9k_hw_disablepcie(ah);
583
584 if (!AR_SREV_9300_20_OR_LATER(ah))
585 ar9002_hw_cck_chan14_spread(ah);
586
587 r = ath9k_hw_post_init(ah);
588 if (r)
589 return r;
590
591 ath9k_hw_init_mode_gain_regs(ah);
592 r = ath9k_hw_fill_cap_info(ah);
593 if (r)
594 return r;
595
596 r = ath9k_hw_init_macaddr(ah);
597 if (r) {
598 ath_err(common, "Failed to initialize MAC address\n");
599 return r;
600 }
601
602 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
603 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
604 else
605 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
606
607 ah->bb_watchdog_timeout_ms = 25;
608
609 common->state = ATH_HW_INITIALIZED;
610
611 return 0;
612 }
613
614 int ath9k_hw_init(struct ath_hw *ah)
615 {
616 int ret;
617 struct ath_common *common = ath9k_hw_common(ah);
618
619 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
620 switch (ah->hw_version.devid) {
621 case AR5416_DEVID_PCI:
622 case AR5416_DEVID_PCIE:
623 case AR5416_AR9100_DEVID:
624 case AR9160_DEVID_PCI:
625 case AR9280_DEVID_PCI:
626 case AR9280_DEVID_PCIE:
627 case AR9285_DEVID_PCIE:
628 case AR9287_DEVID_PCI:
629 case AR9287_DEVID_PCIE:
630 case AR2427_DEVID_PCIE:
631 case AR9300_DEVID_PCIE:
632 case AR9300_DEVID_AR9485_PCIE:
633 case AR9300_DEVID_AR9340:
634 break;
635 default:
636 if (common->bus_ops->ath_bus_type == ATH_USB)
637 break;
638 ath_err(common, "Hardware device ID 0x%04x not supported\n",
639 ah->hw_version.devid);
640 return -EOPNOTSUPP;
641 }
642
643 ret = __ath9k_hw_init(ah);
644 if (ret) {
645 ath_err(common,
646 "Unable to initialize hardware; initialization status: %d\n",
647 ret);
648 return ret;
649 }
650
651 return 0;
652 }
653 EXPORT_SYMBOL(ath9k_hw_init);
654
655 static void ath9k_hw_init_qos(struct ath_hw *ah)
656 {
657 ENABLE_REGWRITE_BUFFER(ah);
658
659 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
660 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
661
662 REG_WRITE(ah, AR_QOS_NO_ACK,
663 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
664 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
665 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
666
667 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
668 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
671 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
672
673 REGWRITE_BUFFER_FLUSH(ah);
674 }
675
676 unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
677 {
678 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
679 udelay(100);
680 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
681
682 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
683 udelay(100);
684
685 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
686 }
687 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
688
689 #define DPLL3_PHASE_SHIFT_VAL 0x1
690 static void ath9k_hw_init_pll(struct ath_hw *ah,
691 struct ath9k_channel *chan)
692 {
693 u32 pll;
694
695 if (AR_SREV_9485(ah)) {
696
697 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
698 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
699 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
700 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
701 AR_CH0_DPLL2_KD, 0x40);
702 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
703 AR_CH0_DPLL2_KI, 0x4);
704
705 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
706 AR_CH0_BB_DPLL1_REFDIV, 0x5);
707 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
708 AR_CH0_BB_DPLL1_NINI, 0x58);
709 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
710 AR_CH0_BB_DPLL1_NFRAC, 0x0);
711
712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
713 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
714 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
715 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
716 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
717 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
718
719 /* program BB PLL phase_shift to 0x6 */
720 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
721 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
722
723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
724 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
725 udelay(1000);
726
727 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
728 AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
729 } else if (AR_SREV_9340(ah)) {
730 u32 regval, pll2_divint, pll2_divfrac, refdiv;
731
732 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
733 udelay(1000);
734
735 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
736 udelay(100);
737
738 if (ah->is_clk_25mhz) {
739 pll2_divint = 0x54;
740 pll2_divfrac = 0x1eb85;
741 refdiv = 3;
742 } else {
743 pll2_divint = 88;
744 pll2_divfrac = 0;
745 refdiv = 5;
746 }
747
748 regval = REG_READ(ah, AR_PHY_PLL_MODE);
749 regval |= (0x1 << 16);
750 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
751 udelay(100);
752
753 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
754 (pll2_divint << 18) | pll2_divfrac);
755 udelay(100);
756
757 regval = REG_READ(ah, AR_PHY_PLL_MODE);
758 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
759 (0x4 << 26) | (0x18 << 19);
760 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
761 REG_WRITE(ah, AR_PHY_PLL_MODE,
762 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
763 udelay(1000);
764 }
765
766 pll = ath9k_hw_compute_pll_control(ah, chan);
767
768 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
769
770 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
771 udelay(1000);
772
773 /* Switch the core clock for ar9271 to 117Mhz */
774 if (AR_SREV_9271(ah)) {
775 udelay(500);
776 REG_WRITE(ah, 0x50040, 0x304);
777 }
778
779 udelay(RTC_PLL_SETTLE_DELAY);
780
781 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
782
783 if (AR_SREV_9340(ah)) {
784 if (ah->is_clk_25mhz) {
785 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
786 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
787 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
788 } else {
789 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
790 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
791 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
792 }
793 udelay(100);
794 }
795 }
796
797 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
798 enum nl80211_iftype opmode)
799 {
800 u32 sync_default = AR_INTR_SYNC_DEFAULT;
801 u32 imr_reg = AR_IMR_TXERR |
802 AR_IMR_TXURN |
803 AR_IMR_RXERR |
804 AR_IMR_RXORN |
805 AR_IMR_BCNMISC;
806
807 if (AR_SREV_9340(ah))
808 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
809
810 if (AR_SREV_9300_20_OR_LATER(ah)) {
811 imr_reg |= AR_IMR_RXOK_HP;
812 if (ah->config.rx_intr_mitigation)
813 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
814 else
815 imr_reg |= AR_IMR_RXOK_LP;
816
817 } else {
818 if (ah->config.rx_intr_mitigation)
819 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
820 else
821 imr_reg |= AR_IMR_RXOK;
822 }
823
824 if (ah->config.tx_intr_mitigation)
825 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
826 else
827 imr_reg |= AR_IMR_TXOK;
828
829 if (opmode == NL80211_IFTYPE_AP)
830 imr_reg |= AR_IMR_MIB;
831
832 ENABLE_REGWRITE_BUFFER(ah);
833
834 REG_WRITE(ah, AR_IMR, imr_reg);
835 ah->imrs2_reg |= AR_IMR_S2_GTT;
836 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
837
838 if (!AR_SREV_9100(ah)) {
839 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
840 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
841 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
842 }
843
844 REGWRITE_BUFFER_FLUSH(ah);
845
846 if (AR_SREV_9300_20_OR_LATER(ah)) {
847 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
848 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
849 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
850 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
851 }
852 }
853
854 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
855 {
856 u32 val = ath9k_hw_mac_to_clks(ah, us);
857 val = min(val, (u32) 0xFFFF);
858 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
859 }
860
861 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
862 {
863 u32 val = ath9k_hw_mac_to_clks(ah, us);
864 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
865 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
866 }
867
868 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
869 {
870 u32 val = ath9k_hw_mac_to_clks(ah, us);
871 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
872 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
873 }
874
875 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
876 {
877 if (tu > 0xFFFF) {
878 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
879 "bad global tx timeout %u\n", tu);
880 ah->globaltxtimeout = (u32) -1;
881 return false;
882 } else {
883 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
884 ah->globaltxtimeout = tu;
885 return true;
886 }
887 }
888
889 void ath9k_hw_init_global_settings(struct ath_hw *ah)
890 {
891 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
892 int acktimeout;
893 int slottime;
894 int sifstime;
895
896 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
897 ah->misc_mode);
898
899 if (ah->misc_mode != 0)
900 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
901
902 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
903 sifstime = 16;
904 else
905 sifstime = 10;
906
907 /* As defined by IEEE 802.11-2007 17.3.8.6 */
908 slottime = ah->slottime + 3 * ah->coverage_class;
909 acktimeout = slottime + sifstime;
910
911 /*
912 * Workaround for early ACK timeouts, add an offset to match the
913 * initval's 64us ack timeout value.
914 * This was initially only meant to work around an issue with delayed
915 * BA frames in some implementations, but it has been found to fix ACK
916 * timeout issues in other cases as well.
917 */
918 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
919 acktimeout += 64 - sifstime - ah->slottime;
920
921 ath9k_hw_setslottime(ah, ah->slottime);
922 ath9k_hw_set_ack_timeout(ah, acktimeout);
923 ath9k_hw_set_cts_timeout(ah, acktimeout);
924 if (ah->globaltxtimeout != (u32) -1)
925 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
926 }
927 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
928
929 void ath9k_hw_deinit(struct ath_hw *ah)
930 {
931 struct ath_common *common = ath9k_hw_common(ah);
932
933 if (common->state < ATH_HW_INITIALIZED)
934 goto free_hw;
935
936 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
937
938 free_hw:
939 ath9k_hw_rf_free_ext_banks(ah);
940 }
941 EXPORT_SYMBOL(ath9k_hw_deinit);
942
943 /*******/
944 /* INI */
945 /*******/
946
947 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
948 {
949 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
950
951 if (IS_CHAN_B(chan))
952 ctl |= CTL_11B;
953 else if (IS_CHAN_G(chan))
954 ctl |= CTL_11G;
955 else
956 ctl |= CTL_11A;
957
958 return ctl;
959 }
960
961 /****************************************/
962 /* Reset and Channel Switching Routines */
963 /****************************************/
964
965 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
966 {
967 struct ath_common *common = ath9k_hw_common(ah);
968
969 ENABLE_REGWRITE_BUFFER(ah);
970
971 /*
972 * set AHB_MODE not to do cacheline prefetches
973 */
974 if (!AR_SREV_9300_20_OR_LATER(ah))
975 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
976
977 /*
978 * let mac dma reads be in 128 byte chunks
979 */
980 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
981
982 REGWRITE_BUFFER_FLUSH(ah);
983
984 /*
985 * Restore TX Trigger Level to its pre-reset value.
986 * The initial value depends on whether aggregation is enabled, and is
987 * adjusted whenever underruns are detected.
988 */
989 if (!AR_SREV_9300_20_OR_LATER(ah))
990 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
991
992 ENABLE_REGWRITE_BUFFER(ah);
993
994 /*
995 * let mac dma writes be in 128 byte chunks
996 */
997 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
998
999 /*
1000 * Setup receive FIFO threshold to hold off TX activities
1001 */
1002 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1003
1004 if (AR_SREV_9300_20_OR_LATER(ah)) {
1005 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1006 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1007
1008 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1009 ah->caps.rx_status_len);
1010 }
1011
1012 /*
1013 * reduce the number of usable entries in PCU TXBUF to avoid
1014 * wrap around issues.
1015 */
1016 if (AR_SREV_9285(ah)) {
1017 /* For AR9285 the number of Fifos are reduced to half.
1018 * So set the usable tx buf size also to half to
1019 * avoid data/delimiter underruns
1020 */
1021 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1022 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1023 } else if (!AR_SREV_9271(ah)) {
1024 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1025 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1026 }
1027
1028 REGWRITE_BUFFER_FLUSH(ah);
1029
1030 if (AR_SREV_9300_20_OR_LATER(ah))
1031 ath9k_hw_reset_txstatus_ring(ah);
1032 }
1033
1034 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1035 {
1036 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1037 u32 set = AR_STA_ID1_KSRCH_MODE;
1038
1039 switch (opmode) {
1040 case NL80211_IFTYPE_ADHOC:
1041 case NL80211_IFTYPE_MESH_POINT:
1042 set |= AR_STA_ID1_ADHOC;
1043 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1044 break;
1045 case NL80211_IFTYPE_AP:
1046 set |= AR_STA_ID1_STA_AP;
1047 /* fall through */
1048 case NL80211_IFTYPE_STATION:
1049 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1050 break;
1051 default:
1052 if (!ah->is_monitoring)
1053 set = 0;
1054 break;
1055 }
1056 REG_RMW(ah, AR_STA_ID1, set, mask);
1057 }
1058
1059 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1060 u32 *coef_mantissa, u32 *coef_exponent)
1061 {
1062 u32 coef_exp, coef_man;
1063
1064 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1065 if ((coef_scaled >> coef_exp) & 0x1)
1066 break;
1067
1068 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1069
1070 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1071
1072 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1073 *coef_exponent = coef_exp - 16;
1074 }
1075
1076 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1077 {
1078 u32 rst_flags;
1079 u32 tmpReg;
1080
1081 if (AR_SREV_9100(ah)) {
1082 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1083 AR_RTC_DERIVED_CLK_PERIOD, 1);
1084 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1085 }
1086
1087 ENABLE_REGWRITE_BUFFER(ah);
1088
1089 if (AR_SREV_9300_20_OR_LATER(ah)) {
1090 REG_WRITE(ah, AR_WA, ah->WARegVal);
1091 udelay(10);
1092 }
1093
1094 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1095 AR_RTC_FORCE_WAKE_ON_INT);
1096
1097 if (AR_SREV_9100(ah)) {
1098 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1099 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1100 } else {
1101 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1102 if (tmpReg &
1103 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1104 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1105 u32 val;
1106 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1107
1108 val = AR_RC_HOSTIF;
1109 if (!AR_SREV_9300_20_OR_LATER(ah))
1110 val |= AR_RC_AHB;
1111 REG_WRITE(ah, AR_RC, val);
1112
1113 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1114 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1115
1116 rst_flags = AR_RTC_RC_MAC_WARM;
1117 if (type == ATH9K_RESET_COLD)
1118 rst_flags |= AR_RTC_RC_MAC_COLD;
1119 }
1120
1121 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1122
1123 REGWRITE_BUFFER_FLUSH(ah);
1124
1125 udelay(50);
1126
1127 REG_WRITE(ah, AR_RTC_RC, 0);
1128 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1129 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1130 "RTC stuck in MAC reset\n");
1131 return false;
1132 }
1133
1134 if (!AR_SREV_9100(ah))
1135 REG_WRITE(ah, AR_RC, 0);
1136
1137 if (AR_SREV_9100(ah))
1138 udelay(50);
1139
1140 return true;
1141 }
1142
1143 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1144 {
1145 ENABLE_REGWRITE_BUFFER(ah);
1146
1147 if (AR_SREV_9300_20_OR_LATER(ah)) {
1148 REG_WRITE(ah, AR_WA, ah->WARegVal);
1149 udelay(10);
1150 }
1151
1152 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1153 AR_RTC_FORCE_WAKE_ON_INT);
1154
1155 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1156 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1157
1158 REG_WRITE(ah, AR_RTC_RESET, 0);
1159
1160 REGWRITE_BUFFER_FLUSH(ah);
1161
1162 if (!AR_SREV_9300_20_OR_LATER(ah))
1163 udelay(2);
1164
1165 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1166 REG_WRITE(ah, AR_RC, 0);
1167
1168 REG_WRITE(ah, AR_RTC_RESET, 1);
1169
1170 if (!ath9k_hw_wait(ah,
1171 AR_RTC_STATUS,
1172 AR_RTC_STATUS_M,
1173 AR_RTC_STATUS_ON,
1174 AH_WAIT_TIMEOUT)) {
1175 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1176 "RTC not waking up\n");
1177 return false;
1178 }
1179
1180 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1181 }
1182
1183 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1184 {
1185 if (AR_SREV_9300_20_OR_LATER(ah)) {
1186 REG_WRITE(ah, AR_WA, ah->WARegVal);
1187 udelay(10);
1188 }
1189
1190 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1191 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1192
1193 switch (type) {
1194 case ATH9K_RESET_POWER_ON:
1195 return ath9k_hw_set_reset_power_on(ah);
1196 case ATH9K_RESET_WARM:
1197 case ATH9K_RESET_COLD:
1198 return ath9k_hw_set_reset(ah, type);
1199 default:
1200 return false;
1201 }
1202 }
1203
1204 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1205 struct ath9k_channel *chan)
1206 {
1207 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1208 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1209 return false;
1210 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1211 return false;
1212
1213 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1214 return false;
1215
1216 ah->chip_fullsleep = false;
1217 ath9k_hw_init_pll(ah, chan);
1218 ath9k_hw_set_rfmode(ah, chan);
1219
1220 return true;
1221 }
1222
1223 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1224 struct ath9k_channel *chan)
1225 {
1226 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1227 struct ath_common *common = ath9k_hw_common(ah);
1228 struct ieee80211_channel *channel = chan->chan;
1229 u32 qnum;
1230 int r;
1231
1232 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1233 if (ath9k_hw_numtxpending(ah, qnum)) {
1234 ath_dbg(common, ATH_DBG_QUEUE,
1235 "Transmit frames pending on queue %d\n", qnum);
1236 return false;
1237 }
1238 }
1239
1240 if (!ath9k_hw_rfbus_req(ah)) {
1241 ath_err(common, "Could not kill baseband RX\n");
1242 return false;
1243 }
1244
1245 ath9k_hw_set_channel_regs(ah, chan);
1246
1247 r = ath9k_hw_rf_set_freq(ah, chan);
1248 if (r) {
1249 ath_err(common, "Failed to set channel\n");
1250 return false;
1251 }
1252 ath9k_hw_set_clockrate(ah);
1253
1254 ah->eep_ops->set_txpower(ah, chan,
1255 ath9k_regd_get_ctl(regulatory, chan),
1256 channel->max_antenna_gain * 2,
1257 channel->max_power * 2,
1258 min((u32) MAX_RATE_POWER,
1259 (u32) regulatory->power_limit), false);
1260
1261 ath9k_hw_rfbus_done(ah);
1262
1263 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1264 ath9k_hw_set_delta_slope(ah, chan);
1265
1266 ath9k_hw_spur_mitigate_freq(ah, chan);
1267
1268 return true;
1269 }
1270
1271 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1272 {
1273 u32 gpio_mask = ah->gpio_mask;
1274 int i;
1275
1276 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1277 if (!(gpio_mask & 1))
1278 continue;
1279
1280 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1281 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1282 }
1283 }
1284
1285 bool ath9k_hw_check_alive(struct ath_hw *ah)
1286 {
1287 int count = 50;
1288 u32 reg;
1289
1290 if (AR_SREV_9285_12_OR_LATER(ah))
1291 return true;
1292
1293 do {
1294 reg = REG_READ(ah, AR_OBS_BUS_1);
1295
1296 if ((reg & 0x7E7FFFEF) == 0x00702400)
1297 continue;
1298
1299 switch (reg & 0x7E000B00) {
1300 case 0x1E000000:
1301 case 0x52000B00:
1302 case 0x18000B00:
1303 continue;
1304 default:
1305 return true;
1306 }
1307 } while (count-- > 0);
1308
1309 return false;
1310 }
1311 EXPORT_SYMBOL(ath9k_hw_check_alive);
1312
1313 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1314 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1315 {
1316 struct ath_common *common = ath9k_hw_common(ah);
1317 u32 saveLedState;
1318 struct ath9k_channel *curchan = ah->curchan;
1319 u32 saveDefAntenna;
1320 u32 macStaId1;
1321 u64 tsf = 0;
1322 int i, r;
1323
1324 ah->txchainmask = common->tx_chainmask;
1325 ah->rxchainmask = common->rx_chainmask;
1326
1327 if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) {
1328 ath9k_hw_abortpcurecv(ah);
1329 if (!ath9k_hw_stopdmarecv(ah)) {
1330 ath_dbg(common, ATH_DBG_XMIT,
1331 "Failed to stop receive dma\n");
1332 bChannelChange = false;
1333 }
1334 }
1335
1336 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1337 return -EIO;
1338
1339 if (curchan && !ah->chip_fullsleep)
1340 ath9k_hw_getnf(ah, curchan);
1341
1342 ah->caldata = caldata;
1343 if (caldata &&
1344 (chan->channel != caldata->channel ||
1345 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1346 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1347 /* Operating channel changed, reset channel calibration data */
1348 memset(caldata, 0, sizeof(*caldata));
1349 ath9k_init_nfcal_hist_buffer(ah, chan);
1350 }
1351
1352 if (bChannelChange &&
1353 (ah->chip_fullsleep != true) &&
1354 (ah->curchan != NULL) &&
1355 (chan->channel != ah->curchan->channel) &&
1356 ((chan->channelFlags & CHANNEL_ALL) ==
1357 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1358 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1359
1360 if (ath9k_hw_channel_change(ah, chan)) {
1361 ath9k_hw_loadnf(ah, ah->curchan);
1362 ath9k_hw_start_nfcal(ah, true);
1363 if (AR_SREV_9271(ah))
1364 ar9002_hw_load_ani_reg(ah, chan);
1365 return 0;
1366 }
1367 }
1368
1369 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1370 if (saveDefAntenna == 0)
1371 saveDefAntenna = 1;
1372
1373 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1374
1375 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1376 if (AR_SREV_9100(ah) ||
1377 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1378 tsf = ath9k_hw_gettsf64(ah);
1379
1380 saveLedState = REG_READ(ah, AR_CFG_LED) &
1381 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1382 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1383
1384 ath9k_hw_mark_phy_inactive(ah);
1385
1386 ah->paprd_table_write_done = false;
1387
1388 /* Only required on the first reset */
1389 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1390 REG_WRITE(ah,
1391 AR9271_RESET_POWER_DOWN_CONTROL,
1392 AR9271_RADIO_RF_RST);
1393 udelay(50);
1394 }
1395
1396 if (!ath9k_hw_chip_reset(ah, chan)) {
1397 ath_err(common, "Chip reset failed\n");
1398 return -EINVAL;
1399 }
1400
1401 /* Only required on the first reset */
1402 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1403 ah->htc_reset_init = false;
1404 REG_WRITE(ah,
1405 AR9271_RESET_POWER_DOWN_CONTROL,
1406 AR9271_GATE_MAC_CTL);
1407 udelay(50);
1408 }
1409
1410 /* Restore TSF */
1411 if (tsf)
1412 ath9k_hw_settsf64(ah, tsf);
1413
1414 if (AR_SREV_9280_20_OR_LATER(ah))
1415 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1416
1417 if (!AR_SREV_9300_20_OR_LATER(ah))
1418 ar9002_hw_enable_async_fifo(ah);
1419
1420 r = ath9k_hw_process_ini(ah, chan);
1421 if (r)
1422 return r;
1423
1424 /*
1425 * Some AR91xx SoC devices frequently fail to accept TSF writes
1426 * right after the chip reset. When that happens, write a new
1427 * value after the initvals have been applied, with an offset
1428 * based on measured time difference
1429 */
1430 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1431 tsf += 1500;
1432 ath9k_hw_settsf64(ah, tsf);
1433 }
1434
1435 /* Setup MFP options for CCMP */
1436 if (AR_SREV_9280_20_OR_LATER(ah)) {
1437 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1438 * frames when constructing CCMP AAD. */
1439 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1440 0xc7ff);
1441 ah->sw_mgmt_crypto = false;
1442 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1443 /* Disable hardware crypto for management frames */
1444 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1445 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1446 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1447 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1448 ah->sw_mgmt_crypto = true;
1449 } else
1450 ah->sw_mgmt_crypto = true;
1451
1452 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1453 ath9k_hw_set_delta_slope(ah, chan);
1454
1455 ath9k_hw_spur_mitigate_freq(ah, chan);
1456 ah->eep_ops->set_board_values(ah, chan);
1457
1458 ENABLE_REGWRITE_BUFFER(ah);
1459
1460 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1461 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1462 | macStaId1
1463 | AR_STA_ID1_RTS_USE_DEF
1464 | (ah->config.
1465 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1466 | ah->sta_id1_defaults);
1467 ath_hw_setbssidmask(common);
1468 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1469 ath9k_hw_write_associd(ah);
1470 REG_WRITE(ah, AR_ISR, ~0);
1471 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1472
1473 REGWRITE_BUFFER_FLUSH(ah);
1474
1475 ath9k_hw_set_operating_mode(ah, ah->opmode);
1476
1477 r = ath9k_hw_rf_set_freq(ah, chan);
1478 if (r)
1479 return r;
1480
1481 ath9k_hw_set_clockrate(ah);
1482
1483 ENABLE_REGWRITE_BUFFER(ah);
1484
1485 for (i = 0; i < AR_NUM_DCU; i++)
1486 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1487
1488 REGWRITE_BUFFER_FLUSH(ah);
1489
1490 ah->intr_txqs = 0;
1491 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1492 ath9k_hw_resettxqueue(ah, i);
1493
1494 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1495 ath9k_hw_ani_cache_ini_regs(ah);
1496 ath9k_hw_init_qos(ah);
1497
1498 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1499 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1500
1501 ath9k_hw_init_global_settings(ah);
1502
1503 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1504 ar9002_hw_update_async_fifo(ah);
1505 ar9002_hw_enable_wep_aggregation(ah);
1506 }
1507
1508 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1509
1510 ath9k_hw_set_dma(ah);
1511
1512 REG_WRITE(ah, AR_OBS, 8);
1513
1514 if (ah->config.rx_intr_mitigation) {
1515 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1516 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1517 }
1518
1519 if (ah->config.tx_intr_mitigation) {
1520 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1521 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1522 }
1523
1524 ath9k_hw_init_bb(ah, chan);
1525
1526 if (!ath9k_hw_init_cal(ah, chan))
1527 return -EIO;
1528
1529 ENABLE_REGWRITE_BUFFER(ah);
1530
1531 ath9k_hw_restore_chainmask(ah);
1532 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1533
1534 REGWRITE_BUFFER_FLUSH(ah);
1535
1536 /*
1537 * For big endian systems turn on swapping for descriptors
1538 */
1539 if (AR_SREV_9100(ah)) {
1540 u32 mask;
1541 mask = REG_READ(ah, AR_CFG);
1542 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1543 ath_dbg(common, ATH_DBG_RESET,
1544 "CFG Byte Swap Set 0x%x\n", mask);
1545 } else {
1546 mask =
1547 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1548 REG_WRITE(ah, AR_CFG, mask);
1549 ath_dbg(common, ATH_DBG_RESET,
1550 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1551 }
1552 } else {
1553 if (common->bus_ops->ath_bus_type == ATH_USB) {
1554 /* Configure AR9271 target WLAN */
1555 if (AR_SREV_9271(ah))
1556 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1557 else
1558 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1559 }
1560 #ifdef __BIG_ENDIAN
1561 else if (AR_SREV_9340(ah))
1562 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1563 else
1564 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1565 #endif
1566 }
1567
1568 if (ah->btcoex_hw.enabled)
1569 ath9k_hw_btcoex_enable(ah);
1570
1571 if (AR_SREV_9300_20_OR_LATER(ah))
1572 ar9003_hw_bb_watchdog_config(ah);
1573
1574 ath9k_hw_apply_gpio_override(ah);
1575
1576 return 0;
1577 }
1578 EXPORT_SYMBOL(ath9k_hw_reset);
1579
1580 /******************************/
1581 /* Power Management (Chipset) */
1582 /******************************/
1583
1584 /*
1585 * Notify Power Mgt is disabled in self-generated frames.
1586 * If requested, force chip to sleep.
1587 */
1588 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1589 {
1590 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1591 if (setChip) {
1592 /*
1593 * Clear the RTC force wake bit to allow the
1594 * mac to go to sleep.
1595 */
1596 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1597 AR_RTC_FORCE_WAKE_EN);
1598 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1599 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1600
1601 /* Shutdown chip. Active low */
1602 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1603 REG_CLR_BIT(ah, (AR_RTC_RESET),
1604 AR_RTC_RESET_EN);
1605 }
1606
1607 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1608 if (AR_SREV_9300_20_OR_LATER(ah))
1609 REG_WRITE(ah, AR_WA,
1610 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1611 }
1612
1613 /*
1614 * Notify Power Management is enabled in self-generating
1615 * frames. If request, set power mode of chip to
1616 * auto/normal. Duration in units of 128us (1/8 TU).
1617 */
1618 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1619 {
1620 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1621 if (setChip) {
1622 struct ath9k_hw_capabilities *pCap = &ah->caps;
1623
1624 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1625 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1626 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1627 AR_RTC_FORCE_WAKE_ON_INT);
1628 } else {
1629 /*
1630 * Clear the RTC force wake bit to allow the
1631 * mac to go to sleep.
1632 */
1633 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1634 AR_RTC_FORCE_WAKE_EN);
1635 }
1636 }
1637
1638 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1639 if (AR_SREV_9300_20_OR_LATER(ah))
1640 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1641 }
1642
1643 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1644 {
1645 u32 val;
1646 int i;
1647
1648 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1649 if (AR_SREV_9300_20_OR_LATER(ah)) {
1650 REG_WRITE(ah, AR_WA, ah->WARegVal);
1651 udelay(10);
1652 }
1653
1654 if (setChip) {
1655 if ((REG_READ(ah, AR_RTC_STATUS) &
1656 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1657 if (ath9k_hw_set_reset_reg(ah,
1658 ATH9K_RESET_POWER_ON) != true) {
1659 return false;
1660 }
1661 if (!AR_SREV_9300_20_OR_LATER(ah))
1662 ath9k_hw_init_pll(ah, NULL);
1663 }
1664 if (AR_SREV_9100(ah))
1665 REG_SET_BIT(ah, AR_RTC_RESET,
1666 AR_RTC_RESET_EN);
1667
1668 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1669 AR_RTC_FORCE_WAKE_EN);
1670 udelay(50);
1671
1672 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1673 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1674 if (val == AR_RTC_STATUS_ON)
1675 break;
1676 udelay(50);
1677 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1678 AR_RTC_FORCE_WAKE_EN);
1679 }
1680 if (i == 0) {
1681 ath_err(ath9k_hw_common(ah),
1682 "Failed to wakeup in %uus\n",
1683 POWER_UP_TIME / 20);
1684 return false;
1685 }
1686 }
1687
1688 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1689
1690 return true;
1691 }
1692
1693 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1694 {
1695 struct ath_common *common = ath9k_hw_common(ah);
1696 int status = true, setChip = true;
1697 static const char *modes[] = {
1698 "AWAKE",
1699 "FULL-SLEEP",
1700 "NETWORK SLEEP",
1701 "UNDEFINED"
1702 };
1703
1704 if (ah->power_mode == mode)
1705 return status;
1706
1707 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1708 modes[ah->power_mode], modes[mode]);
1709
1710 switch (mode) {
1711 case ATH9K_PM_AWAKE:
1712 status = ath9k_hw_set_power_awake(ah, setChip);
1713 break;
1714 case ATH9K_PM_FULL_SLEEP:
1715 ath9k_set_power_sleep(ah, setChip);
1716 ah->chip_fullsleep = true;
1717 break;
1718 case ATH9K_PM_NETWORK_SLEEP:
1719 ath9k_set_power_network_sleep(ah, setChip);
1720 break;
1721 default:
1722 ath_err(common, "Unknown power mode %u\n", mode);
1723 return false;
1724 }
1725 ah->power_mode = mode;
1726
1727 /*
1728 * XXX: If this warning never comes up after a while then
1729 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1730 * ath9k_hw_setpower() return type void.
1731 */
1732
1733 if (!(ah->ah_flags & AH_UNPLUGGED))
1734 ATH_DBG_WARN_ON_ONCE(!status);
1735
1736 return status;
1737 }
1738 EXPORT_SYMBOL(ath9k_hw_setpower);
1739
1740 /*******************/
1741 /* Beacon Handling */
1742 /*******************/
1743
1744 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1745 {
1746 int flags = 0;
1747
1748 ENABLE_REGWRITE_BUFFER(ah);
1749
1750 switch (ah->opmode) {
1751 case NL80211_IFTYPE_ADHOC:
1752 case NL80211_IFTYPE_MESH_POINT:
1753 REG_SET_BIT(ah, AR_TXCFG,
1754 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1755 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1756 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1757 flags |= AR_NDP_TIMER_EN;
1758 case NL80211_IFTYPE_AP:
1759 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1760 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1761 TU_TO_USEC(ah->config.dma_beacon_response_time));
1762 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1763 TU_TO_USEC(ah->config.sw_beacon_response_time));
1764 flags |=
1765 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1766 break;
1767 default:
1768 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1769 "%s: unsupported opmode: %d\n",
1770 __func__, ah->opmode);
1771 return;
1772 break;
1773 }
1774
1775 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1776 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1777 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1778 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1779
1780 REGWRITE_BUFFER_FLUSH(ah);
1781
1782 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1783 }
1784 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1785
1786 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1787 const struct ath9k_beacon_state *bs)
1788 {
1789 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1790 struct ath9k_hw_capabilities *pCap = &ah->caps;
1791 struct ath_common *common = ath9k_hw_common(ah);
1792
1793 ENABLE_REGWRITE_BUFFER(ah);
1794
1795 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1796
1797 REG_WRITE(ah, AR_BEACON_PERIOD,
1798 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1799 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1800 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1801
1802 REGWRITE_BUFFER_FLUSH(ah);
1803
1804 REG_RMW_FIELD(ah, AR_RSSI_THR,
1805 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1806
1807 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1808
1809 if (bs->bs_sleepduration > beaconintval)
1810 beaconintval = bs->bs_sleepduration;
1811
1812 dtimperiod = bs->bs_dtimperiod;
1813 if (bs->bs_sleepduration > dtimperiod)
1814 dtimperiod = bs->bs_sleepduration;
1815
1816 if (beaconintval == dtimperiod)
1817 nextTbtt = bs->bs_nextdtim;
1818 else
1819 nextTbtt = bs->bs_nexttbtt;
1820
1821 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1822 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1823 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1824 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1825
1826 ENABLE_REGWRITE_BUFFER(ah);
1827
1828 REG_WRITE(ah, AR_NEXT_DTIM,
1829 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1830 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1831
1832 REG_WRITE(ah, AR_SLEEP1,
1833 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1834 | AR_SLEEP1_ASSUME_DTIM);
1835
1836 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1837 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1838 else
1839 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1840
1841 REG_WRITE(ah, AR_SLEEP2,
1842 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1843
1844 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1845 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1846
1847 REGWRITE_BUFFER_FLUSH(ah);
1848
1849 REG_SET_BIT(ah, AR_TIMER_MODE,
1850 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1851 AR_DTIM_TIMER_EN);
1852
1853 /* TSF Out of Range Threshold */
1854 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1855 }
1856 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1857
1858 /*******************/
1859 /* HW Capabilities */
1860 /*******************/
1861
1862 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1863 {
1864 struct ath9k_hw_capabilities *pCap = &ah->caps;
1865 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1866 struct ath_common *common = ath9k_hw_common(ah);
1867 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1868
1869 u16 eeval;
1870 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1871
1872 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1873 regulatory->current_rd = eeval;
1874
1875 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1876 if (AR_SREV_9285_12_OR_LATER(ah))
1877 eeval |= AR9285_RDEXT_DEFAULT;
1878 regulatory->current_rd_ext = eeval;
1879
1880 if (ah->opmode != NL80211_IFTYPE_AP &&
1881 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1882 if (regulatory->current_rd == 0x64 ||
1883 regulatory->current_rd == 0x65)
1884 regulatory->current_rd += 5;
1885 else if (regulatory->current_rd == 0x41)
1886 regulatory->current_rd = 0x43;
1887 ath_dbg(common, ATH_DBG_REGULATORY,
1888 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1889 }
1890
1891 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1892 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1893 ath_err(common,
1894 "no band has been marked as supported in EEPROM\n");
1895 return -EINVAL;
1896 }
1897
1898 if (eeval & AR5416_OPFLAGS_11A)
1899 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1900
1901 if (eeval & AR5416_OPFLAGS_11G)
1902 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1903
1904 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1905 /*
1906 * For AR9271 we will temporarilly uses the rx chainmax as read from
1907 * the EEPROM.
1908 */
1909 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1910 !(eeval & AR5416_OPFLAGS_11A) &&
1911 !(AR_SREV_9271(ah)))
1912 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1913 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1914 else if (AR_SREV_9100(ah))
1915 pCap->rx_chainmask = 0x7;
1916 else
1917 /* Use rx_chainmask from EEPROM. */
1918 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1919
1920 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1921
1922 /* enable key search for every frame in an aggregate */
1923 if (AR_SREV_9300_20_OR_LATER(ah))
1924 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1925
1926 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1927
1928 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
1929 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1930 else
1931 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1932
1933 if (AR_SREV_9271(ah))
1934 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1935 else if (AR_DEVID_7010(ah))
1936 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1937 else if (AR_SREV_9285_12_OR_LATER(ah))
1938 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1939 else if (AR_SREV_9280_20_OR_LATER(ah))
1940 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1941 else
1942 pCap->num_gpio_pins = AR_NUM_GPIO;
1943
1944 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1945 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1946 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1947 } else {
1948 pCap->rts_aggr_limit = (8 * 1024);
1949 }
1950
1951 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1952 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1953 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1954 ah->rfkill_gpio =
1955 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1956 ah->rfkill_polarity =
1957 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1958
1959 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1960 }
1961 #endif
1962 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1963 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1964 else
1965 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1966
1967 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1968 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1969 else
1970 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1971
1972 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1973 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1974 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1975
1976 if (AR_SREV_9285(ah)) {
1977 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1978 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1979 } else {
1980 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1981 }
1982 } else {
1983 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1984 }
1985
1986 if (AR_SREV_9300_20_OR_LATER(ah)) {
1987 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1988 if (!AR_SREV_9485(ah))
1989 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1990
1991 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1992 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1993 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1994 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1995 pCap->txs_len = sizeof(struct ar9003_txs);
1996 if (!ah->config.paprd_disable &&
1997 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1998 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1999 } else {
2000 pCap->tx_desc_len = sizeof(struct ath_desc);
2001 if (AR_SREV_9280_20(ah) &&
2002 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2003 AR5416_EEP_MINOR_VER_16) ||
2004 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2005 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2006 }
2007
2008 if (AR_SREV_9300_20_OR_LATER(ah))
2009 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2010
2011 if (AR_SREV_9300_20_OR_LATER(ah))
2012 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2013
2014 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2015 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2016
2017 if (AR_SREV_9285(ah))
2018 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2019 ant_div_ctl1 =
2020 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2021 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2022 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2023 }
2024 if (AR_SREV_9300_20_OR_LATER(ah)) {
2025 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2026 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2027 }
2028
2029
2030
2031 if (AR_SREV_9485_10(ah)) {
2032 pCap->pcie_lcr_extsync_en = true;
2033 pCap->pcie_lcr_offset = 0x80;
2034 }
2035
2036 tx_chainmask = pCap->tx_chainmask;
2037 rx_chainmask = pCap->rx_chainmask;
2038 while (tx_chainmask || rx_chainmask) {
2039 if (tx_chainmask & BIT(0))
2040 pCap->max_txchains++;
2041 if (rx_chainmask & BIT(0))
2042 pCap->max_rxchains++;
2043
2044 tx_chainmask >>= 1;
2045 rx_chainmask >>= 1;
2046 }
2047
2048 return 0;
2049 }
2050
2051 /****************************/
2052 /* GPIO / RFKILL / Antennae */
2053 /****************************/
2054
2055 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2056 u32 gpio, u32 type)
2057 {
2058 int addr;
2059 u32 gpio_shift, tmp;
2060
2061 if (gpio > 11)
2062 addr = AR_GPIO_OUTPUT_MUX3;
2063 else if (gpio > 5)
2064 addr = AR_GPIO_OUTPUT_MUX2;
2065 else
2066 addr = AR_GPIO_OUTPUT_MUX1;
2067
2068 gpio_shift = (gpio % 6) * 5;
2069
2070 if (AR_SREV_9280_20_OR_LATER(ah)
2071 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2072 REG_RMW(ah, addr, (type << gpio_shift),
2073 (0x1f << gpio_shift));
2074 } else {
2075 tmp = REG_READ(ah, addr);
2076 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2077 tmp &= ~(0x1f << gpio_shift);
2078 tmp |= (type << gpio_shift);
2079 REG_WRITE(ah, addr, tmp);
2080 }
2081 }
2082
2083 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2084 {
2085 u32 gpio_shift;
2086
2087 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2088
2089 if (AR_DEVID_7010(ah)) {
2090 gpio_shift = gpio;
2091 REG_RMW(ah, AR7010_GPIO_OE,
2092 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2093 (AR7010_GPIO_OE_MASK << gpio_shift));
2094 return;
2095 }
2096
2097 gpio_shift = gpio << 1;
2098 REG_RMW(ah,
2099 AR_GPIO_OE_OUT,
2100 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2101 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2102 }
2103 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2104
2105 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2106 {
2107 #define MS_REG_READ(x, y) \
2108 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2109
2110 if (gpio >= ah->caps.num_gpio_pins)
2111 return 0xffffffff;
2112
2113 if (AR_DEVID_7010(ah)) {
2114 u32 val;
2115 val = REG_READ(ah, AR7010_GPIO_IN);
2116 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2117 } else if (AR_SREV_9300_20_OR_LATER(ah))
2118 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2119 AR_GPIO_BIT(gpio)) != 0;
2120 else if (AR_SREV_9271(ah))
2121 return MS_REG_READ(AR9271, gpio) != 0;
2122 else if (AR_SREV_9287_11_OR_LATER(ah))
2123 return MS_REG_READ(AR9287, gpio) != 0;
2124 else if (AR_SREV_9285_12_OR_LATER(ah))
2125 return MS_REG_READ(AR9285, gpio) != 0;
2126 else if (AR_SREV_9280_20_OR_LATER(ah))
2127 return MS_REG_READ(AR928X, gpio) != 0;
2128 else
2129 return MS_REG_READ(AR, gpio) != 0;
2130 }
2131 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2132
2133 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2134 u32 ah_signal_type)
2135 {
2136 u32 gpio_shift;
2137
2138 if (AR_DEVID_7010(ah)) {
2139 gpio_shift = gpio;
2140 REG_RMW(ah, AR7010_GPIO_OE,
2141 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2142 (AR7010_GPIO_OE_MASK << gpio_shift));
2143 return;
2144 }
2145
2146 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2147 gpio_shift = 2 * gpio;
2148 REG_RMW(ah,
2149 AR_GPIO_OE_OUT,
2150 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2151 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2152 }
2153 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2154
2155 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2156 {
2157 if (AR_DEVID_7010(ah)) {
2158 val = val ? 0 : 1;
2159 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2160 AR_GPIO_BIT(gpio));
2161 return;
2162 }
2163
2164 if (AR_SREV_9271(ah))
2165 val = ~val;
2166
2167 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2168 AR_GPIO_BIT(gpio));
2169 }
2170 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2171
2172 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2173 {
2174 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2175 }
2176 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2177
2178 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2179 {
2180 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2181 }
2182 EXPORT_SYMBOL(ath9k_hw_setantenna);
2183
2184 /*********************/
2185 /* General Operation */
2186 /*********************/
2187
2188 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2189 {
2190 u32 bits = REG_READ(ah, AR_RX_FILTER);
2191 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2192
2193 if (phybits & AR_PHY_ERR_RADAR)
2194 bits |= ATH9K_RX_FILTER_PHYRADAR;
2195 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2196 bits |= ATH9K_RX_FILTER_PHYERR;
2197
2198 return bits;
2199 }
2200 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2201
2202 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2203 {
2204 u32 phybits;
2205
2206 ENABLE_REGWRITE_BUFFER(ah);
2207
2208 REG_WRITE(ah, AR_RX_FILTER, bits);
2209
2210 phybits = 0;
2211 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2212 phybits |= AR_PHY_ERR_RADAR;
2213 if (bits & ATH9K_RX_FILTER_PHYERR)
2214 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2215 REG_WRITE(ah, AR_PHY_ERR, phybits);
2216
2217 if (phybits)
2218 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2219 else
2220 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2221
2222 REGWRITE_BUFFER_FLUSH(ah);
2223 }
2224 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2225
2226 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2227 {
2228 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2229 return false;
2230
2231 ath9k_hw_init_pll(ah, NULL);
2232 return true;
2233 }
2234 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2235
2236 bool ath9k_hw_disable(struct ath_hw *ah)
2237 {
2238 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2239 return false;
2240
2241 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2242 return false;
2243
2244 ath9k_hw_init_pll(ah, NULL);
2245 return true;
2246 }
2247 EXPORT_SYMBOL(ath9k_hw_disable);
2248
2249 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2250 {
2251 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2252 struct ath9k_channel *chan = ah->curchan;
2253 struct ieee80211_channel *channel = chan->chan;
2254
2255 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2256
2257 ah->eep_ops->set_txpower(ah, chan,
2258 ath9k_regd_get_ctl(regulatory, chan),
2259 channel->max_antenna_gain * 2,
2260 channel->max_power * 2,
2261 min((u32) MAX_RATE_POWER,
2262 (u32) regulatory->power_limit), test);
2263 }
2264 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2265
2266 void ath9k_hw_setopmode(struct ath_hw *ah)
2267 {
2268 ath9k_hw_set_operating_mode(ah, ah->opmode);
2269 }
2270 EXPORT_SYMBOL(ath9k_hw_setopmode);
2271
2272 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2273 {
2274 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2275 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2276 }
2277 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2278
2279 void ath9k_hw_write_associd(struct ath_hw *ah)
2280 {
2281 struct ath_common *common = ath9k_hw_common(ah);
2282
2283 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2284 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2285 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2286 }
2287 EXPORT_SYMBOL(ath9k_hw_write_associd);
2288
2289 #define ATH9K_MAX_TSF_READ 10
2290
2291 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2292 {
2293 u32 tsf_lower, tsf_upper1, tsf_upper2;
2294 int i;
2295
2296 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2297 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2298 tsf_lower = REG_READ(ah, AR_TSF_L32);
2299 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2300 if (tsf_upper2 == tsf_upper1)
2301 break;
2302 tsf_upper1 = tsf_upper2;
2303 }
2304
2305 WARN_ON( i == ATH9K_MAX_TSF_READ );
2306
2307 return (((u64)tsf_upper1 << 32) | tsf_lower);
2308 }
2309 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2310
2311 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2312 {
2313 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2314 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2315 }
2316 EXPORT_SYMBOL(ath9k_hw_settsf64);
2317
2318 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2319 {
2320 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2321 AH_TSF_WRITE_TIMEOUT))
2322 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2323 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2324
2325 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2326 }
2327 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2328
2329 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2330 {
2331 if (setting)
2332 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2333 else
2334 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2335 }
2336 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2337
2338 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2339 {
2340 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2341 u32 macmode;
2342
2343 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2344 macmode = AR_2040_JOINED_RX_CLEAR;
2345 else
2346 macmode = 0;
2347
2348 REG_WRITE(ah, AR_2040_MODE, macmode);
2349 }
2350
2351 /* HW Generic timers configuration */
2352
2353 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2354 {
2355 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2356 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2357 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2358 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2359 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2360 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2361 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2362 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2363 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2364 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2365 AR_NDP2_TIMER_MODE, 0x0002},
2366 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2367 AR_NDP2_TIMER_MODE, 0x0004},
2368 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2369 AR_NDP2_TIMER_MODE, 0x0008},
2370 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2371 AR_NDP2_TIMER_MODE, 0x0010},
2372 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2373 AR_NDP2_TIMER_MODE, 0x0020},
2374 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2375 AR_NDP2_TIMER_MODE, 0x0040},
2376 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2377 AR_NDP2_TIMER_MODE, 0x0080}
2378 };
2379
2380 /* HW generic timer primitives */
2381
2382 /* compute and clear index of rightmost 1 */
2383 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2384 {
2385 u32 b;
2386
2387 b = *mask;
2388 b &= (0-b);
2389 *mask &= ~b;
2390 b *= debruijn32;
2391 b >>= 27;
2392
2393 return timer_table->gen_timer_index[b];
2394 }
2395
2396 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2397 {
2398 return REG_READ(ah, AR_TSF_L32);
2399 }
2400 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2401
2402 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2403 void (*trigger)(void *),
2404 void (*overflow)(void *),
2405 void *arg,
2406 u8 timer_index)
2407 {
2408 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2409 struct ath_gen_timer *timer;
2410
2411 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2412
2413 if (timer == NULL) {
2414 ath_err(ath9k_hw_common(ah),
2415 "Failed to allocate memory for hw timer[%d]\n",
2416 timer_index);
2417 return NULL;
2418 }
2419
2420 /* allocate a hardware generic timer slot */
2421 timer_table->timers[timer_index] = timer;
2422 timer->index = timer_index;
2423 timer->trigger = trigger;
2424 timer->overflow = overflow;
2425 timer->arg = arg;
2426
2427 return timer;
2428 }
2429 EXPORT_SYMBOL(ath_gen_timer_alloc);
2430
2431 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2432 struct ath_gen_timer *timer,
2433 u32 timer_next,
2434 u32 timer_period)
2435 {
2436 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2437 u32 tsf;
2438
2439 BUG_ON(!timer_period);
2440
2441 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2442
2443 tsf = ath9k_hw_gettsf32(ah);
2444
2445 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2446 "current tsf %x period %x timer_next %x\n",
2447 tsf, timer_period, timer_next);
2448
2449 /*
2450 * Pull timer_next forward if the current TSF already passed it
2451 * because of software latency
2452 */
2453 if (timer_next < tsf)
2454 timer_next = tsf + timer_period;
2455
2456 /*
2457 * Program generic timer registers
2458 */
2459 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2460 timer_next);
2461 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2462 timer_period);
2463 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2464 gen_tmr_configuration[timer->index].mode_mask);
2465
2466 /* Enable both trigger and thresh interrupt masks */
2467 REG_SET_BIT(ah, AR_IMR_S5,
2468 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2469 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2470 }
2471 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2472
2473 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2474 {
2475 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2476
2477 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2478 (timer->index >= ATH_MAX_GEN_TIMER)) {
2479 return;
2480 }
2481
2482 /* Clear generic timer enable bits. */
2483 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2484 gen_tmr_configuration[timer->index].mode_mask);
2485
2486 /* Disable both trigger and thresh interrupt masks */
2487 REG_CLR_BIT(ah, AR_IMR_S5,
2488 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2489 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2490
2491 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2492 }
2493 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2494
2495 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2496 {
2497 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2498
2499 /* free the hardware generic timer slot */
2500 timer_table->timers[timer->index] = NULL;
2501 kfree(timer);
2502 }
2503 EXPORT_SYMBOL(ath_gen_timer_free);
2504
2505 /*
2506 * Generic Timer Interrupts handling
2507 */
2508 void ath_gen_timer_isr(struct ath_hw *ah)
2509 {
2510 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2511 struct ath_gen_timer *timer;
2512 struct ath_common *common = ath9k_hw_common(ah);
2513 u32 trigger_mask, thresh_mask, index;
2514
2515 /* get hardware generic timer interrupt status */
2516 trigger_mask = ah->intr_gen_timer_trigger;
2517 thresh_mask = ah->intr_gen_timer_thresh;
2518 trigger_mask &= timer_table->timer_mask.val;
2519 thresh_mask &= timer_table->timer_mask.val;
2520
2521 trigger_mask &= ~thresh_mask;
2522
2523 while (thresh_mask) {
2524 index = rightmost_index(timer_table, &thresh_mask);
2525 timer = timer_table->timers[index];
2526 BUG_ON(!timer);
2527 ath_dbg(common, ATH_DBG_HWTIMER,
2528 "TSF overflow for Gen timer %d\n", index);
2529 timer->overflow(timer->arg);
2530 }
2531
2532 while (trigger_mask) {
2533 index = rightmost_index(timer_table, &trigger_mask);
2534 timer = timer_table->timers[index];
2535 BUG_ON(!timer);
2536 ath_dbg(common, ATH_DBG_HWTIMER,
2537 "Gen timer[%d] trigger\n", index);
2538 timer->trigger(timer->arg);
2539 }
2540 }
2541 EXPORT_SYMBOL(ath_gen_timer_isr);
2542
2543 /********/
2544 /* HTC */
2545 /********/
2546
2547 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2548 {
2549 ah->htc_reset_init = true;
2550 }
2551 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2552
2553 static struct {
2554 u32 version;
2555 const char * name;
2556 } ath_mac_bb_names[] = {
2557 /* Devices with external radios */
2558 { AR_SREV_VERSION_5416_PCI, "5416" },
2559 { AR_SREV_VERSION_5416_PCIE, "5418" },
2560 { AR_SREV_VERSION_9100, "9100" },
2561 { AR_SREV_VERSION_9160, "9160" },
2562 /* Single-chip solutions */
2563 { AR_SREV_VERSION_9280, "9280" },
2564 { AR_SREV_VERSION_9285, "9285" },
2565 { AR_SREV_VERSION_9287, "9287" },
2566 { AR_SREV_VERSION_9271, "9271" },
2567 { AR_SREV_VERSION_9300, "9300" },
2568 { AR_SREV_VERSION_9485, "9485" },
2569 };
2570
2571 /* For devices with external radios */
2572 static struct {
2573 u16 version;
2574 const char * name;
2575 } ath_rf_names[] = {
2576 { 0, "5133" },
2577 { AR_RAD5133_SREV_MAJOR, "5133" },
2578 { AR_RAD5122_SREV_MAJOR, "5122" },
2579 { AR_RAD2133_SREV_MAJOR, "2133" },
2580 { AR_RAD2122_SREV_MAJOR, "2122" }
2581 };
2582
2583 /*
2584 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2585 */
2586 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2587 {
2588 int i;
2589
2590 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2591 if (ath_mac_bb_names[i].version == mac_bb_version) {
2592 return ath_mac_bb_names[i].name;
2593 }
2594 }
2595
2596 return "????";
2597 }
2598
2599 /*
2600 * Return the RF name. "????" is returned if the RF is unknown.
2601 * Used for devices with external radios.
2602 */
2603 static const char *ath9k_hw_rf_name(u16 rf_version)
2604 {
2605 int i;
2606
2607 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2608 if (ath_rf_names[i].version == rf_version) {
2609 return ath_rf_names[i].name;
2610 }
2611 }
2612
2613 return "????";
2614 }
2615
2616 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2617 {
2618 int used;
2619
2620 /* chipsets >= AR9280 are single-chip */
2621 if (AR_SREV_9280_20_OR_LATER(ah)) {
2622 used = snprintf(hw_name, len,
2623 "Atheros AR%s Rev:%x",
2624 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2625 ah->hw_version.macRev);
2626 }
2627 else {
2628 used = snprintf(hw_name, len,
2629 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2630 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2631 ah->hw_version.macRev,
2632 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2633 AR_RADIO_SREV_MAJOR)),
2634 ah->hw_version.phyRev);
2635 }
2636
2637 hw_name[used] = '\0';
2638 }
2639 EXPORT_SYMBOL(ath9k_hw_name);
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