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ath9k_hw: add default chainmask for AR9462
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
21
22 #include "hw.h"
23 #include "hw-ops.h"
24 #include "rc.h"
25 #include "ar9003_mac.h"
26
27 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28
29 MODULE_AUTHOR("Atheros Communications");
30 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
31 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
32 MODULE_LICENSE("Dual BSD/GPL");
33
34 static int __init ath9k_init(void)
35 {
36 return 0;
37 }
38 module_init(ath9k_init);
39
40 static void __exit ath9k_exit(void)
41 {
42 return;
43 }
44 module_exit(ath9k_exit);
45
46 /* Private hardware callbacks */
47
48 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49 {
50 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
51 }
52
53 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 {
55 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
56 }
57
58 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
59 struct ath9k_channel *chan)
60 {
61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
62 }
63
64 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65 {
66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
67 return;
68
69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
70 }
71
72 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73 {
74 /* You will not have this callback if using the old ANI */
75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
76 return;
77
78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
79 }
80
81 /********************/
82 /* Helper Functions */
83 /********************/
84
85 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
86 {
87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
88 struct ath_common *common = ath9k_hw_common(ah);
89 unsigned int clockrate;
90
91 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
92 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
93 clockrate = 117;
94 else if (!ah->curchan) /* should really check for CCK instead */
95 clockrate = ATH9K_CLOCK_RATE_CCK;
96 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
97 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
98 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
99 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
100 else
101 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
102
103 if (conf_is_ht40(conf))
104 clockrate *= 2;
105
106 if (ah->curchan) {
107 if (IS_CHAN_HALF_RATE(ah->curchan))
108 clockrate /= 2;
109 if (IS_CHAN_QUARTER_RATE(ah->curchan))
110 clockrate /= 4;
111 }
112
113 common->clockrate = clockrate;
114 }
115
116 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
117 {
118 struct ath_common *common = ath9k_hw_common(ah);
119
120 return usecs * common->clockrate;
121 }
122
123 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
124 {
125 int i;
126
127 BUG_ON(timeout < AH_TIME_QUANTUM);
128
129 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
130 if ((REG_READ(ah, reg) & mask) == val)
131 return true;
132
133 udelay(AH_TIME_QUANTUM);
134 }
135
136 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
137 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
138 timeout, reg, REG_READ(ah, reg), mask, val);
139
140 return false;
141 }
142 EXPORT_SYMBOL(ath9k_hw_wait);
143
144 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
145 int column, unsigned int *writecnt)
146 {
147 int r;
148
149 ENABLE_REGWRITE_BUFFER(ah);
150 for (r = 0; r < array->ia_rows; r++) {
151 REG_WRITE(ah, INI_RA(array, r, 0),
152 INI_RA(array, r, column));
153 DO_DELAY(*writecnt);
154 }
155 REGWRITE_BUFFER_FLUSH(ah);
156 }
157
158 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
159 {
160 u32 retval;
161 int i;
162
163 for (i = 0, retval = 0; i < n; i++) {
164 retval = (retval << 1) | (val & 1);
165 val >>= 1;
166 }
167 return retval;
168 }
169
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 u8 phy, int kbps,
172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
174 {
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176
177 if (kbps == 0)
178 return 0;
179
180 switch (phy) {
181 case WLAN_RC_PHY_CCK:
182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
183 if (shortPreamble)
184 phyTime >>= 1;
185 numBits = frameLen << 3;
186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
187 break;
188 case WLAN_RC_PHY_OFDM:
189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME_QUARTER
194 + OFDM_PREAMBLE_TIME_QUARTER
195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
196 } else if (ah->curchan &&
197 IS_CHAN_HALF_RATE(ah->curchan)) {
198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME_HALF +
202 OFDM_PREAMBLE_TIME_HALF
203 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
204 } else {
205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
206 numBits = OFDM_PLCP_BITS + (frameLen << 3);
207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
209 + (numSymbols * OFDM_SYMBOL_TIME);
210 }
211 break;
212 default:
213 ath_err(ath9k_hw_common(ah),
214 "Unknown phy %u (rate ix %u)\n", phy, rateix);
215 txTime = 0;
216 break;
217 }
218
219 return txTime;
220 }
221 EXPORT_SYMBOL(ath9k_hw_computetxtime);
222
223 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
224 struct ath9k_channel *chan,
225 struct chan_centers *centers)
226 {
227 int8_t extoff;
228
229 if (!IS_CHAN_HT40(chan)) {
230 centers->ctl_center = centers->ext_center =
231 centers->synth_center = chan->channel;
232 return;
233 }
234
235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
236 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
237 centers->synth_center =
238 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
239 extoff = 1;
240 } else {
241 centers->synth_center =
242 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
243 extoff = -1;
244 }
245
246 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
248 /* 25 MHz spacing is supported by hw but not on upper layers */
249 centers->ext_center =
250 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 }
252
253 /******************/
254 /* Chip Revisions */
255 /******************/
256
257 static void ath9k_hw_read_revisions(struct ath_hw *ah)
258 {
259 u32 val;
260
261 switch (ah->hw_version.devid) {
262 case AR5416_AR9100_DEVID:
263 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 break;
265 case AR9300_DEVID_AR9330:
266 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
267 if (ah->get_mac_revision) {
268 ah->hw_version.macRev = ah->get_mac_revision();
269 } else {
270 val = REG_READ(ah, AR_SREV);
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 }
273 return;
274 case AR9300_DEVID_AR9340:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
276 val = REG_READ(ah, AR_SREV);
277 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
278 return;
279 }
280
281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
282
283 if (val == 0xFF) {
284 val = REG_READ(ah, AR_SREV);
285 ah->hw_version.macVersion =
286 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
287 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
288
289 if (AR_SREV_9462(ah))
290 ah->is_pciexpress = true;
291 else
292 ah->is_pciexpress = (val &
293 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
294 } else {
295 if (!AR_SREV_9100(ah))
296 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
297
298 ah->hw_version.macRev = val & AR_SREV_REVISION;
299
300 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
301 ah->is_pciexpress = true;
302 }
303 }
304
305 /************************************/
306 /* HW Attach, Detach, Init Routines */
307 /************************************/
308
309 static void ath9k_hw_disablepcie(struct ath_hw *ah)
310 {
311 if (!AR_SREV_5416(ah))
312 return;
313
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
323
324 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
325 }
326
327 static void ath9k_hw_aspm_init(struct ath_hw *ah)
328 {
329 struct ath_common *common = ath9k_hw_common(ah);
330
331 if (common->bus_ops->aspm_init)
332 common->bus_ops->aspm_init(common);
333 }
334
335 /* This should work for all families including legacy */
336 static bool ath9k_hw_chip_test(struct ath_hw *ah)
337 {
338 struct ath_common *common = ath9k_hw_common(ah);
339 u32 regAddr[2] = { AR_STA_ID0 };
340 u32 regHold[2];
341 static const u32 patternData[4] = {
342 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
343 };
344 int i, j, loop_max;
345
346 if (!AR_SREV_9300_20_OR_LATER(ah)) {
347 loop_max = 2;
348 regAddr[1] = AR_PHY_BASE + (8 << 2);
349 } else
350 loop_max = 1;
351
352 for (i = 0; i < loop_max; i++) {
353 u32 addr = regAddr[i];
354 u32 wrData, rdData;
355
356 regHold[i] = REG_READ(ah, addr);
357 for (j = 0; j < 0x100; j++) {
358 wrData = (j << 16) | j;
359 REG_WRITE(ah, addr, wrData);
360 rdData = REG_READ(ah, addr);
361 if (rdData != wrData) {
362 ath_err(common,
363 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
364 addr, wrData, rdData);
365 return false;
366 }
367 }
368 for (j = 0; j < 4; j++) {
369 wrData = patternData[j];
370 REG_WRITE(ah, addr, wrData);
371 rdData = REG_READ(ah, addr);
372 if (wrData != rdData) {
373 ath_err(common,
374 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
375 addr, wrData, rdData);
376 return false;
377 }
378 }
379 REG_WRITE(ah, regAddr[i], regHold[i]);
380 }
381 udelay(100);
382
383 return true;
384 }
385
386 static void ath9k_hw_init_config(struct ath_hw *ah)
387 {
388 int i;
389
390 ah->config.dma_beacon_response_time = 2;
391 ah->config.sw_beacon_response_time = 10;
392 ah->config.additional_swba_backoff = 0;
393 ah->config.ack_6mb = 0x0;
394 ah->config.cwm_ignore_extcca = 0;
395 ah->config.pcie_clock_req = 0;
396 ah->config.pcie_waen = 0;
397 ah->config.analog_shiftreg = 1;
398 ah->config.enable_ani = true;
399
400 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
401 ah->config.spurchans[i][0] = AR_NO_SPUR;
402 ah->config.spurchans[i][1] = AR_NO_SPUR;
403 }
404
405 /* PAPRD needs some more work to be enabled */
406 ah->config.paprd_disable = 1;
407
408 ah->config.rx_intr_mitigation = true;
409 ah->config.pcieSerDesWrite = true;
410
411 /*
412 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
413 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
414 * This means we use it for all AR5416 devices, and the few
415 * minor PCI AR9280 devices out there.
416 *
417 * Serialization is required because these devices do not handle
418 * well the case of two concurrent reads/writes due to the latency
419 * involved. During one read/write another read/write can be issued
420 * on another CPU while the previous read/write may still be working
421 * on our hardware, if we hit this case the hardware poops in a loop.
422 * We prevent this by serializing reads and writes.
423 *
424 * This issue is not present on PCI-Express devices or pre-AR5416
425 * devices (legacy, 802.11abg).
426 */
427 if (num_possible_cpus() > 1)
428 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
429 }
430
431 static void ath9k_hw_init_defaults(struct ath_hw *ah)
432 {
433 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
434
435 regulatory->country_code = CTRY_DEFAULT;
436 regulatory->power_limit = MAX_RATE_POWER;
437
438 ah->hw_version.magic = AR5416_MAGIC;
439 ah->hw_version.subvendorid = 0;
440
441 ah->atim_window = 0;
442 ah->sta_id1_defaults =
443 AR_STA_ID1_CRPT_MIC_ENABLE |
444 AR_STA_ID1_MCAST_KSRCH;
445 if (AR_SREV_9100(ah))
446 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
447 ah->enable_32kHz_clock = DONT_USE_32KHZ;
448 ah->slottime = ATH9K_SLOT_TIME_9;
449 ah->globaltxtimeout = (u32) -1;
450 ah->power_mode = ATH9K_PM_UNDEFINED;
451 }
452
453 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
454 {
455 struct ath_common *common = ath9k_hw_common(ah);
456 u32 sum;
457 int i;
458 u16 eeval;
459 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
460
461 sum = 0;
462 for (i = 0; i < 3; i++) {
463 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
464 sum += eeval;
465 common->macaddr[2 * i] = eeval >> 8;
466 common->macaddr[2 * i + 1] = eeval & 0xff;
467 }
468 if (sum == 0 || sum == 0xffff * 3)
469 return -EADDRNOTAVAIL;
470
471 return 0;
472 }
473
474 static int ath9k_hw_post_init(struct ath_hw *ah)
475 {
476 struct ath_common *common = ath9k_hw_common(ah);
477 int ecode;
478
479 if (common->bus_ops->ath_bus_type != ATH_USB) {
480 if (!ath9k_hw_chip_test(ah))
481 return -ENODEV;
482 }
483
484 if (!AR_SREV_9300_20_OR_LATER(ah)) {
485 ecode = ar9002_hw_rf_claim(ah);
486 if (ecode != 0)
487 return ecode;
488 }
489
490 ecode = ath9k_hw_eeprom_init(ah);
491 if (ecode != 0)
492 return ecode;
493
494 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
495 "Eeprom VER: %d, REV: %d\n",
496 ah->eep_ops->get_eeprom_ver(ah),
497 ah->eep_ops->get_eeprom_rev(ah));
498
499 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
500 if (ecode) {
501 ath_err(ath9k_hw_common(ah),
502 "Failed allocating banks for external radio\n");
503 ath9k_hw_rf_free_ext_banks(ah);
504 return ecode;
505 }
506
507 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
508 ath9k_hw_ani_setup(ah);
509 ath9k_hw_ani_init(ah);
510 }
511
512 return 0;
513 }
514
515 static void ath9k_hw_attach_ops(struct ath_hw *ah)
516 {
517 if (AR_SREV_9300_20_OR_LATER(ah))
518 ar9003_hw_attach_ops(ah);
519 else
520 ar9002_hw_attach_ops(ah);
521 }
522
523 /* Called for all hardware families */
524 static int __ath9k_hw_init(struct ath_hw *ah)
525 {
526 struct ath_common *common = ath9k_hw_common(ah);
527 int r = 0;
528
529 ath9k_hw_read_revisions(ah);
530
531 /*
532 * Read back AR_WA into a permanent copy and set bits 14 and 17.
533 * We need to do this to avoid RMW of this register. We cannot
534 * read the reg when chip is asleep.
535 */
536 ah->WARegVal = REG_READ(ah, AR_WA);
537 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
538 AR_WA_ASPM_TIMER_BASED_DISABLE);
539
540 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
541 ath_err(common, "Couldn't reset chip\n");
542 return -EIO;
543 }
544
545 if (AR_SREV_9462(ah))
546 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
547
548 ath9k_hw_init_defaults(ah);
549 ath9k_hw_init_config(ah);
550
551 ath9k_hw_attach_ops(ah);
552
553 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
554 ath_err(common, "Couldn't wakeup chip\n");
555 return -EIO;
556 }
557
558 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
559 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
560 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
561 !ah->is_pciexpress)) {
562 ah->config.serialize_regmode =
563 SER_REG_MODE_ON;
564 } else {
565 ah->config.serialize_regmode =
566 SER_REG_MODE_OFF;
567 }
568 }
569
570 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
571 ah->config.serialize_regmode);
572
573 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
574 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
575 else
576 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
577
578 switch (ah->hw_version.macVersion) {
579 case AR_SREV_VERSION_5416_PCI:
580 case AR_SREV_VERSION_5416_PCIE:
581 case AR_SREV_VERSION_9160:
582 case AR_SREV_VERSION_9100:
583 case AR_SREV_VERSION_9280:
584 case AR_SREV_VERSION_9285:
585 case AR_SREV_VERSION_9287:
586 case AR_SREV_VERSION_9271:
587 case AR_SREV_VERSION_9300:
588 case AR_SREV_VERSION_9330:
589 case AR_SREV_VERSION_9485:
590 case AR_SREV_VERSION_9340:
591 case AR_SREV_VERSION_9462:
592 break;
593 default:
594 ath_err(common,
595 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
596 ah->hw_version.macVersion, ah->hw_version.macRev);
597 return -EOPNOTSUPP;
598 }
599
600 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
601 AR_SREV_9330(ah))
602 ah->is_pciexpress = false;
603
604 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
605 ath9k_hw_init_cal_settings(ah);
606
607 ah->ani_function = ATH9K_ANI_ALL;
608 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
609 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
610 if (!AR_SREV_9300_20_OR_LATER(ah))
611 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
612
613 ath9k_hw_init_mode_regs(ah);
614
615 if (!ah->is_pciexpress)
616 ath9k_hw_disablepcie(ah);
617
618 if (!AR_SREV_9300_20_OR_LATER(ah))
619 ar9002_hw_cck_chan14_spread(ah);
620
621 r = ath9k_hw_post_init(ah);
622 if (r)
623 return r;
624
625 ath9k_hw_init_mode_gain_regs(ah);
626 r = ath9k_hw_fill_cap_info(ah);
627 if (r)
628 return r;
629
630 if (ah->is_pciexpress)
631 ath9k_hw_aspm_init(ah);
632
633 r = ath9k_hw_init_macaddr(ah);
634 if (r) {
635 ath_err(common, "Failed to initialize MAC address\n");
636 return r;
637 }
638
639 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
640 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
641 else
642 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
643
644 if (AR_SREV_9330(ah))
645 ah->bb_watchdog_timeout_ms = 85;
646 else
647 ah->bb_watchdog_timeout_ms = 25;
648
649 common->state = ATH_HW_INITIALIZED;
650
651 return 0;
652 }
653
654 int ath9k_hw_init(struct ath_hw *ah)
655 {
656 int ret;
657 struct ath_common *common = ath9k_hw_common(ah);
658
659 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
660 switch (ah->hw_version.devid) {
661 case AR5416_DEVID_PCI:
662 case AR5416_DEVID_PCIE:
663 case AR5416_AR9100_DEVID:
664 case AR9160_DEVID_PCI:
665 case AR9280_DEVID_PCI:
666 case AR9280_DEVID_PCIE:
667 case AR9285_DEVID_PCIE:
668 case AR9287_DEVID_PCI:
669 case AR9287_DEVID_PCIE:
670 case AR2427_DEVID_PCIE:
671 case AR9300_DEVID_PCIE:
672 case AR9300_DEVID_AR9485_PCIE:
673 case AR9300_DEVID_AR9330:
674 case AR9300_DEVID_AR9340:
675 case AR9300_DEVID_AR9580:
676 case AR9300_DEVID_AR9462:
677 break;
678 default:
679 if (common->bus_ops->ath_bus_type == ATH_USB)
680 break;
681 ath_err(common, "Hardware device ID 0x%04x not supported\n",
682 ah->hw_version.devid);
683 return -EOPNOTSUPP;
684 }
685
686 ret = __ath9k_hw_init(ah);
687 if (ret) {
688 ath_err(common,
689 "Unable to initialize hardware; initialization status: %d\n",
690 ret);
691 return ret;
692 }
693
694 return 0;
695 }
696 EXPORT_SYMBOL(ath9k_hw_init);
697
698 static void ath9k_hw_init_qos(struct ath_hw *ah)
699 {
700 ENABLE_REGWRITE_BUFFER(ah);
701
702 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
703 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
704
705 REG_WRITE(ah, AR_QOS_NO_ACK,
706 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
707 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
708 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
709
710 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
711 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
712 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
713 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
714 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
715
716 REGWRITE_BUFFER_FLUSH(ah);
717 }
718
719 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
720 {
721 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
722 udelay(100);
723 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
724
725 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
726 udelay(100);
727
728 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
729 }
730 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
731
732 static void ath9k_hw_init_pll(struct ath_hw *ah,
733 struct ath9k_channel *chan)
734 {
735 u32 pll;
736
737 if (AR_SREV_9485(ah)) {
738
739 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
740 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
741 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
742 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
743 AR_CH0_DPLL2_KD, 0x40);
744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
745 AR_CH0_DPLL2_KI, 0x4);
746
747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
748 AR_CH0_BB_DPLL1_REFDIV, 0x5);
749 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
750 AR_CH0_BB_DPLL1_NINI, 0x58);
751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
752 AR_CH0_BB_DPLL1_NFRAC, 0x0);
753
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
755 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
757 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
760
761 /* program BB PLL phase_shift to 0x6 */
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
763 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
764
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
766 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
767 udelay(1000);
768 } else if (AR_SREV_9330(ah)) {
769 u32 ddr_dpll2, pll_control2, kd;
770
771 if (ah->is_clk_25mhz) {
772 ddr_dpll2 = 0x18e82f01;
773 pll_control2 = 0xe04a3d;
774 kd = 0x1d;
775 } else {
776 ddr_dpll2 = 0x19e82f01;
777 pll_control2 = 0x886666;
778 kd = 0x3d;
779 }
780
781 /* program DDR PLL ki and kd value */
782 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
783
784 /* program DDR PLL phase_shift */
785 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
786 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
787
788 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
789 udelay(1000);
790
791 /* program refdiv, nint, frac to RTC register */
792 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
793
794 /* program BB PLL kd and ki value */
795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
796 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
797
798 /* program BB PLL phase_shift */
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
800 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
801 } else if (AR_SREV_9340(ah)) {
802 u32 regval, pll2_divint, pll2_divfrac, refdiv;
803
804 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
805 udelay(1000);
806
807 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
808 udelay(100);
809
810 if (ah->is_clk_25mhz) {
811 pll2_divint = 0x54;
812 pll2_divfrac = 0x1eb85;
813 refdiv = 3;
814 } else {
815 pll2_divint = 88;
816 pll2_divfrac = 0;
817 refdiv = 5;
818 }
819
820 regval = REG_READ(ah, AR_PHY_PLL_MODE);
821 regval |= (0x1 << 16);
822 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
823 udelay(100);
824
825 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
826 (pll2_divint << 18) | pll2_divfrac);
827 udelay(100);
828
829 regval = REG_READ(ah, AR_PHY_PLL_MODE);
830 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
831 (0x4 << 26) | (0x18 << 19);
832 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
833 REG_WRITE(ah, AR_PHY_PLL_MODE,
834 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
835 udelay(1000);
836 }
837
838 pll = ath9k_hw_compute_pll_control(ah, chan);
839
840 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
841
842 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
843 udelay(1000);
844
845 /* Switch the core clock for ar9271 to 117Mhz */
846 if (AR_SREV_9271(ah)) {
847 udelay(500);
848 REG_WRITE(ah, 0x50040, 0x304);
849 }
850
851 udelay(RTC_PLL_SETTLE_DELAY);
852
853 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
854
855 if (AR_SREV_9340(ah)) {
856 if (ah->is_clk_25mhz) {
857 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
858 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
859 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
860 } else {
861 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
862 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
863 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
864 }
865 udelay(100);
866 }
867 }
868
869 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
870 enum nl80211_iftype opmode)
871 {
872 u32 sync_default = AR_INTR_SYNC_DEFAULT;
873 u32 imr_reg = AR_IMR_TXERR |
874 AR_IMR_TXURN |
875 AR_IMR_RXERR |
876 AR_IMR_RXORN |
877 AR_IMR_BCNMISC;
878
879 if (AR_SREV_9340(ah))
880 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
881
882 if (AR_SREV_9300_20_OR_LATER(ah)) {
883 imr_reg |= AR_IMR_RXOK_HP;
884 if (ah->config.rx_intr_mitigation)
885 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
886 else
887 imr_reg |= AR_IMR_RXOK_LP;
888
889 } else {
890 if (ah->config.rx_intr_mitigation)
891 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
892 else
893 imr_reg |= AR_IMR_RXOK;
894 }
895
896 if (ah->config.tx_intr_mitigation)
897 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
898 else
899 imr_reg |= AR_IMR_TXOK;
900
901 if (opmode == NL80211_IFTYPE_AP)
902 imr_reg |= AR_IMR_MIB;
903
904 ENABLE_REGWRITE_BUFFER(ah);
905
906 REG_WRITE(ah, AR_IMR, imr_reg);
907 ah->imrs2_reg |= AR_IMR_S2_GTT;
908 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
909
910 if (!AR_SREV_9100(ah)) {
911 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
912 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
913 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
914 }
915
916 REGWRITE_BUFFER_FLUSH(ah);
917
918 if (AR_SREV_9300_20_OR_LATER(ah)) {
919 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
920 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
921 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
922 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
923 }
924 }
925
926 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
927 {
928 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
929 val = min(val, (u32) 0xFFFF);
930 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
931 }
932
933 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
934 {
935 u32 val = ath9k_hw_mac_to_clks(ah, us);
936 val = min(val, (u32) 0xFFFF);
937 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
938 }
939
940 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
941 {
942 u32 val = ath9k_hw_mac_to_clks(ah, us);
943 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
944 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
945 }
946
947 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
948 {
949 u32 val = ath9k_hw_mac_to_clks(ah, us);
950 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
951 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
952 }
953
954 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
955 {
956 if (tu > 0xFFFF) {
957 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
958 "bad global tx timeout %u\n", tu);
959 ah->globaltxtimeout = (u32) -1;
960 return false;
961 } else {
962 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
963 ah->globaltxtimeout = tu;
964 return true;
965 }
966 }
967
968 void ath9k_hw_init_global_settings(struct ath_hw *ah)
969 {
970 struct ath_common *common = ath9k_hw_common(ah);
971 struct ieee80211_conf *conf = &common->hw->conf;
972 const struct ath9k_channel *chan = ah->curchan;
973 int acktimeout, ctstimeout;
974 int slottime;
975 int sifstime;
976 int rx_lat = 0, tx_lat = 0, eifs = 0;
977 u32 reg;
978
979 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
980 ah->misc_mode);
981
982 if (!chan)
983 return;
984
985 if (ah->misc_mode != 0)
986 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
987
988 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
989 rx_lat = 41;
990 else
991 rx_lat = 37;
992 tx_lat = 54;
993
994 if (IS_CHAN_HALF_RATE(chan)) {
995 eifs = 175;
996 rx_lat *= 2;
997 tx_lat *= 2;
998 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
999 tx_lat += 11;
1000
1001 slottime = 13;
1002 sifstime = 32;
1003 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1004 eifs = 340;
1005 rx_lat = (rx_lat * 4) - 1;
1006 tx_lat *= 4;
1007 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1008 tx_lat += 22;
1009
1010 slottime = 21;
1011 sifstime = 64;
1012 } else {
1013 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1014 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1015 reg = AR_USEC_ASYNC_FIFO;
1016 } else {
1017 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1018 common->clockrate;
1019 reg = REG_READ(ah, AR_USEC);
1020 }
1021 rx_lat = MS(reg, AR_USEC_RX_LAT);
1022 tx_lat = MS(reg, AR_USEC_TX_LAT);
1023
1024 slottime = ah->slottime;
1025 if (IS_CHAN_5GHZ(chan))
1026 sifstime = 16;
1027 else
1028 sifstime = 10;
1029 }
1030
1031 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1032 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1033 ctstimeout = acktimeout;
1034
1035 /*
1036 * Workaround for early ACK timeouts, add an offset to match the
1037 * initval's 64us ack timeout value.
1038 * This was initially only meant to work around an issue with delayed
1039 * BA frames in some implementations, but it has been found to fix ACK
1040 * timeout issues in other cases as well.
1041 */
1042 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1043 acktimeout += 64 - sifstime - ah->slottime;
1044
1045 ath9k_hw_set_sifs_time(ah, sifstime);
1046 ath9k_hw_setslottime(ah, slottime);
1047 ath9k_hw_set_ack_timeout(ah, acktimeout);
1048 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1049 if (ah->globaltxtimeout != (u32) -1)
1050 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1051
1052 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1053 REG_RMW(ah, AR_USEC,
1054 (common->clockrate - 1) |
1055 SM(rx_lat, AR_USEC_RX_LAT) |
1056 SM(tx_lat, AR_USEC_TX_LAT),
1057 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1058
1059 }
1060 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1061
1062 void ath9k_hw_deinit(struct ath_hw *ah)
1063 {
1064 struct ath_common *common = ath9k_hw_common(ah);
1065
1066 if (common->state < ATH_HW_INITIALIZED)
1067 goto free_hw;
1068
1069 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1070
1071 free_hw:
1072 ath9k_hw_rf_free_ext_banks(ah);
1073 }
1074 EXPORT_SYMBOL(ath9k_hw_deinit);
1075
1076 /*******/
1077 /* INI */
1078 /*******/
1079
1080 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1081 {
1082 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1083
1084 if (IS_CHAN_B(chan))
1085 ctl |= CTL_11B;
1086 else if (IS_CHAN_G(chan))
1087 ctl |= CTL_11G;
1088 else
1089 ctl |= CTL_11A;
1090
1091 return ctl;
1092 }
1093
1094 /****************************************/
1095 /* Reset and Channel Switching Routines */
1096 /****************************************/
1097
1098 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1099 {
1100 struct ath_common *common = ath9k_hw_common(ah);
1101
1102 ENABLE_REGWRITE_BUFFER(ah);
1103
1104 /*
1105 * set AHB_MODE not to do cacheline prefetches
1106 */
1107 if (!AR_SREV_9300_20_OR_LATER(ah))
1108 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1109
1110 /*
1111 * let mac dma reads be in 128 byte chunks
1112 */
1113 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1114
1115 REGWRITE_BUFFER_FLUSH(ah);
1116
1117 /*
1118 * Restore TX Trigger Level to its pre-reset value.
1119 * The initial value depends on whether aggregation is enabled, and is
1120 * adjusted whenever underruns are detected.
1121 */
1122 if (!AR_SREV_9300_20_OR_LATER(ah))
1123 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1124
1125 ENABLE_REGWRITE_BUFFER(ah);
1126
1127 /*
1128 * let mac dma writes be in 128 byte chunks
1129 */
1130 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1131
1132 /*
1133 * Setup receive FIFO threshold to hold off TX activities
1134 */
1135 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1136
1137 if (AR_SREV_9300_20_OR_LATER(ah)) {
1138 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1139 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1140
1141 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1142 ah->caps.rx_status_len);
1143 }
1144
1145 /*
1146 * reduce the number of usable entries in PCU TXBUF to avoid
1147 * wrap around issues.
1148 */
1149 if (AR_SREV_9285(ah)) {
1150 /* For AR9285 the number of Fifos are reduced to half.
1151 * So set the usable tx buf size also to half to
1152 * avoid data/delimiter underruns
1153 */
1154 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1155 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1156 } else if (!AR_SREV_9271(ah)) {
1157 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1158 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1159 }
1160
1161 REGWRITE_BUFFER_FLUSH(ah);
1162
1163 if (AR_SREV_9300_20_OR_LATER(ah))
1164 ath9k_hw_reset_txstatus_ring(ah);
1165 }
1166
1167 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1168 {
1169 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1170 u32 set = AR_STA_ID1_KSRCH_MODE;
1171
1172 switch (opmode) {
1173 case NL80211_IFTYPE_ADHOC:
1174 case NL80211_IFTYPE_MESH_POINT:
1175 set |= AR_STA_ID1_ADHOC;
1176 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1177 break;
1178 case NL80211_IFTYPE_AP:
1179 set |= AR_STA_ID1_STA_AP;
1180 /* fall through */
1181 case NL80211_IFTYPE_STATION:
1182 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1183 break;
1184 default:
1185 if (!ah->is_monitoring)
1186 set = 0;
1187 break;
1188 }
1189 REG_RMW(ah, AR_STA_ID1, set, mask);
1190 }
1191
1192 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1193 u32 *coef_mantissa, u32 *coef_exponent)
1194 {
1195 u32 coef_exp, coef_man;
1196
1197 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1198 if ((coef_scaled >> coef_exp) & 0x1)
1199 break;
1200
1201 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1202
1203 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1204
1205 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1206 *coef_exponent = coef_exp - 16;
1207 }
1208
1209 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1210 {
1211 u32 rst_flags;
1212 u32 tmpReg;
1213
1214 if (AR_SREV_9100(ah)) {
1215 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1216 AR_RTC_DERIVED_CLK_PERIOD, 1);
1217 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1218 }
1219
1220 ENABLE_REGWRITE_BUFFER(ah);
1221
1222 if (AR_SREV_9300_20_OR_LATER(ah)) {
1223 REG_WRITE(ah, AR_WA, ah->WARegVal);
1224 udelay(10);
1225 }
1226
1227 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1228 AR_RTC_FORCE_WAKE_ON_INT);
1229
1230 if (AR_SREV_9100(ah)) {
1231 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1232 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1233 } else {
1234 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1235 if (tmpReg &
1236 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1237 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1238 u32 val;
1239 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1240
1241 val = AR_RC_HOSTIF;
1242 if (!AR_SREV_9300_20_OR_LATER(ah))
1243 val |= AR_RC_AHB;
1244 REG_WRITE(ah, AR_RC, val);
1245
1246 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1247 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1248
1249 rst_flags = AR_RTC_RC_MAC_WARM;
1250 if (type == ATH9K_RESET_COLD)
1251 rst_flags |= AR_RTC_RC_MAC_COLD;
1252 }
1253
1254 if (AR_SREV_9330(ah)) {
1255 int npend = 0;
1256 int i;
1257
1258 /* AR9330 WAR:
1259 * call external reset function to reset WMAC if:
1260 * - doing a cold reset
1261 * - we have pending frames in the TX queues
1262 */
1263
1264 for (i = 0; i < AR_NUM_QCU; i++) {
1265 npend = ath9k_hw_numtxpending(ah, i);
1266 if (npend)
1267 break;
1268 }
1269
1270 if (ah->external_reset &&
1271 (npend || type == ATH9K_RESET_COLD)) {
1272 int reset_err = 0;
1273
1274 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1275 "reset MAC via external reset\n");
1276
1277 reset_err = ah->external_reset();
1278 if (reset_err) {
1279 ath_err(ath9k_hw_common(ah),
1280 "External reset failed, err=%d\n",
1281 reset_err);
1282 return false;
1283 }
1284
1285 REG_WRITE(ah, AR_RTC_RESET, 1);
1286 }
1287 }
1288
1289 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1290
1291 REGWRITE_BUFFER_FLUSH(ah);
1292
1293 udelay(50);
1294
1295 REG_WRITE(ah, AR_RTC_RC, 0);
1296 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1297 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1298 "RTC stuck in MAC reset\n");
1299 return false;
1300 }
1301
1302 if (!AR_SREV_9100(ah))
1303 REG_WRITE(ah, AR_RC, 0);
1304
1305 if (AR_SREV_9100(ah))
1306 udelay(50);
1307
1308 return true;
1309 }
1310
1311 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1312 {
1313 ENABLE_REGWRITE_BUFFER(ah);
1314
1315 if (AR_SREV_9300_20_OR_LATER(ah)) {
1316 REG_WRITE(ah, AR_WA, ah->WARegVal);
1317 udelay(10);
1318 }
1319
1320 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1321 AR_RTC_FORCE_WAKE_ON_INT);
1322
1323 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1324 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1325
1326 REG_WRITE(ah, AR_RTC_RESET, 0);
1327
1328 REGWRITE_BUFFER_FLUSH(ah);
1329
1330 if (!AR_SREV_9300_20_OR_LATER(ah))
1331 udelay(2);
1332
1333 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1334 REG_WRITE(ah, AR_RC, 0);
1335
1336 REG_WRITE(ah, AR_RTC_RESET, 1);
1337
1338 if (!ath9k_hw_wait(ah,
1339 AR_RTC_STATUS,
1340 AR_RTC_STATUS_M,
1341 AR_RTC_STATUS_ON,
1342 AH_WAIT_TIMEOUT)) {
1343 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1344 "RTC not waking up\n");
1345 return false;
1346 }
1347
1348 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1349 }
1350
1351 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1352 {
1353 bool ret = false;
1354
1355 if (AR_SREV_9300_20_OR_LATER(ah)) {
1356 REG_WRITE(ah, AR_WA, ah->WARegVal);
1357 udelay(10);
1358 }
1359
1360 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1361 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1362
1363 switch (type) {
1364 case ATH9K_RESET_POWER_ON:
1365 ret = ath9k_hw_set_reset_power_on(ah);
1366 break;
1367 case ATH9K_RESET_WARM:
1368 case ATH9K_RESET_COLD:
1369 ret = ath9k_hw_set_reset(ah, type);
1370 break;
1371 default:
1372 break;
1373 }
1374
1375 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1376 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1377
1378 return ret;
1379 }
1380
1381 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1382 struct ath9k_channel *chan)
1383 {
1384 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1385 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1386 return false;
1387 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1388 return false;
1389
1390 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1391 return false;
1392
1393 ah->chip_fullsleep = false;
1394 ath9k_hw_init_pll(ah, chan);
1395 ath9k_hw_set_rfmode(ah, chan);
1396
1397 return true;
1398 }
1399
1400 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1401 struct ath9k_channel *chan)
1402 {
1403 struct ath_common *common = ath9k_hw_common(ah);
1404 u32 qnum;
1405 int r;
1406 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1407 bool band_switch, mode_diff;
1408 u8 ini_reloaded;
1409
1410 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1411 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1412 CHANNEL_5GHZ));
1413 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1414
1415 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1416 if (ath9k_hw_numtxpending(ah, qnum)) {
1417 ath_dbg(common, ATH_DBG_QUEUE,
1418 "Transmit frames pending on queue %d\n", qnum);
1419 return false;
1420 }
1421 }
1422
1423 if (!ath9k_hw_rfbus_req(ah)) {
1424 ath_err(common, "Could not kill baseband RX\n");
1425 return false;
1426 }
1427
1428 if (edma && (band_switch || mode_diff)) {
1429 ath9k_hw_mark_phy_inactive(ah);
1430 udelay(5);
1431
1432 ath9k_hw_init_pll(ah, NULL);
1433
1434 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1435 ath_err(common, "Failed to do fast channel change\n");
1436 return false;
1437 }
1438 }
1439
1440 ath9k_hw_set_channel_regs(ah, chan);
1441
1442 r = ath9k_hw_rf_set_freq(ah, chan);
1443 if (r) {
1444 ath_err(common, "Failed to set channel\n");
1445 return false;
1446 }
1447 ath9k_hw_set_clockrate(ah);
1448 ath9k_hw_apply_txpower(ah, chan);
1449 ath9k_hw_rfbus_done(ah);
1450
1451 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1452 ath9k_hw_set_delta_slope(ah, chan);
1453
1454 ath9k_hw_spur_mitigate_freq(ah, chan);
1455
1456 if (edma && (band_switch || mode_diff)) {
1457 ah->ah_flags |= AH_FASTCC;
1458 if (band_switch || ini_reloaded)
1459 ah->eep_ops->set_board_values(ah, chan);
1460
1461 ath9k_hw_init_bb(ah, chan);
1462
1463 if (band_switch || ini_reloaded)
1464 ath9k_hw_init_cal(ah, chan);
1465 ah->ah_flags &= ~AH_FASTCC;
1466 }
1467
1468 return true;
1469 }
1470
1471 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1472 {
1473 u32 gpio_mask = ah->gpio_mask;
1474 int i;
1475
1476 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1477 if (!(gpio_mask & 1))
1478 continue;
1479
1480 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1481 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1482 }
1483 }
1484
1485 bool ath9k_hw_check_alive(struct ath_hw *ah)
1486 {
1487 int count = 50;
1488 u32 reg;
1489
1490 if (AR_SREV_9285_12_OR_LATER(ah))
1491 return true;
1492
1493 do {
1494 reg = REG_READ(ah, AR_OBS_BUS_1);
1495
1496 if ((reg & 0x7E7FFFEF) == 0x00702400)
1497 continue;
1498
1499 switch (reg & 0x7E000B00) {
1500 case 0x1E000000:
1501 case 0x52000B00:
1502 case 0x18000B00:
1503 continue;
1504 default:
1505 return true;
1506 }
1507 } while (count-- > 0);
1508
1509 return false;
1510 }
1511 EXPORT_SYMBOL(ath9k_hw_check_alive);
1512
1513 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1514 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1515 {
1516 struct ath_common *common = ath9k_hw_common(ah);
1517 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
1518 u32 saveLedState;
1519 struct ath9k_channel *curchan = ah->curchan;
1520 u32 saveDefAntenna;
1521 u32 macStaId1;
1522 u64 tsf = 0;
1523 int i, r;
1524 bool allow_fbs = false;
1525 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1526 bool save_fullsleep = ah->chip_fullsleep;
1527
1528 if (mci) {
1529
1530 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan));
1531
1532 if (mci_hw->bt_state == MCI_BT_CAL_START) {
1533 u32 payload[4] = {0, 0, 0, 0};
1534
1535 ath_dbg(common, ATH_DBG_MCI, "MCI stop rx for BT CAL");
1536
1537 mci_hw->bt_state = MCI_BT_CAL;
1538
1539 /*
1540 * MCI FIX: disable mci interrupt here. This is to avoid
1541 * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and
1542 * lead to mci_intr reentry.
1543 */
1544
1545 ar9003_mci_disable_interrupt(ah);
1546
1547 ath_dbg(common, ATH_DBG_MCI, "send WLAN_CAL_GRANT");
1548 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT);
1549 ar9003_mci_send_message(ah, MCI_GPM, 0, payload,
1550 16, true, false);
1551
1552 ath_dbg(common, ATH_DBG_MCI, "\nMCI BT is calibrating");
1553
1554 /* Wait BT calibration to be completed for 25ms */
1555
1556 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE,
1557 0, 25000))
1558 ath_dbg(common, ATH_DBG_MCI,
1559 "MCI got BT_CAL_DONE\n");
1560 else
1561 ath_dbg(common, ATH_DBG_MCI,
1562 "MCI ### BT cal takes to long, force"
1563 "bt_state to be bt_awake\n");
1564 mci_hw->bt_state = MCI_BT_AWAKE;
1565 /* MCI FIX: enable mci interrupt here */
1566 ar9003_mci_enable_interrupt(ah);
1567
1568 return true;
1569 }
1570 }
1571
1572
1573 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1574 return -EIO;
1575
1576 if (curchan && !ah->chip_fullsleep)
1577 ath9k_hw_getnf(ah, curchan);
1578
1579 ah->caldata = caldata;
1580 if (caldata &&
1581 (chan->channel != caldata->channel ||
1582 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1583 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1584 /* Operating channel changed, reset channel calibration data */
1585 memset(caldata, 0, sizeof(*caldata));
1586 ath9k_init_nfcal_hist_buffer(ah, chan);
1587 }
1588 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1589
1590 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1591 bChannelChange = false;
1592
1593 if (caldata &&
1594 caldata->done_txiqcal_once &&
1595 caldata->done_txclcal_once &&
1596 caldata->rtt_hist.num_readings)
1597 allow_fbs = true;
1598
1599 if (bChannelChange &&
1600 (ah->chip_fullsleep != true) &&
1601 (ah->curchan != NULL) &&
1602 (chan->channel != ah->curchan->channel) &&
1603 (allow_fbs ||
1604 ((chan->channelFlags & CHANNEL_ALL) ==
1605 (ah->curchan->channelFlags & CHANNEL_ALL)))) {
1606 if (ath9k_hw_channel_change(ah, chan)) {
1607 ath9k_hw_loadnf(ah, ah->curchan);
1608 ath9k_hw_start_nfcal(ah, true);
1609 if (mci && mci_hw->ready)
1610 ar9003_mci_2g5g_switch(ah, true);
1611
1612 if (AR_SREV_9271(ah))
1613 ar9002_hw_load_ani_reg(ah, chan);
1614 return 0;
1615 }
1616 }
1617
1618 if (mci) {
1619 ar9003_mci_disable_interrupt(ah);
1620
1621 if (mci_hw->ready && !save_fullsleep) {
1622 ar9003_mci_mute_bt(ah);
1623 udelay(20);
1624 REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
1625 }
1626
1627 mci_hw->bt_state = MCI_BT_SLEEP;
1628 mci_hw->ready = false;
1629 }
1630
1631
1632 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1633 if (saveDefAntenna == 0)
1634 saveDefAntenna = 1;
1635
1636 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1637
1638 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1639 if (AR_SREV_9100(ah) ||
1640 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1641 tsf = ath9k_hw_gettsf64(ah);
1642
1643 saveLedState = REG_READ(ah, AR_CFG_LED) &
1644 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1645 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1646
1647 ath9k_hw_mark_phy_inactive(ah);
1648
1649 ah->paprd_table_write_done = false;
1650
1651 /* Only required on the first reset */
1652 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1653 REG_WRITE(ah,
1654 AR9271_RESET_POWER_DOWN_CONTROL,
1655 AR9271_RADIO_RF_RST);
1656 udelay(50);
1657 }
1658
1659 if (!ath9k_hw_chip_reset(ah, chan)) {
1660 ath_err(common, "Chip reset failed\n");
1661 return -EINVAL;
1662 }
1663
1664 /* Only required on the first reset */
1665 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1666 ah->htc_reset_init = false;
1667 REG_WRITE(ah,
1668 AR9271_RESET_POWER_DOWN_CONTROL,
1669 AR9271_GATE_MAC_CTL);
1670 udelay(50);
1671 }
1672
1673 /* Restore TSF */
1674 if (tsf)
1675 ath9k_hw_settsf64(ah, tsf);
1676
1677 if (AR_SREV_9280_20_OR_LATER(ah))
1678 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1679
1680 if (!AR_SREV_9300_20_OR_LATER(ah))
1681 ar9002_hw_enable_async_fifo(ah);
1682
1683 r = ath9k_hw_process_ini(ah, chan);
1684 if (r)
1685 return r;
1686
1687 if (mci)
1688 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1689
1690 /*
1691 * Some AR91xx SoC devices frequently fail to accept TSF writes
1692 * right after the chip reset. When that happens, write a new
1693 * value after the initvals have been applied, with an offset
1694 * based on measured time difference
1695 */
1696 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1697 tsf += 1500;
1698 ath9k_hw_settsf64(ah, tsf);
1699 }
1700
1701 /* Setup MFP options for CCMP */
1702 if (AR_SREV_9280_20_OR_LATER(ah)) {
1703 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1704 * frames when constructing CCMP AAD. */
1705 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1706 0xc7ff);
1707 ah->sw_mgmt_crypto = false;
1708 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1709 /* Disable hardware crypto for management frames */
1710 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1711 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1712 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1713 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1714 ah->sw_mgmt_crypto = true;
1715 } else
1716 ah->sw_mgmt_crypto = true;
1717
1718 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1719 ath9k_hw_set_delta_slope(ah, chan);
1720
1721 ath9k_hw_spur_mitigate_freq(ah, chan);
1722 ah->eep_ops->set_board_values(ah, chan);
1723
1724 ENABLE_REGWRITE_BUFFER(ah);
1725
1726 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1727 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1728 | macStaId1
1729 | AR_STA_ID1_RTS_USE_DEF
1730 | (ah->config.
1731 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1732 | ah->sta_id1_defaults);
1733 ath_hw_setbssidmask(common);
1734 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1735 ath9k_hw_write_associd(ah);
1736 REG_WRITE(ah, AR_ISR, ~0);
1737 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1738
1739 REGWRITE_BUFFER_FLUSH(ah);
1740
1741 ath9k_hw_set_operating_mode(ah, ah->opmode);
1742
1743 r = ath9k_hw_rf_set_freq(ah, chan);
1744 if (r)
1745 return r;
1746
1747 ath9k_hw_set_clockrate(ah);
1748
1749 ENABLE_REGWRITE_BUFFER(ah);
1750
1751 for (i = 0; i < AR_NUM_DCU; i++)
1752 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1753
1754 REGWRITE_BUFFER_FLUSH(ah);
1755
1756 ah->intr_txqs = 0;
1757 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1758 ath9k_hw_resettxqueue(ah, i);
1759
1760 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1761 ath9k_hw_ani_cache_ini_regs(ah);
1762 ath9k_hw_init_qos(ah);
1763
1764 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1765 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1766
1767 ath9k_hw_init_global_settings(ah);
1768
1769 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1770 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1771 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1772 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1773 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1774 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1775 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1776 }
1777
1778 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1779
1780 ath9k_hw_set_dma(ah);
1781
1782 REG_WRITE(ah, AR_OBS, 8);
1783
1784 if (ah->config.rx_intr_mitigation) {
1785 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1786 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1787 }
1788
1789 if (ah->config.tx_intr_mitigation) {
1790 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1791 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1792 }
1793
1794 ath9k_hw_init_bb(ah, chan);
1795
1796 if (caldata) {
1797 caldata->done_txiqcal_once = false;
1798 caldata->done_txclcal_once = false;
1799 caldata->rtt_hist.num_readings = 0;
1800 }
1801 if (!ath9k_hw_init_cal(ah, chan))
1802 return -EIO;
1803
1804 ath9k_hw_loadnf(ah, chan);
1805 ath9k_hw_start_nfcal(ah, true);
1806
1807 if (mci && mci_hw->ready) {
1808
1809 if (IS_CHAN_2GHZ(chan) &&
1810 (mci_hw->bt_state == MCI_BT_SLEEP)) {
1811
1812 if (ar9003_mci_check_int(ah,
1813 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
1814 ar9003_mci_check_int(ah,
1815 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) {
1816
1817 /*
1818 * BT is sleeping. Check if BT wakes up during
1819 * WLAN calibration. If BT wakes up during
1820 * WLAN calibration, need to go through all
1821 * message exchanges again and recal.
1822 */
1823
1824 ath_dbg(common, ATH_DBG_MCI, "MCI BT wakes up"
1825 "during WLAN calibration\n");
1826
1827 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1828 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
1829 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE);
1830 ath_dbg(common, ATH_DBG_MCI, "MCI send"
1831 "REMOTE_RESET\n");
1832 ar9003_mci_remote_reset(ah, true);
1833 ar9003_mci_send_sys_waking(ah, true);
1834 udelay(1);
1835 if (IS_CHAN_2GHZ(chan))
1836 ar9003_mci_send_lna_transfer(ah, true);
1837
1838 mci_hw->bt_state = MCI_BT_AWAKE;
1839
1840 ath_dbg(common, ATH_DBG_MCI, "MCI re-cal\n");
1841
1842 if (caldata) {
1843 caldata->done_txiqcal_once = false;
1844 caldata->done_txclcal_once = false;
1845 caldata->rtt_hist.num_readings = 0;
1846 }
1847
1848 if (!ath9k_hw_init_cal(ah, chan))
1849 return -EIO;
1850
1851 }
1852 }
1853 ar9003_mci_enable_interrupt(ah);
1854 }
1855
1856 ENABLE_REGWRITE_BUFFER(ah);
1857
1858 ath9k_hw_restore_chainmask(ah);
1859 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1860
1861 REGWRITE_BUFFER_FLUSH(ah);
1862
1863 /*
1864 * For big endian systems turn on swapping for descriptors
1865 */
1866 if (AR_SREV_9100(ah)) {
1867 u32 mask;
1868 mask = REG_READ(ah, AR_CFG);
1869 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1870 ath_dbg(common, ATH_DBG_RESET,
1871 "CFG Byte Swap Set 0x%x\n", mask);
1872 } else {
1873 mask =
1874 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1875 REG_WRITE(ah, AR_CFG, mask);
1876 ath_dbg(common, ATH_DBG_RESET,
1877 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1878 }
1879 } else {
1880 if (common->bus_ops->ath_bus_type == ATH_USB) {
1881 /* Configure AR9271 target WLAN */
1882 if (AR_SREV_9271(ah))
1883 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1884 else
1885 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1886 }
1887 #ifdef __BIG_ENDIAN
1888 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1889 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1890 else
1891 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1892 #endif
1893 }
1894
1895 if (ah->btcoex_hw.enabled)
1896 ath9k_hw_btcoex_enable(ah);
1897
1898 if (mci && mci_hw->ready) {
1899 /*
1900 * check BT state again to make
1901 * sure it's not changed.
1902 */
1903
1904 ar9003_mci_sync_bt_state(ah);
1905 ar9003_mci_2g5g_switch(ah, true);
1906
1907 if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
1908 (mci_hw->query_bt == true)) {
1909 mci_hw->need_flush_btinfo = true;
1910 }
1911 }
1912
1913 if (AR_SREV_9300_20_OR_LATER(ah)) {
1914 ar9003_hw_bb_watchdog_config(ah);
1915
1916 ar9003_hw_disable_phy_restart(ah);
1917 }
1918
1919 ath9k_hw_apply_gpio_override(ah);
1920
1921 return 0;
1922 }
1923 EXPORT_SYMBOL(ath9k_hw_reset);
1924
1925 /******************************/
1926 /* Power Management (Chipset) */
1927 /******************************/
1928
1929 /*
1930 * Notify Power Mgt is disabled in self-generated frames.
1931 * If requested, force chip to sleep.
1932 */
1933 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1934 {
1935 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1936 if (setChip) {
1937 if (AR_SREV_9462(ah)) {
1938 REG_WRITE(ah, AR_TIMER_MODE,
1939 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1940 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1941 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1942 REG_WRITE(ah, AR_SLP32_INC,
1943 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1944 /* xxx Required for WLAN only case ? */
1945 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1946 udelay(100);
1947 }
1948
1949 /*
1950 * Clear the RTC force wake bit to allow the
1951 * mac to go to sleep.
1952 */
1953 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1954
1955 if (AR_SREV_9462(ah))
1956 udelay(100);
1957
1958 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1959 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1960
1961 /* Shutdown chip. Active low */
1962 if (!AR_SREV_5416(ah) &&
1963 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) {
1964 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1965 udelay(2);
1966 }
1967 }
1968
1969 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1970 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1971 }
1972
1973 /*
1974 * Notify Power Management is enabled in self-generating
1975 * frames. If request, set power mode of chip to
1976 * auto/normal. Duration in units of 128us (1/8 TU).
1977 */
1978 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1979 {
1980 u32 val;
1981
1982 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1983 if (setChip) {
1984 struct ath9k_hw_capabilities *pCap = &ah->caps;
1985
1986 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1987 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1988 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1989 AR_RTC_FORCE_WAKE_ON_INT);
1990 } else {
1991
1992 /* When chip goes into network sleep, it could be waken
1993 * up by MCI_INT interrupt caused by BT's HW messages
1994 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1995 * rate (~100us). This will cause chip to leave and
1996 * re-enter network sleep mode frequently, which in
1997 * consequence will have WLAN MCI HW to generate lots of
1998 * SYS_WAKING and SYS_SLEEPING messages which will make
1999 * BT CPU to busy to process.
2000 */
2001 if (AR_SREV_9462(ah)) {
2002 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
2003 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
2004 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2005 }
2006 /*
2007 * Clear the RTC force wake bit to allow the
2008 * mac to go to sleep.
2009 */
2010 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2011 AR_RTC_FORCE_WAKE_EN);
2012
2013 if (AR_SREV_9462(ah))
2014 udelay(30);
2015 }
2016 }
2017
2018 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2019 if (AR_SREV_9300_20_OR_LATER(ah))
2020 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2021 }
2022
2023 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2024 {
2025 u32 val;
2026 int i;
2027
2028 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2029 if (AR_SREV_9300_20_OR_LATER(ah)) {
2030 REG_WRITE(ah, AR_WA, ah->WARegVal);
2031 udelay(10);
2032 }
2033
2034 if (setChip) {
2035 if ((REG_READ(ah, AR_RTC_STATUS) &
2036 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2037 if (ath9k_hw_set_reset_reg(ah,
2038 ATH9K_RESET_POWER_ON) != true) {
2039 return false;
2040 }
2041 if (!AR_SREV_9300_20_OR_LATER(ah))
2042 ath9k_hw_init_pll(ah, NULL);
2043 }
2044 if (AR_SREV_9100(ah))
2045 REG_SET_BIT(ah, AR_RTC_RESET,
2046 AR_RTC_RESET_EN);
2047
2048 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2049 AR_RTC_FORCE_WAKE_EN);
2050 udelay(50);
2051
2052 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2053 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2054 if (val == AR_RTC_STATUS_ON)
2055 break;
2056 udelay(50);
2057 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2058 AR_RTC_FORCE_WAKE_EN);
2059 }
2060 if (i == 0) {
2061 ath_err(ath9k_hw_common(ah),
2062 "Failed to wakeup in %uus\n",
2063 POWER_UP_TIME / 20);
2064 return false;
2065 }
2066 }
2067
2068 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2069
2070 return true;
2071 }
2072
2073 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2074 {
2075 struct ath_common *common = ath9k_hw_common(ah);
2076 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
2077 int status = true, setChip = true;
2078 static const char *modes[] = {
2079 "AWAKE",
2080 "FULL-SLEEP",
2081 "NETWORK SLEEP",
2082 "UNDEFINED"
2083 };
2084
2085 if (ah->power_mode == mode)
2086 return status;
2087
2088 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
2089 modes[ah->power_mode], modes[mode]);
2090
2091 switch (mode) {
2092 case ATH9K_PM_AWAKE:
2093 status = ath9k_hw_set_power_awake(ah, setChip);
2094
2095 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2096 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2097
2098 break;
2099 case ATH9K_PM_FULL_SLEEP:
2100
2101 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) {
2102 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) &&
2103 (mci->bt_state != MCI_BT_SLEEP) &&
2104 !mci->halted_bt_gpm) {
2105 ath_dbg(common, ATH_DBG_MCI, "MCI halt BT GPM"
2106 "(full_sleep)");
2107 ar9003_mci_send_coex_halt_bt_gpm(ah,
2108 true, true);
2109 }
2110
2111 mci->ready = false;
2112 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2113 }
2114
2115 ath9k_set_power_sleep(ah, setChip);
2116 ah->chip_fullsleep = true;
2117 break;
2118 case ATH9K_PM_NETWORK_SLEEP:
2119
2120 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2121 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2122
2123 ath9k_set_power_network_sleep(ah, setChip);
2124 break;
2125 default:
2126 ath_err(common, "Unknown power mode %u\n", mode);
2127 return false;
2128 }
2129 ah->power_mode = mode;
2130
2131 /*
2132 * XXX: If this warning never comes up after a while then
2133 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2134 * ath9k_hw_setpower() return type void.
2135 */
2136
2137 if (!(ah->ah_flags & AH_UNPLUGGED))
2138 ATH_DBG_WARN_ON_ONCE(!status);
2139
2140 return status;
2141 }
2142 EXPORT_SYMBOL(ath9k_hw_setpower);
2143
2144 /*******************/
2145 /* Beacon Handling */
2146 /*******************/
2147
2148 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2149 {
2150 int flags = 0;
2151
2152 ENABLE_REGWRITE_BUFFER(ah);
2153
2154 switch (ah->opmode) {
2155 case NL80211_IFTYPE_ADHOC:
2156 case NL80211_IFTYPE_MESH_POINT:
2157 REG_SET_BIT(ah, AR_TXCFG,
2158 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2159 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2160 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2161 flags |= AR_NDP_TIMER_EN;
2162 case NL80211_IFTYPE_AP:
2163 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2164 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2165 TU_TO_USEC(ah->config.dma_beacon_response_time));
2166 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2167 TU_TO_USEC(ah->config.sw_beacon_response_time));
2168 flags |=
2169 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2170 break;
2171 default:
2172 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
2173 "%s: unsupported opmode: %d\n",
2174 __func__, ah->opmode);
2175 return;
2176 break;
2177 }
2178
2179 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2180 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2181 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2182 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2183
2184 REGWRITE_BUFFER_FLUSH(ah);
2185
2186 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2187 }
2188 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2189
2190 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2191 const struct ath9k_beacon_state *bs)
2192 {
2193 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2194 struct ath9k_hw_capabilities *pCap = &ah->caps;
2195 struct ath_common *common = ath9k_hw_common(ah);
2196
2197 ENABLE_REGWRITE_BUFFER(ah);
2198
2199 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2200
2201 REG_WRITE(ah, AR_BEACON_PERIOD,
2202 TU_TO_USEC(bs->bs_intval));
2203 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2204 TU_TO_USEC(bs->bs_intval));
2205
2206 REGWRITE_BUFFER_FLUSH(ah);
2207
2208 REG_RMW_FIELD(ah, AR_RSSI_THR,
2209 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2210
2211 beaconintval = bs->bs_intval;
2212
2213 if (bs->bs_sleepduration > beaconintval)
2214 beaconintval = bs->bs_sleepduration;
2215
2216 dtimperiod = bs->bs_dtimperiod;
2217 if (bs->bs_sleepduration > dtimperiod)
2218 dtimperiod = bs->bs_sleepduration;
2219
2220 if (beaconintval == dtimperiod)
2221 nextTbtt = bs->bs_nextdtim;
2222 else
2223 nextTbtt = bs->bs_nexttbtt;
2224
2225 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2226 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2227 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2228 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2229
2230 ENABLE_REGWRITE_BUFFER(ah);
2231
2232 REG_WRITE(ah, AR_NEXT_DTIM,
2233 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2234 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2235
2236 REG_WRITE(ah, AR_SLEEP1,
2237 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2238 | AR_SLEEP1_ASSUME_DTIM);
2239
2240 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2241 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2242 else
2243 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2244
2245 REG_WRITE(ah, AR_SLEEP2,
2246 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2247
2248 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2249 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2250
2251 REGWRITE_BUFFER_FLUSH(ah);
2252
2253 REG_SET_BIT(ah, AR_TIMER_MODE,
2254 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2255 AR_DTIM_TIMER_EN);
2256
2257 /* TSF Out of Range Threshold */
2258 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2259 }
2260 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2261
2262 /*******************/
2263 /* HW Capabilities */
2264 /*******************/
2265
2266 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2267 {
2268 eeprom_chainmask &= chip_chainmask;
2269 if (eeprom_chainmask)
2270 return eeprom_chainmask;
2271 else
2272 return chip_chainmask;
2273 }
2274
2275 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2276 {
2277 struct ath9k_hw_capabilities *pCap = &ah->caps;
2278 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2279 struct ath_common *common = ath9k_hw_common(ah);
2280 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2281 unsigned int chip_chainmask;
2282
2283 u16 eeval;
2284 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2285
2286 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2287 regulatory->current_rd = eeval;
2288
2289 if (ah->opmode != NL80211_IFTYPE_AP &&
2290 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2291 if (regulatory->current_rd == 0x64 ||
2292 regulatory->current_rd == 0x65)
2293 regulatory->current_rd += 5;
2294 else if (regulatory->current_rd == 0x41)
2295 regulatory->current_rd = 0x43;
2296 ath_dbg(common, ATH_DBG_REGULATORY,
2297 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2298 }
2299
2300 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2301 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2302 ath_err(common,
2303 "no band has been marked as supported in EEPROM\n");
2304 return -EINVAL;
2305 }
2306
2307 if (eeval & AR5416_OPFLAGS_11A)
2308 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2309
2310 if (eeval & AR5416_OPFLAGS_11G)
2311 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2312
2313 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2314 chip_chainmask = 1;
2315 else if (AR_SREV_9462(ah))
2316 chip_chainmask = 3;
2317 else if (!AR_SREV_9280_20_OR_LATER(ah))
2318 chip_chainmask = 7;
2319 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2320 chip_chainmask = 3;
2321 else
2322 chip_chainmask = 7;
2323
2324 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2325 /*
2326 * For AR9271 we will temporarilly uses the rx chainmax as read from
2327 * the EEPROM.
2328 */
2329 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2330 !(eeval & AR5416_OPFLAGS_11A) &&
2331 !(AR_SREV_9271(ah)))
2332 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2333 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2334 else if (AR_SREV_9100(ah))
2335 pCap->rx_chainmask = 0x7;
2336 else
2337 /* Use rx_chainmask from EEPROM. */
2338 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2339
2340 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2341 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2342 ah->txchainmask = pCap->tx_chainmask;
2343 ah->rxchainmask = pCap->rx_chainmask;
2344
2345 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2346
2347 /* enable key search for every frame in an aggregate */
2348 if (AR_SREV_9300_20_OR_LATER(ah))
2349 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2350
2351 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2352
2353 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2354 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2355 else
2356 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2357
2358 if (AR_SREV_9271(ah))
2359 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2360 else if (AR_DEVID_7010(ah))
2361 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2362 else if (AR_SREV_9300_20_OR_LATER(ah))
2363 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2364 else if (AR_SREV_9287_11_OR_LATER(ah))
2365 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2366 else if (AR_SREV_9285_12_OR_LATER(ah))
2367 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2368 else if (AR_SREV_9280_20_OR_LATER(ah))
2369 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2370 else
2371 pCap->num_gpio_pins = AR_NUM_GPIO;
2372
2373 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2374 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2375 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2376 } else {
2377 pCap->rts_aggr_limit = (8 * 1024);
2378 }
2379
2380 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2381 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2382 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2383 ah->rfkill_gpio =
2384 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2385 ah->rfkill_polarity =
2386 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2387
2388 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2389 }
2390 #endif
2391 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2392 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2393 else
2394 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2395
2396 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2397 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2398 else
2399 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2400
2401 if (common->btcoex_enabled) {
2402 if (AR_SREV_9462(ah))
2403 btcoex_hw->scheme = ATH_BTCOEX_CFG_MCI;
2404 else if (AR_SREV_9300_20_OR_LATER(ah)) {
2405 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2406 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2407 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2408 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2409 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2410 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2411 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2412
2413 if (AR_SREV_9285(ah)) {
2414 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2415 btcoex_hw->btpriority_gpio =
2416 ATH_BTPRIORITY_GPIO_9285;
2417 } else {
2418 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2419 }
2420 }
2421 } else {
2422 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2423 }
2424
2425 if (AR_SREV_9300_20_OR_LATER(ah)) {
2426 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2427 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2428 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2429
2430 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2431 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2432 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2433 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2434 pCap->txs_len = sizeof(struct ar9003_txs);
2435 if (!ah->config.paprd_disable &&
2436 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2437 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2438 } else {
2439 pCap->tx_desc_len = sizeof(struct ath_desc);
2440 if (AR_SREV_9280_20(ah))
2441 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2442 }
2443
2444 if (AR_SREV_9300_20_OR_LATER(ah))
2445 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2446
2447 if (AR_SREV_9300_20_OR_LATER(ah))
2448 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2449
2450 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2451 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2452
2453 if (AR_SREV_9285(ah))
2454 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2455 ant_div_ctl1 =
2456 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2457 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2458 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2459 }
2460 if (AR_SREV_9300_20_OR_LATER(ah)) {
2461 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2462 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2463 }
2464
2465
2466 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2467 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2468 /*
2469 * enable the diversity-combining algorithm only when
2470 * both enable_lna_div and enable_fast_div are set
2471 * Table for Diversity
2472 * ant_div_alt_lnaconf bit 0-1
2473 * ant_div_main_lnaconf bit 2-3
2474 * ant_div_alt_gaintb bit 4
2475 * ant_div_main_gaintb bit 5
2476 * enable_ant_div_lnadiv bit 6
2477 * enable_ant_fast_div bit 7
2478 */
2479 if ((ant_div_ctl1 >> 0x6) == 0x3)
2480 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2481 }
2482
2483 if (AR_SREV_9485_10(ah)) {
2484 pCap->pcie_lcr_extsync_en = true;
2485 pCap->pcie_lcr_offset = 0x80;
2486 }
2487
2488 tx_chainmask = pCap->tx_chainmask;
2489 rx_chainmask = pCap->rx_chainmask;
2490 while (tx_chainmask || rx_chainmask) {
2491 if (tx_chainmask & BIT(0))
2492 pCap->max_txchains++;
2493 if (rx_chainmask & BIT(0))
2494 pCap->max_rxchains++;
2495
2496 tx_chainmask >>= 1;
2497 rx_chainmask >>= 1;
2498 }
2499
2500 if (AR_SREV_9300_20_OR_LATER(ah)) {
2501 ah->enabled_cals |= TX_IQ_CAL;
2502 if (AR_SREV_9485_OR_LATER(ah))
2503 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2504 }
2505 if (AR_SREV_9462(ah))
2506 pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI;
2507
2508 return 0;
2509 }
2510
2511 /****************************/
2512 /* GPIO / RFKILL / Antennae */
2513 /****************************/
2514
2515 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2516 u32 gpio, u32 type)
2517 {
2518 int addr;
2519 u32 gpio_shift, tmp;
2520
2521 if (gpio > 11)
2522 addr = AR_GPIO_OUTPUT_MUX3;
2523 else if (gpio > 5)
2524 addr = AR_GPIO_OUTPUT_MUX2;
2525 else
2526 addr = AR_GPIO_OUTPUT_MUX1;
2527
2528 gpio_shift = (gpio % 6) * 5;
2529
2530 if (AR_SREV_9280_20_OR_LATER(ah)
2531 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2532 REG_RMW(ah, addr, (type << gpio_shift),
2533 (0x1f << gpio_shift));
2534 } else {
2535 tmp = REG_READ(ah, addr);
2536 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2537 tmp &= ~(0x1f << gpio_shift);
2538 tmp |= (type << gpio_shift);
2539 REG_WRITE(ah, addr, tmp);
2540 }
2541 }
2542
2543 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2544 {
2545 u32 gpio_shift;
2546
2547 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2548
2549 if (AR_DEVID_7010(ah)) {
2550 gpio_shift = gpio;
2551 REG_RMW(ah, AR7010_GPIO_OE,
2552 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2553 (AR7010_GPIO_OE_MASK << gpio_shift));
2554 return;
2555 }
2556
2557 gpio_shift = gpio << 1;
2558 REG_RMW(ah,
2559 AR_GPIO_OE_OUT,
2560 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2561 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2562 }
2563 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2564
2565 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2566 {
2567 #define MS_REG_READ(x, y) \
2568 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2569
2570 if (gpio >= ah->caps.num_gpio_pins)
2571 return 0xffffffff;
2572
2573 if (AR_DEVID_7010(ah)) {
2574 u32 val;
2575 val = REG_READ(ah, AR7010_GPIO_IN);
2576 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2577 } else if (AR_SREV_9300_20_OR_LATER(ah))
2578 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2579 AR_GPIO_BIT(gpio)) != 0;
2580 else if (AR_SREV_9271(ah))
2581 return MS_REG_READ(AR9271, gpio) != 0;
2582 else if (AR_SREV_9287_11_OR_LATER(ah))
2583 return MS_REG_READ(AR9287, gpio) != 0;
2584 else if (AR_SREV_9285_12_OR_LATER(ah))
2585 return MS_REG_READ(AR9285, gpio) != 0;
2586 else if (AR_SREV_9280_20_OR_LATER(ah))
2587 return MS_REG_READ(AR928X, gpio) != 0;
2588 else
2589 return MS_REG_READ(AR, gpio) != 0;
2590 }
2591 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2592
2593 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2594 u32 ah_signal_type)
2595 {
2596 u32 gpio_shift;
2597
2598 if (AR_DEVID_7010(ah)) {
2599 gpio_shift = gpio;
2600 REG_RMW(ah, AR7010_GPIO_OE,
2601 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2602 (AR7010_GPIO_OE_MASK << gpio_shift));
2603 return;
2604 }
2605
2606 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2607 gpio_shift = 2 * gpio;
2608 REG_RMW(ah,
2609 AR_GPIO_OE_OUT,
2610 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2611 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2612 }
2613 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2614
2615 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2616 {
2617 if (AR_DEVID_7010(ah)) {
2618 val = val ? 0 : 1;
2619 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2620 AR_GPIO_BIT(gpio));
2621 return;
2622 }
2623
2624 if (AR_SREV_9271(ah))
2625 val = ~val;
2626
2627 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2628 AR_GPIO_BIT(gpio));
2629 }
2630 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2631
2632 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2633 {
2634 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2635 }
2636 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2637
2638 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2639 {
2640 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2641 }
2642 EXPORT_SYMBOL(ath9k_hw_setantenna);
2643
2644 /*********************/
2645 /* General Operation */
2646 /*********************/
2647
2648 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2649 {
2650 u32 bits = REG_READ(ah, AR_RX_FILTER);
2651 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2652
2653 if (phybits & AR_PHY_ERR_RADAR)
2654 bits |= ATH9K_RX_FILTER_PHYRADAR;
2655 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2656 bits |= ATH9K_RX_FILTER_PHYERR;
2657
2658 return bits;
2659 }
2660 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2661
2662 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2663 {
2664 u32 phybits;
2665
2666 ENABLE_REGWRITE_BUFFER(ah);
2667
2668 if (AR_SREV_9462(ah))
2669 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2670
2671 REG_WRITE(ah, AR_RX_FILTER, bits);
2672
2673 phybits = 0;
2674 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2675 phybits |= AR_PHY_ERR_RADAR;
2676 if (bits & ATH9K_RX_FILTER_PHYERR)
2677 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2678 REG_WRITE(ah, AR_PHY_ERR, phybits);
2679
2680 if (phybits)
2681 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2682 else
2683 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2684
2685 REGWRITE_BUFFER_FLUSH(ah);
2686 }
2687 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2688
2689 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2690 {
2691 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2692 return false;
2693
2694 ath9k_hw_init_pll(ah, NULL);
2695 return true;
2696 }
2697 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2698
2699 bool ath9k_hw_disable(struct ath_hw *ah)
2700 {
2701 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2702 return false;
2703
2704 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2705 return false;
2706
2707 ath9k_hw_init_pll(ah, NULL);
2708 return true;
2709 }
2710 EXPORT_SYMBOL(ath9k_hw_disable);
2711
2712 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2713 {
2714 enum eeprom_param gain_param;
2715
2716 if (IS_CHAN_2GHZ(chan))
2717 gain_param = EEP_ANTENNA_GAIN_2G;
2718 else
2719 gain_param = EEP_ANTENNA_GAIN_5G;
2720
2721 return ah->eep_ops->get_eeprom(ah, gain_param);
2722 }
2723
2724 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2725 {
2726 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2727 struct ieee80211_channel *channel;
2728 int chan_pwr, new_pwr, max_gain;
2729 int ant_gain, ant_reduction = 0;
2730
2731 if (!chan)
2732 return;
2733
2734 channel = chan->chan;
2735 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2736 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2737 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2738
2739 ant_gain = get_antenna_gain(ah, chan);
2740 if (ant_gain > max_gain)
2741 ant_reduction = ant_gain - max_gain;
2742
2743 ah->eep_ops->set_txpower(ah, chan,
2744 ath9k_regd_get_ctl(reg, chan),
2745 ant_reduction, new_pwr, false);
2746 }
2747
2748 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2749 {
2750 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2751 struct ath9k_channel *chan = ah->curchan;
2752 struct ieee80211_channel *channel = chan->chan;
2753
2754 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2755 if (test)
2756 channel->max_power = MAX_RATE_POWER / 2;
2757
2758 ath9k_hw_apply_txpower(ah, chan);
2759
2760 if (test)
2761 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2762 }
2763 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2764
2765 void ath9k_hw_setopmode(struct ath_hw *ah)
2766 {
2767 ath9k_hw_set_operating_mode(ah, ah->opmode);
2768 }
2769 EXPORT_SYMBOL(ath9k_hw_setopmode);
2770
2771 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2772 {
2773 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2774 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2775 }
2776 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2777
2778 void ath9k_hw_write_associd(struct ath_hw *ah)
2779 {
2780 struct ath_common *common = ath9k_hw_common(ah);
2781
2782 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2783 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2784 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2785 }
2786 EXPORT_SYMBOL(ath9k_hw_write_associd);
2787
2788 #define ATH9K_MAX_TSF_READ 10
2789
2790 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2791 {
2792 u32 tsf_lower, tsf_upper1, tsf_upper2;
2793 int i;
2794
2795 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2796 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2797 tsf_lower = REG_READ(ah, AR_TSF_L32);
2798 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2799 if (tsf_upper2 == tsf_upper1)
2800 break;
2801 tsf_upper1 = tsf_upper2;
2802 }
2803
2804 WARN_ON( i == ATH9K_MAX_TSF_READ );
2805
2806 return (((u64)tsf_upper1 << 32) | tsf_lower);
2807 }
2808 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2809
2810 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2811 {
2812 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2813 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2814 }
2815 EXPORT_SYMBOL(ath9k_hw_settsf64);
2816
2817 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2818 {
2819 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2820 AH_TSF_WRITE_TIMEOUT))
2821 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2822 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2823
2824 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2825 }
2826 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2827
2828 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2829 {
2830 if (setting)
2831 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2832 else
2833 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2834 }
2835 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2836
2837 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2838 {
2839 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2840 u32 macmode;
2841
2842 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2843 macmode = AR_2040_JOINED_RX_CLEAR;
2844 else
2845 macmode = 0;
2846
2847 REG_WRITE(ah, AR_2040_MODE, macmode);
2848 }
2849
2850 /* HW Generic timers configuration */
2851
2852 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2853 {
2854 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2855 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2856 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2857 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2858 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2859 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2860 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2861 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2862 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2863 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2864 AR_NDP2_TIMER_MODE, 0x0002},
2865 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2866 AR_NDP2_TIMER_MODE, 0x0004},
2867 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2868 AR_NDP2_TIMER_MODE, 0x0008},
2869 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2870 AR_NDP2_TIMER_MODE, 0x0010},
2871 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2872 AR_NDP2_TIMER_MODE, 0x0020},
2873 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2874 AR_NDP2_TIMER_MODE, 0x0040},
2875 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2876 AR_NDP2_TIMER_MODE, 0x0080}
2877 };
2878
2879 /* HW generic timer primitives */
2880
2881 /* compute and clear index of rightmost 1 */
2882 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2883 {
2884 u32 b;
2885
2886 b = *mask;
2887 b &= (0-b);
2888 *mask &= ~b;
2889 b *= debruijn32;
2890 b >>= 27;
2891
2892 return timer_table->gen_timer_index[b];
2893 }
2894
2895 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2896 {
2897 return REG_READ(ah, AR_TSF_L32);
2898 }
2899 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2900
2901 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2902 void (*trigger)(void *),
2903 void (*overflow)(void *),
2904 void *arg,
2905 u8 timer_index)
2906 {
2907 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2908 struct ath_gen_timer *timer;
2909
2910 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2911
2912 if (timer == NULL) {
2913 ath_err(ath9k_hw_common(ah),
2914 "Failed to allocate memory for hw timer[%d]\n",
2915 timer_index);
2916 return NULL;
2917 }
2918
2919 /* allocate a hardware generic timer slot */
2920 timer_table->timers[timer_index] = timer;
2921 timer->index = timer_index;
2922 timer->trigger = trigger;
2923 timer->overflow = overflow;
2924 timer->arg = arg;
2925
2926 return timer;
2927 }
2928 EXPORT_SYMBOL(ath_gen_timer_alloc);
2929
2930 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2931 struct ath_gen_timer *timer,
2932 u32 trig_timeout,
2933 u32 timer_period)
2934 {
2935 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2936 u32 tsf, timer_next;
2937
2938 BUG_ON(!timer_period);
2939
2940 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2941
2942 tsf = ath9k_hw_gettsf32(ah);
2943
2944 timer_next = tsf + trig_timeout;
2945
2946 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2947 "current tsf %x period %x timer_next %x\n",
2948 tsf, timer_period, timer_next);
2949
2950 /*
2951 * Program generic timer registers
2952 */
2953 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2954 timer_next);
2955 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2956 timer_period);
2957 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2958 gen_tmr_configuration[timer->index].mode_mask);
2959
2960 if (AR_SREV_9462(ah)) {
2961 /*
2962 * Starting from AR9462, each generic timer can select which tsf
2963 * to use. But we still follow the old rule, 0 - 7 use tsf and
2964 * 8 - 15 use tsf2.
2965 */
2966 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2967 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2968 (1 << timer->index));
2969 else
2970 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2971 (1 << timer->index));
2972 }
2973
2974 /* Enable both trigger and thresh interrupt masks */
2975 REG_SET_BIT(ah, AR_IMR_S5,
2976 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2977 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2978 }
2979 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2980
2981 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2982 {
2983 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2984
2985 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2986 (timer->index >= ATH_MAX_GEN_TIMER)) {
2987 return;
2988 }
2989
2990 /* Clear generic timer enable bits. */
2991 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2992 gen_tmr_configuration[timer->index].mode_mask);
2993
2994 /* Disable both trigger and thresh interrupt masks */
2995 REG_CLR_BIT(ah, AR_IMR_S5,
2996 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2997 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2998
2999 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3000 }
3001 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3002
3003 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3004 {
3005 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3006
3007 /* free the hardware generic timer slot */
3008 timer_table->timers[timer->index] = NULL;
3009 kfree(timer);
3010 }
3011 EXPORT_SYMBOL(ath_gen_timer_free);
3012
3013 /*
3014 * Generic Timer Interrupts handling
3015 */
3016 void ath_gen_timer_isr(struct ath_hw *ah)
3017 {
3018 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3019 struct ath_gen_timer *timer;
3020 struct ath_common *common = ath9k_hw_common(ah);
3021 u32 trigger_mask, thresh_mask, index;
3022
3023 /* get hardware generic timer interrupt status */
3024 trigger_mask = ah->intr_gen_timer_trigger;
3025 thresh_mask = ah->intr_gen_timer_thresh;
3026 trigger_mask &= timer_table->timer_mask.val;
3027 thresh_mask &= timer_table->timer_mask.val;
3028
3029 trigger_mask &= ~thresh_mask;
3030
3031 while (thresh_mask) {
3032 index = rightmost_index(timer_table, &thresh_mask);
3033 timer = timer_table->timers[index];
3034 BUG_ON(!timer);
3035 ath_dbg(common, ATH_DBG_HWTIMER,
3036 "TSF overflow for Gen timer %d\n", index);
3037 timer->overflow(timer->arg);
3038 }
3039
3040 while (trigger_mask) {
3041 index = rightmost_index(timer_table, &trigger_mask);
3042 timer = timer_table->timers[index];
3043 BUG_ON(!timer);
3044 ath_dbg(common, ATH_DBG_HWTIMER,
3045 "Gen timer[%d] trigger\n", index);
3046 timer->trigger(timer->arg);
3047 }
3048 }
3049 EXPORT_SYMBOL(ath_gen_timer_isr);
3050
3051 /********/
3052 /* HTC */
3053 /********/
3054
3055 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3056 {
3057 ah->htc_reset_init = true;
3058 }
3059 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3060
3061 static struct {
3062 u32 version;
3063 const char * name;
3064 } ath_mac_bb_names[] = {
3065 /* Devices with external radios */
3066 { AR_SREV_VERSION_5416_PCI, "5416" },
3067 { AR_SREV_VERSION_5416_PCIE, "5418" },
3068 { AR_SREV_VERSION_9100, "9100" },
3069 { AR_SREV_VERSION_9160, "9160" },
3070 /* Single-chip solutions */
3071 { AR_SREV_VERSION_9280, "9280" },
3072 { AR_SREV_VERSION_9285, "9285" },
3073 { AR_SREV_VERSION_9287, "9287" },
3074 { AR_SREV_VERSION_9271, "9271" },
3075 { AR_SREV_VERSION_9300, "9300" },
3076 { AR_SREV_VERSION_9330, "9330" },
3077 { AR_SREV_VERSION_9340, "9340" },
3078 { AR_SREV_VERSION_9485, "9485" },
3079 { AR_SREV_VERSION_9462, "9462" },
3080 };
3081
3082 /* For devices with external radios */
3083 static struct {
3084 u16 version;
3085 const char * name;
3086 } ath_rf_names[] = {
3087 { 0, "5133" },
3088 { AR_RAD5133_SREV_MAJOR, "5133" },
3089 { AR_RAD5122_SREV_MAJOR, "5122" },
3090 { AR_RAD2133_SREV_MAJOR, "2133" },
3091 { AR_RAD2122_SREV_MAJOR, "2122" }
3092 };
3093
3094 /*
3095 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3096 */
3097 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3098 {
3099 int i;
3100
3101 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3102 if (ath_mac_bb_names[i].version == mac_bb_version) {
3103 return ath_mac_bb_names[i].name;
3104 }
3105 }
3106
3107 return "????";
3108 }
3109
3110 /*
3111 * Return the RF name. "????" is returned if the RF is unknown.
3112 * Used for devices with external radios.
3113 */
3114 static const char *ath9k_hw_rf_name(u16 rf_version)
3115 {
3116 int i;
3117
3118 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3119 if (ath_rf_names[i].version == rf_version) {
3120 return ath_rf_names[i].name;
3121 }
3122 }
3123
3124 return "????";
3125 }
3126
3127 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3128 {
3129 int used;
3130
3131 /* chipsets >= AR9280 are single-chip */
3132 if (AR_SREV_9280_20_OR_LATER(ah)) {
3133 used = snprintf(hw_name, len,
3134 "Atheros AR%s Rev:%x",
3135 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3136 ah->hw_version.macRev);
3137 }
3138 else {
3139 used = snprintf(hw_name, len,
3140 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3141 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3142 ah->hw_version.macRev,
3143 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3144 AR_RADIO_SREV_MAJOR)),
3145 ah->hw_version.phyRev);
3146 }
3147
3148 hw_name[used] = '\0';
3149 }
3150 EXPORT_SYMBOL(ath9k_hw_name);
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