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[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
21
22 #include "hw.h"
23 #include "hw-ops.h"
24 #include "rc.h"
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
27 #include "debug.h"
28 #include "ath9k.h"
29
30 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
31
32 MODULE_AUTHOR("Atheros Communications");
33 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
34 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
35 MODULE_LICENSE("Dual BSD/GPL");
36
37 static int __init ath9k_init(void)
38 {
39 return 0;
40 }
41 module_init(ath9k_init);
42
43 static void __exit ath9k_exit(void)
44 {
45 return;
46 }
47 module_exit(ath9k_exit);
48
49 /* Private hardware callbacks */
50
51 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
52 {
53 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
54 }
55
56 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
57 {
58 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
59 }
60
61 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
62 struct ath9k_channel *chan)
63 {
64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
65 }
66
67 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
68 {
69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
70 return;
71
72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
73 }
74
75 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
76 {
77 /* You will not have this callback if using the old ANI */
78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
79 return;
80
81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
82 }
83
84 /********************/
85 /* Helper Functions */
86 /********************/
87
88 #ifdef CONFIG_ATH9K_DEBUGFS
89
90 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
91 {
92 struct ath_softc *sc = common->priv;
93 if (sync_cause)
94 sc->debug.stats.istats.sync_cause_all++;
95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
96 sc->debug.stats.istats.sync_rtc_irq++;
97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
98 sc->debug.stats.istats.sync_mac_irq++;
99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
100 sc->debug.stats.istats.eeprom_illegal_access++;
101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
102 sc->debug.stats.istats.apb_timeout++;
103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
104 sc->debug.stats.istats.pci_mode_conflict++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
106 sc->debug.stats.istats.host1_fatal++;
107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
108 sc->debug.stats.istats.host1_perr++;
109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
110 sc->debug.stats.istats.trcv_fifo_perr++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
112 sc->debug.stats.istats.radm_cpl_ep++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_dllp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
116 sc->debug.stats.istats.radm_cpl_tlp_abort++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
118 sc->debug.stats.istats.radm_cpl_ecrc_err++;
119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
120 sc->debug.stats.istats.radm_cpl_timeout++;
121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
122 sc->debug.stats.istats.local_timeout++;
123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
124 sc->debug.stats.istats.pm_access++;
125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
126 sc->debug.stats.istats.mac_awake++;
127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
128 sc->debug.stats.istats.mac_asleep++;
129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
130 sc->debug.stats.istats.mac_sleep_access++;
131 }
132 #endif
133
134
135 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
136 {
137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
138 struct ath_common *common = ath9k_hw_common(ah);
139 unsigned int clockrate;
140
141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
143 clockrate = 117;
144 else if (!ah->curchan) /* should really check for CCK instead */
145 clockrate = ATH9K_CLOCK_RATE_CCK;
146 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
150 else
151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
152
153 if (conf_is_ht40(conf))
154 clockrate *= 2;
155
156 if (ah->curchan) {
157 if (IS_CHAN_HALF_RATE(ah->curchan))
158 clockrate /= 2;
159 if (IS_CHAN_QUARTER_RATE(ah->curchan))
160 clockrate /= 4;
161 }
162
163 common->clockrate = clockrate;
164 }
165
166 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
167 {
168 struct ath_common *common = ath9k_hw_common(ah);
169
170 return usecs * common->clockrate;
171 }
172
173 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
174 {
175 int i;
176
177 BUG_ON(timeout < AH_TIME_QUANTUM);
178
179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
180 if ((REG_READ(ah, reg) & mask) == val)
181 return true;
182
183 udelay(AH_TIME_QUANTUM);
184 }
185
186 ath_dbg(ath9k_hw_common(ah), ANY,
187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
188 timeout, reg, REG_READ(ah, reg), mask, val);
189
190 return false;
191 }
192 EXPORT_SYMBOL(ath9k_hw_wait);
193
194 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
195 int hw_delay)
196 {
197 if (IS_CHAN_B(chan))
198 hw_delay = (4 * hw_delay) / 22;
199 else
200 hw_delay /= 10;
201
202 if (IS_CHAN_HALF_RATE(chan))
203 hw_delay *= 2;
204 else if (IS_CHAN_QUARTER_RATE(chan))
205 hw_delay *= 4;
206
207 udelay(hw_delay + BASE_ACTIVATE_DELAY);
208 }
209
210 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
211 int column, unsigned int *writecnt)
212 {
213 int r;
214
215 ENABLE_REGWRITE_BUFFER(ah);
216 for (r = 0; r < array->ia_rows; r++) {
217 REG_WRITE(ah, INI_RA(array, r, 0),
218 INI_RA(array, r, column));
219 DO_DELAY(*writecnt);
220 }
221 REGWRITE_BUFFER_FLUSH(ah);
222 }
223
224 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
225 {
226 u32 retval;
227 int i;
228
229 for (i = 0, retval = 0; i < n; i++) {
230 retval = (retval << 1) | (val & 1);
231 val >>= 1;
232 }
233 return retval;
234 }
235
236 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
237 u8 phy, int kbps,
238 u32 frameLen, u16 rateix,
239 bool shortPreamble)
240 {
241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
242
243 if (kbps == 0)
244 return 0;
245
246 switch (phy) {
247 case WLAN_RC_PHY_CCK:
248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
249 if (shortPreamble)
250 phyTime >>= 1;
251 numBits = frameLen << 3;
252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
253 break;
254 case WLAN_RC_PHY_OFDM:
255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
257 numBits = OFDM_PLCP_BITS + (frameLen << 3);
258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
259 txTime = OFDM_SIFS_TIME_QUARTER
260 + OFDM_PREAMBLE_TIME_QUARTER
261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
262 } else if (ah->curchan &&
263 IS_CHAN_HALF_RATE(ah->curchan)) {
264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
265 numBits = OFDM_PLCP_BITS + (frameLen << 3);
266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
267 txTime = OFDM_SIFS_TIME_HALF +
268 OFDM_PREAMBLE_TIME_HALF
269 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
270 } else {
271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
272 numBits = OFDM_PLCP_BITS + (frameLen << 3);
273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
275 + (numSymbols * OFDM_SYMBOL_TIME);
276 }
277 break;
278 default:
279 ath_err(ath9k_hw_common(ah),
280 "Unknown phy %u (rate ix %u)\n", phy, rateix);
281 txTime = 0;
282 break;
283 }
284
285 return txTime;
286 }
287 EXPORT_SYMBOL(ath9k_hw_computetxtime);
288
289 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
290 struct ath9k_channel *chan,
291 struct chan_centers *centers)
292 {
293 int8_t extoff;
294
295 if (!IS_CHAN_HT40(chan)) {
296 centers->ctl_center = centers->ext_center =
297 centers->synth_center = chan->channel;
298 return;
299 }
300
301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
302 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
303 centers->synth_center =
304 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
305 extoff = 1;
306 } else {
307 centers->synth_center =
308 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
309 extoff = -1;
310 }
311
312 centers->ctl_center =
313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
314 /* 25 MHz spacing is supported by hw but not on upper layers */
315 centers->ext_center =
316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
317 }
318
319 /******************/
320 /* Chip Revisions */
321 /******************/
322
323 static void ath9k_hw_read_revisions(struct ath_hw *ah)
324 {
325 u32 val;
326
327 switch (ah->hw_version.devid) {
328 case AR5416_AR9100_DEVID:
329 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
330 break;
331 case AR9300_DEVID_AR9330:
332 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
333 if (ah->get_mac_revision) {
334 ah->hw_version.macRev = ah->get_mac_revision();
335 } else {
336 val = REG_READ(ah, AR_SREV);
337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
338 }
339 return;
340 case AR9300_DEVID_AR9340:
341 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
342 val = REG_READ(ah, AR_SREV);
343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
344 return;
345 case AR9300_DEVID_QCA955X:
346 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
347 return;
348 }
349
350 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
351
352 if (val == 0xFF) {
353 val = REG_READ(ah, AR_SREV);
354 ah->hw_version.macVersion =
355 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
356 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
357
358 if (AR_SREV_9462(ah))
359 ah->is_pciexpress = true;
360 else
361 ah->is_pciexpress = (val &
362 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
363 } else {
364 if (!AR_SREV_9100(ah))
365 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
366
367 ah->hw_version.macRev = val & AR_SREV_REVISION;
368
369 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
370 ah->is_pciexpress = true;
371 }
372 }
373
374 /************************************/
375 /* HW Attach, Detach, Init Routines */
376 /************************************/
377
378 static void ath9k_hw_disablepcie(struct ath_hw *ah)
379 {
380 if (!AR_SREV_5416(ah))
381 return;
382
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
388 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
389 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
390 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
391 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
392
393 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
394 }
395
396 /* This should work for all families including legacy */
397 static bool ath9k_hw_chip_test(struct ath_hw *ah)
398 {
399 struct ath_common *common = ath9k_hw_common(ah);
400 u32 regAddr[2] = { AR_STA_ID0 };
401 u32 regHold[2];
402 static const u32 patternData[4] = {
403 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
404 };
405 int i, j, loop_max;
406
407 if (!AR_SREV_9300_20_OR_LATER(ah)) {
408 loop_max = 2;
409 regAddr[1] = AR_PHY_BASE + (8 << 2);
410 } else
411 loop_max = 1;
412
413 for (i = 0; i < loop_max; i++) {
414 u32 addr = regAddr[i];
415 u32 wrData, rdData;
416
417 regHold[i] = REG_READ(ah, addr);
418 for (j = 0; j < 0x100; j++) {
419 wrData = (j << 16) | j;
420 REG_WRITE(ah, addr, wrData);
421 rdData = REG_READ(ah, addr);
422 if (rdData != wrData) {
423 ath_err(common,
424 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
425 addr, wrData, rdData);
426 return false;
427 }
428 }
429 for (j = 0; j < 4; j++) {
430 wrData = patternData[j];
431 REG_WRITE(ah, addr, wrData);
432 rdData = REG_READ(ah, addr);
433 if (wrData != rdData) {
434 ath_err(common,
435 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
436 addr, wrData, rdData);
437 return false;
438 }
439 }
440 REG_WRITE(ah, regAddr[i], regHold[i]);
441 }
442 udelay(100);
443
444 return true;
445 }
446
447 static void ath9k_hw_init_config(struct ath_hw *ah)
448 {
449 int i;
450
451 ah->config.dma_beacon_response_time = 1;
452 ah->config.sw_beacon_response_time = 6;
453 ah->config.additional_swba_backoff = 0;
454 ah->config.ack_6mb = 0x0;
455 ah->config.cwm_ignore_extcca = 0;
456 ah->config.pcie_clock_req = 0;
457 ah->config.pcie_waen = 0;
458 ah->config.analog_shiftreg = 1;
459 ah->config.enable_ani = true;
460
461 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
462 ah->config.spurchans[i][0] = AR_NO_SPUR;
463 ah->config.spurchans[i][1] = AR_NO_SPUR;
464 }
465
466 /* PAPRD needs some more work to be enabled */
467 ah->config.paprd_disable = 1;
468
469 ah->config.rx_intr_mitigation = true;
470 ah->config.pcieSerDesWrite = true;
471
472 /*
473 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
474 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
475 * This means we use it for all AR5416 devices, and the few
476 * minor PCI AR9280 devices out there.
477 *
478 * Serialization is required because these devices do not handle
479 * well the case of two concurrent reads/writes due to the latency
480 * involved. During one read/write another read/write can be issued
481 * on another CPU while the previous read/write may still be working
482 * on our hardware, if we hit this case the hardware poops in a loop.
483 * We prevent this by serializing reads and writes.
484 *
485 * This issue is not present on PCI-Express devices or pre-AR5416
486 * devices (legacy, 802.11abg).
487 */
488 if (num_possible_cpus() > 1)
489 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
490 }
491
492 static void ath9k_hw_init_defaults(struct ath_hw *ah)
493 {
494 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
495
496 regulatory->country_code = CTRY_DEFAULT;
497 regulatory->power_limit = MAX_RATE_POWER;
498
499 ah->hw_version.magic = AR5416_MAGIC;
500 ah->hw_version.subvendorid = 0;
501
502 ah->atim_window = 0;
503 ah->sta_id1_defaults =
504 AR_STA_ID1_CRPT_MIC_ENABLE |
505 AR_STA_ID1_MCAST_KSRCH;
506 if (AR_SREV_9100(ah))
507 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
508 ah->slottime = ATH9K_SLOT_TIME_9;
509 ah->globaltxtimeout = (u32) -1;
510 ah->power_mode = ATH9K_PM_UNDEFINED;
511 ah->htc_reset_init = true;
512 }
513
514 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
515 {
516 struct ath_common *common = ath9k_hw_common(ah);
517 u32 sum;
518 int i;
519 u16 eeval;
520 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
521
522 sum = 0;
523 for (i = 0; i < 3; i++) {
524 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
525 sum += eeval;
526 common->macaddr[2 * i] = eeval >> 8;
527 common->macaddr[2 * i + 1] = eeval & 0xff;
528 }
529 if (sum == 0 || sum == 0xffff * 3)
530 return -EADDRNOTAVAIL;
531
532 return 0;
533 }
534
535 static int ath9k_hw_post_init(struct ath_hw *ah)
536 {
537 struct ath_common *common = ath9k_hw_common(ah);
538 int ecode;
539
540 if (common->bus_ops->ath_bus_type != ATH_USB) {
541 if (!ath9k_hw_chip_test(ah))
542 return -ENODEV;
543 }
544
545 if (!AR_SREV_9300_20_OR_LATER(ah)) {
546 ecode = ar9002_hw_rf_claim(ah);
547 if (ecode != 0)
548 return ecode;
549 }
550
551 ecode = ath9k_hw_eeprom_init(ah);
552 if (ecode != 0)
553 return ecode;
554
555 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
556 ah->eep_ops->get_eeprom_ver(ah),
557 ah->eep_ops->get_eeprom_rev(ah));
558
559 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
560 if (ecode) {
561 ath_err(ath9k_hw_common(ah),
562 "Failed allocating banks for external radio\n");
563 ath9k_hw_rf_free_ext_banks(ah);
564 return ecode;
565 }
566
567 if (ah->config.enable_ani) {
568 ath9k_hw_ani_setup(ah);
569 ath9k_hw_ani_init(ah);
570 }
571
572 return 0;
573 }
574
575 static void ath9k_hw_attach_ops(struct ath_hw *ah)
576 {
577 if (AR_SREV_9300_20_OR_LATER(ah))
578 ar9003_hw_attach_ops(ah);
579 else
580 ar9002_hw_attach_ops(ah);
581 }
582
583 /* Called for all hardware families */
584 static int __ath9k_hw_init(struct ath_hw *ah)
585 {
586 struct ath_common *common = ath9k_hw_common(ah);
587 int r = 0;
588
589 ath9k_hw_read_revisions(ah);
590
591 /*
592 * Read back AR_WA into a permanent copy and set bits 14 and 17.
593 * We need to do this to avoid RMW of this register. We cannot
594 * read the reg when chip is asleep.
595 */
596 ah->WARegVal = REG_READ(ah, AR_WA);
597 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
598 AR_WA_ASPM_TIMER_BASED_DISABLE);
599
600 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
601 ath_err(common, "Couldn't reset chip\n");
602 return -EIO;
603 }
604
605 if (AR_SREV_9462(ah))
606 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
607
608 ath9k_hw_init_defaults(ah);
609 ath9k_hw_init_config(ah);
610
611 ath9k_hw_attach_ops(ah);
612
613 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
614 ath_err(common, "Couldn't wakeup chip\n");
615 return -EIO;
616 }
617
618 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
619 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
620 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
621 !ah->is_pciexpress)) {
622 ah->config.serialize_regmode =
623 SER_REG_MODE_ON;
624 } else {
625 ah->config.serialize_regmode =
626 SER_REG_MODE_OFF;
627 }
628 }
629
630 ath_dbg(common, RESET, "serialize_regmode is %d\n",
631 ah->config.serialize_regmode);
632
633 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
634 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
635 else
636 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
637
638 switch (ah->hw_version.macVersion) {
639 case AR_SREV_VERSION_5416_PCI:
640 case AR_SREV_VERSION_5416_PCIE:
641 case AR_SREV_VERSION_9160:
642 case AR_SREV_VERSION_9100:
643 case AR_SREV_VERSION_9280:
644 case AR_SREV_VERSION_9285:
645 case AR_SREV_VERSION_9287:
646 case AR_SREV_VERSION_9271:
647 case AR_SREV_VERSION_9300:
648 case AR_SREV_VERSION_9330:
649 case AR_SREV_VERSION_9485:
650 case AR_SREV_VERSION_9340:
651 case AR_SREV_VERSION_9462:
652 case AR_SREV_VERSION_9550:
653 break;
654 default:
655 ath_err(common,
656 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
657 ah->hw_version.macVersion, ah->hw_version.macRev);
658 return -EOPNOTSUPP;
659 }
660
661 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
662 AR_SREV_9330(ah) || AR_SREV_9550(ah))
663 ah->is_pciexpress = false;
664
665 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
666 ath9k_hw_init_cal_settings(ah);
667
668 ah->ani_function = ATH9K_ANI_ALL;
669 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
671 if (!AR_SREV_9300_20_OR_LATER(ah))
672 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
673
674 /* disable ANI for 9340 */
675 if (AR_SREV_9340(ah))
676 ah->config.enable_ani = false;
677
678 ath9k_hw_init_mode_regs(ah);
679
680 if (!ah->is_pciexpress)
681 ath9k_hw_disablepcie(ah);
682
683 r = ath9k_hw_post_init(ah);
684 if (r)
685 return r;
686
687 ath9k_hw_init_mode_gain_regs(ah);
688 r = ath9k_hw_fill_cap_info(ah);
689 if (r)
690 return r;
691
692 r = ath9k_hw_init_macaddr(ah);
693 if (r) {
694 ath_err(common, "Failed to initialize MAC address\n");
695 return r;
696 }
697
698 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
699 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
700 else
701 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
702
703 if (AR_SREV_9330(ah))
704 ah->bb_watchdog_timeout_ms = 85;
705 else
706 ah->bb_watchdog_timeout_ms = 25;
707
708 common->state = ATH_HW_INITIALIZED;
709
710 return 0;
711 }
712
713 int ath9k_hw_init(struct ath_hw *ah)
714 {
715 int ret;
716 struct ath_common *common = ath9k_hw_common(ah);
717
718 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
719 switch (ah->hw_version.devid) {
720 case AR5416_DEVID_PCI:
721 case AR5416_DEVID_PCIE:
722 case AR5416_AR9100_DEVID:
723 case AR9160_DEVID_PCI:
724 case AR9280_DEVID_PCI:
725 case AR9280_DEVID_PCIE:
726 case AR9285_DEVID_PCIE:
727 case AR9287_DEVID_PCI:
728 case AR9287_DEVID_PCIE:
729 case AR2427_DEVID_PCIE:
730 case AR9300_DEVID_PCIE:
731 case AR9300_DEVID_AR9485_PCIE:
732 case AR9300_DEVID_AR9330:
733 case AR9300_DEVID_AR9340:
734 case AR9300_DEVID_QCA955X:
735 case AR9300_DEVID_AR9580:
736 case AR9300_DEVID_AR9462:
737 break;
738 default:
739 if (common->bus_ops->ath_bus_type == ATH_USB)
740 break;
741 ath_err(common, "Hardware device ID 0x%04x not supported\n",
742 ah->hw_version.devid);
743 return -EOPNOTSUPP;
744 }
745
746 ret = __ath9k_hw_init(ah);
747 if (ret) {
748 ath_err(common,
749 "Unable to initialize hardware; initialization status: %d\n",
750 ret);
751 return ret;
752 }
753
754 return 0;
755 }
756 EXPORT_SYMBOL(ath9k_hw_init);
757
758 static void ath9k_hw_init_qos(struct ath_hw *ah)
759 {
760 ENABLE_REGWRITE_BUFFER(ah);
761
762 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
763 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
764
765 REG_WRITE(ah, AR_QOS_NO_ACK,
766 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
767 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
768 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
769
770 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
771 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
772 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
773 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
774 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
775
776 REGWRITE_BUFFER_FLUSH(ah);
777 }
778
779 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
780 {
781 struct ath_common *common = ath9k_hw_common(ah);
782 int i = 0;
783
784 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
785 udelay(100);
786 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
787
788 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
789
790 udelay(100);
791
792 if (WARN_ON_ONCE(i >= 100)) {
793 ath_err(common, "PLL4 meaurement not done\n");
794 break;
795 }
796
797 i++;
798 }
799
800 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
801 }
802 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
803
804 static void ath9k_hw_init_pll(struct ath_hw *ah,
805 struct ath9k_channel *chan)
806 {
807 u32 pll;
808
809 if (AR_SREV_9485(ah)) {
810
811 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
813 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
815 AR_CH0_DPLL2_KD, 0x40);
816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
817 AR_CH0_DPLL2_KI, 0x4);
818
819 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
820 AR_CH0_BB_DPLL1_REFDIV, 0x5);
821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
822 AR_CH0_BB_DPLL1_NINI, 0x58);
823 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
824 AR_CH0_BB_DPLL1_NFRAC, 0x0);
825
826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
827 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
828 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
829 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
830 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
831 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
832
833 /* program BB PLL phase_shift to 0x6 */
834 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
835 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
836
837 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
838 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
839 udelay(1000);
840 } else if (AR_SREV_9330(ah)) {
841 u32 ddr_dpll2, pll_control2, kd;
842
843 if (ah->is_clk_25mhz) {
844 ddr_dpll2 = 0x18e82f01;
845 pll_control2 = 0xe04a3d;
846 kd = 0x1d;
847 } else {
848 ddr_dpll2 = 0x19e82f01;
849 pll_control2 = 0x886666;
850 kd = 0x3d;
851 }
852
853 /* program DDR PLL ki and kd value */
854 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
855
856 /* program DDR PLL phase_shift */
857 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
858 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
859
860 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
861 udelay(1000);
862
863 /* program refdiv, nint, frac to RTC register */
864 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
865
866 /* program BB PLL kd and ki value */
867 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
868 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
869
870 /* program BB PLL phase_shift */
871 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
872 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
873 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
874 u32 regval, pll2_divint, pll2_divfrac, refdiv;
875
876 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
877 udelay(1000);
878
879 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
880 udelay(100);
881
882 if (ah->is_clk_25mhz) {
883 pll2_divint = 0x54;
884 pll2_divfrac = 0x1eb85;
885 refdiv = 3;
886 } else {
887 if (AR_SREV_9340(ah)) {
888 pll2_divint = 88;
889 pll2_divfrac = 0;
890 refdiv = 5;
891 } else {
892 pll2_divint = 0x11;
893 pll2_divfrac = 0x26666;
894 refdiv = 1;
895 }
896 }
897
898 regval = REG_READ(ah, AR_PHY_PLL_MODE);
899 regval |= (0x1 << 16);
900 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
901 udelay(100);
902
903 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
904 (pll2_divint << 18) | pll2_divfrac);
905 udelay(100);
906
907 regval = REG_READ(ah, AR_PHY_PLL_MODE);
908 if (AR_SREV_9340(ah))
909 regval = (regval & 0x80071fff) | (0x1 << 30) |
910 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
911 else
912 regval = (regval & 0x80071fff) | (0x3 << 30) |
913 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
914 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
915 REG_WRITE(ah, AR_PHY_PLL_MODE,
916 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
917 udelay(1000);
918 }
919
920 pll = ath9k_hw_compute_pll_control(ah, chan);
921
922 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
923
924 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
925 AR_SREV_9550(ah))
926 udelay(1000);
927
928 /* Switch the core clock for ar9271 to 117Mhz */
929 if (AR_SREV_9271(ah)) {
930 udelay(500);
931 REG_WRITE(ah, 0x50040, 0x304);
932 }
933
934 udelay(RTC_PLL_SETTLE_DELAY);
935
936 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
937
938 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
939 if (ah->is_clk_25mhz) {
940 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
941 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
942 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
943 } else {
944 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
945 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
946 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
947 }
948 udelay(100);
949 }
950 }
951
952 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
953 enum nl80211_iftype opmode)
954 {
955 u32 sync_default = AR_INTR_SYNC_DEFAULT;
956 u32 imr_reg = AR_IMR_TXERR |
957 AR_IMR_TXURN |
958 AR_IMR_RXERR |
959 AR_IMR_RXORN |
960 AR_IMR_BCNMISC;
961
962 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
963 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
964
965 if (AR_SREV_9300_20_OR_LATER(ah)) {
966 imr_reg |= AR_IMR_RXOK_HP;
967 if (ah->config.rx_intr_mitigation)
968 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
969 else
970 imr_reg |= AR_IMR_RXOK_LP;
971
972 } else {
973 if (ah->config.rx_intr_mitigation)
974 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
975 else
976 imr_reg |= AR_IMR_RXOK;
977 }
978
979 if (ah->config.tx_intr_mitigation)
980 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
981 else
982 imr_reg |= AR_IMR_TXOK;
983
984 if (opmode == NL80211_IFTYPE_AP)
985 imr_reg |= AR_IMR_MIB;
986
987 ENABLE_REGWRITE_BUFFER(ah);
988
989 REG_WRITE(ah, AR_IMR, imr_reg);
990 ah->imrs2_reg |= AR_IMR_S2_GTT;
991 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
992
993 if (!AR_SREV_9100(ah)) {
994 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
995 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
996 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
997 }
998
999 REGWRITE_BUFFER_FLUSH(ah);
1000
1001 if (AR_SREV_9300_20_OR_LATER(ah)) {
1002 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
1003 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
1004 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
1005 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
1006 }
1007 }
1008
1009 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
1010 {
1011 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
1012 val = min(val, (u32) 0xFFFF);
1013 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1014 }
1015
1016 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1017 {
1018 u32 val = ath9k_hw_mac_to_clks(ah, us);
1019 val = min(val, (u32) 0xFFFF);
1020 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1021 }
1022
1023 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1024 {
1025 u32 val = ath9k_hw_mac_to_clks(ah, us);
1026 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1027 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1028 }
1029
1030 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1031 {
1032 u32 val = ath9k_hw_mac_to_clks(ah, us);
1033 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1034 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1035 }
1036
1037 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1038 {
1039 if (tu > 0xFFFF) {
1040 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1041 tu);
1042 ah->globaltxtimeout = (u32) -1;
1043 return false;
1044 } else {
1045 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1046 ah->globaltxtimeout = tu;
1047 return true;
1048 }
1049 }
1050
1051 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1052 {
1053 struct ath_common *common = ath9k_hw_common(ah);
1054 struct ieee80211_conf *conf = &common->hw->conf;
1055 const struct ath9k_channel *chan = ah->curchan;
1056 int acktimeout, ctstimeout, ack_offset = 0;
1057 int slottime;
1058 int sifstime;
1059 int rx_lat = 0, tx_lat = 0, eifs = 0;
1060 u32 reg;
1061
1062 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1063 ah->misc_mode);
1064
1065 if (!chan)
1066 return;
1067
1068 if (ah->misc_mode != 0)
1069 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1070
1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1072 rx_lat = 41;
1073 else
1074 rx_lat = 37;
1075 tx_lat = 54;
1076
1077 if (IS_CHAN_5GHZ(chan))
1078 sifstime = 16;
1079 else
1080 sifstime = 10;
1081
1082 if (IS_CHAN_HALF_RATE(chan)) {
1083 eifs = 175;
1084 rx_lat *= 2;
1085 tx_lat *= 2;
1086 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1087 tx_lat += 11;
1088
1089 sifstime *= 2;
1090 ack_offset = 16;
1091 slottime = 13;
1092 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1093 eifs = 340;
1094 rx_lat = (rx_lat * 4) - 1;
1095 tx_lat *= 4;
1096 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1097 tx_lat += 22;
1098
1099 sifstime *= 4;
1100 ack_offset = 32;
1101 slottime = 21;
1102 } else {
1103 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1104 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1105 reg = AR_USEC_ASYNC_FIFO;
1106 } else {
1107 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1108 common->clockrate;
1109 reg = REG_READ(ah, AR_USEC);
1110 }
1111 rx_lat = MS(reg, AR_USEC_RX_LAT);
1112 tx_lat = MS(reg, AR_USEC_TX_LAT);
1113
1114 slottime = ah->slottime;
1115 }
1116
1117 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1118 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
1119 ctstimeout = acktimeout;
1120
1121 /*
1122 * Workaround for early ACK timeouts, add an offset to match the
1123 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1124 * This was initially only meant to work around an issue with delayed
1125 * BA frames in some implementations, but it has been found to fix ACK
1126 * timeout issues in other cases as well.
1127 */
1128 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
1129 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1130 acktimeout += 64 - sifstime - ah->slottime;
1131 ctstimeout += 48 - sifstime - ah->slottime;
1132 }
1133
1134
1135 ath9k_hw_set_sifs_time(ah, sifstime);
1136 ath9k_hw_setslottime(ah, slottime);
1137 ath9k_hw_set_ack_timeout(ah, acktimeout);
1138 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1139 if (ah->globaltxtimeout != (u32) -1)
1140 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1141
1142 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1143 REG_RMW(ah, AR_USEC,
1144 (common->clockrate - 1) |
1145 SM(rx_lat, AR_USEC_RX_LAT) |
1146 SM(tx_lat, AR_USEC_TX_LAT),
1147 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1148
1149 }
1150 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1151
1152 void ath9k_hw_deinit(struct ath_hw *ah)
1153 {
1154 struct ath_common *common = ath9k_hw_common(ah);
1155
1156 if (common->state < ATH_HW_INITIALIZED)
1157 goto free_hw;
1158
1159 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1160
1161 free_hw:
1162 ath9k_hw_rf_free_ext_banks(ah);
1163 }
1164 EXPORT_SYMBOL(ath9k_hw_deinit);
1165
1166 /*******/
1167 /* INI */
1168 /*******/
1169
1170 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1171 {
1172 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1173
1174 if (IS_CHAN_B(chan))
1175 ctl |= CTL_11B;
1176 else if (IS_CHAN_G(chan))
1177 ctl |= CTL_11G;
1178 else
1179 ctl |= CTL_11A;
1180
1181 return ctl;
1182 }
1183
1184 /****************************************/
1185 /* Reset and Channel Switching Routines */
1186 /****************************************/
1187
1188 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1189 {
1190 struct ath_common *common = ath9k_hw_common(ah);
1191
1192 ENABLE_REGWRITE_BUFFER(ah);
1193
1194 /*
1195 * set AHB_MODE not to do cacheline prefetches
1196 */
1197 if (!AR_SREV_9300_20_OR_LATER(ah))
1198 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1199
1200 /*
1201 * let mac dma reads be in 128 byte chunks
1202 */
1203 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1204
1205 REGWRITE_BUFFER_FLUSH(ah);
1206
1207 /*
1208 * Restore TX Trigger Level to its pre-reset value.
1209 * The initial value depends on whether aggregation is enabled, and is
1210 * adjusted whenever underruns are detected.
1211 */
1212 if (!AR_SREV_9300_20_OR_LATER(ah))
1213 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1214
1215 ENABLE_REGWRITE_BUFFER(ah);
1216
1217 /*
1218 * let mac dma writes be in 128 byte chunks
1219 */
1220 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1221
1222 /*
1223 * Setup receive FIFO threshold to hold off TX activities
1224 */
1225 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1226
1227 if (AR_SREV_9300_20_OR_LATER(ah)) {
1228 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1229 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1230
1231 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1232 ah->caps.rx_status_len);
1233 }
1234
1235 /*
1236 * reduce the number of usable entries in PCU TXBUF to avoid
1237 * wrap around issues.
1238 */
1239 if (AR_SREV_9285(ah)) {
1240 /* For AR9285 the number of Fifos are reduced to half.
1241 * So set the usable tx buf size also to half to
1242 * avoid data/delimiter underruns
1243 */
1244 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1245 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1246 } else if (!AR_SREV_9271(ah)) {
1247 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1248 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1249 }
1250
1251 REGWRITE_BUFFER_FLUSH(ah);
1252
1253 if (AR_SREV_9300_20_OR_LATER(ah))
1254 ath9k_hw_reset_txstatus_ring(ah);
1255 }
1256
1257 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1258 {
1259 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1260 u32 set = AR_STA_ID1_KSRCH_MODE;
1261
1262 switch (opmode) {
1263 case NL80211_IFTYPE_ADHOC:
1264 case NL80211_IFTYPE_MESH_POINT:
1265 set |= AR_STA_ID1_ADHOC;
1266 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1267 break;
1268 case NL80211_IFTYPE_AP:
1269 set |= AR_STA_ID1_STA_AP;
1270 /* fall through */
1271 case NL80211_IFTYPE_STATION:
1272 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1273 break;
1274 default:
1275 if (!ah->is_monitoring)
1276 set = 0;
1277 break;
1278 }
1279 REG_RMW(ah, AR_STA_ID1, set, mask);
1280 }
1281
1282 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1283 u32 *coef_mantissa, u32 *coef_exponent)
1284 {
1285 u32 coef_exp, coef_man;
1286
1287 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1288 if ((coef_scaled >> coef_exp) & 0x1)
1289 break;
1290
1291 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1292
1293 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1294
1295 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1296 *coef_exponent = coef_exp - 16;
1297 }
1298
1299 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1300 {
1301 u32 rst_flags;
1302 u32 tmpReg;
1303
1304 if (AR_SREV_9100(ah)) {
1305 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1306 AR_RTC_DERIVED_CLK_PERIOD, 1);
1307 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1308 }
1309
1310 ENABLE_REGWRITE_BUFFER(ah);
1311
1312 if (AR_SREV_9300_20_OR_LATER(ah)) {
1313 REG_WRITE(ah, AR_WA, ah->WARegVal);
1314 udelay(10);
1315 }
1316
1317 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1318 AR_RTC_FORCE_WAKE_ON_INT);
1319
1320 if (AR_SREV_9100(ah)) {
1321 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1322 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1323 } else {
1324 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1325 if (tmpReg &
1326 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1327 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1328 u32 val;
1329 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1330
1331 val = AR_RC_HOSTIF;
1332 if (!AR_SREV_9300_20_OR_LATER(ah))
1333 val |= AR_RC_AHB;
1334 REG_WRITE(ah, AR_RC, val);
1335
1336 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1337 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1338
1339 rst_flags = AR_RTC_RC_MAC_WARM;
1340 if (type == ATH9K_RESET_COLD)
1341 rst_flags |= AR_RTC_RC_MAC_COLD;
1342 }
1343
1344 if (AR_SREV_9330(ah)) {
1345 int npend = 0;
1346 int i;
1347
1348 /* AR9330 WAR:
1349 * call external reset function to reset WMAC if:
1350 * - doing a cold reset
1351 * - we have pending frames in the TX queues
1352 */
1353
1354 for (i = 0; i < AR_NUM_QCU; i++) {
1355 npend = ath9k_hw_numtxpending(ah, i);
1356 if (npend)
1357 break;
1358 }
1359
1360 if (ah->external_reset &&
1361 (npend || type == ATH9K_RESET_COLD)) {
1362 int reset_err = 0;
1363
1364 ath_dbg(ath9k_hw_common(ah), RESET,
1365 "reset MAC via external reset\n");
1366
1367 reset_err = ah->external_reset();
1368 if (reset_err) {
1369 ath_err(ath9k_hw_common(ah),
1370 "External reset failed, err=%d\n",
1371 reset_err);
1372 return false;
1373 }
1374
1375 REG_WRITE(ah, AR_RTC_RESET, 1);
1376 }
1377 }
1378
1379 if (ath9k_hw_mci_is_enabled(ah))
1380 ar9003_mci_check_gpm_offset(ah);
1381
1382 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1383
1384 REGWRITE_BUFFER_FLUSH(ah);
1385
1386 udelay(50);
1387
1388 REG_WRITE(ah, AR_RTC_RC, 0);
1389 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1390 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1391 return false;
1392 }
1393
1394 if (!AR_SREV_9100(ah))
1395 REG_WRITE(ah, AR_RC, 0);
1396
1397 if (AR_SREV_9100(ah))
1398 udelay(50);
1399
1400 return true;
1401 }
1402
1403 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1404 {
1405 ENABLE_REGWRITE_BUFFER(ah);
1406
1407 if (AR_SREV_9300_20_OR_LATER(ah)) {
1408 REG_WRITE(ah, AR_WA, ah->WARegVal);
1409 udelay(10);
1410 }
1411
1412 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1413 AR_RTC_FORCE_WAKE_ON_INT);
1414
1415 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1416 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1417
1418 REG_WRITE(ah, AR_RTC_RESET, 0);
1419
1420 REGWRITE_BUFFER_FLUSH(ah);
1421
1422 if (!AR_SREV_9300_20_OR_LATER(ah))
1423 udelay(2);
1424
1425 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1426 REG_WRITE(ah, AR_RC, 0);
1427
1428 REG_WRITE(ah, AR_RTC_RESET, 1);
1429
1430 if (!ath9k_hw_wait(ah,
1431 AR_RTC_STATUS,
1432 AR_RTC_STATUS_M,
1433 AR_RTC_STATUS_ON,
1434 AH_WAIT_TIMEOUT)) {
1435 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1436 return false;
1437 }
1438
1439 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1440 }
1441
1442 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1443 {
1444 bool ret = false;
1445
1446 if (AR_SREV_9300_20_OR_LATER(ah)) {
1447 REG_WRITE(ah, AR_WA, ah->WARegVal);
1448 udelay(10);
1449 }
1450
1451 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1452 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1453
1454 switch (type) {
1455 case ATH9K_RESET_POWER_ON:
1456 ret = ath9k_hw_set_reset_power_on(ah);
1457 break;
1458 case ATH9K_RESET_WARM:
1459 case ATH9K_RESET_COLD:
1460 ret = ath9k_hw_set_reset(ah, type);
1461 break;
1462 default:
1463 break;
1464 }
1465
1466 return ret;
1467 }
1468
1469 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1470 struct ath9k_channel *chan)
1471 {
1472 int reset_type = ATH9K_RESET_WARM;
1473
1474 if (AR_SREV_9280(ah)) {
1475 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1476 reset_type = ATH9K_RESET_POWER_ON;
1477 else
1478 reset_type = ATH9K_RESET_COLD;
1479 }
1480
1481 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1482 return false;
1483
1484 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1485 return false;
1486
1487 ah->chip_fullsleep = false;
1488
1489 if (AR_SREV_9330(ah))
1490 ar9003_hw_internal_regulator_apply(ah);
1491 ath9k_hw_init_pll(ah, chan);
1492 ath9k_hw_set_rfmode(ah, chan);
1493
1494 return true;
1495 }
1496
1497 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1498 struct ath9k_channel *chan)
1499 {
1500 struct ath_common *common = ath9k_hw_common(ah);
1501 u32 qnum;
1502 int r;
1503 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1504 bool band_switch, mode_diff;
1505 u8 ini_reloaded;
1506
1507 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1508 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1509 CHANNEL_5GHZ));
1510 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1511
1512 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1513 if (ath9k_hw_numtxpending(ah, qnum)) {
1514 ath_dbg(common, QUEUE,
1515 "Transmit frames pending on queue %d\n", qnum);
1516 return false;
1517 }
1518 }
1519
1520 if (!ath9k_hw_rfbus_req(ah)) {
1521 ath_err(common, "Could not kill baseband RX\n");
1522 return false;
1523 }
1524
1525 if (edma && (band_switch || mode_diff)) {
1526 ath9k_hw_mark_phy_inactive(ah);
1527 udelay(5);
1528
1529 ath9k_hw_init_pll(ah, NULL);
1530
1531 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1532 ath_err(common, "Failed to do fast channel change\n");
1533 return false;
1534 }
1535 }
1536
1537 ath9k_hw_set_channel_regs(ah, chan);
1538
1539 r = ath9k_hw_rf_set_freq(ah, chan);
1540 if (r) {
1541 ath_err(common, "Failed to set channel\n");
1542 return false;
1543 }
1544 ath9k_hw_set_clockrate(ah);
1545 ath9k_hw_apply_txpower(ah, chan, false);
1546 ath9k_hw_rfbus_done(ah);
1547
1548 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1549 ath9k_hw_set_delta_slope(ah, chan);
1550
1551 ath9k_hw_spur_mitigate_freq(ah, chan);
1552
1553 if (edma && (band_switch || mode_diff)) {
1554 ah->ah_flags |= AH_FASTCC;
1555 if (band_switch || ini_reloaded)
1556 ah->eep_ops->set_board_values(ah, chan);
1557
1558 ath9k_hw_init_bb(ah, chan);
1559
1560 if (band_switch || ini_reloaded)
1561 ath9k_hw_init_cal(ah, chan);
1562 ah->ah_flags &= ~AH_FASTCC;
1563 }
1564
1565 return true;
1566 }
1567
1568 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1569 {
1570 u32 gpio_mask = ah->gpio_mask;
1571 int i;
1572
1573 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1574 if (!(gpio_mask & 1))
1575 continue;
1576
1577 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1578 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1579 }
1580 }
1581
1582 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1583 int *hang_state, int *hang_pos)
1584 {
1585 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1586 u32 chain_state, dcs_pos, i;
1587
1588 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1589 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1590 for (i = 0; i < 3; i++) {
1591 if (chain_state == dcu_chain_state[i]) {
1592 *hang_state = chain_state;
1593 *hang_pos = dcs_pos;
1594 return true;
1595 }
1596 }
1597 }
1598 return false;
1599 }
1600
1601 #define DCU_COMPLETE_STATE 1
1602 #define DCU_COMPLETE_STATE_MASK 0x3
1603 #define NUM_STATUS_READS 50
1604 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1605 {
1606 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1607 u32 i, hang_pos, hang_state, num_state = 6;
1608
1609 comp_state = REG_READ(ah, AR_DMADBG_6);
1610
1611 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1612 ath_dbg(ath9k_hw_common(ah), RESET,
1613 "MAC Hang signature not found at DCU complete\n");
1614 return false;
1615 }
1616
1617 chain_state = REG_READ(ah, dcs_reg);
1618 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1619 goto hang_check_iter;
1620
1621 dcs_reg = AR_DMADBG_5;
1622 num_state = 4;
1623 chain_state = REG_READ(ah, dcs_reg);
1624 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1625 goto hang_check_iter;
1626
1627 ath_dbg(ath9k_hw_common(ah), RESET,
1628 "MAC Hang signature 1 not found\n");
1629 return false;
1630
1631 hang_check_iter:
1632 ath_dbg(ath9k_hw_common(ah), RESET,
1633 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1634 chain_state, comp_state, hang_state, hang_pos);
1635
1636 for (i = 0; i < NUM_STATUS_READS; i++) {
1637 chain_state = REG_READ(ah, dcs_reg);
1638 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1639 comp_state = REG_READ(ah, AR_DMADBG_6);
1640
1641 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1642 DCU_COMPLETE_STATE) ||
1643 (chain_state != hang_state))
1644 return false;
1645 }
1646
1647 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1648
1649 return true;
1650 }
1651
1652 bool ath9k_hw_check_alive(struct ath_hw *ah)
1653 {
1654 int count = 50;
1655 u32 reg;
1656
1657 if (AR_SREV_9300(ah))
1658 return !ath9k_hw_detect_mac_hang(ah);
1659
1660 if (AR_SREV_9285_12_OR_LATER(ah))
1661 return true;
1662
1663 do {
1664 reg = REG_READ(ah, AR_OBS_BUS_1);
1665
1666 if ((reg & 0x7E7FFFEF) == 0x00702400)
1667 continue;
1668
1669 switch (reg & 0x7E000B00) {
1670 case 0x1E000000:
1671 case 0x52000B00:
1672 case 0x18000B00:
1673 continue;
1674 default:
1675 return true;
1676 }
1677 } while (count-- > 0);
1678
1679 return false;
1680 }
1681 EXPORT_SYMBOL(ath9k_hw_check_alive);
1682
1683 /*
1684 * Fast channel change:
1685 * (Change synthesizer based on channel freq without resetting chip)
1686 *
1687 * Don't do FCC when
1688 * - Flag is not set
1689 * - Chip is just coming out of full sleep
1690 * - Channel to be set is same as current channel
1691 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1692 */
1693 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1694 {
1695 struct ath_common *common = ath9k_hw_common(ah);
1696 int ret;
1697
1698 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1699 goto fail;
1700
1701 if (ah->chip_fullsleep)
1702 goto fail;
1703
1704 if (!ah->curchan)
1705 goto fail;
1706
1707 if (chan->channel == ah->curchan->channel)
1708 goto fail;
1709
1710 if ((ah->curchan->channelFlags | chan->channelFlags) &
1711 (CHANNEL_HALF | CHANNEL_QUARTER))
1712 goto fail;
1713
1714 if ((chan->channelFlags & CHANNEL_ALL) !=
1715 (ah->curchan->channelFlags & CHANNEL_ALL))
1716 goto fail;
1717
1718 if (!ath9k_hw_check_alive(ah))
1719 goto fail;
1720
1721 /*
1722 * For AR9462, make sure that calibration data for
1723 * re-using are present.
1724 */
1725 if (AR_SREV_9462(ah) && (ah->caldata &&
1726 (!ah->caldata->done_txiqcal_once ||
1727 !ah->caldata->done_txclcal_once ||
1728 !ah->caldata->rtt_done)))
1729 goto fail;
1730
1731 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1732 ah->curchan->channel, chan->channel);
1733
1734 ret = ath9k_hw_channel_change(ah, chan);
1735 if (!ret)
1736 goto fail;
1737
1738 ath9k_hw_loadnf(ah, ah->curchan);
1739 ath9k_hw_start_nfcal(ah, true);
1740
1741 if (ath9k_hw_mci_is_enabled(ah))
1742 ar9003_mci_2g5g_switch(ah, false);
1743
1744 if (AR_SREV_9271(ah))
1745 ar9002_hw_load_ani_reg(ah, chan);
1746
1747 return 0;
1748 fail:
1749 return -EINVAL;
1750 }
1751
1752 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1753 struct ath9k_hw_cal_data *caldata, bool fastcc)
1754 {
1755 struct ath_common *common = ath9k_hw_common(ah);
1756 u32 saveLedState;
1757 u32 saveDefAntenna;
1758 u32 macStaId1;
1759 u64 tsf = 0;
1760 int i, r;
1761 bool start_mci_reset = false;
1762 bool save_fullsleep = ah->chip_fullsleep;
1763
1764 if (ath9k_hw_mci_is_enabled(ah)) {
1765 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1766 if (start_mci_reset)
1767 return 0;
1768 }
1769
1770 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1771 return -EIO;
1772
1773 if (ah->curchan && !ah->chip_fullsleep)
1774 ath9k_hw_getnf(ah, ah->curchan);
1775
1776 ah->caldata = caldata;
1777 if (caldata &&
1778 (chan->channel != caldata->channel ||
1779 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1780 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1781 /* Operating channel changed, reset channel calibration data */
1782 memset(caldata, 0, sizeof(*caldata));
1783 ath9k_init_nfcal_hist_buffer(ah, chan);
1784 }
1785 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1786
1787 if (fastcc) {
1788 r = ath9k_hw_do_fastcc(ah, chan);
1789 if (!r)
1790 return r;
1791 }
1792
1793 if (ath9k_hw_mci_is_enabled(ah))
1794 ar9003_mci_stop_bt(ah, save_fullsleep);
1795
1796 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1797 if (saveDefAntenna == 0)
1798 saveDefAntenna = 1;
1799
1800 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1801
1802 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1803 if (AR_SREV_9100(ah) ||
1804 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1805 tsf = ath9k_hw_gettsf64(ah);
1806
1807 saveLedState = REG_READ(ah, AR_CFG_LED) &
1808 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1809 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1810
1811 ath9k_hw_mark_phy_inactive(ah);
1812
1813 ah->paprd_table_write_done = false;
1814
1815 /* Only required on the first reset */
1816 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1817 REG_WRITE(ah,
1818 AR9271_RESET_POWER_DOWN_CONTROL,
1819 AR9271_RADIO_RF_RST);
1820 udelay(50);
1821 }
1822
1823 if (!ath9k_hw_chip_reset(ah, chan)) {
1824 ath_err(common, "Chip reset failed\n");
1825 return -EINVAL;
1826 }
1827
1828 /* Only required on the first reset */
1829 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1830 ah->htc_reset_init = false;
1831 REG_WRITE(ah,
1832 AR9271_RESET_POWER_DOWN_CONTROL,
1833 AR9271_GATE_MAC_CTL);
1834 udelay(50);
1835 }
1836
1837 /* Restore TSF */
1838 if (tsf)
1839 ath9k_hw_settsf64(ah, tsf);
1840
1841 if (AR_SREV_9280_20_OR_LATER(ah))
1842 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1843
1844 if (!AR_SREV_9300_20_OR_LATER(ah))
1845 ar9002_hw_enable_async_fifo(ah);
1846
1847 r = ath9k_hw_process_ini(ah, chan);
1848 if (r)
1849 return r;
1850
1851 if (ath9k_hw_mci_is_enabled(ah))
1852 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1853
1854 /*
1855 * Some AR91xx SoC devices frequently fail to accept TSF writes
1856 * right after the chip reset. When that happens, write a new
1857 * value after the initvals have been applied, with an offset
1858 * based on measured time difference
1859 */
1860 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1861 tsf += 1500;
1862 ath9k_hw_settsf64(ah, tsf);
1863 }
1864
1865 /* Setup MFP options for CCMP */
1866 if (AR_SREV_9280_20_OR_LATER(ah)) {
1867 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1868 * frames when constructing CCMP AAD. */
1869 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1870 0xc7ff);
1871 ah->sw_mgmt_crypto = false;
1872 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1873 /* Disable hardware crypto for management frames */
1874 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1875 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1876 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1877 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1878 ah->sw_mgmt_crypto = true;
1879 } else
1880 ah->sw_mgmt_crypto = true;
1881
1882 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1883 ath9k_hw_set_delta_slope(ah, chan);
1884
1885 ath9k_hw_spur_mitigate_freq(ah, chan);
1886 ah->eep_ops->set_board_values(ah, chan);
1887
1888 ENABLE_REGWRITE_BUFFER(ah);
1889
1890 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1891 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1892 | macStaId1
1893 | AR_STA_ID1_RTS_USE_DEF
1894 | (ah->config.
1895 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1896 | ah->sta_id1_defaults);
1897 ath_hw_setbssidmask(common);
1898 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1899 ath9k_hw_write_associd(ah);
1900 REG_WRITE(ah, AR_ISR, ~0);
1901 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1902
1903 REGWRITE_BUFFER_FLUSH(ah);
1904
1905 ath9k_hw_set_operating_mode(ah, ah->opmode);
1906
1907 r = ath9k_hw_rf_set_freq(ah, chan);
1908 if (r)
1909 return r;
1910
1911 ath9k_hw_set_clockrate(ah);
1912
1913 ENABLE_REGWRITE_BUFFER(ah);
1914
1915 for (i = 0; i < AR_NUM_DCU; i++)
1916 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1917
1918 REGWRITE_BUFFER_FLUSH(ah);
1919
1920 ah->intr_txqs = 0;
1921 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1922 ath9k_hw_resettxqueue(ah, i);
1923
1924 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1925 ath9k_hw_ani_cache_ini_regs(ah);
1926 ath9k_hw_init_qos(ah);
1927
1928 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1929 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1930
1931 ath9k_hw_init_global_settings(ah);
1932
1933 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1934 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1935 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1936 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1937 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1938 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1939 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1940 }
1941
1942 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1943
1944 ath9k_hw_set_dma(ah);
1945
1946 if (!ath9k_hw_mci_is_enabled(ah))
1947 REG_WRITE(ah, AR_OBS, 8);
1948
1949 if (ah->config.rx_intr_mitigation) {
1950 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1951 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1952 }
1953
1954 if (ah->config.tx_intr_mitigation) {
1955 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1956 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1957 }
1958
1959 ath9k_hw_init_bb(ah, chan);
1960
1961 if (caldata) {
1962 caldata->done_txiqcal_once = false;
1963 caldata->done_txclcal_once = false;
1964 }
1965 if (!ath9k_hw_init_cal(ah, chan))
1966 return -EIO;
1967
1968 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1969 return -EIO;
1970
1971 ENABLE_REGWRITE_BUFFER(ah);
1972
1973 ath9k_hw_restore_chainmask(ah);
1974 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1975
1976 REGWRITE_BUFFER_FLUSH(ah);
1977
1978 /*
1979 * For big endian systems turn on swapping for descriptors
1980 */
1981 if (AR_SREV_9100(ah)) {
1982 u32 mask;
1983 mask = REG_READ(ah, AR_CFG);
1984 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1985 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1986 mask);
1987 } else {
1988 mask =
1989 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1990 REG_WRITE(ah, AR_CFG, mask);
1991 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1992 REG_READ(ah, AR_CFG));
1993 }
1994 } else {
1995 if (common->bus_ops->ath_bus_type == ATH_USB) {
1996 /* Configure AR9271 target WLAN */
1997 if (AR_SREV_9271(ah))
1998 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1999 else
2000 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2001 }
2002 #ifdef __BIG_ENDIAN
2003 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
2004 AR_SREV_9550(ah))
2005 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
2006 else
2007 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2008 #endif
2009 }
2010
2011 if (ath9k_hw_btcoex_is_enabled(ah))
2012 ath9k_hw_btcoex_enable(ah);
2013
2014 if (ath9k_hw_mci_is_enabled(ah))
2015 ar9003_mci_check_bt(ah);
2016
2017 ath9k_hw_loadnf(ah, chan);
2018 ath9k_hw_start_nfcal(ah, true);
2019
2020 if (AR_SREV_9300_20_OR_LATER(ah)) {
2021 ar9003_hw_bb_watchdog_config(ah);
2022
2023 ar9003_hw_disable_phy_restart(ah);
2024 }
2025
2026 ath9k_hw_apply_gpio_override(ah);
2027
2028 return 0;
2029 }
2030 EXPORT_SYMBOL(ath9k_hw_reset);
2031
2032 /******************************/
2033 /* Power Management (Chipset) */
2034 /******************************/
2035
2036 /*
2037 * Notify Power Mgt is disabled in self-generated frames.
2038 * If requested, force chip to sleep.
2039 */
2040 static void ath9k_set_power_sleep(struct ath_hw *ah)
2041 {
2042 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2043
2044 if (AR_SREV_9462(ah)) {
2045 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2046 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2047 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2048 /* xxx Required for WLAN only case ? */
2049 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2050 udelay(100);
2051 }
2052
2053 /*
2054 * Clear the RTC force wake bit to allow the
2055 * mac to go to sleep.
2056 */
2057 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2058
2059 if (ath9k_hw_mci_is_enabled(ah))
2060 udelay(100);
2061
2062 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2063 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2064
2065 /* Shutdown chip. Active low */
2066 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2067 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2068 udelay(2);
2069 }
2070
2071 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2072 if (AR_SREV_9300_20_OR_LATER(ah))
2073 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2074 }
2075
2076 /*
2077 * Notify Power Management is enabled in self-generating
2078 * frames. If request, set power mode of chip to
2079 * auto/normal. Duration in units of 128us (1/8 TU).
2080 */
2081 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2082 {
2083 struct ath9k_hw_capabilities *pCap = &ah->caps;
2084
2085 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2086
2087 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2088 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2089 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2090 AR_RTC_FORCE_WAKE_ON_INT);
2091 } else {
2092
2093 /* When chip goes into network sleep, it could be waken
2094 * up by MCI_INT interrupt caused by BT's HW messages
2095 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2096 * rate (~100us). This will cause chip to leave and
2097 * re-enter network sleep mode frequently, which in
2098 * consequence will have WLAN MCI HW to generate lots of
2099 * SYS_WAKING and SYS_SLEEPING messages which will make
2100 * BT CPU to busy to process.
2101 */
2102 if (ath9k_hw_mci_is_enabled(ah))
2103 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2104 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2105 /*
2106 * Clear the RTC force wake bit to allow the
2107 * mac to go to sleep.
2108 */
2109 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2110
2111 if (ath9k_hw_mci_is_enabled(ah))
2112 udelay(30);
2113 }
2114
2115 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2116 if (AR_SREV_9300_20_OR_LATER(ah))
2117 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2118 }
2119
2120 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2121 {
2122 u32 val;
2123 int i;
2124
2125 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2126 if (AR_SREV_9300_20_OR_LATER(ah)) {
2127 REG_WRITE(ah, AR_WA, ah->WARegVal);
2128 udelay(10);
2129 }
2130
2131 if ((REG_READ(ah, AR_RTC_STATUS) &
2132 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2133 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2134 return false;
2135 }
2136 if (!AR_SREV_9300_20_OR_LATER(ah))
2137 ath9k_hw_init_pll(ah, NULL);
2138 }
2139 if (AR_SREV_9100(ah))
2140 REG_SET_BIT(ah, AR_RTC_RESET,
2141 AR_RTC_RESET_EN);
2142
2143 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2144 AR_RTC_FORCE_WAKE_EN);
2145 udelay(50);
2146
2147 if (ath9k_hw_mci_is_enabled(ah))
2148 ar9003_mci_set_power_awake(ah);
2149
2150 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2151 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2152 if (val == AR_RTC_STATUS_ON)
2153 break;
2154 udelay(50);
2155 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2156 AR_RTC_FORCE_WAKE_EN);
2157 }
2158 if (i == 0) {
2159 ath_err(ath9k_hw_common(ah),
2160 "Failed to wakeup in %uus\n",
2161 POWER_UP_TIME / 20);
2162 return false;
2163 }
2164
2165 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2166
2167 return true;
2168 }
2169
2170 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2171 {
2172 struct ath_common *common = ath9k_hw_common(ah);
2173 int status = true;
2174 static const char *modes[] = {
2175 "AWAKE",
2176 "FULL-SLEEP",
2177 "NETWORK SLEEP",
2178 "UNDEFINED"
2179 };
2180
2181 if (ah->power_mode == mode)
2182 return status;
2183
2184 ath_dbg(common, RESET, "%s -> %s\n",
2185 modes[ah->power_mode], modes[mode]);
2186
2187 switch (mode) {
2188 case ATH9K_PM_AWAKE:
2189 status = ath9k_hw_set_power_awake(ah);
2190 break;
2191 case ATH9K_PM_FULL_SLEEP:
2192 if (ath9k_hw_mci_is_enabled(ah))
2193 ar9003_mci_set_full_sleep(ah);
2194
2195 ath9k_set_power_sleep(ah);
2196 ah->chip_fullsleep = true;
2197 break;
2198 case ATH9K_PM_NETWORK_SLEEP:
2199 ath9k_set_power_network_sleep(ah);
2200 break;
2201 default:
2202 ath_err(common, "Unknown power mode %u\n", mode);
2203 return false;
2204 }
2205 ah->power_mode = mode;
2206
2207 /*
2208 * XXX: If this warning never comes up after a while then
2209 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2210 * ath9k_hw_setpower() return type void.
2211 */
2212
2213 if (!(ah->ah_flags & AH_UNPLUGGED))
2214 ATH_DBG_WARN_ON_ONCE(!status);
2215
2216 return status;
2217 }
2218 EXPORT_SYMBOL(ath9k_hw_setpower);
2219
2220 /*******************/
2221 /* Beacon Handling */
2222 /*******************/
2223
2224 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2225 {
2226 int flags = 0;
2227
2228 ENABLE_REGWRITE_BUFFER(ah);
2229
2230 switch (ah->opmode) {
2231 case NL80211_IFTYPE_ADHOC:
2232 case NL80211_IFTYPE_MESH_POINT:
2233 REG_SET_BIT(ah, AR_TXCFG,
2234 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2235 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2236 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2237 flags |= AR_NDP_TIMER_EN;
2238 case NL80211_IFTYPE_AP:
2239 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2240 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2241 TU_TO_USEC(ah->config.dma_beacon_response_time));
2242 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2243 TU_TO_USEC(ah->config.sw_beacon_response_time));
2244 flags |=
2245 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2246 break;
2247 default:
2248 ath_dbg(ath9k_hw_common(ah), BEACON,
2249 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2250 return;
2251 break;
2252 }
2253
2254 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2255 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2256 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2257 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2258
2259 REGWRITE_BUFFER_FLUSH(ah);
2260
2261 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2262 }
2263 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2264
2265 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2266 const struct ath9k_beacon_state *bs)
2267 {
2268 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2269 struct ath9k_hw_capabilities *pCap = &ah->caps;
2270 struct ath_common *common = ath9k_hw_common(ah);
2271
2272 ENABLE_REGWRITE_BUFFER(ah);
2273
2274 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2275
2276 REG_WRITE(ah, AR_BEACON_PERIOD,
2277 TU_TO_USEC(bs->bs_intval));
2278 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2279 TU_TO_USEC(bs->bs_intval));
2280
2281 REGWRITE_BUFFER_FLUSH(ah);
2282
2283 REG_RMW_FIELD(ah, AR_RSSI_THR,
2284 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2285
2286 beaconintval = bs->bs_intval;
2287
2288 if (bs->bs_sleepduration > beaconintval)
2289 beaconintval = bs->bs_sleepduration;
2290
2291 dtimperiod = bs->bs_dtimperiod;
2292 if (bs->bs_sleepduration > dtimperiod)
2293 dtimperiod = bs->bs_sleepduration;
2294
2295 if (beaconintval == dtimperiod)
2296 nextTbtt = bs->bs_nextdtim;
2297 else
2298 nextTbtt = bs->bs_nexttbtt;
2299
2300 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2301 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2302 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2303 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2304
2305 ENABLE_REGWRITE_BUFFER(ah);
2306
2307 REG_WRITE(ah, AR_NEXT_DTIM,
2308 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2309 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2310
2311 REG_WRITE(ah, AR_SLEEP1,
2312 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2313 | AR_SLEEP1_ASSUME_DTIM);
2314
2315 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2316 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2317 else
2318 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2319
2320 REG_WRITE(ah, AR_SLEEP2,
2321 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2322
2323 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2324 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2325
2326 REGWRITE_BUFFER_FLUSH(ah);
2327
2328 REG_SET_BIT(ah, AR_TIMER_MODE,
2329 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2330 AR_DTIM_TIMER_EN);
2331
2332 /* TSF Out of Range Threshold */
2333 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2334 }
2335 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2336
2337 /*******************/
2338 /* HW Capabilities */
2339 /*******************/
2340
2341 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2342 {
2343 eeprom_chainmask &= chip_chainmask;
2344 if (eeprom_chainmask)
2345 return eeprom_chainmask;
2346 else
2347 return chip_chainmask;
2348 }
2349
2350 /**
2351 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2352 * @ah: the atheros hardware data structure
2353 *
2354 * We enable DFS support upstream on chipsets which have passed a series
2355 * of tests. The testing requirements are going to be documented. Desired
2356 * test requirements are documented at:
2357 *
2358 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2359 *
2360 * Once a new chipset gets properly tested an individual commit can be used
2361 * to document the testing for DFS for that chipset.
2362 */
2363 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2364 {
2365
2366 switch (ah->hw_version.macVersion) {
2367 /* AR9580 will likely be our first target to get testing on */
2368 case AR_SREV_VERSION_9580:
2369 default:
2370 return false;
2371 }
2372 }
2373
2374 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2375 {
2376 struct ath9k_hw_capabilities *pCap = &ah->caps;
2377 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2378 struct ath_common *common = ath9k_hw_common(ah);
2379 unsigned int chip_chainmask;
2380
2381 u16 eeval;
2382 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2383
2384 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2385 regulatory->current_rd = eeval;
2386
2387 if (ah->opmode != NL80211_IFTYPE_AP &&
2388 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2389 if (regulatory->current_rd == 0x64 ||
2390 regulatory->current_rd == 0x65)
2391 regulatory->current_rd += 5;
2392 else if (regulatory->current_rd == 0x41)
2393 regulatory->current_rd = 0x43;
2394 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2395 regulatory->current_rd);
2396 }
2397
2398 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2399 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2400 ath_err(common,
2401 "no band has been marked as supported in EEPROM\n");
2402 return -EINVAL;
2403 }
2404
2405 if (eeval & AR5416_OPFLAGS_11A)
2406 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2407
2408 if (eeval & AR5416_OPFLAGS_11G)
2409 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2410
2411 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2412 chip_chainmask = 1;
2413 else if (AR_SREV_9462(ah))
2414 chip_chainmask = 3;
2415 else if (!AR_SREV_9280_20_OR_LATER(ah))
2416 chip_chainmask = 7;
2417 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2418 chip_chainmask = 3;
2419 else
2420 chip_chainmask = 7;
2421
2422 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2423 /*
2424 * For AR9271 we will temporarilly uses the rx chainmax as read from
2425 * the EEPROM.
2426 */
2427 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2428 !(eeval & AR5416_OPFLAGS_11A) &&
2429 !(AR_SREV_9271(ah)))
2430 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2431 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2432 else if (AR_SREV_9100(ah))
2433 pCap->rx_chainmask = 0x7;
2434 else
2435 /* Use rx_chainmask from EEPROM. */
2436 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2437
2438 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2439 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2440 ah->txchainmask = pCap->tx_chainmask;
2441 ah->rxchainmask = pCap->rx_chainmask;
2442
2443 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2444
2445 /* enable key search for every frame in an aggregate */
2446 if (AR_SREV_9300_20_OR_LATER(ah))
2447 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2448
2449 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2450
2451 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2452 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2453 else
2454 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2455
2456 if (AR_SREV_9271(ah))
2457 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2458 else if (AR_DEVID_7010(ah))
2459 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2460 else if (AR_SREV_9300_20_OR_LATER(ah))
2461 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2462 else if (AR_SREV_9287_11_OR_LATER(ah))
2463 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2464 else if (AR_SREV_9285_12_OR_LATER(ah))
2465 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2466 else if (AR_SREV_9280_20_OR_LATER(ah))
2467 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2468 else
2469 pCap->num_gpio_pins = AR_NUM_GPIO;
2470
2471 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2472 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2473 else
2474 pCap->rts_aggr_limit = (8 * 1024);
2475
2476 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2477 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2478 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2479 ah->rfkill_gpio =
2480 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2481 ah->rfkill_polarity =
2482 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2483
2484 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2485 }
2486 #endif
2487 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2488 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2489 else
2490 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2491
2492 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2493 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2494 else
2495 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2496
2497 if (AR_SREV_9300_20_OR_LATER(ah)) {
2498 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2499 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2500 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2501
2502 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2503 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2504 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2505 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2506 pCap->txs_len = sizeof(struct ar9003_txs);
2507 if (!ah->config.paprd_disable &&
2508 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2509 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2510 } else {
2511 pCap->tx_desc_len = sizeof(struct ath_desc);
2512 if (AR_SREV_9280_20(ah))
2513 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2514 }
2515
2516 if (AR_SREV_9300_20_OR_LATER(ah))
2517 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2518
2519 if (AR_SREV_9300_20_OR_LATER(ah))
2520 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2521
2522 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2523 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2524
2525 if (AR_SREV_9285(ah))
2526 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2527 ant_div_ctl1 =
2528 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2529 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2530 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2531 }
2532 if (AR_SREV_9300_20_OR_LATER(ah)) {
2533 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2534 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2535 }
2536
2537
2538 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2539 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2540 /*
2541 * enable the diversity-combining algorithm only when
2542 * both enable_lna_div and enable_fast_div are set
2543 * Table for Diversity
2544 * ant_div_alt_lnaconf bit 0-1
2545 * ant_div_main_lnaconf bit 2-3
2546 * ant_div_alt_gaintb bit 4
2547 * ant_div_main_gaintb bit 5
2548 * enable_ant_div_lnadiv bit 6
2549 * enable_ant_fast_div bit 7
2550 */
2551 if ((ant_div_ctl1 >> 0x6) == 0x3)
2552 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2553 }
2554
2555 if (AR_SREV_9485_10(ah)) {
2556 pCap->pcie_lcr_extsync_en = true;
2557 pCap->pcie_lcr_offset = 0x80;
2558 }
2559
2560 if (ath9k_hw_dfs_tested(ah))
2561 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2562
2563 tx_chainmask = pCap->tx_chainmask;
2564 rx_chainmask = pCap->rx_chainmask;
2565 while (tx_chainmask || rx_chainmask) {
2566 if (tx_chainmask & BIT(0))
2567 pCap->max_txchains++;
2568 if (rx_chainmask & BIT(0))
2569 pCap->max_rxchains++;
2570
2571 tx_chainmask >>= 1;
2572 rx_chainmask >>= 1;
2573 }
2574
2575 if (AR_SREV_9300_20_OR_LATER(ah)) {
2576 ah->enabled_cals |= TX_IQ_CAL;
2577 if (AR_SREV_9485_OR_LATER(ah))
2578 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2579 }
2580
2581 if (AR_SREV_9462(ah)) {
2582
2583 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2584 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2585
2586 if (AR_SREV_9462_20(ah))
2587 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2588
2589 }
2590
2591
2592 if (AR_SREV_9280_20_OR_LATER(ah)) {
2593 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
2594 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;
2595
2596 if (AR_SREV_9280(ah))
2597 pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
2598 }
2599
2600 return 0;
2601 }
2602
2603 /****************************/
2604 /* GPIO / RFKILL / Antennae */
2605 /****************************/
2606
2607 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2608 u32 gpio, u32 type)
2609 {
2610 int addr;
2611 u32 gpio_shift, tmp;
2612
2613 if (gpio > 11)
2614 addr = AR_GPIO_OUTPUT_MUX3;
2615 else if (gpio > 5)
2616 addr = AR_GPIO_OUTPUT_MUX2;
2617 else
2618 addr = AR_GPIO_OUTPUT_MUX1;
2619
2620 gpio_shift = (gpio % 6) * 5;
2621
2622 if (AR_SREV_9280_20_OR_LATER(ah)
2623 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2624 REG_RMW(ah, addr, (type << gpio_shift),
2625 (0x1f << gpio_shift));
2626 } else {
2627 tmp = REG_READ(ah, addr);
2628 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2629 tmp &= ~(0x1f << gpio_shift);
2630 tmp |= (type << gpio_shift);
2631 REG_WRITE(ah, addr, tmp);
2632 }
2633 }
2634
2635 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2636 {
2637 u32 gpio_shift;
2638
2639 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2640
2641 if (AR_DEVID_7010(ah)) {
2642 gpio_shift = gpio;
2643 REG_RMW(ah, AR7010_GPIO_OE,
2644 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2645 (AR7010_GPIO_OE_MASK << gpio_shift));
2646 return;
2647 }
2648
2649 gpio_shift = gpio << 1;
2650 REG_RMW(ah,
2651 AR_GPIO_OE_OUT,
2652 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2653 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2654 }
2655 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2656
2657 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2658 {
2659 #define MS_REG_READ(x, y) \
2660 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2661
2662 if (gpio >= ah->caps.num_gpio_pins)
2663 return 0xffffffff;
2664
2665 if (AR_DEVID_7010(ah)) {
2666 u32 val;
2667 val = REG_READ(ah, AR7010_GPIO_IN);
2668 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2669 } else if (AR_SREV_9300_20_OR_LATER(ah))
2670 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2671 AR_GPIO_BIT(gpio)) != 0;
2672 else if (AR_SREV_9271(ah))
2673 return MS_REG_READ(AR9271, gpio) != 0;
2674 else if (AR_SREV_9287_11_OR_LATER(ah))
2675 return MS_REG_READ(AR9287, gpio) != 0;
2676 else if (AR_SREV_9285_12_OR_LATER(ah))
2677 return MS_REG_READ(AR9285, gpio) != 0;
2678 else if (AR_SREV_9280_20_OR_LATER(ah))
2679 return MS_REG_READ(AR928X, gpio) != 0;
2680 else
2681 return MS_REG_READ(AR, gpio) != 0;
2682 }
2683 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2684
2685 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2686 u32 ah_signal_type)
2687 {
2688 u32 gpio_shift;
2689
2690 if (AR_DEVID_7010(ah)) {
2691 gpio_shift = gpio;
2692 REG_RMW(ah, AR7010_GPIO_OE,
2693 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2694 (AR7010_GPIO_OE_MASK << gpio_shift));
2695 return;
2696 }
2697
2698 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2699 gpio_shift = 2 * gpio;
2700 REG_RMW(ah,
2701 AR_GPIO_OE_OUT,
2702 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2703 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2704 }
2705 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2706
2707 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2708 {
2709 if (AR_DEVID_7010(ah)) {
2710 val = val ? 0 : 1;
2711 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2712 AR_GPIO_BIT(gpio));
2713 return;
2714 }
2715
2716 if (AR_SREV_9271(ah))
2717 val = ~val;
2718
2719 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2720 AR_GPIO_BIT(gpio));
2721 }
2722 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2723
2724 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2725 {
2726 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2727 }
2728 EXPORT_SYMBOL(ath9k_hw_setantenna);
2729
2730 /*********************/
2731 /* General Operation */
2732 /*********************/
2733
2734 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2735 {
2736 u32 bits = REG_READ(ah, AR_RX_FILTER);
2737 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2738
2739 if (phybits & AR_PHY_ERR_RADAR)
2740 bits |= ATH9K_RX_FILTER_PHYRADAR;
2741 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2742 bits |= ATH9K_RX_FILTER_PHYERR;
2743
2744 return bits;
2745 }
2746 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2747
2748 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2749 {
2750 u32 phybits;
2751
2752 ENABLE_REGWRITE_BUFFER(ah);
2753
2754 if (AR_SREV_9462(ah))
2755 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2756
2757 REG_WRITE(ah, AR_RX_FILTER, bits);
2758
2759 phybits = 0;
2760 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2761 phybits |= AR_PHY_ERR_RADAR;
2762 if (bits & ATH9K_RX_FILTER_PHYERR)
2763 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2764 REG_WRITE(ah, AR_PHY_ERR, phybits);
2765
2766 if (phybits)
2767 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2768 else
2769 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2770
2771 REGWRITE_BUFFER_FLUSH(ah);
2772 }
2773 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2774
2775 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2776 {
2777 if (ath9k_hw_mci_is_enabled(ah))
2778 ar9003_mci_bt_gain_ctrl(ah);
2779
2780 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2781 return false;
2782
2783 ath9k_hw_init_pll(ah, NULL);
2784 ah->htc_reset_init = true;
2785 return true;
2786 }
2787 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2788
2789 bool ath9k_hw_disable(struct ath_hw *ah)
2790 {
2791 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2792 return false;
2793
2794 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2795 return false;
2796
2797 ath9k_hw_init_pll(ah, NULL);
2798 return true;
2799 }
2800 EXPORT_SYMBOL(ath9k_hw_disable);
2801
2802 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2803 {
2804 enum eeprom_param gain_param;
2805
2806 if (IS_CHAN_2GHZ(chan))
2807 gain_param = EEP_ANTENNA_GAIN_2G;
2808 else
2809 gain_param = EEP_ANTENNA_GAIN_5G;
2810
2811 return ah->eep_ops->get_eeprom(ah, gain_param);
2812 }
2813
2814 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2815 bool test)
2816 {
2817 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2818 struct ieee80211_channel *channel;
2819 int chan_pwr, new_pwr, max_gain;
2820 int ant_gain, ant_reduction = 0;
2821
2822 if (!chan)
2823 return;
2824
2825 channel = chan->chan;
2826 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2827 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2828 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2829
2830 ant_gain = get_antenna_gain(ah, chan);
2831 if (ant_gain > max_gain)
2832 ant_reduction = ant_gain - max_gain;
2833
2834 ah->eep_ops->set_txpower(ah, chan,
2835 ath9k_regd_get_ctl(reg, chan),
2836 ant_reduction, new_pwr, test);
2837 }
2838
2839 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2840 {
2841 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2842 struct ath9k_channel *chan = ah->curchan;
2843 struct ieee80211_channel *channel = chan->chan;
2844
2845 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2846 if (test)
2847 channel->max_power = MAX_RATE_POWER / 2;
2848
2849 ath9k_hw_apply_txpower(ah, chan, test);
2850
2851 if (test)
2852 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2853 }
2854 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2855
2856 void ath9k_hw_setopmode(struct ath_hw *ah)
2857 {
2858 ath9k_hw_set_operating_mode(ah, ah->opmode);
2859 }
2860 EXPORT_SYMBOL(ath9k_hw_setopmode);
2861
2862 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2863 {
2864 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2865 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2866 }
2867 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2868
2869 void ath9k_hw_write_associd(struct ath_hw *ah)
2870 {
2871 struct ath_common *common = ath9k_hw_common(ah);
2872
2873 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2874 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2875 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2876 }
2877 EXPORT_SYMBOL(ath9k_hw_write_associd);
2878
2879 #define ATH9K_MAX_TSF_READ 10
2880
2881 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2882 {
2883 u32 tsf_lower, tsf_upper1, tsf_upper2;
2884 int i;
2885
2886 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2887 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2888 tsf_lower = REG_READ(ah, AR_TSF_L32);
2889 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2890 if (tsf_upper2 == tsf_upper1)
2891 break;
2892 tsf_upper1 = tsf_upper2;
2893 }
2894
2895 WARN_ON( i == ATH9K_MAX_TSF_READ );
2896
2897 return (((u64)tsf_upper1 << 32) | tsf_lower);
2898 }
2899 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2900
2901 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2902 {
2903 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2904 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2905 }
2906 EXPORT_SYMBOL(ath9k_hw_settsf64);
2907
2908 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2909 {
2910 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2911 AH_TSF_WRITE_TIMEOUT))
2912 ath_dbg(ath9k_hw_common(ah), RESET,
2913 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2914
2915 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2916 }
2917 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2918
2919 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2920 {
2921 if (setting)
2922 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2923 else
2924 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2925 }
2926 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2927
2928 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2929 {
2930 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2931 u32 macmode;
2932
2933 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2934 macmode = AR_2040_JOINED_RX_CLEAR;
2935 else
2936 macmode = 0;
2937
2938 REG_WRITE(ah, AR_2040_MODE, macmode);
2939 }
2940
2941 /* HW Generic timers configuration */
2942
2943 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2944 {
2945 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2946 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2947 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2948 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2949 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2950 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2951 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2952 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2953 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2954 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2955 AR_NDP2_TIMER_MODE, 0x0002},
2956 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2957 AR_NDP2_TIMER_MODE, 0x0004},
2958 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2959 AR_NDP2_TIMER_MODE, 0x0008},
2960 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2961 AR_NDP2_TIMER_MODE, 0x0010},
2962 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2963 AR_NDP2_TIMER_MODE, 0x0020},
2964 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2965 AR_NDP2_TIMER_MODE, 0x0040},
2966 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2967 AR_NDP2_TIMER_MODE, 0x0080}
2968 };
2969
2970 /* HW generic timer primitives */
2971
2972 /* compute and clear index of rightmost 1 */
2973 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2974 {
2975 u32 b;
2976
2977 b = *mask;
2978 b &= (0-b);
2979 *mask &= ~b;
2980 b *= debruijn32;
2981 b >>= 27;
2982
2983 return timer_table->gen_timer_index[b];
2984 }
2985
2986 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2987 {
2988 return REG_READ(ah, AR_TSF_L32);
2989 }
2990 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2991
2992 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2993 void (*trigger)(void *),
2994 void (*overflow)(void *),
2995 void *arg,
2996 u8 timer_index)
2997 {
2998 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2999 struct ath_gen_timer *timer;
3000
3001 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3002
3003 if (timer == NULL) {
3004 ath_err(ath9k_hw_common(ah),
3005 "Failed to allocate memory for hw timer[%d]\n",
3006 timer_index);
3007 return NULL;
3008 }
3009
3010 /* allocate a hardware generic timer slot */
3011 timer_table->timers[timer_index] = timer;
3012 timer->index = timer_index;
3013 timer->trigger = trigger;
3014 timer->overflow = overflow;
3015 timer->arg = arg;
3016
3017 return timer;
3018 }
3019 EXPORT_SYMBOL(ath_gen_timer_alloc);
3020
3021 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3022 struct ath_gen_timer *timer,
3023 u32 trig_timeout,
3024 u32 timer_period)
3025 {
3026 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3027 u32 tsf, timer_next;
3028
3029 BUG_ON(!timer_period);
3030
3031 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3032
3033 tsf = ath9k_hw_gettsf32(ah);
3034
3035 timer_next = tsf + trig_timeout;
3036
3037 ath_dbg(ath9k_hw_common(ah), HWTIMER,
3038 "current tsf %x period %x timer_next %x\n",
3039 tsf, timer_period, timer_next);
3040
3041 /*
3042 * Program generic timer registers
3043 */
3044 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3045 timer_next);
3046 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3047 timer_period);
3048 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3049 gen_tmr_configuration[timer->index].mode_mask);
3050
3051 if (AR_SREV_9462(ah)) {
3052 /*
3053 * Starting from AR9462, each generic timer can select which tsf
3054 * to use. But we still follow the old rule, 0 - 7 use tsf and
3055 * 8 - 15 use tsf2.
3056 */
3057 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3058 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3059 (1 << timer->index));
3060 else
3061 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3062 (1 << timer->index));
3063 }
3064
3065 /* Enable both trigger and thresh interrupt masks */
3066 REG_SET_BIT(ah, AR_IMR_S5,
3067 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3068 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3069 }
3070 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3071
3072 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3073 {
3074 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3075
3076 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3077 (timer->index >= ATH_MAX_GEN_TIMER)) {
3078 return;
3079 }
3080
3081 /* Clear generic timer enable bits. */
3082 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3083 gen_tmr_configuration[timer->index].mode_mask);
3084
3085 /* Disable both trigger and thresh interrupt masks */
3086 REG_CLR_BIT(ah, AR_IMR_S5,
3087 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3088 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3089
3090 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3091 }
3092 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3093
3094 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3095 {
3096 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3097
3098 /* free the hardware generic timer slot */
3099 timer_table->timers[timer->index] = NULL;
3100 kfree(timer);
3101 }
3102 EXPORT_SYMBOL(ath_gen_timer_free);
3103
3104 /*
3105 * Generic Timer Interrupts handling
3106 */
3107 void ath_gen_timer_isr(struct ath_hw *ah)
3108 {
3109 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3110 struct ath_gen_timer *timer;
3111 struct ath_common *common = ath9k_hw_common(ah);
3112 u32 trigger_mask, thresh_mask, index;
3113
3114 /* get hardware generic timer interrupt status */
3115 trigger_mask = ah->intr_gen_timer_trigger;
3116 thresh_mask = ah->intr_gen_timer_thresh;
3117 trigger_mask &= timer_table->timer_mask.val;
3118 thresh_mask &= timer_table->timer_mask.val;
3119
3120 trigger_mask &= ~thresh_mask;
3121
3122 while (thresh_mask) {
3123 index = rightmost_index(timer_table, &thresh_mask);
3124 timer = timer_table->timers[index];
3125 BUG_ON(!timer);
3126 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3127 index);
3128 timer->overflow(timer->arg);
3129 }
3130
3131 while (trigger_mask) {
3132 index = rightmost_index(timer_table, &trigger_mask);
3133 timer = timer_table->timers[index];
3134 BUG_ON(!timer);
3135 ath_dbg(common, HWTIMER,
3136 "Gen timer[%d] trigger\n", index);
3137 timer->trigger(timer->arg);
3138 }
3139 }
3140 EXPORT_SYMBOL(ath_gen_timer_isr);
3141
3142 /********/
3143 /* HTC */
3144 /********/
3145
3146 static struct {
3147 u32 version;
3148 const char * name;
3149 } ath_mac_bb_names[] = {
3150 /* Devices with external radios */
3151 { AR_SREV_VERSION_5416_PCI, "5416" },
3152 { AR_SREV_VERSION_5416_PCIE, "5418" },
3153 { AR_SREV_VERSION_9100, "9100" },
3154 { AR_SREV_VERSION_9160, "9160" },
3155 /* Single-chip solutions */
3156 { AR_SREV_VERSION_9280, "9280" },
3157 { AR_SREV_VERSION_9285, "9285" },
3158 { AR_SREV_VERSION_9287, "9287" },
3159 { AR_SREV_VERSION_9271, "9271" },
3160 { AR_SREV_VERSION_9300, "9300" },
3161 { AR_SREV_VERSION_9330, "9330" },
3162 { AR_SREV_VERSION_9340, "9340" },
3163 { AR_SREV_VERSION_9485, "9485" },
3164 { AR_SREV_VERSION_9462, "9462" },
3165 { AR_SREV_VERSION_9550, "9550" },
3166 };
3167
3168 /* For devices with external radios */
3169 static struct {
3170 u16 version;
3171 const char * name;
3172 } ath_rf_names[] = {
3173 { 0, "5133" },
3174 { AR_RAD5133_SREV_MAJOR, "5133" },
3175 { AR_RAD5122_SREV_MAJOR, "5122" },
3176 { AR_RAD2133_SREV_MAJOR, "2133" },
3177 { AR_RAD2122_SREV_MAJOR, "2122" }
3178 };
3179
3180 /*
3181 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3182 */
3183 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3184 {
3185 int i;
3186
3187 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3188 if (ath_mac_bb_names[i].version == mac_bb_version) {
3189 return ath_mac_bb_names[i].name;
3190 }
3191 }
3192
3193 return "????";
3194 }
3195
3196 /*
3197 * Return the RF name. "????" is returned if the RF is unknown.
3198 * Used for devices with external radios.
3199 */
3200 static const char *ath9k_hw_rf_name(u16 rf_version)
3201 {
3202 int i;
3203
3204 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3205 if (ath_rf_names[i].version == rf_version) {
3206 return ath_rf_names[i].name;
3207 }
3208 }
3209
3210 return "????";
3211 }
3212
3213 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3214 {
3215 int used;
3216
3217 /* chipsets >= AR9280 are single-chip */
3218 if (AR_SREV_9280_20_OR_LATER(ah)) {
3219 used = snprintf(hw_name, len,
3220 "Atheros AR%s Rev:%x",
3221 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3222 ah->hw_version.macRev);
3223 }
3224 else {
3225 used = snprintf(hw_name, len,
3226 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3227 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3228 ah->hw_version.macRev,
3229 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3230 AR_RADIO_SREV_MAJOR)),
3231 ah->hw_version.phyRev);
3232 }
3233
3234 hw_name[used] = '\0';
3235 }
3236 EXPORT_SYMBOL(ath9k_hw_name);
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