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ath9k_hw: fix device ID check for AR956x
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <linux/bitops.h>
22 #include <linux/etherdevice.h>
23 #include <linux/gpio.h>
24 #include <asm/unaligned.h>
25
26 #include "hw.h"
27 #include "hw-ops.h"
28 #include "ar9003_mac.h"
29 #include "ar9003_mci.h"
30 #include "ar9003_phy.h"
31 #include "ath9k.h"
32
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
34
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
39
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
41 {
42 struct ath_common *common = ath9k_hw_common(ah);
43 struct ath9k_channel *chan = ah->curchan;
44 unsigned int clockrate;
45
46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
49 else if (!chan) /* should really check for CCK instead */
50 clockrate = ATH9K_CLOCK_RATE_CCK;
51 else if (IS_CHAN_2GHZ(chan))
52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
55 else
56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
61 if (IS_CHAN_HALF_RATE(chan))
62 clockrate /= 2;
63 if (IS_CHAN_QUARTER_RATE(chan))
64 clockrate /= 4;
65 }
66
67 common->clockrate = clockrate;
68 }
69
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
71 {
72 struct ath_common *common = ath9k_hw_common(ah);
73
74 return usecs * common->clockrate;
75 }
76
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
78 {
79 int i;
80
81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
89
90 ath_dbg(ath9k_hw_common(ah), ANY,
91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
93
94 return false;
95 }
96 EXPORT_SYMBOL(ath9k_hw_wait);
97
98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100 {
101 hw_delay /= 10;
102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109 }
110
111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
112 int column, unsigned int *writecnt)
113 {
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123 }
124
125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
126 {
127 u32 *tmp_reg_list, *tmp_data;
128 int i;
129
130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
131 if (!tmp_reg_list) {
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
133 return;
134 }
135
136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
137 if (!tmp_data) {
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
139 goto error_tmp_data;
140 }
141
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
144
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
146
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
149
150 kfree(tmp_data);
151 error_tmp_data:
152 kfree(tmp_reg_list);
153 }
154
155 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
156 {
157 u32 retval;
158 int i;
159
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
162 val >>= 1;
163 }
164 return retval;
165 }
166
167 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
168 u8 phy, int kbps,
169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
171 {
172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
173
174 if (kbps == 0)
175 return 0;
176
177 switch (phy) {
178 case WLAN_RC_PHY_CCK:
179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
180 if (shortPreamble)
181 phyTime >>= 1;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
184 break;
185 case WLAN_RC_PHY_OFDM:
186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_QUARTER
191 + OFDM_PREAMBLE_TIME_QUARTER
192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
196 numBits = OFDM_PLCP_BITS + (frameLen << 3);
197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
198 txTime = OFDM_SIFS_TIME_HALF +
199 OFDM_PREAMBLE_TIME_HALF
200 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
201 } else {
202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
203 numBits = OFDM_PLCP_BITS + (frameLen << 3);
204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
206 + (numSymbols * OFDM_SYMBOL_TIME);
207 }
208 break;
209 default:
210 ath_err(ath9k_hw_common(ah),
211 "Unknown phy %u (rate ix %u)\n", phy, rateix);
212 txTime = 0;
213 break;
214 }
215
216 return txTime;
217 }
218 EXPORT_SYMBOL(ath9k_hw_computetxtime);
219
220 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
221 struct ath9k_channel *chan,
222 struct chan_centers *centers)
223 {
224 int8_t extoff;
225
226 if (!IS_CHAN_HT40(chan)) {
227 centers->ctl_center = centers->ext_center =
228 centers->synth_center = chan->channel;
229 return;
230 }
231
232 if (IS_CHAN_HT40PLUS(chan)) {
233 centers->synth_center =
234 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
235 extoff = 1;
236 } else {
237 centers->synth_center =
238 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
239 extoff = -1;
240 }
241
242 centers->ctl_center =
243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
244 /* 25 MHz spacing is supported by hw but not on upper layers */
245 centers->ext_center =
246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 }
248
249 /******************/
250 /* Chip Revisions */
251 /******************/
252
253 static void ath9k_hw_read_revisions(struct ath_hw *ah)
254 {
255 u32 val;
256
257 if (ah->get_mac_revision)
258 ah->hw_version.macRev = ah->get_mac_revision();
259
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (!ah->get_mac_revision) {
267 val = REG_READ(ah, AR_SREV);
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 }
270 return;
271 case AR9300_DEVID_AR9340:
272 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
273 return;
274 case AR9300_DEVID_QCA955X:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
276 return;
277 case AR9300_DEVID_AR953X:
278 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
279 return;
280 case AR9300_DEVID_QCA956X:
281 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
282 return;
283 }
284
285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
286
287 if (val == 0xFF) {
288 val = REG_READ(ah, AR_SREV);
289 ah->hw_version.macVersion =
290 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
292
293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
294 ah->is_pciexpress = true;
295 else
296 ah->is_pciexpress = (val &
297 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
298 } else {
299 if (!AR_SREV_9100(ah))
300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
301
302 ah->hw_version.macRev = val & AR_SREV_REVISION;
303
304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
305 ah->is_pciexpress = true;
306 }
307 }
308
309 /************************************/
310 /* HW Attach, Detach, Init Routines */
311 /************************************/
312
313 static void ath9k_hw_disablepcie(struct ath_hw *ah)
314 {
315 if (!AR_SREV_5416(ah))
316 return;
317
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
327
328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
329 }
330
331 /* This should work for all families including legacy */
332 static bool ath9k_hw_chip_test(struct ath_hw *ah)
333 {
334 struct ath_common *common = ath9k_hw_common(ah);
335 u32 regAddr[2] = { AR_STA_ID0 };
336 u32 regHold[2];
337 static const u32 patternData[4] = {
338 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
339 };
340 int i, j, loop_max;
341
342 if (!AR_SREV_9300_20_OR_LATER(ah)) {
343 loop_max = 2;
344 regAddr[1] = AR_PHY_BASE + (8 << 2);
345 } else
346 loop_max = 1;
347
348 for (i = 0; i < loop_max; i++) {
349 u32 addr = regAddr[i];
350 u32 wrData, rdData;
351
352 regHold[i] = REG_READ(ah, addr);
353 for (j = 0; j < 0x100; j++) {
354 wrData = (j << 16) | j;
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (rdData != wrData) {
358 ath_err(common,
359 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
360 addr, wrData, rdData);
361 return false;
362 }
363 }
364 for (j = 0; j < 4; j++) {
365 wrData = patternData[j];
366 REG_WRITE(ah, addr, wrData);
367 rdData = REG_READ(ah, addr);
368 if (wrData != rdData) {
369 ath_err(common,
370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 addr, wrData, rdData);
372 return false;
373 }
374 }
375 REG_WRITE(ah, regAddr[i], regHold[i]);
376 }
377 udelay(100);
378
379 return true;
380 }
381
382 static void ath9k_hw_init_config(struct ath_hw *ah)
383 {
384 struct ath_common *common = ath9k_hw_common(ah);
385
386 ah->config.dma_beacon_response_time = 1;
387 ah->config.sw_beacon_response_time = 6;
388 ah->config.cwm_ignore_extcca = 0;
389 ah->config.analog_shiftreg = 1;
390
391 ah->config.rx_intr_mitigation = true;
392
393 if (AR_SREV_9300_20_OR_LATER(ah)) {
394 ah->config.rimt_last = 500;
395 ah->config.rimt_first = 2000;
396 } else {
397 ah->config.rimt_last = 250;
398 ah->config.rimt_first = 700;
399 }
400
401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
402 ah->config.pll_pwrsave = 7;
403
404 /*
405 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
406 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
407 * This means we use it for all AR5416 devices, and the few
408 * minor PCI AR9280 devices out there.
409 *
410 * Serialization is required because these devices do not handle
411 * well the case of two concurrent reads/writes due to the latency
412 * involved. During one read/write another read/write can be issued
413 * on another CPU while the previous read/write may still be working
414 * on our hardware, if we hit this case the hardware poops in a loop.
415 * We prevent this by serializing reads and writes.
416 *
417 * This issue is not present on PCI-Express devices or pre-AR5416
418 * devices (legacy, 802.11abg).
419 */
420 if (num_possible_cpus() > 1)
421 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
422
423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
426 !ah->is_pciexpress)) {
427 ah->config.serialize_regmode = SER_REG_MODE_ON;
428 } else {
429 ah->config.serialize_regmode = SER_REG_MODE_OFF;
430 }
431 }
432
433 ath_dbg(common, RESET, "serialize_regmode is %d\n",
434 ah->config.serialize_regmode);
435
436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
438 else
439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
440 }
441
442 static void ath9k_hw_init_defaults(struct ath_hw *ah)
443 {
444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
445
446 regulatory->country_code = CTRY_DEFAULT;
447 regulatory->power_limit = MAX_RATE_POWER;
448
449 ah->hw_version.magic = AR5416_MAGIC;
450 ah->hw_version.subvendorid = 0;
451
452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
453 AR_STA_ID1_MCAST_KSRCH;
454 if (AR_SREV_9100(ah))
455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
456
457 ah->slottime = ATH9K_SLOT_TIME_9;
458 ah->globaltxtimeout = (u32) -1;
459 ah->power_mode = ATH9K_PM_UNDEFINED;
460 ah->htc_reset_init = true;
461
462 ah->tpc_enabled = false;
463
464 ah->ani_function = ATH9K_ANI_ALL;
465 if (!AR_SREV_9300_20_OR_LATER(ah))
466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
467
468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
470 else
471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
472 }
473
474 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
475 {
476 struct ath_common *common = ath9k_hw_common(ah);
477 u32 sum;
478 int i;
479 u16 eeval;
480 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
481
482 sum = 0;
483 for (i = 0; i < 3; i++) {
484 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
485 sum += eeval;
486 common->macaddr[2 * i] = eeval >> 8;
487 common->macaddr[2 * i + 1] = eeval & 0xff;
488 }
489 if (!is_valid_ether_addr(common->macaddr)) {
490 ath_err(common,
491 "eeprom contains invalid mac address: %pM\n",
492 common->macaddr);
493
494 random_ether_addr(common->macaddr);
495 ath_err(common,
496 "random mac address will be used: %pM\n",
497 common->macaddr);
498 }
499
500 return 0;
501 }
502
503 static int ath9k_hw_post_init(struct ath_hw *ah)
504 {
505 struct ath_common *common = ath9k_hw_common(ah);
506 int ecode;
507
508 if (common->bus_ops->ath_bus_type != ATH_USB) {
509 if (!ath9k_hw_chip_test(ah))
510 return -ENODEV;
511 }
512
513 if (!AR_SREV_9300_20_OR_LATER(ah)) {
514 ecode = ar9002_hw_rf_claim(ah);
515 if (ecode != 0)
516 return ecode;
517 }
518
519 ecode = ath9k_hw_eeprom_init(ah);
520 if (ecode != 0)
521 return ecode;
522
523 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
524 ah->eep_ops->get_eeprom_ver(ah),
525 ah->eep_ops->get_eeprom_rev(ah));
526
527 ath9k_hw_ani_init(ah);
528
529 /*
530 * EEPROM needs to be initialized before we do this.
531 * This is required for regulatory compliance.
532 */
533 if (AR_SREV_9300_20_OR_LATER(ah)) {
534 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
535 if ((regdmn & 0xF0) == CTL_FCC) {
536 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
537 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
538 }
539 }
540
541 return 0;
542 }
543
544 static int ath9k_hw_attach_ops(struct ath_hw *ah)
545 {
546 if (!AR_SREV_9300_20_OR_LATER(ah))
547 return ar9002_hw_attach_ops(ah);
548
549 ar9003_hw_attach_ops(ah);
550 return 0;
551 }
552
553 /* Called for all hardware families */
554 static int __ath9k_hw_init(struct ath_hw *ah)
555 {
556 struct ath_common *common = ath9k_hw_common(ah);
557 int r = 0;
558
559 ath9k_hw_read_revisions(ah);
560
561 switch (ah->hw_version.macVersion) {
562 case AR_SREV_VERSION_5416_PCI:
563 case AR_SREV_VERSION_5416_PCIE:
564 case AR_SREV_VERSION_9160:
565 case AR_SREV_VERSION_9100:
566 case AR_SREV_VERSION_9280:
567 case AR_SREV_VERSION_9285:
568 case AR_SREV_VERSION_9287:
569 case AR_SREV_VERSION_9271:
570 case AR_SREV_VERSION_9300:
571 case AR_SREV_VERSION_9330:
572 case AR_SREV_VERSION_9485:
573 case AR_SREV_VERSION_9340:
574 case AR_SREV_VERSION_9462:
575 case AR_SREV_VERSION_9550:
576 case AR_SREV_VERSION_9565:
577 case AR_SREV_VERSION_9531:
578 case AR_SREV_VERSION_9561:
579 break;
580 default:
581 ath_err(common,
582 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
583 ah->hw_version.macVersion, ah->hw_version.macRev);
584 return -EOPNOTSUPP;
585 }
586
587 /*
588 * Read back AR_WA into a permanent copy and set bits 14 and 17.
589 * We need to do this to avoid RMW of this register. We cannot
590 * read the reg when chip is asleep.
591 */
592 if (AR_SREV_9300_20_OR_LATER(ah)) {
593 ah->WARegVal = REG_READ(ah, AR_WA);
594 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
595 AR_WA_ASPM_TIMER_BASED_DISABLE);
596 }
597
598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
599 ath_err(common, "Couldn't reset chip\n");
600 return -EIO;
601 }
602
603 if (AR_SREV_9565(ah)) {
604 ah->WARegVal |= AR_WA_BIT22;
605 REG_WRITE(ah, AR_WA, ah->WARegVal);
606 }
607
608 ath9k_hw_init_defaults(ah);
609 ath9k_hw_init_config(ah);
610
611 r = ath9k_hw_attach_ops(ah);
612 if (r)
613 return r;
614
615 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
616 ath_err(common, "Couldn't wakeup chip\n");
617 return -EIO;
618 }
619
620 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
621 AR_SREV_9330(ah) || AR_SREV_9550(ah))
622 ah->is_pciexpress = false;
623
624 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
625 ath9k_hw_init_cal_settings(ah);
626
627 if (!ah->is_pciexpress)
628 ath9k_hw_disablepcie(ah);
629
630 r = ath9k_hw_post_init(ah);
631 if (r)
632 return r;
633
634 ath9k_hw_init_mode_gain_regs(ah);
635 r = ath9k_hw_fill_cap_info(ah);
636 if (r)
637 return r;
638
639 r = ath9k_hw_init_macaddr(ah);
640 if (r) {
641 ath_err(common, "Failed to initialize MAC address\n");
642 return r;
643 }
644
645 ath9k_hw_init_hang_checks(ah);
646
647 common->state = ATH_HW_INITIALIZED;
648
649 return 0;
650 }
651
652 int ath9k_hw_init(struct ath_hw *ah)
653 {
654 int ret;
655 struct ath_common *common = ath9k_hw_common(ah);
656
657 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
658 switch (ah->hw_version.devid) {
659 case AR5416_DEVID_PCI:
660 case AR5416_DEVID_PCIE:
661 case AR5416_AR9100_DEVID:
662 case AR9160_DEVID_PCI:
663 case AR9280_DEVID_PCI:
664 case AR9280_DEVID_PCIE:
665 case AR9285_DEVID_PCIE:
666 case AR9287_DEVID_PCI:
667 case AR9287_DEVID_PCIE:
668 case AR2427_DEVID_PCIE:
669 case AR9300_DEVID_PCIE:
670 case AR9300_DEVID_AR9485_PCIE:
671 case AR9300_DEVID_AR9330:
672 case AR9300_DEVID_AR9340:
673 case AR9300_DEVID_QCA955X:
674 case AR9300_DEVID_AR9580:
675 case AR9300_DEVID_AR9462:
676 case AR9485_DEVID_AR1111:
677 case AR9300_DEVID_AR9565:
678 case AR9300_DEVID_AR953X:
679 case AR9300_DEVID_QCA956X:
680 break;
681 default:
682 if (common->bus_ops->ath_bus_type == ATH_USB)
683 break;
684 ath_err(common, "Hardware device ID 0x%04x not supported\n",
685 ah->hw_version.devid);
686 return -EOPNOTSUPP;
687 }
688
689 ret = __ath9k_hw_init(ah);
690 if (ret) {
691 ath_err(common,
692 "Unable to initialize hardware; initialization status: %d\n",
693 ret);
694 return ret;
695 }
696
697 ath_dynack_init(ah);
698
699 return 0;
700 }
701 EXPORT_SYMBOL(ath9k_hw_init);
702
703 static void ath9k_hw_init_qos(struct ath_hw *ah)
704 {
705 ENABLE_REGWRITE_BUFFER(ah);
706
707 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
708 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
709
710 REG_WRITE(ah, AR_QOS_NO_ACK,
711 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
712 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
713 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
714
715 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
716 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
718 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
719 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
720
721 REGWRITE_BUFFER_FLUSH(ah);
722 }
723
724 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
725 {
726 struct ath_common *common = ath9k_hw_common(ah);
727 int i = 0;
728
729 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
730 udelay(100);
731 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
732
733 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
734
735 udelay(100);
736
737 if (WARN_ON_ONCE(i >= 100)) {
738 ath_err(common, "PLL4 meaurement not done\n");
739 break;
740 }
741
742 i++;
743 }
744
745 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
746 }
747 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
748
749 static void ath9k_hw_init_pll(struct ath_hw *ah,
750 struct ath9k_channel *chan)
751 {
752 u32 pll;
753
754 pll = ath9k_hw_compute_pll_control(ah, chan);
755
756 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
757 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
761 AR_CH0_DPLL2_KD, 0x40);
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
763 AR_CH0_DPLL2_KI, 0x4);
764
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
766 AR_CH0_BB_DPLL1_REFDIV, 0x5);
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
768 AR_CH0_BB_DPLL1_NINI, 0x58);
769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
770 AR_CH0_BB_DPLL1_NFRAC, 0x0);
771
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
775 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
777 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
778
779 /* program BB PLL phase_shift to 0x6 */
780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
781 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
782
783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
784 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
785 udelay(1000);
786 } else if (AR_SREV_9330(ah)) {
787 u32 ddr_dpll2, pll_control2, kd;
788
789 if (ah->is_clk_25mhz) {
790 ddr_dpll2 = 0x18e82f01;
791 pll_control2 = 0xe04a3d;
792 kd = 0x1d;
793 } else {
794 ddr_dpll2 = 0x19e82f01;
795 pll_control2 = 0x886666;
796 kd = 0x3d;
797 }
798
799 /* program DDR PLL ki and kd value */
800 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
801
802 /* program DDR PLL phase_shift */
803 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
804 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
805
806 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
807 pll | AR_RTC_9300_PLL_BYPASS);
808 udelay(1000);
809
810 /* program refdiv, nint, frac to RTC register */
811 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
812
813 /* program BB PLL kd and ki value */
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
816
817 /* program BB PLL phase_shift */
818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
819 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
820 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
821 AR_SREV_9561(ah)) {
822 u32 regval, pll2_divint, pll2_divfrac, refdiv;
823
824 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
825 pll | AR_RTC_9300_SOC_PLL_BYPASS);
826 udelay(1000);
827
828 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
829 udelay(100);
830
831 if (ah->is_clk_25mhz) {
832 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
833 pll2_divint = 0x1c;
834 pll2_divfrac = 0xa3d2;
835 refdiv = 1;
836 } else {
837 pll2_divint = 0x54;
838 pll2_divfrac = 0x1eb85;
839 refdiv = 3;
840 }
841 } else {
842 if (AR_SREV_9340(ah)) {
843 pll2_divint = 88;
844 pll2_divfrac = 0;
845 refdiv = 5;
846 } else {
847 pll2_divint = 0x11;
848 pll2_divfrac = (AR_SREV_9531(ah) ||
849 AR_SREV_9561(ah)) ?
850 0x26665 : 0x26666;
851 refdiv = 1;
852 }
853 }
854
855 regval = REG_READ(ah, AR_PHY_PLL_MODE);
856 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
857 regval |= (0x1 << 22);
858 else
859 regval |= (0x1 << 16);
860 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
861 udelay(100);
862
863 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
864 (pll2_divint << 18) | pll2_divfrac);
865 udelay(100);
866
867 regval = REG_READ(ah, AR_PHY_PLL_MODE);
868 if (AR_SREV_9340(ah))
869 regval = (regval & 0x80071fff) |
870 (0x1 << 30) |
871 (0x1 << 13) |
872 (0x4 << 26) |
873 (0x18 << 19);
874 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
875 regval = (regval & 0x01c00fff) |
876 (0x1 << 31) |
877 (0x2 << 29) |
878 (0xa << 25) |
879 (0x1 << 19);
880
881 if (AR_SREV_9531(ah))
882 regval |= (0x6 << 12);
883 } else
884 regval = (regval & 0x80071fff) |
885 (0x3 << 30) |
886 (0x1 << 13) |
887 (0x4 << 26) |
888 (0x60 << 19);
889 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
890
891 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
892 REG_WRITE(ah, AR_PHY_PLL_MODE,
893 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
894 else
895 REG_WRITE(ah, AR_PHY_PLL_MODE,
896 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
897
898 udelay(1000);
899 }
900
901 if (AR_SREV_9565(ah))
902 pll |= 0x40000;
903 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
904
905 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
906 AR_SREV_9550(ah))
907 udelay(1000);
908
909 /* Switch the core clock for ar9271 to 117Mhz */
910 if (AR_SREV_9271(ah)) {
911 udelay(500);
912 REG_WRITE(ah, 0x50040, 0x304);
913 }
914
915 udelay(RTC_PLL_SETTLE_DELAY);
916
917 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
918 }
919
920 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
921 enum nl80211_iftype opmode)
922 {
923 u32 sync_default = AR_INTR_SYNC_DEFAULT;
924 u32 imr_reg = AR_IMR_TXERR |
925 AR_IMR_TXURN |
926 AR_IMR_RXERR |
927 AR_IMR_RXORN |
928 AR_IMR_BCNMISC;
929
930 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
931 AR_SREV_9561(ah))
932 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
933
934 if (AR_SREV_9300_20_OR_LATER(ah)) {
935 imr_reg |= AR_IMR_RXOK_HP;
936 if (ah->config.rx_intr_mitigation)
937 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
938 else
939 imr_reg |= AR_IMR_RXOK_LP;
940
941 } else {
942 if (ah->config.rx_intr_mitigation)
943 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
944 else
945 imr_reg |= AR_IMR_RXOK;
946 }
947
948 if (ah->config.tx_intr_mitigation)
949 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
950 else
951 imr_reg |= AR_IMR_TXOK;
952
953 ENABLE_REGWRITE_BUFFER(ah);
954
955 REG_WRITE(ah, AR_IMR, imr_reg);
956 ah->imrs2_reg |= AR_IMR_S2_GTT;
957 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
958
959 if (!AR_SREV_9100(ah)) {
960 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
961 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
962 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
963 }
964
965 REGWRITE_BUFFER_FLUSH(ah);
966
967 if (AR_SREV_9300_20_OR_LATER(ah)) {
968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
969 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
971 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
972 }
973 }
974
975 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
976 {
977 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
978 val = min(val, (u32) 0xFFFF);
979 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
980 }
981
982 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
983 {
984 u32 val = ath9k_hw_mac_to_clks(ah, us);
985 val = min(val, (u32) 0xFFFF);
986 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
987 }
988
989 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
990 {
991 u32 val = ath9k_hw_mac_to_clks(ah, us);
992 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
993 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
994 }
995
996 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
997 {
998 u32 val = ath9k_hw_mac_to_clks(ah, us);
999 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1000 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1001 }
1002
1003 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1004 {
1005 if (tu > 0xFFFF) {
1006 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1007 tu);
1008 ah->globaltxtimeout = (u32) -1;
1009 return false;
1010 } else {
1011 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1012 ah->globaltxtimeout = tu;
1013 return true;
1014 }
1015 }
1016
1017 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1018 {
1019 struct ath_common *common = ath9k_hw_common(ah);
1020 const struct ath9k_channel *chan = ah->curchan;
1021 int acktimeout, ctstimeout, ack_offset = 0;
1022 int slottime;
1023 int sifstime;
1024 int rx_lat = 0, tx_lat = 0, eifs = 0;
1025 u32 reg;
1026
1027 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1028 ah->misc_mode);
1029
1030 if (!chan)
1031 return;
1032
1033 if (ah->misc_mode != 0)
1034 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1035
1036 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1037 rx_lat = 41;
1038 else
1039 rx_lat = 37;
1040 tx_lat = 54;
1041
1042 if (IS_CHAN_5GHZ(chan))
1043 sifstime = 16;
1044 else
1045 sifstime = 10;
1046
1047 if (IS_CHAN_HALF_RATE(chan)) {
1048 eifs = 175;
1049 rx_lat *= 2;
1050 tx_lat *= 2;
1051 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1052 tx_lat += 11;
1053
1054 sifstime = 32;
1055 ack_offset = 16;
1056 slottime = 13;
1057 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1058 eifs = 340;
1059 rx_lat = (rx_lat * 4) - 1;
1060 tx_lat *= 4;
1061 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1062 tx_lat += 22;
1063
1064 sifstime = 64;
1065 ack_offset = 32;
1066 slottime = 21;
1067 } else {
1068 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1069 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1070 reg = AR_USEC_ASYNC_FIFO;
1071 } else {
1072 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1073 common->clockrate;
1074 reg = REG_READ(ah, AR_USEC);
1075 }
1076 rx_lat = MS(reg, AR_USEC_RX_LAT);
1077 tx_lat = MS(reg, AR_USEC_TX_LAT);
1078
1079 slottime = ah->slottime;
1080 }
1081
1082 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1083 slottime += 3 * ah->coverage_class;
1084 acktimeout = slottime + sifstime + ack_offset;
1085 ctstimeout = acktimeout;
1086
1087 /*
1088 * Workaround for early ACK timeouts, add an offset to match the
1089 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1090 * This was initially only meant to work around an issue with delayed
1091 * BA frames in some implementations, but it has been found to fix ACK
1092 * timeout issues in other cases as well.
1093 */
1094 if (IS_CHAN_2GHZ(chan) &&
1095 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1096 acktimeout += 64 - sifstime - ah->slottime;
1097 ctstimeout += 48 - sifstime - ah->slottime;
1098 }
1099
1100 if (ah->dynack.enabled) {
1101 acktimeout = ah->dynack.ackto;
1102 ctstimeout = acktimeout;
1103 slottime = (acktimeout - 3) / 2;
1104 } else {
1105 ah->dynack.ackto = acktimeout;
1106 }
1107
1108 ath9k_hw_set_sifs_time(ah, sifstime);
1109 ath9k_hw_setslottime(ah, slottime);
1110 ath9k_hw_set_ack_timeout(ah, acktimeout);
1111 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1112 if (ah->globaltxtimeout != (u32) -1)
1113 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1114
1115 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1116 REG_RMW(ah, AR_USEC,
1117 (common->clockrate - 1) |
1118 SM(rx_lat, AR_USEC_RX_LAT) |
1119 SM(tx_lat, AR_USEC_TX_LAT),
1120 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1121
1122 }
1123 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1124
1125 void ath9k_hw_deinit(struct ath_hw *ah)
1126 {
1127 struct ath_common *common = ath9k_hw_common(ah);
1128
1129 if (common->state < ATH_HW_INITIALIZED)
1130 return;
1131
1132 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1133 }
1134 EXPORT_SYMBOL(ath9k_hw_deinit);
1135
1136 /*******/
1137 /* INI */
1138 /*******/
1139
1140 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1141 {
1142 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1143
1144 if (IS_CHAN_2GHZ(chan))
1145 ctl |= CTL_11G;
1146 else
1147 ctl |= CTL_11A;
1148
1149 return ctl;
1150 }
1151
1152 /****************************************/
1153 /* Reset and Channel Switching Routines */
1154 /****************************************/
1155
1156 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1157 {
1158 struct ath_common *common = ath9k_hw_common(ah);
1159 int txbuf_size;
1160
1161 ENABLE_REGWRITE_BUFFER(ah);
1162
1163 /*
1164 * set AHB_MODE not to do cacheline prefetches
1165 */
1166 if (!AR_SREV_9300_20_OR_LATER(ah))
1167 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1168
1169 /*
1170 * let mac dma reads be in 128 byte chunks
1171 */
1172 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1173
1174 REGWRITE_BUFFER_FLUSH(ah);
1175
1176 /*
1177 * Restore TX Trigger Level to its pre-reset value.
1178 * The initial value depends on whether aggregation is enabled, and is
1179 * adjusted whenever underruns are detected.
1180 */
1181 if (!AR_SREV_9300_20_OR_LATER(ah))
1182 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1183
1184 ENABLE_REGWRITE_BUFFER(ah);
1185
1186 /*
1187 * let mac dma writes be in 128 byte chunks
1188 */
1189 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1190
1191 /*
1192 * Setup receive FIFO threshold to hold off TX activities
1193 */
1194 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1195
1196 if (AR_SREV_9300_20_OR_LATER(ah)) {
1197 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1198 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1199
1200 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1201 ah->caps.rx_status_len);
1202 }
1203
1204 /*
1205 * reduce the number of usable entries in PCU TXBUF to avoid
1206 * wrap around issues.
1207 */
1208 if (AR_SREV_9285(ah)) {
1209 /* For AR9285 the number of Fifos are reduced to half.
1210 * So set the usable tx buf size also to half to
1211 * avoid data/delimiter underruns
1212 */
1213 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1214 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1215 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1216 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1217 } else {
1218 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1219 }
1220
1221 if (!AR_SREV_9271(ah))
1222 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1223
1224 REGWRITE_BUFFER_FLUSH(ah);
1225
1226 if (AR_SREV_9300_20_OR_LATER(ah))
1227 ath9k_hw_reset_txstatus_ring(ah);
1228 }
1229
1230 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1231 {
1232 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1233 u32 set = AR_STA_ID1_KSRCH_MODE;
1234
1235 ENABLE_REG_RMW_BUFFER(ah);
1236 switch (opmode) {
1237 case NL80211_IFTYPE_ADHOC:
1238 if (!AR_SREV_9340_13(ah)) {
1239 set |= AR_STA_ID1_ADHOC;
1240 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1241 break;
1242 }
1243 /* fall through */
1244 case NL80211_IFTYPE_MESH_POINT:
1245 case NL80211_IFTYPE_AP:
1246 set |= AR_STA_ID1_STA_AP;
1247 /* fall through */
1248 case NL80211_IFTYPE_STATION:
1249 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1250 break;
1251 default:
1252 if (!ah->is_monitoring)
1253 set = 0;
1254 break;
1255 }
1256 REG_RMW(ah, AR_STA_ID1, set, mask);
1257 REG_RMW_BUFFER_FLUSH(ah);
1258 }
1259
1260 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1261 u32 *coef_mantissa, u32 *coef_exponent)
1262 {
1263 u32 coef_exp, coef_man;
1264
1265 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1266 if ((coef_scaled >> coef_exp) & 0x1)
1267 break;
1268
1269 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1270
1271 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1272
1273 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1274 *coef_exponent = coef_exp - 16;
1275 }
1276
1277 /* AR9330 WAR:
1278 * call external reset function to reset WMAC if:
1279 * - doing a cold reset
1280 * - we have pending frames in the TX queues.
1281 */
1282 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1283 {
1284 int i, npend = 0;
1285
1286 for (i = 0; i < AR_NUM_QCU; i++) {
1287 npend = ath9k_hw_numtxpending(ah, i);
1288 if (npend)
1289 break;
1290 }
1291
1292 if (ah->external_reset &&
1293 (npend || type == ATH9K_RESET_COLD)) {
1294 int reset_err = 0;
1295
1296 ath_dbg(ath9k_hw_common(ah), RESET,
1297 "reset MAC via external reset\n");
1298
1299 reset_err = ah->external_reset();
1300 if (reset_err) {
1301 ath_err(ath9k_hw_common(ah),
1302 "External reset failed, err=%d\n",
1303 reset_err);
1304 return false;
1305 }
1306
1307 REG_WRITE(ah, AR_RTC_RESET, 1);
1308 }
1309
1310 return true;
1311 }
1312
1313 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1314 {
1315 u32 rst_flags;
1316 u32 tmpReg;
1317
1318 if (AR_SREV_9100(ah)) {
1319 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1320 AR_RTC_DERIVED_CLK_PERIOD, 1);
1321 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1322 }
1323
1324 ENABLE_REGWRITE_BUFFER(ah);
1325
1326 if (AR_SREV_9300_20_OR_LATER(ah)) {
1327 REG_WRITE(ah, AR_WA, ah->WARegVal);
1328 udelay(10);
1329 }
1330
1331 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1332 AR_RTC_FORCE_WAKE_ON_INT);
1333
1334 if (AR_SREV_9100(ah)) {
1335 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1336 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1337 } else {
1338 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1339 if (AR_SREV_9340(ah))
1340 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1341 else
1342 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1343 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1344
1345 if (tmpReg) {
1346 u32 val;
1347 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1348
1349 val = AR_RC_HOSTIF;
1350 if (!AR_SREV_9300_20_OR_LATER(ah))
1351 val |= AR_RC_AHB;
1352 REG_WRITE(ah, AR_RC, val);
1353
1354 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1355 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1356
1357 rst_flags = AR_RTC_RC_MAC_WARM;
1358 if (type == ATH9K_RESET_COLD)
1359 rst_flags |= AR_RTC_RC_MAC_COLD;
1360 }
1361
1362 if (AR_SREV_9330(ah)) {
1363 if (!ath9k_hw_ar9330_reset_war(ah, type))
1364 return false;
1365 }
1366
1367 if (ath9k_hw_mci_is_enabled(ah))
1368 ar9003_mci_check_gpm_offset(ah);
1369
1370 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1371
1372 REGWRITE_BUFFER_FLUSH(ah);
1373
1374 if (AR_SREV_9300_20_OR_LATER(ah))
1375 udelay(50);
1376 else if (AR_SREV_9100(ah))
1377 mdelay(10);
1378 else
1379 udelay(100);
1380
1381 REG_WRITE(ah, AR_RTC_RC, 0);
1382 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1383 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1384 return false;
1385 }
1386
1387 if (!AR_SREV_9100(ah))
1388 REG_WRITE(ah, AR_RC, 0);
1389
1390 if (AR_SREV_9100(ah))
1391 udelay(50);
1392
1393 return true;
1394 }
1395
1396 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1397 {
1398 ENABLE_REGWRITE_BUFFER(ah);
1399
1400 if (AR_SREV_9300_20_OR_LATER(ah)) {
1401 REG_WRITE(ah, AR_WA, ah->WARegVal);
1402 udelay(10);
1403 }
1404
1405 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1406 AR_RTC_FORCE_WAKE_ON_INT);
1407
1408 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1409 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1410
1411 REG_WRITE(ah, AR_RTC_RESET, 0);
1412
1413 REGWRITE_BUFFER_FLUSH(ah);
1414
1415 udelay(2);
1416
1417 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1418 REG_WRITE(ah, AR_RC, 0);
1419
1420 REG_WRITE(ah, AR_RTC_RESET, 1);
1421
1422 if (!ath9k_hw_wait(ah,
1423 AR_RTC_STATUS,
1424 AR_RTC_STATUS_M,
1425 AR_RTC_STATUS_ON,
1426 AH_WAIT_TIMEOUT)) {
1427 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1428 return false;
1429 }
1430
1431 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1432 }
1433
1434 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1435 {
1436 bool ret = false;
1437
1438 if (AR_SREV_9300_20_OR_LATER(ah)) {
1439 REG_WRITE(ah, AR_WA, ah->WARegVal);
1440 udelay(10);
1441 }
1442
1443 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1444 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1445
1446 if (!ah->reset_power_on)
1447 type = ATH9K_RESET_POWER_ON;
1448
1449 switch (type) {
1450 case ATH9K_RESET_POWER_ON:
1451 ret = ath9k_hw_set_reset_power_on(ah);
1452 if (ret)
1453 ah->reset_power_on = true;
1454 break;
1455 case ATH9K_RESET_WARM:
1456 case ATH9K_RESET_COLD:
1457 ret = ath9k_hw_set_reset(ah, type);
1458 break;
1459 default:
1460 break;
1461 }
1462
1463 return ret;
1464 }
1465
1466 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1467 struct ath9k_channel *chan)
1468 {
1469 int reset_type = ATH9K_RESET_WARM;
1470
1471 if (AR_SREV_9280(ah)) {
1472 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1473 reset_type = ATH9K_RESET_POWER_ON;
1474 else
1475 reset_type = ATH9K_RESET_COLD;
1476 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1477 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1478 reset_type = ATH9K_RESET_COLD;
1479
1480 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1481 return false;
1482
1483 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1484 return false;
1485
1486 ah->chip_fullsleep = false;
1487
1488 if (AR_SREV_9330(ah))
1489 ar9003_hw_internal_regulator_apply(ah);
1490 ath9k_hw_init_pll(ah, chan);
1491
1492 return true;
1493 }
1494
1495 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1496 struct ath9k_channel *chan)
1497 {
1498 struct ath_common *common = ath9k_hw_common(ah);
1499 struct ath9k_hw_capabilities *pCap = &ah->caps;
1500 bool band_switch = false, mode_diff = false;
1501 u8 ini_reloaded = 0;
1502 u32 qnum;
1503 int r;
1504
1505 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1506 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1507 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1508 mode_diff = !!(flags_diff & ~CHANNEL_HT);
1509 }
1510
1511 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1512 if (ath9k_hw_numtxpending(ah, qnum)) {
1513 ath_dbg(common, QUEUE,
1514 "Transmit frames pending on queue %d\n", qnum);
1515 return false;
1516 }
1517 }
1518
1519 if (!ath9k_hw_rfbus_req(ah)) {
1520 ath_err(common, "Could not kill baseband RX\n");
1521 return false;
1522 }
1523
1524 if (band_switch || mode_diff) {
1525 ath9k_hw_mark_phy_inactive(ah);
1526 udelay(5);
1527
1528 if (band_switch)
1529 ath9k_hw_init_pll(ah, chan);
1530
1531 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1532 ath_err(common, "Failed to do fast channel change\n");
1533 return false;
1534 }
1535 }
1536
1537 ath9k_hw_set_channel_regs(ah, chan);
1538
1539 r = ath9k_hw_rf_set_freq(ah, chan);
1540 if (r) {
1541 ath_err(common, "Failed to set channel\n");
1542 return false;
1543 }
1544 ath9k_hw_set_clockrate(ah);
1545 ath9k_hw_apply_txpower(ah, chan, false);
1546
1547 ath9k_hw_set_delta_slope(ah, chan);
1548 ath9k_hw_spur_mitigate_freq(ah, chan);
1549
1550 if (band_switch || ini_reloaded)
1551 ah->eep_ops->set_board_values(ah, chan);
1552
1553 ath9k_hw_init_bb(ah, chan);
1554 ath9k_hw_rfbus_done(ah);
1555
1556 if (band_switch || ini_reloaded) {
1557 ah->ah_flags |= AH_FASTCC;
1558 ath9k_hw_init_cal(ah, chan);
1559 ah->ah_flags &= ~AH_FASTCC;
1560 }
1561
1562 return true;
1563 }
1564
1565 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1566 {
1567 u32 gpio_mask = ah->gpio_mask;
1568 int i;
1569
1570 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1571 if (!(gpio_mask & 1))
1572 continue;
1573
1574 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1575 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1576 }
1577 }
1578
1579 void ath9k_hw_check_nav(struct ath_hw *ah)
1580 {
1581 struct ath_common *common = ath9k_hw_common(ah);
1582 u32 val;
1583
1584 val = REG_READ(ah, AR_NAV);
1585 if (val != 0xdeadbeef && val > 0x7fff) {
1586 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1587 REG_WRITE(ah, AR_NAV, 0);
1588 }
1589 }
1590 EXPORT_SYMBOL(ath9k_hw_check_nav);
1591
1592 bool ath9k_hw_check_alive(struct ath_hw *ah)
1593 {
1594 int count = 50;
1595 u32 reg, last_val;
1596
1597 if (AR_SREV_9300(ah))
1598 return !ath9k_hw_detect_mac_hang(ah);
1599
1600 if (AR_SREV_9285_12_OR_LATER(ah))
1601 return true;
1602
1603 last_val = REG_READ(ah, AR_OBS_BUS_1);
1604 do {
1605 reg = REG_READ(ah, AR_OBS_BUS_1);
1606 if (reg != last_val)
1607 return true;
1608
1609 udelay(1);
1610 last_val = reg;
1611 if ((reg & 0x7E7FFFEF) == 0x00702400)
1612 continue;
1613
1614 switch (reg & 0x7E000B00) {
1615 case 0x1E000000:
1616 case 0x52000B00:
1617 case 0x18000B00:
1618 continue;
1619 default:
1620 return true;
1621 }
1622 } while (count-- > 0);
1623
1624 return false;
1625 }
1626 EXPORT_SYMBOL(ath9k_hw_check_alive);
1627
1628 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1629 {
1630 /* Setup MFP options for CCMP */
1631 if (AR_SREV_9280_20_OR_LATER(ah)) {
1632 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1633 * frames when constructing CCMP AAD. */
1634 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1635 0xc7ff);
1636 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1637 ah->sw_mgmt_crypto_tx = true;
1638 else
1639 ah->sw_mgmt_crypto_tx = false;
1640 ah->sw_mgmt_crypto_rx = false;
1641 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1642 /* Disable hardware crypto for management frames */
1643 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1644 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1645 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1646 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1647 ah->sw_mgmt_crypto_tx = true;
1648 ah->sw_mgmt_crypto_rx = true;
1649 } else {
1650 ah->sw_mgmt_crypto_tx = true;
1651 ah->sw_mgmt_crypto_rx = true;
1652 }
1653 }
1654
1655 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1656 u32 macStaId1, u32 saveDefAntenna)
1657 {
1658 struct ath_common *common = ath9k_hw_common(ah);
1659
1660 ENABLE_REGWRITE_BUFFER(ah);
1661
1662 REG_RMW(ah, AR_STA_ID1, macStaId1
1663 | AR_STA_ID1_RTS_USE_DEF
1664 | ah->sta_id1_defaults,
1665 ~AR_STA_ID1_SADH_MASK);
1666 ath_hw_setbssidmask(common);
1667 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1668 ath9k_hw_write_associd(ah);
1669 REG_WRITE(ah, AR_ISR, ~0);
1670 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1671
1672 REGWRITE_BUFFER_FLUSH(ah);
1673
1674 ath9k_hw_set_operating_mode(ah, ah->opmode);
1675 }
1676
1677 static void ath9k_hw_init_queues(struct ath_hw *ah)
1678 {
1679 int i;
1680
1681 ENABLE_REGWRITE_BUFFER(ah);
1682
1683 for (i = 0; i < AR_NUM_DCU; i++)
1684 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1685
1686 REGWRITE_BUFFER_FLUSH(ah);
1687
1688 ah->intr_txqs = 0;
1689 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1690 ath9k_hw_resettxqueue(ah, i);
1691 }
1692
1693 /*
1694 * For big endian systems turn on swapping for descriptors
1695 */
1696 static void ath9k_hw_init_desc(struct ath_hw *ah)
1697 {
1698 struct ath_common *common = ath9k_hw_common(ah);
1699
1700 if (AR_SREV_9100(ah)) {
1701 u32 mask;
1702 mask = REG_READ(ah, AR_CFG);
1703 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1704 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1705 mask);
1706 } else {
1707 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1708 REG_WRITE(ah, AR_CFG, mask);
1709 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1710 REG_READ(ah, AR_CFG));
1711 }
1712 } else {
1713 if (common->bus_ops->ath_bus_type == ATH_USB) {
1714 /* Configure AR9271 target WLAN */
1715 if (AR_SREV_9271(ah))
1716 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1717 else
1718 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1719 }
1720 #ifdef __BIG_ENDIAN
1721 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1722 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1723 AR_SREV_9561(ah))
1724 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1725 else
1726 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1727 #endif
1728 }
1729 }
1730
1731 /*
1732 * Fast channel change:
1733 * (Change synthesizer based on channel freq without resetting chip)
1734 */
1735 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1736 {
1737 struct ath_common *common = ath9k_hw_common(ah);
1738 struct ath9k_hw_capabilities *pCap = &ah->caps;
1739 int ret;
1740
1741 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1742 goto fail;
1743
1744 if (ah->chip_fullsleep)
1745 goto fail;
1746
1747 if (!ah->curchan)
1748 goto fail;
1749
1750 if (chan->channel == ah->curchan->channel)
1751 goto fail;
1752
1753 if ((ah->curchan->channelFlags | chan->channelFlags) &
1754 (CHANNEL_HALF | CHANNEL_QUARTER))
1755 goto fail;
1756
1757 /*
1758 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1759 */
1760 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1761 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1762 goto fail;
1763
1764 if (!ath9k_hw_check_alive(ah))
1765 goto fail;
1766
1767 /*
1768 * For AR9462, make sure that calibration data for
1769 * re-using are present.
1770 */
1771 if (AR_SREV_9462(ah) && (ah->caldata &&
1772 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1773 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1774 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1775 goto fail;
1776
1777 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1778 ah->curchan->channel, chan->channel);
1779
1780 ret = ath9k_hw_channel_change(ah, chan);
1781 if (!ret)
1782 goto fail;
1783
1784 if (ath9k_hw_mci_is_enabled(ah))
1785 ar9003_mci_2g5g_switch(ah, false);
1786
1787 ath9k_hw_loadnf(ah, ah->curchan);
1788 ath9k_hw_start_nfcal(ah, true);
1789
1790 if (AR_SREV_9271(ah))
1791 ar9002_hw_load_ani_reg(ah, chan);
1792
1793 return 0;
1794 fail:
1795 return -EINVAL;
1796 }
1797
1798 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1799 {
1800 struct timespec ts;
1801 s64 usec;
1802
1803 if (!cur) {
1804 getrawmonotonic(&ts);
1805 cur = &ts;
1806 }
1807
1808 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1809 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1810
1811 return (u32) usec;
1812 }
1813 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1814
1815 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1816 struct ath9k_hw_cal_data *caldata, bool fastcc)
1817 {
1818 struct ath_common *common = ath9k_hw_common(ah);
1819 u32 saveLedState;
1820 u32 saveDefAntenna;
1821 u32 macStaId1;
1822 u64 tsf = 0;
1823 s64 usec = 0;
1824 int r;
1825 bool start_mci_reset = false;
1826 bool save_fullsleep = ah->chip_fullsleep;
1827
1828 if (ath9k_hw_mci_is_enabled(ah)) {
1829 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1830 if (start_mci_reset)
1831 return 0;
1832 }
1833
1834 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1835 return -EIO;
1836
1837 if (ah->curchan && !ah->chip_fullsleep)
1838 ath9k_hw_getnf(ah, ah->curchan);
1839
1840 ah->caldata = caldata;
1841 if (caldata && (chan->channel != caldata->channel ||
1842 chan->channelFlags != caldata->channelFlags)) {
1843 /* Operating channel changed, reset channel calibration data */
1844 memset(caldata, 0, sizeof(*caldata));
1845 ath9k_init_nfcal_hist_buffer(ah, chan);
1846 } else if (caldata) {
1847 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1848 }
1849 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1850
1851 if (fastcc) {
1852 r = ath9k_hw_do_fastcc(ah, chan);
1853 if (!r)
1854 return r;
1855 }
1856
1857 if (ath9k_hw_mci_is_enabled(ah))
1858 ar9003_mci_stop_bt(ah, save_fullsleep);
1859
1860 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1861 if (saveDefAntenna == 0)
1862 saveDefAntenna = 1;
1863
1864 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1865
1866 /* Save TSF before chip reset, a cold reset clears it */
1867 tsf = ath9k_hw_gettsf64(ah);
1868 usec = ktime_to_us(ktime_get_raw());
1869
1870 saveLedState = REG_READ(ah, AR_CFG_LED) &
1871 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1872 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1873
1874 ath9k_hw_mark_phy_inactive(ah);
1875
1876 ah->paprd_table_write_done = false;
1877
1878 /* Only required on the first reset */
1879 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1880 REG_WRITE(ah,
1881 AR9271_RESET_POWER_DOWN_CONTROL,
1882 AR9271_RADIO_RF_RST);
1883 udelay(50);
1884 }
1885
1886 if (!ath9k_hw_chip_reset(ah, chan)) {
1887 ath_err(common, "Chip reset failed\n");
1888 return -EINVAL;
1889 }
1890
1891 /* Only required on the first reset */
1892 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1893 ah->htc_reset_init = false;
1894 REG_WRITE(ah,
1895 AR9271_RESET_POWER_DOWN_CONTROL,
1896 AR9271_GATE_MAC_CTL);
1897 udelay(50);
1898 }
1899
1900 /* Restore TSF */
1901 usec = ktime_to_us(ktime_get_raw()) - usec;
1902 ath9k_hw_settsf64(ah, tsf + usec);
1903
1904 if (AR_SREV_9280_20_OR_LATER(ah))
1905 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1906
1907 if (!AR_SREV_9300_20_OR_LATER(ah))
1908 ar9002_hw_enable_async_fifo(ah);
1909
1910 r = ath9k_hw_process_ini(ah, chan);
1911 if (r)
1912 return r;
1913
1914 ath9k_hw_set_rfmode(ah, chan);
1915
1916 if (ath9k_hw_mci_is_enabled(ah))
1917 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1918
1919 /*
1920 * Some AR91xx SoC devices frequently fail to accept TSF writes
1921 * right after the chip reset. When that happens, write a new
1922 * value after the initvals have been applied, with an offset
1923 * based on measured time difference
1924 */
1925 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1926 tsf += 1500;
1927 ath9k_hw_settsf64(ah, tsf);
1928 }
1929
1930 ath9k_hw_init_mfp(ah);
1931
1932 ath9k_hw_set_delta_slope(ah, chan);
1933 ath9k_hw_spur_mitigate_freq(ah, chan);
1934 ah->eep_ops->set_board_values(ah, chan);
1935
1936 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1937
1938 r = ath9k_hw_rf_set_freq(ah, chan);
1939 if (r)
1940 return r;
1941
1942 ath9k_hw_set_clockrate(ah);
1943
1944 ath9k_hw_init_queues(ah);
1945 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1946 ath9k_hw_ani_cache_ini_regs(ah);
1947 ath9k_hw_init_qos(ah);
1948
1949 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1950 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1951
1952 ath9k_hw_init_global_settings(ah);
1953
1954 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1955 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1956 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1957 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1958 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1959 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1960 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1961 }
1962
1963 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1964
1965 ath9k_hw_set_dma(ah);
1966
1967 if (!ath9k_hw_mci_is_enabled(ah))
1968 REG_WRITE(ah, AR_OBS, 8);
1969
1970 ENABLE_REG_RMW_BUFFER(ah);
1971 if (ah->config.rx_intr_mitigation) {
1972 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1973 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
1974 }
1975
1976 if (ah->config.tx_intr_mitigation) {
1977 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1978 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1979 }
1980 REG_RMW_BUFFER_FLUSH(ah);
1981
1982 ath9k_hw_init_bb(ah, chan);
1983
1984 if (caldata) {
1985 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1986 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
1987 }
1988 if (!ath9k_hw_init_cal(ah, chan))
1989 return -EIO;
1990
1991 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1992 return -EIO;
1993
1994 ENABLE_REGWRITE_BUFFER(ah);
1995
1996 ath9k_hw_restore_chainmask(ah);
1997 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1998
1999 REGWRITE_BUFFER_FLUSH(ah);
2000
2001 ath9k_hw_gen_timer_start_tsf2(ah);
2002
2003 ath9k_hw_init_desc(ah);
2004
2005 if (ath9k_hw_btcoex_is_enabled(ah))
2006 ath9k_hw_btcoex_enable(ah);
2007
2008 if (ath9k_hw_mci_is_enabled(ah))
2009 ar9003_mci_check_bt(ah);
2010
2011 if (AR_SREV_9300_20_OR_LATER(ah)) {
2012 ath9k_hw_loadnf(ah, chan);
2013 ath9k_hw_start_nfcal(ah, true);
2014 }
2015
2016 if (AR_SREV_9300_20_OR_LATER(ah))
2017 ar9003_hw_bb_watchdog_config(ah);
2018
2019 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
2020 ar9003_hw_disable_phy_restart(ah);
2021
2022 ath9k_hw_apply_gpio_override(ah);
2023
2024 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2025 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2026
2027 if (ah->hw->conf.radar_enabled) {
2028 /* set HW specific DFS configuration */
2029 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
2030 ath9k_hw_set_radar_params(ah);
2031 }
2032
2033 return 0;
2034 }
2035 EXPORT_SYMBOL(ath9k_hw_reset);
2036
2037 /******************************/
2038 /* Power Management (Chipset) */
2039 /******************************/
2040
2041 /*
2042 * Notify Power Mgt is disabled in self-generated frames.
2043 * If requested, force chip to sleep.
2044 */
2045 static void ath9k_set_power_sleep(struct ath_hw *ah)
2046 {
2047 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2048
2049 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2050 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2051 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2052 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2053 /* xxx Required for WLAN only case ? */
2054 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2055 udelay(100);
2056 }
2057
2058 /*
2059 * Clear the RTC force wake bit to allow the
2060 * mac to go to sleep.
2061 */
2062 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2063
2064 if (ath9k_hw_mci_is_enabled(ah))
2065 udelay(100);
2066
2067 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2068 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2069
2070 /* Shutdown chip. Active low */
2071 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2072 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2073 udelay(2);
2074 }
2075
2076 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2077 if (AR_SREV_9300_20_OR_LATER(ah))
2078 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2079 }
2080
2081 /*
2082 * Notify Power Management is enabled in self-generating
2083 * frames. If request, set power mode of chip to
2084 * auto/normal. Duration in units of 128us (1/8 TU).
2085 */
2086 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2087 {
2088 struct ath9k_hw_capabilities *pCap = &ah->caps;
2089
2090 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2091
2092 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2093 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2094 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2095 AR_RTC_FORCE_WAKE_ON_INT);
2096 } else {
2097
2098 /* When chip goes into network sleep, it could be waken
2099 * up by MCI_INT interrupt caused by BT's HW messages
2100 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2101 * rate (~100us). This will cause chip to leave and
2102 * re-enter network sleep mode frequently, which in
2103 * consequence will have WLAN MCI HW to generate lots of
2104 * SYS_WAKING and SYS_SLEEPING messages which will make
2105 * BT CPU to busy to process.
2106 */
2107 if (ath9k_hw_mci_is_enabled(ah))
2108 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2109 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2110 /*
2111 * Clear the RTC force wake bit to allow the
2112 * mac to go to sleep.
2113 */
2114 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2115
2116 if (ath9k_hw_mci_is_enabled(ah))
2117 udelay(30);
2118 }
2119
2120 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2121 if (AR_SREV_9300_20_OR_LATER(ah))
2122 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2123 }
2124
2125 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2126 {
2127 u32 val;
2128 int i;
2129
2130 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2131 if (AR_SREV_9300_20_OR_LATER(ah)) {
2132 REG_WRITE(ah, AR_WA, ah->WARegVal);
2133 udelay(10);
2134 }
2135
2136 if ((REG_READ(ah, AR_RTC_STATUS) &
2137 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2138 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2139 return false;
2140 }
2141 if (!AR_SREV_9300_20_OR_LATER(ah))
2142 ath9k_hw_init_pll(ah, NULL);
2143 }
2144 if (AR_SREV_9100(ah))
2145 REG_SET_BIT(ah, AR_RTC_RESET,
2146 AR_RTC_RESET_EN);
2147
2148 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2149 AR_RTC_FORCE_WAKE_EN);
2150 if (AR_SREV_9100(ah))
2151 mdelay(10);
2152 else
2153 udelay(50);
2154
2155 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2156 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2157 if (val == AR_RTC_STATUS_ON)
2158 break;
2159 udelay(50);
2160 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2161 AR_RTC_FORCE_WAKE_EN);
2162 }
2163 if (i == 0) {
2164 ath_err(ath9k_hw_common(ah),
2165 "Failed to wakeup in %uus\n",
2166 POWER_UP_TIME / 20);
2167 return false;
2168 }
2169
2170 if (ath9k_hw_mci_is_enabled(ah))
2171 ar9003_mci_set_power_awake(ah);
2172
2173 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2174
2175 return true;
2176 }
2177
2178 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2179 {
2180 struct ath_common *common = ath9k_hw_common(ah);
2181 int status = true;
2182 static const char *modes[] = {
2183 "AWAKE",
2184 "FULL-SLEEP",
2185 "NETWORK SLEEP",
2186 "UNDEFINED"
2187 };
2188
2189 if (ah->power_mode == mode)
2190 return status;
2191
2192 ath_dbg(common, RESET, "%s -> %s\n",
2193 modes[ah->power_mode], modes[mode]);
2194
2195 switch (mode) {
2196 case ATH9K_PM_AWAKE:
2197 status = ath9k_hw_set_power_awake(ah);
2198 break;
2199 case ATH9K_PM_FULL_SLEEP:
2200 if (ath9k_hw_mci_is_enabled(ah))
2201 ar9003_mci_set_full_sleep(ah);
2202
2203 ath9k_set_power_sleep(ah);
2204 ah->chip_fullsleep = true;
2205 break;
2206 case ATH9K_PM_NETWORK_SLEEP:
2207 ath9k_set_power_network_sleep(ah);
2208 break;
2209 default:
2210 ath_err(common, "Unknown power mode %u\n", mode);
2211 return false;
2212 }
2213 ah->power_mode = mode;
2214
2215 /*
2216 * XXX: If this warning never comes up after a while then
2217 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2218 * ath9k_hw_setpower() return type void.
2219 */
2220
2221 if (!(ah->ah_flags & AH_UNPLUGGED))
2222 ATH_DBG_WARN_ON_ONCE(!status);
2223
2224 return status;
2225 }
2226 EXPORT_SYMBOL(ath9k_hw_setpower);
2227
2228 /*******************/
2229 /* Beacon Handling */
2230 /*******************/
2231
2232 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2233 {
2234 int flags = 0;
2235
2236 ENABLE_REGWRITE_BUFFER(ah);
2237
2238 switch (ah->opmode) {
2239 case NL80211_IFTYPE_ADHOC:
2240 REG_SET_BIT(ah, AR_TXCFG,
2241 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2242 case NL80211_IFTYPE_MESH_POINT:
2243 case NL80211_IFTYPE_AP:
2244 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2245 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2246 TU_TO_USEC(ah->config.dma_beacon_response_time));
2247 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2248 TU_TO_USEC(ah->config.sw_beacon_response_time));
2249 flags |=
2250 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2251 break;
2252 default:
2253 ath_dbg(ath9k_hw_common(ah), BEACON,
2254 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2255 return;
2256 break;
2257 }
2258
2259 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2260 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2261 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2262
2263 REGWRITE_BUFFER_FLUSH(ah);
2264
2265 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2266 }
2267 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2268
2269 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2270 const struct ath9k_beacon_state *bs)
2271 {
2272 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2273 struct ath9k_hw_capabilities *pCap = &ah->caps;
2274 struct ath_common *common = ath9k_hw_common(ah);
2275
2276 ENABLE_REGWRITE_BUFFER(ah);
2277
2278 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2279 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2280 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2281
2282 REGWRITE_BUFFER_FLUSH(ah);
2283
2284 REG_RMW_FIELD(ah, AR_RSSI_THR,
2285 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2286
2287 beaconintval = bs->bs_intval;
2288
2289 if (bs->bs_sleepduration > beaconintval)
2290 beaconintval = bs->bs_sleepduration;
2291
2292 dtimperiod = bs->bs_dtimperiod;
2293 if (bs->bs_sleepduration > dtimperiod)
2294 dtimperiod = bs->bs_sleepduration;
2295
2296 if (beaconintval == dtimperiod)
2297 nextTbtt = bs->bs_nextdtim;
2298 else
2299 nextTbtt = bs->bs_nexttbtt;
2300
2301 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2302 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2303 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2304 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2305
2306 ENABLE_REGWRITE_BUFFER(ah);
2307
2308 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2309 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2310
2311 REG_WRITE(ah, AR_SLEEP1,
2312 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2313 | AR_SLEEP1_ASSUME_DTIM);
2314
2315 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2316 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2317 else
2318 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2319
2320 REG_WRITE(ah, AR_SLEEP2,
2321 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2322
2323 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2324 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2325
2326 REGWRITE_BUFFER_FLUSH(ah);
2327
2328 REG_SET_BIT(ah, AR_TIMER_MODE,
2329 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2330 AR_DTIM_TIMER_EN);
2331
2332 /* TSF Out of Range Threshold */
2333 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2334 }
2335 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2336
2337 /*******************/
2338 /* HW Capabilities */
2339 /*******************/
2340
2341 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2342 {
2343 eeprom_chainmask &= chip_chainmask;
2344 if (eeprom_chainmask)
2345 return eeprom_chainmask;
2346 else
2347 return chip_chainmask;
2348 }
2349
2350 /**
2351 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2352 * @ah: the atheros hardware data structure
2353 *
2354 * We enable DFS support upstream on chipsets which have passed a series
2355 * of tests. The testing requirements are going to be documented. Desired
2356 * test requirements are documented at:
2357 *
2358 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2359 *
2360 * Once a new chipset gets properly tested an individual commit can be used
2361 * to document the testing for DFS for that chipset.
2362 */
2363 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2364 {
2365
2366 switch (ah->hw_version.macVersion) {
2367 /* for temporary testing DFS with 9280 */
2368 case AR_SREV_VERSION_9280:
2369 /* AR9580 will likely be our first target to get testing on */
2370 case AR_SREV_VERSION_9580:
2371 return true;
2372 default:
2373 return false;
2374 }
2375 }
2376
2377 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2378 {
2379 struct ath9k_hw_capabilities *pCap = &ah->caps;
2380 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2381 struct ath_common *common = ath9k_hw_common(ah);
2382
2383 u16 eeval;
2384 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2385
2386 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2387 regulatory->current_rd = eeval;
2388
2389 if (ah->opmode != NL80211_IFTYPE_AP &&
2390 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2391 if (regulatory->current_rd == 0x64 ||
2392 regulatory->current_rd == 0x65)
2393 regulatory->current_rd += 5;
2394 else if (regulatory->current_rd == 0x41)
2395 regulatory->current_rd = 0x43;
2396 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2397 regulatory->current_rd);
2398 }
2399
2400 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2401
2402 if (eeval & AR5416_OPFLAGS_11A) {
2403 if (ah->disable_5ghz)
2404 ath_warn(common, "disabling 5GHz band\n");
2405 else
2406 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2407 }
2408
2409 if (eeval & AR5416_OPFLAGS_11G) {
2410 if (ah->disable_2ghz)
2411 ath_warn(common, "disabling 2GHz band\n");
2412 else
2413 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2414 }
2415
2416 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2417 ath_err(common, "both bands are disabled\n");
2418 return -EINVAL;
2419 }
2420
2421 if (AR_SREV_9485(ah) ||
2422 AR_SREV_9285(ah) ||
2423 AR_SREV_9330(ah) ||
2424 AR_SREV_9565(ah))
2425 pCap->chip_chainmask = 1;
2426 else if (!AR_SREV_9280_20_OR_LATER(ah))
2427 pCap->chip_chainmask = 7;
2428 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2429 AR_SREV_9340(ah) ||
2430 AR_SREV_9462(ah) ||
2431 AR_SREV_9531(ah))
2432 pCap->chip_chainmask = 3;
2433 else
2434 pCap->chip_chainmask = 7;
2435
2436 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2437 /*
2438 * For AR9271 we will temporarilly uses the rx chainmax as read from
2439 * the EEPROM.
2440 */
2441 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2442 !(eeval & AR5416_OPFLAGS_11A) &&
2443 !(AR_SREV_9271(ah)))
2444 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2445 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2446 else if (AR_SREV_9100(ah))
2447 pCap->rx_chainmask = 0x7;
2448 else
2449 /* Use rx_chainmask from EEPROM. */
2450 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2451
2452 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2453 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2454 ah->txchainmask = pCap->tx_chainmask;
2455 ah->rxchainmask = pCap->rx_chainmask;
2456
2457 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2458
2459 /* enable key search for every frame in an aggregate */
2460 if (AR_SREV_9300_20_OR_LATER(ah))
2461 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2462
2463 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2464
2465 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2466 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2467 else
2468 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2469
2470 if (AR_SREV_9271(ah))
2471 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2472 else if (AR_DEVID_7010(ah))
2473 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2474 else if (AR_SREV_9300_20_OR_LATER(ah))
2475 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2476 else if (AR_SREV_9287_11_OR_LATER(ah))
2477 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2478 else if (AR_SREV_9285_12_OR_LATER(ah))
2479 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2480 else if (AR_SREV_9280_20_OR_LATER(ah))
2481 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2482 else
2483 pCap->num_gpio_pins = AR_NUM_GPIO;
2484
2485 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2486 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2487 else
2488 pCap->rts_aggr_limit = (8 * 1024);
2489
2490 #ifdef CONFIG_ATH9K_RFKILL
2491 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2492 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2493 ah->rfkill_gpio =
2494 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2495 ah->rfkill_polarity =
2496 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2497
2498 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2499 }
2500 #endif
2501 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2502 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2503 else
2504 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2505
2506 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2507 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2508 else
2509 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2510
2511 if (AR_SREV_9300_20_OR_LATER(ah)) {
2512 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2513 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2514 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
2515 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2516
2517 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2518 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2519 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2520 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2521 pCap->txs_len = sizeof(struct ar9003_txs);
2522 } else {
2523 pCap->tx_desc_len = sizeof(struct ath_desc);
2524 if (AR_SREV_9280_20(ah))
2525 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2526 }
2527
2528 if (AR_SREV_9300_20_OR_LATER(ah))
2529 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2530
2531 if (AR_SREV_9561(ah))
2532 ah->ent_mode = 0x3BDA000;
2533 else if (AR_SREV_9300_20_OR_LATER(ah))
2534 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2535
2536 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2537 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2538
2539 if (AR_SREV_9285(ah)) {
2540 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2541 ant_div_ctl1 =
2542 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2543 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2544 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2545 ath_info(common, "Enable LNA combining\n");
2546 }
2547 }
2548 }
2549
2550 if (AR_SREV_9300_20_OR_LATER(ah)) {
2551 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2552 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2553 }
2554
2555 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2556 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2557 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2558 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2559 ath_info(common, "Enable LNA combining\n");
2560 }
2561 }
2562
2563 if (ath9k_hw_dfs_tested(ah))
2564 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2565
2566 tx_chainmask = pCap->tx_chainmask;
2567 rx_chainmask = pCap->rx_chainmask;
2568 while (tx_chainmask || rx_chainmask) {
2569 if (tx_chainmask & BIT(0))
2570 pCap->max_txchains++;
2571 if (rx_chainmask & BIT(0))
2572 pCap->max_rxchains++;
2573
2574 tx_chainmask >>= 1;
2575 rx_chainmask >>= 1;
2576 }
2577
2578 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2579 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2580 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2581
2582 if (AR_SREV_9462_20_OR_LATER(ah))
2583 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2584 }
2585
2586 if (AR_SREV_9300_20_OR_LATER(ah) &&
2587 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2588 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2589
2590 #ifdef CONFIG_ATH9K_WOW
2591 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2592 ah->wow.max_patterns = MAX_NUM_PATTERN;
2593 else
2594 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2595 #endif
2596
2597 return 0;
2598 }
2599
2600 /****************************/
2601 /* GPIO / RFKILL / Antennae */
2602 /****************************/
2603
2604 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2605 u32 gpio, u32 type)
2606 {
2607 int addr;
2608 u32 gpio_shift, tmp;
2609
2610 if (gpio > 11)
2611 addr = AR_GPIO_OUTPUT_MUX3;
2612 else if (gpio > 5)
2613 addr = AR_GPIO_OUTPUT_MUX2;
2614 else
2615 addr = AR_GPIO_OUTPUT_MUX1;
2616
2617 gpio_shift = (gpio % 6) * 5;
2618
2619 if (AR_SREV_9280_20_OR_LATER(ah)
2620 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2621 REG_RMW(ah, addr, (type << gpio_shift),
2622 (0x1f << gpio_shift));
2623 } else {
2624 tmp = REG_READ(ah, addr);
2625 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2626 tmp &= ~(0x1f << gpio_shift);
2627 tmp |= (type << gpio_shift);
2628 REG_WRITE(ah, addr, tmp);
2629 }
2630 }
2631
2632 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2633 {
2634 u32 gpio_shift;
2635
2636 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2637
2638 if (AR_DEVID_7010(ah)) {
2639 gpio_shift = gpio;
2640 REG_RMW(ah, AR7010_GPIO_OE,
2641 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2642 (AR7010_GPIO_OE_MASK << gpio_shift));
2643 return;
2644 }
2645
2646 gpio_shift = gpio << 1;
2647 REG_RMW(ah,
2648 AR_GPIO_OE_OUT,
2649 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2650 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2651 }
2652 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2653
2654 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2655 {
2656 #define MS_REG_READ(x, y) \
2657 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2658
2659 if (gpio >= ah->caps.num_gpio_pins)
2660 return 0xffffffff;
2661
2662 if (AR_DEVID_7010(ah)) {
2663 u32 val;
2664 val = REG_READ(ah, AR7010_GPIO_IN);
2665 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2666 } else if (AR_SREV_9300_20_OR_LATER(ah))
2667 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2668 AR_GPIO_BIT(gpio)) != 0;
2669 else if (AR_SREV_9271(ah))
2670 return MS_REG_READ(AR9271, gpio) != 0;
2671 else if (AR_SREV_9287_11_OR_LATER(ah))
2672 return MS_REG_READ(AR9287, gpio) != 0;
2673 else if (AR_SREV_9285_12_OR_LATER(ah))
2674 return MS_REG_READ(AR9285, gpio) != 0;
2675 else if (AR_SREV_9280_20_OR_LATER(ah))
2676 return MS_REG_READ(AR928X, gpio) != 0;
2677 else
2678 return MS_REG_READ(AR, gpio) != 0;
2679 }
2680 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2681
2682 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2683 u32 ah_signal_type)
2684 {
2685 u32 gpio_shift;
2686
2687 if (AR_DEVID_7010(ah)) {
2688 gpio_shift = gpio;
2689 REG_RMW(ah, AR7010_GPIO_OE,
2690 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2691 (AR7010_GPIO_OE_MASK << gpio_shift));
2692 return;
2693 }
2694
2695 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2696 gpio_shift = 2 * gpio;
2697 REG_RMW(ah,
2698 AR_GPIO_OE_OUT,
2699 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2700 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2701 }
2702 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2703
2704 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2705 {
2706 if (AR_DEVID_7010(ah)) {
2707 val = val ? 0 : 1;
2708 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2709 AR_GPIO_BIT(gpio));
2710 return;
2711 }
2712
2713 if (AR_SREV_9271(ah))
2714 val = ~val;
2715
2716 if ((1 << gpio) & AR_GPIO_OE_OUT_MASK)
2717 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2718 AR_GPIO_BIT(gpio));
2719 else
2720 gpio_set_value(gpio, val & 1);
2721 }
2722 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2723
2724 void ath9k_hw_request_gpio(struct ath_hw *ah, u32 gpio, const char *label)
2725 {
2726 if (gpio >= ah->caps.num_gpio_pins)
2727 return;
2728
2729 gpio_request_one(gpio, GPIOF_DIR_OUT | GPIOF_INIT_LOW, label);
2730 }
2731 EXPORT_SYMBOL(ath9k_hw_request_gpio);
2732
2733 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2734 {
2735 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2736 }
2737 EXPORT_SYMBOL(ath9k_hw_setantenna);
2738
2739 /*********************/
2740 /* General Operation */
2741 /*********************/
2742
2743 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2744 {
2745 u32 bits = REG_READ(ah, AR_RX_FILTER);
2746 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2747
2748 if (phybits & AR_PHY_ERR_RADAR)
2749 bits |= ATH9K_RX_FILTER_PHYRADAR;
2750 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2751 bits |= ATH9K_RX_FILTER_PHYERR;
2752
2753 return bits;
2754 }
2755 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2756
2757 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2758 {
2759 u32 phybits;
2760
2761 ENABLE_REGWRITE_BUFFER(ah);
2762
2763 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2764 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2765
2766 REG_WRITE(ah, AR_RX_FILTER, bits);
2767
2768 phybits = 0;
2769 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2770 phybits |= AR_PHY_ERR_RADAR;
2771 if (bits & ATH9K_RX_FILTER_PHYERR)
2772 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2773 REG_WRITE(ah, AR_PHY_ERR, phybits);
2774
2775 if (phybits)
2776 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2777 else
2778 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2779
2780 REGWRITE_BUFFER_FLUSH(ah);
2781 }
2782 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2783
2784 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2785 {
2786 if (ath9k_hw_mci_is_enabled(ah))
2787 ar9003_mci_bt_gain_ctrl(ah);
2788
2789 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2790 return false;
2791
2792 ath9k_hw_init_pll(ah, NULL);
2793 ah->htc_reset_init = true;
2794 return true;
2795 }
2796 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2797
2798 bool ath9k_hw_disable(struct ath_hw *ah)
2799 {
2800 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2801 return false;
2802
2803 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2804 return false;
2805
2806 ath9k_hw_init_pll(ah, NULL);
2807 return true;
2808 }
2809 EXPORT_SYMBOL(ath9k_hw_disable);
2810
2811 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2812 {
2813 enum eeprom_param gain_param;
2814
2815 if (IS_CHAN_2GHZ(chan))
2816 gain_param = EEP_ANTENNA_GAIN_2G;
2817 else
2818 gain_param = EEP_ANTENNA_GAIN_5G;
2819
2820 return ah->eep_ops->get_eeprom(ah, gain_param);
2821 }
2822
2823 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2824 bool test)
2825 {
2826 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2827 struct ieee80211_channel *channel;
2828 int chan_pwr, new_pwr, max_gain;
2829 int ant_gain, ant_reduction = 0;
2830
2831 if (!chan)
2832 return;
2833
2834 channel = chan->chan;
2835 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2836 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2837 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2838
2839 ant_gain = get_antenna_gain(ah, chan);
2840 if (ant_gain > max_gain)
2841 ant_reduction = ant_gain - max_gain;
2842
2843 ah->eep_ops->set_txpower(ah, chan,
2844 ath9k_regd_get_ctl(reg, chan),
2845 ant_reduction, new_pwr, test);
2846 }
2847
2848 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2849 {
2850 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2851 struct ath9k_channel *chan = ah->curchan;
2852 struct ieee80211_channel *channel = chan->chan;
2853
2854 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2855 if (test)
2856 channel->max_power = MAX_RATE_POWER / 2;
2857
2858 ath9k_hw_apply_txpower(ah, chan, test);
2859
2860 if (test)
2861 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2862 }
2863 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2864
2865 void ath9k_hw_setopmode(struct ath_hw *ah)
2866 {
2867 ath9k_hw_set_operating_mode(ah, ah->opmode);
2868 }
2869 EXPORT_SYMBOL(ath9k_hw_setopmode);
2870
2871 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2872 {
2873 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2874 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2875 }
2876 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2877
2878 void ath9k_hw_write_associd(struct ath_hw *ah)
2879 {
2880 struct ath_common *common = ath9k_hw_common(ah);
2881
2882 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2883 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2884 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2885 }
2886 EXPORT_SYMBOL(ath9k_hw_write_associd);
2887
2888 #define ATH9K_MAX_TSF_READ 10
2889
2890 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2891 {
2892 u32 tsf_lower, tsf_upper1, tsf_upper2;
2893 int i;
2894
2895 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2896 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2897 tsf_lower = REG_READ(ah, AR_TSF_L32);
2898 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2899 if (tsf_upper2 == tsf_upper1)
2900 break;
2901 tsf_upper1 = tsf_upper2;
2902 }
2903
2904 WARN_ON( i == ATH9K_MAX_TSF_READ );
2905
2906 return (((u64)tsf_upper1 << 32) | tsf_lower);
2907 }
2908 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2909
2910 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2911 {
2912 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2913 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2914 }
2915 EXPORT_SYMBOL(ath9k_hw_settsf64);
2916
2917 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2918 {
2919 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2920 AH_TSF_WRITE_TIMEOUT))
2921 ath_dbg(ath9k_hw_common(ah), RESET,
2922 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2923
2924 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2925 }
2926 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2927
2928 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2929 {
2930 if (set)
2931 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2932 else
2933 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2934 }
2935 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2936
2937 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
2938 {
2939 u32 macmode;
2940
2941 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
2942 macmode = AR_2040_JOINED_RX_CLEAR;
2943 else
2944 macmode = 0;
2945
2946 REG_WRITE(ah, AR_2040_MODE, macmode);
2947 }
2948
2949 /* HW Generic timers configuration */
2950
2951 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2952 {
2953 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2954 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2955 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2956 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2957 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2958 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2959 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2960 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2961 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2962 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2963 AR_NDP2_TIMER_MODE, 0x0002},
2964 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2965 AR_NDP2_TIMER_MODE, 0x0004},
2966 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2967 AR_NDP2_TIMER_MODE, 0x0008},
2968 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2969 AR_NDP2_TIMER_MODE, 0x0010},
2970 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2971 AR_NDP2_TIMER_MODE, 0x0020},
2972 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2973 AR_NDP2_TIMER_MODE, 0x0040},
2974 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2975 AR_NDP2_TIMER_MODE, 0x0080}
2976 };
2977
2978 /* HW generic timer primitives */
2979
2980 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2981 {
2982 return REG_READ(ah, AR_TSF_L32);
2983 }
2984 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2985
2986 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
2987 {
2988 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2989
2990 if (timer_table->tsf2_enabled) {
2991 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
2992 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
2993 }
2994 }
2995
2996 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2997 void (*trigger)(void *),
2998 void (*overflow)(void *),
2999 void *arg,
3000 u8 timer_index)
3001 {
3002 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3003 struct ath_gen_timer *timer;
3004
3005 if ((timer_index < AR_FIRST_NDP_TIMER) ||
3006 (timer_index >= ATH_MAX_GEN_TIMER))
3007 return NULL;
3008
3009 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3010 !AR_SREV_9300_20_OR_LATER(ah))
3011 return NULL;
3012
3013 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3014 if (timer == NULL)
3015 return NULL;
3016
3017 /* allocate a hardware generic timer slot */
3018 timer_table->timers[timer_index] = timer;
3019 timer->index = timer_index;
3020 timer->trigger = trigger;
3021 timer->overflow = overflow;
3022 timer->arg = arg;
3023
3024 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3025 timer_table->tsf2_enabled = true;
3026 ath9k_hw_gen_timer_start_tsf2(ah);
3027 }
3028
3029 return timer;
3030 }
3031 EXPORT_SYMBOL(ath_gen_timer_alloc);
3032
3033 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3034 struct ath_gen_timer *timer,
3035 u32 timer_next,
3036 u32 timer_period)
3037 {
3038 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3039 u32 mask = 0;
3040
3041 timer_table->timer_mask |= BIT(timer->index);
3042
3043 /*
3044 * Program generic timer registers
3045 */
3046 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3047 timer_next);
3048 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3049 timer_period);
3050 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3051 gen_tmr_configuration[timer->index].mode_mask);
3052
3053 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3054 /*
3055 * Starting from AR9462, each generic timer can select which tsf
3056 * to use. But we still follow the old rule, 0 - 7 use tsf and
3057 * 8 - 15 use tsf2.
3058 */
3059 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3060 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3061 (1 << timer->index));
3062 else
3063 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3064 (1 << timer->index));
3065 }
3066
3067 if (timer->trigger)
3068 mask |= SM(AR_GENTMR_BIT(timer->index),
3069 AR_IMR_S5_GENTIMER_TRIG);
3070 if (timer->overflow)
3071 mask |= SM(AR_GENTMR_BIT(timer->index),
3072 AR_IMR_S5_GENTIMER_THRESH);
3073
3074 REG_SET_BIT(ah, AR_IMR_S5, mask);
3075
3076 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3077 ah->imask |= ATH9K_INT_GENTIMER;
3078 ath9k_hw_set_interrupts(ah);
3079 }
3080 }
3081 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3082
3083 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3084 {
3085 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3086
3087 /* Clear generic timer enable bits. */
3088 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3089 gen_tmr_configuration[timer->index].mode_mask);
3090
3091 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3092 /*
3093 * Need to switch back to TSF if it was using TSF2.
3094 */
3095 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3096 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3097 (1 << timer->index));
3098 }
3099 }
3100
3101 /* Disable both trigger and thresh interrupt masks */
3102 REG_CLR_BIT(ah, AR_IMR_S5,
3103 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3104 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3105
3106 timer_table->timer_mask &= ~BIT(timer->index);
3107
3108 if (timer_table->timer_mask == 0) {
3109 ah->imask &= ~ATH9K_INT_GENTIMER;
3110 ath9k_hw_set_interrupts(ah);
3111 }
3112 }
3113 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3114
3115 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3116 {
3117 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3118
3119 /* free the hardware generic timer slot */
3120 timer_table->timers[timer->index] = NULL;
3121 kfree(timer);
3122 }
3123 EXPORT_SYMBOL(ath_gen_timer_free);
3124
3125 /*
3126 * Generic Timer Interrupts handling
3127 */
3128 void ath_gen_timer_isr(struct ath_hw *ah)
3129 {
3130 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3131 struct ath_gen_timer *timer;
3132 unsigned long trigger_mask, thresh_mask;
3133 unsigned int index;
3134
3135 /* get hardware generic timer interrupt status */
3136 trigger_mask = ah->intr_gen_timer_trigger;
3137 thresh_mask = ah->intr_gen_timer_thresh;
3138 trigger_mask &= timer_table->timer_mask;
3139 thresh_mask &= timer_table->timer_mask;
3140
3141 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
3142 timer = timer_table->timers[index];
3143 if (!timer)
3144 continue;
3145 if (!timer->overflow)
3146 continue;
3147
3148 trigger_mask &= ~BIT(index);
3149 timer->overflow(timer->arg);
3150 }
3151
3152 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
3153 timer = timer_table->timers[index];
3154 if (!timer)
3155 continue;
3156 if (!timer->trigger)
3157 continue;
3158 timer->trigger(timer->arg);
3159 }
3160 }
3161 EXPORT_SYMBOL(ath_gen_timer_isr);
3162
3163 /********/
3164 /* HTC */
3165 /********/
3166
3167 static struct {
3168 u32 version;
3169 const char * name;
3170 } ath_mac_bb_names[] = {
3171 /* Devices with external radios */
3172 { AR_SREV_VERSION_5416_PCI, "5416" },
3173 { AR_SREV_VERSION_5416_PCIE, "5418" },
3174 { AR_SREV_VERSION_9100, "9100" },
3175 { AR_SREV_VERSION_9160, "9160" },
3176 /* Single-chip solutions */
3177 { AR_SREV_VERSION_9280, "9280" },
3178 { AR_SREV_VERSION_9285, "9285" },
3179 { AR_SREV_VERSION_9287, "9287" },
3180 { AR_SREV_VERSION_9271, "9271" },
3181 { AR_SREV_VERSION_9300, "9300" },
3182 { AR_SREV_VERSION_9330, "9330" },
3183 { AR_SREV_VERSION_9340, "9340" },
3184 { AR_SREV_VERSION_9485, "9485" },
3185 { AR_SREV_VERSION_9462, "9462" },
3186 { AR_SREV_VERSION_9550, "9550" },
3187 { AR_SREV_VERSION_9565, "9565" },
3188 { AR_SREV_VERSION_9531, "9531" },
3189 };
3190
3191 /* For devices with external radios */
3192 static struct {
3193 u16 version;
3194 const char * name;
3195 } ath_rf_names[] = {
3196 { 0, "5133" },
3197 { AR_RAD5133_SREV_MAJOR, "5133" },
3198 { AR_RAD5122_SREV_MAJOR, "5122" },
3199 { AR_RAD2133_SREV_MAJOR, "2133" },
3200 { AR_RAD2122_SREV_MAJOR, "2122" }
3201 };
3202
3203 /*
3204 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3205 */
3206 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3207 {
3208 int i;
3209
3210 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3211 if (ath_mac_bb_names[i].version == mac_bb_version) {
3212 return ath_mac_bb_names[i].name;
3213 }
3214 }
3215
3216 return "????";
3217 }
3218
3219 /*
3220 * Return the RF name. "????" is returned if the RF is unknown.
3221 * Used for devices with external radios.
3222 */
3223 static const char *ath9k_hw_rf_name(u16 rf_version)
3224 {
3225 int i;
3226
3227 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3228 if (ath_rf_names[i].version == rf_version) {
3229 return ath_rf_names[i].name;
3230 }
3231 }
3232
3233 return "????";
3234 }
3235
3236 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3237 {
3238 int used;
3239
3240 /* chipsets >= AR9280 are single-chip */
3241 if (AR_SREV_9280_20_OR_LATER(ah)) {
3242 used = scnprintf(hw_name, len,
3243 "Atheros AR%s Rev:%x",
3244 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3245 ah->hw_version.macRev);
3246 }
3247 else {
3248 used = scnprintf(hw_name, len,
3249 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3250 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3251 ah->hw_version.macRev,
3252 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3253 & AR_RADIO_SREV_MAJOR)),
3254 ah->hw_version.phyRev);
3255 }
3256
3257 hw_name[used] = '\0';
3258 }
3259 EXPORT_SYMBOL(ath9k_hw_name);
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