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[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
96 else
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
103 }
104
105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
106 {
107 struct ath_common *common = ath9k_hw_common(ah);
108
109 return usecs * common->clockrate;
110 }
111
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
113 {
114 int i;
115
116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
124
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
128
129 return false;
130 }
131 EXPORT_SYMBOL(ath9k_hw_wait);
132
133 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135 {
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145 }
146
147 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
148 {
149 u32 retval;
150 int i;
151
152 for (i = 0, retval = 0; i < n; i++) {
153 retval = (retval << 1) | (val & 1);
154 val >>= 1;
155 }
156 return retval;
157 }
158
159 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
160 u8 phy, int kbps,
161 u32 frameLen, u16 rateix,
162 bool shortPreamble)
163 {
164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
165
166 if (kbps == 0)
167 return 0;
168
169 switch (phy) {
170 case WLAN_RC_PHY_CCK:
171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
172 if (shortPreamble)
173 phyTime >>= 1;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
176 break;
177 case WLAN_RC_PHY_OFDM:
178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
193 } else {
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
199 }
200 break;
201 default:
202 ath_err(ath9k_hw_common(ah),
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
204 txTime = 0;
205 break;
206 }
207
208 return txTime;
209 }
210 EXPORT_SYMBOL(ath9k_hw_computetxtime);
211
212 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
215 {
216 int8_t extoff;
217
218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
221 return;
222 }
223
224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
228 extoff = 1;
229 } else {
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
232 extoff = -1;
233 }
234
235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
237 /* 25 MHz spacing is supported by hw but not on upper layers */
238 centers->ext_center =
239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
240 }
241
242 /******************/
243 /* Chip Revisions */
244 /******************/
245
246 static void ath9k_hw_read_revisions(struct ath_hw *ah)
247 {
248 u32 val;
249
250 switch (ah->hw_version.devid) {
251 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
253 break;
254 case AR9300_DEVID_AR9330:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
256 if (ah->get_mac_revision) {
257 ah->hw_version.macRev = ah->get_mac_revision();
258 } else {
259 val = REG_READ(ah, AR_SREV);
260 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
261 }
262 return;
263 case AR9300_DEVID_AR9340:
264 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
265 val = REG_READ(ah, AR_SREV);
266 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
267 return;
268 }
269
270 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
271
272 if (val == 0xFF) {
273 val = REG_READ(ah, AR_SREV);
274 ah->hw_version.macVersion =
275 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
277 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
278 } else {
279 if (!AR_SREV_9100(ah))
280 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
281
282 ah->hw_version.macRev = val & AR_SREV_REVISION;
283
284 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
285 ah->is_pciexpress = true;
286 }
287 }
288
289 /************************************/
290 /* HW Attach, Detach, Init Routines */
291 /************************************/
292
293 static void ath9k_hw_disablepcie(struct ath_hw *ah)
294 {
295 if (!AR_SREV_5416(ah))
296 return;
297
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
301 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
302 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
303 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
304 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
305 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
306 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
307
308 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
309 }
310
311 /* This should work for all families including legacy */
312 static bool ath9k_hw_chip_test(struct ath_hw *ah)
313 {
314 struct ath_common *common = ath9k_hw_common(ah);
315 u32 regAddr[2] = { AR_STA_ID0 };
316 u32 regHold[2];
317 static const u32 patternData[4] = {
318 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
319 };
320 int i, j, loop_max;
321
322 if (!AR_SREV_9300_20_OR_LATER(ah)) {
323 loop_max = 2;
324 regAddr[1] = AR_PHY_BASE + (8 << 2);
325 } else
326 loop_max = 1;
327
328 for (i = 0; i < loop_max; i++) {
329 u32 addr = regAddr[i];
330 u32 wrData, rdData;
331
332 regHold[i] = REG_READ(ah, addr);
333 for (j = 0; j < 0x100; j++) {
334 wrData = (j << 16) | j;
335 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr);
337 if (rdData != wrData) {
338 ath_err(common,
339 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
340 addr, wrData, rdData);
341 return false;
342 }
343 }
344 for (j = 0; j < 4; j++) {
345 wrData = patternData[j];
346 REG_WRITE(ah, addr, wrData);
347 rdData = REG_READ(ah, addr);
348 if (wrData != rdData) {
349 ath_err(common,
350 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
351 addr, wrData, rdData);
352 return false;
353 }
354 }
355 REG_WRITE(ah, regAddr[i], regHold[i]);
356 }
357 udelay(100);
358
359 return true;
360 }
361
362 static void ath9k_hw_init_config(struct ath_hw *ah)
363 {
364 int i;
365
366 ah->config.dma_beacon_response_time = 2;
367 ah->config.sw_beacon_response_time = 10;
368 ah->config.additional_swba_backoff = 0;
369 ah->config.ack_6mb = 0x0;
370 ah->config.cwm_ignore_extcca = 0;
371 ah->config.pcie_powersave_enable = 0;
372 ah->config.pcie_clock_req = 0;
373 ah->config.pcie_waen = 0;
374 ah->config.analog_shiftreg = 1;
375 ah->config.enable_ani = true;
376
377 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
378 ah->config.spurchans[i][0] = AR_NO_SPUR;
379 ah->config.spurchans[i][1] = AR_NO_SPUR;
380 }
381
382 /* PAPRD needs some more work to be enabled */
383 ah->config.paprd_disable = 1;
384
385 ah->config.rx_intr_mitigation = true;
386 ah->config.pcieSerDesWrite = true;
387
388 /*
389 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
390 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
391 * This means we use it for all AR5416 devices, and the few
392 * minor PCI AR9280 devices out there.
393 *
394 * Serialization is required because these devices do not handle
395 * well the case of two concurrent reads/writes due to the latency
396 * involved. During one read/write another read/write can be issued
397 * on another CPU while the previous read/write may still be working
398 * on our hardware, if we hit this case the hardware poops in a loop.
399 * We prevent this by serializing reads and writes.
400 *
401 * This issue is not present on PCI-Express devices or pre-AR5416
402 * devices (legacy, 802.11abg).
403 */
404 if (num_possible_cpus() > 1)
405 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
406 }
407
408 static void ath9k_hw_init_defaults(struct ath_hw *ah)
409 {
410 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
411
412 regulatory->country_code = CTRY_DEFAULT;
413 regulatory->power_limit = MAX_RATE_POWER;
414 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
415
416 ah->hw_version.magic = AR5416_MAGIC;
417 ah->hw_version.subvendorid = 0;
418
419 ah->atim_window = 0;
420 ah->sta_id1_defaults =
421 AR_STA_ID1_CRPT_MIC_ENABLE |
422 AR_STA_ID1_MCAST_KSRCH;
423 if (AR_SREV_9100(ah))
424 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
425 ah->enable_32kHz_clock = DONT_USE_32KHZ;
426 ah->slottime = 20;
427 ah->globaltxtimeout = (u32) -1;
428 ah->power_mode = ATH9K_PM_UNDEFINED;
429 }
430
431 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
432 {
433 struct ath_common *common = ath9k_hw_common(ah);
434 u32 sum;
435 int i;
436 u16 eeval;
437 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
438
439 sum = 0;
440 for (i = 0; i < 3; i++) {
441 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
442 sum += eeval;
443 common->macaddr[2 * i] = eeval >> 8;
444 common->macaddr[2 * i + 1] = eeval & 0xff;
445 }
446 if (sum == 0 || sum == 0xffff * 3)
447 return -EADDRNOTAVAIL;
448
449 return 0;
450 }
451
452 static int ath9k_hw_post_init(struct ath_hw *ah)
453 {
454 struct ath_common *common = ath9k_hw_common(ah);
455 int ecode;
456
457 if (common->bus_ops->ath_bus_type != ATH_USB) {
458 if (!ath9k_hw_chip_test(ah))
459 return -ENODEV;
460 }
461
462 if (!AR_SREV_9300_20_OR_LATER(ah)) {
463 ecode = ar9002_hw_rf_claim(ah);
464 if (ecode != 0)
465 return ecode;
466 }
467
468 ecode = ath9k_hw_eeprom_init(ah);
469 if (ecode != 0)
470 return ecode;
471
472 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
473 "Eeprom VER: %d, REV: %d\n",
474 ah->eep_ops->get_eeprom_ver(ah),
475 ah->eep_ops->get_eeprom_rev(ah));
476
477 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
478 if (ecode) {
479 ath_err(ath9k_hw_common(ah),
480 "Failed allocating banks for external radio\n");
481 ath9k_hw_rf_free_ext_banks(ah);
482 return ecode;
483 }
484
485 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
486 ath9k_hw_ani_setup(ah);
487 ath9k_hw_ani_init(ah);
488 }
489
490 return 0;
491 }
492
493 static void ath9k_hw_attach_ops(struct ath_hw *ah)
494 {
495 if (AR_SREV_9300_20_OR_LATER(ah))
496 ar9003_hw_attach_ops(ah);
497 else
498 ar9002_hw_attach_ops(ah);
499 }
500
501 /* Called for all hardware families */
502 static int __ath9k_hw_init(struct ath_hw *ah)
503 {
504 struct ath_common *common = ath9k_hw_common(ah);
505 int r = 0;
506
507 ath9k_hw_read_revisions(ah);
508
509 /*
510 * Read back AR_WA into a permanent copy and set bits 14 and 17.
511 * We need to do this to avoid RMW of this register. We cannot
512 * read the reg when chip is asleep.
513 */
514 ah->WARegVal = REG_READ(ah, AR_WA);
515 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
516 AR_WA_ASPM_TIMER_BASED_DISABLE);
517
518 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
519 ath_err(common, "Couldn't reset chip\n");
520 return -EIO;
521 }
522
523 ath9k_hw_init_defaults(ah);
524 ath9k_hw_init_config(ah);
525
526 ath9k_hw_attach_ops(ah);
527
528 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
529 ath_err(common, "Couldn't wakeup chip\n");
530 return -EIO;
531 }
532
533 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
534 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
535 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
536 !ah->is_pciexpress)) {
537 ah->config.serialize_regmode =
538 SER_REG_MODE_ON;
539 } else {
540 ah->config.serialize_regmode =
541 SER_REG_MODE_OFF;
542 }
543 }
544
545 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
546 ah->config.serialize_regmode);
547
548 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
549 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
550 else
551 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
552
553 switch (ah->hw_version.macVersion) {
554 case AR_SREV_VERSION_5416_PCI:
555 case AR_SREV_VERSION_5416_PCIE:
556 case AR_SREV_VERSION_9160:
557 case AR_SREV_VERSION_9100:
558 case AR_SREV_VERSION_9280:
559 case AR_SREV_VERSION_9285:
560 case AR_SREV_VERSION_9287:
561 case AR_SREV_VERSION_9271:
562 case AR_SREV_VERSION_9300:
563 case AR_SREV_VERSION_9330:
564 case AR_SREV_VERSION_9485:
565 case AR_SREV_VERSION_9340:
566 break;
567 default:
568 ath_err(common,
569 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
570 ah->hw_version.macVersion, ah->hw_version.macRev);
571 return -EOPNOTSUPP;
572 }
573
574 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
575 AR_SREV_9330(ah))
576 ah->is_pciexpress = false;
577
578 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
579 ath9k_hw_init_cal_settings(ah);
580
581 ah->ani_function = ATH9K_ANI_ALL;
582 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
583 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
584 if (!AR_SREV_9300_20_OR_LATER(ah))
585 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
586
587 ath9k_hw_init_mode_regs(ah);
588
589
590 if (ah->is_pciexpress)
591 ath9k_hw_configpcipowersave(ah, 0, 0);
592 else
593 ath9k_hw_disablepcie(ah);
594
595 if (!AR_SREV_9300_20_OR_LATER(ah))
596 ar9002_hw_cck_chan14_spread(ah);
597
598 r = ath9k_hw_post_init(ah);
599 if (r)
600 return r;
601
602 ath9k_hw_init_mode_gain_regs(ah);
603 r = ath9k_hw_fill_cap_info(ah);
604 if (r)
605 return r;
606
607 r = ath9k_hw_init_macaddr(ah);
608 if (r) {
609 ath_err(common, "Failed to initialize MAC address\n");
610 return r;
611 }
612
613 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
614 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
615 else
616 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
617
618 if (AR_SREV_9330(ah))
619 ah->bb_watchdog_timeout_ms = 85;
620 else
621 ah->bb_watchdog_timeout_ms = 25;
622
623 common->state = ATH_HW_INITIALIZED;
624
625 return 0;
626 }
627
628 int ath9k_hw_init(struct ath_hw *ah)
629 {
630 int ret;
631 struct ath_common *common = ath9k_hw_common(ah);
632
633 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
634 switch (ah->hw_version.devid) {
635 case AR5416_DEVID_PCI:
636 case AR5416_DEVID_PCIE:
637 case AR5416_AR9100_DEVID:
638 case AR9160_DEVID_PCI:
639 case AR9280_DEVID_PCI:
640 case AR9280_DEVID_PCIE:
641 case AR9285_DEVID_PCIE:
642 case AR9287_DEVID_PCI:
643 case AR9287_DEVID_PCIE:
644 case AR2427_DEVID_PCIE:
645 case AR9300_DEVID_PCIE:
646 case AR9300_DEVID_AR9485_PCIE:
647 case AR9300_DEVID_AR9330:
648 case AR9300_DEVID_AR9340:
649 break;
650 default:
651 if (common->bus_ops->ath_bus_type == ATH_USB)
652 break;
653 ath_err(common, "Hardware device ID 0x%04x not supported\n",
654 ah->hw_version.devid);
655 return -EOPNOTSUPP;
656 }
657
658 ret = __ath9k_hw_init(ah);
659 if (ret) {
660 ath_err(common,
661 "Unable to initialize hardware; initialization status: %d\n",
662 ret);
663 return ret;
664 }
665
666 return 0;
667 }
668 EXPORT_SYMBOL(ath9k_hw_init);
669
670 static void ath9k_hw_init_qos(struct ath_hw *ah)
671 {
672 ENABLE_REGWRITE_BUFFER(ah);
673
674 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
675 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
676
677 REG_WRITE(ah, AR_QOS_NO_ACK,
678 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
679 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
680 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
681
682 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
683 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
684 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
685 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
686 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
687
688 REGWRITE_BUFFER_FLUSH(ah);
689 }
690
691 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
692 {
693 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
694 udelay(100);
695 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
696
697 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
698 udelay(100);
699
700 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
701 }
702 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
703
704 static void ath9k_hw_init_pll(struct ath_hw *ah,
705 struct ath9k_channel *chan)
706 {
707 u32 pll;
708
709 if (AR_SREV_9485(ah)) {
710
711 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
713 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
714 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
715 AR_CH0_DPLL2_KD, 0x40);
716 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
717 AR_CH0_DPLL2_KI, 0x4);
718
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
720 AR_CH0_BB_DPLL1_REFDIV, 0x5);
721 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
722 AR_CH0_BB_DPLL1_NINI, 0x58);
723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
724 AR_CH0_BB_DPLL1_NFRAC, 0x0);
725
726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
727 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
728 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
729 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
731 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
732
733 /* program BB PLL phase_shift to 0x6 */
734 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
735 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
736
737 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
738 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
739 udelay(1000);
740 } else if (AR_SREV_9330(ah)) {
741 u32 ddr_dpll2, pll_control2, kd;
742
743 if (ah->is_clk_25mhz) {
744 ddr_dpll2 = 0x18e82f01;
745 pll_control2 = 0xe04a3d;
746 kd = 0x1d;
747 } else {
748 ddr_dpll2 = 0x19e82f01;
749 pll_control2 = 0x886666;
750 kd = 0x3d;
751 }
752
753 /* program DDR PLL ki and kd value */
754 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
755
756 /* program DDR PLL phase_shift */
757 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
758 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
759
760 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
761 udelay(1000);
762
763 /* program refdiv, nint, frac to RTC register */
764 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
765
766 /* program BB PLL kd and ki value */
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
769
770 /* program BB PLL phase_shift */
771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
772 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
773 } else if (AR_SREV_9340(ah)) {
774 u32 regval, pll2_divint, pll2_divfrac, refdiv;
775
776 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
777 udelay(1000);
778
779 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
780 udelay(100);
781
782 if (ah->is_clk_25mhz) {
783 pll2_divint = 0x54;
784 pll2_divfrac = 0x1eb85;
785 refdiv = 3;
786 } else {
787 pll2_divint = 88;
788 pll2_divfrac = 0;
789 refdiv = 5;
790 }
791
792 regval = REG_READ(ah, AR_PHY_PLL_MODE);
793 regval |= (0x1 << 16);
794 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
795 udelay(100);
796
797 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
798 (pll2_divint << 18) | pll2_divfrac);
799 udelay(100);
800
801 regval = REG_READ(ah, AR_PHY_PLL_MODE);
802 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
803 (0x4 << 26) | (0x18 << 19);
804 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
805 REG_WRITE(ah, AR_PHY_PLL_MODE,
806 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
807 udelay(1000);
808 }
809
810 pll = ath9k_hw_compute_pll_control(ah, chan);
811
812 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
813
814 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
815 udelay(1000);
816
817 /* Switch the core clock for ar9271 to 117Mhz */
818 if (AR_SREV_9271(ah)) {
819 udelay(500);
820 REG_WRITE(ah, 0x50040, 0x304);
821 }
822
823 udelay(RTC_PLL_SETTLE_DELAY);
824
825 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
826
827 if (AR_SREV_9340(ah)) {
828 if (ah->is_clk_25mhz) {
829 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
830 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
831 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
832 } else {
833 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
834 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
835 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
836 }
837 udelay(100);
838 }
839 }
840
841 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
842 enum nl80211_iftype opmode)
843 {
844 u32 sync_default = AR_INTR_SYNC_DEFAULT;
845 u32 imr_reg = AR_IMR_TXERR |
846 AR_IMR_TXURN |
847 AR_IMR_RXERR |
848 AR_IMR_RXORN |
849 AR_IMR_BCNMISC;
850
851 if (AR_SREV_9340(ah))
852 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
853
854 if (AR_SREV_9300_20_OR_LATER(ah)) {
855 imr_reg |= AR_IMR_RXOK_HP;
856 if (ah->config.rx_intr_mitigation)
857 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
858 else
859 imr_reg |= AR_IMR_RXOK_LP;
860
861 } else {
862 if (ah->config.rx_intr_mitigation)
863 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
864 else
865 imr_reg |= AR_IMR_RXOK;
866 }
867
868 if (ah->config.tx_intr_mitigation)
869 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
870 else
871 imr_reg |= AR_IMR_TXOK;
872
873 if (opmode == NL80211_IFTYPE_AP)
874 imr_reg |= AR_IMR_MIB;
875
876 ENABLE_REGWRITE_BUFFER(ah);
877
878 REG_WRITE(ah, AR_IMR, imr_reg);
879 ah->imrs2_reg |= AR_IMR_S2_GTT;
880 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
881
882 if (!AR_SREV_9100(ah)) {
883 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
884 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
885 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
886 }
887
888 REGWRITE_BUFFER_FLUSH(ah);
889
890 if (AR_SREV_9300_20_OR_LATER(ah)) {
891 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
892 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
893 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
894 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
895 }
896 }
897
898 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
899 {
900 u32 val = ath9k_hw_mac_to_clks(ah, us);
901 val = min(val, (u32) 0xFFFF);
902 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
903 }
904
905 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
906 {
907 u32 val = ath9k_hw_mac_to_clks(ah, us);
908 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
909 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
910 }
911
912 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
913 {
914 u32 val = ath9k_hw_mac_to_clks(ah, us);
915 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
916 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
917 }
918
919 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
920 {
921 if (tu > 0xFFFF) {
922 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
923 "bad global tx timeout %u\n", tu);
924 ah->globaltxtimeout = (u32) -1;
925 return false;
926 } else {
927 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
928 ah->globaltxtimeout = tu;
929 return true;
930 }
931 }
932
933 void ath9k_hw_init_global_settings(struct ath_hw *ah)
934 {
935 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
936 int acktimeout;
937 int slottime;
938 int sifstime;
939
940 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
941 ah->misc_mode);
942
943 if (ah->misc_mode != 0)
944 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
945
946 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
947 sifstime = 16;
948 else
949 sifstime = 10;
950
951 /* As defined by IEEE 802.11-2007 17.3.8.6 */
952 slottime = ah->slottime + 3 * ah->coverage_class;
953 acktimeout = slottime + sifstime;
954
955 /*
956 * Workaround for early ACK timeouts, add an offset to match the
957 * initval's 64us ack timeout value.
958 * This was initially only meant to work around an issue with delayed
959 * BA frames in some implementations, but it has been found to fix ACK
960 * timeout issues in other cases as well.
961 */
962 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
963 acktimeout += 64 - sifstime - ah->slottime;
964
965 ath9k_hw_setslottime(ah, ah->slottime);
966 ath9k_hw_set_ack_timeout(ah, acktimeout);
967 ath9k_hw_set_cts_timeout(ah, acktimeout);
968 if (ah->globaltxtimeout != (u32) -1)
969 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
970 }
971 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
972
973 void ath9k_hw_deinit(struct ath_hw *ah)
974 {
975 struct ath_common *common = ath9k_hw_common(ah);
976
977 if (common->state < ATH_HW_INITIALIZED)
978 goto free_hw;
979
980 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
981
982 free_hw:
983 ath9k_hw_rf_free_ext_banks(ah);
984 }
985 EXPORT_SYMBOL(ath9k_hw_deinit);
986
987 /*******/
988 /* INI */
989 /*******/
990
991 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
992 {
993 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
994
995 if (IS_CHAN_B(chan))
996 ctl |= CTL_11B;
997 else if (IS_CHAN_G(chan))
998 ctl |= CTL_11G;
999 else
1000 ctl |= CTL_11A;
1001
1002 return ctl;
1003 }
1004
1005 /****************************************/
1006 /* Reset and Channel Switching Routines */
1007 /****************************************/
1008
1009 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1010 {
1011 struct ath_common *common = ath9k_hw_common(ah);
1012
1013 ENABLE_REGWRITE_BUFFER(ah);
1014
1015 /*
1016 * set AHB_MODE not to do cacheline prefetches
1017 */
1018 if (!AR_SREV_9300_20_OR_LATER(ah))
1019 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1020
1021 /*
1022 * let mac dma reads be in 128 byte chunks
1023 */
1024 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1025
1026 REGWRITE_BUFFER_FLUSH(ah);
1027
1028 /*
1029 * Restore TX Trigger Level to its pre-reset value.
1030 * The initial value depends on whether aggregation is enabled, and is
1031 * adjusted whenever underruns are detected.
1032 */
1033 if (!AR_SREV_9300_20_OR_LATER(ah))
1034 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1035
1036 ENABLE_REGWRITE_BUFFER(ah);
1037
1038 /*
1039 * let mac dma writes be in 128 byte chunks
1040 */
1041 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1042
1043 /*
1044 * Setup receive FIFO threshold to hold off TX activities
1045 */
1046 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1047
1048 if (AR_SREV_9300_20_OR_LATER(ah)) {
1049 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1050 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1051
1052 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1053 ah->caps.rx_status_len);
1054 }
1055
1056 /*
1057 * reduce the number of usable entries in PCU TXBUF to avoid
1058 * wrap around issues.
1059 */
1060 if (AR_SREV_9285(ah)) {
1061 /* For AR9285 the number of Fifos are reduced to half.
1062 * So set the usable tx buf size also to half to
1063 * avoid data/delimiter underruns
1064 */
1065 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1066 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1067 } else if (!AR_SREV_9271(ah)) {
1068 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1069 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1070 }
1071
1072 REGWRITE_BUFFER_FLUSH(ah);
1073
1074 if (AR_SREV_9300_20_OR_LATER(ah))
1075 ath9k_hw_reset_txstatus_ring(ah);
1076 }
1077
1078 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1079 {
1080 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1081 u32 set = AR_STA_ID1_KSRCH_MODE;
1082
1083 switch (opmode) {
1084 case NL80211_IFTYPE_ADHOC:
1085 case NL80211_IFTYPE_MESH_POINT:
1086 set |= AR_STA_ID1_ADHOC;
1087 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1088 break;
1089 case NL80211_IFTYPE_AP:
1090 set |= AR_STA_ID1_STA_AP;
1091 /* fall through */
1092 case NL80211_IFTYPE_STATION:
1093 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1094 break;
1095 default:
1096 if (!ah->is_monitoring)
1097 set = 0;
1098 break;
1099 }
1100 REG_RMW(ah, AR_STA_ID1, set, mask);
1101 }
1102
1103 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1104 u32 *coef_mantissa, u32 *coef_exponent)
1105 {
1106 u32 coef_exp, coef_man;
1107
1108 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1109 if ((coef_scaled >> coef_exp) & 0x1)
1110 break;
1111
1112 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1113
1114 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1115
1116 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1117 *coef_exponent = coef_exp - 16;
1118 }
1119
1120 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1121 {
1122 u32 rst_flags;
1123 u32 tmpReg;
1124
1125 if (AR_SREV_9100(ah)) {
1126 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1127 AR_RTC_DERIVED_CLK_PERIOD, 1);
1128 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1129 }
1130
1131 ENABLE_REGWRITE_BUFFER(ah);
1132
1133 if (AR_SREV_9300_20_OR_LATER(ah)) {
1134 REG_WRITE(ah, AR_WA, ah->WARegVal);
1135 udelay(10);
1136 }
1137
1138 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1139 AR_RTC_FORCE_WAKE_ON_INT);
1140
1141 if (AR_SREV_9100(ah)) {
1142 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1143 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1144 } else {
1145 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1146 if (tmpReg &
1147 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1148 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1149 u32 val;
1150 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1151
1152 val = AR_RC_HOSTIF;
1153 if (!AR_SREV_9300_20_OR_LATER(ah))
1154 val |= AR_RC_AHB;
1155 REG_WRITE(ah, AR_RC, val);
1156
1157 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1158 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1159
1160 rst_flags = AR_RTC_RC_MAC_WARM;
1161 if (type == ATH9K_RESET_COLD)
1162 rst_flags |= AR_RTC_RC_MAC_COLD;
1163 }
1164
1165 if (AR_SREV_9330(ah)) {
1166 int npend = 0;
1167 int i;
1168
1169 /* AR9330 WAR:
1170 * call external reset function to reset WMAC if:
1171 * - doing a cold reset
1172 * - we have pending frames in the TX queues
1173 */
1174
1175 for (i = 0; i < AR_NUM_QCU; i++) {
1176 npend = ath9k_hw_numtxpending(ah, i);
1177 if (npend)
1178 break;
1179 }
1180
1181 if (ah->external_reset &&
1182 (npend || type == ATH9K_RESET_COLD)) {
1183 int reset_err = 0;
1184
1185 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1186 "reset MAC via external reset\n");
1187
1188 reset_err = ah->external_reset();
1189 if (reset_err) {
1190 ath_err(ath9k_hw_common(ah),
1191 "External reset failed, err=%d\n",
1192 reset_err);
1193 return false;
1194 }
1195
1196 REG_WRITE(ah, AR_RTC_RESET, 1);
1197 }
1198 }
1199
1200 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1201
1202 REGWRITE_BUFFER_FLUSH(ah);
1203
1204 udelay(50);
1205
1206 REG_WRITE(ah, AR_RTC_RC, 0);
1207 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1208 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1209 "RTC stuck in MAC reset\n");
1210 return false;
1211 }
1212
1213 if (!AR_SREV_9100(ah))
1214 REG_WRITE(ah, AR_RC, 0);
1215
1216 if (AR_SREV_9100(ah))
1217 udelay(50);
1218
1219 return true;
1220 }
1221
1222 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1223 {
1224 ENABLE_REGWRITE_BUFFER(ah);
1225
1226 if (AR_SREV_9300_20_OR_LATER(ah)) {
1227 REG_WRITE(ah, AR_WA, ah->WARegVal);
1228 udelay(10);
1229 }
1230
1231 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1232 AR_RTC_FORCE_WAKE_ON_INT);
1233
1234 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1235 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1236
1237 REG_WRITE(ah, AR_RTC_RESET, 0);
1238
1239 REGWRITE_BUFFER_FLUSH(ah);
1240
1241 if (!AR_SREV_9300_20_OR_LATER(ah))
1242 udelay(2);
1243
1244 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1245 REG_WRITE(ah, AR_RC, 0);
1246
1247 REG_WRITE(ah, AR_RTC_RESET, 1);
1248
1249 if (!ath9k_hw_wait(ah,
1250 AR_RTC_STATUS,
1251 AR_RTC_STATUS_M,
1252 AR_RTC_STATUS_ON,
1253 AH_WAIT_TIMEOUT)) {
1254 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1255 "RTC not waking up\n");
1256 return false;
1257 }
1258
1259 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1260 }
1261
1262 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1263 {
1264 if (AR_SREV_9300_20_OR_LATER(ah)) {
1265 REG_WRITE(ah, AR_WA, ah->WARegVal);
1266 udelay(10);
1267 }
1268
1269 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1270 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1271
1272 switch (type) {
1273 case ATH9K_RESET_POWER_ON:
1274 return ath9k_hw_set_reset_power_on(ah);
1275 case ATH9K_RESET_WARM:
1276 case ATH9K_RESET_COLD:
1277 return ath9k_hw_set_reset(ah, type);
1278 default:
1279 return false;
1280 }
1281 }
1282
1283 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1284 struct ath9k_channel *chan)
1285 {
1286 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1287 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1288 return false;
1289 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1290 return false;
1291
1292 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1293 return false;
1294
1295 ah->chip_fullsleep = false;
1296 ath9k_hw_init_pll(ah, chan);
1297 ath9k_hw_set_rfmode(ah, chan);
1298
1299 return true;
1300 }
1301
1302 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1303 struct ath9k_channel *chan)
1304 {
1305 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1306 struct ath_common *common = ath9k_hw_common(ah);
1307 struct ieee80211_channel *channel = chan->chan;
1308 u32 qnum;
1309 int r;
1310
1311 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1312 if (ath9k_hw_numtxpending(ah, qnum)) {
1313 ath_dbg(common, ATH_DBG_QUEUE,
1314 "Transmit frames pending on queue %d\n", qnum);
1315 return false;
1316 }
1317 }
1318
1319 if (!ath9k_hw_rfbus_req(ah)) {
1320 ath_err(common, "Could not kill baseband RX\n");
1321 return false;
1322 }
1323
1324 ath9k_hw_set_channel_regs(ah, chan);
1325
1326 r = ath9k_hw_rf_set_freq(ah, chan);
1327 if (r) {
1328 ath_err(common, "Failed to set channel\n");
1329 return false;
1330 }
1331 ath9k_hw_set_clockrate(ah);
1332
1333 ah->eep_ops->set_txpower(ah, chan,
1334 ath9k_regd_get_ctl(regulatory, chan),
1335 channel->max_antenna_gain * 2,
1336 channel->max_power * 2,
1337 min((u32) MAX_RATE_POWER,
1338 (u32) regulatory->power_limit), false);
1339
1340 ath9k_hw_rfbus_done(ah);
1341
1342 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1343 ath9k_hw_set_delta_slope(ah, chan);
1344
1345 ath9k_hw_spur_mitigate_freq(ah, chan);
1346
1347 return true;
1348 }
1349
1350 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1351 {
1352 u32 gpio_mask = ah->gpio_mask;
1353 int i;
1354
1355 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1356 if (!(gpio_mask & 1))
1357 continue;
1358
1359 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1360 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1361 }
1362 }
1363
1364 bool ath9k_hw_check_alive(struct ath_hw *ah)
1365 {
1366 int count = 50;
1367 u32 reg;
1368
1369 if (AR_SREV_9285_12_OR_LATER(ah))
1370 return true;
1371
1372 do {
1373 reg = REG_READ(ah, AR_OBS_BUS_1);
1374
1375 if ((reg & 0x7E7FFFEF) == 0x00702400)
1376 continue;
1377
1378 switch (reg & 0x7E000B00) {
1379 case 0x1E000000:
1380 case 0x52000B00:
1381 case 0x18000B00:
1382 continue;
1383 default:
1384 return true;
1385 }
1386 } while (count-- > 0);
1387
1388 return false;
1389 }
1390 EXPORT_SYMBOL(ath9k_hw_check_alive);
1391
1392 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1393 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1394 {
1395 struct ath_common *common = ath9k_hw_common(ah);
1396 u32 saveLedState;
1397 struct ath9k_channel *curchan = ah->curchan;
1398 u32 saveDefAntenna;
1399 u32 macStaId1;
1400 u64 tsf = 0;
1401 int i, r;
1402
1403 ah->txchainmask = common->tx_chainmask;
1404 ah->rxchainmask = common->rx_chainmask;
1405
1406 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1407 return -EIO;
1408
1409 if (curchan && !ah->chip_fullsleep)
1410 ath9k_hw_getnf(ah, curchan);
1411
1412 ah->caldata = caldata;
1413 if (caldata &&
1414 (chan->channel != caldata->channel ||
1415 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1416 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1417 /* Operating channel changed, reset channel calibration data */
1418 memset(caldata, 0, sizeof(*caldata));
1419 ath9k_init_nfcal_hist_buffer(ah, chan);
1420 }
1421
1422 if (bChannelChange &&
1423 (ah->chip_fullsleep != true) &&
1424 (ah->curchan != NULL) &&
1425 (chan->channel != ah->curchan->channel) &&
1426 ((chan->channelFlags & CHANNEL_ALL) ==
1427 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1428 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1429
1430 if (ath9k_hw_channel_change(ah, chan)) {
1431 ath9k_hw_loadnf(ah, ah->curchan);
1432 ath9k_hw_start_nfcal(ah, true);
1433 if (AR_SREV_9271(ah))
1434 ar9002_hw_load_ani_reg(ah, chan);
1435 return 0;
1436 }
1437 }
1438
1439 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1440 if (saveDefAntenna == 0)
1441 saveDefAntenna = 1;
1442
1443 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1444
1445 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1446 if (AR_SREV_9100(ah) ||
1447 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1448 tsf = ath9k_hw_gettsf64(ah);
1449
1450 saveLedState = REG_READ(ah, AR_CFG_LED) &
1451 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1452 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1453
1454 ath9k_hw_mark_phy_inactive(ah);
1455
1456 ah->paprd_table_write_done = false;
1457
1458 /* Only required on the first reset */
1459 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1460 REG_WRITE(ah,
1461 AR9271_RESET_POWER_DOWN_CONTROL,
1462 AR9271_RADIO_RF_RST);
1463 udelay(50);
1464 }
1465
1466 if (!ath9k_hw_chip_reset(ah, chan)) {
1467 ath_err(common, "Chip reset failed\n");
1468 return -EINVAL;
1469 }
1470
1471 /* Only required on the first reset */
1472 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1473 ah->htc_reset_init = false;
1474 REG_WRITE(ah,
1475 AR9271_RESET_POWER_DOWN_CONTROL,
1476 AR9271_GATE_MAC_CTL);
1477 udelay(50);
1478 }
1479
1480 /* Restore TSF */
1481 if (tsf)
1482 ath9k_hw_settsf64(ah, tsf);
1483
1484 if (AR_SREV_9280_20_OR_LATER(ah))
1485 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1486
1487 if (!AR_SREV_9300_20_OR_LATER(ah))
1488 ar9002_hw_enable_async_fifo(ah);
1489
1490 r = ath9k_hw_process_ini(ah, chan);
1491 if (r)
1492 return r;
1493
1494 /*
1495 * Some AR91xx SoC devices frequently fail to accept TSF writes
1496 * right after the chip reset. When that happens, write a new
1497 * value after the initvals have been applied, with an offset
1498 * based on measured time difference
1499 */
1500 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1501 tsf += 1500;
1502 ath9k_hw_settsf64(ah, tsf);
1503 }
1504
1505 /* Setup MFP options for CCMP */
1506 if (AR_SREV_9280_20_OR_LATER(ah)) {
1507 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1508 * frames when constructing CCMP AAD. */
1509 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1510 0xc7ff);
1511 ah->sw_mgmt_crypto = false;
1512 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1513 /* Disable hardware crypto for management frames */
1514 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1515 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1516 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1517 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1518 ah->sw_mgmt_crypto = true;
1519 } else
1520 ah->sw_mgmt_crypto = true;
1521
1522 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1523 ath9k_hw_set_delta_slope(ah, chan);
1524
1525 ath9k_hw_spur_mitigate_freq(ah, chan);
1526 ah->eep_ops->set_board_values(ah, chan);
1527
1528 ENABLE_REGWRITE_BUFFER(ah);
1529
1530 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1531 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1532 | macStaId1
1533 | AR_STA_ID1_RTS_USE_DEF
1534 | (ah->config.
1535 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1536 | ah->sta_id1_defaults);
1537 ath_hw_setbssidmask(common);
1538 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1539 ath9k_hw_write_associd(ah);
1540 REG_WRITE(ah, AR_ISR, ~0);
1541 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1542
1543 REGWRITE_BUFFER_FLUSH(ah);
1544
1545 ath9k_hw_set_operating_mode(ah, ah->opmode);
1546
1547 r = ath9k_hw_rf_set_freq(ah, chan);
1548 if (r)
1549 return r;
1550
1551 ath9k_hw_set_clockrate(ah);
1552
1553 ENABLE_REGWRITE_BUFFER(ah);
1554
1555 for (i = 0; i < AR_NUM_DCU; i++)
1556 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1557
1558 REGWRITE_BUFFER_FLUSH(ah);
1559
1560 ah->intr_txqs = 0;
1561 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1562 ath9k_hw_resettxqueue(ah, i);
1563
1564 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1565 ath9k_hw_ani_cache_ini_regs(ah);
1566 ath9k_hw_init_qos(ah);
1567
1568 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1569 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1570
1571 ath9k_hw_init_global_settings(ah);
1572
1573 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1574 ar9002_hw_update_async_fifo(ah);
1575 ar9002_hw_enable_wep_aggregation(ah);
1576 }
1577
1578 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1579
1580 ath9k_hw_set_dma(ah);
1581
1582 REG_WRITE(ah, AR_OBS, 8);
1583
1584 if (ah->config.rx_intr_mitigation) {
1585 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1586 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1587 }
1588
1589 if (ah->config.tx_intr_mitigation) {
1590 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1591 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1592 }
1593
1594 ath9k_hw_init_bb(ah, chan);
1595
1596 if (!ath9k_hw_init_cal(ah, chan))
1597 return -EIO;
1598
1599 ENABLE_REGWRITE_BUFFER(ah);
1600
1601 ath9k_hw_restore_chainmask(ah);
1602 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1603
1604 REGWRITE_BUFFER_FLUSH(ah);
1605
1606 /*
1607 * For big endian systems turn on swapping for descriptors
1608 */
1609 if (AR_SREV_9100(ah)) {
1610 u32 mask;
1611 mask = REG_READ(ah, AR_CFG);
1612 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1613 ath_dbg(common, ATH_DBG_RESET,
1614 "CFG Byte Swap Set 0x%x\n", mask);
1615 } else {
1616 mask =
1617 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1618 REG_WRITE(ah, AR_CFG, mask);
1619 ath_dbg(common, ATH_DBG_RESET,
1620 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1621 }
1622 } else {
1623 if (common->bus_ops->ath_bus_type == ATH_USB) {
1624 /* Configure AR9271 target WLAN */
1625 if (AR_SREV_9271(ah))
1626 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1627 else
1628 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1629 }
1630 #ifdef __BIG_ENDIAN
1631 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1632 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1633 else
1634 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1635 #endif
1636 }
1637
1638 if (ah->btcoex_hw.enabled)
1639 ath9k_hw_btcoex_enable(ah);
1640
1641 if (AR_SREV_9300_20_OR_LATER(ah)) {
1642 ar9003_hw_bb_watchdog_config(ah);
1643
1644 ar9003_hw_disable_phy_restart(ah);
1645 }
1646
1647 ath9k_hw_apply_gpio_override(ah);
1648
1649 return 0;
1650 }
1651 EXPORT_SYMBOL(ath9k_hw_reset);
1652
1653 /******************************/
1654 /* Power Management (Chipset) */
1655 /******************************/
1656
1657 /*
1658 * Notify Power Mgt is disabled in self-generated frames.
1659 * If requested, force chip to sleep.
1660 */
1661 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1662 {
1663 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1664 if (setChip) {
1665 /*
1666 * Clear the RTC force wake bit to allow the
1667 * mac to go to sleep.
1668 */
1669 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1670 AR_RTC_FORCE_WAKE_EN);
1671 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1672 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1673
1674 /* Shutdown chip. Active low */
1675 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1676 REG_CLR_BIT(ah, (AR_RTC_RESET),
1677 AR_RTC_RESET_EN);
1678 }
1679
1680 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1681 if (AR_SREV_9300_20_OR_LATER(ah))
1682 REG_WRITE(ah, AR_WA,
1683 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1684 }
1685
1686 /*
1687 * Notify Power Management is enabled in self-generating
1688 * frames. If request, set power mode of chip to
1689 * auto/normal. Duration in units of 128us (1/8 TU).
1690 */
1691 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1692 {
1693 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1694 if (setChip) {
1695 struct ath9k_hw_capabilities *pCap = &ah->caps;
1696
1697 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1698 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1699 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1700 AR_RTC_FORCE_WAKE_ON_INT);
1701 } else {
1702 /*
1703 * Clear the RTC force wake bit to allow the
1704 * mac to go to sleep.
1705 */
1706 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1707 AR_RTC_FORCE_WAKE_EN);
1708 }
1709 }
1710
1711 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1712 if (AR_SREV_9300_20_OR_LATER(ah))
1713 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1714 }
1715
1716 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1717 {
1718 u32 val;
1719 int i;
1720
1721 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1722 if (AR_SREV_9300_20_OR_LATER(ah)) {
1723 REG_WRITE(ah, AR_WA, ah->WARegVal);
1724 udelay(10);
1725 }
1726
1727 if (setChip) {
1728 if ((REG_READ(ah, AR_RTC_STATUS) &
1729 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1730 if (ath9k_hw_set_reset_reg(ah,
1731 ATH9K_RESET_POWER_ON) != true) {
1732 return false;
1733 }
1734 if (!AR_SREV_9300_20_OR_LATER(ah))
1735 ath9k_hw_init_pll(ah, NULL);
1736 }
1737 if (AR_SREV_9100(ah))
1738 REG_SET_BIT(ah, AR_RTC_RESET,
1739 AR_RTC_RESET_EN);
1740
1741 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1742 AR_RTC_FORCE_WAKE_EN);
1743 udelay(50);
1744
1745 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1746 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1747 if (val == AR_RTC_STATUS_ON)
1748 break;
1749 udelay(50);
1750 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1751 AR_RTC_FORCE_WAKE_EN);
1752 }
1753 if (i == 0) {
1754 ath_err(ath9k_hw_common(ah),
1755 "Failed to wakeup in %uus\n",
1756 POWER_UP_TIME / 20);
1757 return false;
1758 }
1759 }
1760
1761 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1762
1763 return true;
1764 }
1765
1766 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1767 {
1768 struct ath_common *common = ath9k_hw_common(ah);
1769 int status = true, setChip = true;
1770 static const char *modes[] = {
1771 "AWAKE",
1772 "FULL-SLEEP",
1773 "NETWORK SLEEP",
1774 "UNDEFINED"
1775 };
1776
1777 if (ah->power_mode == mode)
1778 return status;
1779
1780 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1781 modes[ah->power_mode], modes[mode]);
1782
1783 switch (mode) {
1784 case ATH9K_PM_AWAKE:
1785 status = ath9k_hw_set_power_awake(ah, setChip);
1786 break;
1787 case ATH9K_PM_FULL_SLEEP:
1788 ath9k_set_power_sleep(ah, setChip);
1789 ah->chip_fullsleep = true;
1790 break;
1791 case ATH9K_PM_NETWORK_SLEEP:
1792 ath9k_set_power_network_sleep(ah, setChip);
1793 break;
1794 default:
1795 ath_err(common, "Unknown power mode %u\n", mode);
1796 return false;
1797 }
1798 ah->power_mode = mode;
1799
1800 /*
1801 * XXX: If this warning never comes up after a while then
1802 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1803 * ath9k_hw_setpower() return type void.
1804 */
1805
1806 if (!(ah->ah_flags & AH_UNPLUGGED))
1807 ATH_DBG_WARN_ON_ONCE(!status);
1808
1809 return status;
1810 }
1811 EXPORT_SYMBOL(ath9k_hw_setpower);
1812
1813 /*******************/
1814 /* Beacon Handling */
1815 /*******************/
1816
1817 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1818 {
1819 int flags = 0;
1820
1821 ENABLE_REGWRITE_BUFFER(ah);
1822
1823 switch (ah->opmode) {
1824 case NL80211_IFTYPE_ADHOC:
1825 case NL80211_IFTYPE_MESH_POINT:
1826 REG_SET_BIT(ah, AR_TXCFG,
1827 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1828 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1829 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1830 flags |= AR_NDP_TIMER_EN;
1831 case NL80211_IFTYPE_AP:
1832 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1833 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1834 TU_TO_USEC(ah->config.dma_beacon_response_time));
1835 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1836 TU_TO_USEC(ah->config.sw_beacon_response_time));
1837 flags |=
1838 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1839 break;
1840 default:
1841 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1842 "%s: unsupported opmode: %d\n",
1843 __func__, ah->opmode);
1844 return;
1845 break;
1846 }
1847
1848 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1849 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1850 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1851 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1852
1853 REGWRITE_BUFFER_FLUSH(ah);
1854
1855 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1856 }
1857 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1858
1859 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1860 const struct ath9k_beacon_state *bs)
1861 {
1862 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1863 struct ath9k_hw_capabilities *pCap = &ah->caps;
1864 struct ath_common *common = ath9k_hw_common(ah);
1865
1866 ENABLE_REGWRITE_BUFFER(ah);
1867
1868 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1869
1870 REG_WRITE(ah, AR_BEACON_PERIOD,
1871 TU_TO_USEC(bs->bs_intval));
1872 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1873 TU_TO_USEC(bs->bs_intval));
1874
1875 REGWRITE_BUFFER_FLUSH(ah);
1876
1877 REG_RMW_FIELD(ah, AR_RSSI_THR,
1878 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1879
1880 beaconintval = bs->bs_intval;
1881
1882 if (bs->bs_sleepduration > beaconintval)
1883 beaconintval = bs->bs_sleepduration;
1884
1885 dtimperiod = bs->bs_dtimperiod;
1886 if (bs->bs_sleepduration > dtimperiod)
1887 dtimperiod = bs->bs_sleepduration;
1888
1889 if (beaconintval == dtimperiod)
1890 nextTbtt = bs->bs_nextdtim;
1891 else
1892 nextTbtt = bs->bs_nexttbtt;
1893
1894 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1895 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1896 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1897 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1898
1899 ENABLE_REGWRITE_BUFFER(ah);
1900
1901 REG_WRITE(ah, AR_NEXT_DTIM,
1902 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1903 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1904
1905 REG_WRITE(ah, AR_SLEEP1,
1906 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1907 | AR_SLEEP1_ASSUME_DTIM);
1908
1909 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1910 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1911 else
1912 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1913
1914 REG_WRITE(ah, AR_SLEEP2,
1915 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1916
1917 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1918 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1919
1920 REGWRITE_BUFFER_FLUSH(ah);
1921
1922 REG_SET_BIT(ah, AR_TIMER_MODE,
1923 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1924 AR_DTIM_TIMER_EN);
1925
1926 /* TSF Out of Range Threshold */
1927 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1928 }
1929 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1930
1931 /*******************/
1932 /* HW Capabilities */
1933 /*******************/
1934
1935 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1936 {
1937 struct ath9k_hw_capabilities *pCap = &ah->caps;
1938 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1939 struct ath_common *common = ath9k_hw_common(ah);
1940 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1941
1942 u16 eeval;
1943 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1944
1945 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1946 regulatory->current_rd = eeval;
1947
1948 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1949 if (AR_SREV_9285_12_OR_LATER(ah))
1950 eeval |= AR9285_RDEXT_DEFAULT;
1951 regulatory->current_rd_ext = eeval;
1952
1953 if (ah->opmode != NL80211_IFTYPE_AP &&
1954 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1955 if (regulatory->current_rd == 0x64 ||
1956 regulatory->current_rd == 0x65)
1957 regulatory->current_rd += 5;
1958 else if (regulatory->current_rd == 0x41)
1959 regulatory->current_rd = 0x43;
1960 ath_dbg(common, ATH_DBG_REGULATORY,
1961 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1962 }
1963
1964 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1965 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1966 ath_err(common,
1967 "no band has been marked as supported in EEPROM\n");
1968 return -EINVAL;
1969 }
1970
1971 if (eeval & AR5416_OPFLAGS_11A)
1972 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1973
1974 if (eeval & AR5416_OPFLAGS_11G)
1975 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1976
1977 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1978 /*
1979 * For AR9271 we will temporarilly uses the rx chainmax as read from
1980 * the EEPROM.
1981 */
1982 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1983 !(eeval & AR5416_OPFLAGS_11A) &&
1984 !(AR_SREV_9271(ah)))
1985 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1986 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1987 else if (AR_SREV_9100(ah))
1988 pCap->rx_chainmask = 0x7;
1989 else
1990 /* Use rx_chainmask from EEPROM. */
1991 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1992
1993 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1994
1995 /* enable key search for every frame in an aggregate */
1996 if (AR_SREV_9300_20_OR_LATER(ah))
1997 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1998
1999 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2000
2001 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2002 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2003 else
2004 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2005
2006 if (AR_SREV_9271(ah))
2007 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2008 else if (AR_DEVID_7010(ah))
2009 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2010 else if (AR_SREV_9285_12_OR_LATER(ah))
2011 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2012 else if (AR_SREV_9280_20_OR_LATER(ah))
2013 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2014 else
2015 pCap->num_gpio_pins = AR_NUM_GPIO;
2016
2017 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2018 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2019 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2020 } else {
2021 pCap->rts_aggr_limit = (8 * 1024);
2022 }
2023
2024 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2025 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2026 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2027 ah->rfkill_gpio =
2028 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2029 ah->rfkill_polarity =
2030 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2031
2032 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2033 }
2034 #endif
2035 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2036 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2037 else
2038 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2039
2040 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2041 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2042 else
2043 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2044
2045 if (common->btcoex_enabled) {
2046 if (AR_SREV_9300_20_OR_LATER(ah)) {
2047 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2048 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2049 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2050 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2051 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2052 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2053 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2054
2055 if (AR_SREV_9285(ah)) {
2056 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2057 btcoex_hw->btpriority_gpio =
2058 ATH_BTPRIORITY_GPIO_9285;
2059 } else {
2060 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2061 }
2062 }
2063 } else {
2064 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2065 }
2066
2067 if (AR_SREV_9300_20_OR_LATER(ah)) {
2068 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2069 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2070 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2071
2072 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2073 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2074 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2075 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2076 pCap->txs_len = sizeof(struct ar9003_txs);
2077 if (!ah->config.paprd_disable &&
2078 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2079 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2080 } else {
2081 pCap->tx_desc_len = sizeof(struct ath_desc);
2082 if (AR_SREV_9280_20(ah))
2083 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2084 }
2085
2086 if (AR_SREV_9300_20_OR_LATER(ah))
2087 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2088
2089 if (AR_SREV_9300_20_OR_LATER(ah))
2090 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2091
2092 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2093 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2094
2095 if (AR_SREV_9285(ah))
2096 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2097 ant_div_ctl1 =
2098 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2099 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2100 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2101 }
2102 if (AR_SREV_9300_20_OR_LATER(ah)) {
2103 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2104 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2105 }
2106
2107
2108 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2109 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2110 /*
2111 * enable the diversity-combining algorithm only when
2112 * both enable_lna_div and enable_fast_div are set
2113 * Table for Diversity
2114 * ant_div_alt_lnaconf bit 0-1
2115 * ant_div_main_lnaconf bit 2-3
2116 * ant_div_alt_gaintb bit 4
2117 * ant_div_main_gaintb bit 5
2118 * enable_ant_div_lnadiv bit 6
2119 * enable_ant_fast_div bit 7
2120 */
2121 if ((ant_div_ctl1 >> 0x6) == 0x3)
2122 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2123 }
2124
2125 if (AR_SREV_9485_10(ah)) {
2126 pCap->pcie_lcr_extsync_en = true;
2127 pCap->pcie_lcr_offset = 0x80;
2128 }
2129
2130 tx_chainmask = pCap->tx_chainmask;
2131 rx_chainmask = pCap->rx_chainmask;
2132 while (tx_chainmask || rx_chainmask) {
2133 if (tx_chainmask & BIT(0))
2134 pCap->max_txchains++;
2135 if (rx_chainmask & BIT(0))
2136 pCap->max_rxchains++;
2137
2138 tx_chainmask >>= 1;
2139 rx_chainmask >>= 1;
2140 }
2141
2142 return 0;
2143 }
2144
2145 /****************************/
2146 /* GPIO / RFKILL / Antennae */
2147 /****************************/
2148
2149 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2150 u32 gpio, u32 type)
2151 {
2152 int addr;
2153 u32 gpio_shift, tmp;
2154
2155 if (gpio > 11)
2156 addr = AR_GPIO_OUTPUT_MUX3;
2157 else if (gpio > 5)
2158 addr = AR_GPIO_OUTPUT_MUX2;
2159 else
2160 addr = AR_GPIO_OUTPUT_MUX1;
2161
2162 gpio_shift = (gpio % 6) * 5;
2163
2164 if (AR_SREV_9280_20_OR_LATER(ah)
2165 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2166 REG_RMW(ah, addr, (type << gpio_shift),
2167 (0x1f << gpio_shift));
2168 } else {
2169 tmp = REG_READ(ah, addr);
2170 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2171 tmp &= ~(0x1f << gpio_shift);
2172 tmp |= (type << gpio_shift);
2173 REG_WRITE(ah, addr, tmp);
2174 }
2175 }
2176
2177 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2178 {
2179 u32 gpio_shift;
2180
2181 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2182
2183 if (AR_DEVID_7010(ah)) {
2184 gpio_shift = gpio;
2185 REG_RMW(ah, AR7010_GPIO_OE,
2186 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2187 (AR7010_GPIO_OE_MASK << gpio_shift));
2188 return;
2189 }
2190
2191 gpio_shift = gpio << 1;
2192 REG_RMW(ah,
2193 AR_GPIO_OE_OUT,
2194 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2195 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2196 }
2197 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2198
2199 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2200 {
2201 #define MS_REG_READ(x, y) \
2202 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2203
2204 if (gpio >= ah->caps.num_gpio_pins)
2205 return 0xffffffff;
2206
2207 if (AR_DEVID_7010(ah)) {
2208 u32 val;
2209 val = REG_READ(ah, AR7010_GPIO_IN);
2210 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2211 } else if (AR_SREV_9300_20_OR_LATER(ah))
2212 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2213 AR_GPIO_BIT(gpio)) != 0;
2214 else if (AR_SREV_9271(ah))
2215 return MS_REG_READ(AR9271, gpio) != 0;
2216 else if (AR_SREV_9287_11_OR_LATER(ah))
2217 return MS_REG_READ(AR9287, gpio) != 0;
2218 else if (AR_SREV_9285_12_OR_LATER(ah))
2219 return MS_REG_READ(AR9285, gpio) != 0;
2220 else if (AR_SREV_9280_20_OR_LATER(ah))
2221 return MS_REG_READ(AR928X, gpio) != 0;
2222 else
2223 return MS_REG_READ(AR, gpio) != 0;
2224 }
2225 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2226
2227 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2228 u32 ah_signal_type)
2229 {
2230 u32 gpio_shift;
2231
2232 if (AR_DEVID_7010(ah)) {
2233 gpio_shift = gpio;
2234 REG_RMW(ah, AR7010_GPIO_OE,
2235 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2236 (AR7010_GPIO_OE_MASK << gpio_shift));
2237 return;
2238 }
2239
2240 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2241 gpio_shift = 2 * gpio;
2242 REG_RMW(ah,
2243 AR_GPIO_OE_OUT,
2244 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2245 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2246 }
2247 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2248
2249 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2250 {
2251 if (AR_DEVID_7010(ah)) {
2252 val = val ? 0 : 1;
2253 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2254 AR_GPIO_BIT(gpio));
2255 return;
2256 }
2257
2258 if (AR_SREV_9271(ah))
2259 val = ~val;
2260
2261 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2262 AR_GPIO_BIT(gpio));
2263 }
2264 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2265
2266 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2267 {
2268 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2269 }
2270 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2271
2272 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2273 {
2274 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2275 }
2276 EXPORT_SYMBOL(ath9k_hw_setantenna);
2277
2278 /*********************/
2279 /* General Operation */
2280 /*********************/
2281
2282 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2283 {
2284 u32 bits = REG_READ(ah, AR_RX_FILTER);
2285 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2286
2287 if (phybits & AR_PHY_ERR_RADAR)
2288 bits |= ATH9K_RX_FILTER_PHYRADAR;
2289 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2290 bits |= ATH9K_RX_FILTER_PHYERR;
2291
2292 return bits;
2293 }
2294 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2295
2296 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2297 {
2298 u32 phybits;
2299
2300 ENABLE_REGWRITE_BUFFER(ah);
2301
2302 REG_WRITE(ah, AR_RX_FILTER, bits);
2303
2304 phybits = 0;
2305 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2306 phybits |= AR_PHY_ERR_RADAR;
2307 if (bits & ATH9K_RX_FILTER_PHYERR)
2308 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2309 REG_WRITE(ah, AR_PHY_ERR, phybits);
2310
2311 if (phybits)
2312 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2313 else
2314 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2315
2316 REGWRITE_BUFFER_FLUSH(ah);
2317 }
2318 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2319
2320 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2321 {
2322 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2323 return false;
2324
2325 ath9k_hw_init_pll(ah, NULL);
2326 return true;
2327 }
2328 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2329
2330 bool ath9k_hw_disable(struct ath_hw *ah)
2331 {
2332 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2333 return false;
2334
2335 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2336 return false;
2337
2338 ath9k_hw_init_pll(ah, NULL);
2339 return true;
2340 }
2341 EXPORT_SYMBOL(ath9k_hw_disable);
2342
2343 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2344 {
2345 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2346 struct ath9k_channel *chan = ah->curchan;
2347 struct ieee80211_channel *channel = chan->chan;
2348
2349 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2350
2351 ah->eep_ops->set_txpower(ah, chan,
2352 ath9k_regd_get_ctl(regulatory, chan),
2353 channel->max_antenna_gain * 2,
2354 channel->max_power * 2,
2355 min((u32) MAX_RATE_POWER,
2356 (u32) regulatory->power_limit), test);
2357 }
2358 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2359
2360 void ath9k_hw_setopmode(struct ath_hw *ah)
2361 {
2362 ath9k_hw_set_operating_mode(ah, ah->opmode);
2363 }
2364 EXPORT_SYMBOL(ath9k_hw_setopmode);
2365
2366 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2367 {
2368 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2369 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2370 }
2371 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2372
2373 void ath9k_hw_write_associd(struct ath_hw *ah)
2374 {
2375 struct ath_common *common = ath9k_hw_common(ah);
2376
2377 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2378 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2379 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2380 }
2381 EXPORT_SYMBOL(ath9k_hw_write_associd);
2382
2383 #define ATH9K_MAX_TSF_READ 10
2384
2385 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2386 {
2387 u32 tsf_lower, tsf_upper1, tsf_upper2;
2388 int i;
2389
2390 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2391 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2392 tsf_lower = REG_READ(ah, AR_TSF_L32);
2393 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2394 if (tsf_upper2 == tsf_upper1)
2395 break;
2396 tsf_upper1 = tsf_upper2;
2397 }
2398
2399 WARN_ON( i == ATH9K_MAX_TSF_READ );
2400
2401 return (((u64)tsf_upper1 << 32) | tsf_lower);
2402 }
2403 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2404
2405 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2406 {
2407 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2408 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2409 }
2410 EXPORT_SYMBOL(ath9k_hw_settsf64);
2411
2412 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2413 {
2414 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2415 AH_TSF_WRITE_TIMEOUT))
2416 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2417 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2418
2419 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2420 }
2421 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2422
2423 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2424 {
2425 if (setting)
2426 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2427 else
2428 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2429 }
2430 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2431
2432 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2433 {
2434 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2435 u32 macmode;
2436
2437 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2438 macmode = AR_2040_JOINED_RX_CLEAR;
2439 else
2440 macmode = 0;
2441
2442 REG_WRITE(ah, AR_2040_MODE, macmode);
2443 }
2444
2445 /* HW Generic timers configuration */
2446
2447 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2448 {
2449 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2450 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2451 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2452 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2453 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2454 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2455 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2456 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2457 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2458 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2459 AR_NDP2_TIMER_MODE, 0x0002},
2460 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2461 AR_NDP2_TIMER_MODE, 0x0004},
2462 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2463 AR_NDP2_TIMER_MODE, 0x0008},
2464 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2465 AR_NDP2_TIMER_MODE, 0x0010},
2466 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2467 AR_NDP2_TIMER_MODE, 0x0020},
2468 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2469 AR_NDP2_TIMER_MODE, 0x0040},
2470 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2471 AR_NDP2_TIMER_MODE, 0x0080}
2472 };
2473
2474 /* HW generic timer primitives */
2475
2476 /* compute and clear index of rightmost 1 */
2477 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2478 {
2479 u32 b;
2480
2481 b = *mask;
2482 b &= (0-b);
2483 *mask &= ~b;
2484 b *= debruijn32;
2485 b >>= 27;
2486
2487 return timer_table->gen_timer_index[b];
2488 }
2489
2490 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2491 {
2492 return REG_READ(ah, AR_TSF_L32);
2493 }
2494 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2495
2496 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2497 void (*trigger)(void *),
2498 void (*overflow)(void *),
2499 void *arg,
2500 u8 timer_index)
2501 {
2502 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2503 struct ath_gen_timer *timer;
2504
2505 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2506
2507 if (timer == NULL) {
2508 ath_err(ath9k_hw_common(ah),
2509 "Failed to allocate memory for hw timer[%d]\n",
2510 timer_index);
2511 return NULL;
2512 }
2513
2514 /* allocate a hardware generic timer slot */
2515 timer_table->timers[timer_index] = timer;
2516 timer->index = timer_index;
2517 timer->trigger = trigger;
2518 timer->overflow = overflow;
2519 timer->arg = arg;
2520
2521 return timer;
2522 }
2523 EXPORT_SYMBOL(ath_gen_timer_alloc);
2524
2525 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2526 struct ath_gen_timer *timer,
2527 u32 trig_timeout,
2528 u32 timer_period)
2529 {
2530 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2531 u32 tsf, timer_next;
2532
2533 BUG_ON(!timer_period);
2534
2535 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2536
2537 tsf = ath9k_hw_gettsf32(ah);
2538
2539 timer_next = tsf + trig_timeout;
2540
2541 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2542 "current tsf %x period %x timer_next %x\n",
2543 tsf, timer_period, timer_next);
2544
2545 /*
2546 * Program generic timer registers
2547 */
2548 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2549 timer_next);
2550 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2551 timer_period);
2552 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2553 gen_tmr_configuration[timer->index].mode_mask);
2554
2555 /* Enable both trigger and thresh interrupt masks */
2556 REG_SET_BIT(ah, AR_IMR_S5,
2557 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2558 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2559 }
2560 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2561
2562 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2563 {
2564 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2565
2566 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2567 (timer->index >= ATH_MAX_GEN_TIMER)) {
2568 return;
2569 }
2570
2571 /* Clear generic timer enable bits. */
2572 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2573 gen_tmr_configuration[timer->index].mode_mask);
2574
2575 /* Disable both trigger and thresh interrupt masks */
2576 REG_CLR_BIT(ah, AR_IMR_S5,
2577 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2578 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2579
2580 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2581 }
2582 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2583
2584 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2585 {
2586 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2587
2588 /* free the hardware generic timer slot */
2589 timer_table->timers[timer->index] = NULL;
2590 kfree(timer);
2591 }
2592 EXPORT_SYMBOL(ath_gen_timer_free);
2593
2594 /*
2595 * Generic Timer Interrupts handling
2596 */
2597 void ath_gen_timer_isr(struct ath_hw *ah)
2598 {
2599 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2600 struct ath_gen_timer *timer;
2601 struct ath_common *common = ath9k_hw_common(ah);
2602 u32 trigger_mask, thresh_mask, index;
2603
2604 /* get hardware generic timer interrupt status */
2605 trigger_mask = ah->intr_gen_timer_trigger;
2606 thresh_mask = ah->intr_gen_timer_thresh;
2607 trigger_mask &= timer_table->timer_mask.val;
2608 thresh_mask &= timer_table->timer_mask.val;
2609
2610 trigger_mask &= ~thresh_mask;
2611
2612 while (thresh_mask) {
2613 index = rightmost_index(timer_table, &thresh_mask);
2614 timer = timer_table->timers[index];
2615 BUG_ON(!timer);
2616 ath_dbg(common, ATH_DBG_HWTIMER,
2617 "TSF overflow for Gen timer %d\n", index);
2618 timer->overflow(timer->arg);
2619 }
2620
2621 while (trigger_mask) {
2622 index = rightmost_index(timer_table, &trigger_mask);
2623 timer = timer_table->timers[index];
2624 BUG_ON(!timer);
2625 ath_dbg(common, ATH_DBG_HWTIMER,
2626 "Gen timer[%d] trigger\n", index);
2627 timer->trigger(timer->arg);
2628 }
2629 }
2630 EXPORT_SYMBOL(ath_gen_timer_isr);
2631
2632 /********/
2633 /* HTC */
2634 /********/
2635
2636 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2637 {
2638 ah->htc_reset_init = true;
2639 }
2640 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2641
2642 static struct {
2643 u32 version;
2644 const char * name;
2645 } ath_mac_bb_names[] = {
2646 /* Devices with external radios */
2647 { AR_SREV_VERSION_5416_PCI, "5416" },
2648 { AR_SREV_VERSION_5416_PCIE, "5418" },
2649 { AR_SREV_VERSION_9100, "9100" },
2650 { AR_SREV_VERSION_9160, "9160" },
2651 /* Single-chip solutions */
2652 { AR_SREV_VERSION_9280, "9280" },
2653 { AR_SREV_VERSION_9285, "9285" },
2654 { AR_SREV_VERSION_9287, "9287" },
2655 { AR_SREV_VERSION_9271, "9271" },
2656 { AR_SREV_VERSION_9300, "9300" },
2657 { AR_SREV_VERSION_9330, "9330" },
2658 { AR_SREV_VERSION_9485, "9485" },
2659 };
2660
2661 /* For devices with external radios */
2662 static struct {
2663 u16 version;
2664 const char * name;
2665 } ath_rf_names[] = {
2666 { 0, "5133" },
2667 { AR_RAD5133_SREV_MAJOR, "5133" },
2668 { AR_RAD5122_SREV_MAJOR, "5122" },
2669 { AR_RAD2133_SREV_MAJOR, "2133" },
2670 { AR_RAD2122_SREV_MAJOR, "2122" }
2671 };
2672
2673 /*
2674 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2675 */
2676 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2677 {
2678 int i;
2679
2680 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2681 if (ath_mac_bb_names[i].version == mac_bb_version) {
2682 return ath_mac_bb_names[i].name;
2683 }
2684 }
2685
2686 return "????";
2687 }
2688
2689 /*
2690 * Return the RF name. "????" is returned if the RF is unknown.
2691 * Used for devices with external radios.
2692 */
2693 static const char *ath9k_hw_rf_name(u16 rf_version)
2694 {
2695 int i;
2696
2697 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2698 if (ath_rf_names[i].version == rf_version) {
2699 return ath_rf_names[i].name;
2700 }
2701 }
2702
2703 return "????";
2704 }
2705
2706 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2707 {
2708 int used;
2709
2710 /* chipsets >= AR9280 are single-chip */
2711 if (AR_SREV_9280_20_OR_LATER(ah)) {
2712 used = snprintf(hw_name, len,
2713 "Atheros AR%s Rev:%x",
2714 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2715 ah->hw_version.macRev);
2716 }
2717 else {
2718 used = snprintf(hw_name, len,
2719 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2720 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2721 ah->hw_version.macRev,
2722 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2723 AR_RADIO_SREV_MAJOR)),
2724 ah->hw_version.phyRev);
2725 }
2726
2727 hw_name[used] = '\0';
2728 }
2729 EXPORT_SYMBOL(ath9k_hw_name);
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