2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <linux/bitops.h>
22 #include <linux/etherdevice.h>
23 #include <asm/unaligned.h>
27 #include "ar9003_mac.h"
28 #include "ar9003_mci.h"
29 #include "ar9003_phy.h"
32 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
39 static void ath9k_hw_set_clockrate(struct ath_hw
*ah
)
41 struct ath_common
*common
= ath9k_hw_common(ah
);
42 struct ath9k_channel
*chan
= ah
->curchan
;
43 unsigned int clockrate
;
45 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
46 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
))
48 else if (!chan
) /* should really check for CCK instead */
49 clockrate
= ATH9K_CLOCK_RATE_CCK
;
50 else if (IS_CHAN_2GHZ(chan
))
51 clockrate
= ATH9K_CLOCK_RATE_2GHZ_OFDM
;
52 else if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_FASTCLOCK
)
53 clockrate
= ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM
;
55 clockrate
= ATH9K_CLOCK_RATE_5GHZ_OFDM
;
58 if (IS_CHAN_HT40(chan
))
60 if (IS_CHAN_HALF_RATE(chan
))
62 if (IS_CHAN_QUARTER_RATE(chan
))
66 common
->clockrate
= clockrate
;
69 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
71 struct ath_common
*common
= ath9k_hw_common(ah
);
73 return usecs
* common
->clockrate
;
76 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
80 BUG_ON(timeout
< AH_TIME_QUANTUM
);
82 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
83 if ((REG_READ(ah
, reg
) & mask
) == val
)
86 udelay(AH_TIME_QUANTUM
);
89 ath_dbg(ath9k_hw_common(ah
), ANY
,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
95 EXPORT_SYMBOL(ath9k_hw_wait
);
97 void ath9k_hw_synth_delay(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
102 if (IS_CHAN_HALF_RATE(chan
))
104 else if (IS_CHAN_QUARTER_RATE(chan
))
107 udelay(hw_delay
+ BASE_ACTIVATE_DELAY
);
110 void ath9k_hw_write_array(struct ath_hw
*ah
, const struct ar5416IniArray
*array
,
111 int column
, unsigned int *writecnt
)
115 ENABLE_REGWRITE_BUFFER(ah
);
116 for (r
= 0; r
< array
->ia_rows
; r
++) {
117 REG_WRITE(ah
, INI_RA(array
, r
, 0),
118 INI_RA(array
, r
, column
));
121 REGWRITE_BUFFER_FLUSH(ah
);
124 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
129 for (i
= 0, retval
= 0; i
< n
; i
++) {
130 retval
= (retval
<< 1) | (val
& 1);
136 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
138 u32 frameLen
, u16 rateix
,
141 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
147 case WLAN_RC_PHY_CCK
:
148 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
151 numBits
= frameLen
<< 3;
152 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
154 case WLAN_RC_PHY_OFDM
:
155 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
156 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
157 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
158 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
159 txTime
= OFDM_SIFS_TIME_QUARTER
160 + OFDM_PREAMBLE_TIME_QUARTER
161 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
162 } else if (ah
->curchan
&&
163 IS_CHAN_HALF_RATE(ah
->curchan
)) {
164 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
165 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
166 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
167 txTime
= OFDM_SIFS_TIME_HALF
+
168 OFDM_PREAMBLE_TIME_HALF
169 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
171 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
172 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
173 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
174 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
175 + (numSymbols
* OFDM_SYMBOL_TIME
);
179 ath_err(ath9k_hw_common(ah
),
180 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
187 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
189 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
190 struct ath9k_channel
*chan
,
191 struct chan_centers
*centers
)
195 if (!IS_CHAN_HT40(chan
)) {
196 centers
->ctl_center
= centers
->ext_center
=
197 centers
->synth_center
= chan
->channel
;
201 if (IS_CHAN_HT40PLUS(chan
)) {
202 centers
->synth_center
=
203 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
206 centers
->synth_center
=
207 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
211 centers
->ctl_center
=
212 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
213 /* 25 MHz spacing is supported by hw but not on upper layers */
214 centers
->ext_center
=
215 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
222 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
226 if (ah
->get_mac_revision
)
227 ah
->hw_version
.macRev
= ah
->get_mac_revision();
229 switch (ah
->hw_version
.devid
) {
230 case AR5416_AR9100_DEVID
:
231 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
233 case AR9300_DEVID_AR9330
:
234 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9330
;
235 if (!ah
->get_mac_revision
) {
236 val
= REG_READ(ah
, AR_SREV
);
237 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
240 case AR9300_DEVID_AR9340
:
241 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9340
;
243 case AR9300_DEVID_QCA955X
:
244 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9550
;
246 case AR9300_DEVID_AR953X
:
247 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9531
;
251 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
254 val
= REG_READ(ah
, AR_SREV
);
255 ah
->hw_version
.macVersion
=
256 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
257 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
259 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
))
260 ah
->is_pciexpress
= true;
262 ah
->is_pciexpress
= (val
&
263 AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
265 if (!AR_SREV_9100(ah
))
266 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
268 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
270 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
271 ah
->is_pciexpress
= true;
275 /************************************/
276 /* HW Attach, Detach, Init Routines */
277 /************************************/
279 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
281 if (!AR_SREV_5416(ah
))
284 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
285 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
286 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
287 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
288 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
289 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
290 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
291 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
292 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
294 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
297 /* This should work for all families including legacy */
298 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
300 struct ath_common
*common
= ath9k_hw_common(ah
);
301 u32 regAddr
[2] = { AR_STA_ID0
};
303 static const u32 patternData
[4] = {
304 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
308 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
310 regAddr
[1] = AR_PHY_BASE
+ (8 << 2);
314 for (i
= 0; i
< loop_max
; i
++) {
315 u32 addr
= regAddr
[i
];
318 regHold
[i
] = REG_READ(ah
, addr
);
319 for (j
= 0; j
< 0x100; j
++) {
320 wrData
= (j
<< 16) | j
;
321 REG_WRITE(ah
, addr
, wrData
);
322 rdData
= REG_READ(ah
, addr
);
323 if (rdData
!= wrData
) {
325 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
326 addr
, wrData
, rdData
);
330 for (j
= 0; j
< 4; j
++) {
331 wrData
= patternData
[j
];
332 REG_WRITE(ah
, addr
, wrData
);
333 rdData
= REG_READ(ah
, addr
);
334 if (wrData
!= rdData
) {
336 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
337 addr
, wrData
, rdData
);
341 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
348 static void ath9k_hw_init_config(struct ath_hw
*ah
)
350 struct ath_common
*common
= ath9k_hw_common(ah
);
352 ah
->config
.dma_beacon_response_time
= 1;
353 ah
->config
.sw_beacon_response_time
= 6;
354 ah
->config
.cwm_ignore_extcca
= 0;
355 ah
->config
.analog_shiftreg
= 1;
357 ah
->config
.rx_intr_mitigation
= true;
359 if (AR_SREV_9300_20_OR_LATER(ah
)) {
360 ah
->config
.rimt_last
= 500;
361 ah
->config
.rimt_first
= 2000;
363 ah
->config
.rimt_last
= 250;
364 ah
->config
.rimt_first
= 700;
368 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
369 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
370 * This means we use it for all AR5416 devices, and the few
371 * minor PCI AR9280 devices out there.
373 * Serialization is required because these devices do not handle
374 * well the case of two concurrent reads/writes due to the latency
375 * involved. During one read/write another read/write can be issued
376 * on another CPU while the previous read/write may still be working
377 * on our hardware, if we hit this case the hardware poops in a loop.
378 * We prevent this by serializing reads and writes.
380 * This issue is not present on PCI-Express devices or pre-AR5416
381 * devices (legacy, 802.11abg).
383 if (num_possible_cpus() > 1)
384 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
386 if (NR_CPUS
> 1 && ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
387 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
388 ((AR_SREV_9160(ah
) || AR_SREV_9280(ah
) || AR_SREV_9287(ah
)) &&
389 !ah
->is_pciexpress
)) {
390 ah
->config
.serialize_regmode
= SER_REG_MODE_ON
;
392 ah
->config
.serialize_regmode
= SER_REG_MODE_OFF
;
396 ath_dbg(common
, RESET
, "serialize_regmode is %d\n",
397 ah
->config
.serialize_regmode
);
399 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
400 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
402 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
405 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
407 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
409 regulatory
->country_code
= CTRY_DEFAULT
;
410 regulatory
->power_limit
= MAX_RATE_POWER
;
412 ah
->hw_version
.magic
= AR5416_MAGIC
;
413 ah
->hw_version
.subvendorid
= 0;
415 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
|
416 AR_STA_ID1_MCAST_KSRCH
;
417 if (AR_SREV_9100(ah
))
418 ah
->sta_id1_defaults
|= AR_STA_ID1_AR9100_BA_FIX
;
420 ah
->slottime
= ATH9K_SLOT_TIME_9
;
421 ah
->globaltxtimeout
= (u32
) -1;
422 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
423 ah
->htc_reset_init
= true;
425 ah
->ani_function
= ATH9K_ANI_ALL
;
426 if (!AR_SREV_9300_20_OR_LATER(ah
))
427 ah
->ani_function
&= ~ATH9K_ANI_MRC_CCK
;
429 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
430 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
432 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
435 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
437 struct ath_common
*common
= ath9k_hw_common(ah
);
441 static const u32 EEP_MAC
[] = { EEP_MAC_LSW
, EEP_MAC_MID
, EEP_MAC_MSW
};
444 for (i
= 0; i
< 3; i
++) {
445 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_MAC
[i
]);
447 common
->macaddr
[2 * i
] = eeval
>> 8;
448 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
450 if (!is_valid_ether_addr(common
->macaddr
)) {
452 "eeprom contains invalid mac address: %pM\n",
455 random_ether_addr(common
->macaddr
);
457 "random mac address will be used: %pM\n",
464 static int ath9k_hw_post_init(struct ath_hw
*ah
)
466 struct ath_common
*common
= ath9k_hw_common(ah
);
469 if (common
->bus_ops
->ath_bus_type
!= ATH_USB
) {
470 if (!ath9k_hw_chip_test(ah
))
474 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
475 ecode
= ar9002_hw_rf_claim(ah
);
480 ecode
= ath9k_hw_eeprom_init(ah
);
484 ath_dbg(ath9k_hw_common(ah
), CONFIG
, "Eeprom VER: %d, REV: %d\n",
485 ah
->eep_ops
->get_eeprom_ver(ah
),
486 ah
->eep_ops
->get_eeprom_rev(ah
));
488 ath9k_hw_ani_init(ah
);
491 * EEPROM needs to be initialized before we do this.
492 * This is required for regulatory compliance.
494 if (AR_SREV_9300_20_OR_LATER(ah
)) {
495 u16 regdmn
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
496 if ((regdmn
& 0xF0) == CTL_FCC
) {
497 ah
->nf_2g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ
;
498 ah
->nf_5g
.max
= AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ
;
505 static int ath9k_hw_attach_ops(struct ath_hw
*ah
)
507 if (!AR_SREV_9300_20_OR_LATER(ah
))
508 return ar9002_hw_attach_ops(ah
);
510 ar9003_hw_attach_ops(ah
);
514 /* Called for all hardware families */
515 static int __ath9k_hw_init(struct ath_hw
*ah
)
517 struct ath_common
*common
= ath9k_hw_common(ah
);
520 ath9k_hw_read_revisions(ah
);
522 switch (ah
->hw_version
.macVersion
) {
523 case AR_SREV_VERSION_5416_PCI
:
524 case AR_SREV_VERSION_5416_PCIE
:
525 case AR_SREV_VERSION_9160
:
526 case AR_SREV_VERSION_9100
:
527 case AR_SREV_VERSION_9280
:
528 case AR_SREV_VERSION_9285
:
529 case AR_SREV_VERSION_9287
:
530 case AR_SREV_VERSION_9271
:
531 case AR_SREV_VERSION_9300
:
532 case AR_SREV_VERSION_9330
:
533 case AR_SREV_VERSION_9485
:
534 case AR_SREV_VERSION_9340
:
535 case AR_SREV_VERSION_9462
:
536 case AR_SREV_VERSION_9550
:
537 case AR_SREV_VERSION_9565
:
538 case AR_SREV_VERSION_9531
:
542 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
543 ah
->hw_version
.macVersion
, ah
->hw_version
.macRev
);
548 * Read back AR_WA into a permanent copy and set bits 14 and 17.
549 * We need to do this to avoid RMW of this register. We cannot
550 * read the reg when chip is asleep.
552 if (AR_SREV_9300_20_OR_LATER(ah
)) {
553 ah
->WARegVal
= REG_READ(ah
, AR_WA
);
554 ah
->WARegVal
|= (AR_WA_D3_L1_DISABLE
|
555 AR_WA_ASPM_TIMER_BASED_DISABLE
);
558 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
559 ath_err(common
, "Couldn't reset chip\n");
563 if (AR_SREV_9565(ah
)) {
564 ah
->WARegVal
|= AR_WA_BIT22
;
565 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
568 ath9k_hw_init_defaults(ah
);
569 ath9k_hw_init_config(ah
);
571 r
= ath9k_hw_attach_ops(ah
);
575 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
576 ath_err(common
, "Couldn't wakeup chip\n");
580 if (AR_SREV_9271(ah
) || AR_SREV_9100(ah
) || AR_SREV_9340(ah
) ||
581 AR_SREV_9330(ah
) || AR_SREV_9550(ah
))
582 ah
->is_pciexpress
= false;
584 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
585 ath9k_hw_init_cal_settings(ah
);
587 if (!ah
->is_pciexpress
)
588 ath9k_hw_disablepcie(ah
);
590 r
= ath9k_hw_post_init(ah
);
594 ath9k_hw_init_mode_gain_regs(ah
);
595 r
= ath9k_hw_fill_cap_info(ah
);
599 r
= ath9k_hw_init_macaddr(ah
);
601 ath_err(common
, "Failed to initialize MAC address\n");
605 ath9k_hw_init_hang_checks(ah
);
607 common
->state
= ATH_HW_INITIALIZED
;
612 int ath9k_hw_init(struct ath_hw
*ah
)
615 struct ath_common
*common
= ath9k_hw_common(ah
);
617 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
618 switch (ah
->hw_version
.devid
) {
619 case AR5416_DEVID_PCI
:
620 case AR5416_DEVID_PCIE
:
621 case AR5416_AR9100_DEVID
:
622 case AR9160_DEVID_PCI
:
623 case AR9280_DEVID_PCI
:
624 case AR9280_DEVID_PCIE
:
625 case AR9285_DEVID_PCIE
:
626 case AR9287_DEVID_PCI
:
627 case AR9287_DEVID_PCIE
:
628 case AR2427_DEVID_PCIE
:
629 case AR9300_DEVID_PCIE
:
630 case AR9300_DEVID_AR9485_PCIE
:
631 case AR9300_DEVID_AR9330
:
632 case AR9300_DEVID_AR9340
:
633 case AR9300_DEVID_QCA955X
:
634 case AR9300_DEVID_AR9580
:
635 case AR9300_DEVID_AR9462
:
636 case AR9485_DEVID_AR1111
:
637 case AR9300_DEVID_AR9565
:
638 case AR9300_DEVID_AR953X
:
641 if (common
->bus_ops
->ath_bus_type
== ATH_USB
)
643 ath_err(common
, "Hardware device ID 0x%04x not supported\n",
644 ah
->hw_version
.devid
);
648 ret
= __ath9k_hw_init(ah
);
651 "Unable to initialize hardware; initialization status: %d\n",
660 EXPORT_SYMBOL(ath9k_hw_init
);
662 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
664 ENABLE_REGWRITE_BUFFER(ah
);
666 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
667 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
669 REG_WRITE(ah
, AR_QOS_NO_ACK
,
670 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
671 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
672 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
674 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
675 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
676 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
677 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
678 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
680 REGWRITE_BUFFER_FLUSH(ah
);
683 u32
ar9003_get_pll_sqsum_dvc(struct ath_hw
*ah
)
685 struct ath_common
*common
= ath9k_hw_common(ah
);
688 REG_CLR_BIT(ah
, PLL3
, PLL3_DO_MEAS_MASK
);
690 REG_SET_BIT(ah
, PLL3
, PLL3_DO_MEAS_MASK
);
692 while ((REG_READ(ah
, PLL4
) & PLL4_MEAS_DONE
) == 0) {
696 if (WARN_ON_ONCE(i
>= 100)) {
697 ath_err(common
, "PLL4 meaurement not done\n");
704 return (REG_READ(ah
, PLL3
) & SQSUM_DVC_MASK
) >> 3;
706 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc
);
708 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
709 struct ath9k_channel
*chan
)
713 pll
= ath9k_hw_compute_pll_control(ah
, chan
);
715 if (AR_SREV_9485(ah
) || AR_SREV_9565(ah
)) {
716 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
717 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
718 AR_CH0_BB_DPLL2_PLL_PWD
, 0x1);
719 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
720 AR_CH0_DPLL2_KD
, 0x40);
721 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
722 AR_CH0_DPLL2_KI
, 0x4);
724 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
725 AR_CH0_BB_DPLL1_REFDIV
, 0x5);
726 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
727 AR_CH0_BB_DPLL1_NINI
, 0x58);
728 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
729 AR_CH0_BB_DPLL1_NFRAC
, 0x0);
731 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
732 AR_CH0_BB_DPLL2_OUTDIV
, 0x1);
733 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
734 AR_CH0_BB_DPLL2_LOCAL_PLL
, 0x1);
735 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
736 AR_CH0_BB_DPLL2_EN_NEGTRIG
, 0x1);
738 /* program BB PLL phase_shift to 0x6 */
739 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL3
,
740 AR_CH0_BB_DPLL3_PHASE_SHIFT
, 0x6);
742 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
743 AR_CH0_BB_DPLL2_PLL_PWD
, 0x0);
745 } else if (AR_SREV_9330(ah
)) {
746 u32 ddr_dpll2
, pll_control2
, kd
;
748 if (ah
->is_clk_25mhz
) {
749 ddr_dpll2
= 0x18e82f01;
750 pll_control2
= 0xe04a3d;
753 ddr_dpll2
= 0x19e82f01;
754 pll_control2
= 0x886666;
758 /* program DDR PLL ki and kd value */
759 REG_WRITE(ah
, AR_CH0_DDR_DPLL2
, ddr_dpll2
);
761 /* program DDR PLL phase_shift */
762 REG_RMW_FIELD(ah
, AR_CH0_DDR_DPLL3
,
763 AR_CH0_DPLL3_PHASE_SHIFT
, 0x1);
765 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
,
766 pll
| AR_RTC_9300_PLL_BYPASS
);
769 /* program refdiv, nint, frac to RTC register */
770 REG_WRITE(ah
, AR_RTC_PLL_CONTROL2
, pll_control2
);
772 /* program BB PLL kd and ki value */
773 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
, AR_CH0_DPLL2_KD
, kd
);
774 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
, AR_CH0_DPLL2_KI
, 0x06);
776 /* program BB PLL phase_shift */
777 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL3
,
778 AR_CH0_BB_DPLL3_PHASE_SHIFT
, 0x1);
779 } else if (AR_SREV_9340(ah
) || AR_SREV_9550(ah
) || AR_SREV_9531(ah
)) {
780 u32 regval
, pll2_divint
, pll2_divfrac
, refdiv
;
782 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
,
783 pll
| AR_RTC_9300_SOC_PLL_BYPASS
);
786 REG_SET_BIT(ah
, AR_PHY_PLL_MODE
, 0x1 << 16);
789 if (ah
->is_clk_25mhz
) {
790 if (AR_SREV_9531(ah
)) {
792 pll2_divfrac
= 0xa3d2;
796 pll2_divfrac
= 0x1eb85;
800 if (AR_SREV_9340(ah
)) {
807 AR_SREV_9531(ah
) ? 0x26665 : 0x26666;
812 regval
= REG_READ(ah
, AR_PHY_PLL_MODE
);
813 if (AR_SREV_9531(ah
))
814 regval
|= (0x1 << 22);
816 regval
|= (0x1 << 16);
817 REG_WRITE(ah
, AR_PHY_PLL_MODE
, regval
);
820 REG_WRITE(ah
, AR_PHY_PLL_CONTROL
, (refdiv
<< 27) |
821 (pll2_divint
<< 18) | pll2_divfrac
);
824 regval
= REG_READ(ah
, AR_PHY_PLL_MODE
);
825 if (AR_SREV_9340(ah
))
826 regval
= (regval
& 0x80071fff) |
831 else if (AR_SREV_9531(ah
))
832 regval
= (regval
& 0x01c00fff) |
839 regval
= (regval
& 0x80071fff) |
844 REG_WRITE(ah
, AR_PHY_PLL_MODE
, regval
);
846 if (AR_SREV_9531(ah
))
847 REG_WRITE(ah
, AR_PHY_PLL_MODE
,
848 REG_READ(ah
, AR_PHY_PLL_MODE
) & 0xffbfffff);
850 REG_WRITE(ah
, AR_PHY_PLL_MODE
,
851 REG_READ(ah
, AR_PHY_PLL_MODE
) & 0xfffeffff);
856 if (AR_SREV_9565(ah
))
858 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
860 if (AR_SREV_9485(ah
) || AR_SREV_9340(ah
) || AR_SREV_9330(ah
) ||
864 /* Switch the core clock for ar9271 to 117Mhz */
865 if (AR_SREV_9271(ah
)) {
867 REG_WRITE(ah
, 0x50040, 0x304);
870 udelay(RTC_PLL_SETTLE_DELAY
);
872 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
874 if (AR_SREV_9340(ah
) || AR_SREV_9550(ah
)) {
875 if (ah
->is_clk_25mhz
) {
876 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, 0x17c << 1);
877 REG_WRITE(ah
, AR_SLP32_MODE
, 0x0010f3d7);
878 REG_WRITE(ah
, AR_SLP32_INC
, 0x0001e7ae);
880 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, 0x261 << 1);
881 REG_WRITE(ah
, AR_SLP32_MODE
, 0x0010f400);
882 REG_WRITE(ah
, AR_SLP32_INC
, 0x0001e800);
888 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
889 enum nl80211_iftype opmode
)
891 u32 sync_default
= AR_INTR_SYNC_DEFAULT
;
892 u32 imr_reg
= AR_IMR_TXERR
|
898 if (AR_SREV_9340(ah
) || AR_SREV_9550(ah
) || AR_SREV_9531(ah
))
899 sync_default
&= ~AR_INTR_SYNC_HOST1_FATAL
;
901 if (AR_SREV_9300_20_OR_LATER(ah
)) {
902 imr_reg
|= AR_IMR_RXOK_HP
;
903 if (ah
->config
.rx_intr_mitigation
)
904 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
906 imr_reg
|= AR_IMR_RXOK_LP
;
909 if (ah
->config
.rx_intr_mitigation
)
910 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
912 imr_reg
|= AR_IMR_RXOK
;
915 if (ah
->config
.tx_intr_mitigation
)
916 imr_reg
|= AR_IMR_TXINTM
| AR_IMR_TXMINTR
;
918 imr_reg
|= AR_IMR_TXOK
;
920 ENABLE_REGWRITE_BUFFER(ah
);
922 REG_WRITE(ah
, AR_IMR
, imr_reg
);
923 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
924 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
926 if (!AR_SREV_9100(ah
)) {
927 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
928 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, sync_default
);
929 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
932 REGWRITE_BUFFER_FLUSH(ah
);
934 if (AR_SREV_9300_20_OR_LATER(ah
)) {
935 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_ENABLE
, 0);
936 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_MASK
, 0);
937 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_ENABLE
, 0);
938 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_MASK
, 0);
942 static void ath9k_hw_set_sifs_time(struct ath_hw
*ah
, u32 us
)
944 u32 val
= ath9k_hw_mac_to_clks(ah
, us
- 2);
945 val
= min(val
, (u32
) 0xFFFF);
946 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
, val
);
949 void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
951 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
952 val
= min(val
, (u32
) 0xFFFF);
953 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
956 void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
958 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
959 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
960 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
963 void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
965 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
966 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
967 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
970 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
973 ath_dbg(ath9k_hw_common(ah
), XMIT
, "bad global tx timeout %u\n",
975 ah
->globaltxtimeout
= (u32
) -1;
978 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
979 ah
->globaltxtimeout
= tu
;
984 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
986 struct ath_common
*common
= ath9k_hw_common(ah
);
987 const struct ath9k_channel
*chan
= ah
->curchan
;
988 int acktimeout
, ctstimeout
, ack_offset
= 0;
991 int rx_lat
= 0, tx_lat
= 0, eifs
= 0;
994 ath_dbg(ath9k_hw_common(ah
), RESET
, "ah->misc_mode 0x%x\n",
1000 if (ah
->misc_mode
!= 0)
1001 REG_SET_BIT(ah
, AR_PCU_MISC
, ah
->misc_mode
);
1003 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1009 if (IS_CHAN_5GHZ(chan
))
1014 if (IS_CHAN_HALF_RATE(chan
)) {
1018 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1024 } else if (IS_CHAN_QUARTER_RATE(chan
)) {
1026 rx_lat
= (rx_lat
* 4) - 1;
1028 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1035 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
)) {
1036 eifs
= AR_D_GBL_IFS_EIFS_ASYNC_FIFO
;
1037 reg
= AR_USEC_ASYNC_FIFO
;
1039 eifs
= REG_READ(ah
, AR_D_GBL_IFS_EIFS
)/
1041 reg
= REG_READ(ah
, AR_USEC
);
1043 rx_lat
= MS(reg
, AR_USEC_RX_LAT
);
1044 tx_lat
= MS(reg
, AR_USEC_TX_LAT
);
1046 slottime
= ah
->slottime
;
1049 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1050 slottime
+= 3 * ah
->coverage_class
;
1051 acktimeout
= slottime
+ sifstime
+ ack_offset
;
1052 ctstimeout
= acktimeout
;
1055 * Workaround for early ACK timeouts, add an offset to match the
1056 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1057 * This was initially only meant to work around an issue with delayed
1058 * BA frames in some implementations, but it has been found to fix ACK
1059 * timeout issues in other cases as well.
1061 if (IS_CHAN_2GHZ(chan
) &&
1062 !IS_CHAN_HALF_RATE(chan
) && !IS_CHAN_QUARTER_RATE(chan
)) {
1063 acktimeout
+= 64 - sifstime
- ah
->slottime
;
1064 ctstimeout
+= 48 - sifstime
- ah
->slottime
;
1067 if (ah
->dynack
.enabled
) {
1068 acktimeout
= ah
->dynack
.ackto
;
1069 ctstimeout
= acktimeout
;
1070 slottime
= (acktimeout
- 3) / 2;
1072 ah
->dynack
.ackto
= acktimeout
;
1075 ath9k_hw_set_sifs_time(ah
, sifstime
);
1076 ath9k_hw_setslottime(ah
, slottime
);
1077 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
1078 ath9k_hw_set_cts_timeout(ah
, ctstimeout
);
1079 if (ah
->globaltxtimeout
!= (u32
) -1)
1080 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1082 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
, ath9k_hw_mac_to_clks(ah
, eifs
));
1083 REG_RMW(ah
, AR_USEC
,
1084 (common
->clockrate
- 1) |
1085 SM(rx_lat
, AR_USEC_RX_LAT
) |
1086 SM(tx_lat
, AR_USEC_TX_LAT
),
1087 AR_USEC_TX_LAT
| AR_USEC_RX_LAT
| AR_USEC_USEC
);
1090 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
1092 void ath9k_hw_deinit(struct ath_hw
*ah
)
1094 struct ath_common
*common
= ath9k_hw_common(ah
);
1096 if (common
->state
< ATH_HW_INITIALIZED
)
1099 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1101 EXPORT_SYMBOL(ath9k_hw_deinit
);
1107 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
)
1109 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1111 if (IS_CHAN_2GHZ(chan
))
1119 /****************************************/
1120 /* Reset and Channel Switching Routines */
1121 /****************************************/
1123 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1125 struct ath_common
*common
= ath9k_hw_common(ah
);
1128 ENABLE_REGWRITE_BUFFER(ah
);
1131 * set AHB_MODE not to do cacheline prefetches
1133 if (!AR_SREV_9300_20_OR_LATER(ah
))
1134 REG_SET_BIT(ah
, AR_AHB_MODE
, AR_AHB_PREFETCH_RD_EN
);
1137 * let mac dma reads be in 128 byte chunks
1139 REG_RMW(ah
, AR_TXCFG
, AR_TXCFG_DMASZ_128B
, AR_TXCFG_DMASZ_MASK
);
1141 REGWRITE_BUFFER_FLUSH(ah
);
1144 * Restore TX Trigger Level to its pre-reset value.
1145 * The initial value depends on whether aggregation is enabled, and is
1146 * adjusted whenever underruns are detected.
1148 if (!AR_SREV_9300_20_OR_LATER(ah
))
1149 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1151 ENABLE_REGWRITE_BUFFER(ah
);
1154 * let mac dma writes be in 128 byte chunks
1156 REG_RMW(ah
, AR_RXCFG
, AR_RXCFG_DMASZ_128B
, AR_RXCFG_DMASZ_MASK
);
1159 * Setup receive FIFO threshold to hold off TX activities
1161 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1163 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1164 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_HP
, 0x1);
1165 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_LP
, 0x1);
1167 ath9k_hw_set_rx_bufsize(ah
, common
->rx_bufsize
-
1168 ah
->caps
.rx_status_len
);
1172 * reduce the number of usable entries in PCU TXBUF to avoid
1173 * wrap around issues.
1175 if (AR_SREV_9285(ah
)) {
1176 /* For AR9285 the number of Fifos are reduced to half.
1177 * So set the usable tx buf size also to half to
1178 * avoid data/delimiter underruns
1180 txbuf_size
= AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
;
1181 } else if (AR_SREV_9340_13_OR_LATER(ah
)) {
1182 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1183 txbuf_size
= AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE
;
1185 txbuf_size
= AR_PCU_TXBUF_CTRL_USABLE_SIZE
;
1188 if (!AR_SREV_9271(ah
))
1189 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
, txbuf_size
);
1191 REGWRITE_BUFFER_FLUSH(ah
);
1193 if (AR_SREV_9300_20_OR_LATER(ah
))
1194 ath9k_hw_reset_txstatus_ring(ah
);
1197 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1199 u32 mask
= AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
;
1200 u32 set
= AR_STA_ID1_KSRCH_MODE
;
1203 case NL80211_IFTYPE_ADHOC
:
1204 if (!AR_SREV_9340_13(ah
)) {
1205 set
|= AR_STA_ID1_ADHOC
;
1206 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1210 case NL80211_IFTYPE_MESH_POINT
:
1211 case NL80211_IFTYPE_AP
:
1212 set
|= AR_STA_ID1_STA_AP
;
1214 case NL80211_IFTYPE_STATION
:
1215 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1218 if (!ah
->is_monitoring
)
1222 REG_RMW(ah
, AR_STA_ID1
, set
, mask
);
1225 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
1226 u32
*coef_mantissa
, u32
*coef_exponent
)
1228 u32 coef_exp
, coef_man
;
1230 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1231 if ((coef_scaled
>> coef_exp
) & 0x1)
1234 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1236 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1238 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1239 *coef_exponent
= coef_exp
- 16;
1243 * call external reset function to reset WMAC if:
1244 * - doing a cold reset
1245 * - we have pending frames in the TX queues.
1247 static bool ath9k_hw_ar9330_reset_war(struct ath_hw
*ah
, int type
)
1251 for (i
= 0; i
< AR_NUM_QCU
; i
++) {
1252 npend
= ath9k_hw_numtxpending(ah
, i
);
1257 if (ah
->external_reset
&&
1258 (npend
|| type
== ATH9K_RESET_COLD
)) {
1261 ath_dbg(ath9k_hw_common(ah
), RESET
,
1262 "reset MAC via external reset\n");
1264 reset_err
= ah
->external_reset();
1266 ath_err(ath9k_hw_common(ah
),
1267 "External reset failed, err=%d\n",
1272 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1278 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1283 if (AR_SREV_9100(ah
)) {
1284 REG_RMW_FIELD(ah
, AR_RTC_DERIVED_CLK
,
1285 AR_RTC_DERIVED_CLK_PERIOD
, 1);
1286 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1289 ENABLE_REGWRITE_BUFFER(ah
);
1291 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1292 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1296 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1297 AR_RTC_FORCE_WAKE_ON_INT
);
1299 if (AR_SREV_9100(ah
)) {
1300 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1301 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1303 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1304 if (AR_SREV_9340(ah
))
1305 tmpReg
&= AR9340_INTR_SYNC_LOCAL_TIMEOUT
;
1307 tmpReg
&= AR_INTR_SYNC_LOCAL_TIMEOUT
|
1308 AR_INTR_SYNC_RADM_CPL_TIMEOUT
;
1312 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1315 if (!AR_SREV_9300_20_OR_LATER(ah
))
1317 REG_WRITE(ah
, AR_RC
, val
);
1319 } else if (!AR_SREV_9300_20_OR_LATER(ah
))
1320 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1322 rst_flags
= AR_RTC_RC_MAC_WARM
;
1323 if (type
== ATH9K_RESET_COLD
)
1324 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1327 if (AR_SREV_9330(ah
)) {
1328 if (!ath9k_hw_ar9330_reset_war(ah
, type
))
1332 if (ath9k_hw_mci_is_enabled(ah
))
1333 ar9003_mci_check_gpm_offset(ah
);
1335 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1337 REGWRITE_BUFFER_FLUSH(ah
);
1339 if (AR_SREV_9300_20_OR_LATER(ah
))
1341 else if (AR_SREV_9100(ah
))
1346 REG_WRITE(ah
, AR_RTC_RC
, 0);
1347 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1348 ath_dbg(ath9k_hw_common(ah
), RESET
, "RTC stuck in MAC reset\n");
1352 if (!AR_SREV_9100(ah
))
1353 REG_WRITE(ah
, AR_RC
, 0);
1355 if (AR_SREV_9100(ah
))
1361 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1363 ENABLE_REGWRITE_BUFFER(ah
);
1365 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1366 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1370 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1371 AR_RTC_FORCE_WAKE_ON_INT
);
1373 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1374 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1376 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1378 REGWRITE_BUFFER_FLUSH(ah
);
1382 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1383 REG_WRITE(ah
, AR_RC
, 0);
1385 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1387 if (!ath9k_hw_wait(ah
,
1392 ath_dbg(ath9k_hw_common(ah
), RESET
, "RTC not waking up\n");
1396 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1399 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1403 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1404 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1408 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1409 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1411 if (!ah
->reset_power_on
)
1412 type
= ATH9K_RESET_POWER_ON
;
1415 case ATH9K_RESET_POWER_ON
:
1416 ret
= ath9k_hw_set_reset_power_on(ah
);
1418 ah
->reset_power_on
= true;
1420 case ATH9K_RESET_WARM
:
1421 case ATH9K_RESET_COLD
:
1422 ret
= ath9k_hw_set_reset(ah
, type
);
1431 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1432 struct ath9k_channel
*chan
)
1434 int reset_type
= ATH9K_RESET_WARM
;
1436 if (AR_SREV_9280(ah
)) {
1437 if (ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1438 reset_type
= ATH9K_RESET_POWER_ON
;
1440 reset_type
= ATH9K_RESET_COLD
;
1441 } else if (ah
->chip_fullsleep
|| REG_READ(ah
, AR_Q_TXE
) ||
1442 (REG_READ(ah
, AR_CR
) & AR_CR_RXE
))
1443 reset_type
= ATH9K_RESET_COLD
;
1445 if (!ath9k_hw_set_reset_reg(ah
, reset_type
))
1448 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1451 ah
->chip_fullsleep
= false;
1453 if (AR_SREV_9330(ah
))
1454 ar9003_hw_internal_regulator_apply(ah
);
1455 ath9k_hw_init_pll(ah
, chan
);
1460 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1461 struct ath9k_channel
*chan
)
1463 struct ath_common
*common
= ath9k_hw_common(ah
);
1464 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1465 bool band_switch
= false, mode_diff
= false;
1466 u8 ini_reloaded
= 0;
1470 if (pCap
->hw_caps
& ATH9K_HW_CAP_FCC_BAND_SWITCH
) {
1471 u32 flags_diff
= chan
->channelFlags
^ ah
->curchan
->channelFlags
;
1472 band_switch
= !!(flags_diff
& CHANNEL_5GHZ
);
1473 mode_diff
= !!(flags_diff
& ~CHANNEL_HT
);
1476 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1477 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1478 ath_dbg(common
, QUEUE
,
1479 "Transmit frames pending on queue %d\n", qnum
);
1484 if (!ath9k_hw_rfbus_req(ah
)) {
1485 ath_err(common
, "Could not kill baseband RX\n");
1489 if (band_switch
|| mode_diff
) {
1490 ath9k_hw_mark_phy_inactive(ah
);
1494 ath9k_hw_init_pll(ah
, chan
);
1496 if (ath9k_hw_fast_chan_change(ah
, chan
, &ini_reloaded
)) {
1497 ath_err(common
, "Failed to do fast channel change\n");
1502 ath9k_hw_set_channel_regs(ah
, chan
);
1504 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1506 ath_err(common
, "Failed to set channel\n");
1509 ath9k_hw_set_clockrate(ah
);
1510 ath9k_hw_apply_txpower(ah
, chan
, false);
1512 ath9k_hw_set_delta_slope(ah
, chan
);
1513 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1515 if (band_switch
|| ini_reloaded
)
1516 ah
->eep_ops
->set_board_values(ah
, chan
);
1518 ath9k_hw_init_bb(ah
, chan
);
1519 ath9k_hw_rfbus_done(ah
);
1521 if (band_switch
|| ini_reloaded
) {
1522 ah
->ah_flags
|= AH_FASTCC
;
1523 ath9k_hw_init_cal(ah
, chan
);
1524 ah
->ah_flags
&= ~AH_FASTCC
;
1530 static void ath9k_hw_apply_gpio_override(struct ath_hw
*ah
)
1532 u32 gpio_mask
= ah
->gpio_mask
;
1535 for (i
= 0; gpio_mask
; i
++, gpio_mask
>>= 1) {
1536 if (!(gpio_mask
& 1))
1539 ath9k_hw_cfg_output(ah
, i
, AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1540 ath9k_hw_set_gpio(ah
, i
, !!(ah
->gpio_val
& BIT(i
)));
1544 void ath9k_hw_check_nav(struct ath_hw
*ah
)
1546 struct ath_common
*common
= ath9k_hw_common(ah
);
1549 val
= REG_READ(ah
, AR_NAV
);
1550 if (val
!= 0xdeadbeef && val
> 0x7fff) {
1551 ath_dbg(common
, BSTUCK
, "Abnormal NAV: 0x%x\n", val
);
1552 REG_WRITE(ah
, AR_NAV
, 0);
1555 EXPORT_SYMBOL(ath9k_hw_check_nav
);
1557 bool ath9k_hw_check_alive(struct ath_hw
*ah
)
1562 if (AR_SREV_9300(ah
))
1563 return !ath9k_hw_detect_mac_hang(ah
);
1565 if (AR_SREV_9285_12_OR_LATER(ah
))
1568 last_val
= REG_READ(ah
, AR_OBS_BUS_1
);
1570 reg
= REG_READ(ah
, AR_OBS_BUS_1
);
1571 if (reg
!= last_val
)
1576 if ((reg
& 0x7E7FFFEF) == 0x00702400)
1579 switch (reg
& 0x7E000B00) {
1587 } while (count
-- > 0);
1591 EXPORT_SYMBOL(ath9k_hw_check_alive
);
1593 static void ath9k_hw_init_mfp(struct ath_hw
*ah
)
1595 /* Setup MFP options for CCMP */
1596 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1597 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1598 * frames when constructing CCMP AAD. */
1599 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1601 ah
->sw_mgmt_crypto
= false;
1602 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1603 /* Disable hardware crypto for management frames */
1604 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1605 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1606 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1607 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1608 ah
->sw_mgmt_crypto
= true;
1610 ah
->sw_mgmt_crypto
= true;
1614 static void ath9k_hw_reset_opmode(struct ath_hw
*ah
,
1615 u32 macStaId1
, u32 saveDefAntenna
)
1617 struct ath_common
*common
= ath9k_hw_common(ah
);
1619 ENABLE_REGWRITE_BUFFER(ah
);
1621 REG_RMW(ah
, AR_STA_ID1
, macStaId1
1622 | AR_STA_ID1_RTS_USE_DEF
1623 | ah
->sta_id1_defaults
,
1624 ~AR_STA_ID1_SADH_MASK
);
1625 ath_hw_setbssidmask(common
);
1626 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
1627 ath9k_hw_write_associd(ah
);
1628 REG_WRITE(ah
, AR_ISR
, ~0);
1629 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
1631 REGWRITE_BUFFER_FLUSH(ah
);
1633 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
1636 static void ath9k_hw_init_queues(struct ath_hw
*ah
)
1640 ENABLE_REGWRITE_BUFFER(ah
);
1642 for (i
= 0; i
< AR_NUM_DCU
; i
++)
1643 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
1645 REGWRITE_BUFFER_FLUSH(ah
);
1648 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1649 ath9k_hw_resettxqueue(ah
, i
);
1653 * For big endian systems turn on swapping for descriptors
1655 static void ath9k_hw_init_desc(struct ath_hw
*ah
)
1657 struct ath_common
*common
= ath9k_hw_common(ah
);
1659 if (AR_SREV_9100(ah
)) {
1661 mask
= REG_READ(ah
, AR_CFG
);
1662 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
1663 ath_dbg(common
, RESET
, "CFG Byte Swap Set 0x%x\n",
1666 mask
= INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
1667 REG_WRITE(ah
, AR_CFG
, mask
);
1668 ath_dbg(common
, RESET
, "Setting CFG 0x%x\n",
1669 REG_READ(ah
, AR_CFG
));
1672 if (common
->bus_ops
->ath_bus_type
== ATH_USB
) {
1673 /* Configure AR9271 target WLAN */
1674 if (AR_SREV_9271(ah
))
1675 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
1677 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1680 else if (AR_SREV_9330(ah
) || AR_SREV_9340(ah
) ||
1681 AR_SREV_9550(ah
) || AR_SREV_9531(ah
))
1682 REG_RMW(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
, 0);
1684 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1690 * Fast channel change:
1691 * (Change synthesizer based on channel freq without resetting chip)
1693 static int ath9k_hw_do_fastcc(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1695 struct ath_common
*common
= ath9k_hw_common(ah
);
1696 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1699 if (AR_SREV_9280(ah
) && common
->bus_ops
->ath_bus_type
== ATH_PCI
)
1702 if (ah
->chip_fullsleep
)
1708 if (chan
->channel
== ah
->curchan
->channel
)
1711 if ((ah
->curchan
->channelFlags
| chan
->channelFlags
) &
1712 (CHANNEL_HALF
| CHANNEL_QUARTER
))
1716 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1718 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_FCC_BAND_SWITCH
) &&
1719 ((chan
->channelFlags
^ ah
->curchan
->channelFlags
) & ~CHANNEL_HT
))
1722 if (!ath9k_hw_check_alive(ah
))
1726 * For AR9462, make sure that calibration data for
1727 * re-using are present.
1729 if (AR_SREV_9462(ah
) && (ah
->caldata
&&
1730 (!test_bit(TXIQCAL_DONE
, &ah
->caldata
->cal_flags
) ||
1731 !test_bit(TXCLCAL_DONE
, &ah
->caldata
->cal_flags
) ||
1732 !test_bit(RTT_DONE
, &ah
->caldata
->cal_flags
))))
1735 ath_dbg(common
, RESET
, "FastChannelChange for %d -> %d\n",
1736 ah
->curchan
->channel
, chan
->channel
);
1738 ret
= ath9k_hw_channel_change(ah
, chan
);
1742 if (ath9k_hw_mci_is_enabled(ah
))
1743 ar9003_mci_2g5g_switch(ah
, false);
1745 ath9k_hw_loadnf(ah
, ah
->curchan
);
1746 ath9k_hw_start_nfcal(ah
, true);
1748 if (AR_SREV_9271(ah
))
1749 ar9002_hw_load_ani_reg(ah
, chan
);
1756 u32
ath9k_hw_get_tsf_offset(struct timespec
*last
, struct timespec
*cur
)
1762 getrawmonotonic(&ts
);
1766 usec
= cur
->tv_sec
* 1000000ULL + cur
->tv_nsec
/ 1000;
1767 usec
-= last
->tv_sec
* 1000000ULL + last
->tv_nsec
/ 1000;
1771 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset
);
1773 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1774 struct ath9k_hw_cal_data
*caldata
, bool fastcc
)
1776 struct ath_common
*common
= ath9k_hw_common(ah
);
1783 bool start_mci_reset
= false;
1784 bool save_fullsleep
= ah
->chip_fullsleep
;
1786 if (ath9k_hw_mci_is_enabled(ah
)) {
1787 start_mci_reset
= ar9003_mci_start_reset(ah
, chan
);
1788 if (start_mci_reset
)
1792 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1795 if (ah
->curchan
&& !ah
->chip_fullsleep
)
1796 ath9k_hw_getnf(ah
, ah
->curchan
);
1798 ah
->caldata
= caldata
;
1799 if (caldata
&& (chan
->channel
!= caldata
->channel
||
1800 chan
->channelFlags
!= caldata
->channelFlags
)) {
1801 /* Operating channel changed, reset channel calibration data */
1802 memset(caldata
, 0, sizeof(*caldata
));
1803 ath9k_init_nfcal_hist_buffer(ah
, chan
);
1804 } else if (caldata
) {
1805 clear_bit(PAPRD_PACKET_SENT
, &caldata
->cal_flags
);
1807 ah
->noise
= ath9k_hw_getchan_noise(ah
, chan
, chan
->noisefloor
);
1810 r
= ath9k_hw_do_fastcc(ah
, chan
);
1815 if (ath9k_hw_mci_is_enabled(ah
))
1816 ar9003_mci_stop_bt(ah
, save_fullsleep
);
1818 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1819 if (saveDefAntenna
== 0)
1822 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1824 /* Save TSF before chip reset, a cold reset clears it */
1825 tsf
= ath9k_hw_gettsf64(ah
);
1826 usec
= ktime_to_us(ktime_get_raw());
1828 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1829 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1830 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1832 ath9k_hw_mark_phy_inactive(ah
);
1834 ah
->paprd_table_write_done
= false;
1836 /* Only required on the first reset */
1837 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1839 AR9271_RESET_POWER_DOWN_CONTROL
,
1840 AR9271_RADIO_RF_RST
);
1844 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1845 ath_err(common
, "Chip reset failed\n");
1849 /* Only required on the first reset */
1850 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1851 ah
->htc_reset_init
= false;
1853 AR9271_RESET_POWER_DOWN_CONTROL
,
1854 AR9271_GATE_MAC_CTL
);
1859 usec
= ktime_to_us(ktime_get_raw()) - usec
;
1860 ath9k_hw_settsf64(ah
, tsf
+ usec
);
1862 if (AR_SREV_9280_20_OR_LATER(ah
))
1863 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1865 if (!AR_SREV_9300_20_OR_LATER(ah
))
1866 ar9002_hw_enable_async_fifo(ah
);
1868 r
= ath9k_hw_process_ini(ah
, chan
);
1872 ath9k_hw_set_rfmode(ah
, chan
);
1874 if (ath9k_hw_mci_is_enabled(ah
))
1875 ar9003_mci_reset(ah
, false, IS_CHAN_2GHZ(chan
), save_fullsleep
);
1878 * Some AR91xx SoC devices frequently fail to accept TSF writes
1879 * right after the chip reset. When that happens, write a new
1880 * value after the initvals have been applied, with an offset
1881 * based on measured time difference
1883 if (AR_SREV_9100(ah
) && (ath9k_hw_gettsf64(ah
) < tsf
)) {
1885 ath9k_hw_settsf64(ah
, tsf
);
1888 ath9k_hw_init_mfp(ah
);
1890 ath9k_hw_set_delta_slope(ah
, chan
);
1891 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1892 ah
->eep_ops
->set_board_values(ah
, chan
);
1894 ath9k_hw_reset_opmode(ah
, macStaId1
, saveDefAntenna
);
1896 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1900 ath9k_hw_set_clockrate(ah
);
1902 ath9k_hw_init_queues(ah
);
1903 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
1904 ath9k_hw_ani_cache_ini_regs(ah
);
1905 ath9k_hw_init_qos(ah
);
1907 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1908 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
1910 ath9k_hw_init_global_settings(ah
);
1912 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
)) {
1913 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
1914 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
1915 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
1916 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
1917 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1918 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
1921 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PRESERVE_SEQNUM
);
1923 ath9k_hw_set_dma(ah
);
1925 if (!ath9k_hw_mci_is_enabled(ah
))
1926 REG_WRITE(ah
, AR_OBS
, 8);
1928 if (ah
->config
.rx_intr_mitigation
) {
1929 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, ah
->config
.rimt_last
);
1930 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, ah
->config
.rimt_first
);
1933 if (ah
->config
.tx_intr_mitigation
) {
1934 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_LAST
, 300);
1935 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_FIRST
, 750);
1938 ath9k_hw_init_bb(ah
, chan
);
1941 clear_bit(TXIQCAL_DONE
, &caldata
->cal_flags
);
1942 clear_bit(TXCLCAL_DONE
, &caldata
->cal_flags
);
1944 if (!ath9k_hw_init_cal(ah
, chan
))
1947 if (ath9k_hw_mci_is_enabled(ah
) && ar9003_mci_end_reset(ah
, chan
, caldata
))
1950 ENABLE_REGWRITE_BUFFER(ah
);
1952 ath9k_hw_restore_chainmask(ah
);
1953 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
1955 REGWRITE_BUFFER_FLUSH(ah
);
1957 ath9k_hw_init_desc(ah
);
1959 if (ath9k_hw_btcoex_is_enabled(ah
))
1960 ath9k_hw_btcoex_enable(ah
);
1962 if (ath9k_hw_mci_is_enabled(ah
))
1963 ar9003_mci_check_bt(ah
);
1965 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1966 ath9k_hw_loadnf(ah
, chan
);
1967 ath9k_hw_start_nfcal(ah
, true);
1970 if (AR_SREV_9300_20_OR_LATER(ah
))
1971 ar9003_hw_bb_watchdog_config(ah
);
1973 if (ah
->config
.hw_hang_checks
& HW_PHYRESTART_CLC_WAR
)
1974 ar9003_hw_disable_phy_restart(ah
);
1976 ath9k_hw_apply_gpio_override(ah
);
1978 if (AR_SREV_9565(ah
) && common
->bt_ant_diversity
)
1979 REG_SET_BIT(ah
, AR_BTCOEX_WL_LNADIV
, AR_BTCOEX_WL_LNADIV_FORCE_ON
);
1981 if (ah
->hw
->conf
.radar_enabled
) {
1982 /* set HW specific DFS configuration */
1983 ah
->radar_conf
.ext_channel
= IS_CHAN_HT40(chan
);
1984 ath9k_hw_set_radar_params(ah
);
1989 EXPORT_SYMBOL(ath9k_hw_reset
);
1991 /******************************/
1992 /* Power Management (Chipset) */
1993 /******************************/
1996 * Notify Power Mgt is disabled in self-generated frames.
1997 * If requested, force chip to sleep.
1999 static void ath9k_set_power_sleep(struct ath_hw
*ah
)
2001 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2003 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
2004 REG_CLR_BIT(ah
, AR_TIMER_MODE
, 0xff);
2005 REG_CLR_BIT(ah
, AR_NDP2_TIMER_MODE
, 0xff);
2006 REG_CLR_BIT(ah
, AR_SLP32_INC
, 0xfffff);
2007 /* xxx Required for WLAN only case ? */
2008 REG_WRITE(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
, 0);
2013 * Clear the RTC force wake bit to allow the
2014 * mac to go to sleep.
2016 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
);
2018 if (ath9k_hw_mci_is_enabled(ah
))
2021 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
2022 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
2024 /* Shutdown chip. Active low */
2025 if (!AR_SREV_5416(ah
) && !AR_SREV_9271(ah
)) {
2026 REG_CLR_BIT(ah
, AR_RTC_RESET
, AR_RTC_RESET_EN
);
2030 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2031 if (AR_SREV_9300_20_OR_LATER(ah
))
2032 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
2036 * Notify Power Management is enabled in self-generating
2037 * frames. If request, set power mode of chip to
2038 * auto/normal. Duration in units of 128us (1/8 TU).
2040 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
)
2042 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2044 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2046 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2047 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2048 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2049 AR_RTC_FORCE_WAKE_ON_INT
);
2052 /* When chip goes into network sleep, it could be waken
2053 * up by MCI_INT interrupt caused by BT's HW messages
2054 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2055 * rate (~100us). This will cause chip to leave and
2056 * re-enter network sleep mode frequently, which in
2057 * consequence will have WLAN MCI HW to generate lots of
2058 * SYS_WAKING and SYS_SLEEPING messages which will make
2059 * BT CPU to busy to process.
2061 if (ath9k_hw_mci_is_enabled(ah
))
2062 REG_CLR_BIT(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
,
2063 AR_MCI_INTERRUPT_RX_HW_MSG_MASK
);
2065 * Clear the RTC force wake bit to allow the
2066 * mac to go to sleep.
2068 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
);
2070 if (ath9k_hw_mci_is_enabled(ah
))
2074 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2075 if (AR_SREV_9300_20_OR_LATER(ah
))
2076 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
2079 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
)
2084 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2085 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2086 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
2090 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2091 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2092 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
2095 if (!AR_SREV_9300_20_OR_LATER(ah
))
2096 ath9k_hw_init_pll(ah
, NULL
);
2098 if (AR_SREV_9100(ah
))
2099 REG_SET_BIT(ah
, AR_RTC_RESET
,
2102 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2103 AR_RTC_FORCE_WAKE_EN
);
2104 if (AR_SREV_9100(ah
))
2109 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2110 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2111 if (val
== AR_RTC_STATUS_ON
)
2114 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2115 AR_RTC_FORCE_WAKE_EN
);
2118 ath_err(ath9k_hw_common(ah
),
2119 "Failed to wakeup in %uus\n",
2120 POWER_UP_TIME
/ 20);
2124 if (ath9k_hw_mci_is_enabled(ah
))
2125 ar9003_mci_set_power_awake(ah
);
2127 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2132 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2134 struct ath_common
*common
= ath9k_hw_common(ah
);
2136 static const char *modes
[] = {
2143 if (ah
->power_mode
== mode
)
2146 ath_dbg(common
, RESET
, "%s -> %s\n",
2147 modes
[ah
->power_mode
], modes
[mode
]);
2150 case ATH9K_PM_AWAKE
:
2151 status
= ath9k_hw_set_power_awake(ah
);
2153 case ATH9K_PM_FULL_SLEEP
:
2154 if (ath9k_hw_mci_is_enabled(ah
))
2155 ar9003_mci_set_full_sleep(ah
);
2157 ath9k_set_power_sleep(ah
);
2158 ah
->chip_fullsleep
= true;
2160 case ATH9K_PM_NETWORK_SLEEP
:
2161 ath9k_set_power_network_sleep(ah
);
2164 ath_err(common
, "Unknown power mode %u\n", mode
);
2167 ah
->power_mode
= mode
;
2170 * XXX: If this warning never comes up after a while then
2171 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2172 * ath9k_hw_setpower() return type void.
2175 if (!(ah
->ah_flags
& AH_UNPLUGGED
))
2176 ATH_DBG_WARN_ON_ONCE(!status
);
2180 EXPORT_SYMBOL(ath9k_hw_setpower
);
2182 /*******************/
2183 /* Beacon Handling */
2184 /*******************/
2186 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
2190 ENABLE_REGWRITE_BUFFER(ah
);
2192 switch (ah
->opmode
) {
2193 case NL80211_IFTYPE_ADHOC
:
2194 REG_SET_BIT(ah
, AR_TXCFG
,
2195 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
2196 case NL80211_IFTYPE_MESH_POINT
:
2197 case NL80211_IFTYPE_AP
:
2198 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, next_beacon
);
2199 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, next_beacon
-
2200 TU_TO_USEC(ah
->config
.dma_beacon_response_time
));
2201 REG_WRITE(ah
, AR_NEXT_SWBA
, next_beacon
-
2202 TU_TO_USEC(ah
->config
.sw_beacon_response_time
));
2204 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
2207 ath_dbg(ath9k_hw_common(ah
), BEACON
,
2208 "%s: unsupported opmode: %d\n", __func__
, ah
->opmode
);
2213 REG_WRITE(ah
, AR_BEACON_PERIOD
, beacon_period
);
2214 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, beacon_period
);
2215 REG_WRITE(ah
, AR_SWBA_PERIOD
, beacon_period
);
2217 REGWRITE_BUFFER_FLUSH(ah
);
2219 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
2221 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
2223 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
2224 const struct ath9k_beacon_state
*bs
)
2226 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
2227 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2228 struct ath_common
*common
= ath9k_hw_common(ah
);
2230 ENABLE_REGWRITE_BUFFER(ah
);
2232 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, bs
->bs_nexttbtt
);
2233 REG_WRITE(ah
, AR_BEACON_PERIOD
, bs
->bs_intval
);
2234 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, bs
->bs_intval
);
2236 REGWRITE_BUFFER_FLUSH(ah
);
2238 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
2239 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
2241 beaconintval
= bs
->bs_intval
;
2243 if (bs
->bs_sleepduration
> beaconintval
)
2244 beaconintval
= bs
->bs_sleepduration
;
2246 dtimperiod
= bs
->bs_dtimperiod
;
2247 if (bs
->bs_sleepduration
> dtimperiod
)
2248 dtimperiod
= bs
->bs_sleepduration
;
2250 if (beaconintval
== dtimperiod
)
2251 nextTbtt
= bs
->bs_nextdtim
;
2253 nextTbtt
= bs
->bs_nexttbtt
;
2255 ath_dbg(common
, BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
2256 ath_dbg(common
, BEACON
, "next beacon %d\n", nextTbtt
);
2257 ath_dbg(common
, BEACON
, "beacon period %d\n", beaconintval
);
2258 ath_dbg(common
, BEACON
, "DTIM period %d\n", dtimperiod
);
2260 ENABLE_REGWRITE_BUFFER(ah
);
2262 REG_WRITE(ah
, AR_NEXT_DTIM
, bs
->bs_nextdtim
- SLEEP_SLOP
);
2263 REG_WRITE(ah
, AR_NEXT_TIM
, nextTbtt
- SLEEP_SLOP
);
2265 REG_WRITE(ah
, AR_SLEEP1
,
2266 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
2267 | AR_SLEEP1_ASSUME_DTIM
);
2269 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
2270 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
2272 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
2274 REG_WRITE(ah
, AR_SLEEP2
,
2275 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
2277 REG_WRITE(ah
, AR_TIM_PERIOD
, beaconintval
);
2278 REG_WRITE(ah
, AR_DTIM_PERIOD
, dtimperiod
);
2280 REGWRITE_BUFFER_FLUSH(ah
);
2282 REG_SET_BIT(ah
, AR_TIMER_MODE
,
2283 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
2286 /* TSF Out of Range Threshold */
2287 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
2289 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
2291 /*******************/
2292 /* HW Capabilities */
2293 /*******************/
2295 static u8
fixup_chainmask(u8 chip_chainmask
, u8 eeprom_chainmask
)
2297 eeprom_chainmask
&= chip_chainmask
;
2298 if (eeprom_chainmask
)
2299 return eeprom_chainmask
;
2301 return chip_chainmask
;
2305 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2306 * @ah: the atheros hardware data structure
2308 * We enable DFS support upstream on chipsets which have passed a series
2309 * of tests. The testing requirements are going to be documented. Desired
2310 * test requirements are documented at:
2312 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2314 * Once a new chipset gets properly tested an individual commit can be used
2315 * to document the testing for DFS for that chipset.
2317 static bool ath9k_hw_dfs_tested(struct ath_hw
*ah
)
2320 switch (ah
->hw_version
.macVersion
) {
2321 /* for temporary testing DFS with 9280 */
2322 case AR_SREV_VERSION_9280
:
2323 /* AR9580 will likely be our first target to get testing on */
2324 case AR_SREV_VERSION_9580
:
2331 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
2333 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2334 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2335 struct ath_common
*common
= ath9k_hw_common(ah
);
2336 unsigned int chip_chainmask
;
2339 u8 ant_div_ctl1
, tx_chainmask
, rx_chainmask
;
2341 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
2342 regulatory
->current_rd
= eeval
;
2344 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
2345 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
2346 if (regulatory
->current_rd
== 0x64 ||
2347 regulatory
->current_rd
== 0x65)
2348 regulatory
->current_rd
+= 5;
2349 else if (regulatory
->current_rd
== 0x41)
2350 regulatory
->current_rd
= 0x43;
2351 ath_dbg(common
, REGULATORY
, "regdomain mapped to 0x%x\n",
2352 regulatory
->current_rd
);
2355 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
2357 if (eeval
& AR5416_OPFLAGS_11A
) {
2358 if (ah
->disable_5ghz
)
2359 ath_warn(common
, "disabling 5GHz band\n");
2361 pCap
->hw_caps
|= ATH9K_HW_CAP_5GHZ
;
2364 if (eeval
& AR5416_OPFLAGS_11G
) {
2365 if (ah
->disable_2ghz
)
2366 ath_warn(common
, "disabling 2GHz band\n");
2368 pCap
->hw_caps
|= ATH9K_HW_CAP_2GHZ
;
2371 if ((pCap
->hw_caps
& (ATH9K_HW_CAP_2GHZ
| ATH9K_HW_CAP_5GHZ
)) == 0) {
2372 ath_err(common
, "both bands are disabled\n");
2376 if (AR_SREV_9485(ah
) ||
2381 else if (AR_SREV_9462(ah
))
2383 else if (!AR_SREV_9280_20_OR_LATER(ah
))
2385 else if (!AR_SREV_9300_20_OR_LATER(ah
) || AR_SREV_9340(ah
))
2390 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
2392 * For AR9271 we will temporarilly uses the rx chainmax as read from
2395 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
2396 !(eeval
& AR5416_OPFLAGS_11A
) &&
2397 !(AR_SREV_9271(ah
)))
2398 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2399 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
2400 else if (AR_SREV_9100(ah
))
2401 pCap
->rx_chainmask
= 0x7;
2403 /* Use rx_chainmask from EEPROM. */
2404 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
2406 pCap
->tx_chainmask
= fixup_chainmask(chip_chainmask
, pCap
->tx_chainmask
);
2407 pCap
->rx_chainmask
= fixup_chainmask(chip_chainmask
, pCap
->rx_chainmask
);
2408 ah
->txchainmask
= pCap
->tx_chainmask
;
2409 ah
->rxchainmask
= pCap
->rx_chainmask
;
2411 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
2413 /* enable key search for every frame in an aggregate */
2414 if (AR_SREV_9300_20_OR_LATER(ah
))
2415 ah
->misc_mode
|= AR_PCU_ALWAYS_PERFORM_KEYSEARCH
;
2417 common
->crypt_caps
|= ATH_CRYPT_CAP_CIPHER_AESCCM
;
2419 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
2420 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
2422 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
2424 if (AR_SREV_9271(ah
))
2425 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
2426 else if (AR_DEVID_7010(ah
))
2427 pCap
->num_gpio_pins
= AR7010_NUM_GPIO
;
2428 else if (AR_SREV_9300_20_OR_LATER(ah
))
2429 pCap
->num_gpio_pins
= AR9300_NUM_GPIO
;
2430 else if (AR_SREV_9287_11_OR_LATER(ah
))
2431 pCap
->num_gpio_pins
= AR9287_NUM_GPIO
;
2432 else if (AR_SREV_9285_12_OR_LATER(ah
))
2433 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
2434 else if (AR_SREV_9280_20_OR_LATER(ah
))
2435 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
2437 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
2439 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
))
2440 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
2442 pCap
->rts_aggr_limit
= (8 * 1024);
2444 #ifdef CONFIG_ATH9K_RFKILL
2445 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
2446 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
2448 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
2449 ah
->rfkill_polarity
=
2450 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
2452 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
2455 if (AR_SREV_9271(ah
) || AR_SREV_9300_20_OR_LATER(ah
))
2456 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
2458 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
2460 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
2461 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
2463 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
2465 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2466 pCap
->hw_caps
|= ATH9K_HW_CAP_EDMA
| ATH9K_HW_CAP_FASTCLOCK
;
2467 if (!AR_SREV_9330(ah
) && !AR_SREV_9485(ah
) && !AR_SREV_9565(ah
))
2468 pCap
->hw_caps
|= ATH9K_HW_CAP_LDPC
;
2470 pCap
->rx_hp_qdepth
= ATH9K_HW_RX_HP_QDEPTH
;
2471 pCap
->rx_lp_qdepth
= ATH9K_HW_RX_LP_QDEPTH
;
2472 pCap
->rx_status_len
= sizeof(struct ar9003_rxs
);
2473 pCap
->tx_desc_len
= sizeof(struct ar9003_txc
);
2474 pCap
->txs_len
= sizeof(struct ar9003_txs
);
2476 pCap
->tx_desc_len
= sizeof(struct ath_desc
);
2477 if (AR_SREV_9280_20(ah
))
2478 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCLOCK
;
2481 if (AR_SREV_9300_20_OR_LATER(ah
))
2482 pCap
->hw_caps
|= ATH9K_HW_CAP_RAC_SUPPORTED
;
2484 if (AR_SREV_9300_20_OR_LATER(ah
))
2485 ah
->ent_mode
= REG_READ(ah
, AR_ENT_OTP
);
2487 if (AR_SREV_9287_11_OR_LATER(ah
) || AR_SREV_9271(ah
))
2488 pCap
->hw_caps
|= ATH9K_HW_CAP_SGI_20
;
2490 if (AR_SREV_9285(ah
)) {
2491 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MODAL_VER
) >= 3) {
2493 ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
2494 if ((ant_div_ctl1
& 0x1) && ((ant_div_ctl1
>> 3) & 0x1)) {
2495 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
2496 ath_info(common
, "Enable LNA combining\n");
2501 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2502 if (ah
->eep_ops
->get_eeprom(ah
, EEP_CHAIN_MASK_REDUCE
))
2503 pCap
->hw_caps
|= ATH9K_HW_CAP_APM
;
2506 if (AR_SREV_9330(ah
) || AR_SREV_9485(ah
) || AR_SREV_9565(ah
)) {
2507 ant_div_ctl1
= ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
2508 if ((ant_div_ctl1
>> 0x6) == 0x3) {
2509 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
2510 ath_info(common
, "Enable LNA combining\n");
2514 if (ath9k_hw_dfs_tested(ah
))
2515 pCap
->hw_caps
|= ATH9K_HW_CAP_DFS
;
2517 tx_chainmask
= pCap
->tx_chainmask
;
2518 rx_chainmask
= pCap
->rx_chainmask
;
2519 while (tx_chainmask
|| rx_chainmask
) {
2520 if (tx_chainmask
& BIT(0))
2521 pCap
->max_txchains
++;
2522 if (rx_chainmask
& BIT(0))
2523 pCap
->max_rxchains
++;
2529 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
2530 if (!(ah
->ent_mode
& AR_ENT_OTP_49GHZ_DISABLE
))
2531 pCap
->hw_caps
|= ATH9K_HW_CAP_MCI
;
2533 if (AR_SREV_9462_20_OR_LATER(ah
))
2534 pCap
->hw_caps
|= ATH9K_HW_CAP_RTT
;
2537 if (AR_SREV_9462(ah
))
2538 pCap
->hw_caps
|= ATH9K_HW_WOW_DEVICE_CAPABLE
;
2540 if (AR_SREV_9300_20_OR_LATER(ah
) &&
2541 ah
->eep_ops
->get_eeprom(ah
, EEP_PAPRD
))
2542 pCap
->hw_caps
|= ATH9K_HW_CAP_PAPRD
;
2547 /****************************/
2548 /* GPIO / RFKILL / Antennae */
2549 /****************************/
2551 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
2555 u32 gpio_shift
, tmp
;
2558 addr
= AR_GPIO_OUTPUT_MUX3
;
2560 addr
= AR_GPIO_OUTPUT_MUX2
;
2562 addr
= AR_GPIO_OUTPUT_MUX1
;
2564 gpio_shift
= (gpio
% 6) * 5;
2566 if (AR_SREV_9280_20_OR_LATER(ah
)
2567 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
2568 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
2569 (0x1f << gpio_shift
));
2571 tmp
= REG_READ(ah
, addr
);
2572 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
2573 tmp
&= ~(0x1f << gpio_shift
);
2574 tmp
|= (type
<< gpio_shift
);
2575 REG_WRITE(ah
, addr
, tmp
);
2579 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
2583 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
2585 if (AR_DEVID_7010(ah
)) {
2587 REG_RMW(ah
, AR7010_GPIO_OE
,
2588 (AR7010_GPIO_OE_AS_INPUT
<< gpio_shift
),
2589 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2593 gpio_shift
= gpio
<< 1;
2596 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
2597 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2599 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
2601 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
2603 #define MS_REG_READ(x, y) \
2604 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2606 if (gpio
>= ah
->caps
.num_gpio_pins
)
2609 if (AR_DEVID_7010(ah
)) {
2611 val
= REG_READ(ah
, AR7010_GPIO_IN
);
2612 return (MS(val
, AR7010_GPIO_IN_VAL
) & AR_GPIO_BIT(gpio
)) == 0;
2613 } else if (AR_SREV_9300_20_OR_LATER(ah
))
2614 return (MS(REG_READ(ah
, AR_GPIO_IN
), AR9300_GPIO_IN_VAL
) &
2615 AR_GPIO_BIT(gpio
)) != 0;
2616 else if (AR_SREV_9271(ah
))
2617 return MS_REG_READ(AR9271
, gpio
) != 0;
2618 else if (AR_SREV_9287_11_OR_LATER(ah
))
2619 return MS_REG_READ(AR9287
, gpio
) != 0;
2620 else if (AR_SREV_9285_12_OR_LATER(ah
))
2621 return MS_REG_READ(AR9285
, gpio
) != 0;
2622 else if (AR_SREV_9280_20_OR_LATER(ah
))
2623 return MS_REG_READ(AR928X
, gpio
) != 0;
2625 return MS_REG_READ(AR
, gpio
) != 0;
2627 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
2629 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
2634 if (AR_DEVID_7010(ah
)) {
2636 REG_RMW(ah
, AR7010_GPIO_OE
,
2637 (AR7010_GPIO_OE_AS_OUTPUT
<< gpio_shift
),
2638 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2642 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
2643 gpio_shift
= 2 * gpio
;
2646 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
2647 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2649 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
2651 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
2653 if (AR_DEVID_7010(ah
)) {
2655 REG_RMW(ah
, AR7010_GPIO_OUT
, ((val
&1) << gpio
),
2660 if (AR_SREV_9271(ah
))
2663 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
2666 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
2668 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
2670 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
2672 EXPORT_SYMBOL(ath9k_hw_setantenna
);
2674 /*********************/
2675 /* General Operation */
2676 /*********************/
2678 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
2680 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
2681 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
2683 if (phybits
& AR_PHY_ERR_RADAR
)
2684 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
2685 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
2686 bits
|= ATH9K_RX_FILTER_PHYERR
;
2690 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
2692 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
2696 ENABLE_REGWRITE_BUFFER(ah
);
2698 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
))
2699 bits
|= ATH9K_RX_FILTER_CONTROL_WRAPPER
;
2701 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
2704 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
2705 phybits
|= AR_PHY_ERR_RADAR
;
2706 if (bits
& ATH9K_RX_FILTER_PHYERR
)
2707 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
2708 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
2711 REG_SET_BIT(ah
, AR_RXCFG
, AR_RXCFG_ZLFDMA
);
2713 REG_CLR_BIT(ah
, AR_RXCFG
, AR_RXCFG_ZLFDMA
);
2715 REGWRITE_BUFFER_FLUSH(ah
);
2717 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
2719 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
2721 if (ath9k_hw_mci_is_enabled(ah
))
2722 ar9003_mci_bt_gain_ctrl(ah
);
2724 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
2727 ath9k_hw_init_pll(ah
, NULL
);
2728 ah
->htc_reset_init
= true;
2731 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
2733 bool ath9k_hw_disable(struct ath_hw
*ah
)
2735 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2738 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
2741 ath9k_hw_init_pll(ah
, NULL
);
2744 EXPORT_SYMBOL(ath9k_hw_disable
);
2746 static int get_antenna_gain(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2748 enum eeprom_param gain_param
;
2750 if (IS_CHAN_2GHZ(chan
))
2751 gain_param
= EEP_ANTENNA_GAIN_2G
;
2753 gain_param
= EEP_ANTENNA_GAIN_5G
;
2755 return ah
->eep_ops
->get_eeprom(ah
, gain_param
);
2758 void ath9k_hw_apply_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
2761 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
2762 struct ieee80211_channel
*channel
;
2763 int chan_pwr
, new_pwr
, max_gain
;
2764 int ant_gain
, ant_reduction
= 0;
2769 channel
= chan
->chan
;
2770 chan_pwr
= min_t(int, channel
->max_power
* 2, MAX_RATE_POWER
);
2771 new_pwr
= min_t(int, chan_pwr
, reg
->power_limit
);
2772 max_gain
= chan_pwr
- new_pwr
+ channel
->max_antenna_gain
* 2;
2774 ant_gain
= get_antenna_gain(ah
, chan
);
2775 if (ant_gain
> max_gain
)
2776 ant_reduction
= ant_gain
- max_gain
;
2778 ah
->eep_ops
->set_txpower(ah
, chan
,
2779 ath9k_regd_get_ctl(reg
, chan
),
2780 ant_reduction
, new_pwr
, test
);
2783 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
, bool test
)
2785 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
2786 struct ath9k_channel
*chan
= ah
->curchan
;
2787 struct ieee80211_channel
*channel
= chan
->chan
;
2789 reg
->power_limit
= min_t(u32
, limit
, MAX_RATE_POWER
);
2791 channel
->max_power
= MAX_RATE_POWER
/ 2;
2793 ath9k_hw_apply_txpower(ah
, chan
, test
);
2796 channel
->max_power
= DIV_ROUND_UP(reg
->max_power_level
, 2);
2798 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
2800 void ath9k_hw_setopmode(struct ath_hw
*ah
)
2802 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2804 EXPORT_SYMBOL(ath9k_hw_setopmode
);
2806 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
2808 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
2809 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
2811 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
2813 void ath9k_hw_write_associd(struct ath_hw
*ah
)
2815 struct ath_common
*common
= ath9k_hw_common(ah
);
2817 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
2818 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
2819 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2821 EXPORT_SYMBOL(ath9k_hw_write_associd
);
2823 #define ATH9K_MAX_TSF_READ 10
2825 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
2827 u32 tsf_lower
, tsf_upper1
, tsf_upper2
;
2830 tsf_upper1
= REG_READ(ah
, AR_TSF_U32
);
2831 for (i
= 0; i
< ATH9K_MAX_TSF_READ
; i
++) {
2832 tsf_lower
= REG_READ(ah
, AR_TSF_L32
);
2833 tsf_upper2
= REG_READ(ah
, AR_TSF_U32
);
2834 if (tsf_upper2
== tsf_upper1
)
2836 tsf_upper1
= tsf_upper2
;
2839 WARN_ON( i
== ATH9K_MAX_TSF_READ
);
2841 return (((u64
)tsf_upper1
<< 32) | tsf_lower
);
2843 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
2845 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
2847 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
2848 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
2850 EXPORT_SYMBOL(ath9k_hw_settsf64
);
2852 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
2854 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
2855 AH_TSF_WRITE_TIMEOUT
))
2856 ath_dbg(ath9k_hw_common(ah
), RESET
,
2857 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2859 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
2861 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
2863 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, bool set
)
2866 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
2868 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
2870 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
2872 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2876 if (IS_CHAN_HT40(chan
) && !ah
->config
.cwm_ignore_extcca
)
2877 macmode
= AR_2040_JOINED_RX_CLEAR
;
2881 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
2884 /* HW Generic timers configuration */
2886 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
2888 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2889 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2890 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2891 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2892 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2893 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2894 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2895 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2896 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
2897 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
2898 AR_NDP2_TIMER_MODE
, 0x0002},
2899 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
2900 AR_NDP2_TIMER_MODE
, 0x0004},
2901 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
2902 AR_NDP2_TIMER_MODE
, 0x0008},
2903 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
2904 AR_NDP2_TIMER_MODE
, 0x0010},
2905 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
2906 AR_NDP2_TIMER_MODE
, 0x0020},
2907 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
2908 AR_NDP2_TIMER_MODE
, 0x0040},
2909 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
2910 AR_NDP2_TIMER_MODE
, 0x0080}
2913 /* HW generic timer primitives */
2915 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
2917 return REG_READ(ah
, AR_TSF_L32
);
2919 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
2921 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
2922 void (*trigger
)(void *),
2923 void (*overflow
)(void *),
2927 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2928 struct ath_gen_timer
*timer
;
2930 if ((timer_index
< AR_FIRST_NDP_TIMER
) ||
2931 (timer_index
>= ATH_MAX_GEN_TIMER
))
2934 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
2938 /* allocate a hardware generic timer slot */
2939 timer_table
->timers
[timer_index
] = timer
;
2940 timer
->index
= timer_index
;
2941 timer
->trigger
= trigger
;
2942 timer
->overflow
= overflow
;
2947 EXPORT_SYMBOL(ath_gen_timer_alloc
);
2949 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
2950 struct ath_gen_timer
*timer
,
2954 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2957 timer_table
->timer_mask
|= BIT(timer
->index
);
2960 * Program generic timer registers
2962 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
2964 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
2966 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2967 gen_tmr_configuration
[timer
->index
].mode_mask
);
2969 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
2971 * Starting from AR9462, each generic timer can select which tsf
2972 * to use. But we still follow the old rule, 0 - 7 use tsf and
2975 if ((timer
->index
< AR_GEN_TIMER_BANK_1_LEN
))
2976 REG_CLR_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
2977 (1 << timer
->index
));
2979 REG_SET_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
2980 (1 << timer
->index
));
2984 mask
|= SM(AR_GENTMR_BIT(timer
->index
),
2985 AR_IMR_S5_GENTIMER_TRIG
);
2986 if (timer
->overflow
)
2987 mask
|= SM(AR_GENTMR_BIT(timer
->index
),
2988 AR_IMR_S5_GENTIMER_THRESH
);
2990 REG_SET_BIT(ah
, AR_IMR_S5
, mask
);
2992 if ((ah
->imask
& ATH9K_INT_GENTIMER
) == 0) {
2993 ah
->imask
|= ATH9K_INT_GENTIMER
;
2994 ath9k_hw_set_interrupts(ah
);
2997 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
2999 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3001 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3003 /* Clear generic timer enable bits. */
3004 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3005 gen_tmr_configuration
[timer
->index
].mode_mask
);
3007 if (AR_SREV_9462(ah
) || AR_SREV_9565(ah
)) {
3009 * Need to switch back to TSF if it was using TSF2.
3011 if ((timer
->index
>= AR_GEN_TIMER_BANK_1_LEN
)) {
3012 REG_CLR_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
3013 (1 << timer
->index
));
3017 /* Disable both trigger and thresh interrupt masks */
3018 REG_CLR_BIT(ah
, AR_IMR_S5
,
3019 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3020 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3022 timer_table
->timer_mask
&= ~BIT(timer
->index
);
3024 if (timer_table
->timer_mask
== 0) {
3025 ah
->imask
&= ~ATH9K_INT_GENTIMER
;
3026 ath9k_hw_set_interrupts(ah
);
3029 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
3031 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3033 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3035 /* free the hardware generic timer slot */
3036 timer_table
->timers
[timer
->index
] = NULL
;
3039 EXPORT_SYMBOL(ath_gen_timer_free
);
3042 * Generic Timer Interrupts handling
3044 void ath_gen_timer_isr(struct ath_hw
*ah
)
3046 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3047 struct ath_gen_timer
*timer
;
3048 unsigned long trigger_mask
, thresh_mask
;
3051 /* get hardware generic timer interrupt status */
3052 trigger_mask
= ah
->intr_gen_timer_trigger
;
3053 thresh_mask
= ah
->intr_gen_timer_thresh
;
3054 trigger_mask
&= timer_table
->timer_mask
;
3055 thresh_mask
&= timer_table
->timer_mask
;
3057 for_each_set_bit(index
, &thresh_mask
, ARRAY_SIZE(timer_table
->timers
)) {
3058 timer
= timer_table
->timers
[index
];
3061 if (!timer
->overflow
)
3064 trigger_mask
&= ~BIT(index
);
3065 timer
->overflow(timer
->arg
);
3068 for_each_set_bit(index
, &trigger_mask
, ARRAY_SIZE(timer_table
->timers
)) {
3069 timer
= timer_table
->timers
[index
];
3072 if (!timer
->trigger
)
3074 timer
->trigger(timer
->arg
);
3077 EXPORT_SYMBOL(ath_gen_timer_isr
);
3086 } ath_mac_bb_names
[] = {
3087 /* Devices with external radios */
3088 { AR_SREV_VERSION_5416_PCI
, "5416" },
3089 { AR_SREV_VERSION_5416_PCIE
, "5418" },
3090 { AR_SREV_VERSION_9100
, "9100" },
3091 { AR_SREV_VERSION_9160
, "9160" },
3092 /* Single-chip solutions */
3093 { AR_SREV_VERSION_9280
, "9280" },
3094 { AR_SREV_VERSION_9285
, "9285" },
3095 { AR_SREV_VERSION_9287
, "9287" },
3096 { AR_SREV_VERSION_9271
, "9271" },
3097 { AR_SREV_VERSION_9300
, "9300" },
3098 { AR_SREV_VERSION_9330
, "9330" },
3099 { AR_SREV_VERSION_9340
, "9340" },
3100 { AR_SREV_VERSION_9485
, "9485" },
3101 { AR_SREV_VERSION_9462
, "9462" },
3102 { AR_SREV_VERSION_9550
, "9550" },
3103 { AR_SREV_VERSION_9565
, "9565" },
3104 { AR_SREV_VERSION_9531
, "9531" },
3107 /* For devices with external radios */
3111 } ath_rf_names
[] = {
3113 { AR_RAD5133_SREV_MAJOR
, "5133" },
3114 { AR_RAD5122_SREV_MAJOR
, "5122" },
3115 { AR_RAD2133_SREV_MAJOR
, "2133" },
3116 { AR_RAD2122_SREV_MAJOR
, "2122" }
3120 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3122 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
3126 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
3127 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
3128 return ath_mac_bb_names
[i
].name
;
3136 * Return the RF name. "????" is returned if the RF is unknown.
3137 * Used for devices with external radios.
3139 static const char *ath9k_hw_rf_name(u16 rf_version
)
3143 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
3144 if (ath_rf_names
[i
].version
== rf_version
) {
3145 return ath_rf_names
[i
].name
;
3152 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
3156 /* chipsets >= AR9280 are single-chip */
3157 if (AR_SREV_9280_20_OR_LATER(ah
)) {
3158 used
= scnprintf(hw_name
, len
,
3159 "Atheros AR%s Rev:%x",
3160 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3161 ah
->hw_version
.macRev
);
3164 used
= scnprintf(hw_name
, len
,
3165 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3166 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3167 ah
->hw_version
.macRev
,
3168 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
3169 & AR_RADIO_SREV_MAJOR
)),
3170 ah
->hw_version
.phyRev
);
3173 hw_name
[used
] = '\0';
3175 EXPORT_SYMBOL(ath9k_hw_name
);