2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
29 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
30 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
31 struct ar5416_eeprom_def
*pEepData
,
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
39 static int __init
ath9k_init(void)
43 module_init(ath9k_init
);
45 static void __exit
ath9k_exit(void)
49 module_exit(ath9k_exit
);
51 /********************/
52 /* Helper Functions */
53 /********************/
55 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
57 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
59 if (!ah
->curchan
) /* should really check for CCK instead */
60 return usecs
*ATH9K_CLOCK_RATE_CCK
;
61 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
62 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
63 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
66 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
68 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
70 if (conf_is_ht40(conf
))
71 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
73 return ath9k_hw_mac_clks(ah
, usecs
);
76 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
80 BUG_ON(timeout
< AH_TIME_QUANTUM
);
82 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
83 if ((REG_READ(ah
, reg
) & mask
) == val
)
86 udelay(AH_TIME_QUANTUM
);
89 ath_print(ath9k_hw_common(ah
), ATH_DBG_ANY
,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
95 EXPORT_SYMBOL(ath9k_hw_wait
);
97 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
102 for (i
= 0, retval
= 0; i
< n
; i
++) {
103 retval
= (retval
<< 1) | (val
& 1);
109 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
113 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
115 if (flags
& CHANNEL_5GHZ
) {
116 *low
= pCap
->low_5ghz_chan
;
117 *high
= pCap
->high_5ghz_chan
;
120 if ((flags
& CHANNEL_2GHZ
)) {
121 *low
= pCap
->low_2ghz_chan
;
122 *high
= pCap
->high_2ghz_chan
;
128 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
130 u32 frameLen
, u16 rateix
,
133 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
139 case WLAN_RC_PHY_CCK
:
140 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
143 numBits
= frameLen
<< 3;
144 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
146 case WLAN_RC_PHY_OFDM
:
147 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
148 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
149 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
150 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
151 txTime
= OFDM_SIFS_TIME_QUARTER
152 + OFDM_PREAMBLE_TIME_QUARTER
153 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
154 } else if (ah
->curchan
&&
155 IS_CHAN_HALF_RATE(ah
->curchan
)) {
156 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
157 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
158 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
159 txTime
= OFDM_SIFS_TIME_HALF
+
160 OFDM_PREAMBLE_TIME_HALF
161 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
163 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
164 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
165 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
166 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
167 + (numSymbols
* OFDM_SYMBOL_TIME
);
171 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
172 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
179 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
181 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
182 struct ath9k_channel
*chan
,
183 struct chan_centers
*centers
)
187 if (!IS_CHAN_HT40(chan
)) {
188 centers
->ctl_center
= centers
->ext_center
=
189 centers
->synth_center
= chan
->channel
;
193 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
194 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
195 centers
->synth_center
=
196 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
199 centers
->synth_center
=
200 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
204 centers
->ctl_center
=
205 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
206 /* 25 MHz spacing is supported by hw but not on upper layers */
207 centers
->ext_center
=
208 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
215 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
219 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
222 val
= REG_READ(ah
, AR_SREV
);
223 ah
->hw_version
.macVersion
=
224 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
225 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
226 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
228 if (!AR_SREV_9100(ah
))
229 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
231 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
233 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
234 ah
->is_pciexpress
= true;
238 static int ath9k_hw_get_radiorev(struct ath_hw
*ah
)
243 REG_WRITE(ah
, AR_PHY(0x36), 0x00007058);
245 for (i
= 0; i
< 8; i
++)
246 REG_WRITE(ah
, AR_PHY(0x20), 0x00010000);
247 val
= (REG_READ(ah
, AR_PHY(256)) >> 24) & 0xff;
248 val
= ((val
& 0xf0) >> 4) | ((val
& 0x0f) << 4);
250 return ath9k_hw_reverse_bits(val
, 8);
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
257 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
259 if (AR_SREV_9100(ah
))
262 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
263 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
264 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
265 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
266 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
267 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
268 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
269 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
270 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
272 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
275 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
277 struct ath_common
*common
= ath9k_hw_common(ah
);
278 u32 regAddr
[2] = { AR_STA_ID0
, AR_PHY_BASE
+ (8 << 2) };
280 u32 patternData
[4] = { 0x55555555,
286 for (i
= 0; i
< 2; i
++) {
287 u32 addr
= regAddr
[i
];
290 regHold
[i
] = REG_READ(ah
, addr
);
291 for (j
= 0; j
< 0x100; j
++) {
292 wrData
= (j
<< 16) | j
;
293 REG_WRITE(ah
, addr
, wrData
);
294 rdData
= REG_READ(ah
, addr
);
295 if (rdData
!= wrData
) {
296 ath_print(common
, ATH_DBG_FATAL
,
297 "address test failed "
298 "addr: 0x%08x - wr:0x%08x != "
300 addr
, wrData
, rdData
);
304 for (j
= 0; j
< 4; j
++) {
305 wrData
= patternData
[j
];
306 REG_WRITE(ah
, addr
, wrData
);
307 rdData
= REG_READ(ah
, addr
);
308 if (wrData
!= rdData
) {
309 ath_print(common
, ATH_DBG_FATAL
,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != "
313 addr
, wrData
, rdData
);
317 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
324 static void ath9k_hw_init_config(struct ath_hw
*ah
)
328 ah
->config
.dma_beacon_response_time
= 2;
329 ah
->config
.sw_beacon_response_time
= 10;
330 ah
->config
.additional_swba_backoff
= 0;
331 ah
->config
.ack_6mb
= 0x0;
332 ah
->config
.cwm_ignore_extcca
= 0;
333 ah
->config
.pcie_powersave_enable
= 0;
334 ah
->config
.pcie_clock_req
= 0;
335 ah
->config
.pcie_waen
= 0;
336 ah
->config
.analog_shiftreg
= 1;
337 ah
->config
.ht_enable
= 1;
338 ah
->config
.ofdm_trig_low
= 200;
339 ah
->config
.ofdm_trig_high
= 500;
340 ah
->config
.cck_trig_high
= 200;
341 ah
->config
.cck_trig_low
= 100;
342 ah
->config
.enable_ani
= 1;
344 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
345 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
346 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
349 ah
->config
.rx_intr_mitigation
= true;
352 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
353 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
354 * This means we use it for all AR5416 devices, and the few
355 * minor PCI AR9280 devices out there.
357 * Serialization is required because these devices do not handle
358 * well the case of two concurrent reads/writes due to the latency
359 * involved. During one read/write another read/write can be issued
360 * on another CPU while the previous read/write may still be working
361 * on our hardware, if we hit this case the hardware poops in a loop.
362 * We prevent this by serializing reads and writes.
364 * This issue is not present on PCI-Express devices or pre-AR5416
365 * devices (legacy, 802.11abg).
367 if (num_possible_cpus() > 1)
368 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
370 EXPORT_SYMBOL(ath9k_hw_init
);
372 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
374 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
376 regulatory
->country_code
= CTRY_DEFAULT
;
377 regulatory
->power_limit
= MAX_RATE_POWER
;
378 regulatory
->tp_scale
= ATH9K_TP_SCALE_MAX
;
380 ah
->hw_version
.magic
= AR5416_MAGIC
;
381 ah
->hw_version
.subvendorid
= 0;
384 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
385 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
386 if (!AR_SREV_9100(ah
))
387 ah
->ah_flags
= AH_USE_EEPROM
;
390 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
391 ah
->beacon_interval
= 100;
392 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
393 ah
->slottime
= (u32
) -1;
394 ah
->globaltxtimeout
= (u32
) -1;
395 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
398 static int ath9k_hw_rf_claim(struct ath_hw
*ah
)
402 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
404 val
= ath9k_hw_get_radiorev(ah
);
405 switch (val
& AR_RADIO_SREV_MAJOR
) {
407 val
= AR_RAD5133_SREV_MAJOR
;
409 case AR_RAD5133_SREV_MAJOR
:
410 case AR_RAD5122_SREV_MAJOR
:
411 case AR_RAD2133_SREV_MAJOR
:
412 case AR_RAD2122_SREV_MAJOR
:
415 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
416 "Radio Chip Rev 0x%02X not supported\n",
417 val
& AR_RADIO_SREV_MAJOR
);
421 ah
->hw_version
.analog5GhzRev
= val
;
426 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
428 struct ath_common
*common
= ath9k_hw_common(ah
);
434 for (i
= 0; i
< 3; i
++) {
435 eeval
= ah
->eep_ops
->get_eeprom(ah
, AR_EEPROM_MAC(i
));
437 common
->macaddr
[2 * i
] = eeval
>> 8;
438 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
440 if (sum
== 0 || sum
== 0xffff * 3)
441 return -EADDRNOTAVAIL
;
446 static void ath9k_hw_init_rxgain_ini(struct ath_hw
*ah
)
450 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_17
) {
451 rxgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_RXGAIN_TYPE
);
453 if (rxgain_type
== AR5416_EEP_RXGAIN_13DB_BACKOFF
)
454 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
455 ar9280Modes_backoff_13db_rxgain_9280_2
,
456 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2
), 6);
457 else if (rxgain_type
== AR5416_EEP_RXGAIN_23DB_BACKOFF
)
458 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
459 ar9280Modes_backoff_23db_rxgain_9280_2
,
460 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2
), 6);
462 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
463 ar9280Modes_original_rxgain_9280_2
,
464 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
466 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
467 ar9280Modes_original_rxgain_9280_2
,
468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
472 static void ath9k_hw_init_txgain_ini(struct ath_hw
*ah
)
476 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_19
) {
477 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
479 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
)
480 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
481 ar9280Modes_high_power_tx_gain_9280_2
,
482 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2
), 6);
484 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
485 ar9280Modes_original_tx_gain_9280_2
,
486 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
488 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
489 ar9280Modes_original_tx_gain_9280_2
,
490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
494 static int ath9k_hw_post_init(struct ath_hw
*ah
)
498 if (!ath9k_hw_chip_test(ah
))
501 ecode
= ath9k_hw_rf_claim(ah
);
505 ecode
= ath9k_hw_eeprom_init(ah
);
509 ath_print(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
510 "Eeprom VER: %d, REV: %d\n",
511 ah
->eep_ops
->get_eeprom_ver(ah
),
512 ah
->eep_ops
->get_eeprom_rev(ah
));
514 if (!AR_SREV_9280_10_OR_LATER(ah
)) {
515 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
517 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
518 "Failed allocating banks for "
524 if (!AR_SREV_9100(ah
)) {
525 ath9k_hw_ani_setup(ah
);
526 ath9k_hw_ani_init(ah
);
532 static bool ath9k_hw_devid_supported(u16 devid
)
535 case AR5416_DEVID_PCI
:
536 case AR5416_DEVID_PCIE
:
537 case AR5416_AR9100_DEVID
:
538 case AR9160_DEVID_PCI
:
539 case AR9280_DEVID_PCI
:
540 case AR9280_DEVID_PCIE
:
541 case AR9285_DEVID_PCIE
:
542 case AR5416_DEVID_AR9287_PCI
:
543 case AR5416_DEVID_AR9287_PCIE
:
552 static bool ath9k_hw_macversion_supported(u32 macversion
)
554 switch (macversion
) {
555 case AR_SREV_VERSION_5416_PCI
:
556 case AR_SREV_VERSION_5416_PCIE
:
557 case AR_SREV_VERSION_9160
:
558 case AR_SREV_VERSION_9100
:
559 case AR_SREV_VERSION_9280
:
560 case AR_SREV_VERSION_9285
:
561 case AR_SREV_VERSION_9287
:
562 case AR_SREV_VERSION_9271
:
570 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
572 if (AR_SREV_9160_10_OR_LATER(ah
)) {
573 if (AR_SREV_9280_10_OR_LATER(ah
)) {
574 ah
->iq_caldata
.calData
= &iq_cal_single_sample
;
575 ah
->adcgain_caldata
.calData
=
576 &adc_gain_cal_single_sample
;
577 ah
->adcdc_caldata
.calData
=
578 &adc_dc_cal_single_sample
;
579 ah
->adcdc_calinitdata
.calData
=
582 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
583 ah
->adcgain_caldata
.calData
=
584 &adc_gain_cal_multi_sample
;
585 ah
->adcdc_caldata
.calData
=
586 &adc_dc_cal_multi_sample
;
587 ah
->adcdc_calinitdata
.calData
=
590 ah
->supp_cals
= ADC_GAIN_CAL
| ADC_DC_CAL
| IQ_MISMATCH_CAL
;
594 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
596 if (AR_SREV_9271(ah
)) {
597 INIT_INI_ARRAY(&ah
->iniModes
, ar9271Modes_9271
,
598 ARRAY_SIZE(ar9271Modes_9271
), 6);
599 INIT_INI_ARRAY(&ah
->iniCommon
, ar9271Common_9271
,
600 ARRAY_SIZE(ar9271Common_9271
), 2);
601 INIT_INI_ARRAY(&ah
->iniModes_9271_1_0_only
,
602 ar9271Modes_9271_1_0_only
,
603 ARRAY_SIZE(ar9271Modes_9271_1_0_only
), 6);
607 if (AR_SREV_9287_11_OR_LATER(ah
)) {
608 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_1
,
609 ARRAY_SIZE(ar9287Modes_9287_1_1
), 6);
610 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_1
,
611 ARRAY_SIZE(ar9287Common_9287_1_1
), 2);
612 if (ah
->config
.pcie_clock_req
)
613 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
614 ar9287PciePhy_clkreq_off_L1_9287_1_1
,
615 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1
), 2);
617 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
618 ar9287PciePhy_clkreq_always_on_L1_9287_1_1
,
619 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1
),
621 } else if (AR_SREV_9287_10_OR_LATER(ah
)) {
622 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_0
,
623 ARRAY_SIZE(ar9287Modes_9287_1_0
), 6);
624 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_0
,
625 ARRAY_SIZE(ar9287Common_9287_1_0
), 2);
627 if (ah
->config
.pcie_clock_req
)
628 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
629 ar9287PciePhy_clkreq_off_L1_9287_1_0
,
630 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0
), 2);
632 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
633 ar9287PciePhy_clkreq_always_on_L1_9287_1_0
,
634 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0
),
636 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
639 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285_1_2
,
640 ARRAY_SIZE(ar9285Modes_9285_1_2
), 6);
641 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285_1_2
,
642 ARRAY_SIZE(ar9285Common_9285_1_2
), 2);
644 if (ah
->config
.pcie_clock_req
) {
645 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
646 ar9285PciePhy_clkreq_off_L1_9285_1_2
,
647 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2
), 2);
649 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
650 ar9285PciePhy_clkreq_always_on_L1_9285_1_2
,
651 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2
),
654 } else if (AR_SREV_9285_10_OR_LATER(ah
)) {
655 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285
,
656 ARRAY_SIZE(ar9285Modes_9285
), 6);
657 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285
,
658 ARRAY_SIZE(ar9285Common_9285
), 2);
660 if (ah
->config
.pcie_clock_req
) {
661 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
662 ar9285PciePhy_clkreq_off_L1_9285
,
663 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285
), 2);
665 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
666 ar9285PciePhy_clkreq_always_on_L1_9285
,
667 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285
), 2);
669 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
670 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280_2
,
671 ARRAY_SIZE(ar9280Modes_9280_2
), 6);
672 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280_2
,
673 ARRAY_SIZE(ar9280Common_9280_2
), 2);
675 if (ah
->config
.pcie_clock_req
) {
676 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
677 ar9280PciePhy_clkreq_off_L1_9280
,
678 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280
),2);
680 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
681 ar9280PciePhy_clkreq_always_on_L1_9280
,
682 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280
), 2);
684 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
685 ar9280Modes_fast_clock_9280_2
,
686 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2
), 3);
687 } else if (AR_SREV_9280_10_OR_LATER(ah
)) {
688 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280
,
689 ARRAY_SIZE(ar9280Modes_9280
), 6);
690 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280
,
691 ARRAY_SIZE(ar9280Common_9280
), 2);
692 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
693 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9160
,
694 ARRAY_SIZE(ar5416Modes_9160
), 6);
695 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9160
,
696 ARRAY_SIZE(ar5416Common_9160
), 2);
697 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9160
,
698 ARRAY_SIZE(ar5416Bank0_9160
), 2);
699 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9160
,
700 ARRAY_SIZE(ar5416BB_RfGain_9160
), 3);
701 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9160
,
702 ARRAY_SIZE(ar5416Bank1_9160
), 2);
703 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9160
,
704 ARRAY_SIZE(ar5416Bank2_9160
), 2);
705 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9160
,
706 ARRAY_SIZE(ar5416Bank3_9160
), 3);
707 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9160
,
708 ARRAY_SIZE(ar5416Bank6_9160
), 3);
709 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9160
,
710 ARRAY_SIZE(ar5416Bank6TPC_9160
), 3);
711 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9160
,
712 ARRAY_SIZE(ar5416Bank7_9160
), 2);
713 if (AR_SREV_9160_11(ah
)) {
714 INIT_INI_ARRAY(&ah
->iniAddac
,
716 ARRAY_SIZE(ar5416Addac_91601_1
), 2);
718 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9160
,
719 ARRAY_SIZE(ar5416Addac_9160
), 2);
721 } else if (AR_SREV_9100_OR_LATER(ah
)) {
722 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9100
,
723 ARRAY_SIZE(ar5416Modes_9100
), 6);
724 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9100
,
725 ARRAY_SIZE(ar5416Common_9100
), 2);
726 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9100
,
727 ARRAY_SIZE(ar5416Bank0_9100
), 2);
728 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9100
,
729 ARRAY_SIZE(ar5416BB_RfGain_9100
), 3);
730 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9100
,
731 ARRAY_SIZE(ar5416Bank1_9100
), 2);
732 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9100
,
733 ARRAY_SIZE(ar5416Bank2_9100
), 2);
734 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9100
,
735 ARRAY_SIZE(ar5416Bank3_9100
), 3);
736 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9100
,
737 ARRAY_SIZE(ar5416Bank6_9100
), 3);
738 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9100
,
739 ARRAY_SIZE(ar5416Bank6TPC_9100
), 3);
740 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9100
,
741 ARRAY_SIZE(ar5416Bank7_9100
), 2);
742 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9100
,
743 ARRAY_SIZE(ar5416Addac_9100
), 2);
745 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes
,
746 ARRAY_SIZE(ar5416Modes
), 6);
747 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common
,
748 ARRAY_SIZE(ar5416Common
), 2);
749 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0
,
750 ARRAY_SIZE(ar5416Bank0
), 2);
751 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain
,
752 ARRAY_SIZE(ar5416BB_RfGain
), 3);
753 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1
,
754 ARRAY_SIZE(ar5416Bank1
), 2);
755 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2
,
756 ARRAY_SIZE(ar5416Bank2
), 2);
757 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3
,
758 ARRAY_SIZE(ar5416Bank3
), 3);
759 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6
,
760 ARRAY_SIZE(ar5416Bank6
), 3);
761 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC
,
762 ARRAY_SIZE(ar5416Bank6TPC
), 3);
763 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7
,
764 ARRAY_SIZE(ar5416Bank7
), 2);
765 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac
,
766 ARRAY_SIZE(ar5416Addac
), 2);
770 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
772 if (AR_SREV_9287_11_OR_LATER(ah
))
773 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
774 ar9287Modes_rx_gain_9287_1_1
,
775 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1
), 6);
776 else if (AR_SREV_9287_10(ah
))
777 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
778 ar9287Modes_rx_gain_9287_1_0
,
779 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0
), 6);
780 else if (AR_SREV_9280_20(ah
))
781 ath9k_hw_init_rxgain_ini(ah
);
783 if (AR_SREV_9287_11_OR_LATER(ah
)) {
784 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
785 ar9287Modes_tx_gain_9287_1_1
,
786 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1
), 6);
787 } else if (AR_SREV_9287_10(ah
)) {
788 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
789 ar9287Modes_tx_gain_9287_1_0
,
790 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0
), 6);
791 } else if (AR_SREV_9280_20(ah
)) {
792 ath9k_hw_init_txgain_ini(ah
);
793 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
794 u32 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
797 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
) {
798 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
799 ar9285Modes_high_power_tx_gain_9285_1_2
,
800 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2
), 6);
802 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
803 ar9285Modes_original_tx_gain_9285_1_2
,
804 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2
), 6);
810 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw
*ah
)
814 if ((ah
->hw_version
.devid
== AR9280_DEVID_PCI
) &&
815 test_bit(ATH9K_MODE_11A
, ah
->caps
.wireless_modes
)) {
818 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
819 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
821 for (j
= 1; j
< ah
->iniModes
.ia_columns
; j
++) {
822 u32 val
= INI_RA(&ah
->iniModes
, i
, j
);
824 INI_RA(&ah
->iniModes
, i
, j
) =
825 ath9k_hw_ini_fixup(ah
,
833 int ath9k_hw_init(struct ath_hw
*ah
)
835 struct ath_common
*common
= ath9k_hw_common(ah
);
838 if (!ath9k_hw_devid_supported(ah
->hw_version
.devid
)) {
839 ath_print(common
, ATH_DBG_FATAL
,
840 "Unsupported device ID: 0x%0x\n",
841 ah
->hw_version
.devid
);
845 ath9k_hw_init_defaults(ah
);
846 ath9k_hw_init_config(ah
);
848 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
849 ath_print(common
, ATH_DBG_FATAL
,
850 "Couldn't reset chip\n");
854 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
855 ath_print(common
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
859 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
860 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
861 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
862 ah
->config
.serialize_regmode
=
865 ah
->config
.serialize_regmode
=
870 ath_print(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
871 ah
->config
.serialize_regmode
);
873 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
874 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
876 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
878 if (!ath9k_hw_macversion_supported(ah
->hw_version
.macVersion
)) {
879 ath_print(common
, ATH_DBG_FATAL
,
880 "Mac Chip Rev 0x%02x.%x is not supported by "
881 "this driver\n", ah
->hw_version
.macVersion
,
882 ah
->hw_version
.macRev
);
886 if (AR_SREV_9100(ah
)) {
887 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
888 ah
->supp_cals
= IQ_MISMATCH_CAL
;
889 ah
->is_pciexpress
= false;
892 if (AR_SREV_9271(ah
))
893 ah
->is_pciexpress
= false;
895 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
897 ath9k_hw_init_cal_settings(ah
);
899 ah
->ani_function
= ATH9K_ANI_ALL
;
900 if (AR_SREV_9280_10_OR_LATER(ah
)) {
901 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
902 ah
->ath9k_hw_rf_set_freq
= &ath9k_hw_ar9280_set_channel
;
903 ah
->ath9k_hw_spur_mitigate_freq
= &ath9k_hw_9280_spur_mitigate
;
905 ah
->ath9k_hw_rf_set_freq
= &ath9k_hw_set_channel
;
906 ah
->ath9k_hw_spur_mitigate_freq
= &ath9k_hw_spur_mitigate
;
909 ath9k_hw_init_mode_regs(ah
);
911 if (ah
->is_pciexpress
)
912 ath9k_hw_configpcipowersave(ah
, 0, 0);
914 ath9k_hw_disablepcie(ah
);
916 /* Support for Japan ch.14 (2484) spread */
917 if (AR_SREV_9287_11_OR_LATER(ah
)) {
918 INIT_INI_ARRAY(&ah
->iniCckfirNormal
,
919 ar9287Common_normal_cck_fir_coeff_92871_1
,
920 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1
), 2);
921 INIT_INI_ARRAY(&ah
->iniCckfirJapan2484
,
922 ar9287Common_japan_2484_cck_fir_coeff_92871_1
,
923 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1
), 2);
926 r
= ath9k_hw_post_init(ah
);
930 ath9k_hw_init_mode_gain_regs(ah
);
931 r
= ath9k_hw_fill_cap_info(ah
);
935 ath9k_hw_init_11a_eeprom_fix(ah
);
937 r
= ath9k_hw_init_macaddr(ah
);
939 ath_print(common
, ATH_DBG_FATAL
,
940 "Failed to initialize MAC address\n");
944 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
945 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
947 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
949 ath9k_init_nfcal_hist_buffer(ah
);
951 common
->state
= ATH_HW_INITIALIZED
;
956 static void ath9k_hw_init_bb(struct ath_hw
*ah
,
957 struct ath9k_channel
*chan
)
961 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
963 synthDelay
= (4 * synthDelay
) / 22;
967 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_EN
);
969 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
972 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
974 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
975 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
977 REG_WRITE(ah
, AR_QOS_NO_ACK
,
978 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
979 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
980 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
982 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
983 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
984 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
985 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
986 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
989 static void ath9k_hw_change_target_baud(struct ath_hw
*ah
, u32 freq
, u32 baud
)
992 u32 baud_divider
= freq
* 1000 * 1000 / 16 / baud
;
994 lcr
= REG_READ(ah
, 0x5100c);
997 REG_WRITE(ah
, 0x5100c, lcr
);
998 REG_WRITE(ah
, 0x51004, (baud_divider
>> 8));
999 REG_WRITE(ah
, 0x51000, (baud_divider
& 0xff));
1002 REG_WRITE(ah
, 0x5100c, lcr
);
1005 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
1006 struct ath9k_channel
*chan
)
1010 if (AR_SREV_9100(ah
)) {
1011 if (chan
&& IS_CHAN_5GHZ(chan
))
1016 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1017 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1019 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1020 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1021 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1022 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1024 if (chan
&& IS_CHAN_5GHZ(chan
)) {
1025 pll
|= SM(0x28, AR_RTC_9160_PLL_DIV
);
1028 if (AR_SREV_9280_20(ah
)) {
1029 if (((chan
->channel
% 20) == 0)
1030 || ((chan
->channel
% 10) == 0))
1036 pll
|= SM(0x2c, AR_RTC_9160_PLL_DIV
);
1039 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1041 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1043 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1044 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1045 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1046 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1048 if (chan
&& IS_CHAN_5GHZ(chan
))
1049 pll
|= SM(0x50, AR_RTC_9160_PLL_DIV
);
1051 pll
|= SM(0x58, AR_RTC_9160_PLL_DIV
);
1053 pll
= AR_RTC_PLL_REFDIV_5
| AR_RTC_PLL_DIV2
;
1055 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1056 pll
|= SM(0x1, AR_RTC_PLL_CLKSEL
);
1057 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1058 pll
|= SM(0x2, AR_RTC_PLL_CLKSEL
);
1060 if (chan
&& IS_CHAN_5GHZ(chan
))
1061 pll
|= SM(0xa, AR_RTC_PLL_DIV
);
1063 pll
|= SM(0xb, AR_RTC_PLL_DIV
);
1066 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
1068 /* Switch the core clock for ar9271 to 117Mhz */
1069 if (AR_SREV_9271(ah
)) {
1070 if ((pll
== 0x142c) || (pll
== 0x2850) ) {
1072 /* set CLKOBS to output AHB clock */
1073 REG_WRITE(ah
, 0x7020, 0xe);
1075 * 0x304: 117Mhz, ahb_ratio: 1x1
1076 * 0x306: 40Mhz, ahb_ratio: 1x1
1078 REG_WRITE(ah
, 0x50040, 0x304);
1080 * makes adjustments for the baud dividor to keep the
1081 * targetted baud rate based on the used core clock.
1083 ath9k_hw_change_target_baud(ah
, AR9271_CORE_CLOCK
,
1084 AR9271_TARGET_BAUD_RATE
);
1088 udelay(RTC_PLL_SETTLE_DELAY
);
1090 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
1093 static void ath9k_hw_init_chain_masks(struct ath_hw
*ah
)
1095 int rx_chainmask
, tx_chainmask
;
1097 rx_chainmask
= ah
->rxchainmask
;
1098 tx_chainmask
= ah
->txchainmask
;
1100 switch (rx_chainmask
) {
1102 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1103 AR_PHY_SWAP_ALT_CHAIN
);
1105 if (ah
->hw_version
.macVersion
== AR_SREV_REVISION_5416_10
) {
1106 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, 0x7);
1107 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, 0x7);
1113 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
1114 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
1120 REG_WRITE(ah
, AR_SELFGEN_MASK
, tx_chainmask
);
1121 if (tx_chainmask
== 0x5) {
1122 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1123 AR_PHY_SWAP_ALT_CHAIN
);
1125 if (AR_SREV_9100(ah
))
1126 REG_WRITE(ah
, AR_PHY_ANALOG_SWAP
,
1127 REG_READ(ah
, AR_PHY_ANALOG_SWAP
) | 0x00000001);
1130 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
1131 enum nl80211_iftype opmode
)
1133 ah
->mask_reg
= AR_IMR_TXERR
|
1139 if (ah
->config
.rx_intr_mitigation
)
1140 ah
->mask_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
1142 ah
->mask_reg
|= AR_IMR_RXOK
;
1144 ah
->mask_reg
|= AR_IMR_TXOK
;
1146 if (opmode
== NL80211_IFTYPE_AP
)
1147 ah
->mask_reg
|= AR_IMR_MIB
;
1149 REG_WRITE(ah
, AR_IMR
, ah
->mask_reg
);
1150 REG_WRITE(ah
, AR_IMR_S2
, REG_READ(ah
, AR_IMR_S2
) | AR_IMR_S2_GTT
);
1152 if (!AR_SREV_9100(ah
)) {
1153 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
1154 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
1155 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
1159 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
1161 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1162 val
= min(val
, (u32
) 0xFFFF);
1163 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
1166 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
1168 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1169 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
1170 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
1173 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
1175 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
1176 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
1177 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
1180 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
1183 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
1184 "bad global tx timeout %u\n", tu
);
1185 ah
->globaltxtimeout
= (u32
) -1;
1188 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
1189 ah
->globaltxtimeout
= tu
;
1194 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
1196 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
1200 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
1203 if (ah
->misc_mode
!= 0)
1204 REG_WRITE(ah
, AR_PCU_MISC
,
1205 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
1207 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_5GHZ
)
1212 acktimeout
= ah
->slottime
+ sifstime
;
1213 ath9k_hw_setslottime(ah
, ah
->slottime
);
1214 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
1215 ath9k_hw_set_cts_timeout(ah
, acktimeout
);
1216 if (ah
->globaltxtimeout
!= (u32
) -1)
1217 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1219 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
1221 void ath9k_hw_deinit(struct ath_hw
*ah
)
1223 struct ath_common
*common
= ath9k_hw_common(ah
);
1225 if (common
->state
<= ATH_HW_INITIALIZED
)
1228 if (!AR_SREV_9100(ah
))
1229 ath9k_hw_ani_disable(ah
);
1231 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1234 if (!AR_SREV_9280_10_OR_LATER(ah
))
1235 ath9k_hw_rf_free_ext_banks(ah
);
1239 EXPORT_SYMBOL(ath9k_hw_deinit
);
1245 static void ath9k_hw_override_ini(struct ath_hw
*ah
,
1246 struct ath9k_channel
*chan
)
1250 if (AR_SREV_9271(ah
)) {
1252 * Enable spectral scan to solution for issues with stuck
1253 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1256 if (AR_SREV_9271_10(ah
)) {
1257 val
= REG_READ(ah
, AR_PHY_SPECTRAL_SCAN
) |
1258 AR_PHY_SPECTRAL_SCAN_ENABLE
;
1259 REG_WRITE(ah
, AR_PHY_SPECTRAL_SCAN
, val
);
1261 else if (AR_SREV_9271_11(ah
))
1263 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1264 * present on AR9271 1.1
1266 REG_WRITE(ah
, AR_PHY_RF_CTL3
, 0x3a020001);
1271 * Set the RX_ABORT and RX_DIS and clear if off only after
1272 * RXE is set for MAC. This prevents frames with corrupted
1273 * descriptor status.
1275 REG_SET_BIT(ah
, AR_DIAG_SW
, (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
1277 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1278 val
= REG_READ(ah
, AR_PCU_MISC_MODE2
) &
1279 (~AR_PCU_MISC_MODE2_HWWAR1
);
1281 if (AR_SREV_9287_10_OR_LATER(ah
))
1282 val
= val
& (~AR_PCU_MISC_MODE2_HWWAR2
);
1284 REG_WRITE(ah
, AR_PCU_MISC_MODE2
, val
);
1287 if (!AR_SREV_5416_20_OR_LATER(ah
) ||
1288 AR_SREV_9280_10_OR_LATER(ah
))
1291 * Disable BB clock gating
1292 * Necessary to avoid issues on AR5416 2.0
1294 REG_WRITE(ah
, 0x9800 + (651 << 2), 0x11);
1297 static u32
ath9k_hw_def_ini_fixup(struct ath_hw
*ah
,
1298 struct ar5416_eeprom_def
*pEepData
,
1301 struct base_eep_header
*pBase
= &(pEepData
->baseEepHeader
);
1302 struct ath_common
*common
= ath9k_hw_common(ah
);
1304 switch (ah
->hw_version
.devid
) {
1305 case AR9280_DEVID_PCI
:
1306 if (reg
== 0x7894) {
1307 ath_print(common
, ATH_DBG_EEPROM
,
1308 "ini VAL: %x EEPROM: %x\n", value
,
1309 (pBase
->version
& 0xff));
1311 if ((pBase
->version
& 0xff) > 0x0a) {
1312 ath_print(common
, ATH_DBG_EEPROM
,
1315 value
&= ~AR_AN_TOP2_PWDCLKIND
;
1316 value
|= AR_AN_TOP2_PWDCLKIND
&
1317 (pBase
->pwdclkind
<< AR_AN_TOP2_PWDCLKIND_S
);
1319 ath_print(common
, ATH_DBG_EEPROM
,
1320 "PWDCLKIND Earlier Rev\n");
1323 ath_print(common
, ATH_DBG_EEPROM
,
1324 "final ini VAL: %x\n", value
);
1332 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
1333 struct ar5416_eeprom_def
*pEepData
,
1336 if (ah
->eep_map
== EEP_MAP_4KBITS
)
1339 return ath9k_hw_def_ini_fixup(ah
, pEepData
, reg
, value
);
1342 static void ath9k_olc_init(struct ath_hw
*ah
)
1346 if (OLC_FOR_AR9287_10_LATER
) {
1347 REG_SET_BIT(ah
, AR_PHY_TX_PWRCTRL9
,
1348 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL
);
1349 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_TXPC0
,
1350 AR9287_AN_TXPC0_TXPCMODE
,
1351 AR9287_AN_TXPC0_TXPCMODE_S
,
1352 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE
);
1355 for (i
= 0; i
< AR9280_TX_GAIN_TABLE_SIZE
; i
++)
1356 ah
->originalGain
[i
] =
1357 MS(REG_READ(ah
, AR_PHY_TX_GAIN_TBL1
+ i
* 4),
1363 static u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
,
1364 struct ath9k_channel
*chan
)
1366 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1368 if (IS_CHAN_B(chan
))
1370 else if (IS_CHAN_G(chan
))
1378 static int ath9k_hw_process_ini(struct ath_hw
*ah
,
1379 struct ath9k_channel
*chan
)
1381 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1382 int i
, regWrites
= 0;
1383 struct ieee80211_channel
*channel
= chan
->chan
;
1384 u32 modesIndex
, freqIndex
;
1386 switch (chan
->chanmode
) {
1388 case CHANNEL_A_HT20
:
1392 case CHANNEL_A_HT40PLUS
:
1393 case CHANNEL_A_HT40MINUS
:
1398 case CHANNEL_G_HT20
:
1403 case CHANNEL_G_HT40PLUS
:
1404 case CHANNEL_G_HT40MINUS
:
1413 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
1414 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_EXTERNAL_RADIO
);
1415 ah
->eep_ops
->set_addac(ah
, chan
);
1417 if (AR_SREV_5416_22_OR_LATER(ah
)) {
1418 REG_WRITE_ARRAY(&ah
->iniAddac
, 1, regWrites
);
1420 struct ar5416IniArray temp
;
1422 sizeof(u32
) * ah
->iniAddac
.ia_rows
*
1423 ah
->iniAddac
.ia_columns
;
1425 memcpy(ah
->addac5416_21
,
1426 ah
->iniAddac
.ia_array
, addacSize
);
1428 (ah
->addac5416_21
)[31 * ah
->iniAddac
.ia_columns
+ 1] = 0;
1430 temp
.ia_array
= ah
->addac5416_21
;
1431 temp
.ia_columns
= ah
->iniAddac
.ia_columns
;
1432 temp
.ia_rows
= ah
->iniAddac
.ia_rows
;
1433 REG_WRITE_ARRAY(&temp
, 1, regWrites
);
1436 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_INTERNAL_ADDAC
);
1438 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
1439 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
1440 u32 val
= INI_RA(&ah
->iniModes
, i
, modesIndex
);
1442 REG_WRITE(ah
, reg
, val
);
1444 if (reg
>= 0x7800 && reg
< 0x78a0
1445 && ah
->config
.analog_shiftreg
) {
1449 DO_DELAY(regWrites
);
1452 if (AR_SREV_9280(ah
) || AR_SREV_9287_10_OR_LATER(ah
))
1453 REG_WRITE_ARRAY(&ah
->iniModesRxGain
, modesIndex
, regWrites
);
1455 if (AR_SREV_9280(ah
) || AR_SREV_9285_12_OR_LATER(ah
) ||
1456 AR_SREV_9287_10_OR_LATER(ah
))
1457 REG_WRITE_ARRAY(&ah
->iniModesTxGain
, modesIndex
, regWrites
);
1459 for (i
= 0; i
< ah
->iniCommon
.ia_rows
; i
++) {
1460 u32 reg
= INI_RA(&ah
->iniCommon
, i
, 0);
1461 u32 val
= INI_RA(&ah
->iniCommon
, i
, 1);
1463 REG_WRITE(ah
, reg
, val
);
1465 if (reg
>= 0x7800 && reg
< 0x78a0
1466 && ah
->config
.analog_shiftreg
) {
1470 DO_DELAY(regWrites
);
1473 ath9k_hw_write_regs(ah
, freqIndex
, regWrites
);
1475 if (AR_SREV_9271_10(ah
))
1476 REG_WRITE_ARRAY(&ah
->iniModes_9271_1_0_only
,
1477 modesIndex
, regWrites
);
1479 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
)) {
1480 REG_WRITE_ARRAY(&ah
->iniModesAdditional
, modesIndex
,
1484 ath9k_hw_override_ini(ah
, chan
);
1485 ath9k_hw_set_regs(ah
, chan
);
1486 ath9k_hw_init_chain_masks(ah
);
1488 if (OLC_FOR_AR9280_20_LATER
)
1491 ah
->eep_ops
->set_txpower(ah
, chan
,
1492 ath9k_regd_get_ctl(regulatory
, chan
),
1493 channel
->max_antenna_gain
* 2,
1494 channel
->max_power
* 2,
1495 min((u32
) MAX_RATE_POWER
,
1496 (u32
) regulatory
->power_limit
));
1498 if (!ath9k_hw_set_rf_regs(ah
, chan
, freqIndex
)) {
1499 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1500 "ar5416SetRfRegs failed\n");
1507 /****************************************/
1508 /* Reset and Channel Switching Routines */
1509 /****************************************/
1511 static void ath9k_hw_set_rfmode(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1518 rfMode
|= (IS_CHAN_B(chan
) || IS_CHAN_G(chan
))
1519 ? AR_PHY_MODE_DYNAMIC
: AR_PHY_MODE_OFDM
;
1521 if (!AR_SREV_9280_10_OR_LATER(ah
))
1522 rfMode
|= (IS_CHAN_5GHZ(chan
)) ?
1523 AR_PHY_MODE_RF5GHZ
: AR_PHY_MODE_RF2GHZ
;
1525 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
))
1526 rfMode
|= (AR_PHY_MODE_DYNAMIC
| AR_PHY_MODE_DYN_CCK_DISABLE
);
1528 REG_WRITE(ah
, AR_PHY_MODE
, rfMode
);
1531 static void ath9k_hw_mark_phy_inactive(struct ath_hw
*ah
)
1533 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_DIS
);
1536 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1541 * set AHB_MODE not to do cacheline prefetches
1543 regval
= REG_READ(ah
, AR_AHB_MODE
);
1544 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
1547 * let mac dma reads be in 128 byte chunks
1549 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
1550 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
1553 * Restore TX Trigger Level to its pre-reset value.
1554 * The initial value depends on whether aggregation is enabled, and is
1555 * adjusted whenever underruns are detected.
1557 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1560 * let mac dma writes be in 128 byte chunks
1562 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
1563 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
1566 * Setup receive FIFO threshold to hold off TX activities
1568 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1571 * reduce the number of usable entries in PCU TXBUF to avoid
1572 * wrap around issues.
1574 if (AR_SREV_9285(ah
)) {
1575 /* For AR9285 the number of Fifos are reduced to half.
1576 * So set the usable tx buf size also to half to
1577 * avoid data/delimiter underruns
1579 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1580 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1581 } else if (!AR_SREV_9271(ah
)) {
1582 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1583 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1587 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1591 val
= REG_READ(ah
, AR_STA_ID1
);
1592 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
1594 case NL80211_IFTYPE_AP
:
1595 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
1596 | AR_STA_ID1_KSRCH_MODE
);
1597 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1599 case NL80211_IFTYPE_ADHOC
:
1600 case NL80211_IFTYPE_MESH_POINT
:
1601 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
1602 | AR_STA_ID1_KSRCH_MODE
);
1603 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1605 case NL80211_IFTYPE_STATION
:
1606 case NL80211_IFTYPE_MONITOR
:
1607 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
1612 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
,
1617 u32 coef_exp
, coef_man
;
1619 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1620 if ((coef_scaled
>> coef_exp
) & 0x1)
1623 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1625 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1627 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1628 *coef_exponent
= coef_exp
- 16;
1631 static void ath9k_hw_set_delta_slope(struct ath_hw
*ah
,
1632 struct ath9k_channel
*chan
)
1634 u32 coef_scaled
, ds_coef_exp
, ds_coef_man
;
1635 u32 clockMhzScaled
= 0x64000000;
1636 struct chan_centers centers
;
1638 if (IS_CHAN_HALF_RATE(chan
))
1639 clockMhzScaled
= clockMhzScaled
>> 1;
1640 else if (IS_CHAN_QUARTER_RATE(chan
))
1641 clockMhzScaled
= clockMhzScaled
>> 2;
1643 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1644 coef_scaled
= clockMhzScaled
/ centers
.synth_center
;
1646 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1649 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1650 AR_PHY_TIMING3_DSC_MAN
, ds_coef_man
);
1651 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1652 AR_PHY_TIMING3_DSC_EXP
, ds_coef_exp
);
1654 coef_scaled
= (9 * coef_scaled
) / 10;
1656 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1659 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1660 AR_PHY_HALFGI_DSC_MAN
, ds_coef_man
);
1661 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1662 AR_PHY_HALFGI_DSC_EXP
, ds_coef_exp
);
1665 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1670 if (AR_SREV_9100(ah
)) {
1671 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1672 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
1673 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
1674 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
1675 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1678 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1679 AR_RTC_FORCE_WAKE_ON_INT
);
1681 if (AR_SREV_9100(ah
)) {
1682 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1683 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1685 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1687 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1688 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1689 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1690 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1692 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1695 rst_flags
= AR_RTC_RC_MAC_WARM
;
1696 if (type
== ATH9K_RESET_COLD
)
1697 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1700 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1703 REG_WRITE(ah
, AR_RTC_RC
, 0);
1704 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1705 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1706 "RTC stuck in MAC reset\n");
1710 if (!AR_SREV_9100(ah
))
1711 REG_WRITE(ah
, AR_RC
, 0);
1713 if (AR_SREV_9100(ah
))
1719 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1721 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1722 AR_RTC_FORCE_WAKE_ON_INT
);
1724 if (!AR_SREV_9100(ah
))
1725 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1727 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1730 if (!AR_SREV_9100(ah
))
1731 REG_WRITE(ah
, AR_RC
, 0);
1733 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1735 if (!ath9k_hw_wait(ah
,
1740 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1741 "RTC not waking up\n");
1745 ath9k_hw_read_revisions(ah
);
1747 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1750 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1752 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1753 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1756 case ATH9K_RESET_POWER_ON
:
1757 return ath9k_hw_set_reset_power_on(ah
);
1758 case ATH9K_RESET_WARM
:
1759 case ATH9K_RESET_COLD
:
1760 return ath9k_hw_set_reset(ah
, type
);
1766 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1769 u32 enableDacFifo
= 0;
1771 if (AR_SREV_9285_10_OR_LATER(ah
))
1772 enableDacFifo
= (REG_READ(ah
, AR_PHY_TURBO
) &
1773 AR_PHY_FC_ENABLE_DAC_FIFO
);
1775 phymode
= AR_PHY_FC_HT_EN
| AR_PHY_FC_SHORT_GI_40
1776 | AR_PHY_FC_SINGLE_HT_LTF1
| AR_PHY_FC_WALSH
| enableDacFifo
;
1778 if (IS_CHAN_HT40(chan
)) {
1779 phymode
|= AR_PHY_FC_DYN2040_EN
;
1781 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
1782 (chan
->chanmode
== CHANNEL_G_HT40PLUS
))
1783 phymode
|= AR_PHY_FC_DYN2040_PRI_CH
;
1786 REG_WRITE(ah
, AR_PHY_TURBO
, phymode
);
1788 ath9k_hw_set11nmac2040(ah
);
1790 REG_WRITE(ah
, AR_GTXTO
, 25 << AR_GTXTO_TIMEOUT_LIMIT_S
);
1791 REG_WRITE(ah
, AR_CST
, 0xF << AR_CST_TIMEOUT_LIMIT_S
);
1794 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1795 struct ath9k_channel
*chan
)
1797 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1798 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1800 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1803 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1806 ah
->chip_fullsleep
= false;
1807 ath9k_hw_init_pll(ah
, chan
);
1808 ath9k_hw_set_rfmode(ah
, chan
);
1813 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1814 struct ath9k_channel
*chan
)
1816 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1817 struct ath_common
*common
= ath9k_hw_common(ah
);
1818 struct ieee80211_channel
*channel
= chan
->chan
;
1819 u32 synthDelay
, qnum
;
1822 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1823 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1824 ath_print(common
, ATH_DBG_QUEUE
,
1825 "Transmit frames pending on "
1826 "queue %d\n", qnum
);
1831 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, AR_PHY_RFBUS_REQ_EN
);
1832 if (!ath9k_hw_wait(ah
, AR_PHY_RFBUS_GRANT
, AR_PHY_RFBUS_GRANT_EN
,
1833 AR_PHY_RFBUS_GRANT_EN
, AH_WAIT_TIMEOUT
)) {
1834 ath_print(common
, ATH_DBG_FATAL
,
1835 "Could not kill baseband RX\n");
1839 ath9k_hw_set_regs(ah
, chan
);
1841 r
= ah
->ath9k_hw_rf_set_freq(ah
, chan
);
1843 ath_print(common
, ATH_DBG_FATAL
,
1844 "Failed to set channel\n");
1848 ah
->eep_ops
->set_txpower(ah
, chan
,
1849 ath9k_regd_get_ctl(regulatory
, chan
),
1850 channel
->max_antenna_gain
* 2,
1851 channel
->max_power
* 2,
1852 min((u32
) MAX_RATE_POWER
,
1853 (u32
) regulatory
->power_limit
));
1855 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1856 if (IS_CHAN_B(chan
))
1857 synthDelay
= (4 * synthDelay
) / 22;
1861 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1863 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, 0);
1865 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1866 ath9k_hw_set_delta_slope(ah
, chan
);
1868 ah
->ath9k_hw_spur_mitigate_freq(ah
, chan
);
1870 if (!chan
->oneTimeCalsDone
)
1871 chan
->oneTimeCalsDone
= true;
1876 static void ath9k_enable_rfkill(struct ath_hw
*ah
)
1878 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
1879 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB
);
1881 REG_CLR_BIT(ah
, AR_GPIO_INPUT_MUX2
,
1882 AR_GPIO_INPUT_MUX2_RFSILENT
);
1884 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
1885 REG_SET_BIT(ah
, AR_PHY_TEST
, RFSILENT_BB
);
1888 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1889 bool bChannelChange
)
1891 struct ath_common
*common
= ath9k_hw_common(ah
);
1893 struct ath9k_channel
*curchan
= ah
->curchan
;
1897 int i
, rx_chainmask
, r
;
1899 ah
->txchainmask
= common
->tx_chainmask
;
1900 ah
->rxchainmask
= common
->rx_chainmask
;
1902 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1905 if (curchan
&& !ah
->chip_fullsleep
)
1906 ath9k_hw_getnf(ah
, curchan
);
1908 if (bChannelChange
&&
1909 (ah
->chip_fullsleep
!= true) &&
1910 (ah
->curchan
!= NULL
) &&
1911 (chan
->channel
!= ah
->curchan
->channel
) &&
1912 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1913 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
1914 !(AR_SREV_9280(ah
) || IS_CHAN_A_5MHZ_SPACED(chan
) ||
1915 IS_CHAN_A_5MHZ_SPACED(ah
->curchan
))) {
1917 if (ath9k_hw_channel_change(ah
, chan
)) {
1918 ath9k_hw_loadnf(ah
, ah
->curchan
);
1919 ath9k_hw_start_nfcal(ah
);
1924 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1925 if (saveDefAntenna
== 0)
1928 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1930 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1931 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1932 tsf
= ath9k_hw_gettsf64(ah
);
1934 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1935 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1936 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1938 ath9k_hw_mark_phy_inactive(ah
);
1940 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1942 AR9271_RESET_POWER_DOWN_CONTROL
,
1943 AR9271_RADIO_RF_RST
);
1947 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1948 ath_print(common
, ATH_DBG_FATAL
, "Chip reset failed\n");
1952 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1953 ah
->htc_reset_init
= false;
1955 AR9271_RESET_POWER_DOWN_CONTROL
,
1956 AR9271_GATE_MAC_CTL
);
1961 if (tsf
&& AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1962 ath9k_hw_settsf64(ah
, tsf
);
1964 if (AR_SREV_9280_10_OR_LATER(ah
))
1965 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1967 if (AR_SREV_9287_12_OR_LATER(ah
)) {
1968 /* Enable ASYNC FIFO */
1969 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
1970 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
);
1971 REG_SET_BIT(ah
, AR_PHY_MODE
, AR_PHY_MODE_ASYNCFIFO
);
1972 REG_CLR_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
1973 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
1974 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
1975 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
1977 r
= ath9k_hw_process_ini(ah
, chan
);
1981 /* Setup MFP options for CCMP */
1982 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1983 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1984 * frames when constructing CCMP AAD. */
1985 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1987 ah
->sw_mgmt_crypto
= false;
1988 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1989 /* Disable hardware crypto for management frames */
1990 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1991 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1992 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1993 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1994 ah
->sw_mgmt_crypto
= true;
1996 ah
->sw_mgmt_crypto
= true;
1998 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1999 ath9k_hw_set_delta_slope(ah
, chan
);
2001 ah
->ath9k_hw_spur_mitigate_freq(ah
, chan
);
2002 ah
->eep_ops
->set_board_values(ah
, chan
);
2004 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
2005 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
2007 | AR_STA_ID1_RTS_USE_DEF
2009 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
2010 | ah
->sta_id1_defaults
);
2011 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2013 ath_hw_setbssidmask(common
);
2015 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
2017 ath9k_hw_write_associd(ah
);
2019 REG_WRITE(ah
, AR_ISR
, ~0);
2021 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
2023 r
= ah
->ath9k_hw_rf_set_freq(ah
, chan
);
2027 for (i
= 0; i
< AR_NUM_DCU
; i
++)
2028 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
2031 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
2032 ath9k_hw_resettxqueue(ah
, i
);
2034 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
2035 ath9k_hw_init_qos(ah
);
2037 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2038 ath9k_enable_rfkill(ah
);
2040 ath9k_hw_init_global_settings(ah
);
2042 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2043 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
,
2044 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
);
2045 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
,
2046 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
);
2047 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
,
2048 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
);
2050 REG_WRITE(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
);
2051 REG_WRITE(ah
, AR_USEC
, AR_USEC_ASYNC_FIFO_DUR
);
2053 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
2054 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
2055 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
2056 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
2058 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2059 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2060 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
2063 REG_WRITE(ah
, AR_STA_ID1
,
2064 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
2066 ath9k_hw_set_dma(ah
);
2068 REG_WRITE(ah
, AR_OBS
, 8);
2070 if (ah
->config
.rx_intr_mitigation
) {
2071 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
2072 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
2075 ath9k_hw_init_bb(ah
, chan
);
2077 if (!ath9k_hw_init_cal(ah
, chan
))
2080 rx_chainmask
= ah
->rxchainmask
;
2081 if ((rx_chainmask
== 0x5) || (rx_chainmask
== 0x3)) {
2082 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
2083 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
2086 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
2089 * For big endian systems turn on swapping for descriptors
2091 if (AR_SREV_9100(ah
)) {
2093 mask
= REG_READ(ah
, AR_CFG
);
2094 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
2095 ath_print(common
, ATH_DBG_RESET
,
2096 "CFG Byte Swap Set 0x%x\n", mask
);
2099 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
2100 REG_WRITE(ah
, AR_CFG
, mask
);
2101 ath_print(common
, ATH_DBG_RESET
,
2102 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
2105 /* Configure AR9271 target WLAN */
2106 if (AR_SREV_9271(ah
))
2107 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
2110 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
2114 if (ah
->btcoex_hw
.enabled
)
2115 ath9k_hw_btcoex_enable(ah
);
2119 EXPORT_SYMBOL(ath9k_hw_reset
);
2121 /************************/
2122 /* Key Cache Management */
2123 /************************/
2125 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
2129 if (entry
>= ah
->caps
.keycache_size
) {
2130 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2131 "keychache entry %u out of range\n", entry
);
2135 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
2137 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
2138 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
2139 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
2140 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
2141 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
2142 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
2143 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
2144 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
2146 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2147 u16 micentry
= entry
+ 64;
2149 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
2150 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2151 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
2152 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2158 EXPORT_SYMBOL(ath9k_hw_keyreset
);
2160 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
2164 if (entry
>= ah
->caps
.keycache_size
) {
2165 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2166 "keychache entry %u out of range\n", entry
);
2171 macHi
= (mac
[5] << 8) | mac
[4];
2172 macLo
= (mac
[3] << 24) |
2177 macLo
|= (macHi
& 1) << 31;
2182 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
2183 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
2187 EXPORT_SYMBOL(ath9k_hw_keysetmac
);
2189 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
2190 const struct ath9k_keyval
*k
,
2193 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2194 struct ath_common
*common
= ath9k_hw_common(ah
);
2195 u32 key0
, key1
, key2
, key3
, key4
;
2198 if (entry
>= pCap
->keycache_size
) {
2199 ath_print(common
, ATH_DBG_FATAL
,
2200 "keycache entry %u out of range\n", entry
);
2204 switch (k
->kv_type
) {
2205 case ATH9K_CIPHER_AES_OCB
:
2206 keyType
= AR_KEYTABLE_TYPE_AES
;
2208 case ATH9K_CIPHER_AES_CCM
:
2209 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
2210 ath_print(common
, ATH_DBG_ANY
,
2211 "AES-CCM not supported by mac rev 0x%x\n",
2212 ah
->hw_version
.macRev
);
2215 keyType
= AR_KEYTABLE_TYPE_CCM
;
2217 case ATH9K_CIPHER_TKIP
:
2218 keyType
= AR_KEYTABLE_TYPE_TKIP
;
2219 if (ATH9K_IS_MIC_ENABLED(ah
)
2220 && entry
+ 64 >= pCap
->keycache_size
) {
2221 ath_print(common
, ATH_DBG_ANY
,
2222 "entry %u inappropriate for TKIP\n", entry
);
2226 case ATH9K_CIPHER_WEP
:
2227 if (k
->kv_len
< WLAN_KEY_LEN_WEP40
) {
2228 ath_print(common
, ATH_DBG_ANY
,
2229 "WEP key length %u too small\n", k
->kv_len
);
2232 if (k
->kv_len
<= WLAN_KEY_LEN_WEP40
)
2233 keyType
= AR_KEYTABLE_TYPE_40
;
2234 else if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2235 keyType
= AR_KEYTABLE_TYPE_104
;
2237 keyType
= AR_KEYTABLE_TYPE_128
;
2239 case ATH9K_CIPHER_CLR
:
2240 keyType
= AR_KEYTABLE_TYPE_CLR
;
2243 ath_print(common
, ATH_DBG_FATAL
,
2244 "cipher %u not supported\n", k
->kv_type
);
2248 key0
= get_unaligned_le32(k
->kv_val
+ 0);
2249 key1
= get_unaligned_le16(k
->kv_val
+ 4);
2250 key2
= get_unaligned_le32(k
->kv_val
+ 6);
2251 key3
= get_unaligned_le16(k
->kv_val
+ 10);
2252 key4
= get_unaligned_le32(k
->kv_val
+ 12);
2253 if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2257 * Note: Key cache registers access special memory area that requires
2258 * two 32-bit writes to actually update the values in the internal
2259 * memory. Consequently, the exact order and pairs used here must be
2263 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2264 u16 micentry
= entry
+ 64;
2267 * Write inverted key[47:0] first to avoid Michael MIC errors
2268 * on frames that could be sent or received at the same time.
2269 * The correct key will be written in the end once everything
2272 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
2273 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
2275 /* Write key[95:48] */
2276 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2277 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2279 /* Write key[127:96] and key type */
2280 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2281 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2283 /* Write MAC address for the entry */
2284 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2286 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
2288 * TKIP uses two key cache entries:
2289 * Michael MIC TX/RX keys in the same key cache entry
2290 * (idx = main index + 64):
2291 * key0 [31:0] = RX key [31:0]
2292 * key1 [15:0] = TX key [31:16]
2293 * key1 [31:16] = reserved
2294 * key2 [31:0] = RX key [63:32]
2295 * key3 [15:0] = TX key [15:0]
2296 * key3 [31:16] = reserved
2297 * key4 [31:0] = TX key [63:32]
2299 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
2301 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2302 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2303 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
2304 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
2305 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
2307 /* Write RX[31:0] and TX[31:16] */
2308 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2309 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
2311 /* Write RX[63:32] and TX[15:0] */
2312 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2313 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
2315 /* Write TX[63:32] and keyType(reserved) */
2316 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
2317 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2318 AR_KEYTABLE_TYPE_CLR
);
2322 * TKIP uses four key cache entries (two for group
2324 * Michael MIC TX/RX keys are in different key cache
2325 * entries (idx = main index + 64 for TX and
2326 * main index + 32 + 96 for RX):
2327 * key0 [31:0] = TX/RX MIC key [31:0]
2328 * key1 [31:0] = reserved
2329 * key2 [31:0] = TX/RX MIC key [63:32]
2330 * key3 [31:0] = reserved
2331 * key4 [31:0] = reserved
2333 * Upper layer code will call this function separately
2334 * for TX and RX keys when these registers offsets are
2339 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2340 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2342 /* Write MIC key[31:0] */
2343 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2344 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2346 /* Write MIC key[63:32] */
2347 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2348 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2350 /* Write TX[63:32] and keyType(reserved) */
2351 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
2352 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2353 AR_KEYTABLE_TYPE_CLR
);
2356 /* MAC address registers are reserved for the MIC entry */
2357 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
2358 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
2361 * Write the correct (un-inverted) key[47:0] last to enable
2362 * TKIP now that all other registers are set with correct
2365 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2366 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2368 /* Write key[47:0] */
2369 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2370 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2372 /* Write key[95:48] */
2373 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2374 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2376 /* Write key[127:96] and key type */
2377 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2378 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2380 /* Write MAC address for the entry */
2381 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2386 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry
);
2388 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
2390 if (entry
< ah
->caps
.keycache_size
) {
2391 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
2392 if (val
& AR_KEYTABLE_VALID
)
2397 EXPORT_SYMBOL(ath9k_hw_keyisvalid
);
2399 /******************************/
2400 /* Power Management (Chipset) */
2401 /******************************/
2403 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
2405 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2407 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2408 AR_RTC_FORCE_WAKE_EN
);
2409 if (!AR_SREV_9100(ah
))
2410 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
2412 if(!AR_SREV_5416(ah
))
2413 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
2418 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
2420 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2422 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2424 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2425 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2426 AR_RTC_FORCE_WAKE_ON_INT
);
2428 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2429 AR_RTC_FORCE_WAKE_EN
);
2434 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
2440 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2441 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2442 if (ath9k_hw_set_reset_reg(ah
,
2443 ATH9K_RESET_POWER_ON
) != true) {
2446 ath9k_hw_init_pll(ah
, NULL
);
2448 if (AR_SREV_9100(ah
))
2449 REG_SET_BIT(ah
, AR_RTC_RESET
,
2452 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2453 AR_RTC_FORCE_WAKE_EN
);
2456 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2457 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2458 if (val
== AR_RTC_STATUS_ON
)
2461 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2462 AR_RTC_FORCE_WAKE_EN
);
2465 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2466 "Failed to wakeup in %uus\n",
2467 POWER_UP_TIME
/ 20);
2472 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2477 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2479 struct ath_common
*common
= ath9k_hw_common(ah
);
2480 int status
= true, setChip
= true;
2481 static const char *modes
[] = {
2488 if (ah
->power_mode
== mode
)
2491 ath_print(common
, ATH_DBG_RESET
, "%s -> %s\n",
2492 modes
[ah
->power_mode
], modes
[mode
]);
2495 case ATH9K_PM_AWAKE
:
2496 status
= ath9k_hw_set_power_awake(ah
, setChip
);
2498 case ATH9K_PM_FULL_SLEEP
:
2499 ath9k_set_power_sleep(ah
, setChip
);
2500 ah
->chip_fullsleep
= true;
2502 case ATH9K_PM_NETWORK_SLEEP
:
2503 ath9k_set_power_network_sleep(ah
, setChip
);
2506 ath_print(common
, ATH_DBG_FATAL
,
2507 "Unknown power mode %u\n", mode
);
2510 ah
->power_mode
= mode
;
2514 EXPORT_SYMBOL(ath9k_hw_setpower
);
2517 * Helper for ASPM support.
2519 * Disable PLL when in L0s as well as receiver clock when in L1.
2520 * This power saving option must be enabled through the SerDes.
2522 * Programming the SerDes must go through the same 288 bit serial shift
2523 * register as the other analog registers. Hence the 9 writes.
2525 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
, int power_off
)
2530 if (ah
->is_pciexpress
!= true)
2533 /* Do not touch SerDes registers */
2534 if (ah
->config
.pcie_powersave_enable
== 2)
2537 /* Nothing to do on restore for 11N */
2539 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2541 * AR9280 2.0 or later chips use SerDes values from the
2542 * initvals.h initialized depending on chipset during
2545 for (i
= 0; i
< ah
->iniPcieSerdes
.ia_rows
; i
++) {
2546 REG_WRITE(ah
, INI_RA(&ah
->iniPcieSerdes
, i
, 0),
2547 INI_RA(&ah
->iniPcieSerdes
, i
, 1));
2549 } else if (AR_SREV_9280(ah
) &&
2550 (ah
->hw_version
.macRev
== AR_SREV_REVISION_9280_10
)) {
2551 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fd00);
2552 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2554 /* RX shut off when elecidle is asserted */
2555 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xa8000019);
2556 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x13160820);
2557 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980560);
2559 /* Shut off CLKREQ active in L1 */
2560 if (ah
->config
.pcie_clock_req
)
2561 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffc);
2563 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffd);
2565 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2566 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2567 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00043007);
2569 /* Load the new settings */
2570 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2573 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
2574 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2576 /* RX shut off when elecidle is asserted */
2577 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000039);
2578 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x53160824);
2579 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980579);
2582 * Ignore ah->ah_config.pcie_clock_req setting for
2585 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x001defff);
2587 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2588 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2589 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e3007);
2591 /* Load the new settings */
2592 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2597 /* set bit 19 to allow forcing of pcie core into L1 state */
2598 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PCIE_PM_CTRL_ENA
);
2600 /* Several PCIe massages to ensure proper behaviour */
2601 if (ah
->config
.pcie_waen
) {
2602 val
= ah
->config
.pcie_waen
;
2604 val
&= (~AR_WA_D3_L1_DISABLE
);
2606 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2608 val
= AR9285_WA_DEFAULT
;
2610 val
&= (~AR_WA_D3_L1_DISABLE
);
2611 } else if (AR_SREV_9280(ah
)) {
2613 * On AR9280 chips bit 22 of 0x4004 needs to be
2614 * set otherwise card may disappear.
2616 val
= AR9280_WA_DEFAULT
;
2618 val
&= (~AR_WA_D3_L1_DISABLE
);
2620 val
= AR_WA_DEFAULT
;
2623 REG_WRITE(ah
, AR_WA
, val
);
2628 * Set PCIe workaround bits
2629 * bit 14 in WA register (disable L1) should only
2630 * be set when device enters D3 and be cleared
2631 * when device comes back to D0.
2633 if (ah
->config
.pcie_waen
) {
2634 if (ah
->config
.pcie_waen
& AR_WA_D3_L1_DISABLE
)
2635 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2637 if (((AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2638 AR_SREV_9287(ah
)) &&
2639 (AR9285_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
)) ||
2640 (AR_SREV_9280(ah
) &&
2641 (AR9280_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
))) {
2642 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2647 EXPORT_SYMBOL(ath9k_hw_configpcipowersave
);
2649 /**********************/
2650 /* Interrupt Handling */
2651 /**********************/
2653 bool ath9k_hw_intrpend(struct ath_hw
*ah
)
2657 if (AR_SREV_9100(ah
))
2660 host_isr
= REG_READ(ah
, AR_INTR_ASYNC_CAUSE
);
2661 if ((host_isr
& AR_INTR_MAC_IRQ
) && (host_isr
!= AR_INTR_SPURIOUS
))
2664 host_isr
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
2665 if ((host_isr
& AR_INTR_SYNC_DEFAULT
)
2666 && (host_isr
!= AR_INTR_SPURIOUS
))
2671 EXPORT_SYMBOL(ath9k_hw_intrpend
);
2673 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
2677 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2679 bool fatal_int
= false;
2680 struct ath_common
*common
= ath9k_hw_common(ah
);
2682 if (!AR_SREV_9100(ah
)) {
2683 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
2684 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
2685 == AR_RTC_STATUS_ON
) {
2686 isr
= REG_READ(ah
, AR_ISR
);
2690 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) &
2691 AR_INTR_SYNC_DEFAULT
;
2695 if (!isr
&& !sync_cause
)
2699 isr
= REG_READ(ah
, AR_ISR
);
2703 if (isr
& AR_ISR_BCNMISC
) {
2705 isr2
= REG_READ(ah
, AR_ISR_S2
);
2706 if (isr2
& AR_ISR_S2_TIM
)
2707 mask2
|= ATH9K_INT_TIM
;
2708 if (isr2
& AR_ISR_S2_DTIM
)
2709 mask2
|= ATH9K_INT_DTIM
;
2710 if (isr2
& AR_ISR_S2_DTIMSYNC
)
2711 mask2
|= ATH9K_INT_DTIMSYNC
;
2712 if (isr2
& (AR_ISR_S2_CABEND
))
2713 mask2
|= ATH9K_INT_CABEND
;
2714 if (isr2
& AR_ISR_S2_GTT
)
2715 mask2
|= ATH9K_INT_GTT
;
2716 if (isr2
& AR_ISR_S2_CST
)
2717 mask2
|= ATH9K_INT_CST
;
2718 if (isr2
& AR_ISR_S2_TSFOOR
)
2719 mask2
|= ATH9K_INT_TSFOOR
;
2722 isr
= REG_READ(ah
, AR_ISR_RAC
);
2723 if (isr
== 0xffffffff) {
2728 *masked
= isr
& ATH9K_INT_COMMON
;
2730 if (ah
->config
.rx_intr_mitigation
) {
2731 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
2732 *masked
|= ATH9K_INT_RX
;
2735 if (isr
& (AR_ISR_RXOK
| AR_ISR_RXERR
))
2736 *masked
|= ATH9K_INT_RX
;
2738 (AR_ISR_TXOK
| AR_ISR_TXDESC
| AR_ISR_TXERR
|
2742 *masked
|= ATH9K_INT_TX
;
2744 s0_s
= REG_READ(ah
, AR_ISR_S0_S
);
2745 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXOK
);
2746 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXDESC
);
2748 s1_s
= REG_READ(ah
, AR_ISR_S1_S
);
2749 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXERR
);
2750 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXEOL
);
2753 if (isr
& AR_ISR_RXORN
) {
2754 ath_print(common
, ATH_DBG_INTERRUPT
,
2755 "receive FIFO overrun interrupt\n");
2758 if (!AR_SREV_9100(ah
)) {
2759 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2760 u32 isr5
= REG_READ(ah
, AR_ISR_S5_S
);
2761 if (isr5
& AR_ISR_S5_TIM_TIMER
)
2762 *masked
|= ATH9K_INT_TIM_TIMER
;
2769 if (AR_SREV_9100(ah
))
2772 if (isr
& AR_ISR_GENTMR
) {
2775 s5_s
= REG_READ(ah
, AR_ISR_S5_S
);
2776 if (isr
& AR_ISR_GENTMR
) {
2777 ah
->intr_gen_timer_trigger
=
2778 MS(s5_s
, AR_ISR_S5_GENTIMER_TRIG
);
2780 ah
->intr_gen_timer_thresh
=
2781 MS(s5_s
, AR_ISR_S5_GENTIMER_THRESH
);
2783 if (ah
->intr_gen_timer_trigger
)
2784 *masked
|= ATH9K_INT_GENTIMER
;
2792 (AR_INTR_SYNC_HOST1_FATAL
| AR_INTR_SYNC_HOST1_PERR
))
2796 if (sync_cause
& AR_INTR_SYNC_HOST1_FATAL
) {
2797 ath_print(common
, ATH_DBG_ANY
,
2798 "received PCI FATAL interrupt\n");
2800 if (sync_cause
& AR_INTR_SYNC_HOST1_PERR
) {
2801 ath_print(common
, ATH_DBG_ANY
,
2802 "received PCI PERR interrupt\n");
2804 *masked
|= ATH9K_INT_FATAL
;
2806 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
2807 ath_print(common
, ATH_DBG_INTERRUPT
,
2808 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2809 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
2810 REG_WRITE(ah
, AR_RC
, 0);
2811 *masked
|= ATH9K_INT_FATAL
;
2813 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
) {
2814 ath_print(common
, ATH_DBG_INTERRUPT
,
2815 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2818 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
2819 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
2824 EXPORT_SYMBOL(ath9k_hw_getisr
);
2826 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
)
2828 u32 omask
= ah
->mask_reg
;
2830 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2831 struct ath_common
*common
= ath9k_hw_common(ah
);
2833 ath_print(common
, ATH_DBG_INTERRUPT
, "0x%x => 0x%x\n", omask
, ints
);
2835 if (omask
& ATH9K_INT_GLOBAL
) {
2836 ath_print(common
, ATH_DBG_INTERRUPT
, "disable IER\n");
2837 REG_WRITE(ah
, AR_IER
, AR_IER_DISABLE
);
2838 (void) REG_READ(ah
, AR_IER
);
2839 if (!AR_SREV_9100(ah
)) {
2840 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
, 0);
2841 (void) REG_READ(ah
, AR_INTR_ASYNC_ENABLE
);
2843 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
2844 (void) REG_READ(ah
, AR_INTR_SYNC_ENABLE
);
2848 mask
= ints
& ATH9K_INT_COMMON
;
2851 if (ints
& ATH9K_INT_TX
) {
2852 if (ah
->txok_interrupt_mask
)
2853 mask
|= AR_IMR_TXOK
;
2854 if (ah
->txdesc_interrupt_mask
)
2855 mask
|= AR_IMR_TXDESC
;
2856 if (ah
->txerr_interrupt_mask
)
2857 mask
|= AR_IMR_TXERR
;
2858 if (ah
->txeol_interrupt_mask
)
2859 mask
|= AR_IMR_TXEOL
;
2861 if (ints
& ATH9K_INT_RX
) {
2862 mask
|= AR_IMR_RXERR
;
2863 if (ah
->config
.rx_intr_mitigation
)
2864 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
2866 mask
|= AR_IMR_RXOK
| AR_IMR_RXDESC
;
2867 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
2868 mask
|= AR_IMR_GENTMR
;
2871 if (ints
& (ATH9K_INT_BMISC
)) {
2872 mask
|= AR_IMR_BCNMISC
;
2873 if (ints
& ATH9K_INT_TIM
)
2874 mask2
|= AR_IMR_S2_TIM
;
2875 if (ints
& ATH9K_INT_DTIM
)
2876 mask2
|= AR_IMR_S2_DTIM
;
2877 if (ints
& ATH9K_INT_DTIMSYNC
)
2878 mask2
|= AR_IMR_S2_DTIMSYNC
;
2879 if (ints
& ATH9K_INT_CABEND
)
2880 mask2
|= AR_IMR_S2_CABEND
;
2881 if (ints
& ATH9K_INT_TSFOOR
)
2882 mask2
|= AR_IMR_S2_TSFOOR
;
2885 if (ints
& (ATH9K_INT_GTT
| ATH9K_INT_CST
)) {
2886 mask
|= AR_IMR_BCNMISC
;
2887 if (ints
& ATH9K_INT_GTT
)
2888 mask2
|= AR_IMR_S2_GTT
;
2889 if (ints
& ATH9K_INT_CST
)
2890 mask2
|= AR_IMR_S2_CST
;
2893 ath_print(common
, ATH_DBG_INTERRUPT
, "new IMR 0x%x\n", mask
);
2894 REG_WRITE(ah
, AR_IMR
, mask
);
2895 mask
= REG_READ(ah
, AR_IMR_S2
) & ~(AR_IMR_S2_TIM
|
2897 AR_IMR_S2_DTIMSYNC
|
2901 AR_IMR_S2_GTT
| AR_IMR_S2_CST
);
2902 REG_WRITE(ah
, AR_IMR_S2
, mask
| mask2
);
2903 ah
->mask_reg
= ints
;
2905 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2906 if (ints
& ATH9K_INT_TIM_TIMER
)
2907 REG_SET_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2909 REG_CLR_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2912 if (ints
& ATH9K_INT_GLOBAL
) {
2913 ath_print(common
, ATH_DBG_INTERRUPT
, "enable IER\n");
2914 REG_WRITE(ah
, AR_IER
, AR_IER_ENABLE
);
2915 if (!AR_SREV_9100(ah
)) {
2916 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
,
2918 REG_WRITE(ah
, AR_INTR_ASYNC_MASK
, AR_INTR_MAC_IRQ
);
2921 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
,
2922 AR_INTR_SYNC_DEFAULT
);
2923 REG_WRITE(ah
, AR_INTR_SYNC_MASK
,
2924 AR_INTR_SYNC_DEFAULT
);
2926 ath_print(common
, ATH_DBG_INTERRUPT
, "AR_IMR 0x%x IER 0x%x\n",
2927 REG_READ(ah
, AR_IMR
), REG_READ(ah
, AR_IER
));
2932 EXPORT_SYMBOL(ath9k_hw_set_interrupts
);
2934 /*******************/
2935 /* Beacon Handling */
2936 /*******************/
2938 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
2942 ah
->beacon_interval
= beacon_period
;
2944 switch (ah
->opmode
) {
2945 case NL80211_IFTYPE_STATION
:
2946 case NL80211_IFTYPE_MONITOR
:
2947 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
2948 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
2949 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
2950 flags
|= AR_TBTT_TIMER_EN
;
2952 case NL80211_IFTYPE_ADHOC
:
2953 case NL80211_IFTYPE_MESH_POINT
:
2954 REG_SET_BIT(ah
, AR_TXCFG
,
2955 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
2956 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
2957 TU_TO_USEC(next_beacon
+
2958 (ah
->atim_window
? ah
->
2960 flags
|= AR_NDP_TIMER_EN
;
2961 case NL80211_IFTYPE_AP
:
2962 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
2963 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
2964 TU_TO_USEC(next_beacon
-
2966 dma_beacon_response_time
));
2967 REG_WRITE(ah
, AR_NEXT_SWBA
,
2968 TU_TO_USEC(next_beacon
-
2970 sw_beacon_response_time
));
2972 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
2975 ath_print(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
2976 "%s: unsupported opmode: %d\n",
2977 __func__
, ah
->opmode
);
2982 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
2983 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
2984 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
2985 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
2987 beacon_period
&= ~ATH9K_BEACON_ENA
;
2988 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
2989 ath9k_hw_reset_tsf(ah
);
2992 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
2994 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
2996 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
2997 const struct ath9k_beacon_state
*bs
)
2999 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
3000 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3001 struct ath_common
*common
= ath9k_hw_common(ah
);
3003 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
3005 REG_WRITE(ah
, AR_BEACON_PERIOD
,
3006 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3007 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
3008 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3010 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
3011 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
3013 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
3015 if (bs
->bs_sleepduration
> beaconintval
)
3016 beaconintval
= bs
->bs_sleepduration
;
3018 dtimperiod
= bs
->bs_dtimperiod
;
3019 if (bs
->bs_sleepduration
> dtimperiod
)
3020 dtimperiod
= bs
->bs_sleepduration
;
3022 if (beaconintval
== dtimperiod
)
3023 nextTbtt
= bs
->bs_nextdtim
;
3025 nextTbtt
= bs
->bs_nexttbtt
;
3027 ath_print(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
3028 ath_print(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
3029 ath_print(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
3030 ath_print(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
3032 REG_WRITE(ah
, AR_NEXT_DTIM
,
3033 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
3034 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
3036 REG_WRITE(ah
, AR_SLEEP1
,
3037 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
3038 | AR_SLEEP1_ASSUME_DTIM
);
3040 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
3041 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
3043 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
3045 REG_WRITE(ah
, AR_SLEEP2
,
3046 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
3048 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
3049 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
3051 REG_SET_BIT(ah
, AR_TIMER_MODE
,
3052 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
3055 /* TSF Out of Range Threshold */
3056 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
3058 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
3060 /*******************/
3061 /* HW Capabilities */
3062 /*******************/
3064 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
3066 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3067 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3068 struct ath_common
*common
= ath9k_hw_common(ah
);
3069 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
3071 u16 capField
= 0, eeval
;
3073 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
3074 regulatory
->current_rd
= eeval
;
3076 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
3077 if (AR_SREV_9285_10_OR_LATER(ah
))
3078 eeval
|= AR9285_RDEXT_DEFAULT
;
3079 regulatory
->current_rd_ext
= eeval
;
3081 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
3083 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
3084 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
3085 if (regulatory
->current_rd
== 0x64 ||
3086 regulatory
->current_rd
== 0x65)
3087 regulatory
->current_rd
+= 5;
3088 else if (regulatory
->current_rd
== 0x41)
3089 regulatory
->current_rd
= 0x43;
3090 ath_print(common
, ATH_DBG_REGULATORY
,
3091 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
3094 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
3095 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
3096 ath_print(common
, ATH_DBG_FATAL
,
3097 "no band has been marked as supported in EEPROM.\n");
3101 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
3103 if (eeval
& AR5416_OPFLAGS_11A
) {
3104 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
3105 if (ah
->config
.ht_enable
) {
3106 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
3107 set_bit(ATH9K_MODE_11NA_HT20
,
3108 pCap
->wireless_modes
);
3109 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
3110 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
3111 pCap
->wireless_modes
);
3112 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
3113 pCap
->wireless_modes
);
3118 if (eeval
& AR5416_OPFLAGS_11G
) {
3119 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
3120 if (ah
->config
.ht_enable
) {
3121 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
3122 set_bit(ATH9K_MODE_11NG_HT20
,
3123 pCap
->wireless_modes
);
3124 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
3125 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
3126 pCap
->wireless_modes
);
3127 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
3128 pCap
->wireless_modes
);
3133 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
3135 * For AR9271 we will temporarilly uses the rx chainmax as read from
3138 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
3139 !(eeval
& AR5416_OPFLAGS_11A
) &&
3140 !(AR_SREV_9271(ah
)))
3141 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3142 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
3144 /* Use rx_chainmask from EEPROM. */
3145 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
3147 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
3148 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
3150 pCap
->low_2ghz_chan
= 2312;
3151 pCap
->high_2ghz_chan
= 2732;
3153 pCap
->low_5ghz_chan
= 4920;
3154 pCap
->high_5ghz_chan
= 6100;
3156 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
3157 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
3158 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
3160 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
3161 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
3162 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
3164 if (ah
->config
.ht_enable
)
3165 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
3167 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
3169 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
3170 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
3171 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
3172 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
3174 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
3175 pCap
->total_queues
=
3176 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
3178 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
3180 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
3181 pCap
->keycache_size
=
3182 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
3184 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
3186 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
3188 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
3189 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
>> 1;
3191 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
3193 if (AR_SREV_9285_10_OR_LATER(ah
))
3194 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
3195 else if (AR_SREV_9280_10_OR_LATER(ah
))
3196 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
3198 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
3200 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
3201 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
3202 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
3204 pCap
->rts_aggr_limit
= (8 * 1024);
3207 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
3209 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3210 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
3211 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
3213 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
3214 ah
->rfkill_polarity
=
3215 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
3217 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
3221 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
3223 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
3224 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
3226 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
3228 if (regulatory
->current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
3230 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3231 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
3232 AR_EEPROM_EEREGCAP_EN_KK_U2
|
3233 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
3236 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3237 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
3240 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3241 if (regulatory
->current_rd_ext
& (1 << REG_EXT_FCC_MIDBAND
) &&
3243 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
3245 pCap
->num_antcfg_5ghz
=
3246 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
3247 pCap
->num_antcfg_2ghz
=
3248 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
3250 if (AR_SREV_9280_10_OR_LATER(ah
) &&
3251 ath9k_hw_btcoex_supported(ah
)) {
3252 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO
;
3253 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO
;
3255 if (AR_SREV_9285(ah
)) {
3256 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
3257 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO
;
3259 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
3262 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
3268 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3269 u32 capability
, u32
*result
)
3271 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3273 case ATH9K_CAP_CIPHER
:
3274 switch (capability
) {
3275 case ATH9K_CIPHER_AES_CCM
:
3276 case ATH9K_CIPHER_AES_OCB
:
3277 case ATH9K_CIPHER_TKIP
:
3278 case ATH9K_CIPHER_WEP
:
3279 case ATH9K_CIPHER_MIC
:
3280 case ATH9K_CIPHER_CLR
:
3285 case ATH9K_CAP_TKIP_MIC
:
3286 switch (capability
) {
3290 return (ah
->sta_id1_defaults
&
3291 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
3294 case ATH9K_CAP_TKIP_SPLIT
:
3295 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
3297 case ATH9K_CAP_DIVERSITY
:
3298 return (REG_READ(ah
, AR_PHY_CCK_DETECT
) &
3299 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
) ?
3301 case ATH9K_CAP_MCAST_KEYSRCH
:
3302 switch (capability
) {
3306 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
3309 return (ah
->sta_id1_defaults
&
3310 AR_STA_ID1_MCAST_KSRCH
) ? true :
3315 case ATH9K_CAP_TXPOW
:
3316 switch (capability
) {
3320 *result
= regulatory
->power_limit
;
3323 *result
= regulatory
->max_power_level
;
3326 *result
= regulatory
->tp_scale
;
3331 return (AR_SREV_9280_20_OR_LATER(ah
) &&
3332 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
3338 EXPORT_SYMBOL(ath9k_hw_getcapability
);
3340 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3341 u32 capability
, u32 setting
, int *status
)
3346 case ATH9K_CAP_TKIP_MIC
:
3348 ah
->sta_id1_defaults
|=
3349 AR_STA_ID1_CRPT_MIC_ENABLE
;
3351 ah
->sta_id1_defaults
&=
3352 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
3354 case ATH9K_CAP_DIVERSITY
:
3355 v
= REG_READ(ah
, AR_PHY_CCK_DETECT
);
3357 v
|= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3359 v
&= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3360 REG_WRITE(ah
, AR_PHY_CCK_DETECT
, v
);
3362 case ATH9K_CAP_MCAST_KEYSRCH
:
3364 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
3366 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
3372 EXPORT_SYMBOL(ath9k_hw_setcapability
);
3374 /****************************/
3375 /* GPIO / RFKILL / Antennae */
3376 /****************************/
3378 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
3382 u32 gpio_shift
, tmp
;
3385 addr
= AR_GPIO_OUTPUT_MUX3
;
3387 addr
= AR_GPIO_OUTPUT_MUX2
;
3389 addr
= AR_GPIO_OUTPUT_MUX1
;
3391 gpio_shift
= (gpio
% 6) * 5;
3393 if (AR_SREV_9280_20_OR_LATER(ah
)
3394 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
3395 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
3396 (0x1f << gpio_shift
));
3398 tmp
= REG_READ(ah
, addr
);
3399 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
3400 tmp
&= ~(0x1f << gpio_shift
);
3401 tmp
|= (type
<< gpio_shift
);
3402 REG_WRITE(ah
, addr
, tmp
);
3406 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
3410 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
3412 gpio_shift
= gpio
<< 1;
3416 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
3417 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3419 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
3421 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
3423 #define MS_REG_READ(x, y) \
3424 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3426 if (gpio
>= ah
->caps
.num_gpio_pins
)
3429 if (AR_SREV_9287_10_OR_LATER(ah
))
3430 return MS_REG_READ(AR9287
, gpio
) != 0;
3431 else if (AR_SREV_9285_10_OR_LATER(ah
))
3432 return MS_REG_READ(AR9285
, gpio
) != 0;
3433 else if (AR_SREV_9280_10_OR_LATER(ah
))
3434 return MS_REG_READ(AR928X
, gpio
) != 0;
3436 return MS_REG_READ(AR
, gpio
) != 0;
3438 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
3440 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
3445 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
3447 gpio_shift
= 2 * gpio
;
3451 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
3452 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3454 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
3456 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
3458 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
3461 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
3463 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
3465 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
3467 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
3469 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
3471 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
3473 EXPORT_SYMBOL(ath9k_hw_setantenna
);
3475 /*********************/
3476 /* General Operation */
3477 /*********************/
3479 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
3481 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
3482 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
3484 if (phybits
& AR_PHY_ERR_RADAR
)
3485 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
3486 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
3487 bits
|= ATH9K_RX_FILTER_PHYERR
;
3491 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
3493 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
3497 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
3500 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
3501 phybits
|= AR_PHY_ERR_RADAR
;
3502 if (bits
& ATH9K_RX_FILTER_PHYERR
)
3503 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
3504 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
3507 REG_WRITE(ah
, AR_RXCFG
,
3508 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
3510 REG_WRITE(ah
, AR_RXCFG
,
3511 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
3513 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
3515 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
3517 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
3520 ath9k_hw_init_pll(ah
, NULL
);
3523 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
3525 bool ath9k_hw_disable(struct ath_hw
*ah
)
3527 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
3530 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
3533 ath9k_hw_init_pll(ah
, NULL
);
3536 EXPORT_SYMBOL(ath9k_hw_disable
);
3538 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
3540 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3541 struct ath9k_channel
*chan
= ah
->curchan
;
3542 struct ieee80211_channel
*channel
= chan
->chan
;
3544 regulatory
->power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
3546 ah
->eep_ops
->set_txpower(ah
, chan
,
3547 ath9k_regd_get_ctl(regulatory
, chan
),
3548 channel
->max_antenna_gain
* 2,
3549 channel
->max_power
* 2,
3550 min((u32
) MAX_RATE_POWER
,
3551 (u32
) regulatory
->power_limit
));
3553 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
3555 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
3557 memcpy(ath9k_hw_common(ah
)->macaddr
, mac
, ETH_ALEN
);
3559 EXPORT_SYMBOL(ath9k_hw_setmac
);
3561 void ath9k_hw_setopmode(struct ath_hw
*ah
)
3563 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
3565 EXPORT_SYMBOL(ath9k_hw_setopmode
);
3567 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
3569 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
3570 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
3572 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
3574 void ath9k_hw_write_associd(struct ath_hw
*ah
)
3576 struct ath_common
*common
= ath9k_hw_common(ah
);
3578 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
3579 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
3580 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
3582 EXPORT_SYMBOL(ath9k_hw_write_associd
);
3584 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
3588 tsf
= REG_READ(ah
, AR_TSF_U32
);
3589 tsf
= (tsf
<< 32) | REG_READ(ah
, AR_TSF_L32
);
3593 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
3595 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
3597 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
3598 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
3600 EXPORT_SYMBOL(ath9k_hw_settsf64
);
3602 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
3604 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
3605 AH_TSF_WRITE_TIMEOUT
))
3606 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
3607 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3609 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
3611 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
3613 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
3616 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
3618 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
3620 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
3623 * Extend 15-bit time stamp from rx descriptor to
3624 * a full 64-bit TSF using the current h/w TSF.
3626 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
)
3630 tsf
= ath9k_hw_gettsf64(ah
);
3631 if ((tsf
& 0x7fff) < rstamp
)
3633 return (tsf
& ~0x7fff) | rstamp
;
3635 EXPORT_SYMBOL(ath9k_hw_extend_tsf
);
3637 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
3639 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
3642 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
3643 macmode
= AR_2040_JOINED_RX_CLEAR
;
3647 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
3650 /* HW Generic timers configuration */
3652 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
3654 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3655 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3656 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3657 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3658 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3659 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3660 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3661 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3662 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
3663 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
3664 AR_NDP2_TIMER_MODE
, 0x0002},
3665 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
3666 AR_NDP2_TIMER_MODE
, 0x0004},
3667 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
3668 AR_NDP2_TIMER_MODE
, 0x0008},
3669 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
3670 AR_NDP2_TIMER_MODE
, 0x0010},
3671 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
3672 AR_NDP2_TIMER_MODE
, 0x0020},
3673 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
3674 AR_NDP2_TIMER_MODE
, 0x0040},
3675 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
3676 AR_NDP2_TIMER_MODE
, 0x0080}
3679 /* HW generic timer primitives */
3681 /* compute and clear index of rightmost 1 */
3682 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
3692 return timer_table
->gen_timer_index
[b
];
3695 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
3697 return REG_READ(ah
, AR_TSF_L32
);
3699 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
3701 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
3702 void (*trigger
)(void *),
3703 void (*overflow
)(void *),
3707 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3708 struct ath_gen_timer
*timer
;
3710 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
3712 if (timer
== NULL
) {
3713 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
3714 "Failed to allocate memory"
3715 "for hw timer[%d]\n", timer_index
);
3719 /* allocate a hardware generic timer slot */
3720 timer_table
->timers
[timer_index
] = timer
;
3721 timer
->index
= timer_index
;
3722 timer
->trigger
= trigger
;
3723 timer
->overflow
= overflow
;
3728 EXPORT_SYMBOL(ath_gen_timer_alloc
);
3730 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
3731 struct ath_gen_timer
*timer
,
3735 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3738 BUG_ON(!timer_period
);
3740 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3742 tsf
= ath9k_hw_gettsf32(ah
);
3744 ath_print(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
3745 "curent tsf %x period %x"
3746 "timer_next %x\n", tsf
, timer_period
, timer_next
);
3749 * Pull timer_next forward if the current TSF already passed it
3750 * because of software latency
3752 if (timer_next
< tsf
)
3753 timer_next
= tsf
+ timer_period
;
3756 * Program generic timer registers
3758 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
3760 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
3762 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3763 gen_tmr_configuration
[timer
->index
].mode_mask
);
3765 /* Enable both trigger and thresh interrupt masks */
3766 REG_SET_BIT(ah
, AR_IMR_S5
,
3767 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3768 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3770 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
3772 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3774 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3776 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
3777 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
3781 /* Clear generic timer enable bits. */
3782 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3783 gen_tmr_configuration
[timer
->index
].mode_mask
);
3785 /* Disable both trigger and thresh interrupt masks */
3786 REG_CLR_BIT(ah
, AR_IMR_S5
,
3787 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3788 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3790 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3792 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
3794 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3796 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3798 /* free the hardware generic timer slot */
3799 timer_table
->timers
[timer
->index
] = NULL
;
3802 EXPORT_SYMBOL(ath_gen_timer_free
);
3805 * Generic Timer Interrupts handling
3807 void ath_gen_timer_isr(struct ath_hw
*ah
)
3809 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3810 struct ath_gen_timer
*timer
;
3811 struct ath_common
*common
= ath9k_hw_common(ah
);
3812 u32 trigger_mask
, thresh_mask
, index
;
3814 /* get hardware generic timer interrupt status */
3815 trigger_mask
= ah
->intr_gen_timer_trigger
;
3816 thresh_mask
= ah
->intr_gen_timer_thresh
;
3817 trigger_mask
&= timer_table
->timer_mask
.val
;
3818 thresh_mask
&= timer_table
->timer_mask
.val
;
3820 trigger_mask
&= ~thresh_mask
;
3822 while (thresh_mask
) {
3823 index
= rightmost_index(timer_table
, &thresh_mask
);
3824 timer
= timer_table
->timers
[index
];
3826 ath_print(common
, ATH_DBG_HWTIMER
,
3827 "TSF overflow for Gen timer %d\n", index
);
3828 timer
->overflow(timer
->arg
);
3831 while (trigger_mask
) {
3832 index
= rightmost_index(timer_table
, &trigger_mask
);
3833 timer
= timer_table
->timers
[index
];
3835 ath_print(common
, ATH_DBG_HWTIMER
,
3836 "Gen timer[%d] trigger\n", index
);
3837 timer
->trigger(timer
->arg
);
3840 EXPORT_SYMBOL(ath_gen_timer_isr
);
3845 } ath_mac_bb_names
[] = {
3846 /* Devices with external radios */
3847 { AR_SREV_VERSION_5416_PCI
, "5416" },
3848 { AR_SREV_VERSION_5416_PCIE
, "5418" },
3849 { AR_SREV_VERSION_9100
, "9100" },
3850 { AR_SREV_VERSION_9160
, "9160" },
3851 /* Single-chip solutions */
3852 { AR_SREV_VERSION_9280
, "9280" },
3853 { AR_SREV_VERSION_9285
, "9285" },
3854 { AR_SREV_VERSION_9287
, "9287" },
3855 { AR_SREV_VERSION_9271
, "9271" },
3858 /* For devices with external radios */
3862 } ath_rf_names
[] = {
3864 { AR_RAD5133_SREV_MAJOR
, "5133" },
3865 { AR_RAD5122_SREV_MAJOR
, "5122" },
3866 { AR_RAD2133_SREV_MAJOR
, "2133" },
3867 { AR_RAD2122_SREV_MAJOR
, "2122" }
3871 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3873 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
3877 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
3878 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
3879 return ath_mac_bb_names
[i
].name
;
3887 * Return the RF name. "????" is returned if the RF is unknown.
3888 * Used for devices with external radios.
3890 static const char *ath9k_hw_rf_name(u16 rf_version
)
3894 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
3895 if (ath_rf_names
[i
].version
== rf_version
) {
3896 return ath_rf_names
[i
].name
;
3903 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
3907 /* chipsets >= AR9280 are single-chip */
3908 if (AR_SREV_9280_10_OR_LATER(ah
)) {
3909 used
= snprintf(hw_name
, len
,
3910 "Atheros AR%s Rev:%x",
3911 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3912 ah
->hw_version
.macRev
);
3915 used
= snprintf(hw_name
, len
,
3916 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3917 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3918 ah
->hw_version
.macRev
,
3919 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
3920 AR_RADIO_SREV_MAJOR
)),
3921 ah
->hw_version
.phyRev
);
3924 hw_name
[used
] = '\0';
3926 EXPORT_SYMBOL(ath9k_hw_name
);