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Merge git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41 return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47 return;
48 }
49 module_exit(ath9k_exit);
50
51 /********************/
52 /* Helper Functions */
53 /********************/
54
55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
56 {
57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
58
59 if (!ah->curchan) /* should really check for CCK instead */
60 return usecs *ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
63 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
64 }
65
66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
69
70 if (conf_is_ht40(conf))
71 return ath9k_hw_mac_clks(ah, usecs) * 2;
72 else
73 return ath9k_hw_mac_clks(ah, usecs);
74 }
75
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
77 {
78 int i;
79
80 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
88
89 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
92
93 return false;
94 }
95 EXPORT_SYMBOL(ath9k_hw_wait);
96
97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
98 {
99 u32 retval;
100 int i;
101
102 for (i = 0, retval = 0; i < n; i++) {
103 retval = (retval << 1) | (val & 1);
104 val >>= 1;
105 }
106 return retval;
107 }
108
109 bool ath9k_get_channel_edges(struct ath_hw *ah,
110 u16 flags, u16 *low,
111 u16 *high)
112 {
113 struct ath9k_hw_capabilities *pCap = &ah->caps;
114
115 if (flags & CHANNEL_5GHZ) {
116 *low = pCap->low_5ghz_chan;
117 *high = pCap->high_5ghz_chan;
118 return true;
119 }
120 if ((flags & CHANNEL_2GHZ)) {
121 *low = pCap->low_2ghz_chan;
122 *high = pCap->high_2ghz_chan;
123 return true;
124 }
125 return false;
126 }
127
128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
129 u8 phy, int kbps,
130 u32 frameLen, u16 rateix,
131 bool shortPreamble)
132 {
133 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
134
135 if (kbps == 0)
136 return 0;
137
138 switch (phy) {
139 case WLAN_RC_PHY_CCK:
140 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
141 if (shortPreamble)
142 phyTime >>= 1;
143 numBits = frameLen << 3;
144 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
145 break;
146 case WLAN_RC_PHY_OFDM:
147 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
148 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
149 numBits = OFDM_PLCP_BITS + (frameLen << 3);
150 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
151 txTime = OFDM_SIFS_TIME_QUARTER
152 + OFDM_PREAMBLE_TIME_QUARTER
153 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
154 } else if (ah->curchan &&
155 IS_CHAN_HALF_RATE(ah->curchan)) {
156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_HALF +
160 OFDM_PREAMBLE_TIME_HALF
161 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
162 } else {
163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
167 + (numSymbols * OFDM_SYMBOL_TIME);
168 }
169 break;
170 default:
171 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
172 "Unknown phy %u (rate ix %u)\n", phy, rateix);
173 txTime = 0;
174 break;
175 }
176
177 return txTime;
178 }
179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
180
181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
182 struct ath9k_channel *chan,
183 struct chan_centers *centers)
184 {
185 int8_t extoff;
186
187 if (!IS_CHAN_HT40(chan)) {
188 centers->ctl_center = centers->ext_center =
189 centers->synth_center = chan->channel;
190 return;
191 }
192
193 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
194 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
195 centers->synth_center =
196 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
197 extoff = 1;
198 } else {
199 centers->synth_center =
200 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
201 extoff = -1;
202 }
203
204 centers->ctl_center =
205 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
206 /* 25 MHz spacing is supported by hw but not on upper layers */
207 centers->ext_center =
208 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
209 }
210
211 /******************/
212 /* Chip Revisions */
213 /******************/
214
215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
216 {
217 u32 val;
218
219 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
220
221 if (val == 0xFF) {
222 val = REG_READ(ah, AR_SREV);
223 ah->hw_version.macVersion =
224 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
225 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
226 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
227 } else {
228 if (!AR_SREV_9100(ah))
229 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
230
231 ah->hw_version.macRev = val & AR_SREV_REVISION;
232
233 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
234 ah->is_pciexpress = true;
235 }
236 }
237
238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
239 {
240 u32 val;
241 int i;
242
243 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
244
245 for (i = 0; i < 8; i++)
246 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
247 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
248 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
249
250 return ath9k_hw_reverse_bits(val, 8);
251 }
252
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
256
257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
258 {
259 if (AR_SREV_9100(ah))
260 return;
261
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
263 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
264 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
265 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
266 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
267 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
269 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
270 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
271
272 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
273 }
274
275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
276 {
277 struct ath_common *common = ath9k_hw_common(ah);
278 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
279 u32 regHold[2];
280 u32 patternData[4] = { 0x55555555,
281 0xaaaaaaaa,
282 0x66666666,
283 0x99999999 };
284 int i, j;
285
286 for (i = 0; i < 2; i++) {
287 u32 addr = regAddr[i];
288 u32 wrData, rdData;
289
290 regHold[i] = REG_READ(ah, addr);
291 for (j = 0; j < 0x100; j++) {
292 wrData = (j << 16) | j;
293 REG_WRITE(ah, addr, wrData);
294 rdData = REG_READ(ah, addr);
295 if (rdData != wrData) {
296 ath_print(common, ATH_DBG_FATAL,
297 "address test failed "
298 "addr: 0x%08x - wr:0x%08x != "
299 "rd:0x%08x\n",
300 addr, wrData, rdData);
301 return false;
302 }
303 }
304 for (j = 0; j < 4; j++) {
305 wrData = patternData[j];
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (wrData != rdData) {
309 ath_print(common, ATH_DBG_FATAL,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != "
312 "rd:0x%08x\n",
313 addr, wrData, rdData);
314 return false;
315 }
316 }
317 REG_WRITE(ah, regAddr[i], regHold[i]);
318 }
319 udelay(100);
320
321 return true;
322 }
323
324 static void ath9k_hw_init_config(struct ath_hw *ah)
325 {
326 int i;
327
328 ah->config.dma_beacon_response_time = 2;
329 ah->config.sw_beacon_response_time = 10;
330 ah->config.additional_swba_backoff = 0;
331 ah->config.ack_6mb = 0x0;
332 ah->config.cwm_ignore_extcca = 0;
333 ah->config.pcie_powersave_enable = 0;
334 ah->config.pcie_clock_req = 0;
335 ah->config.pcie_waen = 0;
336 ah->config.analog_shiftreg = 1;
337 ah->config.ht_enable = 1;
338 ah->config.ofdm_trig_low = 200;
339 ah->config.ofdm_trig_high = 500;
340 ah->config.cck_trig_high = 200;
341 ah->config.cck_trig_low = 100;
342 ah->config.enable_ani = 1;
343
344 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
345 ah->config.spurchans[i][0] = AR_NO_SPUR;
346 ah->config.spurchans[i][1] = AR_NO_SPUR;
347 }
348
349 ah->config.rx_intr_mitigation = true;
350
351 /*
352 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
353 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
354 * This means we use it for all AR5416 devices, and the few
355 * minor PCI AR9280 devices out there.
356 *
357 * Serialization is required because these devices do not handle
358 * well the case of two concurrent reads/writes due to the latency
359 * involved. During one read/write another read/write can be issued
360 * on another CPU while the previous read/write may still be working
361 * on our hardware, if we hit this case the hardware poops in a loop.
362 * We prevent this by serializing reads and writes.
363 *
364 * This issue is not present on PCI-Express devices or pre-AR5416
365 * devices (legacy, 802.11abg).
366 */
367 if (num_possible_cpus() > 1)
368 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
369 }
370 EXPORT_SYMBOL(ath9k_hw_init);
371
372 static void ath9k_hw_init_defaults(struct ath_hw *ah)
373 {
374 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
375
376 regulatory->country_code = CTRY_DEFAULT;
377 regulatory->power_limit = MAX_RATE_POWER;
378 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
379
380 ah->hw_version.magic = AR5416_MAGIC;
381 ah->hw_version.subvendorid = 0;
382
383 ah->ah_flags = 0;
384 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
385 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
386 if (!AR_SREV_9100(ah))
387 ah->ah_flags = AH_USE_EEPROM;
388
389 ah->atim_window = 0;
390 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
391 ah->beacon_interval = 100;
392 ah->enable_32kHz_clock = DONT_USE_32KHZ;
393 ah->slottime = (u32) -1;
394 ah->globaltxtimeout = (u32) -1;
395 ah->power_mode = ATH9K_PM_UNDEFINED;
396 }
397
398 static int ath9k_hw_rf_claim(struct ath_hw *ah)
399 {
400 u32 val;
401
402 REG_WRITE(ah, AR_PHY(0), 0x00000007);
403
404 val = ath9k_hw_get_radiorev(ah);
405 switch (val & AR_RADIO_SREV_MAJOR) {
406 case 0:
407 val = AR_RAD5133_SREV_MAJOR;
408 break;
409 case AR_RAD5133_SREV_MAJOR:
410 case AR_RAD5122_SREV_MAJOR:
411 case AR_RAD2133_SREV_MAJOR:
412 case AR_RAD2122_SREV_MAJOR:
413 break;
414 default:
415 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
416 "Radio Chip Rev 0x%02X not supported\n",
417 val & AR_RADIO_SREV_MAJOR);
418 return -EOPNOTSUPP;
419 }
420
421 ah->hw_version.analog5GhzRev = val;
422
423 return 0;
424 }
425
426 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
427 {
428 struct ath_common *common = ath9k_hw_common(ah);
429 u32 sum;
430 int i;
431 u16 eeval;
432
433 sum = 0;
434 for (i = 0; i < 3; i++) {
435 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
436 sum += eeval;
437 common->macaddr[2 * i] = eeval >> 8;
438 common->macaddr[2 * i + 1] = eeval & 0xff;
439 }
440 if (sum == 0 || sum == 0xffff * 3)
441 return -EADDRNOTAVAIL;
442
443 return 0;
444 }
445
446 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
447 {
448 u32 rxgain_type;
449
450 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
451 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
452
453 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
454 INIT_INI_ARRAY(&ah->iniModesRxGain,
455 ar9280Modes_backoff_13db_rxgain_9280_2,
456 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
457 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
458 INIT_INI_ARRAY(&ah->iniModesRxGain,
459 ar9280Modes_backoff_23db_rxgain_9280_2,
460 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
461 else
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9280Modes_original_rxgain_9280_2,
464 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
465 } else {
466 INIT_INI_ARRAY(&ah->iniModesRxGain,
467 ar9280Modes_original_rxgain_9280_2,
468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
469 }
470 }
471
472 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
473 {
474 u32 txgain_type;
475
476 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
477 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
478
479 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
480 INIT_INI_ARRAY(&ah->iniModesTxGain,
481 ar9280Modes_high_power_tx_gain_9280_2,
482 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
483 else
484 INIT_INI_ARRAY(&ah->iniModesTxGain,
485 ar9280Modes_original_tx_gain_9280_2,
486 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
487 } else {
488 INIT_INI_ARRAY(&ah->iniModesTxGain,
489 ar9280Modes_original_tx_gain_9280_2,
490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
491 }
492 }
493
494 static int ath9k_hw_post_init(struct ath_hw *ah)
495 {
496 int ecode;
497
498 if (!ath9k_hw_chip_test(ah))
499 return -ENODEV;
500
501 ecode = ath9k_hw_rf_claim(ah);
502 if (ecode != 0)
503 return ecode;
504
505 ecode = ath9k_hw_eeprom_init(ah);
506 if (ecode != 0)
507 return ecode;
508
509 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
510 "Eeprom VER: %d, REV: %d\n",
511 ah->eep_ops->get_eeprom_ver(ah),
512 ah->eep_ops->get_eeprom_rev(ah));
513
514 if (!AR_SREV_9280_10_OR_LATER(ah)) {
515 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
516 if (ecode) {
517 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
518 "Failed allocating banks for "
519 "external radio\n");
520 return ecode;
521 }
522 }
523
524 if (!AR_SREV_9100(ah)) {
525 ath9k_hw_ani_setup(ah);
526 ath9k_hw_ani_init(ah);
527 }
528
529 return 0;
530 }
531
532 static bool ath9k_hw_devid_supported(u16 devid)
533 {
534 switch (devid) {
535 case AR5416_DEVID_PCI:
536 case AR5416_DEVID_PCIE:
537 case AR5416_AR9100_DEVID:
538 case AR9160_DEVID_PCI:
539 case AR9280_DEVID_PCI:
540 case AR9280_DEVID_PCIE:
541 case AR9285_DEVID_PCIE:
542 case AR5416_DEVID_AR9287_PCI:
543 case AR5416_DEVID_AR9287_PCIE:
544 case AR9271_USB:
545 return true;
546 default:
547 break;
548 }
549 return false;
550 }
551
552 static bool ath9k_hw_macversion_supported(u32 macversion)
553 {
554 switch (macversion) {
555 case AR_SREV_VERSION_5416_PCI:
556 case AR_SREV_VERSION_5416_PCIE:
557 case AR_SREV_VERSION_9160:
558 case AR_SREV_VERSION_9100:
559 case AR_SREV_VERSION_9280:
560 case AR_SREV_VERSION_9285:
561 case AR_SREV_VERSION_9287:
562 case AR_SREV_VERSION_9271:
563 return true;
564 default:
565 break;
566 }
567 return false;
568 }
569
570 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
571 {
572 if (AR_SREV_9160_10_OR_LATER(ah)) {
573 if (AR_SREV_9280_10_OR_LATER(ah)) {
574 ah->iq_caldata.calData = &iq_cal_single_sample;
575 ah->adcgain_caldata.calData =
576 &adc_gain_cal_single_sample;
577 ah->adcdc_caldata.calData =
578 &adc_dc_cal_single_sample;
579 ah->adcdc_calinitdata.calData =
580 &adc_init_dc_cal;
581 } else {
582 ah->iq_caldata.calData = &iq_cal_multi_sample;
583 ah->adcgain_caldata.calData =
584 &adc_gain_cal_multi_sample;
585 ah->adcdc_caldata.calData =
586 &adc_dc_cal_multi_sample;
587 ah->adcdc_calinitdata.calData =
588 &adc_init_dc_cal;
589 }
590 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
591 }
592 }
593
594 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
595 {
596 if (AR_SREV_9271(ah)) {
597 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
598 ARRAY_SIZE(ar9271Modes_9271), 6);
599 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
600 ARRAY_SIZE(ar9271Common_9271), 2);
601 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
602 ar9271Modes_9271_1_0_only,
603 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
604 return;
605 }
606
607 if (AR_SREV_9287_11_OR_LATER(ah)) {
608 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
609 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
610 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
611 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
612 if (ah->config.pcie_clock_req)
613 INIT_INI_ARRAY(&ah->iniPcieSerdes,
614 ar9287PciePhy_clkreq_off_L1_9287_1_1,
615 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
616 else
617 INIT_INI_ARRAY(&ah->iniPcieSerdes,
618 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
619 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
620 2);
621 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
622 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
623 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
624 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
625 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
626
627 if (ah->config.pcie_clock_req)
628 INIT_INI_ARRAY(&ah->iniPcieSerdes,
629 ar9287PciePhy_clkreq_off_L1_9287_1_0,
630 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
631 else
632 INIT_INI_ARRAY(&ah->iniPcieSerdes,
633 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
634 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
635 2);
636 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
637
638
639 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
640 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
641 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
642 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
643
644 if (ah->config.pcie_clock_req) {
645 INIT_INI_ARRAY(&ah->iniPcieSerdes,
646 ar9285PciePhy_clkreq_off_L1_9285_1_2,
647 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
648 } else {
649 INIT_INI_ARRAY(&ah->iniPcieSerdes,
650 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
651 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
652 2);
653 }
654 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
655 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
656 ARRAY_SIZE(ar9285Modes_9285), 6);
657 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
658 ARRAY_SIZE(ar9285Common_9285), 2);
659
660 if (ah->config.pcie_clock_req) {
661 INIT_INI_ARRAY(&ah->iniPcieSerdes,
662 ar9285PciePhy_clkreq_off_L1_9285,
663 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
664 } else {
665 INIT_INI_ARRAY(&ah->iniPcieSerdes,
666 ar9285PciePhy_clkreq_always_on_L1_9285,
667 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
668 }
669 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
670 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
671 ARRAY_SIZE(ar9280Modes_9280_2), 6);
672 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
673 ARRAY_SIZE(ar9280Common_9280_2), 2);
674
675 if (ah->config.pcie_clock_req) {
676 INIT_INI_ARRAY(&ah->iniPcieSerdes,
677 ar9280PciePhy_clkreq_off_L1_9280,
678 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
679 } else {
680 INIT_INI_ARRAY(&ah->iniPcieSerdes,
681 ar9280PciePhy_clkreq_always_on_L1_9280,
682 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
683 }
684 INIT_INI_ARRAY(&ah->iniModesAdditional,
685 ar9280Modes_fast_clock_9280_2,
686 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
687 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
688 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
689 ARRAY_SIZE(ar9280Modes_9280), 6);
690 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
691 ARRAY_SIZE(ar9280Common_9280), 2);
692 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
693 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
694 ARRAY_SIZE(ar5416Modes_9160), 6);
695 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
696 ARRAY_SIZE(ar5416Common_9160), 2);
697 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
698 ARRAY_SIZE(ar5416Bank0_9160), 2);
699 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
700 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
701 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
702 ARRAY_SIZE(ar5416Bank1_9160), 2);
703 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
704 ARRAY_SIZE(ar5416Bank2_9160), 2);
705 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
706 ARRAY_SIZE(ar5416Bank3_9160), 3);
707 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
708 ARRAY_SIZE(ar5416Bank6_9160), 3);
709 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
710 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
711 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
712 ARRAY_SIZE(ar5416Bank7_9160), 2);
713 if (AR_SREV_9160_11(ah)) {
714 INIT_INI_ARRAY(&ah->iniAddac,
715 ar5416Addac_91601_1,
716 ARRAY_SIZE(ar5416Addac_91601_1), 2);
717 } else {
718 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
719 ARRAY_SIZE(ar5416Addac_9160), 2);
720 }
721 } else if (AR_SREV_9100_OR_LATER(ah)) {
722 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
723 ARRAY_SIZE(ar5416Modes_9100), 6);
724 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
725 ARRAY_SIZE(ar5416Common_9100), 2);
726 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
727 ARRAY_SIZE(ar5416Bank0_9100), 2);
728 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
729 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
730 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
731 ARRAY_SIZE(ar5416Bank1_9100), 2);
732 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
733 ARRAY_SIZE(ar5416Bank2_9100), 2);
734 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
735 ARRAY_SIZE(ar5416Bank3_9100), 3);
736 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
737 ARRAY_SIZE(ar5416Bank6_9100), 3);
738 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
739 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
740 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
741 ARRAY_SIZE(ar5416Bank7_9100), 2);
742 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
743 ARRAY_SIZE(ar5416Addac_9100), 2);
744 } else {
745 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
746 ARRAY_SIZE(ar5416Modes), 6);
747 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
748 ARRAY_SIZE(ar5416Common), 2);
749 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
750 ARRAY_SIZE(ar5416Bank0), 2);
751 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
752 ARRAY_SIZE(ar5416BB_RfGain), 3);
753 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
754 ARRAY_SIZE(ar5416Bank1), 2);
755 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
756 ARRAY_SIZE(ar5416Bank2), 2);
757 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
758 ARRAY_SIZE(ar5416Bank3), 3);
759 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
760 ARRAY_SIZE(ar5416Bank6), 3);
761 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
762 ARRAY_SIZE(ar5416Bank6TPC), 3);
763 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
764 ARRAY_SIZE(ar5416Bank7), 2);
765 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
766 ARRAY_SIZE(ar5416Addac), 2);
767 }
768 }
769
770 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
771 {
772 if (AR_SREV_9287_11_OR_LATER(ah))
773 INIT_INI_ARRAY(&ah->iniModesRxGain,
774 ar9287Modes_rx_gain_9287_1_1,
775 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
776 else if (AR_SREV_9287_10(ah))
777 INIT_INI_ARRAY(&ah->iniModesRxGain,
778 ar9287Modes_rx_gain_9287_1_0,
779 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
780 else if (AR_SREV_9280_20(ah))
781 ath9k_hw_init_rxgain_ini(ah);
782
783 if (AR_SREV_9287_11_OR_LATER(ah)) {
784 INIT_INI_ARRAY(&ah->iniModesTxGain,
785 ar9287Modes_tx_gain_9287_1_1,
786 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
787 } else if (AR_SREV_9287_10(ah)) {
788 INIT_INI_ARRAY(&ah->iniModesTxGain,
789 ar9287Modes_tx_gain_9287_1_0,
790 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
791 } else if (AR_SREV_9280_20(ah)) {
792 ath9k_hw_init_txgain_ini(ah);
793 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
794 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
795
796 /* txgain table */
797 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
798 INIT_INI_ARRAY(&ah->iniModesTxGain,
799 ar9285Modes_high_power_tx_gain_9285_1_2,
800 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
801 } else {
802 INIT_INI_ARRAY(&ah->iniModesTxGain,
803 ar9285Modes_original_tx_gain_9285_1_2,
804 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
805 }
806
807 }
808 }
809
810 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
811 {
812 u32 i, j;
813
814 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
815 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
816
817 /* EEPROM Fixup */
818 for (i = 0; i < ah->iniModes.ia_rows; i++) {
819 u32 reg = INI_RA(&ah->iniModes, i, 0);
820
821 for (j = 1; j < ah->iniModes.ia_columns; j++) {
822 u32 val = INI_RA(&ah->iniModes, i, j);
823
824 INI_RA(&ah->iniModes, i, j) =
825 ath9k_hw_ini_fixup(ah,
826 &ah->eeprom.def,
827 reg, val);
828 }
829 }
830 }
831 }
832
833 int ath9k_hw_init(struct ath_hw *ah)
834 {
835 struct ath_common *common = ath9k_hw_common(ah);
836 int r = 0;
837
838 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
839 ath_print(common, ATH_DBG_FATAL,
840 "Unsupported device ID: 0x%0x\n",
841 ah->hw_version.devid);
842 return -EOPNOTSUPP;
843 }
844
845 ath9k_hw_init_defaults(ah);
846 ath9k_hw_init_config(ah);
847
848 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
849 ath_print(common, ATH_DBG_FATAL,
850 "Couldn't reset chip\n");
851 return -EIO;
852 }
853
854 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
855 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
856 return -EIO;
857 }
858
859 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
860 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
861 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
862 ah->config.serialize_regmode =
863 SER_REG_MODE_ON;
864 } else {
865 ah->config.serialize_regmode =
866 SER_REG_MODE_OFF;
867 }
868 }
869
870 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
871 ah->config.serialize_regmode);
872
873 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
874 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
875 else
876 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
877
878 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
879 ath_print(common, ATH_DBG_FATAL,
880 "Mac Chip Rev 0x%02x.%x is not supported by "
881 "this driver\n", ah->hw_version.macVersion,
882 ah->hw_version.macRev);
883 return -EOPNOTSUPP;
884 }
885
886 if (AR_SREV_9100(ah)) {
887 ah->iq_caldata.calData = &iq_cal_multi_sample;
888 ah->supp_cals = IQ_MISMATCH_CAL;
889 ah->is_pciexpress = false;
890 }
891
892 if (AR_SREV_9271(ah))
893 ah->is_pciexpress = false;
894
895 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
896
897 ath9k_hw_init_cal_settings(ah);
898
899 ah->ani_function = ATH9K_ANI_ALL;
900 if (AR_SREV_9280_10_OR_LATER(ah)) {
901 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
902 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
903 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
904 } else {
905 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
906 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
907 }
908
909 ath9k_hw_init_mode_regs(ah);
910
911 if (ah->is_pciexpress)
912 ath9k_hw_configpcipowersave(ah, 0, 0);
913 else
914 ath9k_hw_disablepcie(ah);
915
916 /* Support for Japan ch.14 (2484) spread */
917 if (AR_SREV_9287_11_OR_LATER(ah)) {
918 INIT_INI_ARRAY(&ah->iniCckfirNormal,
919 ar9287Common_normal_cck_fir_coeff_92871_1,
920 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
921 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
922 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
923 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
924 }
925
926 r = ath9k_hw_post_init(ah);
927 if (r)
928 return r;
929
930 ath9k_hw_init_mode_gain_regs(ah);
931 r = ath9k_hw_fill_cap_info(ah);
932 if (r)
933 return r;
934
935 ath9k_hw_init_11a_eeprom_fix(ah);
936
937 r = ath9k_hw_init_macaddr(ah);
938 if (r) {
939 ath_print(common, ATH_DBG_FATAL,
940 "Failed to initialize MAC address\n");
941 return r;
942 }
943
944 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
945 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
946 else
947 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
948
949 ath9k_init_nfcal_hist_buffer(ah);
950
951 common->state = ATH_HW_INITIALIZED;
952
953 return 0;
954 }
955
956 static void ath9k_hw_init_bb(struct ath_hw *ah,
957 struct ath9k_channel *chan)
958 {
959 u32 synthDelay;
960
961 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
962 if (IS_CHAN_B(chan))
963 synthDelay = (4 * synthDelay) / 22;
964 else
965 synthDelay /= 10;
966
967 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
968
969 udelay(synthDelay + BASE_ACTIVATE_DELAY);
970 }
971
972 static void ath9k_hw_init_qos(struct ath_hw *ah)
973 {
974 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
975 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
976
977 REG_WRITE(ah, AR_QOS_NO_ACK,
978 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
979 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
980 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
981
982 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
983 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
984 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
985 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
986 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
987 }
988
989 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
990 {
991 u32 lcr;
992 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
993
994 lcr = REG_READ(ah , 0x5100c);
995 lcr |= 0x80;
996
997 REG_WRITE(ah, 0x5100c, lcr);
998 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
999 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1000
1001 lcr &= ~0x80;
1002 REG_WRITE(ah, 0x5100c, lcr);
1003 }
1004
1005 static void ath9k_hw_init_pll(struct ath_hw *ah,
1006 struct ath9k_channel *chan)
1007 {
1008 u32 pll;
1009
1010 if (AR_SREV_9100(ah)) {
1011 if (chan && IS_CHAN_5GHZ(chan))
1012 pll = 0x1450;
1013 else
1014 pll = 0x1458;
1015 } else {
1016 if (AR_SREV_9280_10_OR_LATER(ah)) {
1017 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1018
1019 if (chan && IS_CHAN_HALF_RATE(chan))
1020 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1021 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1022 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1023
1024 if (chan && IS_CHAN_5GHZ(chan)) {
1025 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1026
1027
1028 if (AR_SREV_9280_20(ah)) {
1029 if (((chan->channel % 20) == 0)
1030 || ((chan->channel % 10) == 0))
1031 pll = 0x2850;
1032 else
1033 pll = 0x142c;
1034 }
1035 } else {
1036 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1037 }
1038
1039 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1040
1041 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1042
1043 if (chan && IS_CHAN_HALF_RATE(chan))
1044 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1045 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1046 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1047
1048 if (chan && IS_CHAN_5GHZ(chan))
1049 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1050 else
1051 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1052 } else {
1053 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1054
1055 if (chan && IS_CHAN_HALF_RATE(chan))
1056 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1057 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1058 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1059
1060 if (chan && IS_CHAN_5GHZ(chan))
1061 pll |= SM(0xa, AR_RTC_PLL_DIV);
1062 else
1063 pll |= SM(0xb, AR_RTC_PLL_DIV);
1064 }
1065 }
1066 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1067
1068 /* Switch the core clock for ar9271 to 117Mhz */
1069 if (AR_SREV_9271(ah)) {
1070 if ((pll == 0x142c) || (pll == 0x2850) ) {
1071 udelay(500);
1072 /* set CLKOBS to output AHB clock */
1073 REG_WRITE(ah, 0x7020, 0xe);
1074 /*
1075 * 0x304: 117Mhz, ahb_ratio: 1x1
1076 * 0x306: 40Mhz, ahb_ratio: 1x1
1077 */
1078 REG_WRITE(ah, 0x50040, 0x304);
1079 /*
1080 * makes adjustments for the baud dividor to keep the
1081 * targetted baud rate based on the used core clock.
1082 */
1083 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1084 AR9271_TARGET_BAUD_RATE);
1085 }
1086 }
1087
1088 udelay(RTC_PLL_SETTLE_DELAY);
1089
1090 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1091 }
1092
1093 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1094 {
1095 int rx_chainmask, tx_chainmask;
1096
1097 rx_chainmask = ah->rxchainmask;
1098 tx_chainmask = ah->txchainmask;
1099
1100 switch (rx_chainmask) {
1101 case 0x5:
1102 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1103 AR_PHY_SWAP_ALT_CHAIN);
1104 case 0x3:
1105 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1106 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1107 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1108 break;
1109 }
1110 case 0x1:
1111 case 0x2:
1112 case 0x7:
1113 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1114 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1115 break;
1116 default:
1117 break;
1118 }
1119
1120 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1121 if (tx_chainmask == 0x5) {
1122 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1123 AR_PHY_SWAP_ALT_CHAIN);
1124 }
1125 if (AR_SREV_9100(ah))
1126 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1127 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1128 }
1129
1130 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1131 enum nl80211_iftype opmode)
1132 {
1133 ah->mask_reg = AR_IMR_TXERR |
1134 AR_IMR_TXURN |
1135 AR_IMR_RXERR |
1136 AR_IMR_RXORN |
1137 AR_IMR_BCNMISC;
1138
1139 if (ah->config.rx_intr_mitigation)
1140 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1141 else
1142 ah->mask_reg |= AR_IMR_RXOK;
1143
1144 ah->mask_reg |= AR_IMR_TXOK;
1145
1146 if (opmode == NL80211_IFTYPE_AP)
1147 ah->mask_reg |= AR_IMR_MIB;
1148
1149 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1150 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1151
1152 if (!AR_SREV_9100(ah)) {
1153 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1154 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1155 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1156 }
1157 }
1158
1159 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1160 {
1161 u32 val = ath9k_hw_mac_to_clks(ah, us);
1162 val = min(val, (u32) 0xFFFF);
1163 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1164 }
1165
1166 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1167 {
1168 u32 val = ath9k_hw_mac_to_clks(ah, us);
1169 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1170 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1171 }
1172
1173 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1174 {
1175 u32 val = ath9k_hw_mac_to_clks(ah, us);
1176 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1177 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1178 }
1179
1180 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1181 {
1182 if (tu > 0xFFFF) {
1183 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1184 "bad global tx timeout %u\n", tu);
1185 ah->globaltxtimeout = (u32) -1;
1186 return false;
1187 } else {
1188 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1189 ah->globaltxtimeout = tu;
1190 return true;
1191 }
1192 }
1193
1194 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1195 {
1196 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1197 int acktimeout;
1198 int slottime;
1199 int sifstime;
1200
1201 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1202 ah->misc_mode);
1203
1204 if (ah->misc_mode != 0)
1205 REG_WRITE(ah, AR_PCU_MISC,
1206 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1207
1208 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1209 sifstime = 16;
1210 else
1211 sifstime = 10;
1212
1213 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1214 slottime = ah->slottime + 3 * ah->coverage_class;
1215 acktimeout = slottime + sifstime;
1216 ath9k_hw_setslottime(ah, slottime);
1217 ath9k_hw_set_ack_timeout(ah, acktimeout);
1218 ath9k_hw_set_cts_timeout(ah, acktimeout);
1219 if (ah->globaltxtimeout != (u32) -1)
1220 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1221 }
1222 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1223
1224 void ath9k_hw_deinit(struct ath_hw *ah)
1225 {
1226 struct ath_common *common = ath9k_hw_common(ah);
1227
1228 if (common->state <= ATH_HW_INITIALIZED)
1229 goto free_hw;
1230
1231 if (!AR_SREV_9100(ah))
1232 ath9k_hw_ani_disable(ah);
1233
1234 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1235
1236 free_hw:
1237 if (!AR_SREV_9280_10_OR_LATER(ah))
1238 ath9k_hw_rf_free_ext_banks(ah);
1239 kfree(ah);
1240 ah = NULL;
1241 }
1242 EXPORT_SYMBOL(ath9k_hw_deinit);
1243
1244 /*******/
1245 /* INI */
1246 /*******/
1247
1248 static void ath9k_hw_override_ini(struct ath_hw *ah,
1249 struct ath9k_channel *chan)
1250 {
1251 u32 val;
1252
1253 if (AR_SREV_9271(ah)) {
1254 /*
1255 * Enable spectral scan to solution for issues with stuck
1256 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1257 * AR9271 1.1
1258 */
1259 if (AR_SREV_9271_10(ah)) {
1260 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1261 AR_PHY_SPECTRAL_SCAN_ENABLE;
1262 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1263 }
1264 else if (AR_SREV_9271_11(ah))
1265 /*
1266 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1267 * present on AR9271 1.1
1268 */
1269 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1270 return;
1271 }
1272
1273 /*
1274 * Set the RX_ABORT and RX_DIS and clear if off only after
1275 * RXE is set for MAC. This prevents frames with corrupted
1276 * descriptor status.
1277 */
1278 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1279
1280 if (AR_SREV_9280_10_OR_LATER(ah)) {
1281 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1282 (~AR_PCU_MISC_MODE2_HWWAR1);
1283
1284 if (AR_SREV_9287_10_OR_LATER(ah))
1285 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1286
1287 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1288 }
1289
1290 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1291 AR_SREV_9280_10_OR_LATER(ah))
1292 return;
1293 /*
1294 * Disable BB clock gating
1295 * Necessary to avoid issues on AR5416 2.0
1296 */
1297 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1298 }
1299
1300 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1301 struct ar5416_eeprom_def *pEepData,
1302 u32 reg, u32 value)
1303 {
1304 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1305 struct ath_common *common = ath9k_hw_common(ah);
1306
1307 switch (ah->hw_version.devid) {
1308 case AR9280_DEVID_PCI:
1309 if (reg == 0x7894) {
1310 ath_print(common, ATH_DBG_EEPROM,
1311 "ini VAL: %x EEPROM: %x\n", value,
1312 (pBase->version & 0xff));
1313
1314 if ((pBase->version & 0xff) > 0x0a) {
1315 ath_print(common, ATH_DBG_EEPROM,
1316 "PWDCLKIND: %d\n",
1317 pBase->pwdclkind);
1318 value &= ~AR_AN_TOP2_PWDCLKIND;
1319 value |= AR_AN_TOP2_PWDCLKIND &
1320 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1321 } else {
1322 ath_print(common, ATH_DBG_EEPROM,
1323 "PWDCLKIND Earlier Rev\n");
1324 }
1325
1326 ath_print(common, ATH_DBG_EEPROM,
1327 "final ini VAL: %x\n", value);
1328 }
1329 break;
1330 }
1331
1332 return value;
1333 }
1334
1335 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1336 struct ar5416_eeprom_def *pEepData,
1337 u32 reg, u32 value)
1338 {
1339 if (ah->eep_map == EEP_MAP_4KBITS)
1340 return value;
1341 else
1342 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1343 }
1344
1345 static void ath9k_olc_init(struct ath_hw *ah)
1346 {
1347 u32 i;
1348
1349 if (OLC_FOR_AR9287_10_LATER) {
1350 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1351 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1352 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1353 AR9287_AN_TXPC0_TXPCMODE,
1354 AR9287_AN_TXPC0_TXPCMODE_S,
1355 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1356 udelay(100);
1357 } else {
1358 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1359 ah->originalGain[i] =
1360 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1361 AR_PHY_TX_GAIN);
1362 ah->PDADCdelta = 0;
1363 }
1364 }
1365
1366 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1367 struct ath9k_channel *chan)
1368 {
1369 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1370
1371 if (IS_CHAN_B(chan))
1372 ctl |= CTL_11B;
1373 else if (IS_CHAN_G(chan))
1374 ctl |= CTL_11G;
1375 else
1376 ctl |= CTL_11A;
1377
1378 return ctl;
1379 }
1380
1381 static int ath9k_hw_process_ini(struct ath_hw *ah,
1382 struct ath9k_channel *chan)
1383 {
1384 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1385 int i, regWrites = 0;
1386 struct ieee80211_channel *channel = chan->chan;
1387 u32 modesIndex, freqIndex;
1388
1389 switch (chan->chanmode) {
1390 case CHANNEL_A:
1391 case CHANNEL_A_HT20:
1392 modesIndex = 1;
1393 freqIndex = 1;
1394 break;
1395 case CHANNEL_A_HT40PLUS:
1396 case CHANNEL_A_HT40MINUS:
1397 modesIndex = 2;
1398 freqIndex = 1;
1399 break;
1400 case CHANNEL_G:
1401 case CHANNEL_G_HT20:
1402 case CHANNEL_B:
1403 modesIndex = 4;
1404 freqIndex = 2;
1405 break;
1406 case CHANNEL_G_HT40PLUS:
1407 case CHANNEL_G_HT40MINUS:
1408 modesIndex = 3;
1409 freqIndex = 2;
1410 break;
1411
1412 default:
1413 return -EINVAL;
1414 }
1415
1416 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1417 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1418 ah->eep_ops->set_addac(ah, chan);
1419
1420 if (AR_SREV_5416_22_OR_LATER(ah)) {
1421 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1422 } else {
1423 struct ar5416IniArray temp;
1424 u32 addacSize =
1425 sizeof(u32) * ah->iniAddac.ia_rows *
1426 ah->iniAddac.ia_columns;
1427
1428 memcpy(ah->addac5416_21,
1429 ah->iniAddac.ia_array, addacSize);
1430
1431 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1432
1433 temp.ia_array = ah->addac5416_21;
1434 temp.ia_columns = ah->iniAddac.ia_columns;
1435 temp.ia_rows = ah->iniAddac.ia_rows;
1436 REG_WRITE_ARRAY(&temp, 1, regWrites);
1437 }
1438
1439 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1440
1441 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1442 u32 reg = INI_RA(&ah->iniModes, i, 0);
1443 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1444
1445 REG_WRITE(ah, reg, val);
1446
1447 if (reg >= 0x7800 && reg < 0x78a0
1448 && ah->config.analog_shiftreg) {
1449 udelay(100);
1450 }
1451
1452 DO_DELAY(regWrites);
1453 }
1454
1455 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1456 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1457
1458 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1459 AR_SREV_9287_10_OR_LATER(ah))
1460 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1461
1462 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1463 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1464 u32 val = INI_RA(&ah->iniCommon, i, 1);
1465
1466 REG_WRITE(ah, reg, val);
1467
1468 if (reg >= 0x7800 && reg < 0x78a0
1469 && ah->config.analog_shiftreg) {
1470 udelay(100);
1471 }
1472
1473 DO_DELAY(regWrites);
1474 }
1475
1476 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1477
1478 if (AR_SREV_9271_10(ah))
1479 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1480 modesIndex, regWrites);
1481
1482 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1483 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1484 regWrites);
1485 }
1486
1487 ath9k_hw_override_ini(ah, chan);
1488 ath9k_hw_set_regs(ah, chan);
1489 ath9k_hw_init_chain_masks(ah);
1490
1491 if (OLC_FOR_AR9280_20_LATER)
1492 ath9k_olc_init(ah);
1493
1494 ah->eep_ops->set_txpower(ah, chan,
1495 ath9k_regd_get_ctl(regulatory, chan),
1496 channel->max_antenna_gain * 2,
1497 channel->max_power * 2,
1498 min((u32) MAX_RATE_POWER,
1499 (u32) regulatory->power_limit));
1500
1501 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1502 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1503 "ar5416SetRfRegs failed\n");
1504 return -EIO;
1505 }
1506
1507 return 0;
1508 }
1509
1510 /****************************************/
1511 /* Reset and Channel Switching Routines */
1512 /****************************************/
1513
1514 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1515 {
1516 u32 rfMode = 0;
1517
1518 if (chan == NULL)
1519 return;
1520
1521 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1522 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1523
1524 if (!AR_SREV_9280_10_OR_LATER(ah))
1525 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1526 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1527
1528 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1529 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1530
1531 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1532 }
1533
1534 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1535 {
1536 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1537 }
1538
1539 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1540 {
1541 u32 regval;
1542
1543 /*
1544 * set AHB_MODE not to do cacheline prefetches
1545 */
1546 regval = REG_READ(ah, AR_AHB_MODE);
1547 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1548
1549 /*
1550 * let mac dma reads be in 128 byte chunks
1551 */
1552 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1553 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1554
1555 /*
1556 * Restore TX Trigger Level to its pre-reset value.
1557 * The initial value depends on whether aggregation is enabled, and is
1558 * adjusted whenever underruns are detected.
1559 */
1560 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1561
1562 /*
1563 * let mac dma writes be in 128 byte chunks
1564 */
1565 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1566 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1567
1568 /*
1569 * Setup receive FIFO threshold to hold off TX activities
1570 */
1571 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1572
1573 /*
1574 * reduce the number of usable entries in PCU TXBUF to avoid
1575 * wrap around issues.
1576 */
1577 if (AR_SREV_9285(ah)) {
1578 /* For AR9285 the number of Fifos are reduced to half.
1579 * So set the usable tx buf size also to half to
1580 * avoid data/delimiter underruns
1581 */
1582 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1583 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1584 } else if (!AR_SREV_9271(ah)) {
1585 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1586 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1587 }
1588 }
1589
1590 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1591 {
1592 u32 val;
1593
1594 val = REG_READ(ah, AR_STA_ID1);
1595 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1596 switch (opmode) {
1597 case NL80211_IFTYPE_AP:
1598 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1599 | AR_STA_ID1_KSRCH_MODE);
1600 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1601 break;
1602 case NL80211_IFTYPE_ADHOC:
1603 case NL80211_IFTYPE_MESH_POINT:
1604 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1605 | AR_STA_ID1_KSRCH_MODE);
1606 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1607 break;
1608 case NL80211_IFTYPE_STATION:
1609 case NL80211_IFTYPE_MONITOR:
1610 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1611 break;
1612 }
1613 }
1614
1615 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1616 u32 coef_scaled,
1617 u32 *coef_mantissa,
1618 u32 *coef_exponent)
1619 {
1620 u32 coef_exp, coef_man;
1621
1622 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1623 if ((coef_scaled >> coef_exp) & 0x1)
1624 break;
1625
1626 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1627
1628 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1629
1630 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1631 *coef_exponent = coef_exp - 16;
1632 }
1633
1634 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1635 struct ath9k_channel *chan)
1636 {
1637 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1638 u32 clockMhzScaled = 0x64000000;
1639 struct chan_centers centers;
1640
1641 if (IS_CHAN_HALF_RATE(chan))
1642 clockMhzScaled = clockMhzScaled >> 1;
1643 else if (IS_CHAN_QUARTER_RATE(chan))
1644 clockMhzScaled = clockMhzScaled >> 2;
1645
1646 ath9k_hw_get_channel_centers(ah, chan, &centers);
1647 coef_scaled = clockMhzScaled / centers.synth_center;
1648
1649 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1650 &ds_coef_exp);
1651
1652 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1653 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1654 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1655 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1656
1657 coef_scaled = (9 * coef_scaled) / 10;
1658
1659 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1660 &ds_coef_exp);
1661
1662 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1663 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1664 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1665 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1666 }
1667
1668 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1669 {
1670 u32 rst_flags;
1671 u32 tmpReg;
1672
1673 if (AR_SREV_9100(ah)) {
1674 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1675 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1676 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1677 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1678 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1679 }
1680
1681 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1682 AR_RTC_FORCE_WAKE_ON_INT);
1683
1684 if (AR_SREV_9100(ah)) {
1685 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1686 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1687 } else {
1688 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1689 if (tmpReg &
1690 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1691 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1692 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1693 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1694 } else {
1695 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1696 }
1697
1698 rst_flags = AR_RTC_RC_MAC_WARM;
1699 if (type == ATH9K_RESET_COLD)
1700 rst_flags |= AR_RTC_RC_MAC_COLD;
1701 }
1702
1703 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1704 udelay(50);
1705
1706 REG_WRITE(ah, AR_RTC_RC, 0);
1707 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1708 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1709 "RTC stuck in MAC reset\n");
1710 return false;
1711 }
1712
1713 if (!AR_SREV_9100(ah))
1714 REG_WRITE(ah, AR_RC, 0);
1715
1716 if (AR_SREV_9100(ah))
1717 udelay(50);
1718
1719 return true;
1720 }
1721
1722 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1723 {
1724 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1725 AR_RTC_FORCE_WAKE_ON_INT);
1726
1727 if (!AR_SREV_9100(ah))
1728 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1729
1730 REG_WRITE(ah, AR_RTC_RESET, 0);
1731 udelay(2);
1732
1733 if (!AR_SREV_9100(ah))
1734 REG_WRITE(ah, AR_RC, 0);
1735
1736 REG_WRITE(ah, AR_RTC_RESET, 1);
1737
1738 if (!ath9k_hw_wait(ah,
1739 AR_RTC_STATUS,
1740 AR_RTC_STATUS_M,
1741 AR_RTC_STATUS_ON,
1742 AH_WAIT_TIMEOUT)) {
1743 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1744 "RTC not waking up\n");
1745 return false;
1746 }
1747
1748 ath9k_hw_read_revisions(ah);
1749
1750 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1751 }
1752
1753 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1754 {
1755 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1756 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1757
1758 switch (type) {
1759 case ATH9K_RESET_POWER_ON:
1760 return ath9k_hw_set_reset_power_on(ah);
1761 case ATH9K_RESET_WARM:
1762 case ATH9K_RESET_COLD:
1763 return ath9k_hw_set_reset(ah, type);
1764 default:
1765 return false;
1766 }
1767 }
1768
1769 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1770 {
1771 u32 phymode;
1772 u32 enableDacFifo = 0;
1773
1774 if (AR_SREV_9285_10_OR_LATER(ah))
1775 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1776 AR_PHY_FC_ENABLE_DAC_FIFO);
1777
1778 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1779 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1780
1781 if (IS_CHAN_HT40(chan)) {
1782 phymode |= AR_PHY_FC_DYN2040_EN;
1783
1784 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1785 (chan->chanmode == CHANNEL_G_HT40PLUS))
1786 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1787
1788 }
1789 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1790
1791 ath9k_hw_set11nmac2040(ah);
1792
1793 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1794 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1795 }
1796
1797 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1798 struct ath9k_channel *chan)
1799 {
1800 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1801 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1802 return false;
1803 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1804 return false;
1805
1806 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1807 return false;
1808
1809 ah->chip_fullsleep = false;
1810 ath9k_hw_init_pll(ah, chan);
1811 ath9k_hw_set_rfmode(ah, chan);
1812
1813 return true;
1814 }
1815
1816 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1817 struct ath9k_channel *chan)
1818 {
1819 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1820 struct ath_common *common = ath9k_hw_common(ah);
1821 struct ieee80211_channel *channel = chan->chan;
1822 u32 synthDelay, qnum;
1823 int r;
1824
1825 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1826 if (ath9k_hw_numtxpending(ah, qnum)) {
1827 ath_print(common, ATH_DBG_QUEUE,
1828 "Transmit frames pending on "
1829 "queue %d\n", qnum);
1830 return false;
1831 }
1832 }
1833
1834 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1835 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1836 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1837 ath_print(common, ATH_DBG_FATAL,
1838 "Could not kill baseband RX\n");
1839 return false;
1840 }
1841
1842 ath9k_hw_set_regs(ah, chan);
1843
1844 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1845 if (r) {
1846 ath_print(common, ATH_DBG_FATAL,
1847 "Failed to set channel\n");
1848 return false;
1849 }
1850
1851 ah->eep_ops->set_txpower(ah, chan,
1852 ath9k_regd_get_ctl(regulatory, chan),
1853 channel->max_antenna_gain * 2,
1854 channel->max_power * 2,
1855 min((u32) MAX_RATE_POWER,
1856 (u32) regulatory->power_limit));
1857
1858 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1859 if (IS_CHAN_B(chan))
1860 synthDelay = (4 * synthDelay) / 22;
1861 else
1862 synthDelay /= 10;
1863
1864 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1865
1866 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1867
1868 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1869 ath9k_hw_set_delta_slope(ah, chan);
1870
1871 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1872
1873 if (!chan->oneTimeCalsDone)
1874 chan->oneTimeCalsDone = true;
1875
1876 return true;
1877 }
1878
1879 static void ath9k_enable_rfkill(struct ath_hw *ah)
1880 {
1881 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1882 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1883
1884 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1885 AR_GPIO_INPUT_MUX2_RFSILENT);
1886
1887 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1888 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1889 }
1890
1891 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1892 bool bChannelChange)
1893 {
1894 struct ath_common *common = ath9k_hw_common(ah);
1895 u32 saveLedState;
1896 struct ath9k_channel *curchan = ah->curchan;
1897 u32 saveDefAntenna;
1898 u32 macStaId1;
1899 u64 tsf = 0;
1900 int i, rx_chainmask, r;
1901
1902 ah->txchainmask = common->tx_chainmask;
1903 ah->rxchainmask = common->rx_chainmask;
1904
1905 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1906 return -EIO;
1907
1908 if (curchan && !ah->chip_fullsleep)
1909 ath9k_hw_getnf(ah, curchan);
1910
1911 if (bChannelChange &&
1912 (ah->chip_fullsleep != true) &&
1913 (ah->curchan != NULL) &&
1914 (chan->channel != ah->curchan->channel) &&
1915 ((chan->channelFlags & CHANNEL_ALL) ==
1916 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1917 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1918 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1919
1920 if (ath9k_hw_channel_change(ah, chan)) {
1921 ath9k_hw_loadnf(ah, ah->curchan);
1922 ath9k_hw_start_nfcal(ah);
1923 return 0;
1924 }
1925 }
1926
1927 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1928 if (saveDefAntenna == 0)
1929 saveDefAntenna = 1;
1930
1931 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1932
1933 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1934 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1935 tsf = ath9k_hw_gettsf64(ah);
1936
1937 saveLedState = REG_READ(ah, AR_CFG_LED) &
1938 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1939 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1940
1941 ath9k_hw_mark_phy_inactive(ah);
1942
1943 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1944 REG_WRITE(ah,
1945 AR9271_RESET_POWER_DOWN_CONTROL,
1946 AR9271_RADIO_RF_RST);
1947 udelay(50);
1948 }
1949
1950 if (!ath9k_hw_chip_reset(ah, chan)) {
1951 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1952 return -EINVAL;
1953 }
1954
1955 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1956 ah->htc_reset_init = false;
1957 REG_WRITE(ah,
1958 AR9271_RESET_POWER_DOWN_CONTROL,
1959 AR9271_GATE_MAC_CTL);
1960 udelay(50);
1961 }
1962
1963 /* Restore TSF */
1964 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1965 ath9k_hw_settsf64(ah, tsf);
1966
1967 if (AR_SREV_9280_10_OR_LATER(ah))
1968 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1969
1970 if (AR_SREV_9287_12_OR_LATER(ah)) {
1971 /* Enable ASYNC FIFO */
1972 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1973 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1974 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1975 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1976 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1977 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1978 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1979 }
1980 r = ath9k_hw_process_ini(ah, chan);
1981 if (r)
1982 return r;
1983
1984 /* Setup MFP options for CCMP */
1985 if (AR_SREV_9280_20_OR_LATER(ah)) {
1986 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1987 * frames when constructing CCMP AAD. */
1988 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1989 0xc7ff);
1990 ah->sw_mgmt_crypto = false;
1991 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1992 /* Disable hardware crypto for management frames */
1993 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1994 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1995 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1996 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1997 ah->sw_mgmt_crypto = true;
1998 } else
1999 ah->sw_mgmt_crypto = true;
2000
2001 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2002 ath9k_hw_set_delta_slope(ah, chan);
2003
2004 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2005 ah->eep_ops->set_board_values(ah, chan);
2006
2007 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2008 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2009 | macStaId1
2010 | AR_STA_ID1_RTS_USE_DEF
2011 | (ah->config.
2012 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2013 | ah->sta_id1_defaults);
2014 ath9k_hw_set_operating_mode(ah, ah->opmode);
2015
2016 ath_hw_setbssidmask(common);
2017
2018 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2019
2020 ath9k_hw_write_associd(ah);
2021
2022 REG_WRITE(ah, AR_ISR, ~0);
2023
2024 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2025
2026 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2027 if (r)
2028 return r;
2029
2030 for (i = 0; i < AR_NUM_DCU; i++)
2031 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2032
2033 ah->intr_txqs = 0;
2034 for (i = 0; i < ah->caps.total_queues; i++)
2035 ath9k_hw_resettxqueue(ah, i);
2036
2037 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2038 ath9k_hw_init_qos(ah);
2039
2040 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2041 ath9k_enable_rfkill(ah);
2042
2043 ath9k_hw_init_global_settings(ah);
2044
2045 if (AR_SREV_9287_12_OR_LATER(ah)) {
2046 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2047 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2048 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2049 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2050 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2051 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2052
2053 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2054 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2055
2056 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2057 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2058 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2059 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2060 }
2061 if (AR_SREV_9287_12_OR_LATER(ah)) {
2062 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2063 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2064 }
2065
2066 REG_WRITE(ah, AR_STA_ID1,
2067 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2068
2069 ath9k_hw_set_dma(ah);
2070
2071 REG_WRITE(ah, AR_OBS, 8);
2072
2073 if (ah->config.rx_intr_mitigation) {
2074 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2075 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2076 }
2077
2078 ath9k_hw_init_bb(ah, chan);
2079
2080 if (!ath9k_hw_init_cal(ah, chan))
2081 return -EIO;
2082
2083 rx_chainmask = ah->rxchainmask;
2084 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2085 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2086 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2087 }
2088
2089 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2090
2091 /*
2092 * For big endian systems turn on swapping for descriptors
2093 */
2094 if (AR_SREV_9100(ah)) {
2095 u32 mask;
2096 mask = REG_READ(ah, AR_CFG);
2097 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2098 ath_print(common, ATH_DBG_RESET,
2099 "CFG Byte Swap Set 0x%x\n", mask);
2100 } else {
2101 mask =
2102 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2103 REG_WRITE(ah, AR_CFG, mask);
2104 ath_print(common, ATH_DBG_RESET,
2105 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2106 }
2107 } else {
2108 /* Configure AR9271 target WLAN */
2109 if (AR_SREV_9271(ah))
2110 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2111 #ifdef __BIG_ENDIAN
2112 else
2113 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2114 #endif
2115 }
2116
2117 if (ah->btcoex_hw.enabled)
2118 ath9k_hw_btcoex_enable(ah);
2119
2120 return 0;
2121 }
2122 EXPORT_SYMBOL(ath9k_hw_reset);
2123
2124 /************************/
2125 /* Key Cache Management */
2126 /************************/
2127
2128 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2129 {
2130 u32 keyType;
2131
2132 if (entry >= ah->caps.keycache_size) {
2133 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2134 "keychache entry %u out of range\n", entry);
2135 return false;
2136 }
2137
2138 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2139
2140 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2141 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2142 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2143 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2144 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2145 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2146 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2147 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2148
2149 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2150 u16 micentry = entry + 64;
2151
2152 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2153 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2154 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2155 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2156
2157 }
2158
2159 return true;
2160 }
2161 EXPORT_SYMBOL(ath9k_hw_keyreset);
2162
2163 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2164 {
2165 u32 macHi, macLo;
2166
2167 if (entry >= ah->caps.keycache_size) {
2168 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2169 "keychache entry %u out of range\n", entry);
2170 return false;
2171 }
2172
2173 if (mac != NULL) {
2174 macHi = (mac[5] << 8) | mac[4];
2175 macLo = (mac[3] << 24) |
2176 (mac[2] << 16) |
2177 (mac[1] << 8) |
2178 mac[0];
2179 macLo >>= 1;
2180 macLo |= (macHi & 1) << 31;
2181 macHi >>= 1;
2182 } else {
2183 macLo = macHi = 0;
2184 }
2185 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2186 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2187
2188 return true;
2189 }
2190 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2191
2192 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2193 const struct ath9k_keyval *k,
2194 const u8 *mac)
2195 {
2196 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2197 struct ath_common *common = ath9k_hw_common(ah);
2198 u32 key0, key1, key2, key3, key4;
2199 u32 keyType;
2200
2201 if (entry >= pCap->keycache_size) {
2202 ath_print(common, ATH_DBG_FATAL,
2203 "keycache entry %u out of range\n", entry);
2204 return false;
2205 }
2206
2207 switch (k->kv_type) {
2208 case ATH9K_CIPHER_AES_OCB:
2209 keyType = AR_KEYTABLE_TYPE_AES;
2210 break;
2211 case ATH9K_CIPHER_AES_CCM:
2212 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2213 ath_print(common, ATH_DBG_ANY,
2214 "AES-CCM not supported by mac rev 0x%x\n",
2215 ah->hw_version.macRev);
2216 return false;
2217 }
2218 keyType = AR_KEYTABLE_TYPE_CCM;
2219 break;
2220 case ATH9K_CIPHER_TKIP:
2221 keyType = AR_KEYTABLE_TYPE_TKIP;
2222 if (ATH9K_IS_MIC_ENABLED(ah)
2223 && entry + 64 >= pCap->keycache_size) {
2224 ath_print(common, ATH_DBG_ANY,
2225 "entry %u inappropriate for TKIP\n", entry);
2226 return false;
2227 }
2228 break;
2229 case ATH9K_CIPHER_WEP:
2230 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2231 ath_print(common, ATH_DBG_ANY,
2232 "WEP key length %u too small\n", k->kv_len);
2233 return false;
2234 }
2235 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2236 keyType = AR_KEYTABLE_TYPE_40;
2237 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2238 keyType = AR_KEYTABLE_TYPE_104;
2239 else
2240 keyType = AR_KEYTABLE_TYPE_128;
2241 break;
2242 case ATH9K_CIPHER_CLR:
2243 keyType = AR_KEYTABLE_TYPE_CLR;
2244 break;
2245 default:
2246 ath_print(common, ATH_DBG_FATAL,
2247 "cipher %u not supported\n", k->kv_type);
2248 return false;
2249 }
2250
2251 key0 = get_unaligned_le32(k->kv_val + 0);
2252 key1 = get_unaligned_le16(k->kv_val + 4);
2253 key2 = get_unaligned_le32(k->kv_val + 6);
2254 key3 = get_unaligned_le16(k->kv_val + 10);
2255 key4 = get_unaligned_le32(k->kv_val + 12);
2256 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2257 key4 &= 0xff;
2258
2259 /*
2260 * Note: Key cache registers access special memory area that requires
2261 * two 32-bit writes to actually update the values in the internal
2262 * memory. Consequently, the exact order and pairs used here must be
2263 * maintained.
2264 */
2265
2266 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2267 u16 micentry = entry + 64;
2268
2269 /*
2270 * Write inverted key[47:0] first to avoid Michael MIC errors
2271 * on frames that could be sent or received at the same time.
2272 * The correct key will be written in the end once everything
2273 * else is ready.
2274 */
2275 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2276 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2277
2278 /* Write key[95:48] */
2279 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2280 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2281
2282 /* Write key[127:96] and key type */
2283 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2284 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2285
2286 /* Write MAC address for the entry */
2287 (void) ath9k_hw_keysetmac(ah, entry, mac);
2288
2289 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2290 /*
2291 * TKIP uses two key cache entries:
2292 * Michael MIC TX/RX keys in the same key cache entry
2293 * (idx = main index + 64):
2294 * key0 [31:0] = RX key [31:0]
2295 * key1 [15:0] = TX key [31:16]
2296 * key1 [31:16] = reserved
2297 * key2 [31:0] = RX key [63:32]
2298 * key3 [15:0] = TX key [15:0]
2299 * key3 [31:16] = reserved
2300 * key4 [31:0] = TX key [63:32]
2301 */
2302 u32 mic0, mic1, mic2, mic3, mic4;
2303
2304 mic0 = get_unaligned_le32(k->kv_mic + 0);
2305 mic2 = get_unaligned_le32(k->kv_mic + 4);
2306 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2307 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2308 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2309
2310 /* Write RX[31:0] and TX[31:16] */
2311 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2312 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2313
2314 /* Write RX[63:32] and TX[15:0] */
2315 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2316 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2317
2318 /* Write TX[63:32] and keyType(reserved) */
2319 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2320 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2321 AR_KEYTABLE_TYPE_CLR);
2322
2323 } else {
2324 /*
2325 * TKIP uses four key cache entries (two for group
2326 * keys):
2327 * Michael MIC TX/RX keys are in different key cache
2328 * entries (idx = main index + 64 for TX and
2329 * main index + 32 + 96 for RX):
2330 * key0 [31:0] = TX/RX MIC key [31:0]
2331 * key1 [31:0] = reserved
2332 * key2 [31:0] = TX/RX MIC key [63:32]
2333 * key3 [31:0] = reserved
2334 * key4 [31:0] = reserved
2335 *
2336 * Upper layer code will call this function separately
2337 * for TX and RX keys when these registers offsets are
2338 * used.
2339 */
2340 u32 mic0, mic2;
2341
2342 mic0 = get_unaligned_le32(k->kv_mic + 0);
2343 mic2 = get_unaligned_le32(k->kv_mic + 4);
2344
2345 /* Write MIC key[31:0] */
2346 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2347 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2348
2349 /* Write MIC key[63:32] */
2350 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2351 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2352
2353 /* Write TX[63:32] and keyType(reserved) */
2354 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2355 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2356 AR_KEYTABLE_TYPE_CLR);
2357 }
2358
2359 /* MAC address registers are reserved for the MIC entry */
2360 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2361 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2362
2363 /*
2364 * Write the correct (un-inverted) key[47:0] last to enable
2365 * TKIP now that all other registers are set with correct
2366 * values.
2367 */
2368 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2369 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2370 } else {
2371 /* Write key[47:0] */
2372 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2373 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2374
2375 /* Write key[95:48] */
2376 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2377 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2378
2379 /* Write key[127:96] and key type */
2380 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2381 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2382
2383 /* Write MAC address for the entry */
2384 (void) ath9k_hw_keysetmac(ah, entry, mac);
2385 }
2386
2387 return true;
2388 }
2389 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2390
2391 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2392 {
2393 if (entry < ah->caps.keycache_size) {
2394 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2395 if (val & AR_KEYTABLE_VALID)
2396 return true;
2397 }
2398 return false;
2399 }
2400 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2401
2402 /******************************/
2403 /* Power Management (Chipset) */
2404 /******************************/
2405
2406 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2407 {
2408 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2409 if (setChip) {
2410 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2411 AR_RTC_FORCE_WAKE_EN);
2412 if (!AR_SREV_9100(ah))
2413 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2414
2415 if(!AR_SREV_5416(ah))
2416 REG_CLR_BIT(ah, (AR_RTC_RESET),
2417 AR_RTC_RESET_EN);
2418 }
2419 }
2420
2421 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2422 {
2423 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2424 if (setChip) {
2425 struct ath9k_hw_capabilities *pCap = &ah->caps;
2426
2427 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2428 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2429 AR_RTC_FORCE_WAKE_ON_INT);
2430 } else {
2431 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2432 AR_RTC_FORCE_WAKE_EN);
2433 }
2434 }
2435 }
2436
2437 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2438 {
2439 u32 val;
2440 int i;
2441
2442 if (setChip) {
2443 if ((REG_READ(ah, AR_RTC_STATUS) &
2444 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2445 if (ath9k_hw_set_reset_reg(ah,
2446 ATH9K_RESET_POWER_ON) != true) {
2447 return false;
2448 }
2449 ath9k_hw_init_pll(ah, NULL);
2450 }
2451 if (AR_SREV_9100(ah))
2452 REG_SET_BIT(ah, AR_RTC_RESET,
2453 AR_RTC_RESET_EN);
2454
2455 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2456 AR_RTC_FORCE_WAKE_EN);
2457 udelay(50);
2458
2459 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2460 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2461 if (val == AR_RTC_STATUS_ON)
2462 break;
2463 udelay(50);
2464 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2465 AR_RTC_FORCE_WAKE_EN);
2466 }
2467 if (i == 0) {
2468 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2469 "Failed to wakeup in %uus\n",
2470 POWER_UP_TIME / 20);
2471 return false;
2472 }
2473 }
2474
2475 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2476
2477 return true;
2478 }
2479
2480 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2481 {
2482 struct ath_common *common = ath9k_hw_common(ah);
2483 int status = true, setChip = true;
2484 static const char *modes[] = {
2485 "AWAKE",
2486 "FULL-SLEEP",
2487 "NETWORK SLEEP",
2488 "UNDEFINED"
2489 };
2490
2491 if (ah->power_mode == mode)
2492 return status;
2493
2494 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2495 modes[ah->power_mode], modes[mode]);
2496
2497 switch (mode) {
2498 case ATH9K_PM_AWAKE:
2499 status = ath9k_hw_set_power_awake(ah, setChip);
2500 break;
2501 case ATH9K_PM_FULL_SLEEP:
2502 ath9k_set_power_sleep(ah, setChip);
2503 ah->chip_fullsleep = true;
2504 break;
2505 case ATH9K_PM_NETWORK_SLEEP:
2506 ath9k_set_power_network_sleep(ah, setChip);
2507 break;
2508 default:
2509 ath_print(common, ATH_DBG_FATAL,
2510 "Unknown power mode %u\n", mode);
2511 return false;
2512 }
2513 ah->power_mode = mode;
2514
2515 return status;
2516 }
2517 EXPORT_SYMBOL(ath9k_hw_setpower);
2518
2519 /*
2520 * Helper for ASPM support.
2521 *
2522 * Disable PLL when in L0s as well as receiver clock when in L1.
2523 * This power saving option must be enabled through the SerDes.
2524 *
2525 * Programming the SerDes must go through the same 288 bit serial shift
2526 * register as the other analog registers. Hence the 9 writes.
2527 */
2528 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2529 {
2530 u8 i;
2531 u32 val;
2532
2533 if (ah->is_pciexpress != true)
2534 return;
2535
2536 /* Do not touch SerDes registers */
2537 if (ah->config.pcie_powersave_enable == 2)
2538 return;
2539
2540 /* Nothing to do on restore for 11N */
2541 if (!restore) {
2542 if (AR_SREV_9280_20_OR_LATER(ah)) {
2543 /*
2544 * AR9280 2.0 or later chips use SerDes values from the
2545 * initvals.h initialized depending on chipset during
2546 * ath9k_hw_init()
2547 */
2548 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2549 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2550 INI_RA(&ah->iniPcieSerdes, i, 1));
2551 }
2552 } else if (AR_SREV_9280(ah) &&
2553 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2554 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2555 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2556
2557 /* RX shut off when elecidle is asserted */
2558 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2559 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2560 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2561
2562 /* Shut off CLKREQ active in L1 */
2563 if (ah->config.pcie_clock_req)
2564 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2565 else
2566 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2567
2568 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2569 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2570 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2571
2572 /* Load the new settings */
2573 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2574
2575 } else {
2576 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2577 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2578
2579 /* RX shut off when elecidle is asserted */
2580 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2581 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2582 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2583
2584 /*
2585 * Ignore ah->ah_config.pcie_clock_req setting for
2586 * pre-AR9280 11n
2587 */
2588 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2589
2590 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2591 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2592 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2593
2594 /* Load the new settings */
2595 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2596 }
2597
2598 udelay(1000);
2599
2600 /* set bit 19 to allow forcing of pcie core into L1 state */
2601 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2602
2603 /* Several PCIe massages to ensure proper behaviour */
2604 if (ah->config.pcie_waen) {
2605 val = ah->config.pcie_waen;
2606 if (!power_off)
2607 val &= (~AR_WA_D3_L1_DISABLE);
2608 } else {
2609 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2610 AR_SREV_9287(ah)) {
2611 val = AR9285_WA_DEFAULT;
2612 if (!power_off)
2613 val &= (~AR_WA_D3_L1_DISABLE);
2614 } else if (AR_SREV_9280(ah)) {
2615 /*
2616 * On AR9280 chips bit 22 of 0x4004 needs to be
2617 * set otherwise card may disappear.
2618 */
2619 val = AR9280_WA_DEFAULT;
2620 if (!power_off)
2621 val &= (~AR_WA_D3_L1_DISABLE);
2622 } else
2623 val = AR_WA_DEFAULT;
2624 }
2625
2626 REG_WRITE(ah, AR_WA, val);
2627 }
2628
2629 if (power_off) {
2630 /*
2631 * Set PCIe workaround bits
2632 * bit 14 in WA register (disable L1) should only
2633 * be set when device enters D3 and be cleared
2634 * when device comes back to D0.
2635 */
2636 if (ah->config.pcie_waen) {
2637 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2638 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2639 } else {
2640 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2641 AR_SREV_9287(ah)) &&
2642 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2643 (AR_SREV_9280(ah) &&
2644 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2645 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2646 }
2647 }
2648 }
2649 }
2650 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2651
2652 /**********************/
2653 /* Interrupt Handling */
2654 /**********************/
2655
2656 bool ath9k_hw_intrpend(struct ath_hw *ah)
2657 {
2658 u32 host_isr;
2659
2660 if (AR_SREV_9100(ah))
2661 return true;
2662
2663 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2664 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2665 return true;
2666
2667 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2668 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2669 && (host_isr != AR_INTR_SPURIOUS))
2670 return true;
2671
2672 return false;
2673 }
2674 EXPORT_SYMBOL(ath9k_hw_intrpend);
2675
2676 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2677 {
2678 u32 isr = 0;
2679 u32 mask2 = 0;
2680 struct ath9k_hw_capabilities *pCap = &ah->caps;
2681 u32 sync_cause = 0;
2682 bool fatal_int = false;
2683 struct ath_common *common = ath9k_hw_common(ah);
2684
2685 if (!AR_SREV_9100(ah)) {
2686 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2687 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2688 == AR_RTC_STATUS_ON) {
2689 isr = REG_READ(ah, AR_ISR);
2690 }
2691 }
2692
2693 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2694 AR_INTR_SYNC_DEFAULT;
2695
2696 *masked = 0;
2697
2698 if (!isr && !sync_cause)
2699 return false;
2700 } else {
2701 *masked = 0;
2702 isr = REG_READ(ah, AR_ISR);
2703 }
2704
2705 if (isr) {
2706 if (isr & AR_ISR_BCNMISC) {
2707 u32 isr2;
2708 isr2 = REG_READ(ah, AR_ISR_S2);
2709 if (isr2 & AR_ISR_S2_TIM)
2710 mask2 |= ATH9K_INT_TIM;
2711 if (isr2 & AR_ISR_S2_DTIM)
2712 mask2 |= ATH9K_INT_DTIM;
2713 if (isr2 & AR_ISR_S2_DTIMSYNC)
2714 mask2 |= ATH9K_INT_DTIMSYNC;
2715 if (isr2 & (AR_ISR_S2_CABEND))
2716 mask2 |= ATH9K_INT_CABEND;
2717 if (isr2 & AR_ISR_S2_GTT)
2718 mask2 |= ATH9K_INT_GTT;
2719 if (isr2 & AR_ISR_S2_CST)
2720 mask2 |= ATH9K_INT_CST;
2721 if (isr2 & AR_ISR_S2_TSFOOR)
2722 mask2 |= ATH9K_INT_TSFOOR;
2723 }
2724
2725 isr = REG_READ(ah, AR_ISR_RAC);
2726 if (isr == 0xffffffff) {
2727 *masked = 0;
2728 return false;
2729 }
2730
2731 *masked = isr & ATH9K_INT_COMMON;
2732
2733 if (ah->config.rx_intr_mitigation) {
2734 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2735 *masked |= ATH9K_INT_RX;
2736 }
2737
2738 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2739 *masked |= ATH9K_INT_RX;
2740 if (isr &
2741 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2742 AR_ISR_TXEOL)) {
2743 u32 s0_s, s1_s;
2744
2745 *masked |= ATH9K_INT_TX;
2746
2747 s0_s = REG_READ(ah, AR_ISR_S0_S);
2748 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2749 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2750
2751 s1_s = REG_READ(ah, AR_ISR_S1_S);
2752 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2753 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2754 }
2755
2756 if (isr & AR_ISR_RXORN) {
2757 ath_print(common, ATH_DBG_INTERRUPT,
2758 "receive FIFO overrun interrupt\n");
2759 }
2760
2761 if (!AR_SREV_9100(ah)) {
2762 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2763 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2764 if (isr5 & AR_ISR_S5_TIM_TIMER)
2765 *masked |= ATH9K_INT_TIM_TIMER;
2766 }
2767 }
2768
2769 *masked |= mask2;
2770 }
2771
2772 if (AR_SREV_9100(ah))
2773 return true;
2774
2775 if (isr & AR_ISR_GENTMR) {
2776 u32 s5_s;
2777
2778 s5_s = REG_READ(ah, AR_ISR_S5_S);
2779 if (isr & AR_ISR_GENTMR) {
2780 ah->intr_gen_timer_trigger =
2781 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2782
2783 ah->intr_gen_timer_thresh =
2784 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2785
2786 if (ah->intr_gen_timer_trigger)
2787 *masked |= ATH9K_INT_GENTIMER;
2788
2789 }
2790 }
2791
2792 if (sync_cause) {
2793 fatal_int =
2794 (sync_cause &
2795 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2796 ? true : false;
2797
2798 if (fatal_int) {
2799 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2800 ath_print(common, ATH_DBG_ANY,
2801 "received PCI FATAL interrupt\n");
2802 }
2803 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2804 ath_print(common, ATH_DBG_ANY,
2805 "received PCI PERR interrupt\n");
2806 }
2807 *masked |= ATH9K_INT_FATAL;
2808 }
2809 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2810 ath_print(common, ATH_DBG_INTERRUPT,
2811 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2812 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2813 REG_WRITE(ah, AR_RC, 0);
2814 *masked |= ATH9K_INT_FATAL;
2815 }
2816 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2817 ath_print(common, ATH_DBG_INTERRUPT,
2818 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2819 }
2820
2821 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2822 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2823 }
2824
2825 return true;
2826 }
2827 EXPORT_SYMBOL(ath9k_hw_getisr);
2828
2829 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2830 {
2831 u32 omask = ah->mask_reg;
2832 u32 mask, mask2;
2833 struct ath9k_hw_capabilities *pCap = &ah->caps;
2834 struct ath_common *common = ath9k_hw_common(ah);
2835
2836 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2837
2838 if (omask & ATH9K_INT_GLOBAL) {
2839 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2840 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2841 (void) REG_READ(ah, AR_IER);
2842 if (!AR_SREV_9100(ah)) {
2843 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2844 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2845
2846 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2847 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2848 }
2849 }
2850
2851 mask = ints & ATH9K_INT_COMMON;
2852 mask2 = 0;
2853
2854 if (ints & ATH9K_INT_TX) {
2855 if (ah->txok_interrupt_mask)
2856 mask |= AR_IMR_TXOK;
2857 if (ah->txdesc_interrupt_mask)
2858 mask |= AR_IMR_TXDESC;
2859 if (ah->txerr_interrupt_mask)
2860 mask |= AR_IMR_TXERR;
2861 if (ah->txeol_interrupt_mask)
2862 mask |= AR_IMR_TXEOL;
2863 }
2864 if (ints & ATH9K_INT_RX) {
2865 mask |= AR_IMR_RXERR;
2866 if (ah->config.rx_intr_mitigation)
2867 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2868 else
2869 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2870 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2871 mask |= AR_IMR_GENTMR;
2872 }
2873
2874 if (ints & (ATH9K_INT_BMISC)) {
2875 mask |= AR_IMR_BCNMISC;
2876 if (ints & ATH9K_INT_TIM)
2877 mask2 |= AR_IMR_S2_TIM;
2878 if (ints & ATH9K_INT_DTIM)
2879 mask2 |= AR_IMR_S2_DTIM;
2880 if (ints & ATH9K_INT_DTIMSYNC)
2881 mask2 |= AR_IMR_S2_DTIMSYNC;
2882 if (ints & ATH9K_INT_CABEND)
2883 mask2 |= AR_IMR_S2_CABEND;
2884 if (ints & ATH9K_INT_TSFOOR)
2885 mask2 |= AR_IMR_S2_TSFOOR;
2886 }
2887
2888 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2889 mask |= AR_IMR_BCNMISC;
2890 if (ints & ATH9K_INT_GTT)
2891 mask2 |= AR_IMR_S2_GTT;
2892 if (ints & ATH9K_INT_CST)
2893 mask2 |= AR_IMR_S2_CST;
2894 }
2895
2896 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2897 REG_WRITE(ah, AR_IMR, mask);
2898 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2899 AR_IMR_S2_DTIM |
2900 AR_IMR_S2_DTIMSYNC |
2901 AR_IMR_S2_CABEND |
2902 AR_IMR_S2_CABTO |
2903 AR_IMR_S2_TSFOOR |
2904 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2905 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2906 ah->mask_reg = ints;
2907
2908 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2909 if (ints & ATH9K_INT_TIM_TIMER)
2910 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2911 else
2912 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2913 }
2914
2915 if (ints & ATH9K_INT_GLOBAL) {
2916 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2917 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2918 if (!AR_SREV_9100(ah)) {
2919 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2920 AR_INTR_MAC_IRQ);
2921 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2922
2923
2924 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2925 AR_INTR_SYNC_DEFAULT);
2926 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2927 AR_INTR_SYNC_DEFAULT);
2928 }
2929 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2930 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2931 }
2932
2933 return omask;
2934 }
2935 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2936
2937 /*******************/
2938 /* Beacon Handling */
2939 /*******************/
2940
2941 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2942 {
2943 int flags = 0;
2944
2945 ah->beacon_interval = beacon_period;
2946
2947 switch (ah->opmode) {
2948 case NL80211_IFTYPE_STATION:
2949 case NL80211_IFTYPE_MONITOR:
2950 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2951 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2952 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2953 flags |= AR_TBTT_TIMER_EN;
2954 break;
2955 case NL80211_IFTYPE_ADHOC:
2956 case NL80211_IFTYPE_MESH_POINT:
2957 REG_SET_BIT(ah, AR_TXCFG,
2958 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2959 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2960 TU_TO_USEC(next_beacon +
2961 (ah->atim_window ? ah->
2962 atim_window : 1)));
2963 flags |= AR_NDP_TIMER_EN;
2964 case NL80211_IFTYPE_AP:
2965 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2966 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2967 TU_TO_USEC(next_beacon -
2968 ah->config.
2969 dma_beacon_response_time));
2970 REG_WRITE(ah, AR_NEXT_SWBA,
2971 TU_TO_USEC(next_beacon -
2972 ah->config.
2973 sw_beacon_response_time));
2974 flags |=
2975 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2976 break;
2977 default:
2978 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2979 "%s: unsupported opmode: %d\n",
2980 __func__, ah->opmode);
2981 return;
2982 break;
2983 }
2984
2985 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2986 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2987 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2988 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2989
2990 beacon_period &= ~ATH9K_BEACON_ENA;
2991 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2992 ath9k_hw_reset_tsf(ah);
2993 }
2994
2995 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2996 }
2997 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2998
2999 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3000 const struct ath9k_beacon_state *bs)
3001 {
3002 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3003 struct ath9k_hw_capabilities *pCap = &ah->caps;
3004 struct ath_common *common = ath9k_hw_common(ah);
3005
3006 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3007
3008 REG_WRITE(ah, AR_BEACON_PERIOD,
3009 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3010 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3011 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3012
3013 REG_RMW_FIELD(ah, AR_RSSI_THR,
3014 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3015
3016 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3017
3018 if (bs->bs_sleepduration > beaconintval)
3019 beaconintval = bs->bs_sleepduration;
3020
3021 dtimperiod = bs->bs_dtimperiod;
3022 if (bs->bs_sleepduration > dtimperiod)
3023 dtimperiod = bs->bs_sleepduration;
3024
3025 if (beaconintval == dtimperiod)
3026 nextTbtt = bs->bs_nextdtim;
3027 else
3028 nextTbtt = bs->bs_nexttbtt;
3029
3030 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3031 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3032 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3033 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3034
3035 REG_WRITE(ah, AR_NEXT_DTIM,
3036 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3037 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3038
3039 REG_WRITE(ah, AR_SLEEP1,
3040 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3041 | AR_SLEEP1_ASSUME_DTIM);
3042
3043 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3044 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3045 else
3046 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3047
3048 REG_WRITE(ah, AR_SLEEP2,
3049 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3050
3051 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3052 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3053
3054 REG_SET_BIT(ah, AR_TIMER_MODE,
3055 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3056 AR_DTIM_TIMER_EN);
3057
3058 /* TSF Out of Range Threshold */
3059 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3060 }
3061 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3062
3063 /*******************/
3064 /* HW Capabilities */
3065 /*******************/
3066
3067 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3068 {
3069 struct ath9k_hw_capabilities *pCap = &ah->caps;
3070 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3071 struct ath_common *common = ath9k_hw_common(ah);
3072 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3073
3074 u16 capField = 0, eeval;
3075
3076 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3077 regulatory->current_rd = eeval;
3078
3079 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3080 if (AR_SREV_9285_10_OR_LATER(ah))
3081 eeval |= AR9285_RDEXT_DEFAULT;
3082 regulatory->current_rd_ext = eeval;
3083
3084 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3085
3086 if (ah->opmode != NL80211_IFTYPE_AP &&
3087 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3088 if (regulatory->current_rd == 0x64 ||
3089 regulatory->current_rd == 0x65)
3090 regulatory->current_rd += 5;
3091 else if (regulatory->current_rd == 0x41)
3092 regulatory->current_rd = 0x43;
3093 ath_print(common, ATH_DBG_REGULATORY,
3094 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3095 }
3096
3097 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3098 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3099 ath_print(common, ATH_DBG_FATAL,
3100 "no band has been marked as supported in EEPROM.\n");
3101 return -EINVAL;
3102 }
3103
3104 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3105
3106 if (eeval & AR5416_OPFLAGS_11A) {
3107 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3108 if (ah->config.ht_enable) {
3109 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3110 set_bit(ATH9K_MODE_11NA_HT20,
3111 pCap->wireless_modes);
3112 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3113 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3114 pCap->wireless_modes);
3115 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3116 pCap->wireless_modes);
3117 }
3118 }
3119 }
3120
3121 if (eeval & AR5416_OPFLAGS_11G) {
3122 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3123 if (ah->config.ht_enable) {
3124 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3125 set_bit(ATH9K_MODE_11NG_HT20,
3126 pCap->wireless_modes);
3127 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3128 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3129 pCap->wireless_modes);
3130 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3131 pCap->wireless_modes);
3132 }
3133 }
3134 }
3135
3136 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3137 /*
3138 * For AR9271 we will temporarilly uses the rx chainmax as read from
3139 * the EEPROM.
3140 */
3141 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3142 !(eeval & AR5416_OPFLAGS_11A) &&
3143 !(AR_SREV_9271(ah)))
3144 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3145 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3146 else
3147 /* Use rx_chainmask from EEPROM. */
3148 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3149
3150 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3151 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3152
3153 pCap->low_2ghz_chan = 2312;
3154 pCap->high_2ghz_chan = 2732;
3155
3156 pCap->low_5ghz_chan = 4920;
3157 pCap->high_5ghz_chan = 6100;
3158
3159 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3160 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3161 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3162
3163 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3164 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3165 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3166
3167 if (ah->config.ht_enable)
3168 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3169 else
3170 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3171
3172 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3173 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3174 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3175 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3176
3177 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3178 pCap->total_queues =
3179 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3180 else
3181 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3182
3183 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3184 pCap->keycache_size =
3185 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3186 else
3187 pCap->keycache_size = AR_KEYTABLE_SIZE;
3188
3189 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3190
3191 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3192 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3193 else
3194 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3195
3196 if (AR_SREV_9285_10_OR_LATER(ah))
3197 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3198 else if (AR_SREV_9280_10_OR_LATER(ah))
3199 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3200 else
3201 pCap->num_gpio_pins = AR_NUM_GPIO;
3202
3203 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3204 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3205 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3206 } else {
3207 pCap->rts_aggr_limit = (8 * 1024);
3208 }
3209
3210 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3211
3212 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3213 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3214 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3215 ah->rfkill_gpio =
3216 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3217 ah->rfkill_polarity =
3218 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3219
3220 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3221 }
3222 #endif
3223
3224 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3225
3226 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3227 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3228 else
3229 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3230
3231 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3232 pCap->reg_cap =
3233 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3234 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3235 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3236 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3237 } else {
3238 pCap->reg_cap =
3239 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3240 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3241 }
3242
3243 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3244 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3245 AR_SREV_5416(ah))
3246 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3247
3248 pCap->num_antcfg_5ghz =
3249 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3250 pCap->num_antcfg_2ghz =
3251 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3252
3253 if (AR_SREV_9280_10_OR_LATER(ah) &&
3254 ath9k_hw_btcoex_supported(ah)) {
3255 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3256 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3257
3258 if (AR_SREV_9285(ah)) {
3259 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3260 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3261 } else {
3262 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3263 }
3264 } else {
3265 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3266 }
3267
3268 return 0;
3269 }
3270
3271 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3272 u32 capability, u32 *result)
3273 {
3274 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3275 switch (type) {
3276 case ATH9K_CAP_CIPHER:
3277 switch (capability) {
3278 case ATH9K_CIPHER_AES_CCM:
3279 case ATH9K_CIPHER_AES_OCB:
3280 case ATH9K_CIPHER_TKIP:
3281 case ATH9K_CIPHER_WEP:
3282 case ATH9K_CIPHER_MIC:
3283 case ATH9K_CIPHER_CLR:
3284 return true;
3285 default:
3286 return false;
3287 }
3288 case ATH9K_CAP_TKIP_MIC:
3289 switch (capability) {
3290 case 0:
3291 return true;
3292 case 1:
3293 return (ah->sta_id1_defaults &
3294 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3295 false;
3296 }
3297 case ATH9K_CAP_TKIP_SPLIT:
3298 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3299 false : true;
3300 case ATH9K_CAP_DIVERSITY:
3301 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3302 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3303 true : false;
3304 case ATH9K_CAP_MCAST_KEYSRCH:
3305 switch (capability) {
3306 case 0:
3307 return true;
3308 case 1:
3309 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3310 return false;
3311 } else {
3312 return (ah->sta_id1_defaults &
3313 AR_STA_ID1_MCAST_KSRCH) ? true :
3314 false;
3315 }
3316 }
3317 return false;
3318 case ATH9K_CAP_TXPOW:
3319 switch (capability) {
3320 case 0:
3321 return 0;
3322 case 1:
3323 *result = regulatory->power_limit;
3324 return 0;
3325 case 2:
3326 *result = regulatory->max_power_level;
3327 return 0;
3328 case 3:
3329 *result = regulatory->tp_scale;
3330 return 0;
3331 }
3332 return false;
3333 case ATH9K_CAP_DS:
3334 return (AR_SREV_9280_20_OR_LATER(ah) &&
3335 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3336 ? false : true;
3337 default:
3338 return false;
3339 }
3340 }
3341 EXPORT_SYMBOL(ath9k_hw_getcapability);
3342
3343 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3344 u32 capability, u32 setting, int *status)
3345 {
3346 u32 v;
3347
3348 switch (type) {
3349 case ATH9K_CAP_TKIP_MIC:
3350 if (setting)
3351 ah->sta_id1_defaults |=
3352 AR_STA_ID1_CRPT_MIC_ENABLE;
3353 else
3354 ah->sta_id1_defaults &=
3355 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3356 return true;
3357 case ATH9K_CAP_DIVERSITY:
3358 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3359 if (setting)
3360 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3361 else
3362 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3363 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3364 return true;
3365 case ATH9K_CAP_MCAST_KEYSRCH:
3366 if (setting)
3367 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3368 else
3369 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3370 return true;
3371 default:
3372 return false;
3373 }
3374 }
3375 EXPORT_SYMBOL(ath9k_hw_setcapability);
3376
3377 /****************************/
3378 /* GPIO / RFKILL / Antennae */
3379 /****************************/
3380
3381 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3382 u32 gpio, u32 type)
3383 {
3384 int addr;
3385 u32 gpio_shift, tmp;
3386
3387 if (gpio > 11)
3388 addr = AR_GPIO_OUTPUT_MUX3;
3389 else if (gpio > 5)
3390 addr = AR_GPIO_OUTPUT_MUX2;
3391 else
3392 addr = AR_GPIO_OUTPUT_MUX1;
3393
3394 gpio_shift = (gpio % 6) * 5;
3395
3396 if (AR_SREV_9280_20_OR_LATER(ah)
3397 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3398 REG_RMW(ah, addr, (type << gpio_shift),
3399 (0x1f << gpio_shift));
3400 } else {
3401 tmp = REG_READ(ah, addr);
3402 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3403 tmp &= ~(0x1f << gpio_shift);
3404 tmp |= (type << gpio_shift);
3405 REG_WRITE(ah, addr, tmp);
3406 }
3407 }
3408
3409 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3410 {
3411 u32 gpio_shift;
3412
3413 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3414
3415 gpio_shift = gpio << 1;
3416
3417 REG_RMW(ah,
3418 AR_GPIO_OE_OUT,
3419 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3420 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3421 }
3422 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3423
3424 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3425 {
3426 #define MS_REG_READ(x, y) \
3427 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3428
3429 if (gpio >= ah->caps.num_gpio_pins)
3430 return 0xffffffff;
3431
3432 if (AR_SREV_9287_10_OR_LATER(ah))
3433 return MS_REG_READ(AR9287, gpio) != 0;
3434 else if (AR_SREV_9285_10_OR_LATER(ah))
3435 return MS_REG_READ(AR9285, gpio) != 0;
3436 else if (AR_SREV_9280_10_OR_LATER(ah))
3437 return MS_REG_READ(AR928X, gpio) != 0;
3438 else
3439 return MS_REG_READ(AR, gpio) != 0;
3440 }
3441 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3442
3443 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3444 u32 ah_signal_type)
3445 {
3446 u32 gpio_shift;
3447
3448 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3449
3450 gpio_shift = 2 * gpio;
3451
3452 REG_RMW(ah,
3453 AR_GPIO_OE_OUT,
3454 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3455 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3456 }
3457 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3458
3459 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3460 {
3461 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3462 AR_GPIO_BIT(gpio));
3463 }
3464 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3465
3466 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3467 {
3468 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3469 }
3470 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3471
3472 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3473 {
3474 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3475 }
3476 EXPORT_SYMBOL(ath9k_hw_setantenna);
3477
3478 /*********************/
3479 /* General Operation */
3480 /*********************/
3481
3482 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3483 {
3484 u32 bits = REG_READ(ah, AR_RX_FILTER);
3485 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3486
3487 if (phybits & AR_PHY_ERR_RADAR)
3488 bits |= ATH9K_RX_FILTER_PHYRADAR;
3489 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3490 bits |= ATH9K_RX_FILTER_PHYERR;
3491
3492 return bits;
3493 }
3494 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3495
3496 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3497 {
3498 u32 phybits;
3499
3500 REG_WRITE(ah, AR_RX_FILTER, bits);
3501
3502 phybits = 0;
3503 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3504 phybits |= AR_PHY_ERR_RADAR;
3505 if (bits & ATH9K_RX_FILTER_PHYERR)
3506 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3507 REG_WRITE(ah, AR_PHY_ERR, phybits);
3508
3509 if (phybits)
3510 REG_WRITE(ah, AR_RXCFG,
3511 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3512 else
3513 REG_WRITE(ah, AR_RXCFG,
3514 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3515 }
3516 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3517
3518 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3519 {
3520 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3521 return false;
3522
3523 ath9k_hw_init_pll(ah, NULL);
3524 return true;
3525 }
3526 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3527
3528 bool ath9k_hw_disable(struct ath_hw *ah)
3529 {
3530 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3531 return false;
3532
3533 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3534 return false;
3535
3536 ath9k_hw_init_pll(ah, NULL);
3537 return true;
3538 }
3539 EXPORT_SYMBOL(ath9k_hw_disable);
3540
3541 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3542 {
3543 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3544 struct ath9k_channel *chan = ah->curchan;
3545 struct ieee80211_channel *channel = chan->chan;
3546
3547 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3548
3549 ah->eep_ops->set_txpower(ah, chan,
3550 ath9k_regd_get_ctl(regulatory, chan),
3551 channel->max_antenna_gain * 2,
3552 channel->max_power * 2,
3553 min((u32) MAX_RATE_POWER,
3554 (u32) regulatory->power_limit));
3555 }
3556 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3557
3558 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3559 {
3560 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3561 }
3562 EXPORT_SYMBOL(ath9k_hw_setmac);
3563
3564 void ath9k_hw_setopmode(struct ath_hw *ah)
3565 {
3566 ath9k_hw_set_operating_mode(ah, ah->opmode);
3567 }
3568 EXPORT_SYMBOL(ath9k_hw_setopmode);
3569
3570 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3571 {
3572 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3573 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3574 }
3575 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3576
3577 void ath9k_hw_write_associd(struct ath_hw *ah)
3578 {
3579 struct ath_common *common = ath9k_hw_common(ah);
3580
3581 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3582 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3583 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3584 }
3585 EXPORT_SYMBOL(ath9k_hw_write_associd);
3586
3587 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3588 {
3589 u64 tsf;
3590
3591 tsf = REG_READ(ah, AR_TSF_U32);
3592 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3593
3594 return tsf;
3595 }
3596 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3597
3598 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3599 {
3600 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3601 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3602 }
3603 EXPORT_SYMBOL(ath9k_hw_settsf64);
3604
3605 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3606 {
3607 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3608 AH_TSF_WRITE_TIMEOUT))
3609 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3610 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3611
3612 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3613 }
3614 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3615
3616 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3617 {
3618 if (setting)
3619 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3620 else
3621 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3622 }
3623 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3624
3625 /*
3626 * Extend 15-bit time stamp from rx descriptor to
3627 * a full 64-bit TSF using the current h/w TSF.
3628 */
3629 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3630 {
3631 u64 tsf;
3632
3633 tsf = ath9k_hw_gettsf64(ah);
3634 if ((tsf & 0x7fff) < rstamp)
3635 tsf -= 0x8000;
3636 return (tsf & ~0x7fff) | rstamp;
3637 }
3638 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3639
3640 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3641 {
3642 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3643 u32 macmode;
3644
3645 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3646 macmode = AR_2040_JOINED_RX_CLEAR;
3647 else
3648 macmode = 0;
3649
3650 REG_WRITE(ah, AR_2040_MODE, macmode);
3651 }
3652
3653 /* HW Generic timers configuration */
3654
3655 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3656 {
3657 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3658 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3659 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3660 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3661 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3662 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3663 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3664 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3665 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3666 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3667 AR_NDP2_TIMER_MODE, 0x0002},
3668 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3669 AR_NDP2_TIMER_MODE, 0x0004},
3670 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3671 AR_NDP2_TIMER_MODE, 0x0008},
3672 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3673 AR_NDP2_TIMER_MODE, 0x0010},
3674 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3675 AR_NDP2_TIMER_MODE, 0x0020},
3676 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3677 AR_NDP2_TIMER_MODE, 0x0040},
3678 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3679 AR_NDP2_TIMER_MODE, 0x0080}
3680 };
3681
3682 /* HW generic timer primitives */
3683
3684 /* compute and clear index of rightmost 1 */
3685 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3686 {
3687 u32 b;
3688
3689 b = *mask;
3690 b &= (0-b);
3691 *mask &= ~b;
3692 b *= debruijn32;
3693 b >>= 27;
3694
3695 return timer_table->gen_timer_index[b];
3696 }
3697
3698 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3699 {
3700 return REG_READ(ah, AR_TSF_L32);
3701 }
3702 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3703
3704 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3705 void (*trigger)(void *),
3706 void (*overflow)(void *),
3707 void *arg,
3708 u8 timer_index)
3709 {
3710 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3711 struct ath_gen_timer *timer;
3712
3713 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3714
3715 if (timer == NULL) {
3716 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3717 "Failed to allocate memory"
3718 "for hw timer[%d]\n", timer_index);
3719 return NULL;
3720 }
3721
3722 /* allocate a hardware generic timer slot */
3723 timer_table->timers[timer_index] = timer;
3724 timer->index = timer_index;
3725 timer->trigger = trigger;
3726 timer->overflow = overflow;
3727 timer->arg = arg;
3728
3729 return timer;
3730 }
3731 EXPORT_SYMBOL(ath_gen_timer_alloc);
3732
3733 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3734 struct ath_gen_timer *timer,
3735 u32 timer_next,
3736 u32 timer_period)
3737 {
3738 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3739 u32 tsf;
3740
3741 BUG_ON(!timer_period);
3742
3743 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3744
3745 tsf = ath9k_hw_gettsf32(ah);
3746
3747 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3748 "curent tsf %x period %x"
3749 "timer_next %x\n", tsf, timer_period, timer_next);
3750
3751 /*
3752 * Pull timer_next forward if the current TSF already passed it
3753 * because of software latency
3754 */
3755 if (timer_next < tsf)
3756 timer_next = tsf + timer_period;
3757
3758 /*
3759 * Program generic timer registers
3760 */
3761 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3762 timer_next);
3763 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3764 timer_period);
3765 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3766 gen_tmr_configuration[timer->index].mode_mask);
3767
3768 /* Enable both trigger and thresh interrupt masks */
3769 REG_SET_BIT(ah, AR_IMR_S5,
3770 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3771 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3772 }
3773 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3774
3775 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3776 {
3777 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3778
3779 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3780 (timer->index >= ATH_MAX_GEN_TIMER)) {
3781 return;
3782 }
3783
3784 /* Clear generic timer enable bits. */
3785 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3786 gen_tmr_configuration[timer->index].mode_mask);
3787
3788 /* Disable both trigger and thresh interrupt masks */
3789 REG_CLR_BIT(ah, AR_IMR_S5,
3790 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3791 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3792
3793 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3794 }
3795 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3796
3797 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3798 {
3799 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3800
3801 /* free the hardware generic timer slot */
3802 timer_table->timers[timer->index] = NULL;
3803 kfree(timer);
3804 }
3805 EXPORT_SYMBOL(ath_gen_timer_free);
3806
3807 /*
3808 * Generic Timer Interrupts handling
3809 */
3810 void ath_gen_timer_isr(struct ath_hw *ah)
3811 {
3812 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3813 struct ath_gen_timer *timer;
3814 struct ath_common *common = ath9k_hw_common(ah);
3815 u32 trigger_mask, thresh_mask, index;
3816
3817 /* get hardware generic timer interrupt status */
3818 trigger_mask = ah->intr_gen_timer_trigger;
3819 thresh_mask = ah->intr_gen_timer_thresh;
3820 trigger_mask &= timer_table->timer_mask.val;
3821 thresh_mask &= timer_table->timer_mask.val;
3822
3823 trigger_mask &= ~thresh_mask;
3824
3825 while (thresh_mask) {
3826 index = rightmost_index(timer_table, &thresh_mask);
3827 timer = timer_table->timers[index];
3828 BUG_ON(!timer);
3829 ath_print(common, ATH_DBG_HWTIMER,
3830 "TSF overflow for Gen timer %d\n", index);
3831 timer->overflow(timer->arg);
3832 }
3833
3834 while (trigger_mask) {
3835 index = rightmost_index(timer_table, &trigger_mask);
3836 timer = timer_table->timers[index];
3837 BUG_ON(!timer);
3838 ath_print(common, ATH_DBG_HWTIMER,
3839 "Gen timer[%d] trigger\n", index);
3840 timer->trigger(timer->arg);
3841 }
3842 }
3843 EXPORT_SYMBOL(ath_gen_timer_isr);
3844
3845 static struct {
3846 u32 version;
3847 const char * name;
3848 } ath_mac_bb_names[] = {
3849 /* Devices with external radios */
3850 { AR_SREV_VERSION_5416_PCI, "5416" },
3851 { AR_SREV_VERSION_5416_PCIE, "5418" },
3852 { AR_SREV_VERSION_9100, "9100" },
3853 { AR_SREV_VERSION_9160, "9160" },
3854 /* Single-chip solutions */
3855 { AR_SREV_VERSION_9280, "9280" },
3856 { AR_SREV_VERSION_9285, "9285" },
3857 { AR_SREV_VERSION_9287, "9287" },
3858 { AR_SREV_VERSION_9271, "9271" },
3859 };
3860
3861 /* For devices with external radios */
3862 static struct {
3863 u16 version;
3864 const char * name;
3865 } ath_rf_names[] = {
3866 { 0, "5133" },
3867 { AR_RAD5133_SREV_MAJOR, "5133" },
3868 { AR_RAD5122_SREV_MAJOR, "5122" },
3869 { AR_RAD2133_SREV_MAJOR, "2133" },
3870 { AR_RAD2122_SREV_MAJOR, "2122" }
3871 };
3872
3873 /*
3874 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3875 */
3876 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3877 {
3878 int i;
3879
3880 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3881 if (ath_mac_bb_names[i].version == mac_bb_version) {
3882 return ath_mac_bb_names[i].name;
3883 }
3884 }
3885
3886 return "????";
3887 }
3888
3889 /*
3890 * Return the RF name. "????" is returned if the RF is unknown.
3891 * Used for devices with external radios.
3892 */
3893 static const char *ath9k_hw_rf_name(u16 rf_version)
3894 {
3895 int i;
3896
3897 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3898 if (ath_rf_names[i].version == rf_version) {
3899 return ath_rf_names[i].name;
3900 }
3901 }
3902
3903 return "????";
3904 }
3905
3906 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3907 {
3908 int used;
3909
3910 /* chipsets >= AR9280 are single-chip */
3911 if (AR_SREV_9280_10_OR_LATER(ah)) {
3912 used = snprintf(hw_name, len,
3913 "Atheros AR%s Rev:%x",
3914 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3915 ah->hw_version.macRev);
3916 }
3917 else {
3918 used = snprintf(hw_name, len,
3919 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3920 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3921 ah->hw_version.macRev,
3922 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3923 AR_RADIO_SREV_MAJOR)),
3924 ah->hw_version.phyRev);
3925 }
3926
3927 hw_name[used] = '\0';
3928 }
3929 EXPORT_SYMBOL(ath9k_hw_name);
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