2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
29 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
30 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
31 struct ar5416_eeprom_def
*pEepData
,
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
39 static int __init
ath9k_init(void)
43 module_init(ath9k_init
);
45 static void __exit
ath9k_exit(void)
49 module_exit(ath9k_exit
);
51 /********************/
52 /* Helper Functions */
53 /********************/
55 static u32
ath9k_hw_mac_usec(struct ath_hw
*ah
, u32 clks
)
57 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
59 if (!ah
->curchan
) /* should really check for CCK instead */
60 return clks
/ ATH9K_CLOCK_RATE_CCK
;
61 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
62 return clks
/ ATH9K_CLOCK_RATE_2GHZ_OFDM
;
64 return clks
/ ATH9K_CLOCK_RATE_5GHZ_OFDM
;
67 static u32
ath9k_hw_mac_to_usec(struct ath_hw
*ah
, u32 clks
)
69 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
71 if (conf_is_ht40(conf
))
72 return ath9k_hw_mac_usec(ah
, clks
) / 2;
74 return ath9k_hw_mac_usec(ah
, clks
);
77 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
79 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
81 if (!ah
->curchan
) /* should really check for CCK instead */
82 return usecs
*ATH9K_CLOCK_RATE_CCK
;
83 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
84 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
85 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
88 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
90 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
92 if (conf_is_ht40(conf
))
93 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
95 return ath9k_hw_mac_clks(ah
, usecs
);
98 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
102 BUG_ON(timeout
< AH_TIME_QUANTUM
);
104 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
105 if ((REG_READ(ah
, reg
) & mask
) == val
)
108 udelay(AH_TIME_QUANTUM
);
111 ath_print(ath9k_hw_common(ah
), ATH_DBG_ANY
,
112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
113 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
117 EXPORT_SYMBOL(ath9k_hw_wait
);
119 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
124 for (i
= 0, retval
= 0; i
< n
; i
++) {
125 retval
= (retval
<< 1) | (val
& 1);
131 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
135 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
137 if (flags
& CHANNEL_5GHZ
) {
138 *low
= pCap
->low_5ghz_chan
;
139 *high
= pCap
->high_5ghz_chan
;
142 if ((flags
& CHANNEL_2GHZ
)) {
143 *low
= pCap
->low_2ghz_chan
;
144 *high
= pCap
->high_2ghz_chan
;
150 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
152 u32 frameLen
, u16 rateix
,
155 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
161 case WLAN_RC_PHY_CCK
:
162 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
165 numBits
= frameLen
<< 3;
166 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
168 case WLAN_RC_PHY_OFDM
:
169 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
170 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
171 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
172 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
173 txTime
= OFDM_SIFS_TIME_QUARTER
174 + OFDM_PREAMBLE_TIME_QUARTER
175 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
176 } else if (ah
->curchan
&&
177 IS_CHAN_HALF_RATE(ah
->curchan
)) {
178 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
179 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
180 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
181 txTime
= OFDM_SIFS_TIME_HALF
+
182 OFDM_PREAMBLE_TIME_HALF
183 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
185 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
186 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
187 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
188 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
189 + (numSymbols
* OFDM_SYMBOL_TIME
);
193 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
194 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
201 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
203 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
204 struct ath9k_channel
*chan
,
205 struct chan_centers
*centers
)
209 if (!IS_CHAN_HT40(chan
)) {
210 centers
->ctl_center
= centers
->ext_center
=
211 centers
->synth_center
= chan
->channel
;
215 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
216 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
217 centers
->synth_center
=
218 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
221 centers
->synth_center
=
222 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
226 centers
->ctl_center
=
227 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
228 /* 25 MHz spacing is supported by hw but not on upper layers */
229 centers
->ext_center
=
230 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
237 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
241 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
244 val
= REG_READ(ah
, AR_SREV
);
245 ah
->hw_version
.macVersion
=
246 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
247 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
248 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
250 if (!AR_SREV_9100(ah
))
251 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
253 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
255 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
256 ah
->is_pciexpress
= true;
260 static int ath9k_hw_get_radiorev(struct ath_hw
*ah
)
265 REG_WRITE(ah
, AR_PHY(0x36), 0x00007058);
267 for (i
= 0; i
< 8; i
++)
268 REG_WRITE(ah
, AR_PHY(0x20), 0x00010000);
269 val
= (REG_READ(ah
, AR_PHY(256)) >> 24) & 0xff;
270 val
= ((val
& 0xf0) >> 4) | ((val
& 0x0f) << 4);
272 return ath9k_hw_reverse_bits(val
, 8);
275 /************************************/
276 /* HW Attach, Detach, Init Routines */
277 /************************************/
279 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
281 if (AR_SREV_9100(ah
))
284 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
285 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
286 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
287 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
288 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
289 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
290 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
291 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
292 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
294 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
297 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
299 struct ath_common
*common
= ath9k_hw_common(ah
);
300 u32 regAddr
[2] = { AR_STA_ID0
, AR_PHY_BASE
+ (8 << 2) };
302 u32 patternData
[4] = { 0x55555555,
308 for (i
= 0; i
< 2; i
++) {
309 u32 addr
= regAddr
[i
];
312 regHold
[i
] = REG_READ(ah
, addr
);
313 for (j
= 0; j
< 0x100; j
++) {
314 wrData
= (j
<< 16) | j
;
315 REG_WRITE(ah
, addr
, wrData
);
316 rdData
= REG_READ(ah
, addr
);
317 if (rdData
!= wrData
) {
318 ath_print(common
, ATH_DBG_FATAL
,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != "
322 addr
, wrData
, rdData
);
326 for (j
= 0; j
< 4; j
++) {
327 wrData
= patternData
[j
];
328 REG_WRITE(ah
, addr
, wrData
);
329 rdData
= REG_READ(ah
, addr
);
330 if (wrData
!= rdData
) {
331 ath_print(common
, ATH_DBG_FATAL
,
332 "address test failed "
333 "addr: 0x%08x - wr:0x%08x != "
335 addr
, wrData
, rdData
);
339 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
346 static const char *ath9k_hw_devname(u16 devid
)
349 case AR5416_DEVID_PCI
:
350 return "Atheros 5416";
351 case AR5416_DEVID_PCIE
:
352 return "Atheros 5418";
353 case AR9160_DEVID_PCI
:
354 return "Atheros 9160";
355 case AR5416_AR9100_DEVID
:
356 return "Atheros 9100";
357 case AR9280_DEVID_PCI
:
358 case AR9280_DEVID_PCIE
:
359 return "Atheros 9280";
360 case AR9285_DEVID_PCIE
:
361 return "Atheros 9285";
362 case AR5416_DEVID_AR9287_PCI
:
363 case AR5416_DEVID_AR9287_PCIE
:
364 return "Atheros 9287";
370 static void ath9k_hw_init_config(struct ath_hw
*ah
)
374 ah
->config
.dma_beacon_response_time
= 2;
375 ah
->config
.sw_beacon_response_time
= 10;
376 ah
->config
.additional_swba_backoff
= 0;
377 ah
->config
.ack_6mb
= 0x0;
378 ah
->config
.cwm_ignore_extcca
= 0;
379 ah
->config
.pcie_powersave_enable
= 0;
380 ah
->config
.pcie_clock_req
= 0;
381 ah
->config
.pcie_waen
= 0;
382 ah
->config
.analog_shiftreg
= 1;
383 ah
->config
.ht_enable
= 1;
384 ah
->config
.ofdm_trig_low
= 200;
385 ah
->config
.ofdm_trig_high
= 500;
386 ah
->config
.cck_trig_high
= 200;
387 ah
->config
.cck_trig_low
= 100;
388 ah
->config
.enable_ani
= 1;
390 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
391 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
392 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
395 ah
->config
.intr_mitigation
= true;
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
413 if (num_possible_cpus() > 1)
414 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
416 EXPORT_SYMBOL(ath9k_hw_init
);
418 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
420 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
422 regulatory
->country_code
= CTRY_DEFAULT
;
423 regulatory
->power_limit
= MAX_RATE_POWER
;
424 regulatory
->tp_scale
= ATH9K_TP_SCALE_MAX
;
426 ah
->hw_version
.magic
= AR5416_MAGIC
;
427 ah
->hw_version
.subvendorid
= 0;
430 if (ah
->hw_version
.devid
== AR5416_AR9100_DEVID
)
431 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
432 if (!AR_SREV_9100(ah
))
433 ah
->ah_flags
= AH_USE_EEPROM
;
436 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
437 ah
->beacon_interval
= 100;
438 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
439 ah
->slottime
= (u32
) -1;
440 ah
->acktimeout
= (u32
) -1;
441 ah
->ctstimeout
= (u32
) -1;
442 ah
->globaltxtimeout
= (u32
) -1;
443 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
446 static int ath9k_hw_rf_claim(struct ath_hw
*ah
)
450 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
452 val
= ath9k_hw_get_radiorev(ah
);
453 switch (val
& AR_RADIO_SREV_MAJOR
) {
455 val
= AR_RAD5133_SREV_MAJOR
;
457 case AR_RAD5133_SREV_MAJOR
:
458 case AR_RAD5122_SREV_MAJOR
:
459 case AR_RAD2133_SREV_MAJOR
:
460 case AR_RAD2122_SREV_MAJOR
:
463 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
464 "Radio Chip Rev 0x%02X not supported\n",
465 val
& AR_RADIO_SREV_MAJOR
);
469 ah
->hw_version
.analog5GhzRev
= val
;
474 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
476 struct ath_common
*common
= ath9k_hw_common(ah
);
482 for (i
= 0; i
< 3; i
++) {
483 eeval
= ah
->eep_ops
->get_eeprom(ah
, AR_EEPROM_MAC(i
));
485 common
->macaddr
[2 * i
] = eeval
>> 8;
486 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
488 if (sum
== 0 || sum
== 0xffff * 3)
489 return -EADDRNOTAVAIL
;
494 static void ath9k_hw_init_rxgain_ini(struct ath_hw
*ah
)
498 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_17
) {
499 rxgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_RXGAIN_TYPE
);
501 if (rxgain_type
== AR5416_EEP_RXGAIN_13DB_BACKOFF
)
502 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
503 ar9280Modes_backoff_13db_rxgain_9280_2
,
504 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2
), 6);
505 else if (rxgain_type
== AR5416_EEP_RXGAIN_23DB_BACKOFF
)
506 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
507 ar9280Modes_backoff_23db_rxgain_9280_2
,
508 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2
), 6);
510 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
511 ar9280Modes_original_rxgain_9280_2
,
512 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
514 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
515 ar9280Modes_original_rxgain_9280_2
,
516 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
520 static void ath9k_hw_init_txgain_ini(struct ath_hw
*ah
)
524 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_19
) {
525 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
527 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
)
528 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
529 ar9280Modes_high_power_tx_gain_9280_2
,
530 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2
), 6);
532 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
533 ar9280Modes_original_tx_gain_9280_2
,
534 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
536 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
537 ar9280Modes_original_tx_gain_9280_2
,
538 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
542 static int ath9k_hw_post_init(struct ath_hw
*ah
)
546 if (!ath9k_hw_chip_test(ah
))
549 ecode
= ath9k_hw_rf_claim(ah
);
553 ecode
= ath9k_hw_eeprom_init(ah
);
557 ath_print(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
558 "Eeprom VER: %d, REV: %d\n",
559 ah
->eep_ops
->get_eeprom_ver(ah
),
560 ah
->eep_ops
->get_eeprom_rev(ah
));
562 if (!AR_SREV_9280_10_OR_LATER(ah
)) {
563 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
565 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
566 "Failed allocating banks for "
572 if (!AR_SREV_9100(ah
)) {
573 ath9k_hw_ani_setup(ah
);
574 ath9k_hw_ani_init(ah
);
580 static bool ath9k_hw_devid_supported(u16 devid
)
583 case AR5416_DEVID_PCI
:
584 case AR5416_DEVID_PCIE
:
585 case AR5416_AR9100_DEVID
:
586 case AR9160_DEVID_PCI
:
587 case AR9280_DEVID_PCI
:
588 case AR9280_DEVID_PCIE
:
589 case AR9285_DEVID_PCIE
:
590 case AR5416_DEVID_AR9287_PCI
:
591 case AR5416_DEVID_AR9287_PCIE
:
600 static bool ath9k_hw_macversion_supported(u32 macversion
)
602 switch (macversion
) {
603 case AR_SREV_VERSION_5416_PCI
:
604 case AR_SREV_VERSION_5416_PCIE
:
605 case AR_SREV_VERSION_9160
:
606 case AR_SREV_VERSION_9100
:
607 case AR_SREV_VERSION_9280
:
608 case AR_SREV_VERSION_9285
:
609 case AR_SREV_VERSION_9287
:
610 case AR_SREV_VERSION_9271
:
618 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
620 if (AR_SREV_9160_10_OR_LATER(ah
)) {
621 if (AR_SREV_9280_10_OR_LATER(ah
)) {
622 ah
->iq_caldata
.calData
= &iq_cal_single_sample
;
623 ah
->adcgain_caldata
.calData
=
624 &adc_gain_cal_single_sample
;
625 ah
->adcdc_caldata
.calData
=
626 &adc_dc_cal_single_sample
;
627 ah
->adcdc_calinitdata
.calData
=
630 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
631 ah
->adcgain_caldata
.calData
=
632 &adc_gain_cal_multi_sample
;
633 ah
->adcdc_caldata
.calData
=
634 &adc_dc_cal_multi_sample
;
635 ah
->adcdc_calinitdata
.calData
=
638 ah
->supp_cals
= ADC_GAIN_CAL
| ADC_DC_CAL
| IQ_MISMATCH_CAL
;
642 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
644 if (AR_SREV_9271(ah
)) {
645 INIT_INI_ARRAY(&ah
->iniModes
, ar9271Modes_9271
,
646 ARRAY_SIZE(ar9271Modes_9271
), 6);
647 INIT_INI_ARRAY(&ah
->iniCommon
, ar9271Common_9271
,
648 ARRAY_SIZE(ar9271Common_9271
), 2);
649 INIT_INI_ARRAY(&ah
->iniModes_9271_1_0_only
,
650 ar9271Modes_9271_1_0_only
,
651 ARRAY_SIZE(ar9271Modes_9271_1_0_only
), 6);
655 if (AR_SREV_9287_11_OR_LATER(ah
)) {
656 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_1
,
657 ARRAY_SIZE(ar9287Modes_9287_1_1
), 6);
658 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_1
,
659 ARRAY_SIZE(ar9287Common_9287_1_1
), 2);
660 if (ah
->config
.pcie_clock_req
)
661 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
662 ar9287PciePhy_clkreq_off_L1_9287_1_1
,
663 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1
), 2);
665 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
666 ar9287PciePhy_clkreq_always_on_L1_9287_1_1
,
667 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1
),
669 } else if (AR_SREV_9287_10_OR_LATER(ah
)) {
670 INIT_INI_ARRAY(&ah
->iniModes
, ar9287Modes_9287_1_0
,
671 ARRAY_SIZE(ar9287Modes_9287_1_0
), 6);
672 INIT_INI_ARRAY(&ah
->iniCommon
, ar9287Common_9287_1_0
,
673 ARRAY_SIZE(ar9287Common_9287_1_0
), 2);
675 if (ah
->config
.pcie_clock_req
)
676 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
677 ar9287PciePhy_clkreq_off_L1_9287_1_0
,
678 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0
), 2);
680 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
681 ar9287PciePhy_clkreq_always_on_L1_9287_1_0
,
682 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0
),
684 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
687 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285_1_2
,
688 ARRAY_SIZE(ar9285Modes_9285_1_2
), 6);
689 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285_1_2
,
690 ARRAY_SIZE(ar9285Common_9285_1_2
), 2);
692 if (ah
->config
.pcie_clock_req
) {
693 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
694 ar9285PciePhy_clkreq_off_L1_9285_1_2
,
695 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2
), 2);
697 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
698 ar9285PciePhy_clkreq_always_on_L1_9285_1_2
,
699 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2
),
702 } else if (AR_SREV_9285_10_OR_LATER(ah
)) {
703 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285
,
704 ARRAY_SIZE(ar9285Modes_9285
), 6);
705 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285
,
706 ARRAY_SIZE(ar9285Common_9285
), 2);
708 if (ah
->config
.pcie_clock_req
) {
709 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
710 ar9285PciePhy_clkreq_off_L1_9285
,
711 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285
), 2);
713 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
714 ar9285PciePhy_clkreq_always_on_L1_9285
,
715 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285
), 2);
717 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
718 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280_2
,
719 ARRAY_SIZE(ar9280Modes_9280_2
), 6);
720 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280_2
,
721 ARRAY_SIZE(ar9280Common_9280_2
), 2);
723 if (ah
->config
.pcie_clock_req
) {
724 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
725 ar9280PciePhy_clkreq_off_L1_9280
,
726 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280
),2);
728 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
729 ar9280PciePhy_clkreq_always_on_L1_9280
,
730 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280
), 2);
732 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
733 ar9280Modes_fast_clock_9280_2
,
734 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2
), 3);
735 } else if (AR_SREV_9280_10_OR_LATER(ah
)) {
736 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280
,
737 ARRAY_SIZE(ar9280Modes_9280
), 6);
738 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280
,
739 ARRAY_SIZE(ar9280Common_9280
), 2);
740 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
741 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9160
,
742 ARRAY_SIZE(ar5416Modes_9160
), 6);
743 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9160
,
744 ARRAY_SIZE(ar5416Common_9160
), 2);
745 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9160
,
746 ARRAY_SIZE(ar5416Bank0_9160
), 2);
747 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9160
,
748 ARRAY_SIZE(ar5416BB_RfGain_9160
), 3);
749 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9160
,
750 ARRAY_SIZE(ar5416Bank1_9160
), 2);
751 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9160
,
752 ARRAY_SIZE(ar5416Bank2_9160
), 2);
753 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9160
,
754 ARRAY_SIZE(ar5416Bank3_9160
), 3);
755 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9160
,
756 ARRAY_SIZE(ar5416Bank6_9160
), 3);
757 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9160
,
758 ARRAY_SIZE(ar5416Bank6TPC_9160
), 3);
759 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9160
,
760 ARRAY_SIZE(ar5416Bank7_9160
), 2);
761 if (AR_SREV_9160_11(ah
)) {
762 INIT_INI_ARRAY(&ah
->iniAddac
,
764 ARRAY_SIZE(ar5416Addac_91601_1
), 2);
766 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9160
,
767 ARRAY_SIZE(ar5416Addac_9160
), 2);
769 } else if (AR_SREV_9100_OR_LATER(ah
)) {
770 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9100
,
771 ARRAY_SIZE(ar5416Modes_9100
), 6);
772 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9100
,
773 ARRAY_SIZE(ar5416Common_9100
), 2);
774 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9100
,
775 ARRAY_SIZE(ar5416Bank0_9100
), 2);
776 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9100
,
777 ARRAY_SIZE(ar5416BB_RfGain_9100
), 3);
778 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9100
,
779 ARRAY_SIZE(ar5416Bank1_9100
), 2);
780 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9100
,
781 ARRAY_SIZE(ar5416Bank2_9100
), 2);
782 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9100
,
783 ARRAY_SIZE(ar5416Bank3_9100
), 3);
784 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9100
,
785 ARRAY_SIZE(ar5416Bank6_9100
), 3);
786 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9100
,
787 ARRAY_SIZE(ar5416Bank6TPC_9100
), 3);
788 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9100
,
789 ARRAY_SIZE(ar5416Bank7_9100
), 2);
790 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9100
,
791 ARRAY_SIZE(ar5416Addac_9100
), 2);
793 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes
,
794 ARRAY_SIZE(ar5416Modes
), 6);
795 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common
,
796 ARRAY_SIZE(ar5416Common
), 2);
797 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0
,
798 ARRAY_SIZE(ar5416Bank0
), 2);
799 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain
,
800 ARRAY_SIZE(ar5416BB_RfGain
), 3);
801 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1
,
802 ARRAY_SIZE(ar5416Bank1
), 2);
803 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2
,
804 ARRAY_SIZE(ar5416Bank2
), 2);
805 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3
,
806 ARRAY_SIZE(ar5416Bank3
), 3);
807 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6
,
808 ARRAY_SIZE(ar5416Bank6
), 3);
809 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC
,
810 ARRAY_SIZE(ar5416Bank6TPC
), 3);
811 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7
,
812 ARRAY_SIZE(ar5416Bank7
), 2);
813 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac
,
814 ARRAY_SIZE(ar5416Addac
), 2);
818 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
820 if (AR_SREV_9287_11_OR_LATER(ah
))
821 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
822 ar9287Modes_rx_gain_9287_1_1
,
823 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1
), 6);
824 else if (AR_SREV_9287_10(ah
))
825 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
826 ar9287Modes_rx_gain_9287_1_0
,
827 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0
), 6);
828 else if (AR_SREV_9280_20(ah
))
829 ath9k_hw_init_rxgain_ini(ah
);
831 if (AR_SREV_9287_11_OR_LATER(ah
)) {
832 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
833 ar9287Modes_tx_gain_9287_1_1
,
834 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1
), 6);
835 } else if (AR_SREV_9287_10(ah
)) {
836 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
837 ar9287Modes_tx_gain_9287_1_0
,
838 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0
), 6);
839 } else if (AR_SREV_9280_20(ah
)) {
840 ath9k_hw_init_txgain_ini(ah
);
841 } else if (AR_SREV_9285_12_OR_LATER(ah
)) {
842 u32 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
845 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
) {
846 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
847 ar9285Modes_high_power_tx_gain_9285_1_2
,
848 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2
), 6);
850 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
851 ar9285Modes_original_tx_gain_9285_1_2
,
852 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2
), 6);
858 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw
*ah
)
862 if ((ah
->hw_version
.devid
== AR9280_DEVID_PCI
) &&
863 test_bit(ATH9K_MODE_11A
, ah
->caps
.wireless_modes
)) {
866 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
867 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
869 for (j
= 1; j
< ah
->iniModes
.ia_columns
; j
++) {
870 u32 val
= INI_RA(&ah
->iniModes
, i
, j
);
872 INI_RA(&ah
->iniModes
, i
, j
) =
873 ath9k_hw_ini_fixup(ah
,
881 int ath9k_hw_init(struct ath_hw
*ah
)
883 struct ath_common
*common
= ath9k_hw_common(ah
);
886 if (!ath9k_hw_devid_supported(ah
->hw_version
.devid
)) {
887 ath_print(common
, ATH_DBG_FATAL
,
888 "Unsupported device ID: 0x%0x\n",
889 ah
->hw_version
.devid
);
893 ath9k_hw_init_defaults(ah
);
894 ath9k_hw_init_config(ah
);
896 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
897 ath_print(common
, ATH_DBG_FATAL
,
898 "Couldn't reset chip\n");
902 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
903 ath_print(common
, ATH_DBG_FATAL
, "Couldn't wakeup chip\n");
907 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
908 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
909 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
910 ah
->config
.serialize_regmode
=
913 ah
->config
.serialize_regmode
=
918 ath_print(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
919 ah
->config
.serialize_regmode
);
921 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
922 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
924 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
926 if (!ath9k_hw_macversion_supported(ah
->hw_version
.macVersion
)) {
927 ath_print(common
, ATH_DBG_FATAL
,
928 "Mac Chip Rev 0x%02x.%x is not supported by "
929 "this driver\n", ah
->hw_version
.macVersion
,
930 ah
->hw_version
.macRev
);
934 if (AR_SREV_9100(ah
)) {
935 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
936 ah
->supp_cals
= IQ_MISMATCH_CAL
;
937 ah
->is_pciexpress
= false;
940 if (AR_SREV_9271(ah
))
941 ah
->is_pciexpress
= false;
943 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
945 ath9k_hw_init_cal_settings(ah
);
947 ah
->ani_function
= ATH9K_ANI_ALL
;
948 if (AR_SREV_9280_10_OR_LATER(ah
)) {
949 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
950 ah
->ath9k_hw_rf_set_freq
= &ath9k_hw_ar9280_set_channel
;
951 ah
->ath9k_hw_spur_mitigate_freq
= &ath9k_hw_9280_spur_mitigate
;
953 ah
->ath9k_hw_rf_set_freq
= &ath9k_hw_set_channel
;
954 ah
->ath9k_hw_spur_mitigate_freq
= &ath9k_hw_spur_mitigate
;
957 ath9k_hw_init_mode_regs(ah
);
959 if (ah
->is_pciexpress
)
960 ath9k_hw_configpcipowersave(ah
, 0, 0);
962 ath9k_hw_disablepcie(ah
);
964 /* Support for Japan ch.14 (2484) spread */
965 if (AR_SREV_9287_11_OR_LATER(ah
)) {
966 INIT_INI_ARRAY(&ah
->iniCckfirNormal
,
967 ar9287Common_normal_cck_fir_coeff_92871_1
,
968 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1
), 2);
969 INIT_INI_ARRAY(&ah
->iniCckfirJapan2484
,
970 ar9287Common_japan_2484_cck_fir_coeff_92871_1
,
971 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1
), 2);
974 r
= ath9k_hw_post_init(ah
);
978 ath9k_hw_init_mode_gain_regs(ah
);
979 r
= ath9k_hw_fill_cap_info(ah
);
983 ath9k_hw_init_11a_eeprom_fix(ah
);
985 r
= ath9k_hw_init_macaddr(ah
);
987 ath_print(common
, ATH_DBG_FATAL
,
988 "Failed to initialize MAC address\n");
992 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
993 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
995 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
997 ath9k_init_nfcal_hist_buffer(ah
);
999 common
->state
= ATH_HW_INITIALIZED
;
1004 static void ath9k_hw_init_bb(struct ath_hw
*ah
,
1005 struct ath9k_channel
*chan
)
1009 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1010 if (IS_CHAN_B(chan
))
1011 synthDelay
= (4 * synthDelay
) / 22;
1015 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_EN
);
1017 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1020 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
1022 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
1023 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
1025 REG_WRITE(ah
, AR_QOS_NO_ACK
,
1026 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
1027 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
1028 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
1030 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
1031 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
1032 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
1033 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
1034 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
1037 static void ath9k_hw_change_target_baud(struct ath_hw
*ah
, u32 freq
, u32 baud
)
1040 u32 baud_divider
= freq
* 1000 * 1000 / 16 / baud
;
1042 lcr
= REG_READ(ah
, 0x5100c);
1045 REG_WRITE(ah
, 0x5100c, lcr
);
1046 REG_WRITE(ah
, 0x51004, (baud_divider
>> 8));
1047 REG_WRITE(ah
, 0x51000, (baud_divider
& 0xff));
1050 REG_WRITE(ah
, 0x5100c, lcr
);
1053 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
1054 struct ath9k_channel
*chan
)
1058 if (AR_SREV_9100(ah
)) {
1059 if (chan
&& IS_CHAN_5GHZ(chan
))
1064 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1065 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1067 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1068 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1069 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1070 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1072 if (chan
&& IS_CHAN_5GHZ(chan
)) {
1073 pll
|= SM(0x28, AR_RTC_9160_PLL_DIV
);
1076 if (AR_SREV_9280_20(ah
)) {
1077 if (((chan
->channel
% 20) == 0)
1078 || ((chan
->channel
% 10) == 0))
1084 pll
|= SM(0x2c, AR_RTC_9160_PLL_DIV
);
1087 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1089 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
1091 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1092 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
1093 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1094 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
1096 if (chan
&& IS_CHAN_5GHZ(chan
))
1097 pll
|= SM(0x50, AR_RTC_9160_PLL_DIV
);
1099 pll
|= SM(0x58, AR_RTC_9160_PLL_DIV
);
1101 pll
= AR_RTC_PLL_REFDIV_5
| AR_RTC_PLL_DIV2
;
1103 if (chan
&& IS_CHAN_HALF_RATE(chan
))
1104 pll
|= SM(0x1, AR_RTC_PLL_CLKSEL
);
1105 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
1106 pll
|= SM(0x2, AR_RTC_PLL_CLKSEL
);
1108 if (chan
&& IS_CHAN_5GHZ(chan
))
1109 pll
|= SM(0xa, AR_RTC_PLL_DIV
);
1111 pll
|= SM(0xb, AR_RTC_PLL_DIV
);
1114 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
1116 /* Switch the core clock for ar9271 to 117Mhz */
1117 if (AR_SREV_9271(ah
)) {
1118 if ((pll
== 0x142c) || (pll
== 0x2850) ) {
1120 /* set CLKOBS to output AHB clock */
1121 REG_WRITE(ah
, 0x7020, 0xe);
1123 * 0x304: 117Mhz, ahb_ratio: 1x1
1124 * 0x306: 40Mhz, ahb_ratio: 1x1
1126 REG_WRITE(ah
, 0x50040, 0x304);
1128 * makes adjustments for the baud dividor to keep the
1129 * targetted baud rate based on the used core clock.
1131 ath9k_hw_change_target_baud(ah
, AR9271_CORE_CLOCK
,
1132 AR9271_TARGET_BAUD_RATE
);
1136 udelay(RTC_PLL_SETTLE_DELAY
);
1138 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
1141 static void ath9k_hw_init_chain_masks(struct ath_hw
*ah
)
1143 int rx_chainmask
, tx_chainmask
;
1145 rx_chainmask
= ah
->rxchainmask
;
1146 tx_chainmask
= ah
->txchainmask
;
1148 switch (rx_chainmask
) {
1150 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1151 AR_PHY_SWAP_ALT_CHAIN
);
1153 if (ah
->hw_version
.macVersion
== AR_SREV_REVISION_5416_10
) {
1154 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, 0x7);
1155 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, 0x7);
1161 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
1162 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
1168 REG_WRITE(ah
, AR_SELFGEN_MASK
, tx_chainmask
);
1169 if (tx_chainmask
== 0x5) {
1170 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1171 AR_PHY_SWAP_ALT_CHAIN
);
1173 if (AR_SREV_9100(ah
))
1174 REG_WRITE(ah
, AR_PHY_ANALOG_SWAP
,
1175 REG_READ(ah
, AR_PHY_ANALOG_SWAP
) | 0x00000001);
1178 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
1179 enum nl80211_iftype opmode
)
1181 ah
->mask_reg
= AR_IMR_TXERR
|
1187 if (ah
->config
.intr_mitigation
)
1188 ah
->mask_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
1190 ah
->mask_reg
|= AR_IMR_RXOK
;
1192 ah
->mask_reg
|= AR_IMR_TXOK
;
1194 if (opmode
== NL80211_IFTYPE_AP
)
1195 ah
->mask_reg
|= AR_IMR_MIB
;
1197 REG_WRITE(ah
, AR_IMR
, ah
->mask_reg
);
1198 REG_WRITE(ah
, AR_IMR_S2
, REG_READ(ah
, AR_IMR_S2
) | AR_IMR_S2_GTT
);
1200 if (!AR_SREV_9100(ah
)) {
1201 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
1202 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
1203 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
1207 static bool ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
1209 if (us
> ath9k_hw_mac_to_usec(ah
, MS(0xffffffff, AR_TIME_OUT_ACK
))) {
1210 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1211 "bad ack timeout %u\n", us
);
1212 ah
->acktimeout
= (u32
) -1;
1215 REG_RMW_FIELD(ah
, AR_TIME_OUT
,
1216 AR_TIME_OUT_ACK
, ath9k_hw_mac_to_clks(ah
, us
));
1217 ah
->acktimeout
= us
;
1222 static bool ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
1224 if (us
> ath9k_hw_mac_to_usec(ah
, MS(0xffffffff, AR_TIME_OUT_CTS
))) {
1225 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1226 "bad cts timeout %u\n", us
);
1227 ah
->ctstimeout
= (u32
) -1;
1230 REG_RMW_FIELD(ah
, AR_TIME_OUT
,
1231 AR_TIME_OUT_CTS
, ath9k_hw_mac_to_clks(ah
, us
));
1232 ah
->ctstimeout
= us
;
1237 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
1240 ath_print(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
1241 "bad global tx timeout %u\n", tu
);
1242 ah
->globaltxtimeout
= (u32
) -1;
1245 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
1246 ah
->globaltxtimeout
= tu
;
1251 static void ath9k_hw_init_user_settings(struct ath_hw
*ah
)
1253 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
1256 if (ah
->misc_mode
!= 0)
1257 REG_WRITE(ah
, AR_PCU_MISC
,
1258 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
1259 if (ah
->slottime
!= (u32
) -1)
1260 ath9k_hw_setslottime(ah
, ah
->slottime
);
1261 if (ah
->acktimeout
!= (u32
) -1)
1262 ath9k_hw_set_ack_timeout(ah
, ah
->acktimeout
);
1263 if (ah
->ctstimeout
!= (u32
) -1)
1264 ath9k_hw_set_cts_timeout(ah
, ah
->ctstimeout
);
1265 if (ah
->globaltxtimeout
!= (u32
) -1)
1266 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1269 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
)
1271 return vendorid
== ATHEROS_VENDOR_ID
?
1272 ath9k_hw_devname(devid
) : NULL
;
1275 void ath9k_hw_detach(struct ath_hw
*ah
)
1277 struct ath_common
*common
= ath9k_hw_common(ah
);
1279 if (common
->state
<= ATH_HW_INITIALIZED
)
1282 if (!AR_SREV_9100(ah
))
1283 ath9k_hw_ani_disable(ah
);
1285 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1288 if (!AR_SREV_9280_10_OR_LATER(ah
))
1289 ath9k_hw_rf_free_ext_banks(ah
);
1293 EXPORT_SYMBOL(ath9k_hw_detach
);
1299 static void ath9k_hw_override_ini(struct ath_hw
*ah
,
1300 struct ath9k_channel
*chan
)
1304 if (AR_SREV_9271(ah
)) {
1306 * Enable spectral scan to solution for issues with stuck
1307 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1310 if (AR_SREV_9271_10(ah
)) {
1311 val
= REG_READ(ah
, AR_PHY_SPECTRAL_SCAN
) |
1312 AR_PHY_SPECTRAL_SCAN_ENABLE
;
1313 REG_WRITE(ah
, AR_PHY_SPECTRAL_SCAN
, val
);
1315 else if (AR_SREV_9271_11(ah
))
1317 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1318 * present on AR9271 1.1
1320 REG_WRITE(ah
, AR_PHY_RF_CTL3
, 0x3a020001);
1325 * Set the RX_ABORT and RX_DIS and clear if off only after
1326 * RXE is set for MAC. This prevents frames with corrupted
1327 * descriptor status.
1329 REG_SET_BIT(ah
, AR_DIAG_SW
, (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
1331 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1332 val
= REG_READ(ah
, AR_PCU_MISC_MODE2
) &
1333 (~AR_PCU_MISC_MODE2_HWWAR1
);
1335 if (AR_SREV_9287_10_OR_LATER(ah
))
1336 val
= val
& (~AR_PCU_MISC_MODE2_HWWAR2
);
1338 REG_WRITE(ah
, AR_PCU_MISC_MODE2
, val
);
1341 if (!AR_SREV_5416_20_OR_LATER(ah
) ||
1342 AR_SREV_9280_10_OR_LATER(ah
))
1345 * Disable BB clock gating
1346 * Necessary to avoid issues on AR5416 2.0
1348 REG_WRITE(ah
, 0x9800 + (651 << 2), 0x11);
1351 static u32
ath9k_hw_def_ini_fixup(struct ath_hw
*ah
,
1352 struct ar5416_eeprom_def
*pEepData
,
1355 struct base_eep_header
*pBase
= &(pEepData
->baseEepHeader
);
1356 struct ath_common
*common
= ath9k_hw_common(ah
);
1358 switch (ah
->hw_version
.devid
) {
1359 case AR9280_DEVID_PCI
:
1360 if (reg
== 0x7894) {
1361 ath_print(common
, ATH_DBG_EEPROM
,
1362 "ini VAL: %x EEPROM: %x\n", value
,
1363 (pBase
->version
& 0xff));
1365 if ((pBase
->version
& 0xff) > 0x0a) {
1366 ath_print(common
, ATH_DBG_EEPROM
,
1369 value
&= ~AR_AN_TOP2_PWDCLKIND
;
1370 value
|= AR_AN_TOP2_PWDCLKIND
&
1371 (pBase
->pwdclkind
<< AR_AN_TOP2_PWDCLKIND_S
);
1373 ath_print(common
, ATH_DBG_EEPROM
,
1374 "PWDCLKIND Earlier Rev\n");
1377 ath_print(common
, ATH_DBG_EEPROM
,
1378 "final ini VAL: %x\n", value
);
1386 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
1387 struct ar5416_eeprom_def
*pEepData
,
1390 if (ah
->eep_map
== EEP_MAP_4KBITS
)
1393 return ath9k_hw_def_ini_fixup(ah
, pEepData
, reg
, value
);
1396 static void ath9k_olc_init(struct ath_hw
*ah
)
1400 if (OLC_FOR_AR9287_10_LATER
) {
1401 REG_SET_BIT(ah
, AR_PHY_TX_PWRCTRL9
,
1402 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL
);
1403 ath9k_hw_analog_shift_rmw(ah
, AR9287_AN_TXPC0
,
1404 AR9287_AN_TXPC0_TXPCMODE
,
1405 AR9287_AN_TXPC0_TXPCMODE_S
,
1406 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE
);
1409 for (i
= 0; i
< AR9280_TX_GAIN_TABLE_SIZE
; i
++)
1410 ah
->originalGain
[i
] =
1411 MS(REG_READ(ah
, AR_PHY_TX_GAIN_TBL1
+ i
* 4),
1417 static u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
,
1418 struct ath9k_channel
*chan
)
1420 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1422 if (IS_CHAN_B(chan
))
1424 else if (IS_CHAN_G(chan
))
1432 static int ath9k_hw_process_ini(struct ath_hw
*ah
,
1433 struct ath9k_channel
*chan
)
1435 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1436 int i
, regWrites
= 0;
1437 struct ieee80211_channel
*channel
= chan
->chan
;
1438 u32 modesIndex
, freqIndex
;
1440 switch (chan
->chanmode
) {
1442 case CHANNEL_A_HT20
:
1446 case CHANNEL_A_HT40PLUS
:
1447 case CHANNEL_A_HT40MINUS
:
1452 case CHANNEL_G_HT20
:
1457 case CHANNEL_G_HT40PLUS
:
1458 case CHANNEL_G_HT40MINUS
:
1467 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
1468 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_EXTERNAL_RADIO
);
1469 ah
->eep_ops
->set_addac(ah
, chan
);
1471 if (AR_SREV_5416_22_OR_LATER(ah
)) {
1472 REG_WRITE_ARRAY(&ah
->iniAddac
, 1, regWrites
);
1474 struct ar5416IniArray temp
;
1476 sizeof(u32
) * ah
->iniAddac
.ia_rows
*
1477 ah
->iniAddac
.ia_columns
;
1479 memcpy(ah
->addac5416_21
,
1480 ah
->iniAddac
.ia_array
, addacSize
);
1482 (ah
->addac5416_21
)[31 * ah
->iniAddac
.ia_columns
+ 1] = 0;
1484 temp
.ia_array
= ah
->addac5416_21
;
1485 temp
.ia_columns
= ah
->iniAddac
.ia_columns
;
1486 temp
.ia_rows
= ah
->iniAddac
.ia_rows
;
1487 REG_WRITE_ARRAY(&temp
, 1, regWrites
);
1490 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_INTERNAL_ADDAC
);
1492 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
1493 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
1494 u32 val
= INI_RA(&ah
->iniModes
, i
, modesIndex
);
1496 REG_WRITE(ah
, reg
, val
);
1498 if (reg
>= 0x7800 && reg
< 0x78a0
1499 && ah
->config
.analog_shiftreg
) {
1503 DO_DELAY(regWrites
);
1506 if (AR_SREV_9280(ah
) || AR_SREV_9287_10_OR_LATER(ah
))
1507 REG_WRITE_ARRAY(&ah
->iniModesRxGain
, modesIndex
, regWrites
);
1509 if (AR_SREV_9280(ah
) || AR_SREV_9285_12_OR_LATER(ah
) ||
1510 AR_SREV_9287_10_OR_LATER(ah
))
1511 REG_WRITE_ARRAY(&ah
->iniModesTxGain
, modesIndex
, regWrites
);
1513 for (i
= 0; i
< ah
->iniCommon
.ia_rows
; i
++) {
1514 u32 reg
= INI_RA(&ah
->iniCommon
, i
, 0);
1515 u32 val
= INI_RA(&ah
->iniCommon
, i
, 1);
1517 REG_WRITE(ah
, reg
, val
);
1519 if (reg
>= 0x7800 && reg
< 0x78a0
1520 && ah
->config
.analog_shiftreg
) {
1524 DO_DELAY(regWrites
);
1527 ath9k_hw_write_regs(ah
, freqIndex
, regWrites
);
1529 if (AR_SREV_9271_10(ah
))
1530 REG_WRITE_ARRAY(&ah
->iniModes_9271_1_0_only
,
1531 modesIndex
, regWrites
);
1533 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
)) {
1534 REG_WRITE_ARRAY(&ah
->iniModesAdditional
, modesIndex
,
1538 ath9k_hw_override_ini(ah
, chan
);
1539 ath9k_hw_set_regs(ah
, chan
);
1540 ath9k_hw_init_chain_masks(ah
);
1542 if (OLC_FOR_AR9280_20_LATER
)
1545 ah
->eep_ops
->set_txpower(ah
, chan
,
1546 ath9k_regd_get_ctl(regulatory
, chan
),
1547 channel
->max_antenna_gain
* 2,
1548 channel
->max_power
* 2,
1549 min((u32
) MAX_RATE_POWER
,
1550 (u32
) regulatory
->power_limit
));
1552 if (!ath9k_hw_set_rf_regs(ah
, chan
, freqIndex
)) {
1553 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
1554 "ar5416SetRfRegs failed\n");
1561 /****************************************/
1562 /* Reset and Channel Switching Routines */
1563 /****************************************/
1565 static void ath9k_hw_set_rfmode(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1572 rfMode
|= (IS_CHAN_B(chan
) || IS_CHAN_G(chan
))
1573 ? AR_PHY_MODE_DYNAMIC
: AR_PHY_MODE_OFDM
;
1575 if (!AR_SREV_9280_10_OR_LATER(ah
))
1576 rfMode
|= (IS_CHAN_5GHZ(chan
)) ?
1577 AR_PHY_MODE_RF5GHZ
: AR_PHY_MODE_RF2GHZ
;
1579 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
))
1580 rfMode
|= (AR_PHY_MODE_DYNAMIC
| AR_PHY_MODE_DYN_CCK_DISABLE
);
1582 REG_WRITE(ah
, AR_PHY_MODE
, rfMode
);
1585 static void ath9k_hw_mark_phy_inactive(struct ath_hw
*ah
)
1587 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_DIS
);
1590 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1595 * set AHB_MODE not to do cacheline prefetches
1597 regval
= REG_READ(ah
, AR_AHB_MODE
);
1598 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
1601 * let mac dma reads be in 128 byte chunks
1603 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
1604 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
1607 * Restore TX Trigger Level to its pre-reset value.
1608 * The initial value depends on whether aggregation is enabled, and is
1609 * adjusted whenever underruns are detected.
1611 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1614 * let mac dma writes be in 128 byte chunks
1616 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
1617 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
1620 * Setup receive FIFO threshold to hold off TX activities
1622 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1625 * reduce the number of usable entries in PCU TXBUF to avoid
1626 * wrap around issues.
1628 if (AR_SREV_9285(ah
)) {
1629 /* For AR9285 the number of Fifos are reduced to half.
1630 * So set the usable tx buf size also to half to
1631 * avoid data/delimiter underruns
1633 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1634 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1635 } else if (!AR_SREV_9271(ah
)) {
1636 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1637 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1641 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1645 val
= REG_READ(ah
, AR_STA_ID1
);
1646 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
1648 case NL80211_IFTYPE_AP
:
1649 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
1650 | AR_STA_ID1_KSRCH_MODE
);
1651 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1653 case NL80211_IFTYPE_ADHOC
:
1654 case NL80211_IFTYPE_MESH_POINT
:
1655 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
1656 | AR_STA_ID1_KSRCH_MODE
);
1657 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1659 case NL80211_IFTYPE_STATION
:
1660 case NL80211_IFTYPE_MONITOR
:
1661 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
1666 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
,
1671 u32 coef_exp
, coef_man
;
1673 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1674 if ((coef_scaled
>> coef_exp
) & 0x1)
1677 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1679 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1681 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1682 *coef_exponent
= coef_exp
- 16;
1685 static void ath9k_hw_set_delta_slope(struct ath_hw
*ah
,
1686 struct ath9k_channel
*chan
)
1688 u32 coef_scaled
, ds_coef_exp
, ds_coef_man
;
1689 u32 clockMhzScaled
= 0x64000000;
1690 struct chan_centers centers
;
1692 if (IS_CHAN_HALF_RATE(chan
))
1693 clockMhzScaled
= clockMhzScaled
>> 1;
1694 else if (IS_CHAN_QUARTER_RATE(chan
))
1695 clockMhzScaled
= clockMhzScaled
>> 2;
1697 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1698 coef_scaled
= clockMhzScaled
/ centers
.synth_center
;
1700 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1703 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1704 AR_PHY_TIMING3_DSC_MAN
, ds_coef_man
);
1705 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1706 AR_PHY_TIMING3_DSC_EXP
, ds_coef_exp
);
1708 coef_scaled
= (9 * coef_scaled
) / 10;
1710 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1713 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1714 AR_PHY_HALFGI_DSC_MAN
, ds_coef_man
);
1715 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1716 AR_PHY_HALFGI_DSC_EXP
, ds_coef_exp
);
1719 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1724 if (AR_SREV_9100(ah
)) {
1725 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1726 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
1727 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
1728 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
1729 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1732 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1733 AR_RTC_FORCE_WAKE_ON_INT
);
1735 if (AR_SREV_9100(ah
)) {
1736 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1737 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1739 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1741 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1742 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1743 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1744 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1746 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1749 rst_flags
= AR_RTC_RC_MAC_WARM
;
1750 if (type
== ATH9K_RESET_COLD
)
1751 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1754 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1757 REG_WRITE(ah
, AR_RTC_RC
, 0);
1758 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1759 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1760 "RTC stuck in MAC reset\n");
1764 if (!AR_SREV_9100(ah
))
1765 REG_WRITE(ah
, AR_RC
, 0);
1767 if (AR_SREV_9100(ah
))
1773 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1775 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1776 AR_RTC_FORCE_WAKE_ON_INT
);
1778 if (!AR_SREV_9100(ah
))
1779 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1781 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1784 if (!AR_SREV_9100(ah
))
1785 REG_WRITE(ah
, AR_RC
, 0);
1787 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1789 if (!ath9k_hw_wait(ah
,
1794 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1795 "RTC not waking up\n");
1799 ath9k_hw_read_revisions(ah
);
1801 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1804 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1806 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1807 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1810 case ATH9K_RESET_POWER_ON
:
1811 return ath9k_hw_set_reset_power_on(ah
);
1812 case ATH9K_RESET_WARM
:
1813 case ATH9K_RESET_COLD
:
1814 return ath9k_hw_set_reset(ah
, type
);
1820 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1823 u32 enableDacFifo
= 0;
1825 if (AR_SREV_9285_10_OR_LATER(ah
))
1826 enableDacFifo
= (REG_READ(ah
, AR_PHY_TURBO
) &
1827 AR_PHY_FC_ENABLE_DAC_FIFO
);
1829 phymode
= AR_PHY_FC_HT_EN
| AR_PHY_FC_SHORT_GI_40
1830 | AR_PHY_FC_SINGLE_HT_LTF1
| AR_PHY_FC_WALSH
| enableDacFifo
;
1832 if (IS_CHAN_HT40(chan
)) {
1833 phymode
|= AR_PHY_FC_DYN2040_EN
;
1835 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
1836 (chan
->chanmode
== CHANNEL_G_HT40PLUS
))
1837 phymode
|= AR_PHY_FC_DYN2040_PRI_CH
;
1840 REG_WRITE(ah
, AR_PHY_TURBO
, phymode
);
1842 ath9k_hw_set11nmac2040(ah
);
1844 REG_WRITE(ah
, AR_GTXTO
, 25 << AR_GTXTO_TIMEOUT_LIMIT_S
);
1845 REG_WRITE(ah
, AR_CST
, 0xF << AR_CST_TIMEOUT_LIMIT_S
);
1848 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1849 struct ath9k_channel
*chan
)
1851 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1852 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1854 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1857 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1860 ah
->chip_fullsleep
= false;
1861 ath9k_hw_init_pll(ah
, chan
);
1862 ath9k_hw_set_rfmode(ah
, chan
);
1867 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1868 struct ath9k_channel
*chan
)
1870 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
1871 struct ath_common
*common
= ath9k_hw_common(ah
);
1872 struct ieee80211_channel
*channel
= chan
->chan
;
1873 u32 synthDelay
, qnum
;
1876 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1877 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1878 ath_print(common
, ATH_DBG_QUEUE
,
1879 "Transmit frames pending on "
1880 "queue %d\n", qnum
);
1885 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, AR_PHY_RFBUS_REQ_EN
);
1886 if (!ath9k_hw_wait(ah
, AR_PHY_RFBUS_GRANT
, AR_PHY_RFBUS_GRANT_EN
,
1887 AR_PHY_RFBUS_GRANT_EN
, AH_WAIT_TIMEOUT
)) {
1888 ath_print(common
, ATH_DBG_FATAL
,
1889 "Could not kill baseband RX\n");
1893 ath9k_hw_set_regs(ah
, chan
);
1895 r
= ah
->ath9k_hw_rf_set_freq(ah
, chan
);
1897 ath_print(common
, ATH_DBG_FATAL
,
1898 "Failed to set channel\n");
1902 ah
->eep_ops
->set_txpower(ah
, chan
,
1903 ath9k_regd_get_ctl(regulatory
, chan
),
1904 channel
->max_antenna_gain
* 2,
1905 channel
->max_power
* 2,
1906 min((u32
) MAX_RATE_POWER
,
1907 (u32
) regulatory
->power_limit
));
1909 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1910 if (IS_CHAN_B(chan
))
1911 synthDelay
= (4 * synthDelay
) / 22;
1915 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1917 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, 0);
1919 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1920 ath9k_hw_set_delta_slope(ah
, chan
);
1922 ah
->ath9k_hw_spur_mitigate_freq(ah
, chan
);
1924 if (!chan
->oneTimeCalsDone
)
1925 chan
->oneTimeCalsDone
= true;
1930 static void ath9k_enable_rfkill(struct ath_hw
*ah
)
1932 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
1933 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB
);
1935 REG_CLR_BIT(ah
, AR_GPIO_INPUT_MUX2
,
1936 AR_GPIO_INPUT_MUX2_RFSILENT
);
1938 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
1939 REG_SET_BIT(ah
, AR_PHY_TEST
, RFSILENT_BB
);
1942 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1943 bool bChannelChange
)
1945 struct ath_common
*common
= ath9k_hw_common(ah
);
1947 struct ath9k_channel
*curchan
= ah
->curchan
;
1951 int i
, rx_chainmask
, r
;
1953 ah
->txchainmask
= common
->tx_chainmask
;
1954 ah
->rxchainmask
= common
->rx_chainmask
;
1956 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1959 if (curchan
&& !ah
->chip_fullsleep
)
1960 ath9k_hw_getnf(ah
, curchan
);
1962 if (bChannelChange
&&
1963 (ah
->chip_fullsleep
!= true) &&
1964 (ah
->curchan
!= NULL
) &&
1965 (chan
->channel
!= ah
->curchan
->channel
) &&
1966 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1967 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
1968 !(AR_SREV_9280(ah
) || IS_CHAN_A_5MHZ_SPACED(chan
) ||
1969 IS_CHAN_A_5MHZ_SPACED(ah
->curchan
))) {
1971 if (ath9k_hw_channel_change(ah
, chan
)) {
1972 ath9k_hw_loadnf(ah
, ah
->curchan
);
1973 ath9k_hw_start_nfcal(ah
);
1978 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1979 if (saveDefAntenna
== 0)
1982 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1984 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1985 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
1986 tsf
= ath9k_hw_gettsf64(ah
);
1988 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1989 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1990 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1992 ath9k_hw_mark_phy_inactive(ah
);
1994 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1996 AR9271_RESET_POWER_DOWN_CONTROL
,
1997 AR9271_RADIO_RF_RST
);
2001 if (!ath9k_hw_chip_reset(ah
, chan
)) {
2002 ath_print(common
, ATH_DBG_FATAL
, "Chip reset failed\n");
2006 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
2007 ah
->htc_reset_init
= false;
2009 AR9271_RESET_POWER_DOWN_CONTROL
,
2010 AR9271_GATE_MAC_CTL
);
2015 if (tsf
&& AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
))
2016 ath9k_hw_settsf64(ah
, tsf
);
2018 if (AR_SREV_9280_10_OR_LATER(ah
))
2019 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
2021 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2022 /* Enable ASYNC FIFO */
2023 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2024 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
);
2025 REG_SET_BIT(ah
, AR_PHY_MODE
, AR_PHY_MODE_ASYNCFIFO
);
2026 REG_CLR_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2027 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
2028 REG_SET_BIT(ah
, AR_MAC_PCU_ASYNC_FIFO_REG3
,
2029 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
);
2031 r
= ath9k_hw_process_ini(ah
, chan
);
2035 /* Setup MFP options for CCMP */
2036 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2037 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2038 * frames when constructing CCMP AAD. */
2039 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
2041 ah
->sw_mgmt_crypto
= false;
2042 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
2043 /* Disable hardware crypto for management frames */
2044 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
2045 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
2046 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2047 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
2048 ah
->sw_mgmt_crypto
= true;
2050 ah
->sw_mgmt_crypto
= true;
2052 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
2053 ath9k_hw_set_delta_slope(ah
, chan
);
2055 ah
->ath9k_hw_spur_mitigate_freq(ah
, chan
);
2056 ah
->eep_ops
->set_board_values(ah
, chan
);
2058 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
2059 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
2061 | AR_STA_ID1_RTS_USE_DEF
2063 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
2064 | ah
->sta_id1_defaults
);
2065 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2067 ath_hw_setbssidmask(common
);
2069 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
2071 ath9k_hw_write_associd(ah
);
2073 REG_WRITE(ah
, AR_ISR
, ~0);
2075 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
2077 r
= ah
->ath9k_hw_rf_set_freq(ah
, chan
);
2081 for (i
= 0; i
< AR_NUM_DCU
; i
++)
2082 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
2085 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
2086 ath9k_hw_resettxqueue(ah
, i
);
2088 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
2089 ath9k_hw_init_qos(ah
);
2091 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2092 ath9k_enable_rfkill(ah
);
2094 ath9k_hw_init_user_settings(ah
);
2096 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2097 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
,
2098 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
);
2099 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
,
2100 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
);
2101 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
,
2102 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
);
2104 REG_WRITE(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
);
2105 REG_WRITE(ah
, AR_USEC
, AR_USEC_ASYNC_FIFO_DUR
);
2107 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
2108 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
2109 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
2110 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
2112 if (AR_SREV_9287_12_OR_LATER(ah
)) {
2113 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2114 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
2117 REG_WRITE(ah
, AR_STA_ID1
,
2118 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
2120 ath9k_hw_set_dma(ah
);
2122 REG_WRITE(ah
, AR_OBS
, 8);
2124 if (ah
->config
.intr_mitigation
) {
2125 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
2126 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
2129 ath9k_hw_init_bb(ah
, chan
);
2131 if (!ath9k_hw_init_cal(ah
, chan
))
2134 rx_chainmask
= ah
->rxchainmask
;
2135 if ((rx_chainmask
== 0x5) || (rx_chainmask
== 0x3)) {
2136 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
2137 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
2140 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
2143 * For big endian systems turn on swapping for descriptors
2145 if (AR_SREV_9100(ah
)) {
2147 mask
= REG_READ(ah
, AR_CFG
);
2148 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
2149 ath_print(common
, ATH_DBG_RESET
,
2150 "CFG Byte Swap Set 0x%x\n", mask
);
2153 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
2154 REG_WRITE(ah
, AR_CFG
, mask
);
2155 ath_print(common
, ATH_DBG_RESET
,
2156 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
2159 /* Configure AR9271 target WLAN */
2160 if (AR_SREV_9271(ah
))
2161 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
2164 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
2168 if (ah
->btcoex_hw
.enabled
)
2169 ath9k_hw_btcoex_enable(ah
);
2173 EXPORT_SYMBOL(ath9k_hw_reset
);
2175 /************************/
2176 /* Key Cache Management */
2177 /************************/
2179 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
2183 if (entry
>= ah
->caps
.keycache_size
) {
2184 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2185 "keychache entry %u out of range\n", entry
);
2189 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
2191 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
2192 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
2193 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
2194 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
2195 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
2196 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
2197 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
2198 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
2200 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2201 u16 micentry
= entry
+ 64;
2203 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
2204 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2205 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
2206 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2212 EXPORT_SYMBOL(ath9k_hw_keyreset
);
2214 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
2218 if (entry
>= ah
->caps
.keycache_size
) {
2219 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2220 "keychache entry %u out of range\n", entry
);
2225 macHi
= (mac
[5] << 8) | mac
[4];
2226 macLo
= (mac
[3] << 24) |
2231 macLo
|= (macHi
& 1) << 31;
2236 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
2237 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
2241 EXPORT_SYMBOL(ath9k_hw_keysetmac
);
2243 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
2244 const struct ath9k_keyval
*k
,
2247 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2248 struct ath_common
*common
= ath9k_hw_common(ah
);
2249 u32 key0
, key1
, key2
, key3
, key4
;
2252 if (entry
>= pCap
->keycache_size
) {
2253 ath_print(common
, ATH_DBG_FATAL
,
2254 "keycache entry %u out of range\n", entry
);
2258 switch (k
->kv_type
) {
2259 case ATH9K_CIPHER_AES_OCB
:
2260 keyType
= AR_KEYTABLE_TYPE_AES
;
2262 case ATH9K_CIPHER_AES_CCM
:
2263 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
2264 ath_print(common
, ATH_DBG_ANY
,
2265 "AES-CCM not supported by mac rev 0x%x\n",
2266 ah
->hw_version
.macRev
);
2269 keyType
= AR_KEYTABLE_TYPE_CCM
;
2271 case ATH9K_CIPHER_TKIP
:
2272 keyType
= AR_KEYTABLE_TYPE_TKIP
;
2273 if (ATH9K_IS_MIC_ENABLED(ah
)
2274 && entry
+ 64 >= pCap
->keycache_size
) {
2275 ath_print(common
, ATH_DBG_ANY
,
2276 "entry %u inappropriate for TKIP\n", entry
);
2280 case ATH9K_CIPHER_WEP
:
2281 if (k
->kv_len
< WLAN_KEY_LEN_WEP40
) {
2282 ath_print(common
, ATH_DBG_ANY
,
2283 "WEP key length %u too small\n", k
->kv_len
);
2286 if (k
->kv_len
<= WLAN_KEY_LEN_WEP40
)
2287 keyType
= AR_KEYTABLE_TYPE_40
;
2288 else if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2289 keyType
= AR_KEYTABLE_TYPE_104
;
2291 keyType
= AR_KEYTABLE_TYPE_128
;
2293 case ATH9K_CIPHER_CLR
:
2294 keyType
= AR_KEYTABLE_TYPE_CLR
;
2297 ath_print(common
, ATH_DBG_FATAL
,
2298 "cipher %u not supported\n", k
->kv_type
);
2302 key0
= get_unaligned_le32(k
->kv_val
+ 0);
2303 key1
= get_unaligned_le16(k
->kv_val
+ 4);
2304 key2
= get_unaligned_le32(k
->kv_val
+ 6);
2305 key3
= get_unaligned_le16(k
->kv_val
+ 10);
2306 key4
= get_unaligned_le32(k
->kv_val
+ 12);
2307 if (k
->kv_len
<= WLAN_KEY_LEN_WEP104
)
2311 * Note: Key cache registers access special memory area that requires
2312 * two 32-bit writes to actually update the values in the internal
2313 * memory. Consequently, the exact order and pairs used here must be
2317 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2318 u16 micentry
= entry
+ 64;
2321 * Write inverted key[47:0] first to avoid Michael MIC errors
2322 * on frames that could be sent or received at the same time.
2323 * The correct key will be written in the end once everything
2326 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
2327 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
2329 /* Write key[95:48] */
2330 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2331 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2333 /* Write key[127:96] and key type */
2334 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2335 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2337 /* Write MAC address for the entry */
2338 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2340 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
2342 * TKIP uses two key cache entries:
2343 * Michael MIC TX/RX keys in the same key cache entry
2344 * (idx = main index + 64):
2345 * key0 [31:0] = RX key [31:0]
2346 * key1 [15:0] = TX key [31:16]
2347 * key1 [31:16] = reserved
2348 * key2 [31:0] = RX key [63:32]
2349 * key3 [15:0] = TX key [15:0]
2350 * key3 [31:16] = reserved
2351 * key4 [31:0] = TX key [63:32]
2353 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
2355 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2356 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2357 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
2358 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
2359 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
2361 /* Write RX[31:0] and TX[31:16] */
2362 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2363 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
2365 /* Write RX[63:32] and TX[15:0] */
2366 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2367 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
2369 /* Write TX[63:32] and keyType(reserved) */
2370 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
2371 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2372 AR_KEYTABLE_TYPE_CLR
);
2376 * TKIP uses four key cache entries (two for group
2378 * Michael MIC TX/RX keys are in different key cache
2379 * entries (idx = main index + 64 for TX and
2380 * main index + 32 + 96 for RX):
2381 * key0 [31:0] = TX/RX MIC key [31:0]
2382 * key1 [31:0] = reserved
2383 * key2 [31:0] = TX/RX MIC key [63:32]
2384 * key3 [31:0] = reserved
2385 * key4 [31:0] = reserved
2387 * Upper layer code will call this function separately
2388 * for TX and RX keys when these registers offsets are
2393 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2394 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2396 /* Write MIC key[31:0] */
2397 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2398 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2400 /* Write MIC key[63:32] */
2401 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2402 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2404 /* Write TX[63:32] and keyType(reserved) */
2405 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
2406 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2407 AR_KEYTABLE_TYPE_CLR
);
2410 /* MAC address registers are reserved for the MIC entry */
2411 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
2412 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
2415 * Write the correct (un-inverted) key[47:0] last to enable
2416 * TKIP now that all other registers are set with correct
2419 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2420 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2422 /* Write key[47:0] */
2423 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2424 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2426 /* Write key[95:48] */
2427 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2428 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2430 /* Write key[127:96] and key type */
2431 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2432 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2434 /* Write MAC address for the entry */
2435 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2440 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry
);
2442 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
2444 if (entry
< ah
->caps
.keycache_size
) {
2445 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
2446 if (val
& AR_KEYTABLE_VALID
)
2451 EXPORT_SYMBOL(ath9k_hw_keyisvalid
);
2453 /******************************/
2454 /* Power Management (Chipset) */
2455 /******************************/
2457 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
2459 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2461 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2462 AR_RTC_FORCE_WAKE_EN
);
2463 if (!AR_SREV_9100(ah
))
2464 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
2466 if(!AR_SREV_5416(ah
))
2467 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
2472 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
2474 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2476 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2478 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2479 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2480 AR_RTC_FORCE_WAKE_ON_INT
);
2482 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2483 AR_RTC_FORCE_WAKE_EN
);
2488 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
2494 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2495 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2496 if (ath9k_hw_set_reset_reg(ah
,
2497 ATH9K_RESET_POWER_ON
) != true) {
2500 ath9k_hw_init_pll(ah
, NULL
);
2502 if (AR_SREV_9100(ah
))
2503 REG_SET_BIT(ah
, AR_RTC_RESET
,
2506 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2507 AR_RTC_FORCE_WAKE_EN
);
2510 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2511 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2512 if (val
== AR_RTC_STATUS_ON
)
2515 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2516 AR_RTC_FORCE_WAKE_EN
);
2519 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
2520 "Failed to wakeup in %uus\n",
2521 POWER_UP_TIME
/ 20);
2526 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2531 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2533 struct ath_common
*common
= ath9k_hw_common(ah
);
2534 int status
= true, setChip
= true;
2535 static const char *modes
[] = {
2542 if (ah
->power_mode
== mode
)
2545 ath_print(common
, ATH_DBG_RESET
, "%s -> %s\n",
2546 modes
[ah
->power_mode
], modes
[mode
]);
2549 case ATH9K_PM_AWAKE
:
2550 status
= ath9k_hw_set_power_awake(ah
, setChip
);
2552 case ATH9K_PM_FULL_SLEEP
:
2553 ath9k_set_power_sleep(ah
, setChip
);
2554 ah
->chip_fullsleep
= true;
2556 case ATH9K_PM_NETWORK_SLEEP
:
2557 ath9k_set_power_network_sleep(ah
, setChip
);
2560 ath_print(common
, ATH_DBG_FATAL
,
2561 "Unknown power mode %u\n", mode
);
2564 ah
->power_mode
= mode
;
2568 EXPORT_SYMBOL(ath9k_hw_setpower
);
2571 * Helper for ASPM support.
2573 * Disable PLL when in L0s as well as receiver clock when in L1.
2574 * This power saving option must be enabled through the SerDes.
2576 * Programming the SerDes must go through the same 288 bit serial shift
2577 * register as the other analog registers. Hence the 9 writes.
2579 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
, int power_off
)
2584 if (ah
->is_pciexpress
!= true)
2587 /* Do not touch SerDes registers */
2588 if (ah
->config
.pcie_powersave_enable
== 2)
2591 /* Nothing to do on restore for 11N */
2593 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2595 * AR9280 2.0 or later chips use SerDes values from the
2596 * initvals.h initialized depending on chipset during
2599 for (i
= 0; i
< ah
->iniPcieSerdes
.ia_rows
; i
++) {
2600 REG_WRITE(ah
, INI_RA(&ah
->iniPcieSerdes
, i
, 0),
2601 INI_RA(&ah
->iniPcieSerdes
, i
, 1));
2603 } else if (AR_SREV_9280(ah
) &&
2604 (ah
->hw_version
.macRev
== AR_SREV_REVISION_9280_10
)) {
2605 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fd00);
2606 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2608 /* RX shut off when elecidle is asserted */
2609 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xa8000019);
2610 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x13160820);
2611 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980560);
2613 /* Shut off CLKREQ active in L1 */
2614 if (ah
->config
.pcie_clock_req
)
2615 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffc);
2617 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffd);
2619 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2620 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2621 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00043007);
2623 /* Load the new settings */
2624 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2627 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
2628 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2630 /* RX shut off when elecidle is asserted */
2631 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000039);
2632 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x53160824);
2633 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980579);
2636 * Ignore ah->ah_config.pcie_clock_req setting for
2639 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x001defff);
2641 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2642 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2643 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e3007);
2645 /* Load the new settings */
2646 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2651 /* set bit 19 to allow forcing of pcie core into L1 state */
2652 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PCIE_PM_CTRL_ENA
);
2654 /* Several PCIe massages to ensure proper behaviour */
2655 if (ah
->config
.pcie_waen
) {
2656 val
= ah
->config
.pcie_waen
;
2658 val
&= (~AR_WA_D3_L1_DISABLE
);
2660 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2662 val
= AR9285_WA_DEFAULT
;
2664 val
&= (~AR_WA_D3_L1_DISABLE
);
2665 } else if (AR_SREV_9280(ah
)) {
2667 * On AR9280 chips bit 22 of 0x4004 needs to be
2668 * set otherwise card may disappear.
2670 val
= AR9280_WA_DEFAULT
;
2672 val
&= (~AR_WA_D3_L1_DISABLE
);
2674 val
= AR_WA_DEFAULT
;
2677 REG_WRITE(ah
, AR_WA
, val
);
2682 * Set PCIe workaround bits
2683 * bit 14 in WA register (disable L1) should only
2684 * be set when device enters D3 and be cleared
2685 * when device comes back to D0.
2687 if (ah
->config
.pcie_waen
) {
2688 if (ah
->config
.pcie_waen
& AR_WA_D3_L1_DISABLE
)
2689 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2691 if (((AR_SREV_9285(ah
) || AR_SREV_9271(ah
) ||
2692 AR_SREV_9287(ah
)) &&
2693 (AR9285_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
)) ||
2694 (AR_SREV_9280(ah
) &&
2695 (AR9280_WA_DEFAULT
& AR_WA_D3_L1_DISABLE
))) {
2696 REG_SET_BIT(ah
, AR_WA
, AR_WA_D3_L1_DISABLE
);
2701 EXPORT_SYMBOL(ath9k_hw_configpcipowersave
);
2703 /**********************/
2704 /* Interrupt Handling */
2705 /**********************/
2707 bool ath9k_hw_intrpend(struct ath_hw
*ah
)
2711 if (AR_SREV_9100(ah
))
2714 host_isr
= REG_READ(ah
, AR_INTR_ASYNC_CAUSE
);
2715 if ((host_isr
& AR_INTR_MAC_IRQ
) && (host_isr
!= AR_INTR_SPURIOUS
))
2718 host_isr
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
2719 if ((host_isr
& AR_INTR_SYNC_DEFAULT
)
2720 && (host_isr
!= AR_INTR_SPURIOUS
))
2725 EXPORT_SYMBOL(ath9k_hw_intrpend
);
2727 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
2731 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2733 bool fatal_int
= false;
2734 struct ath_common
*common
= ath9k_hw_common(ah
);
2736 if (!AR_SREV_9100(ah
)) {
2737 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
2738 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
2739 == AR_RTC_STATUS_ON
) {
2740 isr
= REG_READ(ah
, AR_ISR
);
2744 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) &
2745 AR_INTR_SYNC_DEFAULT
;
2749 if (!isr
&& !sync_cause
)
2753 isr
= REG_READ(ah
, AR_ISR
);
2757 if (isr
& AR_ISR_BCNMISC
) {
2759 isr2
= REG_READ(ah
, AR_ISR_S2
);
2760 if (isr2
& AR_ISR_S2_TIM
)
2761 mask2
|= ATH9K_INT_TIM
;
2762 if (isr2
& AR_ISR_S2_DTIM
)
2763 mask2
|= ATH9K_INT_DTIM
;
2764 if (isr2
& AR_ISR_S2_DTIMSYNC
)
2765 mask2
|= ATH9K_INT_DTIMSYNC
;
2766 if (isr2
& (AR_ISR_S2_CABEND
))
2767 mask2
|= ATH9K_INT_CABEND
;
2768 if (isr2
& AR_ISR_S2_GTT
)
2769 mask2
|= ATH9K_INT_GTT
;
2770 if (isr2
& AR_ISR_S2_CST
)
2771 mask2
|= ATH9K_INT_CST
;
2772 if (isr2
& AR_ISR_S2_TSFOOR
)
2773 mask2
|= ATH9K_INT_TSFOOR
;
2776 isr
= REG_READ(ah
, AR_ISR_RAC
);
2777 if (isr
== 0xffffffff) {
2782 *masked
= isr
& ATH9K_INT_COMMON
;
2784 if (ah
->config
.intr_mitigation
) {
2785 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
2786 *masked
|= ATH9K_INT_RX
;
2789 if (isr
& (AR_ISR_RXOK
| AR_ISR_RXERR
))
2790 *masked
|= ATH9K_INT_RX
;
2792 (AR_ISR_TXOK
| AR_ISR_TXDESC
| AR_ISR_TXERR
|
2796 *masked
|= ATH9K_INT_TX
;
2798 s0_s
= REG_READ(ah
, AR_ISR_S0_S
);
2799 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXOK
);
2800 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXDESC
);
2802 s1_s
= REG_READ(ah
, AR_ISR_S1_S
);
2803 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXERR
);
2804 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXEOL
);
2807 if (isr
& AR_ISR_RXORN
) {
2808 ath_print(common
, ATH_DBG_INTERRUPT
,
2809 "receive FIFO overrun interrupt\n");
2812 if (!AR_SREV_9100(ah
)) {
2813 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2814 u32 isr5
= REG_READ(ah
, AR_ISR_S5_S
);
2815 if (isr5
& AR_ISR_S5_TIM_TIMER
)
2816 *masked
|= ATH9K_INT_TIM_TIMER
;
2823 if (AR_SREV_9100(ah
))
2826 if (isr
& AR_ISR_GENTMR
) {
2829 s5_s
= REG_READ(ah
, AR_ISR_S5_S
);
2830 if (isr
& AR_ISR_GENTMR
) {
2831 ah
->intr_gen_timer_trigger
=
2832 MS(s5_s
, AR_ISR_S5_GENTIMER_TRIG
);
2834 ah
->intr_gen_timer_thresh
=
2835 MS(s5_s
, AR_ISR_S5_GENTIMER_THRESH
);
2837 if (ah
->intr_gen_timer_trigger
)
2838 *masked
|= ATH9K_INT_GENTIMER
;
2846 (AR_INTR_SYNC_HOST1_FATAL
| AR_INTR_SYNC_HOST1_PERR
))
2850 if (sync_cause
& AR_INTR_SYNC_HOST1_FATAL
) {
2851 ath_print(common
, ATH_DBG_ANY
,
2852 "received PCI FATAL interrupt\n");
2854 if (sync_cause
& AR_INTR_SYNC_HOST1_PERR
) {
2855 ath_print(common
, ATH_DBG_ANY
,
2856 "received PCI PERR interrupt\n");
2858 *masked
|= ATH9K_INT_FATAL
;
2860 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
2861 ath_print(common
, ATH_DBG_INTERRUPT
,
2862 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2863 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
2864 REG_WRITE(ah
, AR_RC
, 0);
2865 *masked
|= ATH9K_INT_FATAL
;
2867 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
) {
2868 ath_print(common
, ATH_DBG_INTERRUPT
,
2869 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2872 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
2873 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
2878 EXPORT_SYMBOL(ath9k_hw_getisr
);
2880 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
)
2882 u32 omask
= ah
->mask_reg
;
2884 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2885 struct ath_common
*common
= ath9k_hw_common(ah
);
2887 ath_print(common
, ATH_DBG_INTERRUPT
, "0x%x => 0x%x\n", omask
, ints
);
2889 if (omask
& ATH9K_INT_GLOBAL
) {
2890 ath_print(common
, ATH_DBG_INTERRUPT
, "disable IER\n");
2891 REG_WRITE(ah
, AR_IER
, AR_IER_DISABLE
);
2892 (void) REG_READ(ah
, AR_IER
);
2893 if (!AR_SREV_9100(ah
)) {
2894 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
, 0);
2895 (void) REG_READ(ah
, AR_INTR_ASYNC_ENABLE
);
2897 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
2898 (void) REG_READ(ah
, AR_INTR_SYNC_ENABLE
);
2902 mask
= ints
& ATH9K_INT_COMMON
;
2905 if (ints
& ATH9K_INT_TX
) {
2906 if (ah
->txok_interrupt_mask
)
2907 mask
|= AR_IMR_TXOK
;
2908 if (ah
->txdesc_interrupt_mask
)
2909 mask
|= AR_IMR_TXDESC
;
2910 if (ah
->txerr_interrupt_mask
)
2911 mask
|= AR_IMR_TXERR
;
2912 if (ah
->txeol_interrupt_mask
)
2913 mask
|= AR_IMR_TXEOL
;
2915 if (ints
& ATH9K_INT_RX
) {
2916 mask
|= AR_IMR_RXERR
;
2917 if (ah
->config
.intr_mitigation
)
2918 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
2920 mask
|= AR_IMR_RXOK
| AR_IMR_RXDESC
;
2921 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
2922 mask
|= AR_IMR_GENTMR
;
2925 if (ints
& (ATH9K_INT_BMISC
)) {
2926 mask
|= AR_IMR_BCNMISC
;
2927 if (ints
& ATH9K_INT_TIM
)
2928 mask2
|= AR_IMR_S2_TIM
;
2929 if (ints
& ATH9K_INT_DTIM
)
2930 mask2
|= AR_IMR_S2_DTIM
;
2931 if (ints
& ATH9K_INT_DTIMSYNC
)
2932 mask2
|= AR_IMR_S2_DTIMSYNC
;
2933 if (ints
& ATH9K_INT_CABEND
)
2934 mask2
|= AR_IMR_S2_CABEND
;
2935 if (ints
& ATH9K_INT_TSFOOR
)
2936 mask2
|= AR_IMR_S2_TSFOOR
;
2939 if (ints
& (ATH9K_INT_GTT
| ATH9K_INT_CST
)) {
2940 mask
|= AR_IMR_BCNMISC
;
2941 if (ints
& ATH9K_INT_GTT
)
2942 mask2
|= AR_IMR_S2_GTT
;
2943 if (ints
& ATH9K_INT_CST
)
2944 mask2
|= AR_IMR_S2_CST
;
2947 ath_print(common
, ATH_DBG_INTERRUPT
, "new IMR 0x%x\n", mask
);
2948 REG_WRITE(ah
, AR_IMR
, mask
);
2949 mask
= REG_READ(ah
, AR_IMR_S2
) & ~(AR_IMR_S2_TIM
|
2951 AR_IMR_S2_DTIMSYNC
|
2955 AR_IMR_S2_GTT
| AR_IMR_S2_CST
);
2956 REG_WRITE(ah
, AR_IMR_S2
, mask
| mask2
);
2957 ah
->mask_reg
= ints
;
2959 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2960 if (ints
& ATH9K_INT_TIM_TIMER
)
2961 REG_SET_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2963 REG_CLR_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
2966 if (ints
& ATH9K_INT_GLOBAL
) {
2967 ath_print(common
, ATH_DBG_INTERRUPT
, "enable IER\n");
2968 REG_WRITE(ah
, AR_IER
, AR_IER_ENABLE
);
2969 if (!AR_SREV_9100(ah
)) {
2970 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
,
2972 REG_WRITE(ah
, AR_INTR_ASYNC_MASK
, AR_INTR_MAC_IRQ
);
2975 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
,
2976 AR_INTR_SYNC_DEFAULT
);
2977 REG_WRITE(ah
, AR_INTR_SYNC_MASK
,
2978 AR_INTR_SYNC_DEFAULT
);
2980 ath_print(common
, ATH_DBG_INTERRUPT
, "AR_IMR 0x%x IER 0x%x\n",
2981 REG_READ(ah
, AR_IMR
), REG_READ(ah
, AR_IER
));
2986 EXPORT_SYMBOL(ath9k_hw_set_interrupts
);
2988 /*******************/
2989 /* Beacon Handling */
2990 /*******************/
2992 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
2996 ah
->beacon_interval
= beacon_period
;
2998 switch (ah
->opmode
) {
2999 case NL80211_IFTYPE_STATION
:
3000 case NL80211_IFTYPE_MONITOR
:
3001 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
3002 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
3003 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
3004 flags
|= AR_TBTT_TIMER_EN
;
3006 case NL80211_IFTYPE_ADHOC
:
3007 case NL80211_IFTYPE_MESH_POINT
:
3008 REG_SET_BIT(ah
, AR_TXCFG
,
3009 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
3010 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
3011 TU_TO_USEC(next_beacon
+
3012 (ah
->atim_window
? ah
->
3014 flags
|= AR_NDP_TIMER_EN
;
3015 case NL80211_IFTYPE_AP
:
3016 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
3017 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
3018 TU_TO_USEC(next_beacon
-
3020 dma_beacon_response_time
));
3021 REG_WRITE(ah
, AR_NEXT_SWBA
,
3022 TU_TO_USEC(next_beacon
-
3024 sw_beacon_response_time
));
3026 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
3029 ath_print(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
3030 "%s: unsupported opmode: %d\n",
3031 __func__
, ah
->opmode
);
3036 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
3037 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
3038 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
3039 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
3041 beacon_period
&= ~ATH9K_BEACON_ENA
;
3042 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
3043 ath9k_hw_reset_tsf(ah
);
3046 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
3048 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
3050 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
3051 const struct ath9k_beacon_state
*bs
)
3053 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
3054 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3055 struct ath_common
*common
= ath9k_hw_common(ah
);
3057 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
3059 REG_WRITE(ah
, AR_BEACON_PERIOD
,
3060 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3061 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
3062 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3064 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
3065 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
3067 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
3069 if (bs
->bs_sleepduration
> beaconintval
)
3070 beaconintval
= bs
->bs_sleepduration
;
3072 dtimperiod
= bs
->bs_dtimperiod
;
3073 if (bs
->bs_sleepduration
> dtimperiod
)
3074 dtimperiod
= bs
->bs_sleepduration
;
3076 if (beaconintval
== dtimperiod
)
3077 nextTbtt
= bs
->bs_nextdtim
;
3079 nextTbtt
= bs
->bs_nexttbtt
;
3081 ath_print(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
3082 ath_print(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
3083 ath_print(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
3084 ath_print(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
3086 REG_WRITE(ah
, AR_NEXT_DTIM
,
3087 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
3088 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
3090 REG_WRITE(ah
, AR_SLEEP1
,
3091 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
3092 | AR_SLEEP1_ASSUME_DTIM
);
3094 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
3095 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
3097 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
3099 REG_WRITE(ah
, AR_SLEEP2
,
3100 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
3102 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
3103 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
3105 REG_SET_BIT(ah
, AR_TIMER_MODE
,
3106 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
3109 /* TSF Out of Range Threshold */
3110 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
3112 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
3114 /*******************/
3115 /* HW Capabilities */
3116 /*******************/
3118 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
3120 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3121 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3122 struct ath_common
*common
= ath9k_hw_common(ah
);
3123 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
3125 u16 capField
= 0, eeval
;
3127 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
3128 regulatory
->current_rd
= eeval
;
3130 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
3131 if (AR_SREV_9285_10_OR_LATER(ah
))
3132 eeval
|= AR9285_RDEXT_DEFAULT
;
3133 regulatory
->current_rd_ext
= eeval
;
3135 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
3137 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
3138 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
3139 if (regulatory
->current_rd
== 0x64 ||
3140 regulatory
->current_rd
== 0x65)
3141 regulatory
->current_rd
+= 5;
3142 else if (regulatory
->current_rd
== 0x41)
3143 regulatory
->current_rd
= 0x43;
3144 ath_print(common
, ATH_DBG_REGULATORY
,
3145 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
3148 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
3149 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
3150 ath_print(common
, ATH_DBG_FATAL
,
3151 "no band has been marked as supported in EEPROM.\n");
3155 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
3157 if (eeval
& AR5416_OPFLAGS_11A
) {
3158 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
3159 if (ah
->config
.ht_enable
) {
3160 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
3161 set_bit(ATH9K_MODE_11NA_HT20
,
3162 pCap
->wireless_modes
);
3163 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
3164 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
3165 pCap
->wireless_modes
);
3166 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
3167 pCap
->wireless_modes
);
3172 if (eeval
& AR5416_OPFLAGS_11G
) {
3173 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
3174 if (ah
->config
.ht_enable
) {
3175 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
3176 set_bit(ATH9K_MODE_11NG_HT20
,
3177 pCap
->wireless_modes
);
3178 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
3179 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
3180 pCap
->wireless_modes
);
3181 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
3182 pCap
->wireless_modes
);
3187 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
3189 * For AR9271 we will temporarilly uses the rx chainmax as read from
3192 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
3193 !(eeval
& AR5416_OPFLAGS_11A
) &&
3194 !(AR_SREV_9271(ah
)))
3195 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3196 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
3198 /* Use rx_chainmask from EEPROM. */
3199 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
3201 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
3202 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
3204 pCap
->low_2ghz_chan
= 2312;
3205 pCap
->high_2ghz_chan
= 2732;
3207 pCap
->low_5ghz_chan
= 4920;
3208 pCap
->high_5ghz_chan
= 6100;
3210 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
3211 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
3212 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
3214 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
3215 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
3216 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
3218 if (ah
->config
.ht_enable
)
3219 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
3221 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
3223 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
3224 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
3225 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
3226 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
3228 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
3229 pCap
->total_queues
=
3230 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
3232 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
3234 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
3235 pCap
->keycache_size
=
3236 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
3238 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
3240 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
3242 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
3243 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
>> 1;
3245 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
3247 if (AR_SREV_9285_10_OR_LATER(ah
))
3248 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
3249 else if (AR_SREV_9280_10_OR_LATER(ah
))
3250 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
3252 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
3254 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
3255 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
3256 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
3258 pCap
->rts_aggr_limit
= (8 * 1024);
3261 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
3263 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3264 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
3265 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
3267 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
3268 ah
->rfkill_polarity
=
3269 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
3271 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
3275 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
3277 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
3278 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
3280 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
3282 if (regulatory
->current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
3284 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3285 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
3286 AR_EEPROM_EEREGCAP_EN_KK_U2
|
3287 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
3290 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3291 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
3294 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3295 if (regulatory
->current_rd_ext
& (1 << REG_EXT_FCC_MIDBAND
) &&
3297 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
3299 pCap
->num_antcfg_5ghz
=
3300 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
3301 pCap
->num_antcfg_2ghz
=
3302 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
3304 if (AR_SREV_9280_10_OR_LATER(ah
) &&
3305 ath9k_hw_btcoex_supported(ah
)) {
3306 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO
;
3307 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO
;
3309 if (AR_SREV_9285(ah
)) {
3310 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
3311 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO
;
3313 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
3316 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
3322 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3323 u32 capability
, u32
*result
)
3325 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3327 case ATH9K_CAP_CIPHER
:
3328 switch (capability
) {
3329 case ATH9K_CIPHER_AES_CCM
:
3330 case ATH9K_CIPHER_AES_OCB
:
3331 case ATH9K_CIPHER_TKIP
:
3332 case ATH9K_CIPHER_WEP
:
3333 case ATH9K_CIPHER_MIC
:
3334 case ATH9K_CIPHER_CLR
:
3339 case ATH9K_CAP_TKIP_MIC
:
3340 switch (capability
) {
3344 return (ah
->sta_id1_defaults
&
3345 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
3348 case ATH9K_CAP_TKIP_SPLIT
:
3349 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
3351 case ATH9K_CAP_DIVERSITY
:
3352 return (REG_READ(ah
, AR_PHY_CCK_DETECT
) &
3353 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
) ?
3355 case ATH9K_CAP_MCAST_KEYSRCH
:
3356 switch (capability
) {
3360 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
3363 return (ah
->sta_id1_defaults
&
3364 AR_STA_ID1_MCAST_KSRCH
) ? true :
3369 case ATH9K_CAP_TXPOW
:
3370 switch (capability
) {
3374 *result
= regulatory
->power_limit
;
3377 *result
= regulatory
->max_power_level
;
3380 *result
= regulatory
->tp_scale
;
3385 return (AR_SREV_9280_20_OR_LATER(ah
) &&
3386 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
3392 EXPORT_SYMBOL(ath9k_hw_getcapability
);
3394 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3395 u32 capability
, u32 setting
, int *status
)
3400 case ATH9K_CAP_TKIP_MIC
:
3402 ah
->sta_id1_defaults
|=
3403 AR_STA_ID1_CRPT_MIC_ENABLE
;
3405 ah
->sta_id1_defaults
&=
3406 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
3408 case ATH9K_CAP_DIVERSITY
:
3409 v
= REG_READ(ah
, AR_PHY_CCK_DETECT
);
3411 v
|= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3413 v
&= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3414 REG_WRITE(ah
, AR_PHY_CCK_DETECT
, v
);
3416 case ATH9K_CAP_MCAST_KEYSRCH
:
3418 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
3420 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
3426 EXPORT_SYMBOL(ath9k_hw_setcapability
);
3428 /****************************/
3429 /* GPIO / RFKILL / Antennae */
3430 /****************************/
3432 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
3436 u32 gpio_shift
, tmp
;
3439 addr
= AR_GPIO_OUTPUT_MUX3
;
3441 addr
= AR_GPIO_OUTPUT_MUX2
;
3443 addr
= AR_GPIO_OUTPUT_MUX1
;
3445 gpio_shift
= (gpio
% 6) * 5;
3447 if (AR_SREV_9280_20_OR_LATER(ah
)
3448 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
3449 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
3450 (0x1f << gpio_shift
));
3452 tmp
= REG_READ(ah
, addr
);
3453 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
3454 tmp
&= ~(0x1f << gpio_shift
);
3455 tmp
|= (type
<< gpio_shift
);
3456 REG_WRITE(ah
, addr
, tmp
);
3460 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
3464 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
3466 gpio_shift
= gpio
<< 1;
3470 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
3471 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3473 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
3475 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
3477 #define MS_REG_READ(x, y) \
3478 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3480 if (gpio
>= ah
->caps
.num_gpio_pins
)
3483 if (AR_SREV_9287_10_OR_LATER(ah
))
3484 return MS_REG_READ(AR9287
, gpio
) != 0;
3485 else if (AR_SREV_9285_10_OR_LATER(ah
))
3486 return MS_REG_READ(AR9285
, gpio
) != 0;
3487 else if (AR_SREV_9280_10_OR_LATER(ah
))
3488 return MS_REG_READ(AR928X
, gpio
) != 0;
3490 return MS_REG_READ(AR
, gpio
) != 0;
3492 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
3494 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
3499 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
3501 gpio_shift
= 2 * gpio
;
3505 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
3506 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3508 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
3510 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
3512 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
3515 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
3517 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
3519 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
3521 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
3523 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
3525 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
3527 EXPORT_SYMBOL(ath9k_hw_setantenna
);
3529 /*********************/
3530 /* General Operation */
3531 /*********************/
3533 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
3535 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
3536 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
3538 if (phybits
& AR_PHY_ERR_RADAR
)
3539 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
3540 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
3541 bits
|= ATH9K_RX_FILTER_PHYERR
;
3545 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
3547 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
3551 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
3554 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
3555 phybits
|= AR_PHY_ERR_RADAR
;
3556 if (bits
& ATH9K_RX_FILTER_PHYERR
)
3557 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
3558 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
3561 REG_WRITE(ah
, AR_RXCFG
,
3562 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
3564 REG_WRITE(ah
, AR_RXCFG
,
3565 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
3567 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
3569 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
3571 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
3574 ath9k_hw_init_pll(ah
, NULL
);
3577 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
3579 bool ath9k_hw_disable(struct ath_hw
*ah
)
3581 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
3584 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
3587 ath9k_hw_init_pll(ah
, NULL
);
3590 EXPORT_SYMBOL(ath9k_hw_disable
);
3592 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
3594 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
3595 struct ath9k_channel
*chan
= ah
->curchan
;
3596 struct ieee80211_channel
*channel
= chan
->chan
;
3598 regulatory
->power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
3600 ah
->eep_ops
->set_txpower(ah
, chan
,
3601 ath9k_regd_get_ctl(regulatory
, chan
),
3602 channel
->max_antenna_gain
* 2,
3603 channel
->max_power
* 2,
3604 min((u32
) MAX_RATE_POWER
,
3605 (u32
) regulatory
->power_limit
));
3607 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
3609 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
3611 memcpy(ath9k_hw_common(ah
)->macaddr
, mac
, ETH_ALEN
);
3613 EXPORT_SYMBOL(ath9k_hw_setmac
);
3615 void ath9k_hw_setopmode(struct ath_hw
*ah
)
3617 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
3619 EXPORT_SYMBOL(ath9k_hw_setopmode
);
3621 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
3623 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
3624 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
3626 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
3628 void ath9k_hw_write_associd(struct ath_hw
*ah
)
3630 struct ath_common
*common
= ath9k_hw_common(ah
);
3632 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
3633 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
3634 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
3636 EXPORT_SYMBOL(ath9k_hw_write_associd
);
3638 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
3642 tsf
= REG_READ(ah
, AR_TSF_U32
);
3643 tsf
= (tsf
<< 32) | REG_READ(ah
, AR_TSF_L32
);
3647 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
3649 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
3651 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
3652 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
3654 EXPORT_SYMBOL(ath9k_hw_settsf64
);
3656 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
3658 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
3659 AH_TSF_WRITE_TIMEOUT
))
3660 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
3661 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3663 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
3665 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
3667 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
3670 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
3672 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
3674 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
3677 * Extend 15-bit time stamp from rx descriptor to
3678 * a full 64-bit TSF using the current h/w TSF.
3680 u64
ath9k_hw_extend_tsf(struct ath_hw
*ah
, u32 rstamp
)
3684 tsf
= ath9k_hw_gettsf64(ah
);
3685 if ((tsf
& 0x7fff) < rstamp
)
3687 return (tsf
& ~0x7fff) | rstamp
;
3689 EXPORT_SYMBOL(ath9k_hw_extend_tsf
);
3691 bool ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
3693 if (us
< ATH9K_SLOT_TIME_9
|| us
> ath9k_hw_mac_to_usec(ah
, 0xffff)) {
3694 ath_print(ath9k_hw_common(ah
), ATH_DBG_RESET
,
3695 "bad slot time %u\n", us
);
3696 ah
->slottime
= (u32
) -1;
3699 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, ath9k_hw_mac_to_clks(ah
, us
));
3704 EXPORT_SYMBOL(ath9k_hw_setslottime
);
3706 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
3708 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
3711 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
3712 macmode
= AR_2040_JOINED_RX_CLEAR
;
3716 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
3719 /* HW Generic timers configuration */
3721 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
3723 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3724 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3725 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3726 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3727 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3728 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3729 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3730 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
3731 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
3732 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
3733 AR_NDP2_TIMER_MODE
, 0x0002},
3734 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
3735 AR_NDP2_TIMER_MODE
, 0x0004},
3736 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
3737 AR_NDP2_TIMER_MODE
, 0x0008},
3738 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
3739 AR_NDP2_TIMER_MODE
, 0x0010},
3740 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
3741 AR_NDP2_TIMER_MODE
, 0x0020},
3742 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
3743 AR_NDP2_TIMER_MODE
, 0x0040},
3744 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
3745 AR_NDP2_TIMER_MODE
, 0x0080}
3748 /* HW generic timer primitives */
3750 /* compute and clear index of rightmost 1 */
3751 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
3761 return timer_table
->gen_timer_index
[b
];
3764 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
3766 return REG_READ(ah
, AR_TSF_L32
);
3768 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
3770 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
3771 void (*trigger
)(void *),
3772 void (*overflow
)(void *),
3776 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3777 struct ath_gen_timer
*timer
;
3779 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
3781 if (timer
== NULL
) {
3782 ath_print(ath9k_hw_common(ah
), ATH_DBG_FATAL
,
3783 "Failed to allocate memory"
3784 "for hw timer[%d]\n", timer_index
);
3788 /* allocate a hardware generic timer slot */
3789 timer_table
->timers
[timer_index
] = timer
;
3790 timer
->index
= timer_index
;
3791 timer
->trigger
= trigger
;
3792 timer
->overflow
= overflow
;
3797 EXPORT_SYMBOL(ath_gen_timer_alloc
);
3799 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
3800 struct ath_gen_timer
*timer
,
3804 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3807 BUG_ON(!timer_period
);
3809 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3811 tsf
= ath9k_hw_gettsf32(ah
);
3813 ath_print(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
3814 "curent tsf %x period %x"
3815 "timer_next %x\n", tsf
, timer_period
, timer_next
);
3818 * Pull timer_next forward if the current TSF already passed it
3819 * because of software latency
3821 if (timer_next
< tsf
)
3822 timer_next
= tsf
+ timer_period
;
3825 * Program generic timer registers
3827 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
3829 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
3831 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3832 gen_tmr_configuration
[timer
->index
].mode_mask
);
3834 /* Enable both trigger and thresh interrupt masks */
3835 REG_SET_BIT(ah
, AR_IMR_S5
,
3836 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3837 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3839 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
3841 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3843 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3845 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
3846 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
3850 /* Clear generic timer enable bits. */
3851 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
3852 gen_tmr_configuration
[timer
->index
].mode_mask
);
3854 /* Disable both trigger and thresh interrupt masks */
3855 REG_CLR_BIT(ah
, AR_IMR_S5
,
3856 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
3857 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
3859 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
3861 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
3863 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
3865 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3867 /* free the hardware generic timer slot */
3868 timer_table
->timers
[timer
->index
] = NULL
;
3871 EXPORT_SYMBOL(ath_gen_timer_free
);
3874 * Generic Timer Interrupts handling
3876 void ath_gen_timer_isr(struct ath_hw
*ah
)
3878 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
3879 struct ath_gen_timer
*timer
;
3880 struct ath_common
*common
= ath9k_hw_common(ah
);
3881 u32 trigger_mask
, thresh_mask
, index
;
3883 /* get hardware generic timer interrupt status */
3884 trigger_mask
= ah
->intr_gen_timer_trigger
;
3885 thresh_mask
= ah
->intr_gen_timer_thresh
;
3886 trigger_mask
&= timer_table
->timer_mask
.val
;
3887 thresh_mask
&= timer_table
->timer_mask
.val
;
3889 trigger_mask
&= ~thresh_mask
;
3891 while (thresh_mask
) {
3892 index
= rightmost_index(timer_table
, &thresh_mask
);
3893 timer
= timer_table
->timers
[index
];
3895 ath_print(common
, ATH_DBG_HWTIMER
,
3896 "TSF overflow for Gen timer %d\n", index
);
3897 timer
->overflow(timer
->arg
);
3900 while (trigger_mask
) {
3901 index
= rightmost_index(timer_table
, &trigger_mask
);
3902 timer
= timer_table
->timers
[index
];
3904 ath_print(common
, ATH_DBG_HWTIMER
,
3905 "Gen timer[%d] trigger\n", index
);
3906 timer
->trigger(timer
->arg
);
3909 EXPORT_SYMBOL(ath_gen_timer_isr
);
3914 } ath_mac_bb_names
[] = {
3915 /* Devices with external radios */
3916 { AR_SREV_VERSION_5416_PCI
, "5416" },
3917 { AR_SREV_VERSION_5416_PCIE
, "5418" },
3918 { AR_SREV_VERSION_9100
, "9100" },
3919 { AR_SREV_VERSION_9160
, "9160" },
3920 /* Single-chip solutions */
3921 { AR_SREV_VERSION_9280
, "9280" },
3922 { AR_SREV_VERSION_9285
, "9285" },
3923 { AR_SREV_VERSION_9287
, "9287" },
3924 { AR_SREV_VERSION_9271
, "9271" },
3927 /* For devices with external radios */
3931 } ath_rf_names
[] = {
3933 { AR_RAD5133_SREV_MAJOR
, "5133" },
3934 { AR_RAD5122_SREV_MAJOR
, "5122" },
3935 { AR_RAD2133_SREV_MAJOR
, "2133" },
3936 { AR_RAD2122_SREV_MAJOR
, "2122" }
3940 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3942 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
3946 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
3947 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
3948 return ath_mac_bb_names
[i
].name
;
3956 * Return the RF name. "????" is returned if the RF is unknown.
3957 * Used for devices with external radios.
3959 static const char *ath9k_hw_rf_name(u16 rf_version
)
3963 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
3964 if (ath_rf_names
[i
].version
== rf_version
) {
3965 return ath_rf_names
[i
].name
;
3972 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
3976 /* chipsets >= AR9280 are single-chip */
3977 if (AR_SREV_9280_10_OR_LATER(ah
)) {
3978 used
= snprintf(hw_name
, len
,
3979 "Atheros AR%s Rev:%x",
3980 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3981 ah
->hw_version
.macRev
);
3984 used
= snprintf(hw_name
, len
,
3985 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3986 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
3987 ah
->hw_version
.macRev
,
3988 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
3989 AR_RADIO_SREV_MAJOR
)),
3990 ah
->hw_version
.phyRev
);
3993 hw_name
[used
] = '\0';
3995 EXPORT_SYMBOL(ath9k_hw_name
);