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Merge branch 'for-upstream' of git://openrisc.net/jonas/linux
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
21
22 #include "hw.h"
23 #include "hw-ops.h"
24 #include "rc.h"
25 #include "ar9003_mac.h"
26 #include "ar9003_mci.h"
27 #include "ar9003_phy.h"
28 #include "debug.h"
29 #include "ath9k.h"
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
37
38 static int __init ath9k_init(void)
39 {
40 return 0;
41 }
42 module_init(ath9k_init);
43
44 static void __exit ath9k_exit(void)
45 {
46 return;
47 }
48 module_exit(ath9k_exit);
49
50 /* Private hardware callbacks */
51
52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 #ifdef CONFIG_ATH9K_DEBUGFS
85
86 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
87 {
88 struct ath_softc *sc = common->priv;
89 if (sync_cause)
90 sc->debug.stats.istats.sync_cause_all++;
91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
92 sc->debug.stats.istats.sync_rtc_irq++;
93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
94 sc->debug.stats.istats.sync_mac_irq++;
95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
96 sc->debug.stats.istats.eeprom_illegal_access++;
97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
98 sc->debug.stats.istats.apb_timeout++;
99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
100 sc->debug.stats.istats.pci_mode_conflict++;
101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
102 sc->debug.stats.istats.host1_fatal++;
103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
104 sc->debug.stats.istats.host1_perr++;
105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
106 sc->debug.stats.istats.trcv_fifo_perr++;
107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
108 sc->debug.stats.istats.radm_cpl_ep++;
109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
110 sc->debug.stats.istats.radm_cpl_dllp_abort++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
112 sc->debug.stats.istats.radm_cpl_tlp_abort++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
114 sc->debug.stats.istats.radm_cpl_ecrc_err++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
116 sc->debug.stats.istats.radm_cpl_timeout++;
117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
118 sc->debug.stats.istats.local_timeout++;
119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
120 sc->debug.stats.istats.pm_access++;
121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
122 sc->debug.stats.istats.mac_awake++;
123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
124 sc->debug.stats.istats.mac_asleep++;
125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
126 sc->debug.stats.istats.mac_sleep_access++;
127 }
128 #endif
129
130
131 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
132 {
133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
134 struct ath_common *common = ath9k_hw_common(ah);
135 unsigned int clockrate;
136
137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
139 clockrate = 117;
140 else if (!ah->curchan) /* should really check for CCK instead */
141 clockrate = ATH9K_CLOCK_RATE_CCK;
142 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
146 else
147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
148
149 if (conf_is_ht40(conf))
150 clockrate *= 2;
151
152 if (ah->curchan) {
153 if (IS_CHAN_HALF_RATE(ah->curchan))
154 clockrate /= 2;
155 if (IS_CHAN_QUARTER_RATE(ah->curchan))
156 clockrate /= 4;
157 }
158
159 common->clockrate = clockrate;
160 }
161
162 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
163 {
164 struct ath_common *common = ath9k_hw_common(ah);
165
166 return usecs * common->clockrate;
167 }
168
169 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
170 {
171 int i;
172
173 BUG_ON(timeout < AH_TIME_QUANTUM);
174
175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
176 if ((REG_READ(ah, reg) & mask) == val)
177 return true;
178
179 udelay(AH_TIME_QUANTUM);
180 }
181
182 ath_dbg(ath9k_hw_common(ah), ANY,
183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
184 timeout, reg, REG_READ(ah, reg), mask, val);
185
186 return false;
187 }
188 EXPORT_SYMBOL(ath9k_hw_wait);
189
190 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
191 int hw_delay)
192 {
193 if (IS_CHAN_B(chan))
194 hw_delay = (4 * hw_delay) / 22;
195 else
196 hw_delay /= 10;
197
198 if (IS_CHAN_HALF_RATE(chan))
199 hw_delay *= 2;
200 else if (IS_CHAN_QUARTER_RATE(chan))
201 hw_delay *= 4;
202
203 udelay(hw_delay + BASE_ACTIVATE_DELAY);
204 }
205
206 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
207 int column, unsigned int *writecnt)
208 {
209 int r;
210
211 ENABLE_REGWRITE_BUFFER(ah);
212 for (r = 0; r < array->ia_rows; r++) {
213 REG_WRITE(ah, INI_RA(array, r, 0),
214 INI_RA(array, r, column));
215 DO_DELAY(*writecnt);
216 }
217 REGWRITE_BUFFER_FLUSH(ah);
218 }
219
220 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
221 {
222 u32 retval;
223 int i;
224
225 for (i = 0, retval = 0; i < n; i++) {
226 retval = (retval << 1) | (val & 1);
227 val >>= 1;
228 }
229 return retval;
230 }
231
232 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
233 u8 phy, int kbps,
234 u32 frameLen, u16 rateix,
235 bool shortPreamble)
236 {
237 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
238
239 if (kbps == 0)
240 return 0;
241
242 switch (phy) {
243 case WLAN_RC_PHY_CCK:
244 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
245 if (shortPreamble)
246 phyTime >>= 1;
247 numBits = frameLen << 3;
248 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
249 break;
250 case WLAN_RC_PHY_OFDM:
251 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
252 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
253 numBits = OFDM_PLCP_BITS + (frameLen << 3);
254 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
255 txTime = OFDM_SIFS_TIME_QUARTER
256 + OFDM_PREAMBLE_TIME_QUARTER
257 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
258 } else if (ah->curchan &&
259 IS_CHAN_HALF_RATE(ah->curchan)) {
260 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
261 numBits = OFDM_PLCP_BITS + (frameLen << 3);
262 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
263 txTime = OFDM_SIFS_TIME_HALF +
264 OFDM_PREAMBLE_TIME_HALF
265 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
266 } else {
267 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
268 numBits = OFDM_PLCP_BITS + (frameLen << 3);
269 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
270 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
271 + (numSymbols * OFDM_SYMBOL_TIME);
272 }
273 break;
274 default:
275 ath_err(ath9k_hw_common(ah),
276 "Unknown phy %u (rate ix %u)\n", phy, rateix);
277 txTime = 0;
278 break;
279 }
280
281 return txTime;
282 }
283 EXPORT_SYMBOL(ath9k_hw_computetxtime);
284
285 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
286 struct ath9k_channel *chan,
287 struct chan_centers *centers)
288 {
289 int8_t extoff;
290
291 if (!IS_CHAN_HT40(chan)) {
292 centers->ctl_center = centers->ext_center =
293 centers->synth_center = chan->channel;
294 return;
295 }
296
297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
298 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
299 centers->synth_center =
300 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
301 extoff = 1;
302 } else {
303 centers->synth_center =
304 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
305 extoff = -1;
306 }
307
308 centers->ctl_center =
309 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
310 /* 25 MHz spacing is supported by hw but not on upper layers */
311 centers->ext_center =
312 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
313 }
314
315 /******************/
316 /* Chip Revisions */
317 /******************/
318
319 static void ath9k_hw_read_revisions(struct ath_hw *ah)
320 {
321 u32 val;
322
323 switch (ah->hw_version.devid) {
324 case AR5416_AR9100_DEVID:
325 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
326 break;
327 case AR9300_DEVID_AR9330:
328 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
329 if (ah->get_mac_revision) {
330 ah->hw_version.macRev = ah->get_mac_revision();
331 } else {
332 val = REG_READ(ah, AR_SREV);
333 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
334 }
335 return;
336 case AR9300_DEVID_AR9340:
337 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
338 val = REG_READ(ah, AR_SREV);
339 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
340 return;
341 case AR9300_DEVID_QCA955X:
342 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
343 return;
344 }
345
346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
347
348 if (val == 0xFF) {
349 val = REG_READ(ah, AR_SREV);
350 ah->hw_version.macVersion =
351 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
352 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
353
354 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
355 ah->is_pciexpress = true;
356 else
357 ah->is_pciexpress = (val &
358 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
359 } else {
360 if (!AR_SREV_9100(ah))
361 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
362
363 ah->hw_version.macRev = val & AR_SREV_REVISION;
364
365 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
366 ah->is_pciexpress = true;
367 }
368 }
369
370 /************************************/
371 /* HW Attach, Detach, Init Routines */
372 /************************************/
373
374 static void ath9k_hw_disablepcie(struct ath_hw *ah)
375 {
376 if (!AR_SREV_5416(ah))
377 return;
378
379 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
385 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
386 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
387 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
388
389 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
390 }
391
392 /* This should work for all families including legacy */
393 static bool ath9k_hw_chip_test(struct ath_hw *ah)
394 {
395 struct ath_common *common = ath9k_hw_common(ah);
396 u32 regAddr[2] = { AR_STA_ID0 };
397 u32 regHold[2];
398 static const u32 patternData[4] = {
399 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
400 };
401 int i, j, loop_max;
402
403 if (!AR_SREV_9300_20_OR_LATER(ah)) {
404 loop_max = 2;
405 regAddr[1] = AR_PHY_BASE + (8 << 2);
406 } else
407 loop_max = 1;
408
409 for (i = 0; i < loop_max; i++) {
410 u32 addr = regAddr[i];
411 u32 wrData, rdData;
412
413 regHold[i] = REG_READ(ah, addr);
414 for (j = 0; j < 0x100; j++) {
415 wrData = (j << 16) | j;
416 REG_WRITE(ah, addr, wrData);
417 rdData = REG_READ(ah, addr);
418 if (rdData != wrData) {
419 ath_err(common,
420 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
421 addr, wrData, rdData);
422 return false;
423 }
424 }
425 for (j = 0; j < 4; j++) {
426 wrData = patternData[j];
427 REG_WRITE(ah, addr, wrData);
428 rdData = REG_READ(ah, addr);
429 if (wrData != rdData) {
430 ath_err(common,
431 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
432 addr, wrData, rdData);
433 return false;
434 }
435 }
436 REG_WRITE(ah, regAddr[i], regHold[i]);
437 }
438 udelay(100);
439
440 return true;
441 }
442
443 static void ath9k_hw_init_config(struct ath_hw *ah)
444 {
445 int i;
446
447 ah->config.dma_beacon_response_time = 1;
448 ah->config.sw_beacon_response_time = 6;
449 ah->config.additional_swba_backoff = 0;
450 ah->config.ack_6mb = 0x0;
451 ah->config.cwm_ignore_extcca = 0;
452 ah->config.pcie_clock_req = 0;
453 ah->config.pcie_waen = 0;
454 ah->config.analog_shiftreg = 1;
455 ah->config.enable_ani = true;
456
457 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
458 ah->config.spurchans[i][0] = AR_NO_SPUR;
459 ah->config.spurchans[i][1] = AR_NO_SPUR;
460 }
461
462 ah->config.rx_intr_mitigation = true;
463 ah->config.pcieSerDesWrite = true;
464
465 /*
466 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
467 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
468 * This means we use it for all AR5416 devices, and the few
469 * minor PCI AR9280 devices out there.
470 *
471 * Serialization is required because these devices do not handle
472 * well the case of two concurrent reads/writes due to the latency
473 * involved. During one read/write another read/write can be issued
474 * on another CPU while the previous read/write may still be working
475 * on our hardware, if we hit this case the hardware poops in a loop.
476 * We prevent this by serializing reads and writes.
477 *
478 * This issue is not present on PCI-Express devices or pre-AR5416
479 * devices (legacy, 802.11abg).
480 */
481 if (num_possible_cpus() > 1)
482 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
483 }
484
485 static void ath9k_hw_init_defaults(struct ath_hw *ah)
486 {
487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
488
489 regulatory->country_code = CTRY_DEFAULT;
490 regulatory->power_limit = MAX_RATE_POWER;
491
492 ah->hw_version.magic = AR5416_MAGIC;
493 ah->hw_version.subvendorid = 0;
494
495 ah->atim_window = 0;
496 ah->sta_id1_defaults =
497 AR_STA_ID1_CRPT_MIC_ENABLE |
498 AR_STA_ID1_MCAST_KSRCH;
499 if (AR_SREV_9100(ah))
500 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
501 ah->slottime = ATH9K_SLOT_TIME_9;
502 ah->globaltxtimeout = (u32) -1;
503 ah->power_mode = ATH9K_PM_UNDEFINED;
504 ah->htc_reset_init = true;
505 }
506
507 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
508 {
509 struct ath_common *common = ath9k_hw_common(ah);
510 u32 sum;
511 int i;
512 u16 eeval;
513 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
514
515 sum = 0;
516 for (i = 0; i < 3; i++) {
517 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
518 sum += eeval;
519 common->macaddr[2 * i] = eeval >> 8;
520 common->macaddr[2 * i + 1] = eeval & 0xff;
521 }
522 if (sum == 0 || sum == 0xffff * 3)
523 return -EADDRNOTAVAIL;
524
525 return 0;
526 }
527
528 static int ath9k_hw_post_init(struct ath_hw *ah)
529 {
530 struct ath_common *common = ath9k_hw_common(ah);
531 int ecode;
532
533 if (common->bus_ops->ath_bus_type != ATH_USB) {
534 if (!ath9k_hw_chip_test(ah))
535 return -ENODEV;
536 }
537
538 if (!AR_SREV_9300_20_OR_LATER(ah)) {
539 ecode = ar9002_hw_rf_claim(ah);
540 if (ecode != 0)
541 return ecode;
542 }
543
544 ecode = ath9k_hw_eeprom_init(ah);
545 if (ecode != 0)
546 return ecode;
547
548 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
549 ah->eep_ops->get_eeprom_ver(ah),
550 ah->eep_ops->get_eeprom_rev(ah));
551
552 if (ah->config.enable_ani)
553 ath9k_hw_ani_init(ah);
554
555 return 0;
556 }
557
558 static int ath9k_hw_attach_ops(struct ath_hw *ah)
559 {
560 if (!AR_SREV_9300_20_OR_LATER(ah))
561 return ar9002_hw_attach_ops(ah);
562
563 ar9003_hw_attach_ops(ah);
564 return 0;
565 }
566
567 /* Called for all hardware families */
568 static int __ath9k_hw_init(struct ath_hw *ah)
569 {
570 struct ath_common *common = ath9k_hw_common(ah);
571 int r = 0;
572
573 ath9k_hw_read_revisions(ah);
574
575 /*
576 * Read back AR_WA into a permanent copy and set bits 14 and 17.
577 * We need to do this to avoid RMW of this register. We cannot
578 * read the reg when chip is asleep.
579 */
580 ah->WARegVal = REG_READ(ah, AR_WA);
581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
582 AR_WA_ASPM_TIMER_BASED_DISABLE);
583
584 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
585 ath_err(common, "Couldn't reset chip\n");
586 return -EIO;
587 }
588
589 if (AR_SREV_9462(ah))
590 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
591
592 if (AR_SREV_9565(ah)) {
593 ah->WARegVal |= AR_WA_BIT22;
594 REG_WRITE(ah, AR_WA, ah->WARegVal);
595 }
596
597 ath9k_hw_init_defaults(ah);
598 ath9k_hw_init_config(ah);
599
600 r = ath9k_hw_attach_ops(ah);
601 if (r)
602 return r;
603
604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
605 ath_err(common, "Couldn't wakeup chip\n");
606 return -EIO;
607 }
608
609 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
610 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
611 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
612 !ah->is_pciexpress)) {
613 ah->config.serialize_regmode =
614 SER_REG_MODE_ON;
615 } else {
616 ah->config.serialize_regmode =
617 SER_REG_MODE_OFF;
618 }
619 }
620
621 ath_dbg(common, RESET, "serialize_regmode is %d\n",
622 ah->config.serialize_regmode);
623
624 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
625 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
626 else
627 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
628
629 switch (ah->hw_version.macVersion) {
630 case AR_SREV_VERSION_5416_PCI:
631 case AR_SREV_VERSION_5416_PCIE:
632 case AR_SREV_VERSION_9160:
633 case AR_SREV_VERSION_9100:
634 case AR_SREV_VERSION_9280:
635 case AR_SREV_VERSION_9285:
636 case AR_SREV_VERSION_9287:
637 case AR_SREV_VERSION_9271:
638 case AR_SREV_VERSION_9300:
639 case AR_SREV_VERSION_9330:
640 case AR_SREV_VERSION_9485:
641 case AR_SREV_VERSION_9340:
642 case AR_SREV_VERSION_9462:
643 case AR_SREV_VERSION_9550:
644 case AR_SREV_VERSION_9565:
645 break;
646 default:
647 ath_err(common,
648 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
649 ah->hw_version.macVersion, ah->hw_version.macRev);
650 return -EOPNOTSUPP;
651 }
652
653 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
654 AR_SREV_9330(ah) || AR_SREV_9550(ah))
655 ah->is_pciexpress = false;
656
657 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
658 ath9k_hw_init_cal_settings(ah);
659
660 ah->ani_function = ATH9K_ANI_ALL;
661 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
662 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
663 if (!AR_SREV_9300_20_OR_LATER(ah))
664 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
665
666 if (!ah->is_pciexpress)
667 ath9k_hw_disablepcie(ah);
668
669 r = ath9k_hw_post_init(ah);
670 if (r)
671 return r;
672
673 ath9k_hw_init_mode_gain_regs(ah);
674 r = ath9k_hw_fill_cap_info(ah);
675 if (r)
676 return r;
677
678 r = ath9k_hw_init_macaddr(ah);
679 if (r) {
680 ath_err(common, "Failed to initialize MAC address\n");
681 return r;
682 }
683
684 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
685 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
686 else
687 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
688
689 if (AR_SREV_9330(ah))
690 ah->bb_watchdog_timeout_ms = 85;
691 else
692 ah->bb_watchdog_timeout_ms = 25;
693
694 common->state = ATH_HW_INITIALIZED;
695
696 return 0;
697 }
698
699 int ath9k_hw_init(struct ath_hw *ah)
700 {
701 int ret;
702 struct ath_common *common = ath9k_hw_common(ah);
703
704 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
705 switch (ah->hw_version.devid) {
706 case AR5416_DEVID_PCI:
707 case AR5416_DEVID_PCIE:
708 case AR5416_AR9100_DEVID:
709 case AR9160_DEVID_PCI:
710 case AR9280_DEVID_PCI:
711 case AR9280_DEVID_PCIE:
712 case AR9285_DEVID_PCIE:
713 case AR9287_DEVID_PCI:
714 case AR9287_DEVID_PCIE:
715 case AR2427_DEVID_PCIE:
716 case AR9300_DEVID_PCIE:
717 case AR9300_DEVID_AR9485_PCIE:
718 case AR9300_DEVID_AR9330:
719 case AR9300_DEVID_AR9340:
720 case AR9300_DEVID_QCA955X:
721 case AR9300_DEVID_AR9580:
722 case AR9300_DEVID_AR9462:
723 case AR9485_DEVID_AR1111:
724 case AR9300_DEVID_AR9565:
725 break;
726 default:
727 if (common->bus_ops->ath_bus_type == ATH_USB)
728 break;
729 ath_err(common, "Hardware device ID 0x%04x not supported\n",
730 ah->hw_version.devid);
731 return -EOPNOTSUPP;
732 }
733
734 ret = __ath9k_hw_init(ah);
735 if (ret) {
736 ath_err(common,
737 "Unable to initialize hardware; initialization status: %d\n",
738 ret);
739 return ret;
740 }
741
742 return 0;
743 }
744 EXPORT_SYMBOL(ath9k_hw_init);
745
746 static void ath9k_hw_init_qos(struct ath_hw *ah)
747 {
748 ENABLE_REGWRITE_BUFFER(ah);
749
750 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
751 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
752
753 REG_WRITE(ah, AR_QOS_NO_ACK,
754 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
755 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
756 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
757
758 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
759 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
760 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
761 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
762 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
763
764 REGWRITE_BUFFER_FLUSH(ah);
765 }
766
767 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
768 {
769 struct ath_common *common = ath9k_hw_common(ah);
770 int i = 0;
771
772 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
773 udelay(100);
774 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
775
776 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
777
778 udelay(100);
779
780 if (WARN_ON_ONCE(i >= 100)) {
781 ath_err(common, "PLL4 meaurement not done\n");
782 break;
783 }
784
785 i++;
786 }
787
788 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
789 }
790 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
791
792 static void ath9k_hw_init_pll(struct ath_hw *ah,
793 struct ath9k_channel *chan)
794 {
795 u32 pll;
796
797 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
798 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
800 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
801 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
802 AR_CH0_DPLL2_KD, 0x40);
803 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
804 AR_CH0_DPLL2_KI, 0x4);
805
806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
807 AR_CH0_BB_DPLL1_REFDIV, 0x5);
808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
809 AR_CH0_BB_DPLL1_NINI, 0x58);
810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
811 AR_CH0_BB_DPLL1_NFRAC, 0x0);
812
813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
814 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
816 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
818 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
819
820 /* program BB PLL phase_shift to 0x6 */
821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
822 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
823
824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
825 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
826 udelay(1000);
827 } else if (AR_SREV_9330(ah)) {
828 u32 ddr_dpll2, pll_control2, kd;
829
830 if (ah->is_clk_25mhz) {
831 ddr_dpll2 = 0x18e82f01;
832 pll_control2 = 0xe04a3d;
833 kd = 0x1d;
834 } else {
835 ddr_dpll2 = 0x19e82f01;
836 pll_control2 = 0x886666;
837 kd = 0x3d;
838 }
839
840 /* program DDR PLL ki and kd value */
841 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
842
843 /* program DDR PLL phase_shift */
844 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
845 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
846
847 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
848 udelay(1000);
849
850 /* program refdiv, nint, frac to RTC register */
851 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
852
853 /* program BB PLL kd and ki value */
854 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
855 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
856
857 /* program BB PLL phase_shift */
858 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
859 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
860 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
861 u32 regval, pll2_divint, pll2_divfrac, refdiv;
862
863 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
864 udelay(1000);
865
866 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
867 udelay(100);
868
869 if (ah->is_clk_25mhz) {
870 pll2_divint = 0x54;
871 pll2_divfrac = 0x1eb85;
872 refdiv = 3;
873 } else {
874 if (AR_SREV_9340(ah)) {
875 pll2_divint = 88;
876 pll2_divfrac = 0;
877 refdiv = 5;
878 } else {
879 pll2_divint = 0x11;
880 pll2_divfrac = 0x26666;
881 refdiv = 1;
882 }
883 }
884
885 regval = REG_READ(ah, AR_PHY_PLL_MODE);
886 regval |= (0x1 << 16);
887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
888 udelay(100);
889
890 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
891 (pll2_divint << 18) | pll2_divfrac);
892 udelay(100);
893
894 regval = REG_READ(ah, AR_PHY_PLL_MODE);
895 if (AR_SREV_9340(ah))
896 regval = (regval & 0x80071fff) | (0x1 << 30) |
897 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
898 else
899 regval = (regval & 0x80071fff) | (0x3 << 30) |
900 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
901 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
902 REG_WRITE(ah, AR_PHY_PLL_MODE,
903 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
904 udelay(1000);
905 }
906
907 pll = ath9k_hw_compute_pll_control(ah, chan);
908 if (AR_SREV_9565(ah))
909 pll |= 0x40000;
910 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
911
912 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
913 AR_SREV_9550(ah))
914 udelay(1000);
915
916 /* Switch the core clock for ar9271 to 117Mhz */
917 if (AR_SREV_9271(ah)) {
918 udelay(500);
919 REG_WRITE(ah, 0x50040, 0x304);
920 }
921
922 udelay(RTC_PLL_SETTLE_DELAY);
923
924 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
925
926 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
927 if (ah->is_clk_25mhz) {
928 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
929 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
930 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
931 } else {
932 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
933 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
934 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
935 }
936 udelay(100);
937 }
938 }
939
940 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
941 enum nl80211_iftype opmode)
942 {
943 u32 sync_default = AR_INTR_SYNC_DEFAULT;
944 u32 imr_reg = AR_IMR_TXERR |
945 AR_IMR_TXURN |
946 AR_IMR_RXERR |
947 AR_IMR_RXORN |
948 AR_IMR_BCNMISC;
949
950 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
951 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
952
953 if (AR_SREV_9300_20_OR_LATER(ah)) {
954 imr_reg |= AR_IMR_RXOK_HP;
955 if (ah->config.rx_intr_mitigation)
956 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
957 else
958 imr_reg |= AR_IMR_RXOK_LP;
959
960 } else {
961 if (ah->config.rx_intr_mitigation)
962 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
963 else
964 imr_reg |= AR_IMR_RXOK;
965 }
966
967 if (ah->config.tx_intr_mitigation)
968 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
969 else
970 imr_reg |= AR_IMR_TXOK;
971
972 ENABLE_REGWRITE_BUFFER(ah);
973
974 REG_WRITE(ah, AR_IMR, imr_reg);
975 ah->imrs2_reg |= AR_IMR_S2_GTT;
976 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
977
978 if (!AR_SREV_9100(ah)) {
979 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
980 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
981 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
982 }
983
984 REGWRITE_BUFFER_FLUSH(ah);
985
986 if (AR_SREV_9300_20_OR_LATER(ah)) {
987 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
988 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
989 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
990 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
991 }
992 }
993
994 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
995 {
996 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
997 val = min(val, (u32) 0xFFFF);
998 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
999 }
1000
1001 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1002 {
1003 u32 val = ath9k_hw_mac_to_clks(ah, us);
1004 val = min(val, (u32) 0xFFFF);
1005 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1006 }
1007
1008 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1009 {
1010 u32 val = ath9k_hw_mac_to_clks(ah, us);
1011 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1012 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1013 }
1014
1015 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1016 {
1017 u32 val = ath9k_hw_mac_to_clks(ah, us);
1018 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1019 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1020 }
1021
1022 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1023 {
1024 if (tu > 0xFFFF) {
1025 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1026 tu);
1027 ah->globaltxtimeout = (u32) -1;
1028 return false;
1029 } else {
1030 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1031 ah->globaltxtimeout = tu;
1032 return true;
1033 }
1034 }
1035
1036 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1037 {
1038 struct ath_common *common = ath9k_hw_common(ah);
1039 struct ieee80211_conf *conf = &common->hw->conf;
1040 const struct ath9k_channel *chan = ah->curchan;
1041 int acktimeout, ctstimeout, ack_offset = 0;
1042 int slottime;
1043 int sifstime;
1044 int rx_lat = 0, tx_lat = 0, eifs = 0;
1045 u32 reg;
1046
1047 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1048 ah->misc_mode);
1049
1050 if (!chan)
1051 return;
1052
1053 if (ah->misc_mode != 0)
1054 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1055
1056 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1057 rx_lat = 41;
1058 else
1059 rx_lat = 37;
1060 tx_lat = 54;
1061
1062 if (IS_CHAN_5GHZ(chan))
1063 sifstime = 16;
1064 else
1065 sifstime = 10;
1066
1067 if (IS_CHAN_HALF_RATE(chan)) {
1068 eifs = 175;
1069 rx_lat *= 2;
1070 tx_lat *= 2;
1071 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1072 tx_lat += 11;
1073
1074 sifstime *= 2;
1075 ack_offset = 16;
1076 slottime = 13;
1077 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1078 eifs = 340;
1079 rx_lat = (rx_lat * 4) - 1;
1080 tx_lat *= 4;
1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1082 tx_lat += 22;
1083
1084 sifstime *= 4;
1085 ack_offset = 32;
1086 slottime = 21;
1087 } else {
1088 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1089 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1090 reg = AR_USEC_ASYNC_FIFO;
1091 } else {
1092 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1093 common->clockrate;
1094 reg = REG_READ(ah, AR_USEC);
1095 }
1096 rx_lat = MS(reg, AR_USEC_RX_LAT);
1097 tx_lat = MS(reg, AR_USEC_TX_LAT);
1098
1099 slottime = ah->slottime;
1100 }
1101
1102 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1103 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
1104 ctstimeout = acktimeout;
1105
1106 /*
1107 * Workaround for early ACK timeouts, add an offset to match the
1108 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1109 * This was initially only meant to work around an issue with delayed
1110 * BA frames in some implementations, but it has been found to fix ACK
1111 * timeout issues in other cases as well.
1112 */
1113 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
1114 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1115 acktimeout += 64 - sifstime - ah->slottime;
1116 ctstimeout += 48 - sifstime - ah->slottime;
1117 }
1118
1119
1120 ath9k_hw_set_sifs_time(ah, sifstime);
1121 ath9k_hw_setslottime(ah, slottime);
1122 ath9k_hw_set_ack_timeout(ah, acktimeout);
1123 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1124 if (ah->globaltxtimeout != (u32) -1)
1125 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1126
1127 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1128 REG_RMW(ah, AR_USEC,
1129 (common->clockrate - 1) |
1130 SM(rx_lat, AR_USEC_RX_LAT) |
1131 SM(tx_lat, AR_USEC_TX_LAT),
1132 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1133
1134 }
1135 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1136
1137 void ath9k_hw_deinit(struct ath_hw *ah)
1138 {
1139 struct ath_common *common = ath9k_hw_common(ah);
1140
1141 if (common->state < ATH_HW_INITIALIZED)
1142 return;
1143
1144 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1145 }
1146 EXPORT_SYMBOL(ath9k_hw_deinit);
1147
1148 /*******/
1149 /* INI */
1150 /*******/
1151
1152 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1153 {
1154 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1155
1156 if (IS_CHAN_B(chan))
1157 ctl |= CTL_11B;
1158 else if (IS_CHAN_G(chan))
1159 ctl |= CTL_11G;
1160 else
1161 ctl |= CTL_11A;
1162
1163 return ctl;
1164 }
1165
1166 /****************************************/
1167 /* Reset and Channel Switching Routines */
1168 /****************************************/
1169
1170 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1171 {
1172 struct ath_common *common = ath9k_hw_common(ah);
1173
1174 ENABLE_REGWRITE_BUFFER(ah);
1175
1176 /*
1177 * set AHB_MODE not to do cacheline prefetches
1178 */
1179 if (!AR_SREV_9300_20_OR_LATER(ah))
1180 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1181
1182 /*
1183 * let mac dma reads be in 128 byte chunks
1184 */
1185 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1186
1187 REGWRITE_BUFFER_FLUSH(ah);
1188
1189 /*
1190 * Restore TX Trigger Level to its pre-reset value.
1191 * The initial value depends on whether aggregation is enabled, and is
1192 * adjusted whenever underruns are detected.
1193 */
1194 if (!AR_SREV_9300_20_OR_LATER(ah))
1195 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1196
1197 ENABLE_REGWRITE_BUFFER(ah);
1198
1199 /*
1200 * let mac dma writes be in 128 byte chunks
1201 */
1202 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1203
1204 /*
1205 * Setup receive FIFO threshold to hold off TX activities
1206 */
1207 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1208
1209 if (AR_SREV_9300_20_OR_LATER(ah)) {
1210 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1211 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1212
1213 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1214 ah->caps.rx_status_len);
1215 }
1216
1217 /*
1218 * reduce the number of usable entries in PCU TXBUF to avoid
1219 * wrap around issues.
1220 */
1221 if (AR_SREV_9285(ah)) {
1222 /* For AR9285 the number of Fifos are reduced to half.
1223 * So set the usable tx buf size also to half to
1224 * avoid data/delimiter underruns
1225 */
1226 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1227 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1228 } else if (!AR_SREV_9271(ah)) {
1229 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1230 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1231 }
1232
1233 REGWRITE_BUFFER_FLUSH(ah);
1234
1235 if (AR_SREV_9300_20_OR_LATER(ah))
1236 ath9k_hw_reset_txstatus_ring(ah);
1237 }
1238
1239 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1240 {
1241 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1242 u32 set = AR_STA_ID1_KSRCH_MODE;
1243
1244 switch (opmode) {
1245 case NL80211_IFTYPE_ADHOC:
1246 case NL80211_IFTYPE_MESH_POINT:
1247 set |= AR_STA_ID1_ADHOC;
1248 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1249 break;
1250 case NL80211_IFTYPE_AP:
1251 set |= AR_STA_ID1_STA_AP;
1252 /* fall through */
1253 case NL80211_IFTYPE_STATION:
1254 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1255 break;
1256 default:
1257 if (!ah->is_monitoring)
1258 set = 0;
1259 break;
1260 }
1261 REG_RMW(ah, AR_STA_ID1, set, mask);
1262 }
1263
1264 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1265 u32 *coef_mantissa, u32 *coef_exponent)
1266 {
1267 u32 coef_exp, coef_man;
1268
1269 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1270 if ((coef_scaled >> coef_exp) & 0x1)
1271 break;
1272
1273 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1274
1275 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1276
1277 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1278 *coef_exponent = coef_exp - 16;
1279 }
1280
1281 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1282 {
1283 u32 rst_flags;
1284 u32 tmpReg;
1285
1286 if (AR_SREV_9100(ah)) {
1287 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1288 AR_RTC_DERIVED_CLK_PERIOD, 1);
1289 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1290 }
1291
1292 ENABLE_REGWRITE_BUFFER(ah);
1293
1294 if (AR_SREV_9300_20_OR_LATER(ah)) {
1295 REG_WRITE(ah, AR_WA, ah->WARegVal);
1296 udelay(10);
1297 }
1298
1299 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1300 AR_RTC_FORCE_WAKE_ON_INT);
1301
1302 if (AR_SREV_9100(ah)) {
1303 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1304 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1305 } else {
1306 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1307 if (tmpReg &
1308 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1309 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1310 u32 val;
1311 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1312
1313 val = AR_RC_HOSTIF;
1314 if (!AR_SREV_9300_20_OR_LATER(ah))
1315 val |= AR_RC_AHB;
1316 REG_WRITE(ah, AR_RC, val);
1317
1318 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1319 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1320
1321 rst_flags = AR_RTC_RC_MAC_WARM;
1322 if (type == ATH9K_RESET_COLD)
1323 rst_flags |= AR_RTC_RC_MAC_COLD;
1324 }
1325
1326 if (AR_SREV_9330(ah)) {
1327 int npend = 0;
1328 int i;
1329
1330 /* AR9330 WAR:
1331 * call external reset function to reset WMAC if:
1332 * - doing a cold reset
1333 * - we have pending frames in the TX queues
1334 */
1335
1336 for (i = 0; i < AR_NUM_QCU; i++) {
1337 npend = ath9k_hw_numtxpending(ah, i);
1338 if (npend)
1339 break;
1340 }
1341
1342 if (ah->external_reset &&
1343 (npend || type == ATH9K_RESET_COLD)) {
1344 int reset_err = 0;
1345
1346 ath_dbg(ath9k_hw_common(ah), RESET,
1347 "reset MAC via external reset\n");
1348
1349 reset_err = ah->external_reset();
1350 if (reset_err) {
1351 ath_err(ath9k_hw_common(ah),
1352 "External reset failed, err=%d\n",
1353 reset_err);
1354 return false;
1355 }
1356
1357 REG_WRITE(ah, AR_RTC_RESET, 1);
1358 }
1359 }
1360
1361 if (ath9k_hw_mci_is_enabled(ah))
1362 ar9003_mci_check_gpm_offset(ah);
1363
1364 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1365
1366 REGWRITE_BUFFER_FLUSH(ah);
1367
1368 udelay(50);
1369
1370 REG_WRITE(ah, AR_RTC_RC, 0);
1371 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1372 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1373 return false;
1374 }
1375
1376 if (!AR_SREV_9100(ah))
1377 REG_WRITE(ah, AR_RC, 0);
1378
1379 if (AR_SREV_9100(ah))
1380 udelay(50);
1381
1382 return true;
1383 }
1384
1385 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1386 {
1387 ENABLE_REGWRITE_BUFFER(ah);
1388
1389 if (AR_SREV_9300_20_OR_LATER(ah)) {
1390 REG_WRITE(ah, AR_WA, ah->WARegVal);
1391 udelay(10);
1392 }
1393
1394 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1395 AR_RTC_FORCE_WAKE_ON_INT);
1396
1397 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1398 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1399
1400 REG_WRITE(ah, AR_RTC_RESET, 0);
1401
1402 REGWRITE_BUFFER_FLUSH(ah);
1403
1404 if (!AR_SREV_9300_20_OR_LATER(ah))
1405 udelay(2);
1406
1407 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1408 REG_WRITE(ah, AR_RC, 0);
1409
1410 REG_WRITE(ah, AR_RTC_RESET, 1);
1411
1412 if (!ath9k_hw_wait(ah,
1413 AR_RTC_STATUS,
1414 AR_RTC_STATUS_M,
1415 AR_RTC_STATUS_ON,
1416 AH_WAIT_TIMEOUT)) {
1417 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1418 return false;
1419 }
1420
1421 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1422 }
1423
1424 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1425 {
1426 bool ret = false;
1427
1428 if (AR_SREV_9300_20_OR_LATER(ah)) {
1429 REG_WRITE(ah, AR_WA, ah->WARegVal);
1430 udelay(10);
1431 }
1432
1433 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1434 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1435
1436 if (!ah->reset_power_on)
1437 type = ATH9K_RESET_POWER_ON;
1438
1439 switch (type) {
1440 case ATH9K_RESET_POWER_ON:
1441 ret = ath9k_hw_set_reset_power_on(ah);
1442 if (ret)
1443 ah->reset_power_on = true;
1444 break;
1445 case ATH9K_RESET_WARM:
1446 case ATH9K_RESET_COLD:
1447 ret = ath9k_hw_set_reset(ah, type);
1448 break;
1449 default:
1450 break;
1451 }
1452
1453 return ret;
1454 }
1455
1456 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1457 struct ath9k_channel *chan)
1458 {
1459 int reset_type = ATH9K_RESET_WARM;
1460
1461 if (AR_SREV_9280(ah)) {
1462 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1463 reset_type = ATH9K_RESET_POWER_ON;
1464 else
1465 reset_type = ATH9K_RESET_COLD;
1466 }
1467
1468 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1469 return false;
1470
1471 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1472 return false;
1473
1474 ah->chip_fullsleep = false;
1475
1476 if (AR_SREV_9330(ah))
1477 ar9003_hw_internal_regulator_apply(ah);
1478 ath9k_hw_init_pll(ah, chan);
1479 ath9k_hw_set_rfmode(ah, chan);
1480
1481 return true;
1482 }
1483
1484 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1485 struct ath9k_channel *chan)
1486 {
1487 struct ath_common *common = ath9k_hw_common(ah);
1488 u32 qnum;
1489 int r;
1490 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1491 bool band_switch, mode_diff;
1492 u8 ini_reloaded;
1493
1494 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1495 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1496 CHANNEL_5GHZ));
1497 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1498
1499 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1500 if (ath9k_hw_numtxpending(ah, qnum)) {
1501 ath_dbg(common, QUEUE,
1502 "Transmit frames pending on queue %d\n", qnum);
1503 return false;
1504 }
1505 }
1506
1507 if (!ath9k_hw_rfbus_req(ah)) {
1508 ath_err(common, "Could not kill baseband RX\n");
1509 return false;
1510 }
1511
1512 if (edma && (band_switch || mode_diff)) {
1513 ath9k_hw_mark_phy_inactive(ah);
1514 udelay(5);
1515
1516 ath9k_hw_init_pll(ah, NULL);
1517
1518 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1519 ath_err(common, "Failed to do fast channel change\n");
1520 return false;
1521 }
1522 }
1523
1524 ath9k_hw_set_channel_regs(ah, chan);
1525
1526 r = ath9k_hw_rf_set_freq(ah, chan);
1527 if (r) {
1528 ath_err(common, "Failed to set channel\n");
1529 return false;
1530 }
1531 ath9k_hw_set_clockrate(ah);
1532 ath9k_hw_apply_txpower(ah, chan, false);
1533 ath9k_hw_rfbus_done(ah);
1534
1535 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1536 ath9k_hw_set_delta_slope(ah, chan);
1537
1538 ath9k_hw_spur_mitigate_freq(ah, chan);
1539
1540 if (edma && (band_switch || mode_diff)) {
1541 ah->ah_flags |= AH_FASTCC;
1542 if (band_switch || ini_reloaded)
1543 ah->eep_ops->set_board_values(ah, chan);
1544
1545 ath9k_hw_init_bb(ah, chan);
1546
1547 if (band_switch || ini_reloaded)
1548 ath9k_hw_init_cal(ah, chan);
1549 ah->ah_flags &= ~AH_FASTCC;
1550 }
1551
1552 return true;
1553 }
1554
1555 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1556 {
1557 u32 gpio_mask = ah->gpio_mask;
1558 int i;
1559
1560 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1561 if (!(gpio_mask & 1))
1562 continue;
1563
1564 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1565 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1566 }
1567 }
1568
1569 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1570 int *hang_state, int *hang_pos)
1571 {
1572 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1573 u32 chain_state, dcs_pos, i;
1574
1575 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1576 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1577 for (i = 0; i < 3; i++) {
1578 if (chain_state == dcu_chain_state[i]) {
1579 *hang_state = chain_state;
1580 *hang_pos = dcs_pos;
1581 return true;
1582 }
1583 }
1584 }
1585 return false;
1586 }
1587
1588 #define DCU_COMPLETE_STATE 1
1589 #define DCU_COMPLETE_STATE_MASK 0x3
1590 #define NUM_STATUS_READS 50
1591 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1592 {
1593 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1594 u32 i, hang_pos, hang_state, num_state = 6;
1595
1596 comp_state = REG_READ(ah, AR_DMADBG_6);
1597
1598 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1599 ath_dbg(ath9k_hw_common(ah), RESET,
1600 "MAC Hang signature not found at DCU complete\n");
1601 return false;
1602 }
1603
1604 chain_state = REG_READ(ah, dcs_reg);
1605 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1606 goto hang_check_iter;
1607
1608 dcs_reg = AR_DMADBG_5;
1609 num_state = 4;
1610 chain_state = REG_READ(ah, dcs_reg);
1611 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1612 goto hang_check_iter;
1613
1614 ath_dbg(ath9k_hw_common(ah), RESET,
1615 "MAC Hang signature 1 not found\n");
1616 return false;
1617
1618 hang_check_iter:
1619 ath_dbg(ath9k_hw_common(ah), RESET,
1620 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1621 chain_state, comp_state, hang_state, hang_pos);
1622
1623 for (i = 0; i < NUM_STATUS_READS; i++) {
1624 chain_state = REG_READ(ah, dcs_reg);
1625 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1626 comp_state = REG_READ(ah, AR_DMADBG_6);
1627
1628 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1629 DCU_COMPLETE_STATE) ||
1630 (chain_state != hang_state))
1631 return false;
1632 }
1633
1634 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1635
1636 return true;
1637 }
1638
1639 bool ath9k_hw_check_alive(struct ath_hw *ah)
1640 {
1641 int count = 50;
1642 u32 reg;
1643
1644 if (AR_SREV_9300(ah))
1645 return !ath9k_hw_detect_mac_hang(ah);
1646
1647 if (AR_SREV_9285_12_OR_LATER(ah))
1648 return true;
1649
1650 do {
1651 reg = REG_READ(ah, AR_OBS_BUS_1);
1652
1653 if ((reg & 0x7E7FFFEF) == 0x00702400)
1654 continue;
1655
1656 switch (reg & 0x7E000B00) {
1657 case 0x1E000000:
1658 case 0x52000B00:
1659 case 0x18000B00:
1660 continue;
1661 default:
1662 return true;
1663 }
1664 } while (count-- > 0);
1665
1666 return false;
1667 }
1668 EXPORT_SYMBOL(ath9k_hw_check_alive);
1669
1670 /*
1671 * Fast channel change:
1672 * (Change synthesizer based on channel freq without resetting chip)
1673 *
1674 * Don't do FCC when
1675 * - Flag is not set
1676 * - Chip is just coming out of full sleep
1677 * - Channel to be set is same as current channel
1678 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
1679 */
1680 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1681 {
1682 struct ath_common *common = ath9k_hw_common(ah);
1683 int ret;
1684
1685 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1686 goto fail;
1687
1688 if (ah->chip_fullsleep)
1689 goto fail;
1690
1691 if (!ah->curchan)
1692 goto fail;
1693
1694 if (chan->channel == ah->curchan->channel)
1695 goto fail;
1696
1697 if ((ah->curchan->channelFlags | chan->channelFlags) &
1698 (CHANNEL_HALF | CHANNEL_QUARTER))
1699 goto fail;
1700
1701 if ((chan->channelFlags & CHANNEL_ALL) !=
1702 (ah->curchan->channelFlags & CHANNEL_ALL))
1703 goto fail;
1704
1705 if (!ath9k_hw_check_alive(ah))
1706 goto fail;
1707
1708 /*
1709 * For AR9462, make sure that calibration data for
1710 * re-using are present.
1711 */
1712 if (AR_SREV_9462(ah) && (ah->caldata &&
1713 (!ah->caldata->done_txiqcal_once ||
1714 !ah->caldata->done_txclcal_once ||
1715 !ah->caldata->rtt_done)))
1716 goto fail;
1717
1718 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1719 ah->curchan->channel, chan->channel);
1720
1721 ret = ath9k_hw_channel_change(ah, chan);
1722 if (!ret)
1723 goto fail;
1724
1725 if (ath9k_hw_mci_is_enabled(ah))
1726 ar9003_mci_2g5g_switch(ah, false);
1727
1728 ath9k_hw_loadnf(ah, ah->curchan);
1729 ath9k_hw_start_nfcal(ah, true);
1730
1731 if (AR_SREV_9271(ah))
1732 ar9002_hw_load_ani_reg(ah, chan);
1733
1734 return 0;
1735 fail:
1736 return -EINVAL;
1737 }
1738
1739 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1740 struct ath9k_hw_cal_data *caldata, bool fastcc)
1741 {
1742 struct ath_common *common = ath9k_hw_common(ah);
1743 u32 saveLedState;
1744 u32 saveDefAntenna;
1745 u32 macStaId1;
1746 u64 tsf = 0;
1747 int i, r;
1748 bool start_mci_reset = false;
1749 bool save_fullsleep = ah->chip_fullsleep;
1750
1751 if (ath9k_hw_mci_is_enabled(ah)) {
1752 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1753 if (start_mci_reset)
1754 return 0;
1755 }
1756
1757 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1758 return -EIO;
1759
1760 if (ah->curchan && !ah->chip_fullsleep)
1761 ath9k_hw_getnf(ah, ah->curchan);
1762
1763 ah->caldata = caldata;
1764 if (caldata &&
1765 (chan->channel != caldata->channel ||
1766 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1767 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1768 /* Operating channel changed, reset channel calibration data */
1769 memset(caldata, 0, sizeof(*caldata));
1770 ath9k_init_nfcal_hist_buffer(ah, chan);
1771 } else if (caldata) {
1772 caldata->paprd_packet_sent = false;
1773 }
1774 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1775
1776 if (fastcc) {
1777 r = ath9k_hw_do_fastcc(ah, chan);
1778 if (!r)
1779 return r;
1780 }
1781
1782 if (ath9k_hw_mci_is_enabled(ah))
1783 ar9003_mci_stop_bt(ah, save_fullsleep);
1784
1785 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1786 if (saveDefAntenna == 0)
1787 saveDefAntenna = 1;
1788
1789 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1790
1791 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1792 if (AR_SREV_9100(ah) ||
1793 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1794 tsf = ath9k_hw_gettsf64(ah);
1795
1796 saveLedState = REG_READ(ah, AR_CFG_LED) &
1797 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1798 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1799
1800 ath9k_hw_mark_phy_inactive(ah);
1801
1802 ah->paprd_table_write_done = false;
1803
1804 /* Only required on the first reset */
1805 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1806 REG_WRITE(ah,
1807 AR9271_RESET_POWER_DOWN_CONTROL,
1808 AR9271_RADIO_RF_RST);
1809 udelay(50);
1810 }
1811
1812 if (!ath9k_hw_chip_reset(ah, chan)) {
1813 ath_err(common, "Chip reset failed\n");
1814 return -EINVAL;
1815 }
1816
1817 /* Only required on the first reset */
1818 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1819 ah->htc_reset_init = false;
1820 REG_WRITE(ah,
1821 AR9271_RESET_POWER_DOWN_CONTROL,
1822 AR9271_GATE_MAC_CTL);
1823 udelay(50);
1824 }
1825
1826 /* Restore TSF */
1827 if (tsf)
1828 ath9k_hw_settsf64(ah, tsf);
1829
1830 if (AR_SREV_9280_20_OR_LATER(ah))
1831 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1832
1833 if (!AR_SREV_9300_20_OR_LATER(ah))
1834 ar9002_hw_enable_async_fifo(ah);
1835
1836 r = ath9k_hw_process_ini(ah, chan);
1837 if (r)
1838 return r;
1839
1840 if (ath9k_hw_mci_is_enabled(ah))
1841 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1842
1843 /*
1844 * Some AR91xx SoC devices frequently fail to accept TSF writes
1845 * right after the chip reset. When that happens, write a new
1846 * value after the initvals have been applied, with an offset
1847 * based on measured time difference
1848 */
1849 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1850 tsf += 1500;
1851 ath9k_hw_settsf64(ah, tsf);
1852 }
1853
1854 /* Setup MFP options for CCMP */
1855 if (AR_SREV_9280_20_OR_LATER(ah)) {
1856 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1857 * frames when constructing CCMP AAD. */
1858 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1859 0xc7ff);
1860 ah->sw_mgmt_crypto = false;
1861 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1862 /* Disable hardware crypto for management frames */
1863 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1864 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1865 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1866 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1867 ah->sw_mgmt_crypto = true;
1868 } else
1869 ah->sw_mgmt_crypto = true;
1870
1871 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1872 ath9k_hw_set_delta_slope(ah, chan);
1873
1874 ath9k_hw_spur_mitigate_freq(ah, chan);
1875 ah->eep_ops->set_board_values(ah, chan);
1876
1877 ENABLE_REGWRITE_BUFFER(ah);
1878
1879 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1880 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1881 | macStaId1
1882 | AR_STA_ID1_RTS_USE_DEF
1883 | (ah->config.
1884 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1885 | ah->sta_id1_defaults);
1886 ath_hw_setbssidmask(common);
1887 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1888 ath9k_hw_write_associd(ah);
1889 REG_WRITE(ah, AR_ISR, ~0);
1890 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1891
1892 REGWRITE_BUFFER_FLUSH(ah);
1893
1894 ath9k_hw_set_operating_mode(ah, ah->opmode);
1895
1896 r = ath9k_hw_rf_set_freq(ah, chan);
1897 if (r)
1898 return r;
1899
1900 ath9k_hw_set_clockrate(ah);
1901
1902 ENABLE_REGWRITE_BUFFER(ah);
1903
1904 for (i = 0; i < AR_NUM_DCU; i++)
1905 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1906
1907 REGWRITE_BUFFER_FLUSH(ah);
1908
1909 ah->intr_txqs = 0;
1910 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1911 ath9k_hw_resettxqueue(ah, i);
1912
1913 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1914 ath9k_hw_ani_cache_ini_regs(ah);
1915 ath9k_hw_init_qos(ah);
1916
1917 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1918 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1919
1920 ath9k_hw_init_global_settings(ah);
1921
1922 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1923 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1924 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1925 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1926 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1927 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1928 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1929 }
1930
1931 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1932
1933 ath9k_hw_set_dma(ah);
1934
1935 if (!ath9k_hw_mci_is_enabled(ah))
1936 REG_WRITE(ah, AR_OBS, 8);
1937
1938 if (ah->config.rx_intr_mitigation) {
1939 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1940 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1941 }
1942
1943 if (ah->config.tx_intr_mitigation) {
1944 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1945 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1946 }
1947
1948 ath9k_hw_init_bb(ah, chan);
1949
1950 if (caldata) {
1951 caldata->done_txiqcal_once = false;
1952 caldata->done_txclcal_once = false;
1953 }
1954 if (!ath9k_hw_init_cal(ah, chan))
1955 return -EIO;
1956
1957 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1958 return -EIO;
1959
1960 ENABLE_REGWRITE_BUFFER(ah);
1961
1962 ath9k_hw_restore_chainmask(ah);
1963 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1964
1965 REGWRITE_BUFFER_FLUSH(ah);
1966
1967 /*
1968 * For big endian systems turn on swapping for descriptors
1969 */
1970 if (AR_SREV_9100(ah)) {
1971 u32 mask;
1972 mask = REG_READ(ah, AR_CFG);
1973 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1974 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1975 mask);
1976 } else {
1977 mask =
1978 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1979 REG_WRITE(ah, AR_CFG, mask);
1980 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1981 REG_READ(ah, AR_CFG));
1982 }
1983 } else {
1984 if (common->bus_ops->ath_bus_type == ATH_USB) {
1985 /* Configure AR9271 target WLAN */
1986 if (AR_SREV_9271(ah))
1987 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1988 else
1989 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1990 }
1991 #ifdef __BIG_ENDIAN
1992 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1993 AR_SREV_9550(ah))
1994 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1995 else
1996 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1997 #endif
1998 }
1999
2000 if (ath9k_hw_btcoex_is_enabled(ah))
2001 ath9k_hw_btcoex_enable(ah);
2002
2003 if (ath9k_hw_mci_is_enabled(ah))
2004 ar9003_mci_check_bt(ah);
2005
2006 ath9k_hw_loadnf(ah, chan);
2007 ath9k_hw_start_nfcal(ah, true);
2008
2009 if (AR_SREV_9300_20_OR_LATER(ah)) {
2010 ar9003_hw_bb_watchdog_config(ah);
2011
2012 ar9003_hw_disable_phy_restart(ah);
2013 }
2014
2015 ath9k_hw_apply_gpio_override(ah);
2016
2017 if (AR_SREV_9565(ah) && ah->shared_chain_lnadiv)
2018 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2019
2020 return 0;
2021 }
2022 EXPORT_SYMBOL(ath9k_hw_reset);
2023
2024 /******************************/
2025 /* Power Management (Chipset) */
2026 /******************************/
2027
2028 /*
2029 * Notify Power Mgt is disabled in self-generated frames.
2030 * If requested, force chip to sleep.
2031 */
2032 static void ath9k_set_power_sleep(struct ath_hw *ah)
2033 {
2034 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2035
2036 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2037 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2038 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2039 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2040 /* xxx Required for WLAN only case ? */
2041 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2042 udelay(100);
2043 }
2044
2045 /*
2046 * Clear the RTC force wake bit to allow the
2047 * mac to go to sleep.
2048 */
2049 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2050
2051 if (ath9k_hw_mci_is_enabled(ah))
2052 udelay(100);
2053
2054 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2055 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2056
2057 /* Shutdown chip. Active low */
2058 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2059 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2060 udelay(2);
2061 }
2062
2063 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2064 if (AR_SREV_9300_20_OR_LATER(ah))
2065 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2066 }
2067
2068 /*
2069 * Notify Power Management is enabled in self-generating
2070 * frames. If request, set power mode of chip to
2071 * auto/normal. Duration in units of 128us (1/8 TU).
2072 */
2073 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2074 {
2075 struct ath9k_hw_capabilities *pCap = &ah->caps;
2076
2077 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2078
2079 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2080 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2081 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2082 AR_RTC_FORCE_WAKE_ON_INT);
2083 } else {
2084
2085 /* When chip goes into network sleep, it could be waken
2086 * up by MCI_INT interrupt caused by BT's HW messages
2087 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2088 * rate (~100us). This will cause chip to leave and
2089 * re-enter network sleep mode frequently, which in
2090 * consequence will have WLAN MCI HW to generate lots of
2091 * SYS_WAKING and SYS_SLEEPING messages which will make
2092 * BT CPU to busy to process.
2093 */
2094 if (ath9k_hw_mci_is_enabled(ah))
2095 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2096 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2097 /*
2098 * Clear the RTC force wake bit to allow the
2099 * mac to go to sleep.
2100 */
2101 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2102
2103 if (ath9k_hw_mci_is_enabled(ah))
2104 udelay(30);
2105 }
2106
2107 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2108 if (AR_SREV_9300_20_OR_LATER(ah))
2109 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2110 }
2111
2112 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2113 {
2114 u32 val;
2115 int i;
2116
2117 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2118 if (AR_SREV_9300_20_OR_LATER(ah)) {
2119 REG_WRITE(ah, AR_WA, ah->WARegVal);
2120 udelay(10);
2121 }
2122
2123 if ((REG_READ(ah, AR_RTC_STATUS) &
2124 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2125 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2126 return false;
2127 }
2128 if (!AR_SREV_9300_20_OR_LATER(ah))
2129 ath9k_hw_init_pll(ah, NULL);
2130 }
2131 if (AR_SREV_9100(ah))
2132 REG_SET_BIT(ah, AR_RTC_RESET,
2133 AR_RTC_RESET_EN);
2134
2135 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2136 AR_RTC_FORCE_WAKE_EN);
2137 udelay(50);
2138
2139 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2140 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2141 if (val == AR_RTC_STATUS_ON)
2142 break;
2143 udelay(50);
2144 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2145 AR_RTC_FORCE_WAKE_EN);
2146 }
2147 if (i == 0) {
2148 ath_err(ath9k_hw_common(ah),
2149 "Failed to wakeup in %uus\n",
2150 POWER_UP_TIME / 20);
2151 return false;
2152 }
2153
2154 if (ath9k_hw_mci_is_enabled(ah))
2155 ar9003_mci_set_power_awake(ah);
2156
2157 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2158
2159 return true;
2160 }
2161
2162 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2163 {
2164 struct ath_common *common = ath9k_hw_common(ah);
2165 int status = true;
2166 static const char *modes[] = {
2167 "AWAKE",
2168 "FULL-SLEEP",
2169 "NETWORK SLEEP",
2170 "UNDEFINED"
2171 };
2172
2173 if (ah->power_mode == mode)
2174 return status;
2175
2176 ath_dbg(common, RESET, "%s -> %s\n",
2177 modes[ah->power_mode], modes[mode]);
2178
2179 switch (mode) {
2180 case ATH9K_PM_AWAKE:
2181 status = ath9k_hw_set_power_awake(ah);
2182 break;
2183 case ATH9K_PM_FULL_SLEEP:
2184 if (ath9k_hw_mci_is_enabled(ah))
2185 ar9003_mci_set_full_sleep(ah);
2186
2187 ath9k_set_power_sleep(ah);
2188 ah->chip_fullsleep = true;
2189 break;
2190 case ATH9K_PM_NETWORK_SLEEP:
2191 ath9k_set_power_network_sleep(ah);
2192 break;
2193 default:
2194 ath_err(common, "Unknown power mode %u\n", mode);
2195 return false;
2196 }
2197 ah->power_mode = mode;
2198
2199 /*
2200 * XXX: If this warning never comes up after a while then
2201 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2202 * ath9k_hw_setpower() return type void.
2203 */
2204
2205 if (!(ah->ah_flags & AH_UNPLUGGED))
2206 ATH_DBG_WARN_ON_ONCE(!status);
2207
2208 return status;
2209 }
2210 EXPORT_SYMBOL(ath9k_hw_setpower);
2211
2212 /*******************/
2213 /* Beacon Handling */
2214 /*******************/
2215
2216 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2217 {
2218 int flags = 0;
2219
2220 ENABLE_REGWRITE_BUFFER(ah);
2221
2222 switch (ah->opmode) {
2223 case NL80211_IFTYPE_ADHOC:
2224 case NL80211_IFTYPE_MESH_POINT:
2225 REG_SET_BIT(ah, AR_TXCFG,
2226 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2227 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2228 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2229 flags |= AR_NDP_TIMER_EN;
2230 case NL80211_IFTYPE_AP:
2231 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2232 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2233 TU_TO_USEC(ah->config.dma_beacon_response_time));
2234 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2235 TU_TO_USEC(ah->config.sw_beacon_response_time));
2236 flags |=
2237 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2238 break;
2239 default:
2240 ath_dbg(ath9k_hw_common(ah), BEACON,
2241 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2242 return;
2243 break;
2244 }
2245
2246 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2247 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2248 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2249 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2250
2251 REGWRITE_BUFFER_FLUSH(ah);
2252
2253 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2254 }
2255 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2256
2257 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2258 const struct ath9k_beacon_state *bs)
2259 {
2260 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2261 struct ath9k_hw_capabilities *pCap = &ah->caps;
2262 struct ath_common *common = ath9k_hw_common(ah);
2263
2264 ENABLE_REGWRITE_BUFFER(ah);
2265
2266 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2267
2268 REG_WRITE(ah, AR_BEACON_PERIOD,
2269 TU_TO_USEC(bs->bs_intval));
2270 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2271 TU_TO_USEC(bs->bs_intval));
2272
2273 REGWRITE_BUFFER_FLUSH(ah);
2274
2275 REG_RMW_FIELD(ah, AR_RSSI_THR,
2276 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2277
2278 beaconintval = bs->bs_intval;
2279
2280 if (bs->bs_sleepduration > beaconintval)
2281 beaconintval = bs->bs_sleepduration;
2282
2283 dtimperiod = bs->bs_dtimperiod;
2284 if (bs->bs_sleepduration > dtimperiod)
2285 dtimperiod = bs->bs_sleepduration;
2286
2287 if (beaconintval == dtimperiod)
2288 nextTbtt = bs->bs_nextdtim;
2289 else
2290 nextTbtt = bs->bs_nexttbtt;
2291
2292 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2293 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2294 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2295 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2296
2297 ENABLE_REGWRITE_BUFFER(ah);
2298
2299 REG_WRITE(ah, AR_NEXT_DTIM,
2300 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2301 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2302
2303 REG_WRITE(ah, AR_SLEEP1,
2304 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2305 | AR_SLEEP1_ASSUME_DTIM);
2306
2307 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2308 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2309 else
2310 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2311
2312 REG_WRITE(ah, AR_SLEEP2,
2313 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2314
2315 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2316 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2317
2318 REGWRITE_BUFFER_FLUSH(ah);
2319
2320 REG_SET_BIT(ah, AR_TIMER_MODE,
2321 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2322 AR_DTIM_TIMER_EN);
2323
2324 /* TSF Out of Range Threshold */
2325 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2326 }
2327 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2328
2329 /*******************/
2330 /* HW Capabilities */
2331 /*******************/
2332
2333 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2334 {
2335 eeprom_chainmask &= chip_chainmask;
2336 if (eeprom_chainmask)
2337 return eeprom_chainmask;
2338 else
2339 return chip_chainmask;
2340 }
2341
2342 /**
2343 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2344 * @ah: the atheros hardware data structure
2345 *
2346 * We enable DFS support upstream on chipsets which have passed a series
2347 * of tests. The testing requirements are going to be documented. Desired
2348 * test requirements are documented at:
2349 *
2350 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2351 *
2352 * Once a new chipset gets properly tested an individual commit can be used
2353 * to document the testing for DFS for that chipset.
2354 */
2355 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2356 {
2357
2358 switch (ah->hw_version.macVersion) {
2359 /* AR9580 will likely be our first target to get testing on */
2360 case AR_SREV_VERSION_9580:
2361 default:
2362 return false;
2363 }
2364 }
2365
2366 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2367 {
2368 struct ath9k_hw_capabilities *pCap = &ah->caps;
2369 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2370 struct ath_common *common = ath9k_hw_common(ah);
2371 unsigned int chip_chainmask;
2372
2373 u16 eeval;
2374 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2375
2376 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2377 regulatory->current_rd = eeval;
2378
2379 if (ah->opmode != NL80211_IFTYPE_AP &&
2380 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2381 if (regulatory->current_rd == 0x64 ||
2382 regulatory->current_rd == 0x65)
2383 regulatory->current_rd += 5;
2384 else if (regulatory->current_rd == 0x41)
2385 regulatory->current_rd = 0x43;
2386 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2387 regulatory->current_rd);
2388 }
2389
2390 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2391 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2392 ath_err(common,
2393 "no band has been marked as supported in EEPROM\n");
2394 return -EINVAL;
2395 }
2396
2397 if (eeval & AR5416_OPFLAGS_11A)
2398 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2399
2400 if (eeval & AR5416_OPFLAGS_11G)
2401 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2402
2403 if (AR_SREV_9485(ah) ||
2404 AR_SREV_9285(ah) ||
2405 AR_SREV_9330(ah) ||
2406 AR_SREV_9565(ah))
2407 chip_chainmask = 1;
2408 else if (AR_SREV_9462(ah))
2409 chip_chainmask = 3;
2410 else if (!AR_SREV_9280_20_OR_LATER(ah))
2411 chip_chainmask = 7;
2412 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2413 chip_chainmask = 3;
2414 else
2415 chip_chainmask = 7;
2416
2417 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2418 /*
2419 * For AR9271 we will temporarilly uses the rx chainmax as read from
2420 * the EEPROM.
2421 */
2422 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2423 !(eeval & AR5416_OPFLAGS_11A) &&
2424 !(AR_SREV_9271(ah)))
2425 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2426 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2427 else if (AR_SREV_9100(ah))
2428 pCap->rx_chainmask = 0x7;
2429 else
2430 /* Use rx_chainmask from EEPROM. */
2431 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2432
2433 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2434 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2435 ah->txchainmask = pCap->tx_chainmask;
2436 ah->rxchainmask = pCap->rx_chainmask;
2437
2438 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2439
2440 /* enable key search for every frame in an aggregate */
2441 if (AR_SREV_9300_20_OR_LATER(ah))
2442 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2443
2444 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2445
2446 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2447 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2448 else
2449 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2450
2451 if (AR_SREV_9271(ah))
2452 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2453 else if (AR_DEVID_7010(ah))
2454 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2455 else if (AR_SREV_9300_20_OR_LATER(ah))
2456 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2457 else if (AR_SREV_9287_11_OR_LATER(ah))
2458 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2459 else if (AR_SREV_9285_12_OR_LATER(ah))
2460 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2461 else if (AR_SREV_9280_20_OR_LATER(ah))
2462 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2463 else
2464 pCap->num_gpio_pins = AR_NUM_GPIO;
2465
2466 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2467 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2468 else
2469 pCap->rts_aggr_limit = (8 * 1024);
2470
2471 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2472 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2473 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2474 ah->rfkill_gpio =
2475 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2476 ah->rfkill_polarity =
2477 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2478
2479 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2480 }
2481 #endif
2482 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2483 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2484 else
2485 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2486
2487 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2488 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2489 else
2490 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2491
2492 if (AR_SREV_9300_20_OR_LATER(ah)) {
2493 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2494 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
2495 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2496
2497 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2498 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2499 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2500 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2501 pCap->txs_len = sizeof(struct ar9003_txs);
2502 } else {
2503 pCap->tx_desc_len = sizeof(struct ath_desc);
2504 if (AR_SREV_9280_20(ah))
2505 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2506 }
2507
2508 if (AR_SREV_9300_20_OR_LATER(ah))
2509 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2510
2511 if (AR_SREV_9300_20_OR_LATER(ah))
2512 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2513
2514 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2515 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2516
2517 if (AR_SREV_9285(ah))
2518 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2519 ant_div_ctl1 =
2520 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2521 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2522 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2523 }
2524 if (AR_SREV_9300_20_OR_LATER(ah)) {
2525 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2526 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2527 }
2528
2529
2530 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2531 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2532 /*
2533 * enable the diversity-combining algorithm only when
2534 * both enable_lna_div and enable_fast_div are set
2535 * Table for Diversity
2536 * ant_div_alt_lnaconf bit 0-1
2537 * ant_div_main_lnaconf bit 2-3
2538 * ant_div_alt_gaintb bit 4
2539 * ant_div_main_gaintb bit 5
2540 * enable_ant_div_lnadiv bit 6
2541 * enable_ant_fast_div bit 7
2542 */
2543 if ((ant_div_ctl1 >> 0x6) == 0x3)
2544 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2545 }
2546
2547 if (ath9k_hw_dfs_tested(ah))
2548 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2549
2550 tx_chainmask = pCap->tx_chainmask;
2551 rx_chainmask = pCap->rx_chainmask;
2552 while (tx_chainmask || rx_chainmask) {
2553 if (tx_chainmask & BIT(0))
2554 pCap->max_txchains++;
2555 if (rx_chainmask & BIT(0))
2556 pCap->max_rxchains++;
2557
2558 tx_chainmask >>= 1;
2559 rx_chainmask >>= 1;
2560 }
2561
2562 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2563 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2564 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2565
2566 if (AR_SREV_9462_20(ah))
2567 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2568 }
2569
2570 if (AR_SREV_9280_20_OR_LATER(ah)) {
2571 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE |
2572 ATH9K_HW_WOW_PATTERN_MATCH_EXACT;
2573
2574 if (AR_SREV_9280(ah))
2575 pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD;
2576 }
2577
2578 if (AR_SREV_9300_20_OR_LATER(ah) &&
2579 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2580 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2581
2582 return 0;
2583 }
2584
2585 /****************************/
2586 /* GPIO / RFKILL / Antennae */
2587 /****************************/
2588
2589 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2590 u32 gpio, u32 type)
2591 {
2592 int addr;
2593 u32 gpio_shift, tmp;
2594
2595 if (gpio > 11)
2596 addr = AR_GPIO_OUTPUT_MUX3;
2597 else if (gpio > 5)
2598 addr = AR_GPIO_OUTPUT_MUX2;
2599 else
2600 addr = AR_GPIO_OUTPUT_MUX1;
2601
2602 gpio_shift = (gpio % 6) * 5;
2603
2604 if (AR_SREV_9280_20_OR_LATER(ah)
2605 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2606 REG_RMW(ah, addr, (type << gpio_shift),
2607 (0x1f << gpio_shift));
2608 } else {
2609 tmp = REG_READ(ah, addr);
2610 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2611 tmp &= ~(0x1f << gpio_shift);
2612 tmp |= (type << gpio_shift);
2613 REG_WRITE(ah, addr, tmp);
2614 }
2615 }
2616
2617 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2618 {
2619 u32 gpio_shift;
2620
2621 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2622
2623 if (AR_DEVID_7010(ah)) {
2624 gpio_shift = gpio;
2625 REG_RMW(ah, AR7010_GPIO_OE,
2626 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2627 (AR7010_GPIO_OE_MASK << gpio_shift));
2628 return;
2629 }
2630
2631 gpio_shift = gpio << 1;
2632 REG_RMW(ah,
2633 AR_GPIO_OE_OUT,
2634 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2635 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2636 }
2637 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2638
2639 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2640 {
2641 #define MS_REG_READ(x, y) \
2642 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2643
2644 if (gpio >= ah->caps.num_gpio_pins)
2645 return 0xffffffff;
2646
2647 if (AR_DEVID_7010(ah)) {
2648 u32 val;
2649 val = REG_READ(ah, AR7010_GPIO_IN);
2650 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2651 } else if (AR_SREV_9300_20_OR_LATER(ah))
2652 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2653 AR_GPIO_BIT(gpio)) != 0;
2654 else if (AR_SREV_9271(ah))
2655 return MS_REG_READ(AR9271, gpio) != 0;
2656 else if (AR_SREV_9287_11_OR_LATER(ah))
2657 return MS_REG_READ(AR9287, gpio) != 0;
2658 else if (AR_SREV_9285_12_OR_LATER(ah))
2659 return MS_REG_READ(AR9285, gpio) != 0;
2660 else if (AR_SREV_9280_20_OR_LATER(ah))
2661 return MS_REG_READ(AR928X, gpio) != 0;
2662 else
2663 return MS_REG_READ(AR, gpio) != 0;
2664 }
2665 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2666
2667 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2668 u32 ah_signal_type)
2669 {
2670 u32 gpio_shift;
2671
2672 if (AR_DEVID_7010(ah)) {
2673 gpio_shift = gpio;
2674 REG_RMW(ah, AR7010_GPIO_OE,
2675 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2676 (AR7010_GPIO_OE_MASK << gpio_shift));
2677 return;
2678 }
2679
2680 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2681 gpio_shift = 2 * gpio;
2682 REG_RMW(ah,
2683 AR_GPIO_OE_OUT,
2684 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2685 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2686 }
2687 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2688
2689 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2690 {
2691 if (AR_DEVID_7010(ah)) {
2692 val = val ? 0 : 1;
2693 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2694 AR_GPIO_BIT(gpio));
2695 return;
2696 }
2697
2698 if (AR_SREV_9271(ah))
2699 val = ~val;
2700
2701 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2702 AR_GPIO_BIT(gpio));
2703 }
2704 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2705
2706 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2707 {
2708 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2709 }
2710 EXPORT_SYMBOL(ath9k_hw_setantenna);
2711
2712 /*********************/
2713 /* General Operation */
2714 /*********************/
2715
2716 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2717 {
2718 u32 bits = REG_READ(ah, AR_RX_FILTER);
2719 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2720
2721 if (phybits & AR_PHY_ERR_RADAR)
2722 bits |= ATH9K_RX_FILTER_PHYRADAR;
2723 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2724 bits |= ATH9K_RX_FILTER_PHYERR;
2725
2726 return bits;
2727 }
2728 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2729
2730 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2731 {
2732 u32 phybits;
2733
2734 ENABLE_REGWRITE_BUFFER(ah);
2735
2736 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2737 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2738
2739 REG_WRITE(ah, AR_RX_FILTER, bits);
2740
2741 phybits = 0;
2742 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2743 phybits |= AR_PHY_ERR_RADAR;
2744 if (bits & ATH9K_RX_FILTER_PHYERR)
2745 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2746 REG_WRITE(ah, AR_PHY_ERR, phybits);
2747
2748 if (phybits)
2749 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2750 else
2751 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2752
2753 REGWRITE_BUFFER_FLUSH(ah);
2754 }
2755 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2756
2757 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2758 {
2759 if (ath9k_hw_mci_is_enabled(ah))
2760 ar9003_mci_bt_gain_ctrl(ah);
2761
2762 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2763 return false;
2764
2765 ath9k_hw_init_pll(ah, NULL);
2766 ah->htc_reset_init = true;
2767 return true;
2768 }
2769 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2770
2771 bool ath9k_hw_disable(struct ath_hw *ah)
2772 {
2773 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2774 return false;
2775
2776 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2777 return false;
2778
2779 ath9k_hw_init_pll(ah, NULL);
2780 return true;
2781 }
2782 EXPORT_SYMBOL(ath9k_hw_disable);
2783
2784 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2785 {
2786 enum eeprom_param gain_param;
2787
2788 if (IS_CHAN_2GHZ(chan))
2789 gain_param = EEP_ANTENNA_GAIN_2G;
2790 else
2791 gain_param = EEP_ANTENNA_GAIN_5G;
2792
2793 return ah->eep_ops->get_eeprom(ah, gain_param);
2794 }
2795
2796 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2797 bool test)
2798 {
2799 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2800 struct ieee80211_channel *channel;
2801 int chan_pwr, new_pwr, max_gain;
2802 int ant_gain, ant_reduction = 0;
2803
2804 if (!chan)
2805 return;
2806
2807 channel = chan->chan;
2808 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2809 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2810 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2811
2812 ant_gain = get_antenna_gain(ah, chan);
2813 if (ant_gain > max_gain)
2814 ant_reduction = ant_gain - max_gain;
2815
2816 ah->eep_ops->set_txpower(ah, chan,
2817 ath9k_regd_get_ctl(reg, chan),
2818 ant_reduction, new_pwr, test);
2819 }
2820
2821 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2822 {
2823 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2824 struct ath9k_channel *chan = ah->curchan;
2825 struct ieee80211_channel *channel = chan->chan;
2826
2827 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2828 if (test)
2829 channel->max_power = MAX_RATE_POWER / 2;
2830
2831 ath9k_hw_apply_txpower(ah, chan, test);
2832
2833 if (test)
2834 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2835 }
2836 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2837
2838 void ath9k_hw_setopmode(struct ath_hw *ah)
2839 {
2840 ath9k_hw_set_operating_mode(ah, ah->opmode);
2841 }
2842 EXPORT_SYMBOL(ath9k_hw_setopmode);
2843
2844 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2845 {
2846 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2847 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2848 }
2849 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2850
2851 void ath9k_hw_write_associd(struct ath_hw *ah)
2852 {
2853 struct ath_common *common = ath9k_hw_common(ah);
2854
2855 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2856 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2857 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2858 }
2859 EXPORT_SYMBOL(ath9k_hw_write_associd);
2860
2861 #define ATH9K_MAX_TSF_READ 10
2862
2863 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2864 {
2865 u32 tsf_lower, tsf_upper1, tsf_upper2;
2866 int i;
2867
2868 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2869 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2870 tsf_lower = REG_READ(ah, AR_TSF_L32);
2871 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2872 if (tsf_upper2 == tsf_upper1)
2873 break;
2874 tsf_upper1 = tsf_upper2;
2875 }
2876
2877 WARN_ON( i == ATH9K_MAX_TSF_READ );
2878
2879 return (((u64)tsf_upper1 << 32) | tsf_lower);
2880 }
2881 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2882
2883 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2884 {
2885 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2886 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2887 }
2888 EXPORT_SYMBOL(ath9k_hw_settsf64);
2889
2890 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2891 {
2892 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2893 AH_TSF_WRITE_TIMEOUT))
2894 ath_dbg(ath9k_hw_common(ah), RESET,
2895 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2896
2897 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2898 }
2899 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2900
2901 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2902 {
2903 if (set)
2904 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2905 else
2906 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2907 }
2908 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2909
2910 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2911 {
2912 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2913 u32 macmode;
2914
2915 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2916 macmode = AR_2040_JOINED_RX_CLEAR;
2917 else
2918 macmode = 0;
2919
2920 REG_WRITE(ah, AR_2040_MODE, macmode);
2921 }
2922
2923 /* HW Generic timers configuration */
2924
2925 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2926 {
2927 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2928 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2929 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2930 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2931 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2932 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2933 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2934 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2935 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2936 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2937 AR_NDP2_TIMER_MODE, 0x0002},
2938 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2939 AR_NDP2_TIMER_MODE, 0x0004},
2940 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2941 AR_NDP2_TIMER_MODE, 0x0008},
2942 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2943 AR_NDP2_TIMER_MODE, 0x0010},
2944 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2945 AR_NDP2_TIMER_MODE, 0x0020},
2946 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2947 AR_NDP2_TIMER_MODE, 0x0040},
2948 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2949 AR_NDP2_TIMER_MODE, 0x0080}
2950 };
2951
2952 /* HW generic timer primitives */
2953
2954 /* compute and clear index of rightmost 1 */
2955 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2956 {
2957 u32 b;
2958
2959 b = *mask;
2960 b &= (0-b);
2961 *mask &= ~b;
2962 b *= debruijn32;
2963 b >>= 27;
2964
2965 return timer_table->gen_timer_index[b];
2966 }
2967
2968 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2969 {
2970 return REG_READ(ah, AR_TSF_L32);
2971 }
2972 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2973
2974 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2975 void (*trigger)(void *),
2976 void (*overflow)(void *),
2977 void *arg,
2978 u8 timer_index)
2979 {
2980 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2981 struct ath_gen_timer *timer;
2982
2983 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2984 if (timer == NULL)
2985 return NULL;
2986
2987 /* allocate a hardware generic timer slot */
2988 timer_table->timers[timer_index] = timer;
2989 timer->index = timer_index;
2990 timer->trigger = trigger;
2991 timer->overflow = overflow;
2992 timer->arg = arg;
2993
2994 return timer;
2995 }
2996 EXPORT_SYMBOL(ath_gen_timer_alloc);
2997
2998 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2999 struct ath_gen_timer *timer,
3000 u32 trig_timeout,
3001 u32 timer_period)
3002 {
3003 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3004 u32 tsf, timer_next;
3005
3006 BUG_ON(!timer_period);
3007
3008 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3009
3010 tsf = ath9k_hw_gettsf32(ah);
3011
3012 timer_next = tsf + trig_timeout;
3013
3014 ath_dbg(ath9k_hw_common(ah), HWTIMER,
3015 "current tsf %x period %x timer_next %x\n",
3016 tsf, timer_period, timer_next);
3017
3018 /*
3019 * Program generic timer registers
3020 */
3021 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3022 timer_next);
3023 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3024 timer_period);
3025 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3026 gen_tmr_configuration[timer->index].mode_mask);
3027
3028 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3029 /*
3030 * Starting from AR9462, each generic timer can select which tsf
3031 * to use. But we still follow the old rule, 0 - 7 use tsf and
3032 * 8 - 15 use tsf2.
3033 */
3034 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3035 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3036 (1 << timer->index));
3037 else
3038 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3039 (1 << timer->index));
3040 }
3041
3042 /* Enable both trigger and thresh interrupt masks */
3043 REG_SET_BIT(ah, AR_IMR_S5,
3044 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3045 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3046 }
3047 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3048
3049 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3050 {
3051 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3052
3053 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3054 (timer->index >= ATH_MAX_GEN_TIMER)) {
3055 return;
3056 }
3057
3058 /* Clear generic timer enable bits. */
3059 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3060 gen_tmr_configuration[timer->index].mode_mask);
3061
3062 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3063 /*
3064 * Need to switch back to TSF if it was using TSF2.
3065 */
3066 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3067 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3068 (1 << timer->index));
3069 }
3070 }
3071
3072 /* Disable both trigger and thresh interrupt masks */
3073 REG_CLR_BIT(ah, AR_IMR_S5,
3074 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3075 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3076
3077 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3078 }
3079 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3080
3081 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3082 {
3083 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3084
3085 /* free the hardware generic timer slot */
3086 timer_table->timers[timer->index] = NULL;
3087 kfree(timer);
3088 }
3089 EXPORT_SYMBOL(ath_gen_timer_free);
3090
3091 /*
3092 * Generic Timer Interrupts handling
3093 */
3094 void ath_gen_timer_isr(struct ath_hw *ah)
3095 {
3096 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3097 struct ath_gen_timer *timer;
3098 struct ath_common *common = ath9k_hw_common(ah);
3099 u32 trigger_mask, thresh_mask, index;
3100
3101 /* get hardware generic timer interrupt status */
3102 trigger_mask = ah->intr_gen_timer_trigger;
3103 thresh_mask = ah->intr_gen_timer_thresh;
3104 trigger_mask &= timer_table->timer_mask.val;
3105 thresh_mask &= timer_table->timer_mask.val;
3106
3107 trigger_mask &= ~thresh_mask;
3108
3109 while (thresh_mask) {
3110 index = rightmost_index(timer_table, &thresh_mask);
3111 timer = timer_table->timers[index];
3112 BUG_ON(!timer);
3113 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
3114 index);
3115 timer->overflow(timer->arg);
3116 }
3117
3118 while (trigger_mask) {
3119 index = rightmost_index(timer_table, &trigger_mask);
3120 timer = timer_table->timers[index];
3121 BUG_ON(!timer);
3122 ath_dbg(common, HWTIMER,
3123 "Gen timer[%d] trigger\n", index);
3124 timer->trigger(timer->arg);
3125 }
3126 }
3127 EXPORT_SYMBOL(ath_gen_timer_isr);
3128
3129 /********/
3130 /* HTC */
3131 /********/
3132
3133 static struct {
3134 u32 version;
3135 const char * name;
3136 } ath_mac_bb_names[] = {
3137 /* Devices with external radios */
3138 { AR_SREV_VERSION_5416_PCI, "5416" },
3139 { AR_SREV_VERSION_5416_PCIE, "5418" },
3140 { AR_SREV_VERSION_9100, "9100" },
3141 { AR_SREV_VERSION_9160, "9160" },
3142 /* Single-chip solutions */
3143 { AR_SREV_VERSION_9280, "9280" },
3144 { AR_SREV_VERSION_9285, "9285" },
3145 { AR_SREV_VERSION_9287, "9287" },
3146 { AR_SREV_VERSION_9271, "9271" },
3147 { AR_SREV_VERSION_9300, "9300" },
3148 { AR_SREV_VERSION_9330, "9330" },
3149 { AR_SREV_VERSION_9340, "9340" },
3150 { AR_SREV_VERSION_9485, "9485" },
3151 { AR_SREV_VERSION_9462, "9462" },
3152 { AR_SREV_VERSION_9550, "9550" },
3153 { AR_SREV_VERSION_9565, "9565" },
3154 };
3155
3156 /* For devices with external radios */
3157 static struct {
3158 u16 version;
3159 const char * name;
3160 } ath_rf_names[] = {
3161 { 0, "5133" },
3162 { AR_RAD5133_SREV_MAJOR, "5133" },
3163 { AR_RAD5122_SREV_MAJOR, "5122" },
3164 { AR_RAD2133_SREV_MAJOR, "2133" },
3165 { AR_RAD2122_SREV_MAJOR, "2122" }
3166 };
3167
3168 /*
3169 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3170 */
3171 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3172 {
3173 int i;
3174
3175 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3176 if (ath_mac_bb_names[i].version == mac_bb_version) {
3177 return ath_mac_bb_names[i].name;
3178 }
3179 }
3180
3181 return "????";
3182 }
3183
3184 /*
3185 * Return the RF name. "????" is returned if the RF is unknown.
3186 * Used for devices with external radios.
3187 */
3188 static const char *ath9k_hw_rf_name(u16 rf_version)
3189 {
3190 int i;
3191
3192 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3193 if (ath_rf_names[i].version == rf_version) {
3194 return ath_rf_names[i].name;
3195 }
3196 }
3197
3198 return "????";
3199 }
3200
3201 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3202 {
3203 int used;
3204
3205 /* chipsets >= AR9280 are single-chip */
3206 if (AR_SREV_9280_20_OR_LATER(ah)) {
3207 used = snprintf(hw_name, len,
3208 "Atheros AR%s Rev:%x",
3209 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3210 ah->hw_version.macRev);
3211 }
3212 else {
3213 used = snprintf(hw_name, len,
3214 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3215 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3216 ah->hw_version.macRev,
3217 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3218 AR_RADIO_SREV_MAJOR)),
3219 ah->hw_version.phyRev);
3220 }
3221
3222 hw_name[used] = '\0';
3223 }
3224 EXPORT_SYMBOL(ath9k_hw_name);
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