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Merge git://github.com/herbertx/crypto
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
92 clockrate = 117;
93 else if (!ah->curchan) /* should really check for CCK instead */
94 clockrate = ATH9K_CLOCK_RATE_CCK;
95 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
99 else
100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
101
102 if (conf_is_ht40(conf))
103 clockrate *= 2;
104
105 if (ah->curchan) {
106 if (IS_CHAN_HALF_RATE(ah->curchan))
107 clockrate /= 2;
108 if (IS_CHAN_QUARTER_RATE(ah->curchan))
109 clockrate /= 4;
110 }
111
112 common->clockrate = clockrate;
113 }
114
115 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
116 {
117 struct ath_common *common = ath9k_hw_common(ah);
118
119 return usecs * common->clockrate;
120 }
121
122 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
123 {
124 int i;
125
126 BUG_ON(timeout < AH_TIME_QUANTUM);
127
128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
129 if ((REG_READ(ah, reg) & mask) == val)
130 return true;
131
132 udelay(AH_TIME_QUANTUM);
133 }
134
135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
137 timeout, reg, REG_READ(ah, reg), mask, val);
138
139 return false;
140 }
141 EXPORT_SYMBOL(ath9k_hw_wait);
142
143 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
144 int column, unsigned int *writecnt)
145 {
146 int r;
147
148 ENABLE_REGWRITE_BUFFER(ah);
149 for (r = 0; r < array->ia_rows; r++) {
150 REG_WRITE(ah, INI_RA(array, r, 0),
151 INI_RA(array, r, column));
152 DO_DELAY(*writecnt);
153 }
154 REGWRITE_BUFFER_FLUSH(ah);
155 }
156
157 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
158 {
159 u32 retval;
160 int i;
161
162 for (i = 0, retval = 0; i < n; i++) {
163 retval = (retval << 1) | (val & 1);
164 val >>= 1;
165 }
166 return retval;
167 }
168
169 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
170 u8 phy, int kbps,
171 u32 frameLen, u16 rateix,
172 bool shortPreamble)
173 {
174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
175
176 if (kbps == 0)
177 return 0;
178
179 switch (phy) {
180 case WLAN_RC_PHY_CCK:
181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
182 if (shortPreamble)
183 phyTime >>= 1;
184 numBits = frameLen << 3;
185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
186 break;
187 case WLAN_RC_PHY_OFDM:
188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
190 numBits = OFDM_PLCP_BITS + (frameLen << 3);
191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
192 txTime = OFDM_SIFS_TIME_QUARTER
193 + OFDM_PREAMBLE_TIME_QUARTER
194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
195 } else if (ah->curchan &&
196 IS_CHAN_HALF_RATE(ah->curchan)) {
197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
203 } else {
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
208 + (numSymbols * OFDM_SYMBOL_TIME);
209 }
210 break;
211 default:
212 ath_err(ath9k_hw_common(ah),
213 "Unknown phy %u (rate ix %u)\n", phy, rateix);
214 txTime = 0;
215 break;
216 }
217
218 return txTime;
219 }
220 EXPORT_SYMBOL(ath9k_hw_computetxtime);
221
222 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
223 struct ath9k_channel *chan,
224 struct chan_centers *centers)
225 {
226 int8_t extoff;
227
228 if (!IS_CHAN_HT40(chan)) {
229 centers->ctl_center = centers->ext_center =
230 centers->synth_center = chan->channel;
231 return;
232 }
233
234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
235 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
236 centers->synth_center =
237 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
238 extoff = 1;
239 } else {
240 centers->synth_center =
241 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
242 extoff = -1;
243 }
244
245 centers->ctl_center =
246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers->ext_center =
249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
250 }
251
252 /******************/
253 /* Chip Revisions */
254 /******************/
255
256 static void ath9k_hw_read_revisions(struct ath_hw *ah)
257 {
258 u32 val;
259
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (ah->get_mac_revision) {
267 ah->hw_version.macRev = ah->get_mac_revision();
268 } else {
269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
271 }
272 return;
273 case AR9300_DEVID_AR9340:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
275 val = REG_READ(ah, AR_SREV);
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
277 return;
278 }
279
280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
281
282 if (val == 0xFF) {
283 val = REG_READ(ah, AR_SREV);
284 ah->hw_version.macVersion =
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
287
288 if (AR_SREV_9462(ah))
289 ah->is_pciexpress = true;
290 else
291 ah->is_pciexpress = (val &
292 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
293 } else {
294 if (!AR_SREV_9100(ah))
295 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
296
297 ah->hw_version.macRev = val & AR_SREV_REVISION;
298
299 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
300 ah->is_pciexpress = true;
301 }
302 }
303
304 /************************************/
305 /* HW Attach, Detach, Init Routines */
306 /************************************/
307
308 static void ath9k_hw_disablepcie(struct ath_hw *ah)
309 {
310 if (!AR_SREV_5416(ah))
311 return;
312
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
322
323 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
324 }
325
326 static void ath9k_hw_aspm_init(struct ath_hw *ah)
327 {
328 struct ath_common *common = ath9k_hw_common(ah);
329
330 if (common->bus_ops->aspm_init)
331 common->bus_ops->aspm_init(common);
332 }
333
334 /* This should work for all families including legacy */
335 static bool ath9k_hw_chip_test(struct ath_hw *ah)
336 {
337 struct ath_common *common = ath9k_hw_common(ah);
338 u32 regAddr[2] = { AR_STA_ID0 };
339 u32 regHold[2];
340 static const u32 patternData[4] = {
341 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
342 };
343 int i, j, loop_max;
344
345 if (!AR_SREV_9300_20_OR_LATER(ah)) {
346 loop_max = 2;
347 regAddr[1] = AR_PHY_BASE + (8 << 2);
348 } else
349 loop_max = 1;
350
351 for (i = 0; i < loop_max; i++) {
352 u32 addr = regAddr[i];
353 u32 wrData, rdData;
354
355 regHold[i] = REG_READ(ah, addr);
356 for (j = 0; j < 0x100; j++) {
357 wrData = (j << 16) | j;
358 REG_WRITE(ah, addr, wrData);
359 rdData = REG_READ(ah, addr);
360 if (rdData != wrData) {
361 ath_err(common,
362 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
363 addr, wrData, rdData);
364 return false;
365 }
366 }
367 for (j = 0; j < 4; j++) {
368 wrData = patternData[j];
369 REG_WRITE(ah, addr, wrData);
370 rdData = REG_READ(ah, addr);
371 if (wrData != rdData) {
372 ath_err(common,
373 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
374 addr, wrData, rdData);
375 return false;
376 }
377 }
378 REG_WRITE(ah, regAddr[i], regHold[i]);
379 }
380 udelay(100);
381
382 return true;
383 }
384
385 static void ath9k_hw_init_config(struct ath_hw *ah)
386 {
387 int i;
388
389 ah->config.dma_beacon_response_time = 2;
390 ah->config.sw_beacon_response_time = 10;
391 ah->config.additional_swba_backoff = 0;
392 ah->config.ack_6mb = 0x0;
393 ah->config.cwm_ignore_extcca = 0;
394 ah->config.pcie_clock_req = 0;
395 ah->config.pcie_waen = 0;
396 ah->config.analog_shiftreg = 1;
397 ah->config.enable_ani = true;
398
399 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
400 ah->config.spurchans[i][0] = AR_NO_SPUR;
401 ah->config.spurchans[i][1] = AR_NO_SPUR;
402 }
403
404 /* PAPRD needs some more work to be enabled */
405 ah->config.paprd_disable = 1;
406
407 ah->config.rx_intr_mitigation = true;
408 ah->config.pcieSerDesWrite = true;
409
410 /*
411 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
412 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
413 * This means we use it for all AR5416 devices, and the few
414 * minor PCI AR9280 devices out there.
415 *
416 * Serialization is required because these devices do not handle
417 * well the case of two concurrent reads/writes due to the latency
418 * involved. During one read/write another read/write can be issued
419 * on another CPU while the previous read/write may still be working
420 * on our hardware, if we hit this case the hardware poops in a loop.
421 * We prevent this by serializing reads and writes.
422 *
423 * This issue is not present on PCI-Express devices or pre-AR5416
424 * devices (legacy, 802.11abg).
425 */
426 if (num_possible_cpus() > 1)
427 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
428 }
429
430 static void ath9k_hw_init_defaults(struct ath_hw *ah)
431 {
432 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
433
434 regulatory->country_code = CTRY_DEFAULT;
435 regulatory->power_limit = MAX_RATE_POWER;
436
437 ah->hw_version.magic = AR5416_MAGIC;
438 ah->hw_version.subvendorid = 0;
439
440 ah->atim_window = 0;
441 ah->sta_id1_defaults =
442 AR_STA_ID1_CRPT_MIC_ENABLE |
443 AR_STA_ID1_MCAST_KSRCH;
444 if (AR_SREV_9100(ah))
445 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
446 ah->enable_32kHz_clock = DONT_USE_32KHZ;
447 ah->slottime = ATH9K_SLOT_TIME_9;
448 ah->globaltxtimeout = (u32) -1;
449 ah->power_mode = ATH9K_PM_UNDEFINED;
450 }
451
452 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
453 {
454 struct ath_common *common = ath9k_hw_common(ah);
455 u32 sum;
456 int i;
457 u16 eeval;
458 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
459
460 sum = 0;
461 for (i = 0; i < 3; i++) {
462 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
463 sum += eeval;
464 common->macaddr[2 * i] = eeval >> 8;
465 common->macaddr[2 * i + 1] = eeval & 0xff;
466 }
467 if (sum == 0 || sum == 0xffff * 3)
468 return -EADDRNOTAVAIL;
469
470 return 0;
471 }
472
473 static int ath9k_hw_post_init(struct ath_hw *ah)
474 {
475 struct ath_common *common = ath9k_hw_common(ah);
476 int ecode;
477
478 if (common->bus_ops->ath_bus_type != ATH_USB) {
479 if (!ath9k_hw_chip_test(ah))
480 return -ENODEV;
481 }
482
483 if (!AR_SREV_9300_20_OR_LATER(ah)) {
484 ecode = ar9002_hw_rf_claim(ah);
485 if (ecode != 0)
486 return ecode;
487 }
488
489 ecode = ath9k_hw_eeprom_init(ah);
490 if (ecode != 0)
491 return ecode;
492
493 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
494 "Eeprom VER: %d, REV: %d\n",
495 ah->eep_ops->get_eeprom_ver(ah),
496 ah->eep_ops->get_eeprom_rev(ah));
497
498 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
499 if (ecode) {
500 ath_err(ath9k_hw_common(ah),
501 "Failed allocating banks for external radio\n");
502 ath9k_hw_rf_free_ext_banks(ah);
503 return ecode;
504 }
505
506 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
507 ath9k_hw_ani_setup(ah);
508 ath9k_hw_ani_init(ah);
509 }
510
511 return 0;
512 }
513
514 static void ath9k_hw_attach_ops(struct ath_hw *ah)
515 {
516 if (AR_SREV_9300_20_OR_LATER(ah))
517 ar9003_hw_attach_ops(ah);
518 else
519 ar9002_hw_attach_ops(ah);
520 }
521
522 /* Called for all hardware families */
523 static int __ath9k_hw_init(struct ath_hw *ah)
524 {
525 struct ath_common *common = ath9k_hw_common(ah);
526 int r = 0;
527
528 ath9k_hw_read_revisions(ah);
529
530 /*
531 * Read back AR_WA into a permanent copy and set bits 14 and 17.
532 * We need to do this to avoid RMW of this register. We cannot
533 * read the reg when chip is asleep.
534 */
535 ah->WARegVal = REG_READ(ah, AR_WA);
536 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
537 AR_WA_ASPM_TIMER_BASED_DISABLE);
538
539 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
540 ath_err(common, "Couldn't reset chip\n");
541 return -EIO;
542 }
543
544 if (AR_SREV_9462(ah))
545 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
546
547 ath9k_hw_init_defaults(ah);
548 ath9k_hw_init_config(ah);
549
550 ath9k_hw_attach_ops(ah);
551
552 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
553 ath_err(common, "Couldn't wakeup chip\n");
554 return -EIO;
555 }
556
557 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
558 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
559 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
560 !ah->is_pciexpress)) {
561 ah->config.serialize_regmode =
562 SER_REG_MODE_ON;
563 } else {
564 ah->config.serialize_regmode =
565 SER_REG_MODE_OFF;
566 }
567 }
568
569 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
570 ah->config.serialize_regmode);
571
572 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
573 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
574 else
575 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
576
577 switch (ah->hw_version.macVersion) {
578 case AR_SREV_VERSION_5416_PCI:
579 case AR_SREV_VERSION_5416_PCIE:
580 case AR_SREV_VERSION_9160:
581 case AR_SREV_VERSION_9100:
582 case AR_SREV_VERSION_9280:
583 case AR_SREV_VERSION_9285:
584 case AR_SREV_VERSION_9287:
585 case AR_SREV_VERSION_9271:
586 case AR_SREV_VERSION_9300:
587 case AR_SREV_VERSION_9330:
588 case AR_SREV_VERSION_9485:
589 case AR_SREV_VERSION_9340:
590 case AR_SREV_VERSION_9462:
591 break;
592 default:
593 ath_err(common,
594 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
595 ah->hw_version.macVersion, ah->hw_version.macRev);
596 return -EOPNOTSUPP;
597 }
598
599 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
600 AR_SREV_9330(ah))
601 ah->is_pciexpress = false;
602
603 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
604 ath9k_hw_init_cal_settings(ah);
605
606 ah->ani_function = ATH9K_ANI_ALL;
607 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
608 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
609 if (!AR_SREV_9300_20_OR_LATER(ah))
610 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
611
612 ath9k_hw_init_mode_regs(ah);
613
614 if (!ah->is_pciexpress)
615 ath9k_hw_disablepcie(ah);
616
617 if (!AR_SREV_9300_20_OR_LATER(ah))
618 ar9002_hw_cck_chan14_spread(ah);
619
620 r = ath9k_hw_post_init(ah);
621 if (r)
622 return r;
623
624 ath9k_hw_init_mode_gain_regs(ah);
625 r = ath9k_hw_fill_cap_info(ah);
626 if (r)
627 return r;
628
629 if (ah->is_pciexpress)
630 ath9k_hw_aspm_init(ah);
631
632 r = ath9k_hw_init_macaddr(ah);
633 if (r) {
634 ath_err(common, "Failed to initialize MAC address\n");
635 return r;
636 }
637
638 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
639 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
640 else
641 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
642
643 if (AR_SREV_9330(ah))
644 ah->bb_watchdog_timeout_ms = 85;
645 else
646 ah->bb_watchdog_timeout_ms = 25;
647
648 common->state = ATH_HW_INITIALIZED;
649
650 return 0;
651 }
652
653 int ath9k_hw_init(struct ath_hw *ah)
654 {
655 int ret;
656 struct ath_common *common = ath9k_hw_common(ah);
657
658 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
659 switch (ah->hw_version.devid) {
660 case AR5416_DEVID_PCI:
661 case AR5416_DEVID_PCIE:
662 case AR5416_AR9100_DEVID:
663 case AR9160_DEVID_PCI:
664 case AR9280_DEVID_PCI:
665 case AR9280_DEVID_PCIE:
666 case AR9285_DEVID_PCIE:
667 case AR9287_DEVID_PCI:
668 case AR9287_DEVID_PCIE:
669 case AR2427_DEVID_PCIE:
670 case AR9300_DEVID_PCIE:
671 case AR9300_DEVID_AR9485_PCIE:
672 case AR9300_DEVID_AR9330:
673 case AR9300_DEVID_AR9340:
674 case AR9300_DEVID_AR9580:
675 case AR9300_DEVID_AR9462:
676 break;
677 default:
678 if (common->bus_ops->ath_bus_type == ATH_USB)
679 break;
680 ath_err(common, "Hardware device ID 0x%04x not supported\n",
681 ah->hw_version.devid);
682 return -EOPNOTSUPP;
683 }
684
685 ret = __ath9k_hw_init(ah);
686 if (ret) {
687 ath_err(common,
688 "Unable to initialize hardware; initialization status: %d\n",
689 ret);
690 return ret;
691 }
692
693 return 0;
694 }
695 EXPORT_SYMBOL(ath9k_hw_init);
696
697 static void ath9k_hw_init_qos(struct ath_hw *ah)
698 {
699 ENABLE_REGWRITE_BUFFER(ah);
700
701 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
702 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
703
704 REG_WRITE(ah, AR_QOS_NO_ACK,
705 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
706 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
707 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
708
709 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
710 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
711 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
712 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
713 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
714
715 REGWRITE_BUFFER_FLUSH(ah);
716 }
717
718 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
719 {
720 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
721 udelay(100);
722 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
723
724 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
725 udelay(100);
726
727 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
728 }
729 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
730
731 static void ath9k_hw_init_pll(struct ath_hw *ah,
732 struct ath9k_channel *chan)
733 {
734 u32 pll;
735
736 if (AR_SREV_9485(ah)) {
737
738 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
739 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
740 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
741 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
742 AR_CH0_DPLL2_KD, 0x40);
743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
744 AR_CH0_DPLL2_KI, 0x4);
745
746 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
747 AR_CH0_BB_DPLL1_REFDIV, 0x5);
748 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
749 AR_CH0_BB_DPLL1_NINI, 0x58);
750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
751 AR_CH0_BB_DPLL1_NFRAC, 0x0);
752
753 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
754 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
755 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
756 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
758 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
759
760 /* program BB PLL phase_shift to 0x6 */
761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
762 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
763
764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
765 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
766 udelay(1000);
767 } else if (AR_SREV_9330(ah)) {
768 u32 ddr_dpll2, pll_control2, kd;
769
770 if (ah->is_clk_25mhz) {
771 ddr_dpll2 = 0x18e82f01;
772 pll_control2 = 0xe04a3d;
773 kd = 0x1d;
774 } else {
775 ddr_dpll2 = 0x19e82f01;
776 pll_control2 = 0x886666;
777 kd = 0x3d;
778 }
779
780 /* program DDR PLL ki and kd value */
781 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
782
783 /* program DDR PLL phase_shift */
784 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
785 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
786
787 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
788 udelay(1000);
789
790 /* program refdiv, nint, frac to RTC register */
791 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
792
793 /* program BB PLL kd and ki value */
794 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
796
797 /* program BB PLL phase_shift */
798 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
799 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
800 } else if (AR_SREV_9340(ah)) {
801 u32 regval, pll2_divint, pll2_divfrac, refdiv;
802
803 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
804 udelay(1000);
805
806 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
807 udelay(100);
808
809 if (ah->is_clk_25mhz) {
810 pll2_divint = 0x54;
811 pll2_divfrac = 0x1eb85;
812 refdiv = 3;
813 } else {
814 pll2_divint = 88;
815 pll2_divfrac = 0;
816 refdiv = 5;
817 }
818
819 regval = REG_READ(ah, AR_PHY_PLL_MODE);
820 regval |= (0x1 << 16);
821 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
822 udelay(100);
823
824 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
825 (pll2_divint << 18) | pll2_divfrac);
826 udelay(100);
827
828 regval = REG_READ(ah, AR_PHY_PLL_MODE);
829 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
830 (0x4 << 26) | (0x18 << 19);
831 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
832 REG_WRITE(ah, AR_PHY_PLL_MODE,
833 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
834 udelay(1000);
835 }
836
837 pll = ath9k_hw_compute_pll_control(ah, chan);
838
839 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
840
841 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
842 udelay(1000);
843
844 /* Switch the core clock for ar9271 to 117Mhz */
845 if (AR_SREV_9271(ah)) {
846 udelay(500);
847 REG_WRITE(ah, 0x50040, 0x304);
848 }
849
850 udelay(RTC_PLL_SETTLE_DELAY);
851
852 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
853
854 if (AR_SREV_9340(ah)) {
855 if (ah->is_clk_25mhz) {
856 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
857 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
858 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
859 } else {
860 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
861 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
862 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
863 }
864 udelay(100);
865 }
866 }
867
868 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
869 enum nl80211_iftype opmode)
870 {
871 u32 sync_default = AR_INTR_SYNC_DEFAULT;
872 u32 imr_reg = AR_IMR_TXERR |
873 AR_IMR_TXURN |
874 AR_IMR_RXERR |
875 AR_IMR_RXORN |
876 AR_IMR_BCNMISC;
877
878 if (AR_SREV_9340(ah))
879 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
880
881 if (AR_SREV_9300_20_OR_LATER(ah)) {
882 imr_reg |= AR_IMR_RXOK_HP;
883 if (ah->config.rx_intr_mitigation)
884 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
885 else
886 imr_reg |= AR_IMR_RXOK_LP;
887
888 } else {
889 if (ah->config.rx_intr_mitigation)
890 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
891 else
892 imr_reg |= AR_IMR_RXOK;
893 }
894
895 if (ah->config.tx_intr_mitigation)
896 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
897 else
898 imr_reg |= AR_IMR_TXOK;
899
900 if (opmode == NL80211_IFTYPE_AP)
901 imr_reg |= AR_IMR_MIB;
902
903 ENABLE_REGWRITE_BUFFER(ah);
904
905 REG_WRITE(ah, AR_IMR, imr_reg);
906 ah->imrs2_reg |= AR_IMR_S2_GTT;
907 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
908
909 if (!AR_SREV_9100(ah)) {
910 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
911 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
912 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
913 }
914
915 REGWRITE_BUFFER_FLUSH(ah);
916
917 if (AR_SREV_9300_20_OR_LATER(ah)) {
918 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
919 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
920 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
921 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
922 }
923 }
924
925 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
926 {
927 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
928 val = min(val, (u32) 0xFFFF);
929 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
930 }
931
932 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
933 {
934 u32 val = ath9k_hw_mac_to_clks(ah, us);
935 val = min(val, (u32) 0xFFFF);
936 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
937 }
938
939 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
940 {
941 u32 val = ath9k_hw_mac_to_clks(ah, us);
942 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
943 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
944 }
945
946 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
947 {
948 u32 val = ath9k_hw_mac_to_clks(ah, us);
949 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
950 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
951 }
952
953 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
954 {
955 if (tu > 0xFFFF) {
956 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
957 "bad global tx timeout %u\n", tu);
958 ah->globaltxtimeout = (u32) -1;
959 return false;
960 } else {
961 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
962 ah->globaltxtimeout = tu;
963 return true;
964 }
965 }
966
967 void ath9k_hw_init_global_settings(struct ath_hw *ah)
968 {
969 struct ath_common *common = ath9k_hw_common(ah);
970 struct ieee80211_conf *conf = &common->hw->conf;
971 const struct ath9k_channel *chan = ah->curchan;
972 int acktimeout, ctstimeout;
973 int slottime;
974 int sifstime;
975 int rx_lat = 0, tx_lat = 0, eifs = 0;
976 u32 reg;
977
978 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
979 ah->misc_mode);
980
981 if (!chan)
982 return;
983
984 if (ah->misc_mode != 0)
985 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
986
987 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
988 rx_lat = 41;
989 else
990 rx_lat = 37;
991 tx_lat = 54;
992
993 if (IS_CHAN_HALF_RATE(chan)) {
994 eifs = 175;
995 rx_lat *= 2;
996 tx_lat *= 2;
997 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
998 tx_lat += 11;
999
1000 slottime = 13;
1001 sifstime = 32;
1002 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1003 eifs = 340;
1004 rx_lat = (rx_lat * 4) - 1;
1005 tx_lat *= 4;
1006 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1007 tx_lat += 22;
1008
1009 slottime = 21;
1010 sifstime = 64;
1011 } else {
1012 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1013 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1014 reg = AR_USEC_ASYNC_FIFO;
1015 } else {
1016 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1017 common->clockrate;
1018 reg = REG_READ(ah, AR_USEC);
1019 }
1020 rx_lat = MS(reg, AR_USEC_RX_LAT);
1021 tx_lat = MS(reg, AR_USEC_TX_LAT);
1022
1023 slottime = ah->slottime;
1024 if (IS_CHAN_5GHZ(chan))
1025 sifstime = 16;
1026 else
1027 sifstime = 10;
1028 }
1029
1030 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1031 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1032 ctstimeout = acktimeout;
1033
1034 /*
1035 * Workaround for early ACK timeouts, add an offset to match the
1036 * initval's 64us ack timeout value.
1037 * This was initially only meant to work around an issue with delayed
1038 * BA frames in some implementations, but it has been found to fix ACK
1039 * timeout issues in other cases as well.
1040 */
1041 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1042 acktimeout += 64 - sifstime - ah->slottime;
1043
1044 ath9k_hw_set_sifs_time(ah, sifstime);
1045 ath9k_hw_setslottime(ah, slottime);
1046 ath9k_hw_set_ack_timeout(ah, acktimeout);
1047 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1048 if (ah->globaltxtimeout != (u32) -1)
1049 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1050
1051 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1052 REG_RMW(ah, AR_USEC,
1053 (common->clockrate - 1) |
1054 SM(rx_lat, AR_USEC_RX_LAT) |
1055 SM(tx_lat, AR_USEC_TX_LAT),
1056 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1057
1058 }
1059 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1060
1061 void ath9k_hw_deinit(struct ath_hw *ah)
1062 {
1063 struct ath_common *common = ath9k_hw_common(ah);
1064
1065 if (common->state < ATH_HW_INITIALIZED)
1066 goto free_hw;
1067
1068 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1069
1070 free_hw:
1071 ath9k_hw_rf_free_ext_banks(ah);
1072 }
1073 EXPORT_SYMBOL(ath9k_hw_deinit);
1074
1075 /*******/
1076 /* INI */
1077 /*******/
1078
1079 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1080 {
1081 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1082
1083 if (IS_CHAN_B(chan))
1084 ctl |= CTL_11B;
1085 else if (IS_CHAN_G(chan))
1086 ctl |= CTL_11G;
1087 else
1088 ctl |= CTL_11A;
1089
1090 return ctl;
1091 }
1092
1093 /****************************************/
1094 /* Reset and Channel Switching Routines */
1095 /****************************************/
1096
1097 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1098 {
1099 struct ath_common *common = ath9k_hw_common(ah);
1100
1101 ENABLE_REGWRITE_BUFFER(ah);
1102
1103 /*
1104 * set AHB_MODE not to do cacheline prefetches
1105 */
1106 if (!AR_SREV_9300_20_OR_LATER(ah))
1107 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1108
1109 /*
1110 * let mac dma reads be in 128 byte chunks
1111 */
1112 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1113
1114 REGWRITE_BUFFER_FLUSH(ah);
1115
1116 /*
1117 * Restore TX Trigger Level to its pre-reset value.
1118 * The initial value depends on whether aggregation is enabled, and is
1119 * adjusted whenever underruns are detected.
1120 */
1121 if (!AR_SREV_9300_20_OR_LATER(ah))
1122 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1123
1124 ENABLE_REGWRITE_BUFFER(ah);
1125
1126 /*
1127 * let mac dma writes be in 128 byte chunks
1128 */
1129 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1130
1131 /*
1132 * Setup receive FIFO threshold to hold off TX activities
1133 */
1134 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1135
1136 if (AR_SREV_9300_20_OR_LATER(ah)) {
1137 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1138 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1139
1140 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1141 ah->caps.rx_status_len);
1142 }
1143
1144 /*
1145 * reduce the number of usable entries in PCU TXBUF to avoid
1146 * wrap around issues.
1147 */
1148 if (AR_SREV_9285(ah)) {
1149 /* For AR9285 the number of Fifos are reduced to half.
1150 * So set the usable tx buf size also to half to
1151 * avoid data/delimiter underruns
1152 */
1153 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1154 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1155 } else if (!AR_SREV_9271(ah)) {
1156 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1157 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1158 }
1159
1160 REGWRITE_BUFFER_FLUSH(ah);
1161
1162 if (AR_SREV_9300_20_OR_LATER(ah))
1163 ath9k_hw_reset_txstatus_ring(ah);
1164 }
1165
1166 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1167 {
1168 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1169 u32 set = AR_STA_ID1_KSRCH_MODE;
1170
1171 switch (opmode) {
1172 case NL80211_IFTYPE_ADHOC:
1173 case NL80211_IFTYPE_MESH_POINT:
1174 set |= AR_STA_ID1_ADHOC;
1175 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1176 break;
1177 case NL80211_IFTYPE_AP:
1178 set |= AR_STA_ID1_STA_AP;
1179 /* fall through */
1180 case NL80211_IFTYPE_STATION:
1181 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1182 break;
1183 default:
1184 if (!ah->is_monitoring)
1185 set = 0;
1186 break;
1187 }
1188 REG_RMW(ah, AR_STA_ID1, set, mask);
1189 }
1190
1191 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1192 u32 *coef_mantissa, u32 *coef_exponent)
1193 {
1194 u32 coef_exp, coef_man;
1195
1196 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1197 if ((coef_scaled >> coef_exp) & 0x1)
1198 break;
1199
1200 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1201
1202 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1203
1204 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1205 *coef_exponent = coef_exp - 16;
1206 }
1207
1208 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1209 {
1210 u32 rst_flags;
1211 u32 tmpReg;
1212
1213 if (AR_SREV_9100(ah)) {
1214 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1215 AR_RTC_DERIVED_CLK_PERIOD, 1);
1216 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1217 }
1218
1219 ENABLE_REGWRITE_BUFFER(ah);
1220
1221 if (AR_SREV_9300_20_OR_LATER(ah)) {
1222 REG_WRITE(ah, AR_WA, ah->WARegVal);
1223 udelay(10);
1224 }
1225
1226 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1227 AR_RTC_FORCE_WAKE_ON_INT);
1228
1229 if (AR_SREV_9100(ah)) {
1230 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1231 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1232 } else {
1233 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1234 if (tmpReg &
1235 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1236 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1237 u32 val;
1238 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1239
1240 val = AR_RC_HOSTIF;
1241 if (!AR_SREV_9300_20_OR_LATER(ah))
1242 val |= AR_RC_AHB;
1243 REG_WRITE(ah, AR_RC, val);
1244
1245 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1246 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1247
1248 rst_flags = AR_RTC_RC_MAC_WARM;
1249 if (type == ATH9K_RESET_COLD)
1250 rst_flags |= AR_RTC_RC_MAC_COLD;
1251 }
1252
1253 if (AR_SREV_9330(ah)) {
1254 int npend = 0;
1255 int i;
1256
1257 /* AR9330 WAR:
1258 * call external reset function to reset WMAC if:
1259 * - doing a cold reset
1260 * - we have pending frames in the TX queues
1261 */
1262
1263 for (i = 0; i < AR_NUM_QCU; i++) {
1264 npend = ath9k_hw_numtxpending(ah, i);
1265 if (npend)
1266 break;
1267 }
1268
1269 if (ah->external_reset &&
1270 (npend || type == ATH9K_RESET_COLD)) {
1271 int reset_err = 0;
1272
1273 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1274 "reset MAC via external reset\n");
1275
1276 reset_err = ah->external_reset();
1277 if (reset_err) {
1278 ath_err(ath9k_hw_common(ah),
1279 "External reset failed, err=%d\n",
1280 reset_err);
1281 return false;
1282 }
1283
1284 REG_WRITE(ah, AR_RTC_RESET, 1);
1285 }
1286 }
1287
1288 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1289
1290 REGWRITE_BUFFER_FLUSH(ah);
1291
1292 udelay(50);
1293
1294 REG_WRITE(ah, AR_RTC_RC, 0);
1295 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1296 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1297 "RTC stuck in MAC reset\n");
1298 return false;
1299 }
1300
1301 if (!AR_SREV_9100(ah))
1302 REG_WRITE(ah, AR_RC, 0);
1303
1304 if (AR_SREV_9100(ah))
1305 udelay(50);
1306
1307 return true;
1308 }
1309
1310 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1311 {
1312 ENABLE_REGWRITE_BUFFER(ah);
1313
1314 if (AR_SREV_9300_20_OR_LATER(ah)) {
1315 REG_WRITE(ah, AR_WA, ah->WARegVal);
1316 udelay(10);
1317 }
1318
1319 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1320 AR_RTC_FORCE_WAKE_ON_INT);
1321
1322 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1323 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1324
1325 REG_WRITE(ah, AR_RTC_RESET, 0);
1326
1327 REGWRITE_BUFFER_FLUSH(ah);
1328
1329 if (!AR_SREV_9300_20_OR_LATER(ah))
1330 udelay(2);
1331
1332 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1333 REG_WRITE(ah, AR_RC, 0);
1334
1335 REG_WRITE(ah, AR_RTC_RESET, 1);
1336
1337 if (!ath9k_hw_wait(ah,
1338 AR_RTC_STATUS,
1339 AR_RTC_STATUS_M,
1340 AR_RTC_STATUS_ON,
1341 AH_WAIT_TIMEOUT)) {
1342 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1343 "RTC not waking up\n");
1344 return false;
1345 }
1346
1347 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1348 }
1349
1350 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1351 {
1352
1353 if (AR_SREV_9300_20_OR_LATER(ah)) {
1354 REG_WRITE(ah, AR_WA, ah->WARegVal);
1355 udelay(10);
1356 }
1357
1358 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1359 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1360
1361 switch (type) {
1362 case ATH9K_RESET_POWER_ON:
1363 return ath9k_hw_set_reset_power_on(ah);
1364 case ATH9K_RESET_WARM:
1365 case ATH9K_RESET_COLD:
1366 return ath9k_hw_set_reset(ah, type);
1367 default:
1368 return false;
1369 }
1370 }
1371
1372 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1373 struct ath9k_channel *chan)
1374 {
1375 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1376 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1377 return false;
1378 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1379 return false;
1380
1381 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1382 return false;
1383
1384 ah->chip_fullsleep = false;
1385 ath9k_hw_init_pll(ah, chan);
1386 ath9k_hw_set_rfmode(ah, chan);
1387
1388 return true;
1389 }
1390
1391 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1392 struct ath9k_channel *chan)
1393 {
1394 struct ath_common *common = ath9k_hw_common(ah);
1395 u32 qnum;
1396 int r;
1397 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1398 bool band_switch, mode_diff;
1399 u8 ini_reloaded;
1400
1401 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1402 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1403 CHANNEL_5GHZ));
1404 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1405
1406 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1407 if (ath9k_hw_numtxpending(ah, qnum)) {
1408 ath_dbg(common, ATH_DBG_QUEUE,
1409 "Transmit frames pending on queue %d\n", qnum);
1410 return false;
1411 }
1412 }
1413
1414 if (!ath9k_hw_rfbus_req(ah)) {
1415 ath_err(common, "Could not kill baseband RX\n");
1416 return false;
1417 }
1418
1419 if (edma && (band_switch || mode_diff)) {
1420 ath9k_hw_mark_phy_inactive(ah);
1421 udelay(5);
1422
1423 ath9k_hw_init_pll(ah, NULL);
1424
1425 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1426 ath_err(common, "Failed to do fast channel change\n");
1427 return false;
1428 }
1429 }
1430
1431 ath9k_hw_set_channel_regs(ah, chan);
1432
1433 r = ath9k_hw_rf_set_freq(ah, chan);
1434 if (r) {
1435 ath_err(common, "Failed to set channel\n");
1436 return false;
1437 }
1438 ath9k_hw_set_clockrate(ah);
1439 ath9k_hw_apply_txpower(ah, chan);
1440 ath9k_hw_rfbus_done(ah);
1441
1442 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1443 ath9k_hw_set_delta_slope(ah, chan);
1444
1445 ath9k_hw_spur_mitigate_freq(ah, chan);
1446
1447 if (edma && (band_switch || mode_diff)) {
1448 ah->ah_flags |= AH_FASTCC;
1449 if (band_switch || ini_reloaded)
1450 ah->eep_ops->set_board_values(ah, chan);
1451
1452 ath9k_hw_init_bb(ah, chan);
1453
1454 if (band_switch || ini_reloaded)
1455 ath9k_hw_init_cal(ah, chan);
1456 ah->ah_flags &= ~AH_FASTCC;
1457 }
1458
1459 return true;
1460 }
1461
1462 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1463 {
1464 u32 gpio_mask = ah->gpio_mask;
1465 int i;
1466
1467 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1468 if (!(gpio_mask & 1))
1469 continue;
1470
1471 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1472 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1473 }
1474 }
1475
1476 bool ath9k_hw_check_alive(struct ath_hw *ah)
1477 {
1478 int count = 50;
1479 u32 reg;
1480
1481 if (AR_SREV_9285_12_OR_LATER(ah))
1482 return true;
1483
1484 do {
1485 reg = REG_READ(ah, AR_OBS_BUS_1);
1486
1487 if ((reg & 0x7E7FFFEF) == 0x00702400)
1488 continue;
1489
1490 switch (reg & 0x7E000B00) {
1491 case 0x1E000000:
1492 case 0x52000B00:
1493 case 0x18000B00:
1494 continue;
1495 default:
1496 return true;
1497 }
1498 } while (count-- > 0);
1499
1500 return false;
1501 }
1502 EXPORT_SYMBOL(ath9k_hw_check_alive);
1503
1504 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1505 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1506 {
1507 struct ath_common *common = ath9k_hw_common(ah);
1508 u32 saveLedState;
1509 struct ath9k_channel *curchan = ah->curchan;
1510 u32 saveDefAntenna;
1511 u32 macStaId1;
1512 u64 tsf = 0;
1513 int i, r;
1514 bool allow_fbs = false;
1515
1516 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1517 return -EIO;
1518
1519 if (curchan && !ah->chip_fullsleep)
1520 ath9k_hw_getnf(ah, curchan);
1521
1522 ah->caldata = caldata;
1523 if (caldata &&
1524 (chan->channel != caldata->channel ||
1525 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1526 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1527 /* Operating channel changed, reset channel calibration data */
1528 memset(caldata, 0, sizeof(*caldata));
1529 ath9k_init_nfcal_hist_buffer(ah, chan);
1530 }
1531 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1532
1533 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1534 bChannelChange = false;
1535
1536 if (caldata &&
1537 caldata->done_txiqcal_once &&
1538 caldata->done_txclcal_once &&
1539 caldata->rtt_hist.num_readings)
1540 allow_fbs = true;
1541
1542 if (bChannelChange &&
1543 (ah->chip_fullsleep != true) &&
1544 (ah->curchan != NULL) &&
1545 (chan->channel != ah->curchan->channel) &&
1546 (allow_fbs ||
1547 ((chan->channelFlags & CHANNEL_ALL) ==
1548 (ah->curchan->channelFlags & CHANNEL_ALL)))) {
1549 if (ath9k_hw_channel_change(ah, chan)) {
1550 ath9k_hw_loadnf(ah, ah->curchan);
1551 ath9k_hw_start_nfcal(ah, true);
1552 if (AR_SREV_9271(ah))
1553 ar9002_hw_load_ani_reg(ah, chan);
1554 return 0;
1555 }
1556 }
1557
1558 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1559 if (saveDefAntenna == 0)
1560 saveDefAntenna = 1;
1561
1562 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1563
1564 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1565 if (AR_SREV_9100(ah) ||
1566 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1567 tsf = ath9k_hw_gettsf64(ah);
1568
1569 saveLedState = REG_READ(ah, AR_CFG_LED) &
1570 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1571 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1572
1573 ath9k_hw_mark_phy_inactive(ah);
1574
1575 ah->paprd_table_write_done = false;
1576
1577 /* Only required on the first reset */
1578 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1579 REG_WRITE(ah,
1580 AR9271_RESET_POWER_DOWN_CONTROL,
1581 AR9271_RADIO_RF_RST);
1582 udelay(50);
1583 }
1584
1585 if (!ath9k_hw_chip_reset(ah, chan)) {
1586 ath_err(common, "Chip reset failed\n");
1587 return -EINVAL;
1588 }
1589
1590 /* Only required on the first reset */
1591 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1592 ah->htc_reset_init = false;
1593 REG_WRITE(ah,
1594 AR9271_RESET_POWER_DOWN_CONTROL,
1595 AR9271_GATE_MAC_CTL);
1596 udelay(50);
1597 }
1598
1599 /* Restore TSF */
1600 if (tsf)
1601 ath9k_hw_settsf64(ah, tsf);
1602
1603 if (AR_SREV_9280_20_OR_LATER(ah))
1604 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1605
1606 if (!AR_SREV_9300_20_OR_LATER(ah))
1607 ar9002_hw_enable_async_fifo(ah);
1608
1609 r = ath9k_hw_process_ini(ah, chan);
1610 if (r)
1611 return r;
1612
1613 /*
1614 * Some AR91xx SoC devices frequently fail to accept TSF writes
1615 * right after the chip reset. When that happens, write a new
1616 * value after the initvals have been applied, with an offset
1617 * based on measured time difference
1618 */
1619 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1620 tsf += 1500;
1621 ath9k_hw_settsf64(ah, tsf);
1622 }
1623
1624 /* Setup MFP options for CCMP */
1625 if (AR_SREV_9280_20_OR_LATER(ah)) {
1626 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1627 * frames when constructing CCMP AAD. */
1628 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1629 0xc7ff);
1630 ah->sw_mgmt_crypto = false;
1631 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1632 /* Disable hardware crypto for management frames */
1633 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1634 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1635 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1636 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1637 ah->sw_mgmt_crypto = true;
1638 } else
1639 ah->sw_mgmt_crypto = true;
1640
1641 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1642 ath9k_hw_set_delta_slope(ah, chan);
1643
1644 ath9k_hw_spur_mitigate_freq(ah, chan);
1645 ah->eep_ops->set_board_values(ah, chan);
1646
1647 ENABLE_REGWRITE_BUFFER(ah);
1648
1649 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1650 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1651 | macStaId1
1652 | AR_STA_ID1_RTS_USE_DEF
1653 | (ah->config.
1654 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1655 | ah->sta_id1_defaults);
1656 ath_hw_setbssidmask(common);
1657 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1658 ath9k_hw_write_associd(ah);
1659 REG_WRITE(ah, AR_ISR, ~0);
1660 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1661
1662 REGWRITE_BUFFER_FLUSH(ah);
1663
1664 ath9k_hw_set_operating_mode(ah, ah->opmode);
1665
1666 r = ath9k_hw_rf_set_freq(ah, chan);
1667 if (r)
1668 return r;
1669
1670 ath9k_hw_set_clockrate(ah);
1671
1672 ENABLE_REGWRITE_BUFFER(ah);
1673
1674 for (i = 0; i < AR_NUM_DCU; i++)
1675 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1676
1677 REGWRITE_BUFFER_FLUSH(ah);
1678
1679 ah->intr_txqs = 0;
1680 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1681 ath9k_hw_resettxqueue(ah, i);
1682
1683 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1684 ath9k_hw_ani_cache_ini_regs(ah);
1685 ath9k_hw_init_qos(ah);
1686
1687 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1688 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1689
1690 ath9k_hw_init_global_settings(ah);
1691
1692 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1693 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1694 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1695 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1696 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1697 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1698 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1699 }
1700
1701 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1702
1703 ath9k_hw_set_dma(ah);
1704
1705 REG_WRITE(ah, AR_OBS, 8);
1706
1707 if (ah->config.rx_intr_mitigation) {
1708 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1709 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1710 }
1711
1712 if (ah->config.tx_intr_mitigation) {
1713 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1714 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1715 }
1716
1717 ath9k_hw_init_bb(ah, chan);
1718
1719 if (caldata) {
1720 caldata->done_txiqcal_once = false;
1721 caldata->done_txclcal_once = false;
1722 caldata->rtt_hist.num_readings = 0;
1723 }
1724 if (!ath9k_hw_init_cal(ah, chan))
1725 return -EIO;
1726
1727 ENABLE_REGWRITE_BUFFER(ah);
1728
1729 ath9k_hw_restore_chainmask(ah);
1730 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1731
1732 REGWRITE_BUFFER_FLUSH(ah);
1733
1734 /*
1735 * For big endian systems turn on swapping for descriptors
1736 */
1737 if (AR_SREV_9100(ah)) {
1738 u32 mask;
1739 mask = REG_READ(ah, AR_CFG);
1740 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1741 ath_dbg(common, ATH_DBG_RESET,
1742 "CFG Byte Swap Set 0x%x\n", mask);
1743 } else {
1744 mask =
1745 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1746 REG_WRITE(ah, AR_CFG, mask);
1747 ath_dbg(common, ATH_DBG_RESET,
1748 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1749 }
1750 } else {
1751 if (common->bus_ops->ath_bus_type == ATH_USB) {
1752 /* Configure AR9271 target WLAN */
1753 if (AR_SREV_9271(ah))
1754 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1755 else
1756 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1757 }
1758 #ifdef __BIG_ENDIAN
1759 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1760 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1761 else
1762 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1763 #endif
1764 }
1765
1766 if (ah->btcoex_hw.enabled)
1767 ath9k_hw_btcoex_enable(ah);
1768
1769 if (AR_SREV_9300_20_OR_LATER(ah)) {
1770 ar9003_hw_bb_watchdog_config(ah);
1771
1772 ar9003_hw_disable_phy_restart(ah);
1773 }
1774
1775 ath9k_hw_apply_gpio_override(ah);
1776
1777 return 0;
1778 }
1779 EXPORT_SYMBOL(ath9k_hw_reset);
1780
1781 /******************************/
1782 /* Power Management (Chipset) */
1783 /******************************/
1784
1785 /*
1786 * Notify Power Mgt is disabled in self-generated frames.
1787 * If requested, force chip to sleep.
1788 */
1789 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1790 {
1791 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1792 if (setChip) {
1793 if (AR_SREV_9462(ah)) {
1794 REG_WRITE(ah, AR_TIMER_MODE,
1795 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1796 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1797 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1798 REG_WRITE(ah, AR_SLP32_INC,
1799 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1800 /* xxx Required for WLAN only case ? */
1801 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1802 udelay(100);
1803 }
1804
1805 /*
1806 * Clear the RTC force wake bit to allow the
1807 * mac to go to sleep.
1808 */
1809 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1810
1811 if (AR_SREV_9462(ah))
1812 udelay(100);
1813
1814 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1815 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1816
1817 /* Shutdown chip. Active low */
1818 if (!AR_SREV_5416(ah) &&
1819 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) {
1820 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1821 udelay(2);
1822 }
1823 }
1824
1825 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1826 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1827 }
1828
1829 /*
1830 * Notify Power Management is enabled in self-generating
1831 * frames. If request, set power mode of chip to
1832 * auto/normal. Duration in units of 128us (1/8 TU).
1833 */
1834 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1835 {
1836 u32 val;
1837
1838 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1839 if (setChip) {
1840 struct ath9k_hw_capabilities *pCap = &ah->caps;
1841
1842 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1843 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1844 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1845 AR_RTC_FORCE_WAKE_ON_INT);
1846 } else {
1847
1848 /* When chip goes into network sleep, it could be waken
1849 * up by MCI_INT interrupt caused by BT's HW messages
1850 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1851 * rate (~100us). This will cause chip to leave and
1852 * re-enter network sleep mode frequently, which in
1853 * consequence will have WLAN MCI HW to generate lots of
1854 * SYS_WAKING and SYS_SLEEPING messages which will make
1855 * BT CPU to busy to process.
1856 */
1857 if (AR_SREV_9462(ah)) {
1858 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
1859 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
1860 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
1861 }
1862 /*
1863 * Clear the RTC force wake bit to allow the
1864 * mac to go to sleep.
1865 */
1866 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1867 AR_RTC_FORCE_WAKE_EN);
1868
1869 if (AR_SREV_9462(ah))
1870 udelay(30);
1871 }
1872 }
1873
1874 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1875 if (AR_SREV_9300_20_OR_LATER(ah))
1876 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1877 }
1878
1879 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1880 {
1881 u32 val;
1882 int i;
1883
1884 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1885 if (AR_SREV_9300_20_OR_LATER(ah)) {
1886 REG_WRITE(ah, AR_WA, ah->WARegVal);
1887 udelay(10);
1888 }
1889
1890 if (setChip) {
1891 if ((REG_READ(ah, AR_RTC_STATUS) &
1892 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1893 if (ath9k_hw_set_reset_reg(ah,
1894 ATH9K_RESET_POWER_ON) != true) {
1895 return false;
1896 }
1897 if (!AR_SREV_9300_20_OR_LATER(ah))
1898 ath9k_hw_init_pll(ah, NULL);
1899 }
1900 if (AR_SREV_9100(ah))
1901 REG_SET_BIT(ah, AR_RTC_RESET,
1902 AR_RTC_RESET_EN);
1903
1904 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1905 AR_RTC_FORCE_WAKE_EN);
1906 udelay(50);
1907
1908 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1909 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1910 if (val == AR_RTC_STATUS_ON)
1911 break;
1912 udelay(50);
1913 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1914 AR_RTC_FORCE_WAKE_EN);
1915 }
1916 if (i == 0) {
1917 ath_err(ath9k_hw_common(ah),
1918 "Failed to wakeup in %uus\n",
1919 POWER_UP_TIME / 20);
1920 return false;
1921 }
1922 }
1923
1924 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1925
1926 return true;
1927 }
1928
1929 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1930 {
1931 struct ath_common *common = ath9k_hw_common(ah);
1932 int status = true, setChip = true;
1933 static const char *modes[] = {
1934 "AWAKE",
1935 "FULL-SLEEP",
1936 "NETWORK SLEEP",
1937 "UNDEFINED"
1938 };
1939
1940 if (ah->power_mode == mode)
1941 return status;
1942
1943 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1944 modes[ah->power_mode], modes[mode]);
1945
1946 switch (mode) {
1947 case ATH9K_PM_AWAKE:
1948 status = ath9k_hw_set_power_awake(ah, setChip);
1949 break;
1950 case ATH9K_PM_FULL_SLEEP:
1951 ath9k_set_power_sleep(ah, setChip);
1952 ah->chip_fullsleep = true;
1953 break;
1954 case ATH9K_PM_NETWORK_SLEEP:
1955 ath9k_set_power_network_sleep(ah, setChip);
1956 break;
1957 default:
1958 ath_err(common, "Unknown power mode %u\n", mode);
1959 return false;
1960 }
1961 ah->power_mode = mode;
1962
1963 /*
1964 * XXX: If this warning never comes up after a while then
1965 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1966 * ath9k_hw_setpower() return type void.
1967 */
1968
1969 if (!(ah->ah_flags & AH_UNPLUGGED))
1970 ATH_DBG_WARN_ON_ONCE(!status);
1971
1972 return status;
1973 }
1974 EXPORT_SYMBOL(ath9k_hw_setpower);
1975
1976 /*******************/
1977 /* Beacon Handling */
1978 /*******************/
1979
1980 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1981 {
1982 int flags = 0;
1983
1984 ENABLE_REGWRITE_BUFFER(ah);
1985
1986 switch (ah->opmode) {
1987 case NL80211_IFTYPE_ADHOC:
1988 case NL80211_IFTYPE_MESH_POINT:
1989 REG_SET_BIT(ah, AR_TXCFG,
1990 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1991 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1992 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1993 flags |= AR_NDP_TIMER_EN;
1994 case NL80211_IFTYPE_AP:
1995 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1996 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1997 TU_TO_USEC(ah->config.dma_beacon_response_time));
1998 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1999 TU_TO_USEC(ah->config.sw_beacon_response_time));
2000 flags |=
2001 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2002 break;
2003 default:
2004 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
2005 "%s: unsupported opmode: %d\n",
2006 __func__, ah->opmode);
2007 return;
2008 break;
2009 }
2010
2011 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2012 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2013 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2014 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2015
2016 REGWRITE_BUFFER_FLUSH(ah);
2017
2018 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2019 }
2020 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2021
2022 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2023 const struct ath9k_beacon_state *bs)
2024 {
2025 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2026 struct ath9k_hw_capabilities *pCap = &ah->caps;
2027 struct ath_common *common = ath9k_hw_common(ah);
2028
2029 ENABLE_REGWRITE_BUFFER(ah);
2030
2031 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2032
2033 REG_WRITE(ah, AR_BEACON_PERIOD,
2034 TU_TO_USEC(bs->bs_intval));
2035 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2036 TU_TO_USEC(bs->bs_intval));
2037
2038 REGWRITE_BUFFER_FLUSH(ah);
2039
2040 REG_RMW_FIELD(ah, AR_RSSI_THR,
2041 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2042
2043 beaconintval = bs->bs_intval;
2044
2045 if (bs->bs_sleepduration > beaconintval)
2046 beaconintval = bs->bs_sleepduration;
2047
2048 dtimperiod = bs->bs_dtimperiod;
2049 if (bs->bs_sleepduration > dtimperiod)
2050 dtimperiod = bs->bs_sleepduration;
2051
2052 if (beaconintval == dtimperiod)
2053 nextTbtt = bs->bs_nextdtim;
2054 else
2055 nextTbtt = bs->bs_nexttbtt;
2056
2057 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2058 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2059 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2060 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2061
2062 ENABLE_REGWRITE_BUFFER(ah);
2063
2064 REG_WRITE(ah, AR_NEXT_DTIM,
2065 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2066 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2067
2068 REG_WRITE(ah, AR_SLEEP1,
2069 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2070 | AR_SLEEP1_ASSUME_DTIM);
2071
2072 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2073 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2074 else
2075 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2076
2077 REG_WRITE(ah, AR_SLEEP2,
2078 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2079
2080 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2081 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2082
2083 REGWRITE_BUFFER_FLUSH(ah);
2084
2085 REG_SET_BIT(ah, AR_TIMER_MODE,
2086 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2087 AR_DTIM_TIMER_EN);
2088
2089 /* TSF Out of Range Threshold */
2090 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2091 }
2092 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2093
2094 /*******************/
2095 /* HW Capabilities */
2096 /*******************/
2097
2098 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2099 {
2100 eeprom_chainmask &= chip_chainmask;
2101 if (eeprom_chainmask)
2102 return eeprom_chainmask;
2103 else
2104 return chip_chainmask;
2105 }
2106
2107 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2108 {
2109 struct ath9k_hw_capabilities *pCap = &ah->caps;
2110 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2111 struct ath_common *common = ath9k_hw_common(ah);
2112 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2113 unsigned int chip_chainmask;
2114
2115 u16 eeval;
2116 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2117
2118 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2119 regulatory->current_rd = eeval;
2120
2121 if (ah->opmode != NL80211_IFTYPE_AP &&
2122 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2123 if (regulatory->current_rd == 0x64 ||
2124 regulatory->current_rd == 0x65)
2125 regulatory->current_rd += 5;
2126 else if (regulatory->current_rd == 0x41)
2127 regulatory->current_rd = 0x43;
2128 ath_dbg(common, ATH_DBG_REGULATORY,
2129 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2130 }
2131
2132 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2133 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2134 ath_err(common,
2135 "no band has been marked as supported in EEPROM\n");
2136 return -EINVAL;
2137 }
2138
2139 if (eeval & AR5416_OPFLAGS_11A)
2140 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2141
2142 if (eeval & AR5416_OPFLAGS_11G)
2143 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2144
2145 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2146 chip_chainmask = 1;
2147 else if (!AR_SREV_9280_20_OR_LATER(ah))
2148 chip_chainmask = 7;
2149 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2150 chip_chainmask = 3;
2151 else
2152 chip_chainmask = 7;
2153
2154 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2155 /*
2156 * For AR9271 we will temporarilly uses the rx chainmax as read from
2157 * the EEPROM.
2158 */
2159 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2160 !(eeval & AR5416_OPFLAGS_11A) &&
2161 !(AR_SREV_9271(ah)))
2162 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2163 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2164 else if (AR_SREV_9100(ah))
2165 pCap->rx_chainmask = 0x7;
2166 else
2167 /* Use rx_chainmask from EEPROM. */
2168 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2169
2170 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2171 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2172 ah->txchainmask = pCap->tx_chainmask;
2173 ah->rxchainmask = pCap->rx_chainmask;
2174
2175 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2176
2177 /* enable key search for every frame in an aggregate */
2178 if (AR_SREV_9300_20_OR_LATER(ah))
2179 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2180
2181 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2182
2183 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2184 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2185 else
2186 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2187
2188 if (AR_SREV_9271(ah))
2189 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2190 else if (AR_DEVID_7010(ah))
2191 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2192 else if (AR_SREV_9300_20_OR_LATER(ah))
2193 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2194 else if (AR_SREV_9287_11_OR_LATER(ah))
2195 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2196 else if (AR_SREV_9285_12_OR_LATER(ah))
2197 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2198 else if (AR_SREV_9280_20_OR_LATER(ah))
2199 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2200 else
2201 pCap->num_gpio_pins = AR_NUM_GPIO;
2202
2203 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2204 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2205 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2206 } else {
2207 pCap->rts_aggr_limit = (8 * 1024);
2208 }
2209
2210 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2211 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2212 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2213 ah->rfkill_gpio =
2214 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2215 ah->rfkill_polarity =
2216 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2217
2218 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2219 }
2220 #endif
2221 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2222 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2223 else
2224 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2225
2226 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2227 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2228 else
2229 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2230
2231 if (common->btcoex_enabled) {
2232 if (AR_SREV_9300_20_OR_LATER(ah)) {
2233 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2234 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2235 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2236 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2237 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2238 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2239 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2240
2241 if (AR_SREV_9285(ah)) {
2242 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2243 btcoex_hw->btpriority_gpio =
2244 ATH_BTPRIORITY_GPIO_9285;
2245 } else {
2246 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2247 }
2248 }
2249 } else {
2250 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2251 }
2252
2253 if (AR_SREV_9300_20_OR_LATER(ah)) {
2254 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2255 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2256 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2257
2258 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2259 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2260 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2261 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2262 pCap->txs_len = sizeof(struct ar9003_txs);
2263 if (!ah->config.paprd_disable &&
2264 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2265 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2266 } else {
2267 pCap->tx_desc_len = sizeof(struct ath_desc);
2268 if (AR_SREV_9280_20(ah))
2269 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2270 }
2271
2272 if (AR_SREV_9300_20_OR_LATER(ah))
2273 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2274
2275 if (AR_SREV_9300_20_OR_LATER(ah))
2276 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2277
2278 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2279 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2280
2281 if (AR_SREV_9285(ah))
2282 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2283 ant_div_ctl1 =
2284 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2285 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2286 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2287 }
2288 if (AR_SREV_9300_20_OR_LATER(ah)) {
2289 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2290 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2291 }
2292
2293
2294 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2295 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2296 /*
2297 * enable the diversity-combining algorithm only when
2298 * both enable_lna_div and enable_fast_div are set
2299 * Table for Diversity
2300 * ant_div_alt_lnaconf bit 0-1
2301 * ant_div_main_lnaconf bit 2-3
2302 * ant_div_alt_gaintb bit 4
2303 * ant_div_main_gaintb bit 5
2304 * enable_ant_div_lnadiv bit 6
2305 * enable_ant_fast_div bit 7
2306 */
2307 if ((ant_div_ctl1 >> 0x6) == 0x3)
2308 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2309 }
2310
2311 if (AR_SREV_9485_10(ah)) {
2312 pCap->pcie_lcr_extsync_en = true;
2313 pCap->pcie_lcr_offset = 0x80;
2314 }
2315
2316 tx_chainmask = pCap->tx_chainmask;
2317 rx_chainmask = pCap->rx_chainmask;
2318 while (tx_chainmask || rx_chainmask) {
2319 if (tx_chainmask & BIT(0))
2320 pCap->max_txchains++;
2321 if (rx_chainmask & BIT(0))
2322 pCap->max_rxchains++;
2323
2324 tx_chainmask >>= 1;
2325 rx_chainmask >>= 1;
2326 }
2327
2328 if (AR_SREV_9300_20_OR_LATER(ah)) {
2329 ah->enabled_cals |= TX_IQ_CAL;
2330 if (!AR_SREV_9330(ah))
2331 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2332 }
2333 if (AR_SREV_9462(ah))
2334 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2335
2336 return 0;
2337 }
2338
2339 /****************************/
2340 /* GPIO / RFKILL / Antennae */
2341 /****************************/
2342
2343 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2344 u32 gpio, u32 type)
2345 {
2346 int addr;
2347 u32 gpio_shift, tmp;
2348
2349 if (gpio > 11)
2350 addr = AR_GPIO_OUTPUT_MUX3;
2351 else if (gpio > 5)
2352 addr = AR_GPIO_OUTPUT_MUX2;
2353 else
2354 addr = AR_GPIO_OUTPUT_MUX1;
2355
2356 gpio_shift = (gpio % 6) * 5;
2357
2358 if (AR_SREV_9280_20_OR_LATER(ah)
2359 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2360 REG_RMW(ah, addr, (type << gpio_shift),
2361 (0x1f << gpio_shift));
2362 } else {
2363 tmp = REG_READ(ah, addr);
2364 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2365 tmp &= ~(0x1f << gpio_shift);
2366 tmp |= (type << gpio_shift);
2367 REG_WRITE(ah, addr, tmp);
2368 }
2369 }
2370
2371 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2372 {
2373 u32 gpio_shift;
2374
2375 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2376
2377 if (AR_DEVID_7010(ah)) {
2378 gpio_shift = gpio;
2379 REG_RMW(ah, AR7010_GPIO_OE,
2380 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2381 (AR7010_GPIO_OE_MASK << gpio_shift));
2382 return;
2383 }
2384
2385 gpio_shift = gpio << 1;
2386 REG_RMW(ah,
2387 AR_GPIO_OE_OUT,
2388 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2389 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2390 }
2391 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2392
2393 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2394 {
2395 #define MS_REG_READ(x, y) \
2396 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2397
2398 if (gpio >= ah->caps.num_gpio_pins)
2399 return 0xffffffff;
2400
2401 if (AR_DEVID_7010(ah)) {
2402 u32 val;
2403 val = REG_READ(ah, AR7010_GPIO_IN);
2404 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2405 } else if (AR_SREV_9300_20_OR_LATER(ah))
2406 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2407 AR_GPIO_BIT(gpio)) != 0;
2408 else if (AR_SREV_9271(ah))
2409 return MS_REG_READ(AR9271, gpio) != 0;
2410 else if (AR_SREV_9287_11_OR_LATER(ah))
2411 return MS_REG_READ(AR9287, gpio) != 0;
2412 else if (AR_SREV_9285_12_OR_LATER(ah))
2413 return MS_REG_READ(AR9285, gpio) != 0;
2414 else if (AR_SREV_9280_20_OR_LATER(ah))
2415 return MS_REG_READ(AR928X, gpio) != 0;
2416 else
2417 return MS_REG_READ(AR, gpio) != 0;
2418 }
2419 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2420
2421 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2422 u32 ah_signal_type)
2423 {
2424 u32 gpio_shift;
2425
2426 if (AR_DEVID_7010(ah)) {
2427 gpio_shift = gpio;
2428 REG_RMW(ah, AR7010_GPIO_OE,
2429 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2430 (AR7010_GPIO_OE_MASK << gpio_shift));
2431 return;
2432 }
2433
2434 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2435 gpio_shift = 2 * gpio;
2436 REG_RMW(ah,
2437 AR_GPIO_OE_OUT,
2438 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2439 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2440 }
2441 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2442
2443 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2444 {
2445 if (AR_DEVID_7010(ah)) {
2446 val = val ? 0 : 1;
2447 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2448 AR_GPIO_BIT(gpio));
2449 return;
2450 }
2451
2452 if (AR_SREV_9271(ah))
2453 val = ~val;
2454
2455 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2456 AR_GPIO_BIT(gpio));
2457 }
2458 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2459
2460 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2461 {
2462 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2463 }
2464 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2465
2466 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2467 {
2468 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2469 }
2470 EXPORT_SYMBOL(ath9k_hw_setantenna);
2471
2472 /*********************/
2473 /* General Operation */
2474 /*********************/
2475
2476 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2477 {
2478 u32 bits = REG_READ(ah, AR_RX_FILTER);
2479 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2480
2481 if (phybits & AR_PHY_ERR_RADAR)
2482 bits |= ATH9K_RX_FILTER_PHYRADAR;
2483 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2484 bits |= ATH9K_RX_FILTER_PHYERR;
2485
2486 return bits;
2487 }
2488 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2489
2490 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2491 {
2492 u32 phybits;
2493
2494 ENABLE_REGWRITE_BUFFER(ah);
2495
2496 if (AR_SREV_9462(ah))
2497 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2498
2499 REG_WRITE(ah, AR_RX_FILTER, bits);
2500
2501 phybits = 0;
2502 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2503 phybits |= AR_PHY_ERR_RADAR;
2504 if (bits & ATH9K_RX_FILTER_PHYERR)
2505 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2506 REG_WRITE(ah, AR_PHY_ERR, phybits);
2507
2508 if (phybits)
2509 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2510 else
2511 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2512
2513 REGWRITE_BUFFER_FLUSH(ah);
2514 }
2515 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2516
2517 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2518 {
2519 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2520 return false;
2521
2522 ath9k_hw_init_pll(ah, NULL);
2523 return true;
2524 }
2525 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2526
2527 bool ath9k_hw_disable(struct ath_hw *ah)
2528 {
2529 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2530 return false;
2531
2532 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2533 return false;
2534
2535 ath9k_hw_init_pll(ah, NULL);
2536 return true;
2537 }
2538 EXPORT_SYMBOL(ath9k_hw_disable);
2539
2540 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2541 {
2542 enum eeprom_param gain_param;
2543
2544 if (IS_CHAN_2GHZ(chan))
2545 gain_param = EEP_ANTENNA_GAIN_2G;
2546 else
2547 gain_param = EEP_ANTENNA_GAIN_5G;
2548
2549 return ah->eep_ops->get_eeprom(ah, gain_param);
2550 }
2551
2552 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2553 {
2554 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2555 struct ieee80211_channel *channel;
2556 int chan_pwr, new_pwr, max_gain;
2557 int ant_gain, ant_reduction = 0;
2558
2559 if (!chan)
2560 return;
2561
2562 channel = chan->chan;
2563 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2564 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2565 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2566
2567 ant_gain = get_antenna_gain(ah, chan);
2568 if (ant_gain > max_gain)
2569 ant_reduction = ant_gain - max_gain;
2570
2571 ah->eep_ops->set_txpower(ah, chan,
2572 ath9k_regd_get_ctl(reg, chan),
2573 ant_reduction, new_pwr, false);
2574 }
2575
2576 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2577 {
2578 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2579 struct ath9k_channel *chan = ah->curchan;
2580 struct ieee80211_channel *channel = chan->chan;
2581
2582 reg->power_limit = min_t(int, limit, MAX_RATE_POWER);
2583 if (test)
2584 channel->max_power = MAX_RATE_POWER / 2;
2585
2586 ath9k_hw_apply_txpower(ah, chan);
2587
2588 if (test)
2589 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2590 }
2591 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2592
2593 void ath9k_hw_setopmode(struct ath_hw *ah)
2594 {
2595 ath9k_hw_set_operating_mode(ah, ah->opmode);
2596 }
2597 EXPORT_SYMBOL(ath9k_hw_setopmode);
2598
2599 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2600 {
2601 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2602 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2603 }
2604 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2605
2606 void ath9k_hw_write_associd(struct ath_hw *ah)
2607 {
2608 struct ath_common *common = ath9k_hw_common(ah);
2609
2610 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2611 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2612 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2613 }
2614 EXPORT_SYMBOL(ath9k_hw_write_associd);
2615
2616 #define ATH9K_MAX_TSF_READ 10
2617
2618 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2619 {
2620 u32 tsf_lower, tsf_upper1, tsf_upper2;
2621 int i;
2622
2623 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2624 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2625 tsf_lower = REG_READ(ah, AR_TSF_L32);
2626 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2627 if (tsf_upper2 == tsf_upper1)
2628 break;
2629 tsf_upper1 = tsf_upper2;
2630 }
2631
2632 WARN_ON( i == ATH9K_MAX_TSF_READ );
2633
2634 return (((u64)tsf_upper1 << 32) | tsf_lower);
2635 }
2636 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2637
2638 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2639 {
2640 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2641 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2642 }
2643 EXPORT_SYMBOL(ath9k_hw_settsf64);
2644
2645 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2646 {
2647 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2648 AH_TSF_WRITE_TIMEOUT))
2649 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2650 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2651
2652 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2653 }
2654 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2655
2656 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2657 {
2658 if (setting)
2659 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2660 else
2661 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2662 }
2663 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2664
2665 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2666 {
2667 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2668 u32 macmode;
2669
2670 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2671 macmode = AR_2040_JOINED_RX_CLEAR;
2672 else
2673 macmode = 0;
2674
2675 REG_WRITE(ah, AR_2040_MODE, macmode);
2676 }
2677
2678 /* HW Generic timers configuration */
2679
2680 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2681 {
2682 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2683 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2684 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2685 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2686 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2687 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2688 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2689 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2690 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2691 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2692 AR_NDP2_TIMER_MODE, 0x0002},
2693 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2694 AR_NDP2_TIMER_MODE, 0x0004},
2695 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2696 AR_NDP2_TIMER_MODE, 0x0008},
2697 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2698 AR_NDP2_TIMER_MODE, 0x0010},
2699 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2700 AR_NDP2_TIMER_MODE, 0x0020},
2701 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2702 AR_NDP2_TIMER_MODE, 0x0040},
2703 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2704 AR_NDP2_TIMER_MODE, 0x0080}
2705 };
2706
2707 /* HW generic timer primitives */
2708
2709 /* compute and clear index of rightmost 1 */
2710 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2711 {
2712 u32 b;
2713
2714 b = *mask;
2715 b &= (0-b);
2716 *mask &= ~b;
2717 b *= debruijn32;
2718 b >>= 27;
2719
2720 return timer_table->gen_timer_index[b];
2721 }
2722
2723 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2724 {
2725 return REG_READ(ah, AR_TSF_L32);
2726 }
2727 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2728
2729 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2730 void (*trigger)(void *),
2731 void (*overflow)(void *),
2732 void *arg,
2733 u8 timer_index)
2734 {
2735 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2736 struct ath_gen_timer *timer;
2737
2738 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2739
2740 if (timer == NULL) {
2741 ath_err(ath9k_hw_common(ah),
2742 "Failed to allocate memory for hw timer[%d]\n",
2743 timer_index);
2744 return NULL;
2745 }
2746
2747 /* allocate a hardware generic timer slot */
2748 timer_table->timers[timer_index] = timer;
2749 timer->index = timer_index;
2750 timer->trigger = trigger;
2751 timer->overflow = overflow;
2752 timer->arg = arg;
2753
2754 return timer;
2755 }
2756 EXPORT_SYMBOL(ath_gen_timer_alloc);
2757
2758 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2759 struct ath_gen_timer *timer,
2760 u32 trig_timeout,
2761 u32 timer_period)
2762 {
2763 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2764 u32 tsf, timer_next;
2765
2766 BUG_ON(!timer_period);
2767
2768 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2769
2770 tsf = ath9k_hw_gettsf32(ah);
2771
2772 timer_next = tsf + trig_timeout;
2773
2774 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2775 "current tsf %x period %x timer_next %x\n",
2776 tsf, timer_period, timer_next);
2777
2778 /*
2779 * Program generic timer registers
2780 */
2781 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2782 timer_next);
2783 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2784 timer_period);
2785 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2786 gen_tmr_configuration[timer->index].mode_mask);
2787
2788 if (AR_SREV_9462(ah)) {
2789 /*
2790 * Starting from AR9462, each generic timer can select which tsf
2791 * to use. But we still follow the old rule, 0 - 7 use tsf and
2792 * 8 - 15 use tsf2.
2793 */
2794 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2795 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2796 (1 << timer->index));
2797 else
2798 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2799 (1 << timer->index));
2800 }
2801
2802 /* Enable both trigger and thresh interrupt masks */
2803 REG_SET_BIT(ah, AR_IMR_S5,
2804 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2805 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2806 }
2807 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2808
2809 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2810 {
2811 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2812
2813 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2814 (timer->index >= ATH_MAX_GEN_TIMER)) {
2815 return;
2816 }
2817
2818 /* Clear generic timer enable bits. */
2819 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2820 gen_tmr_configuration[timer->index].mode_mask);
2821
2822 /* Disable both trigger and thresh interrupt masks */
2823 REG_CLR_BIT(ah, AR_IMR_S5,
2824 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2825 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2826
2827 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2828 }
2829 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2830
2831 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2832 {
2833 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2834
2835 /* free the hardware generic timer slot */
2836 timer_table->timers[timer->index] = NULL;
2837 kfree(timer);
2838 }
2839 EXPORT_SYMBOL(ath_gen_timer_free);
2840
2841 /*
2842 * Generic Timer Interrupts handling
2843 */
2844 void ath_gen_timer_isr(struct ath_hw *ah)
2845 {
2846 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2847 struct ath_gen_timer *timer;
2848 struct ath_common *common = ath9k_hw_common(ah);
2849 u32 trigger_mask, thresh_mask, index;
2850
2851 /* get hardware generic timer interrupt status */
2852 trigger_mask = ah->intr_gen_timer_trigger;
2853 thresh_mask = ah->intr_gen_timer_thresh;
2854 trigger_mask &= timer_table->timer_mask.val;
2855 thresh_mask &= timer_table->timer_mask.val;
2856
2857 trigger_mask &= ~thresh_mask;
2858
2859 while (thresh_mask) {
2860 index = rightmost_index(timer_table, &thresh_mask);
2861 timer = timer_table->timers[index];
2862 BUG_ON(!timer);
2863 ath_dbg(common, ATH_DBG_HWTIMER,
2864 "TSF overflow for Gen timer %d\n", index);
2865 timer->overflow(timer->arg);
2866 }
2867
2868 while (trigger_mask) {
2869 index = rightmost_index(timer_table, &trigger_mask);
2870 timer = timer_table->timers[index];
2871 BUG_ON(!timer);
2872 ath_dbg(common, ATH_DBG_HWTIMER,
2873 "Gen timer[%d] trigger\n", index);
2874 timer->trigger(timer->arg);
2875 }
2876 }
2877 EXPORT_SYMBOL(ath_gen_timer_isr);
2878
2879 /********/
2880 /* HTC */
2881 /********/
2882
2883 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2884 {
2885 ah->htc_reset_init = true;
2886 }
2887 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2888
2889 static struct {
2890 u32 version;
2891 const char * name;
2892 } ath_mac_bb_names[] = {
2893 /* Devices with external radios */
2894 { AR_SREV_VERSION_5416_PCI, "5416" },
2895 { AR_SREV_VERSION_5416_PCIE, "5418" },
2896 { AR_SREV_VERSION_9100, "9100" },
2897 { AR_SREV_VERSION_9160, "9160" },
2898 /* Single-chip solutions */
2899 { AR_SREV_VERSION_9280, "9280" },
2900 { AR_SREV_VERSION_9285, "9285" },
2901 { AR_SREV_VERSION_9287, "9287" },
2902 { AR_SREV_VERSION_9271, "9271" },
2903 { AR_SREV_VERSION_9300, "9300" },
2904 { AR_SREV_VERSION_9330, "9330" },
2905 { AR_SREV_VERSION_9340, "9340" },
2906 { AR_SREV_VERSION_9485, "9485" },
2907 { AR_SREV_VERSION_9462, "9462" },
2908 };
2909
2910 /* For devices with external radios */
2911 static struct {
2912 u16 version;
2913 const char * name;
2914 } ath_rf_names[] = {
2915 { 0, "5133" },
2916 { AR_RAD5133_SREV_MAJOR, "5133" },
2917 { AR_RAD5122_SREV_MAJOR, "5122" },
2918 { AR_RAD2133_SREV_MAJOR, "2133" },
2919 { AR_RAD2122_SREV_MAJOR, "2122" }
2920 };
2921
2922 /*
2923 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2924 */
2925 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2926 {
2927 int i;
2928
2929 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2930 if (ath_mac_bb_names[i].version == mac_bb_version) {
2931 return ath_mac_bb_names[i].name;
2932 }
2933 }
2934
2935 return "????";
2936 }
2937
2938 /*
2939 * Return the RF name. "????" is returned if the RF is unknown.
2940 * Used for devices with external radios.
2941 */
2942 static const char *ath9k_hw_rf_name(u16 rf_version)
2943 {
2944 int i;
2945
2946 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2947 if (ath_rf_names[i].version == rf_version) {
2948 return ath_rf_names[i].name;
2949 }
2950 }
2951
2952 return "????";
2953 }
2954
2955 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2956 {
2957 int used;
2958
2959 /* chipsets >= AR9280 are single-chip */
2960 if (AR_SREV_9280_20_OR_LATER(ah)) {
2961 used = snprintf(hw_name, len,
2962 "Atheros AR%s Rev:%x",
2963 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2964 ah->hw_version.macRev);
2965 }
2966 else {
2967 used = snprintf(hw_name, len,
2968 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2969 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2970 ah->hw_version.macRev,
2971 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2972 AR_RADIO_SREV_MAJOR)),
2973 ah->hw_version.phyRev);
2974 }
2975
2976 hw_name[used] = '\0';
2977 }
2978 EXPORT_SYMBOL(ath9k_hw_name);
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