2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
23 #include <linux/firmware.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
47 #define AR9300_DEVID_AR9340 0x0031
48 #define AR9300_DEVID_AR9485_PCIE 0x0032
49 #define AR9300_DEVID_AR9580 0x0033
50 #define AR9300_DEVID_AR9462 0x0034
51 #define AR9300_DEVID_AR9330 0x0035
52 #define AR9300_DEVID_QCA955X 0x0038
53 #define AR9485_DEVID_AR1111 0x0037
54 #define AR9300_DEVID_AR9565 0x0036
56 #define AR5416_AR9100_DEVID 0x000b
58 #define AR_SUBVENDOR_ID_NOG 0x0e11
59 #define AR_SUBVENDOR_ID_NEW_A 0x7065
60 #define AR5416_MAGIC 0x19641014
62 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
63 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
64 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
66 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
68 #define ATH_DEFAULT_NOISE_FLOOR -95
70 #define ATH9K_RSSI_BAD -128
72 #define ATH9K_NUM_CHANNELS 38
74 /* Register read/write primitives */
75 #define REG_WRITE(_ah, _reg, _val) \
76 (_ah)->reg_ops.write((_ah), (_val), (_reg))
78 #define REG_READ(_ah, _reg) \
79 (_ah)->reg_ops.read((_ah), (_reg))
81 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
82 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
84 #define REG_RMW(_ah, _reg, _set, _clr) \
85 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
87 #define ENABLE_REGWRITE_BUFFER(_ah) \
89 if ((_ah)->reg_ops.enable_write_buffer) \
90 (_ah)->reg_ops.enable_write_buffer((_ah)); \
93 #define REGWRITE_BUFFER_FLUSH(_ah) \
95 if ((_ah)->reg_ops.write_flush) \
96 (_ah)->reg_ops.write_flush((_ah)); \
99 #define PR_EEP(_s, _val) \
101 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
105 #define SM(_v, _f) (((_v) << _f##_S) & _f)
106 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
107 #define REG_RMW_FIELD(_a, _r, _f, _v) \
108 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
109 #define REG_READ_FIELD(_a, _r, _f) \
110 (((REG_READ(_a, _r) & _f) >> _f##_S))
111 #define REG_SET_BIT(_a, _r, _f) \
112 REG_RMW(_a, _r, (_f), 0)
113 #define REG_CLR_BIT(_a, _r, _f) \
114 REG_RMW(_a, _r, 0, (_f))
116 #define DO_DELAY(x) do { \
117 if (((++(x) % 64) == 0) && \
118 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
123 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
124 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
126 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
128 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
129 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
130 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
132 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
133 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
134 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
137 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
138 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
139 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
140 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
141 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
142 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
144 #define AR_GPIOD_MASK 0x00001FFF
145 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
147 #define BASE_ACTIVATE_DELAY 100
148 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
149 #define COEF_SCALE_S 24
150 #define HT40_CHANNEL_CENTER_SHIFT 10
152 #define ATH9K_ANTENNA0_CHAINMASK 0x1
153 #define ATH9K_ANTENNA1_CHAINMASK 0x2
155 #define ATH9K_NUM_DMA_DEBUG_REGS 8
156 #define ATH9K_NUM_QUEUES 10
158 #define MAX_RATE_POWER 63
159 #define AH_WAIT_TIMEOUT 100000 /* (us) */
160 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
161 #define AH_TIME_QUANTUM 10
162 #define AR_KEYTABLE_SIZE 128
163 #define POWER_UP_TIME 10000
164 #define SPUR_RSSI_THRESH 40
165 #define UPPER_5G_SUB_BAND_START 5700
166 #define MID_5G_SUB_BAND_START 5400
168 #define CAB_TIMEOUT_VAL 10
169 #define BEACON_TIMEOUT_VAL 10
170 #define MIN_BEACON_TIMEOUT_VAL 1
173 #define INIT_CONFIG_STATUS 0x00000000
174 #define INIT_RSSI_THR 0x00000700
175 #define INIT_BCON_CNTRL_REG 0x00000000
177 #define TU_TO_USEC(_tu) ((_tu) << 10)
179 #define ATH9K_HW_RX_HP_QDEPTH 16
180 #define ATH9K_HW_RX_LP_QDEPTH 128
182 #define PAPRD_GAIN_TABLE_ENTRIES 32
183 #define PAPRD_TABLE_SZ 24
184 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
190 /* Keep Alive Frame */
191 #define KAL_FRAME_LEN 28
192 #define KAL_FRAME_TYPE 0x2 /* data frame */
193 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
194 #define KAL_DURATION_ID 0x3d
195 #define KAL_NUM_DATA_WORDS 6
196 #define KAL_NUM_DESC_WORDS 12
197 #define KAL_ANTENNA_MODE 1
199 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
200 #define KAL_TIMEOUT 900
202 #define MAX_PATTERN_SIZE 256
203 #define MAX_PATTERN_MASK_SIZE 32
204 #define MAX_NUM_PATTERN 8
205 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
206 deauthenticate packets */
209 * WoW trigger mapping to hardware code
212 #define AH_WOW_USER_PATTERN_EN BIT(0)
213 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
214 #define AH_WOW_LINK_CHANGE BIT(2)
215 #define AH_WOW_BEACON_MISS BIT(3)
217 enum ath_hw_txq_subtype
{
224 enum ath_ini_subsys
{
232 ATH9K_HW_CAP_HT
= BIT(0),
233 ATH9K_HW_CAP_RFSILENT
= BIT(1),
234 ATH9K_HW_CAP_AUTOSLEEP
= BIT(2),
235 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(3),
236 ATH9K_HW_CAP_EDMA
= BIT(4),
237 ATH9K_HW_CAP_RAC_SUPPORTED
= BIT(5),
238 ATH9K_HW_CAP_LDPC
= BIT(6),
239 ATH9K_HW_CAP_FASTCLOCK
= BIT(7),
240 ATH9K_HW_CAP_SGI_20
= BIT(8),
241 ATH9K_HW_CAP_ANT_DIV_COMB
= BIT(10),
242 ATH9K_HW_CAP_2GHZ
= BIT(11),
243 ATH9K_HW_CAP_5GHZ
= BIT(12),
244 ATH9K_HW_CAP_APM
= BIT(13),
245 ATH9K_HW_CAP_RTT
= BIT(14),
246 ATH9K_HW_CAP_MCI
= BIT(15),
247 ATH9K_HW_CAP_DFS
= BIT(16),
248 ATH9K_HW_WOW_DEVICE_CAPABLE
= BIT(17),
249 ATH9K_HW_WOW_PATTERN_MATCH_EXACT
= BIT(18),
250 ATH9K_HW_WOW_PATTERN_MATCH_DWORD
= BIT(19),
251 ATH9K_HW_CAP_PAPRD
= BIT(20),
255 * WoW device capabilities
256 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
257 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
258 * an exact user defined pattern or de-authentication/disassoc pattern.
259 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
260 * bytes of the pattern for user defined pattern, de-authentication and
261 * disassociation patterns for all types of possible frames recieved
265 struct ath9k_hw_capabilities
{
266 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
280 struct ath9k_ops_config
{
281 int dma_beacon_response_time
;
282 int sw_beacon_response_time
;
283 int additional_swba_backoff
;
285 u32 cwm_ignore_extcca
;
286 bool pcieSerDesWrite
;
296 int serialize_regmode
;
297 bool rx_intr_mitigation
;
298 bool tx_intr_mitigation
;
299 #define SPUR_DISABLE 0
300 #define SPUR_ENABLE_IOCTL 1
301 #define SPUR_ENABLE_EEPROM 2
302 #define AR_SPUR_5413_1 1640
303 #define AR_SPUR_5413_2 1200
304 #define AR_NO_SPUR 0x8000
305 #define AR_BASE_FREQ_2GHZ 2300
306 #define AR_BASE_FREQ_5GHZ 4900
307 #define AR_SPUR_FEEQ_BOUND_HT40 19
308 #define AR_SPUR_FEEQ_BOUND_HT20 10
310 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
312 u16 ani_poll_interval
; /* ANI poll interval in ms */
316 ATH9K_INT_RX
= 0x00000001,
317 ATH9K_INT_RXDESC
= 0x00000002,
318 ATH9K_INT_RXHP
= 0x00000001,
319 ATH9K_INT_RXLP
= 0x00000002,
320 ATH9K_INT_RXNOFRM
= 0x00000008,
321 ATH9K_INT_RXEOL
= 0x00000010,
322 ATH9K_INT_RXORN
= 0x00000020,
323 ATH9K_INT_TX
= 0x00000040,
324 ATH9K_INT_TXDESC
= 0x00000080,
325 ATH9K_INT_TIM_TIMER
= 0x00000100,
326 ATH9K_INT_MCI
= 0x00000200,
327 ATH9K_INT_BB_WATCHDOG
= 0x00000400,
328 ATH9K_INT_TXURN
= 0x00000800,
329 ATH9K_INT_MIB
= 0x00001000,
330 ATH9K_INT_RXPHY
= 0x00004000,
331 ATH9K_INT_RXKCM
= 0x00008000,
332 ATH9K_INT_SWBA
= 0x00010000,
333 ATH9K_INT_BMISS
= 0x00040000,
334 ATH9K_INT_BNR
= 0x00100000,
335 ATH9K_INT_TIM
= 0x00200000,
336 ATH9K_INT_DTIM
= 0x00400000,
337 ATH9K_INT_DTIMSYNC
= 0x00800000,
338 ATH9K_INT_GPIO
= 0x01000000,
339 ATH9K_INT_CABEND
= 0x02000000,
340 ATH9K_INT_TSFOOR
= 0x04000000,
341 ATH9K_INT_GENTIMER
= 0x08000000,
342 ATH9K_INT_CST
= 0x10000000,
343 ATH9K_INT_GTT
= 0x20000000,
344 ATH9K_INT_FATAL
= 0x40000000,
345 ATH9K_INT_GLOBAL
= 0x80000000,
346 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
351 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
363 ATH9K_INT_NOCARD
= 0xffffffff
366 #define CHANNEL_CCK 0x00020
367 #define CHANNEL_OFDM 0x00040
368 #define CHANNEL_2GHZ 0x00080
369 #define CHANNEL_5GHZ 0x00100
370 #define CHANNEL_PASSIVE 0x00200
371 #define CHANNEL_DYN 0x00400
372 #define CHANNEL_HALF 0x04000
373 #define CHANNEL_QUARTER 0x08000
374 #define CHANNEL_HT20 0x10000
375 #define CHANNEL_HT40PLUS 0x20000
376 #define CHANNEL_HT40MINUS 0x40000
378 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
379 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
380 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
381 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
382 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
383 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
384 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
385 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
386 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
387 #define CHANNEL_ALL \
396 #define MAX_RTT_TABLE_ENTRY 6
397 #define MAX_IQCAL_MEASUREMENT 8
398 #define MAX_CL_TAB_ENTRY 16
399 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
401 struct ath9k_hw_cal_data
{
409 bool paprd_packet_sent
;
412 bool nfcal_interference
;
413 bool done_txiqcal_once
;
414 bool done_txclcal_once
;
415 u16 small_signal_gain
[AR9300_MAX_CHAINS
];
416 u32 pa_table
[AR9300_MAX_CHAINS
][PAPRD_TABLE_SZ
];
417 u32 num_measures
[AR9300_MAX_CHAINS
];
418 int tx_corr_coeff
[MAX_IQCAL_MEASUREMENT
][AR9300_MAX_CHAINS
];
419 u32 tx_clcal
[AR9300_MAX_CHAINS
][MAX_CL_TAB_ENTRY
];
420 u32 rtt_table
[AR9300_MAX_CHAINS
][MAX_RTT_TABLE_ENTRY
];
421 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
424 struct ath9k_channel
{
425 struct ieee80211_channel
*chan
;
426 struct ar5416AniState ani
;
433 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
434 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
435 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
436 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
437 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
438 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
439 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
440 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
441 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
442 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
443 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
444 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
446 /* These macros check chanmode and not channelFlags */
447 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
448 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
449 ((_c)->chanmode == CHANNEL_G_HT20))
450 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
451 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
452 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
453 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
454 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
456 enum ath9k_power_mode
{
459 ATH9K_PM_NETWORK_SLEEP
,
464 SER_REG_MODE_OFF
= 0,
466 SER_REG_MODE_AUTO
= 2,
469 enum ath9k_rx_qtype
{
475 struct ath9k_beacon_state
{
479 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
482 u16 bs_cfpmaxduration
;
485 u16 bs_bmissthreshold
;
486 u32 bs_sleepduration
;
487 u32 bs_tsfoor_threshold
;
490 struct chan_centers
{
497 ATH9K_RESET_POWER_ON
,
502 struct ath9k_hw_version
{
511 enum ath_usb_dev usbdev
;
514 /* Generic TSF timer definitions */
516 #define ATH_MAX_GEN_TIMER 16
518 #define AR_GENTMR_BIT(_index) (1 << (_index))
521 * Using de Bruijin sequence to look up 1's index in a 32 bit number
522 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
524 #define debruijn32 0x077CB531U
526 struct ath_gen_timer_configuration
{
533 struct ath_gen_timer
{
534 void (*trigger
)(void *arg
);
535 void (*overflow
)(void *arg
);
540 struct ath_gen_timer_table
{
541 u32 gen_timer_index
[32];
542 struct ath_gen_timer
*timers
[ATH_MAX_GEN_TIMER
];
544 unsigned long timer_bits
;
549 struct ath_hw_antcomb_conf
{
560 * struct ath_hw_radar_conf - radar detection initialization parameters
562 * @pulse_inband: threshold for checking the ratio of in-band power
563 * to total power for short radar pulses (half dB steps)
564 * @pulse_inband_step: threshold for checking an in-band power to total
565 * power ratio increase for short radar pulses (half dB steps)
566 * @pulse_height: threshold for detecting the beginning of a short
567 * radar pulse (dB step)
568 * @pulse_rssi: threshold for detecting if a short radar pulse is
570 * @pulse_maxlen: maximum pulse length (0.8 us steps)
572 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
573 * @radar_inband: threshold for checking the ratio of in-band power
574 * to total power for long radar pulses (half dB steps)
575 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
577 * @ext_channel: enable extension channel radar detection
579 struct ath_hw_radar_conf
{
580 unsigned int pulse_inband
;
581 unsigned int pulse_inband_step
;
582 unsigned int pulse_height
;
583 unsigned int pulse_rssi
;
584 unsigned int pulse_maxlen
;
586 unsigned int radar_rssi
;
587 unsigned int radar_inband
;
594 * struct ath_hw_private_ops - callbacks used internally by hardware code
596 * This structure contains private callbacks designed to only be used internally
597 * by the hardware core.
599 * @init_cal_settings: setup types of calibrations supported
600 * @init_cal: starts actual calibration
602 * @init_mode_gain_regs: Initialize TX/RX gain registers
604 * @rf_set_freq: change frequency
605 * @spur_mitigate_freq: spur mitigation
607 * @compute_pll_control: compute the PLL control value to use for
608 * AR_RTC_PLL_CONTROL for a given channel
609 * @setup_calibration: set up calibration
610 * @iscal_supported: used to query if a type of calibration is supported
612 * @ani_cache_ini_regs: cache the values for ANI from the initial
613 * register settings through the register initialization.
615 struct ath_hw_private_ops
{
616 /* Calibration ops */
617 void (*init_cal_settings
)(struct ath_hw
*ah
);
618 bool (*init_cal
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
620 void (*init_mode_gain_regs
)(struct ath_hw
*ah
);
621 void (*setup_calibration
)(struct ath_hw
*ah
,
622 struct ath9k_cal_list
*currCal
);
625 int (*rf_set_freq
)(struct ath_hw
*ah
,
626 struct ath9k_channel
*chan
);
627 void (*spur_mitigate_freq
)(struct ath_hw
*ah
,
628 struct ath9k_channel
*chan
);
629 bool (*set_rf_regs
)(struct ath_hw
*ah
,
630 struct ath9k_channel
*chan
,
632 void (*set_channel_regs
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
633 void (*init_bb
)(struct ath_hw
*ah
,
634 struct ath9k_channel
*chan
);
635 int (*process_ini
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
636 void (*olc_init
)(struct ath_hw
*ah
);
637 void (*set_rfmode
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
638 void (*mark_phy_inactive
)(struct ath_hw
*ah
);
639 void (*set_delta_slope
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
640 bool (*rfbus_req
)(struct ath_hw
*ah
);
641 void (*rfbus_done
)(struct ath_hw
*ah
);
642 void (*restore_chainmask
)(struct ath_hw
*ah
);
643 u32 (*compute_pll_control
)(struct ath_hw
*ah
,
644 struct ath9k_channel
*chan
);
645 bool (*ani_control
)(struct ath_hw
*ah
, enum ath9k_ani_cmd cmd
,
647 void (*do_getnf
)(struct ath_hw
*ah
, int16_t nfarray
[NUM_NF_READINGS
]);
648 void (*set_radar_params
)(struct ath_hw
*ah
,
649 struct ath_hw_radar_conf
*conf
);
650 int (*fast_chan_change
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
654 void (*ani_cache_ini_regs
)(struct ath_hw
*ah
);
658 * struct ath_spec_scan - parameters for Atheros spectral scan
660 * @enabled: enable/disable spectral scan
661 * @short_repeat: controls whether the chip is in spectral scan mode
662 * for 4 usec (enabled) or 204 usec (disabled)
663 * @count: number of scan results requested. There are special meanings
664 * in some chip revisions:
665 * AR92xx: highest bit set (>=128) for endless mode
666 * (spectral scan won't stopped until explicitly disabled)
667 * AR9300 and newer: 0 for endless mode
668 * @endless: true if endless mode is intended. Otherwise, count value is
669 * corrected to the next possible value.
670 * @period: time duration between successive spectral scan entry points
671 * (period*256*Tclk). Tclk = ath_common->clockrate
672 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
674 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
675 * Typically it's 44MHz in 2/5GHz on later chips, but there's
676 * a "fast clock" check for this in 5GHz.
679 struct ath_spec_scan
{
689 * struct ath_hw_ops - callbacks used by hardware code and driver code
691 * This structure contains callbacks designed to to be used internally by
692 * hardware code and also by the lower level driver.
694 * @config_pci_powersave:
695 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
697 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
698 * @spectral_scan_trigger: trigger a spectral scan run
699 * @spectral_scan_wait: wait for a spectral scan run to finish
702 void (*config_pci_powersave
)(struct ath_hw
*ah
,
704 void (*rx_enable
)(struct ath_hw
*ah
);
705 void (*set_desc_link
)(void *ds
, u32 link
);
706 bool (*calibrate
)(struct ath_hw
*ah
,
707 struct ath9k_channel
*chan
,
710 bool (*get_isr
)(struct ath_hw
*ah
, enum ath9k_int
*masked
);
711 void (*set_txdesc
)(struct ath_hw
*ah
, void *ds
,
712 struct ath_tx_info
*i
);
713 int (*proc_txdesc
)(struct ath_hw
*ah
, void *ds
,
714 struct ath_tx_status
*ts
);
715 void (*antdiv_comb_conf_get
)(struct ath_hw
*ah
,
716 struct ath_hw_antcomb_conf
*antconf
);
717 void (*antdiv_comb_conf_set
)(struct ath_hw
*ah
,
718 struct ath_hw_antcomb_conf
*antconf
);
719 void (*antctrl_shared_chain_lnadiv
)(struct ath_hw
*hw
, bool enable
);
720 void (*spectral_scan_config
)(struct ath_hw
*ah
,
721 struct ath_spec_scan
*param
);
722 void (*spectral_scan_trigger
)(struct ath_hw
*ah
);
723 void (*spectral_scan_wait
)(struct ath_hw
*ah
);
726 struct ath_nf_limits
{
734 TX_IQ_ON_AGC_CAL
= BIT(1),
739 #define AH_USE_EEPROM 0x1
740 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
741 #define AH_FASTCC 0x4
744 struct ath_ops reg_ops
;
747 struct ieee80211_hw
*hw
;
748 struct ath_common common
;
749 struct ath9k_hw_version hw_version
;
750 struct ath9k_ops_config config
;
751 struct ath9k_hw_capabilities caps
;
752 struct ath9k_channel channels
[ATH9K_NUM_CHANNELS
];
753 struct ath9k_channel
*curchan
;
756 struct ar5416_eeprom_def def
;
757 struct ar5416_eeprom_4k map4k
;
758 struct ar9287_eeprom map9287
;
759 struct ar9300_eeprom ar9300_eep
;
761 const struct eeprom_ops
*eep_ops
;
767 bool need_an_top2_fixup
;
768 bool shared_chain_lnadiv
;
772 struct ath_nf_limits nf_2g
;
773 struct ath_nf_limits nf_5g
;
782 enum nl80211_iftype opmode
;
783 enum ath9k_power_mode power_mode
;
786 struct ath9k_hw_cal_data
*caldata
;
787 struct ath9k_pacal_info pacal_info
;
788 struct ar5416Stats stats
;
789 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
791 enum ath9k_int imask
;
793 u32 txok_interrupt_mask
;
794 u32 txerr_interrupt_mask
;
795 u32 txdesc_interrupt_mask
;
796 u32 txeol_interrupt_mask
;
797 u32 txurn_interrupt_mask
;
798 atomic_t intr_ref_cnt
;
805 struct ath9k_cal_list iq_caldata
;
806 struct ath9k_cal_list adcgain_caldata
;
807 struct ath9k_cal_list adcdc_caldata
;
808 struct ath9k_cal_list
*cal_list
;
809 struct ath9k_cal_list
*cal_list_last
;
810 struct ath9k_cal_list
*cal_list_curr
;
811 #define totalPowerMeasI meas0.unsign
812 #define totalPowerMeasQ meas1.unsign
813 #define totalIqCorrMeas meas2.sign
814 #define totalAdcIOddPhase meas0.unsign
815 #define totalAdcIEvenPhase meas1.unsign
816 #define totalAdcQOddPhase meas2.unsign
817 #define totalAdcQEvenPhase meas3.unsign
818 #define totalAdcDcOffsetIOddPhase meas0.sign
819 #define totalAdcDcOffsetIEvenPhase meas1.sign
820 #define totalAdcDcOffsetQOddPhase meas2.sign
821 #define totalAdcDcOffsetQEvenPhase meas3.sign
823 u32 unsign
[AR5416_MAX_CHAINS
];
824 int32_t sign
[AR5416_MAX_CHAINS
];
827 u32 unsign
[AR5416_MAX_CHAINS
];
828 int32_t sign
[AR5416_MAX_CHAINS
];
831 u32 unsign
[AR5416_MAX_CHAINS
];
832 int32_t sign
[AR5416_MAX_CHAINS
];
835 u32 unsign
[AR5416_MAX_CHAINS
];
836 int32_t sign
[AR5416_MAX_CHAINS
];
841 u32 sta_id1_defaults
;
844 /* Private to hardware code */
845 struct ath_hw_private_ops private_ops
;
846 /* Accessed by the lower level driver */
847 struct ath_hw_ops ops
;
849 /* Used to program the radio on non single-chip devices */
850 u32
*analogBank0Data
;
851 u32
*analogBank1Data
;
852 u32
*analogBank2Data
;
853 u32
*analogBank3Data
;
854 u32
*analogBank6Data
;
855 u32
*analogBank6TPCData
;
856 u32
*analogBank7Data
;
866 enum ath9k_ani_cmd ani_function
;
869 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
870 struct ath_btcoex_hw btcoex_hw
;
877 struct ath_hw_radar_conf radar_conf
;
879 u32 originalGain
[22];
886 struct ar5416IniArray iniModes
;
887 struct ar5416IniArray iniCommon
;
888 struct ar5416IniArray iniBank0
;
889 struct ar5416IniArray iniBB_RfGain
;
890 struct ar5416IniArray iniBank1
;
891 struct ar5416IniArray iniBank2
;
892 struct ar5416IniArray iniBank3
;
893 struct ar5416IniArray iniBank6
;
894 struct ar5416IniArray iniBank6TPC
;
895 struct ar5416IniArray iniBank7
;
896 struct ar5416IniArray iniAddac
;
897 struct ar5416IniArray iniPcieSerdes
;
898 #ifdef CONFIG_PM_SLEEP
899 struct ar5416IniArray iniPcieSerdesWow
;
901 struct ar5416IniArray iniPcieSerdesLowPower
;
902 struct ar5416IniArray iniModesFastClock
;
903 struct ar5416IniArray iniAdditional
;
904 struct ar5416IniArray iniModesRxGain
;
905 struct ar5416IniArray ini_modes_rx_gain_bounds
;
906 struct ar5416IniArray iniModesTxGain
;
907 struct ar5416IniArray iniCckfirNormal
;
908 struct ar5416IniArray iniCckfirJapan2484
;
909 struct ar5416IniArray iniModes_9271_ANI_reg
;
910 struct ar5416IniArray ini_radio_post_sys2ant
;
912 struct ar5416IniArray iniMac
[ATH_INI_NUM_SPLIT
];
913 struct ar5416IniArray iniBB
[ATH_INI_NUM_SPLIT
];
914 struct ar5416IniArray iniRadio
[ATH_INI_NUM_SPLIT
];
915 struct ar5416IniArray iniSOC
[ATH_INI_NUM_SPLIT
];
917 u32 intr_gen_timer_trigger
;
918 u32 intr_gen_timer_thresh
;
919 struct ath_gen_timer_table hw_gen_timers
;
921 struct ar9003_txs
*ts_ring
;
927 u32 bb_watchdog_last_status
;
928 u32 bb_watchdog_timeout_ms
; /* in ms, 0 to disable */
929 u8 bb_hang_rx_ofdm
; /* true if bb hang due to rx_ofdm */
931 unsigned int paprd_target_power
;
932 unsigned int paprd_training_power
;
933 unsigned int paprd_ratemask
;
934 unsigned int paprd_ratemask_ht40
;
935 bool paprd_table_write_done
;
936 u32 paprd_gain_table_entries
[PAPRD_GAIN_TABLE_ENTRIES
];
937 u8 paprd_gain_table_index
[PAPRD_GAIN_TABLE_ENTRIES
];
939 * Store the permanent value of Reg 0x4004in WARegVal
940 * so we dont have to R/M/W. We should not be reading
941 * this register when in sleep states.
945 /* Enterprise mode cap */
948 #ifdef CONFIG_PM_SLEEP
952 int (*get_mac_revision
)(void);
953 int (*external_reset
)(void);
955 const struct firmware
*eeprom_blob
;
959 enum ath_bus_type ath_bus_type
;
960 void (*read_cachesize
)(struct ath_common
*common
, int *csz
);
961 bool (*eeprom_read
)(struct ath_common
*common
, u32 off
, u16
*data
);
962 void (*bt_coex_prep
)(struct ath_common
*common
);
963 void (*aspm_init
)(struct ath_common
*common
);
966 static inline struct ath_common
*ath9k_hw_common(struct ath_hw
*ah
)
971 static inline struct ath_regulatory
*ath9k_hw_regulatory(struct ath_hw
*ah
)
973 return &(ath9k_hw_common(ah
)->regulatory
);
976 static inline struct ath_hw_private_ops
*ath9k_hw_private_ops(struct ath_hw
*ah
)
978 return &ah
->private_ops
;
981 static inline struct ath_hw_ops
*ath9k_hw_ops(struct ath_hw
*ah
)
986 static inline u8
get_streams(int mask
)
988 return !!(mask
& BIT(0)) + !!(mask
& BIT(1)) + !!(mask
& BIT(2));
991 /* Initialization, Detach, Reset */
992 void ath9k_hw_deinit(struct ath_hw
*ah
);
993 int ath9k_hw_init(struct ath_hw
*ah
);
994 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
995 struct ath9k_hw_cal_data
*caldata
, bool fastcc
);
996 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
997 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
);
999 /* GPIO / RFKILL / Antennae */
1000 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
1001 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
1002 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
1003 u32 ah_signal_type
);
1004 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
1005 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
1007 /* General Operation */
1008 void ath9k_hw_synth_delay(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1010 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
1011 void ath9k_hw_write_array(struct ath_hw
*ah
, const struct ar5416IniArray
*array
,
1012 int column
, unsigned int *writecnt
);
1013 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
1014 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
1016 u32 frameLen
, u16 rateix
, bool shortPreamble
);
1017 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
1018 struct ath9k_channel
*chan
,
1019 struct chan_centers
*centers
);
1020 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
1021 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
1022 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
1023 bool ath9k_hw_disable(struct ath_hw
*ah
);
1024 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
, bool test
);
1025 void ath9k_hw_setopmode(struct ath_hw
*ah
);
1026 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
1027 void ath9k_hw_write_associd(struct ath_hw
*ah
);
1028 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
);
1029 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
1030 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
1031 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
1032 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, bool set
);
1033 void ath9k_hw_init_global_settings(struct ath_hw
*ah
);
1034 u32
ar9003_get_pll_sqsum_dvc(struct ath_hw
*ah
);
1035 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
);
1036 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
1037 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
1038 const struct ath9k_beacon_state
*bs
);
1039 bool ath9k_hw_check_alive(struct ath_hw
*ah
);
1041 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
);
1043 #ifdef CONFIG_ATH9K_DEBUGFS
1044 void ath9k_debug_sync_cause(struct ath_common
*common
, u32 sync_cause
);
1046 static inline void ath9k_debug_sync_cause(struct ath_common
*common
,
1050 /* Generic hw timer primitives */
1051 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
1052 void (*trigger
)(void *),
1053 void (*overflow
)(void *),
1056 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
1057 struct ath_gen_timer
*timer
,
1060 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
1062 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
1063 void ath_gen_timer_isr(struct ath_hw
*hw
);
1065 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
);
1068 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
1069 u32
*coef_mantissa
, u32
*coef_exponent
);
1070 void ath9k_hw_apply_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1074 * Code Specific to AR5008, AR9001 or AR9002,
1075 * we stuff these here to avoid callbacks for AR9003.
1077 int ar9002_hw_rf_claim(struct ath_hw
*ah
);
1078 void ar9002_hw_enable_async_fifo(struct ath_hw
*ah
);
1081 * Code specific to AR9003, we stuff these here to avoid callbacks
1082 * for older families
1084 void ar9003_hw_bb_watchdog_config(struct ath_hw
*ah
);
1085 void ar9003_hw_bb_watchdog_read(struct ath_hw
*ah
);
1086 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw
*ah
);
1087 void ar9003_hw_disable_phy_restart(struct ath_hw
*ah
);
1088 void ar9003_paprd_enable(struct ath_hw
*ah
, bool val
);
1089 void ar9003_paprd_populate_single_table(struct ath_hw
*ah
,
1090 struct ath9k_hw_cal_data
*caldata
,
1092 int ar9003_paprd_create_curve(struct ath_hw
*ah
,
1093 struct ath9k_hw_cal_data
*caldata
, int chain
);
1094 void ar9003_paprd_setup_gain_table(struct ath_hw
*ah
, int chain
);
1095 int ar9003_paprd_init_table(struct ath_hw
*ah
);
1096 bool ar9003_paprd_is_done(struct ath_hw
*ah
);
1097 bool ar9003_is_paprd_enabled(struct ath_hw
*ah
);
1098 void ar9003_hw_set_chain_masks(struct ath_hw
*ah
, u8 rx
, u8 tx
);
1100 /* Hardware family op attach helpers */
1101 int ar5008_hw_attach_phy_ops(struct ath_hw
*ah
);
1102 void ar9002_hw_attach_phy_ops(struct ath_hw
*ah
);
1103 void ar9003_hw_attach_phy_ops(struct ath_hw
*ah
);
1105 void ar9002_hw_attach_calib_ops(struct ath_hw
*ah
);
1106 void ar9003_hw_attach_calib_ops(struct ath_hw
*ah
);
1108 int ar9002_hw_attach_ops(struct ath_hw
*ah
);
1109 void ar9003_hw_attach_ops(struct ath_hw
*ah
);
1111 void ar9002_hw_load_ani_reg(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1113 void ath9k_ani_reset(struct ath_hw
*ah
, bool is_scanning
);
1114 void ath9k_hw_ani_monitor(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
1116 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1117 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw
*ah
)
1119 return ah
->btcoex_hw
.enabled
;
1121 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw
*ah
)
1123 return ah
->common
.btcoex_enabled
&&
1124 (ah
->caps
.hw_caps
& ATH9K_HW_CAP_MCI
);
1127 void ath9k_hw_btcoex_enable(struct ath_hw
*ah
);
1128 static inline enum ath_btcoex_scheme
1129 ath9k_hw_get_btcoex_scheme(struct ath_hw
*ah
)
1131 return ah
->btcoex_hw
.scheme
;
1134 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw
*ah
)
1138 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw
*ah
)
1142 static inline void ath9k_hw_btcoex_enable(struct ath_hw
*ah
)
1145 static inline enum ath_btcoex_scheme
1146 ath9k_hw_get_btcoex_scheme(struct ath_hw
*ah
)
1148 return ATH_BTCOEX_CFG_NONE
;
1150 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1153 #ifdef CONFIG_PM_SLEEP
1154 const char *ath9k_hw_wow_event_to_string(u32 wow_event
);
1155 void ath9k_hw_wow_apply_pattern(struct ath_hw
*ah
, u8
*user_pattern
,
1156 u8
*user_mask
, int pattern_count
,
1158 u32
ath9k_hw_wow_wakeup(struct ath_hw
*ah
);
1159 void ath9k_hw_wow_enable(struct ath_hw
*ah
, u32 pattern_enable
);
1161 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event
)
1165 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw
*ah
,
1172 static inline u32
ath9k_hw_wow_wakeup(struct ath_hw
*ah
)
1176 static inline void ath9k_hw_wow_enable(struct ath_hw
*ah
, u32 pattern_enable
)
1183 #define ATH9K_CLOCK_RATE_CCK 22
1184 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1185 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1186 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44