drivers/net/wireless/ath/ath9k/hw.h

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef HW_H
  18 #define HW_H
  19
  20 #include <linux/if_ether.h>
  21 #include <linux/delay.h>
  22 #include <linux/io.h>
  23
  24 #include "mac.h"
  25 #include "ani.h"
  26 #include "eeprom.h"
  27 #include "calib.h"
  28 #include "reg.h"
  29 #include "phy.h"
  30 #include "btcoex.h"
  31
  32 #include "../regd.h"
  33 #include "../debug.h"
  34
  35 #define ATHEROS_VENDOR_ID       0x168c
  36
  37 #define AR5416_DEVID_PCI        0x0023
  38 #define AR5416_DEVID_PCIE       0x0024
  39 #define AR9160_DEVID_PCI        0x0027
  40 #define AR9280_DEVID_PCI        0x0029
  41 #define AR9280_DEVID_PCIE       0x002a
  42 #define AR9285_DEVID_PCIE       0x002b
  43 #define AR2427_DEVID_PCIE       0x002c
  44 #define AR9287_DEVID_PCI        0x002d
  45 #define AR9287_DEVID_PCIE       0x002e
  46 #define AR9300_DEVID_PCIE       0x0030
  47
  48 #define AR5416_AR9100_DEVID     0x000b
  49
  50 #define AR_SUBVENDOR_ID_NOG     0x0e11
  51 #define AR_SUBVENDOR_ID_NEW_A   0x7065
  52 #define AR5416_MAGIC            0x19641014
  53
  54 #define AR9280_COEX2WIRE_SUBSYSID       0x309b
  55 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
  56 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
  57
  58 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
  59
  60 #define ATH_DEFAULT_NOISE_FLOOR -95
  61
  62 #define ATH9K_RSSI_BAD                  -128
  63
  64 /* Register read/write primitives */
  65 #define REG_WRITE(_ah, _reg, _val) \
  66         ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
  67
  68 #define REG_READ(_ah, _reg) \
  69         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
  70
  71 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
  72 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
  73 #define REG_RMW(_a, _r, _set, _clr)    \
  74         REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
  75 #define REG_RMW_FIELD(_a, _r, _f, _v) \
  76         REG_WRITE(_a, _r, \
  77         (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
  78 #define REG_READ_FIELD(_a, _r, _f) \
  79         (((REG_READ(_a, _r) & _f) >> _f##_S))
  80 #define REG_SET_BIT(_a, _r, _f) \
  81         REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
  82 #define REG_CLR_BIT(_a, _r, _f) \
  83         REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
  84
  85 #define DO_DELAY(x) do {                        \
  86                 if ((++(x) % 64) == 0)          \
  87                         udelay(1);              \
  88         } while (0)
  89
  90 #define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
  91                 int r;                                                  \
  92                 for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
  93                         REG_WRITE(ah, INI_RA((iniarray), (r), 0),       \
  94                                   INI_RA((iniarray), r, (column)));     \
  95                         DO_DELAY(regWr);                                \
  96                 }                                                       \
  97         } while (0)
  98
  99 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
 100 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
 101 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
 102 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
 103 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
 104 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
 105 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
 106
 107 #define AR_GPIOD_MASK               0x00001FFF
 108 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
 109
 110 #define BASE_ACTIVATE_DELAY         100
 111 #define RTC_PLL_SETTLE_DELAY        100
 112 #define COEF_SCALE_S                24
 113 #define HT40_CHANNEL_CENTER_SHIFT   10
 114
 115 #define ATH9K_ANTENNA0_CHAINMASK    0x1
 116 #define ATH9K_ANTENNA1_CHAINMASK    0x2
 117
 118 #define ATH9K_NUM_DMA_DEBUG_REGS    8
 119 #define ATH9K_NUM_QUEUES            10
 120
 121 #define MAX_RATE_POWER              63
 122 #define AH_WAIT_TIMEOUT             100000 /* (us) */
 123 #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
 124 #define AH_TIME_QUANTUM             10
 125 #define AR_KEYTABLE_SIZE            128
 126 #define POWER_UP_TIME               10000
 127 #define SPUR_RSSI_THRESH            40
 128
 129 #define CAB_TIMEOUT_VAL             10
 130 #define BEACON_TIMEOUT_VAL          10
 131 #define MIN_BEACON_TIMEOUT_VAL      1
 132 #define SLEEP_SLOP                  3
 133
 134 #define INIT_CONFIG_STATUS          0x00000000
 135 #define INIT_RSSI_THR               0x00000700
 136 #define INIT_BCON_CNTRL_REG         0x00000000
 137
 138 #define TU_TO_USEC(_tu)             ((_tu) << 10)
 139
 140 #define ATH9K_HW_RX_HP_QDEPTH   16
 141 #define ATH9K_HW_RX_LP_QDEPTH   128
 142
 143 enum ath_ini_subsys {
 144         ATH_INI_PRE = 0,
 145         ATH_INI_CORE,
 146         ATH_INI_POST,
 147         ATH_INI_NUM_SPLIT,
 148 };
 149
 150 enum wireless_mode {
 151         ATH9K_MODE_11A = 0,
 152         ATH9K_MODE_11G,
 153         ATH9K_MODE_11NA_HT20,
 154         ATH9K_MODE_11NG_HT20,
 155         ATH9K_MODE_11NA_HT40PLUS,
 156         ATH9K_MODE_11NA_HT40MINUS,
 157         ATH9K_MODE_11NG_HT40PLUS,
 158         ATH9K_MODE_11NG_HT40MINUS,
 159         ATH9K_MODE_MAX,
 160 };
 161
 162 enum ath9k_hw_caps {
 163         ATH9K_HW_CAP_MIC_AESCCM                 = BIT(0),
 164         ATH9K_HW_CAP_MIC_CKIP                   = BIT(1),
 165         ATH9K_HW_CAP_MIC_TKIP                   = BIT(2),
 166         ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(3),
 167         ATH9K_HW_CAP_CIPHER_CKIP                = BIT(4),
 168         ATH9K_HW_CAP_CIPHER_TKIP                = BIT(5),
 169         ATH9K_HW_CAP_VEOL                       = BIT(6),
 170         ATH9K_HW_CAP_BSSIDMASK                  = BIT(7),
 171         ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(8),
 172         ATH9K_HW_CAP_HT                         = BIT(9),
 173         ATH9K_HW_CAP_GTT                        = BIT(10),
 174         ATH9K_HW_CAP_FASTCC                     = BIT(11),
 175         ATH9K_HW_CAP_RFSILENT                   = BIT(12),
 176         ATH9K_HW_CAP_CST                        = BIT(13),
 177         ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
 178         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
 179         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
 180         ATH9K_HW_CAP_EDMA                       = BIT(17),
 181         ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(18),
 182 };
 183
 184 enum ath9k_capability_type {
 185         ATH9K_CAP_CIPHER = 0,
 186         ATH9K_CAP_TKIP_MIC,
 187         ATH9K_CAP_TKIP_SPLIT,
 188         ATH9K_CAP_TXPOW,
 189         ATH9K_CAP_MCAST_KEYSRCH,
 190         ATH9K_CAP_DS
 191 };
 192
 193 struct ath9k_hw_capabilities {
 194         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
 195         DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
 196         u16 total_queues;
 197         u16 keycache_size;
 198         u16 low_5ghz_chan, high_5ghz_chan;
 199         u16 low_2ghz_chan, high_2ghz_chan;
 200         u16 rts_aggr_limit;
 201         u8 tx_chainmask;
 202         u8 rx_chainmask;
 203         u16 tx_triglevel_max;
 204         u16 reg_cap;
 205         u8 num_gpio_pins;
 206         u8 num_antcfg_2ghz;
 207         u8 num_antcfg_5ghz;
 208         u8 rx_hp_qdepth;
 209         u8 rx_lp_qdepth;
 210         u8 rx_status_len;
 211         u8 tx_desc_len;
 212 };
 213
 214 struct ath9k_ops_config {
 215         int dma_beacon_response_time;
 216         int sw_beacon_response_time;
 217         int additional_swba_backoff;
 218         int ack_6mb;
 219         int cwm_ignore_extcca;
 220         u8 pcie_powersave_enable;
 221         u8 pcie_clock_req;
 222         u32 pcie_waen;
 223         u8 analog_shiftreg;
 224         u8 ht_enable;
 225         u32 ofdm_trig_low;
 226         u32 ofdm_trig_high;
 227         u32 cck_trig_high;
 228         u32 cck_trig_low;
 229         u32 enable_ani;
 230         int serialize_regmode;
 231         bool rx_intr_mitigation;
 232         bool tx_intr_mitigation;
 233 #define SPUR_DISABLE            0
 234 #define SPUR_ENABLE_IOCTL       1
 235 #define SPUR_ENABLE_EEPROM      2
 236 #define AR_EEPROM_MODAL_SPURS   5
 237 #define AR_SPUR_5413_1          1640
 238 #define AR_SPUR_5413_2          1200
 239 #define AR_NO_SPUR              0x8000
 240 #define AR_BASE_FREQ_2GHZ       2300
 241 #define AR_BASE_FREQ_5GHZ       4900
 242 #define AR_SPUR_FEEQ_BOUND_HT40 19
 243 #define AR_SPUR_FEEQ_BOUND_HT20 10
 244         int spurmode;
 245         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
 246         u8 max_txtrig_level;
 247 };
 248
 249 enum ath9k_int {
 250         ATH9K_INT_RX = 0x00000001,
 251         ATH9K_INT_RXDESC = 0x00000002,
 252         ATH9K_INT_RXHP = 0x00000001,
 253         ATH9K_INT_RXLP = 0x00000002,
 254         ATH9K_INT_RXNOFRM = 0x00000008,
 255         ATH9K_INT_RXEOL = 0x00000010,
 256         ATH9K_INT_RXORN = 0x00000020,
 257         ATH9K_INT_TX = 0x00000040,
 258         ATH9K_INT_TXDESC = 0x00000080,
 259         ATH9K_INT_TIM_TIMER = 0x00000100,
 260         ATH9K_INT_TXURN = 0x00000800,
 261         ATH9K_INT_MIB = 0x00001000,
 262         ATH9K_INT_RXPHY = 0x00004000,
 263         ATH9K_INT_RXKCM = 0x00008000,
 264         ATH9K_INT_SWBA = 0x00010000,
 265         ATH9K_INT_BMISS = 0x00040000,
 266         ATH9K_INT_BNR = 0x00100000,
 267         ATH9K_INT_TIM = 0x00200000,
 268         ATH9K_INT_DTIM = 0x00400000,
 269         ATH9K_INT_DTIMSYNC = 0x00800000,
 270         ATH9K_INT_GPIO = 0x01000000,
 271         ATH9K_INT_CABEND = 0x02000000,
 272         ATH9K_INT_TSFOOR = 0x04000000,
 273         ATH9K_INT_GENTIMER = 0x08000000,
 274         ATH9K_INT_CST = 0x10000000,
 275         ATH9K_INT_GTT = 0x20000000,
 276         ATH9K_INT_FATAL = 0x40000000,
 277         ATH9K_INT_GLOBAL = 0x80000000,
 278         ATH9K_INT_BMISC = ATH9K_INT_TIM |
 279                 ATH9K_INT_DTIM |
 280                 ATH9K_INT_DTIMSYNC |
 281                 ATH9K_INT_TSFOOR |
 282                 ATH9K_INT_CABEND,
 283         ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
 284                 ATH9K_INT_RXDESC |
 285                 ATH9K_INT_RXEOL |
 286                 ATH9K_INT_RXORN |
 287                 ATH9K_INT_TXURN |
 288                 ATH9K_INT_TXDESC |
 289                 ATH9K_INT_MIB |
 290                 ATH9K_INT_RXPHY |
 291                 ATH9K_INT_RXKCM |
 292                 ATH9K_INT_SWBA |
 293                 ATH9K_INT_BMISS |
 294                 ATH9K_INT_GPIO,
 295         ATH9K_INT_NOCARD = 0xffffffff
 296 };
 297
 298 #define CHANNEL_CW_INT    0x00002
 299 #define CHANNEL_CCK       0x00020
 300 #define CHANNEL_OFDM      0x00040
 301 #define CHANNEL_2GHZ      0x00080
 302 #define CHANNEL_5GHZ      0x00100
 303 #define CHANNEL_PASSIVE   0x00200
 304 #define CHANNEL_DYN       0x00400
 305 #define CHANNEL_HALF      0x04000
 306 #define CHANNEL_QUARTER   0x08000
 307 #define CHANNEL_HT20      0x10000
 308 #define CHANNEL_HT40PLUS  0x20000
 309 #define CHANNEL_HT40MINUS 0x40000
 310
 311 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
 312 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
 313 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
 314 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
 315 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
 316 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
 317 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
 318 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
 319 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
 320 #define CHANNEL_ALL                             \
 321         (CHANNEL_OFDM|                          \
 322          CHANNEL_CCK|                           \
 323          CHANNEL_2GHZ |                         \
 324          CHANNEL_5GHZ |                         \
 325          CHANNEL_HT20 |                         \
 326          CHANNEL_HT40PLUS |                     \
 327          CHANNEL_HT40MINUS)
 328
 329 struct ath9k_channel {
 330         struct ieee80211_channel *chan;
 331         u16 channel;
 332         u32 channelFlags;
 333         u32 chanmode;
 334         int32_t CalValid;
 335         bool oneTimeCalsDone;
 336         int8_t iCoff;
 337         int8_t qCoff;
 338         int16_t rawNoiseFloor;
 339 };
 340
 341 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
 342        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
 343        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
 344        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
 345 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 346 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 347 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 348 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 349 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 350 #define IS_CHAN_A_5MHZ_SPACED(_c)                       \
 351         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
 352          (((_c)->channel % 20) != 0) &&                 \
 353          (((_c)->channel % 10) != 0))
 354
 355 /* These macros check chanmode and not channelFlags */
 356 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
 357 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
 358                           ((_c)->chanmode == CHANNEL_G_HT20))
 359 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||     \
 360                           ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||    \
 361                           ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||     \
 362                           ((_c)->chanmode == CHANNEL_G_HT40MINUS))
 363 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
 364
 365 enum ath9k_power_mode {
 366         ATH9K_PM_AWAKE = 0,
 367         ATH9K_PM_FULL_SLEEP,
 368         ATH9K_PM_NETWORK_SLEEP,
 369         ATH9K_PM_UNDEFINED
 370 };
 371
 372 enum ath9k_tp_scale {
 373         ATH9K_TP_SCALE_MAX = 0,
 374         ATH9K_TP_SCALE_50,
 375         ATH9K_TP_SCALE_25,
 376         ATH9K_TP_SCALE_12,
 377         ATH9K_TP_SCALE_MIN
 378 };
 379
 380 enum ser_reg_mode {
 381         SER_REG_MODE_OFF = 0,
 382         SER_REG_MODE_ON = 1,
 383         SER_REG_MODE_AUTO = 2,
 384 };
 385
 386 enum ath9k_rx_qtype {
 387         ATH9K_RX_QUEUE_HP,
 388         ATH9K_RX_QUEUE_LP,
 389         ATH9K_RX_QUEUE_MAX,
 390 };
 391
 392 struct ath9k_beacon_state {
 393         u32 bs_nexttbtt;
 394         u32 bs_nextdtim;
 395         u32 bs_intval;
 396 #define ATH9K_BEACON_PERIOD       0x0000ffff
 397 #define ATH9K_BEACON_ENA          0x00800000
 398 #define ATH9K_BEACON_RESET_TSF    0x01000000
 399 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
 400         u32 bs_dtimperiod;
 401         u16 bs_cfpperiod;
 402         u16 bs_cfpmaxduration;
 403         u32 bs_cfpnext;
 404         u16 bs_timoffset;
 405         u16 bs_bmissthreshold;
 406         u32 bs_sleepduration;
 407         u32 bs_tsfoor_threshold;
 408 };
 409
 410 struct chan_centers {
 411         u16 synth_center;
 412         u16 ctl_center;
 413         u16 ext_center;
 414 };
 415
 416 enum {
 417         ATH9K_RESET_POWER_ON,
 418         ATH9K_RESET_WARM,
 419         ATH9K_RESET_COLD,
 420 };
 421
 422 struct ath9k_hw_version {
 423         u32 magic;
 424         u16 devid;
 425         u16 subvendorid;
 426         u32 macVersion;
 427         u16 macRev;
 428         u16 phyRev;
 429         u16 analog5GhzRev;
 430         u16 analog2GhzRev;
 431         u16 subsysid;
 432 };
 433
 434 /* Generic TSF timer definitions */
 435
 436 #define ATH_MAX_GEN_TIMER       16
 437
 438 #define AR_GENTMR_BIT(_index)   (1 << (_index))
 439
 440 /*
 441  * Using de Bruijin sequence to to look up 1's index in a 32 bit number
 442  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
 443  */
 444 #define debruijn32 0x077CB531U
 445
 446 struct ath_gen_timer_configuration {
 447         u32 next_addr;
 448         u32 period_addr;
 449         u32 mode_addr;
 450         u32 mode_mask;
 451 };
 452
 453 struct ath_gen_timer {
 454         void (*trigger)(void *arg);
 455         void (*overflow)(void *arg);
 456         void *arg;
 457         u8 index;
 458 };
 459
 460 struct ath_gen_timer_table {
 461         u32 gen_timer_index[32];
 462         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
 463         union {
 464                 unsigned long timer_bits;
 465                 u16 val;
 466         } timer_mask;
 467 };
 468
 469 /**
 470  * struct ath_hw_private_ops - callbacks used internally by hardware code
 471  *
 472  * This structure contains private callbacks designed to only be used internally
 473  * by the hardware core.
 474  *
 475  * @init_cal_settings: setup types of calibrations supported
 476  * @init_cal: starts actual calibration
 477  *
 478  * @init_mode_regs: Initializes mode registers
 479  * @init_mode_gain_regs: Initialize TX/RX gain registers
 480  * @macversion_supported: If this specific mac revision is supported
 481  *
 482  * @rf_set_freq: change frequency
 483  * @spur_mitigate_freq: spur mitigation
 484  * @rf_alloc_ext_banks:
 485  * @rf_free_ext_banks:
 486  * @set_rf_regs:
 487  * @compute_pll_control: compute the PLL control value to use for
 488  *      AR_RTC_PLL_CONTROL for a given channel
 489  * @setup_calibration: set up calibration
 490  * @iscal_supported: used to query if a type of calibration is supported
 491  * @loadnf: load noise floor read from each chain on the CCA registers
 492  */
 493 struct ath_hw_private_ops {
 494         /* Calibration ops */
 495         void (*init_cal_settings)(struct ath_hw *ah);
 496         bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
 497
 498         void (*init_mode_regs)(struct ath_hw *ah);
 499         void (*init_mode_gain_regs)(struct ath_hw *ah);
 500         bool (*macversion_supported)(u32 macversion);
 501         void (*setup_calibration)(struct ath_hw *ah,
 502                                   struct ath9k_cal_list *currCal);
 503         bool (*iscal_supported)(struct ath_hw *ah,
 504                                 enum ath9k_cal_types calType);
 505
 506         /* PHY ops */
 507         int (*rf_set_freq)(struct ath_hw *ah,
 508                            struct ath9k_channel *chan);
 509         void (*spur_mitigate_freq)(struct ath_hw *ah,
 510                                    struct ath9k_channel *chan);
 511         int (*rf_alloc_ext_banks)(struct ath_hw *ah);
 512         void (*rf_free_ext_banks)(struct ath_hw *ah);
 513         bool (*set_rf_regs)(struct ath_hw *ah,
 514                             struct ath9k_channel *chan,
 515                             u16 modesIndex);
 516         void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
 517         void (*init_bb)(struct ath_hw *ah,
 518                         struct ath9k_channel *chan);
 519         int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
 520         void (*olc_init)(struct ath_hw *ah);
 521         void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
 522         void (*mark_phy_inactive)(struct ath_hw *ah);
 523         void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
 524         bool (*rfbus_req)(struct ath_hw *ah);
 525         void (*rfbus_done)(struct ath_hw *ah);
 526         void (*enable_rfkill)(struct ath_hw *ah);
 527         void (*restore_chainmask)(struct ath_hw *ah);
 528         void (*set_diversity)(struct ath_hw *ah, bool value);
 529         u32 (*compute_pll_control)(struct ath_hw *ah,
 530                                    struct ath9k_channel *chan);
 531         bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
 532                             int param);
 533         void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
 534         void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
 535 };
 536
 537 /**
 538  * struct ath_hw_ops - callbacks used by hardware code and driver code
 539  *
 540  * This structure contains callbacks designed to to be used internally by
 541  * hardware code and also by the lower level driver.
 542  *
 543  * @config_pci_powersave:
 544  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
 545  */
 546 struct ath_hw_ops {
 547         void (*config_pci_powersave)(struct ath_hw *ah,
 548                                      int restore,
 549                                      int power_off);
 550         void (*rx_enable)(struct ath_hw *ah);
 551         void (*set_desc_link)(void *ds, u32 link);
 552         void (*get_desc_link)(void *ds, u32 **link);
 553         bool (*calibrate)(struct ath_hw *ah,
 554                           struct ath9k_channel *chan,
 555                           u8 rxchainmask,
 556                           bool longcal);
 557         bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
 558         void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
 559                             bool is_firstseg, bool is_is_lastseg,
 560                             const void *ds0, dma_addr_t buf_addr,
 561                             unsigned int qcu);
 562         int (*proc_txdesc)(struct ath_hw *ah, void *ds,
 563                            struct ath_tx_status *ts);
 564         void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
 565                               u32 pktLen, enum ath9k_pkt_type type,
 566                               u32 txPower, u32 keyIx,
 567                               enum ath9k_key_type keyType,
 568                               u32 flags);
 569         void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
 570                                 void *lastds,
 571                                 u32 durUpdateEn, u32 rtsctsRate,
 572                                 u32 rtsctsDuration,
 573                                 struct ath9k_11n_rate_series series[],
 574                                 u32 nseries, u32 flags);
 575         void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
 576                                   u32 aggrLen);
 577         void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
 578                                    u32 numDelims);
 579         void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
 580         void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
 581         void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
 582                                      u32 burstDuration);
 583         void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
 584                                        u32 vmf);
 585 };
 586
 587 struct ath_hw {
 588         struct ieee80211_hw *hw;
 589         struct ath_common common;
 590         struct ath9k_hw_version hw_version;
 591         struct ath9k_ops_config config;
 592         struct ath9k_hw_capabilities caps;
 593         struct ath9k_channel channels[38];
 594         struct ath9k_channel *curchan;
 595
 596         union {
 597                 struct ar5416_eeprom_def def;
 598                 struct ar5416_eeprom_4k map4k;
 599                 struct ar9287_eeprom map9287;
 600                 struct ar9300_eeprom ar9300_eep;
 601         } eeprom;
 602         const struct eeprom_ops *eep_ops;
 603
 604         bool sw_mgmt_crypto;
 605         bool is_pciexpress;
 606         bool need_an_top2_fixup;
 607         u16 tx_trig_level;
 608         s16 nf_2g_max;
 609         s16 nf_2g_min;
 610         s16 nf_5g_max;
 611         s16 nf_5g_min;
 612         u16 rfsilent;
 613         u32 rfkill_gpio;
 614         u32 rfkill_polarity;
 615         u32 ah_flags;
 616
 617         bool htc_reset_init;
 618
 619         enum nl80211_iftype opmode;
 620         enum ath9k_power_mode power_mode;
 621
 622         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 623         struct ath9k_pacal_info pacal_info;
 624         struct ar5416Stats stats;
 625         struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
 626
 627         int16_t curchan_rad_index;
 628         enum ath9k_int imask;
 629         u32 imrs2_reg;
 630         u32 txok_interrupt_mask;
 631         u32 txerr_interrupt_mask;
 632         u32 txdesc_interrupt_mask;
 633         u32 txeol_interrupt_mask;
 634         u32 txurn_interrupt_mask;
 635         bool chip_fullsleep;
 636         u32 atim_window;
 637
 638         /* Calibration */
 639         enum ath9k_cal_types supp_cals;
 640         struct ath9k_cal_list iq_caldata;
 641         struct ath9k_cal_list adcgain_caldata;
 642         struct ath9k_cal_list adcdc_calinitdata;
 643         struct ath9k_cal_list adcdc_caldata;
 644         struct ath9k_cal_list tempCompCalData;
 645         struct ath9k_cal_list *cal_list;
 646         struct ath9k_cal_list *cal_list_last;
 647         struct ath9k_cal_list *cal_list_curr;
 648 #define totalPowerMeasI meas0.unsign
 649 #define totalPowerMeasQ meas1.unsign
 650 #define totalIqCorrMeas meas2.sign
 651 #define totalAdcIOddPhase  meas0.unsign
 652 #define totalAdcIEvenPhase meas1.unsign
 653 #define totalAdcQOddPhase  meas2.unsign
 654 #define totalAdcQEvenPhase meas3.unsign
 655 #define totalAdcDcOffsetIOddPhase  meas0.sign
 656 #define totalAdcDcOffsetIEvenPhase meas1.sign
 657 #define totalAdcDcOffsetQOddPhase  meas2.sign
 658 #define totalAdcDcOffsetQEvenPhase meas3.sign
 659         union {
 660                 u32 unsign[AR5416_MAX_CHAINS];
 661                 int32_t sign[AR5416_MAX_CHAINS];
 662         } meas0;
 663         union {
 664                 u32 unsign[AR5416_MAX_CHAINS];
 665                 int32_t sign[AR5416_MAX_CHAINS];
 666         } meas1;
 667         union {
 668                 u32 unsign[AR5416_MAX_CHAINS];
 669                 int32_t sign[AR5416_MAX_CHAINS];
 670         } meas2;
 671         union {
 672                 u32 unsign[AR5416_MAX_CHAINS];
 673                 int32_t sign[AR5416_MAX_CHAINS];
 674         } meas3;
 675         u16 cal_samples;
 676
 677         u32 sta_id1_defaults;
 678         u32 misc_mode;
 679         enum {
 680                 AUTO_32KHZ,
 681                 USE_32KHZ,
 682                 DONT_USE_32KHZ,
 683         } enable_32kHz_clock;
 684
 685         /* Private to hardware code */
 686         struct ath_hw_private_ops private_ops;
 687         /* Accessed by the lower level driver */
 688         struct ath_hw_ops ops;
 689
 690         /* Used to program the radio on non single-chip devices */
 691         u32 *analogBank0Data;
 692         u32 *analogBank1Data;
 693         u32 *analogBank2Data;
 694         u32 *analogBank3Data;
 695         u32 *analogBank6Data;
 696         u32 *analogBank6TPCData;
 697         u32 *analogBank7Data;
 698         u32 *addac5416_21;
 699         u32 *bank6Temp;
 700
 701         int16_t txpower_indexoffset;
 702         int coverage_class;
 703         u32 beacon_interval;
 704         u32 slottime;
 705         u32 globaltxtimeout;
 706
 707         /* ANI */
 708         u32 proc_phyerr;
 709         u32 aniperiod;
 710         struct ar5416AniState *curani;
 711         struct ar5416AniState ani[255];
 712         int totalSizeDesired[5];
 713         int coarse_high[5];
 714         int coarse_low[5];
 715         int firpwr[5];
 716         enum ath9k_ani_cmd ani_function;
 717
 718         /* Bluetooth coexistance */
 719         struct ath_btcoex_hw btcoex_hw;
 720
 721         u32 intr_txqs;
 722         u8 txchainmask;
 723         u8 rxchainmask;
 724
 725         u32 originalGain[22];
 726         int initPDADC;
 727         int PDADCdelta;
 728         u8 led_pin;
 729
 730         struct ar5416IniArray iniModes;
 731         struct ar5416IniArray iniCommon;
 732         struct ar5416IniArray iniBank0;
 733         struct ar5416IniArray iniBB_RfGain;
 734         struct ar5416IniArray iniBank1;
 735         struct ar5416IniArray iniBank2;
 736         struct ar5416IniArray iniBank3;
 737         struct ar5416IniArray iniBank6;
 738         struct ar5416IniArray iniBank6TPC;
 739         struct ar5416IniArray iniBank7;
 740         struct ar5416IniArray iniAddac;
 741         struct ar5416IniArray iniPcieSerdes;
 742         struct ar5416IniArray iniPcieSerdesLowPower;
 743         struct ar5416IniArray iniModesAdditional;
 744         struct ar5416IniArray iniModesRxGain;
 745         struct ar5416IniArray iniModesTxGain;
 746         struct ar5416IniArray iniModes_9271_1_0_only;
 747         struct ar5416IniArray iniCckfirNormal;
 748         struct ar5416IniArray iniCckfirJapan2484;
 749         struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
 750         struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
 751         struct ar5416IniArray iniModes_9271_ANI_reg;
 752         struct ar5416IniArray iniModes_high_power_tx_gain_9271;
 753         struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
 754
 755         struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
 756         struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
 757         struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
 758         struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
 759
 760         u32 intr_gen_timer_trigger;
 761         u32 intr_gen_timer_thresh;
 762         struct ath_gen_timer_table hw_gen_timers;
 763
 764         struct ar9003_txs *ts_ring;
 765         void *ts_start;
 766         u32 ts_paddr_start;
 767         u32 ts_paddr_end;
 768         u16 ts_tail;
 769         u8 ts_size;
 770 };
 771
 772 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
 773 {
 774         return &ah->common;
 775 }
 776
 777 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
 778 {
 779         return &(ath9k_hw_common(ah)->regulatory);
 780 }
 781
 782 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
 783 {
 784         return &ah->private_ops;
 785 }
 786
 787 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
 788 {
 789         return &ah->ops;
 790 }
 791
 792 /* Initialization, Detach, Reset */
 793 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
 794 void ath9k_hw_deinit(struct ath_hw *ah);
 795 int ath9k_hw_init(struct ath_hw *ah);
 796 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 797                    bool bChannelChange);
 798 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
 799 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
 800                             u32 capability, u32 *result);
 801 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
 802                             u32 capability, u32 setting, int *status);
 803 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
 804
 805 /* Key Cache Management */
 806 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
 807 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
 808 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
 809                                  const struct ath9k_keyval *k,
 810                                  const u8 *mac);
 811 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
 812
 813 /* GPIO / RFKILL / Antennae */
 814 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
 815 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
 816 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
 817                          u32 ah_signal_type);
 818 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
 819 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
 820 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
 821
 822 /* General Operation */
 823 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
 824 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
 825 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
 826 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 827                            u8 phy, int kbps,
 828                            u32 frameLen, u16 rateix, bool shortPreamble);
 829 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 830                                   struct ath9k_channel *chan,
 831                                   struct chan_centers *centers);
 832 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 833 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 834 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 835 bool ath9k_hw_disable(struct ath_hw *ah);
 836 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
 837 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
 838 void ath9k_hw_setopmode(struct ath_hw *ah);
 839 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 840 void ath9k_hw_setbssidmask(struct ath_hw *ah);
 841 void ath9k_hw_write_associd(struct ath_hw *ah);
 842 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
 843 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
 844 void ath9k_hw_reset_tsf(struct ath_hw *ah);
 845 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
 846 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
 847 void ath9k_hw_init_global_settings(struct ath_hw *ah);
 848 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
 849 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 850 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
 851                                     const struct ath9k_beacon_state *bs);
 852
 853 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
 854
 855 /* Generic hw timer primitives */
 856 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
 857                                           void (*trigger)(void *),
 858                                           void (*overflow)(void *),
 859                                           void *arg,
 860                                           u8 timer_index);
 861 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
 862                               struct ath_gen_timer *timer,
 863                               u32 timer_next,
 864                               u32 timer_period);
 865 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 866
 867 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 868 void ath_gen_timer_isr(struct ath_hw *hw);
 869 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 870
 871 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 872
 873 /* HTC */
 874 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
 875
 876 /* PHY */
 877 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 878                                    u32 *coef_mantissa, u32 *coef_exponent);
 879
 880 /*
 881  * Code Specific to AR5008, AR9001 or AR9002,
 882  * we stuff these here to avoid callbacks for AR9003.
 883  */
 884 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
 885 int ar9002_hw_rf_claim(struct ath_hw *ah);
 886 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
 887 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
 888
 889 /*
 890  * Code specifric to AR9003, we stuff these here to avoid callbacks
 891  * for older families
 892  */
 893 void ar9003_hw_set_nf_limits(struct ath_hw *ah);
 894
 895 /* Hardware family op attach helpers */
 896 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
 897 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
 898 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
 899
 900 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
 901 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
 902
 903 void ar9002_hw_attach_ops(struct ath_hw *ah);
 904 void ar9003_hw_attach_ops(struct ath_hw *ah);
 905
 906 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 907 #define ATH_PCIE_CAP_LINK_L0S   1
 908 #define ATH_PCIE_CAP_LINK_L1    2
 909
 910 #endif